diff --git a/design/src/main/scala/pic_ctrl.scala b/design/src/main/scala/pic_ctrl.scala index 3d23f7e6..08764e4d 100644 --- a/design/src/main/scala/pic_ctrl.scala +++ b/design/src/main/scala/pic_ctrl.scala @@ -3,6 +3,7 @@ import chisel3.util._ import include._ import lib._ import chisel3.experimental.chiselName +import chisel3.stage.ChiselStage @chiselName class pic_ctrl extends Module with RequireAsyncReset with lib { @@ -14,13 +15,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W)) val lsu_pic = Flipped(new lsu_pic()) val dec_pic = Flipped(new dec_pic) -// val dec_tlu_meicurpl = Input(UInt(4.W)) -// val dec_tlu_meipt = Input(UInt(4.W)) -// -// val mexintpend = Output(Bool()) -// val pic_claimid = Output(UInt(8.W)) -// val pic_pl = Output(UInt(4.W)) -// val mhwakeup = Output(Bool()) }) def cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) = @@ -33,12 +27,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { Mux(meigwctrl_type.asBool(), ((extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending), (extintsrc_req_sync ^ meigwctrl_polarity)) } - // io.mexintpend := 0.U - // io.pic_claimid := 0.U - // io.pic_pl := 0.U - //io.picm_rd_data := 0.U - //io.mhwakeup := 0.U - val NUM_LEVELS = log2Ceil(PIC_TOTAL_INT_PLUS1) val INTPRIORITY_BASE_ADDR = aslong(PIC_BASE_ADDR) val INTPEND_BASE_ADDR = aslong(PIC_BASE_ADDR + 0x00001000) @@ -63,20 +51,19 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { val GW_CONFIG = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W), init=0.U) val intpend_rd_out = WireInit(0.U(32.W)) -// val intenable_rd_out = WireInit(0.U(1.W)) val intpriority_reg_inv = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W))) val intpend_reg_extended = WireInit(0.U (INTPEND_SIZE.W)) val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W)) val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))/////////////////// val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W))) - val levelx_intpend_w_prior_en = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(INTPRIORITY_BITS.W)))) + val levelx_intpend_w_prior_en = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+2).toInt,UInt(INTPRIORITY_BITS.W)))) for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_w_prior_en(i)(j) := 0.U val levelx_intpend_id = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(ID_BITS.W)))) for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_id(i)(j) := 0.U - val l2_intpend_w_prior_en_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(INTPRIORITY_BITS.W))) - for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_w_prior_en_ff(i) := 0.U - val l2_intpend_id_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(ID_BITS.W))) - for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_id_ff(i) := 0.U + val l2_intpend_w_prior_en_ff = Wire(Vec((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt,UInt(INTPRIORITY_BITS.W))) + for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt) l2_intpend_w_prior_en_ff(i) := 0.U + val l2_intpend_id_ff = Wire(Vec((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt,UInt(ID_BITS.W))) + for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt) l2_intpend_id_ff(i) := 0.U val config_reg = WireInit(0.U(1.W)) val intpriord = WireInit(0.U(1.W)) val prithresh_reg_write = WireInit(0.U(1.W)) @@ -89,7 +76,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { val mask = WireInit(0.U(4.W)) val picm_mken_ff = WireInit(0.U(1.W)) val claimid_in = WireInit(0.U(ID_BITS.W)) - //val extintsrc_req_gw = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(1.W))) // clocks val pic_raddr_c1_clk = Wire(Clock()) @@ -156,7 +142,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { configurable_gw(io.free_clk, extintsrc_req_sync(i), gw_config_reg(i)(0), gw_config_reg(i)(1), gw_clear_reg_we(i).asBool()) else 0.U) - //val intpriord = WireInit(Bool(), false.B) (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpriority_reg_inv(i) := Mux(intpriord.asBool, ~intpriority_reg(i), intpriority_reg(i))) (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i) := Fill(INTPRIORITY_BITS, extintsrc_req_gw(i) & intenable_reg(i)) & intpriority_reg_inv(i)) (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i) := i.U) @@ -177,8 +162,8 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { level_intpend_w_prior_en(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i)) ++ IndexedSeq(0.U(4.W), 0.U(4.W), 0.U(4.W)) level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(0.U(8.W), 0.U(8.W), 0.U(8.W)) - levelx_intpend_w_prior_en(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_w_prior_en_ff(i)) ++ IndexedSeq(0.U(INTPRIORITY_BITS.W)) - levelx_intpend_id(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_id_ff(i)) ++ IndexedSeq(1.U(ID_BITS.W)) + levelx_intpend_w_prior_en(NUM_LEVELS - NUM_LEVELS/2) := (0 to (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_w_prior_en_ff(i)) ++ IndexedSeq(0.U(INTPRIORITY_BITS.W)) + levelx_intpend_id(NUM_LEVELS - NUM_LEVELS/2) := (0 to (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_id_ff(i)) ++ IndexedSeq(1.U(ID_BITS.W)) /// Do the prioritization of the interrupts here //////////// for (l <-0 until NUM_LEVELS/2 ; m <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(l+1)).toInt)) { @@ -195,7 +180,8 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { (0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_w_prior_en_ff(i) := withClock(io.free_clk){RegNext(level_intpend_w_prior_en(NUM_LEVELS/2)(i))}) (0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_id_ff(i) := withClock(io.free_clk){RegNext(level_intpend_id(NUM_LEVELS/2)(i))}) - for (j <-NUM_LEVELS/2 until NUM_LEVELS ; k <- 0 to ((PIC_TOTAL_INT_PLUS1)/math.pow(2,(j+1)).toInt)) { + for (j <- 0 until (NUM_LEVELS - NUM_LEVELS/2) ) { + for(k <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(j+1+3)).toInt)) { if ( k == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(j+1)).toInt) { levelx_intpend_w_prior_en(j + 1)(k + 1) := 0.U @@ -205,6 +191,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { (levelx_intpend_id(j+1)(k)) := out_id1 (levelx_intpend_w_prior_en(j+1)(k)) := out_priority1 + } } claimid_in := levelx_intpend_id(NUM_LEVELS - NUM_LEVELS/2)(0) // This is the last level output selected_int_priority := levelx_intpend_w_prior_en(NUM_LEVELS - NUM_LEVELS/2)(0) @@ -218,7 +205,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { level_intpend_id(i)(j) := 0.U } level_intpend_w_prior_en(0) := Range(0,PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i)) ++ IndexedSeq(Fill(INTPRIORITY_BITS,0.U),Fill(INTPRIORITY_BITS,0.U)) - level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(Fill(ID_BITS,1.U),Fill(ID_BITS,1.U)) /*Cat((1.U((1*ID_BITS).W)),*///l2_intpend_id_ff//) + level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(Fill(ID_BITS,1.U),Fill(ID_BITS,1.U)) dontTouch(level_intpend_w_prior_en(0)) /// Do the prioritization of the interrupts here //////////// @@ -239,9 +226,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { } - // io.level_intpend_w_prior_en := (0 to NUM_LEVELS).map(i=>(0 to PIC_TOTAL_INT_PLUS1+1).map(j=> - // level_intpend_w_prior_en(i)(j)).reverse.reduce(Cat(_,_))).reverse.reduce(Cat(_,_)) - /////////////////////////////////////////////////////////////////////// // Config Reg` /////////////////////////////////////////////////////////////////////// @@ -278,12 +262,11 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { val intenable_reg_read = raddr_intenable_base_match & picm_rden_ff val gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff - intpend_reg_extended := Cat(Fill(INTPEND_SIZE-PIC_TOTAL_INT_PLUS1,0.U),(0 until PIC_TOTAL_INT_PLUS1/*extintsrc_req_gw.size*/).map(i => extintsrc_req_gw(i)).reverse.reduce(Cat(_,_))) + intpend_reg_extended := Cat(Fill(INTPEND_SIZE-PIC_TOTAL_INT_PLUS1,0.U),(0 until PIC_TOTAL_INT_PLUS1).map(i => extintsrc_req_gw(i)).reverse.reduce(Cat(_,_))) val intpend_rd_part_out = Wire(Vec(INT_GRPS,UInt(32.W))) - (0 until INT_GRPS).map (i=> intpend_rd_part_out(i) := Fill(32,(intpend_reg_read & (picm_raddr_ff(5,2) === i.asUInt))) & intpend_reg_extended((32*i)+31,32*i))//.reverse.reduce(Cat(_,_)) + (0 until INT_GRPS).map (i=> intpend_rd_part_out(i) := Fill(32,(intpend_reg_read & (picm_raddr_ff(5,2) === i.asUInt))) & intpend_reg_extended((32*i)+31,32*i)) intpend_rd_out := intpend_rd_part_out.reduce (_|_) - //for(i <- 0 until PIC_TOTAL_INT_PLUS1) { when (intenable_reg_re(i).asBool){ intenable_rd_out := intenable_reg(i)}.otherwise {intenable_rd_out :=0.U} } val intenable_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> intenable_reg_re(i).asBool -> intenable_reg(i) )) val intpriority_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> intpriority_reg_re(i).asBool -> intpriority_reg(i))) val gw_config_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> gw_config_reg_re(i).asBool -> gw_config_reg(i))) diff --git a/design/target/scala-2.12/classes/pic_ctrl$$anon$1.class b/design/target/scala-2.12/classes/pic_ctrl$$anon$1.class index 4187493b..9e02793b 100644 Binary files a/design/target/scala-2.12/classes/pic_ctrl$$anon$1.class and b/design/target/scala-2.12/classes/pic_ctrl$$anon$1.class differ diff --git a/design/target/scala-2.12/classes/pic_ctrl.class b/design/target/scala-2.12/classes/pic_ctrl.class index 8f5d4f12..05a47e45 100644 Binary files a/design/target/scala-2.12/classes/pic_ctrl.class and b/design/target/scala-2.12/classes/pic_ctrl.class differ diff --git a/design/target/scala-2.12/quasar_2.12-3.3.0.jar b/design/target/scala-2.12/quasar_2.12-3.3.0.jar index 9feb5aed..18bb08bb 100644 Binary files a/design/target/scala-2.12/quasar_2.12-3.3.0.jar and b/design/target/scala-2.12/quasar_2.12-3.3.0.jar differ diff --git a/design/target/streams/compile/_global/_global/compileSourceFileInputs/previous b/design/target/streams/compile/_global/_global/compileSourceFileInputs/previous index 153b65f2..5fb027cb 100644 --- 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\ No newline at end of file diff --git a/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip b/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip index 51a5a5fc..f293f741 100644 Binary files a/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip and b/design/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip differ diff --git a/design/target/streams/compile/compileIncremental/_global/streams/export b/design/target/streams/compile/compileIncremental/_global/streams/export index 95c087c4..fa24aad1 100644 --- a/design/target/streams/compile/compileIncremental/_global/streams/export +++ b/design/target/streams/compile/compileIncremental/_global/streams/export @@ -1 +1 @@ -scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath 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-Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala +scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/mem.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dma_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/pic_ctrl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_ifc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_aln_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_bp_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_compress_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_intf.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_trigger.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_ecc.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_stbuf.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_dccm_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_lsc_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_buffer.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_addrcheck.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_clkdomain.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_mul_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_div_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_alu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dbg/dbg.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/param.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/axi4_to_ahb.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/lib.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/ahb_to_axi4.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dmi/dmi_wrapper.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/include/bundle.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_trigger.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_decode_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_ib_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_dec_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_tlu_ctl.scala /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_gpr_ctl.scala diff --git a/design/target/streams/compile/compileIncremental/_global/streams/out b/design/target/streams/compile/compileIncremental/_global/streams/out index 2803a200..e4020bf8 100644 --- a/design/target/streams/compile/compileIncremental/_global/streams/out +++ b/design/target/streams/compile/compileIncremental/_global/streams/out @@ -2,23 +2,23 @@ [debug] Initial source changes:  [debug]  removed:Set() [debug]  added: Set() -[debug]  modified: Set(/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala) -[debug] Invalidated products: Set() +[debug]  modified: Set(/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/pic_ctrl.scala) +[debug] Invalidated products: Set(/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_dbg.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/br_tlu_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/dbg.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_dma.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/trace_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper_module.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_pic.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_mul_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_intf.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_div_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_gpr_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dctl_busbuff.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/read_addr$.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_clkdomain.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_alu_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_bp_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_exu.class, 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/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/decode_exu.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_tlu_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/quasar_wrapper.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_buffer.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/dbg$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_trigger.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/wrapper.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/exu/exu_div_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/rets_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ahb_out_dma.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_div.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/state_t$.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/lib$rvclkhdr.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/axi_channels$.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class, 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/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/ahb_channel.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/ahb_to_axi4.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/alu_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_addrcheck.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_alu.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/trigger_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_tlu.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_ib_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/read_addr.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/gpr_exu.class, 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/home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/write_addr$.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/quasar.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dest_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_dec_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dec_mem_ctrl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/mem/quasar.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_dec.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/dec_timer_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/dma_ifc.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dbg/dbg_dma.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/ifu/ifu_compress_ctl.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/include/lsu_error_pkt_t.class, /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes/dec/CSRs.class) [debug] External API changes: API Changes: Set() [debug] Modified binary dependencies: Set() -[debug] Initial directly invalidated classes: Set(ifu.ifu_mem_ctl, ifu.mem_ctl_io) +[debug] Initial directly invalidated classes: Set(pic_ctrl) [debug]  [debug] Sources indirectly invalidated by: -[debug]  product: Set() +[debug]  product: Set(/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dma_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_ib_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_div_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_compress_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/mem.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_tlu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_alu_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_stbuf.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/lib.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_buffer.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_bus_intf.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_aln_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_gpr_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/param.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/ahb_to_axi4.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar_wrapper.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_ecc.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_clkdomain.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/pic_ctrl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dbg/dbg.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/exu/exu_mul_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_addrcheck.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lsu/lsu_trigger.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/include/bundle.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/quasar.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/lib/axi4_to_ahb.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_decode_ctl.scala, /home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/dec/dec_trigger.scala) [debug]  binary dep: Set() [debug]  external source: Set() -[debug] All initially invalidated classes: Set(ifu.ifu_mem_ctl, ifu.mem_ctl_io) -[debug] All initially invalidated sources:Set(/home/waleedbinehsan/Desktop/Quasar/design/src/main/scala/ifu/ifu_mem_ctl.scala) -[debug] Initial set of included nodes: ifu.ifu_mem_ctl, ifu.mem_ctl_io -[info] Compiling 1 Scala source to /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes ... +[debug] All sources are invalidated. +[debug] Initial set of included nodes: pic_ctrl +[debug] Recompiling all sources: number of invalidated sources > 50.0% of all sources +[info] Compiling 39 Scala sources to /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes ... [debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 [debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 -[debug] [zinc] Running cached compiler 284ab752 for Scala compiler version 2.12.10 +[debug] [zinc] Running cached compiler 52600d8e for Scala compiler version 2.12.10 [debug] [zinc] The Scala compiler is invoked with: [debug]  -Xsource:2.11 [debug]  -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar @@ -26,11 +26,5 @@ [debug]  /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar [debug]  -classpath [debug]  /home/waleedbinehsan/Desktop/Quasar/design/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -[debug] Scala compilation took 17.036715456 s +[debug] Scala compilation took 40.548310938 s [debug] Done compiling. -[debug] New invalidations: -[debug]  Set() -[debug] Initial set of included nodes:  -[debug] Previously invalidated, but (transitively) depend on new invalidations: -[debug]  Set() -[debug] No classes were invalidated. diff --git a/design/target/streams/compile/copyResources/_global/streams/copy-resources b/design/target/streams/compile/copyResources/_global/streams/copy-resources index a4a6a198..26c2c974 100644 --- a/design/target/streams/compile/copyResources/_global/streams/copy-resources +++ b/design/target/streams/compile/copyResources/_global/streams/copy-resources @@ -1 +1 @@ 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\ No newline at end of file diff --git a/design/target/streams/compile/packageBin/_global/streams/inputs b/design/target/streams/compile/packageBin/_global/streams/inputs index 6ef253e5..31d11c0b 100644 --- a/design/target/streams/compile/packageBin/_global/streams/inputs +++ b/design/target/streams/compile/packageBin/_global/streams/inputs @@ -1 +1 @@ -447944643 \ No newline at end of file +-1974124775 \ No newline at end of file diff --git a/verif/LEC/formality_work/formality_log/readme.md b/verif/LEC/formality_work/formality_log/readme.md new file mode 100644 index 00000000..ce013625 --- /dev/null +++ b/verif/LEC/formality_work/formality_log/readme.md @@ -0,0 +1 @@ +hello diff --git a/verif/LEC/formality_work/run_me.fms b/verif/LEC/formality_work/run_me.fms index 34668b44..f211af08 100755 --- a/verif/LEC/formality_work/run_me.fms +++ b/verif/LEC/formality_work/run_me.fms @@ -85,8 +85,7 @@ if {![file isdirectory $fm_path_r]} { # Setting BLack Boxes on Memories set_black_box r:/WORK/el2_mem - set_black_box i:/WORK/mem_ICACHE_BEAT_BITS3_ICCM_BITS16_ICACHE_NUM_WAYS2_DCCM_BYTE_WIDTH4_ICCM_BANK_INDEX_LO4_ICACHE_BANK_BITS1_DCCM_BITS16_ICACHE_BEAT_ADDR_HI5_ICCM_INDEX_BITS12_ICCM_BANK_HI3_ICACHE_BANKS_WAY2_ICACHE_INDEX_HI12_DCCM_NUM_BANKS4_ICACHE_BANK_HI3_ICACHE_BANK_LO3_DCCM_ENABLE1_ICACHE_TAG_LO13_ICACHE_DATA_INDEX_LO4_ICCM_NUM_BANKS4_ICACHE_ECC1_ICACHE_ENABLE1_DCCM_BANK_BITS2_ICCM_ENABLE1_ICCM_BANK_BITS2_ICACHE_TAG_DEPTH128_ICACHE_WAYPACK0_DCCM_SIZE64_DCCM_FDATA_WIDTH39_ICACHE_TAG_INDEX_LO6_ICACHE_DATA_DEPTH512 - + set_black_box i:/WORK/mem_ICACHE_BEAT_BITS* # Setting User Match on ports source $LEC_ROOT/setup_files/port.fms