IMC started
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@ -300,6 +300,14 @@
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_data",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_wr_data_1",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_wr_data_0"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rw_addr",
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22357
el2_ifu_mem_ctl.fir
22357
el2_ifu_mem_ctl.fir
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9158
el2_ifu_mem_ctl.v
9158
el2_ifu_mem_ctl.v
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@ -126,7 +126,7 @@ class mem_ctl_bundle extends Bundle with el2_lib{
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val iccm_buf_correct_ecc = Output(Bool())
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val iccm_correction_state = Output(Bool())
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val scan_mode = Input(Bool())
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val ic_miss_buff_ecc = Output(UInt())
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val data = Output(UInt())
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val ic_wr_ecc = Output(UInt())
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}
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class el2_ifu_mem_ctl extends Module with el2_lib {
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@ -348,7 +348,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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val ic_miss_buff_ecc = WireInit(UInt(7.W), 0.U) //rvecc_encode_64(ic_miss_buff_half)
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m2.io.din := ic_miss_buff_half
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ic_miss_buff_ecc := m2.io.ecc_out
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io.ic_miss_buff_ecc := ic_miss_buff_ecc
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io.data := Cat(io.ic_wr_data(1),io.ic_wr_data(0))
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val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
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io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
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io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata
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