axi to ahb update
This commit is contained in:
Laraib Khan
parent
408cd7612b
commit
174b18b84e
499
axi4_to_ahb.fir
499
axi4_to_ahb.fir
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@ -245,8 +245,8 @@ circuit axi4_to_ahb :
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input reset : AsyncReset
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input reset : AsyncReset
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output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>}
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output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>}
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wire buf_rst : UInt<1>
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wire buf_rst : UInt<3>
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buf_rst <= UInt<1>("h00")
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buf_rst <= UInt<3>("h00")
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wire buf_state_en : UInt<1>
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wire buf_state_en : UInt<1>
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buf_state_en <= UInt<1>("h00")
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buf_state_en <= UInt<1>("h00")
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wire ahbm_clk : Clock @[axi4_to_ahb.scala 62:22]
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wire ahbm_clk : Clock @[axi4_to_ahb.scala 62:22]
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@ -256,10 +256,10 @@ circuit axi4_to_ahb :
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buf_state <= UInt<3>("h00")
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buf_state <= UInt<3>("h00")
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wire buf_nxtstate : UInt<3>
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wire buf_nxtstate : UInt<3>
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buf_nxtstate <= UInt<3>("h00")
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buf_nxtstate <= UInt<3>("h00")
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node _T = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 68:66]
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node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 68:70]
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node _T_1 = and(buf_state_en, _T) @[axi4_to_ahb.scala 68:64]
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node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 68:50]
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node _T_2 = bits(_T_1, 0, 0) @[axi4_to_ahb.scala 68:76]
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node _T_2 = not(buf_rst) @[axi4_to_ahb.scala 68:100]
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node _T_3 = mux(_T_2, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 68:49]
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node _T_3 = and(_T_1, _T_2) @[axi4_to_ahb.scala 68:98]
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reg _T_4 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 68:45]
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reg _T_4 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 68:45]
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_T_4 <= _T_3 @[axi4_to_ahb.scala 68:45]
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_T_4 <= _T_3 @[axi4_to_ahb.scala 68:45]
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buf_state <= _T_4 @[axi4_to_ahb.scala 68:13]
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buf_state <= _T_4 @[axi4_to_ahb.scala 68:13]
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@ -987,14 +987,13 @@ circuit axi4_to_ahb :
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slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23]
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slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 337:23]
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slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 338:23]
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slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 338:23]
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skip @[Conditional.scala 39:67]
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skip @[Conditional.scala 39:67]
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buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 342:11]
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cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 341:16]
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cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 343:16]
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node _T_442 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 342:33]
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node _T_442 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 344:33]
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node _T_443 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 342:73]
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node _T_443 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 344:73]
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node _T_444 = eq(_T_443, UInt<1>("h01")) @[axi4_to_ahb.scala 342:80]
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node _T_444 = eq(_T_443, UInt<1>("h01")) @[axi4_to_ahb.scala 344:80]
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node _T_445 = and(buf_aligned_in, _T_444) @[axi4_to_ahb.scala 342:60]
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node _T_445 = and(buf_aligned_in, _T_444) @[axi4_to_ahb.scala 344:60]
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node _T_446 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 342:100]
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node _T_446 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 344:100]
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node _T_447 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 342:132]
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node _T_447 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 344:132]
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node _T_448 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:50]
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node _T_448 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:50]
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node _T_449 = eq(_T_448, UInt<8>("h0ff")) @[axi4_to_ahb.scala 173:57]
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node _T_449 = eq(_T_448, UInt<8>("h0ff")) @[axi4_to_ahb.scala 173:57]
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node _T_450 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:81]
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node _T_450 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:81]
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@ -1032,27 +1031,27 @@ circuit axi4_to_ahb :
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node _T_482 = bits(_T_481, 0, 0) @[Bitwise.scala 72:15]
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node _T_482 = bits(_T_481, 0, 0) @[Bitwise.scala 72:15]
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node _T_483 = mux(_T_482, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
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node _T_483 = mux(_T_482, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
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node _T_484 = and(UInt<3>("h06"), _T_483) @[axi4_to_ahb.scala 177:17]
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node _T_484 = and(UInt<3>("h06"), _T_483) @[axi4_to_ahb.scala 177:17]
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node _T_485 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 344:152]
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node _T_485 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 342:152]
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node _T_486 = mux(_T_446, _T_479, _T_485) @[axi4_to_ahb.scala 344:43]
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node _T_486 = mux(_T_446, _T_479, _T_485) @[axi4_to_ahb.scala 342:43]
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node _T_487 = cat(_T_442, _T_486) @[Cat.scala 29:58]
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node _T_487 = cat(_T_442, _T_486) @[Cat.scala 29:58]
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buf_addr_in <= _T_487 @[axi4_to_ahb.scala 344:15]
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buf_addr_in <= _T_487 @[axi4_to_ahb.scala 342:15]
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node _T_488 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 345:27]
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node _T_488 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 343:27]
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buf_tag_in <= _T_488 @[axi4_to_ahb.scala 345:14]
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buf_tag_in <= _T_488 @[axi4_to_ahb.scala 343:14]
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node _T_489 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 346:32]
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node _T_489 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 344:32]
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buf_byteen_in <= _T_489 @[axi4_to_ahb.scala 346:17]
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buf_byteen_in <= _T_489 @[axi4_to_ahb.scala 344:17]
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node _T_490 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 347:33]
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node _T_490 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 345:33]
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node _T_491 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 347:59]
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node _T_491 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 345:59]
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node _T_492 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 347:80]
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node _T_492 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 345:80]
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node _T_493 = mux(_T_490, _T_491, _T_492) @[axi4_to_ahb.scala 347:21]
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node _T_493 = mux(_T_490, _T_491, _T_492) @[axi4_to_ahb.scala 345:21]
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buf_data_in <= _T_493 @[axi4_to_ahb.scala 347:15]
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buf_data_in <= _T_493 @[axi4_to_ahb.scala 345:15]
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node _T_494 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:52]
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node _T_494 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:52]
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node _T_495 = eq(_T_494, UInt<2>("h03")) @[axi4_to_ahb.scala 348:58]
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node _T_495 = eq(_T_494, UInt<2>("h03")) @[axi4_to_ahb.scala 346:58]
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node _T_496 = and(buf_aligned_in, _T_495) @[axi4_to_ahb.scala 348:38]
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node _T_496 = and(buf_aligned_in, _T_495) @[axi4_to_ahb.scala 346:38]
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node _T_497 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 348:84]
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node _T_497 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 346:84]
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node _T_498 = eq(_T_497, UInt<1>("h01")) @[axi4_to_ahb.scala 348:91]
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node _T_498 = eq(_T_497, UInt<1>("h01")) @[axi4_to_ahb.scala 346:91]
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node _T_499 = and(_T_496, _T_498) @[axi4_to_ahb.scala 348:71]
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node _T_499 = and(_T_496, _T_498) @[axi4_to_ahb.scala 346:71]
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node _T_500 = bits(_T_499, 0, 0) @[axi4_to_ahb.scala 348:111]
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node _T_500 = bits(_T_499, 0, 0) @[axi4_to_ahb.scala 346:111]
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node _T_501 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 348:142]
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node _T_501 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:142]
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node _T_502 = bits(_T_501, 7, 0) @[axi4_to_ahb.scala 166:42]
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node _T_502 = bits(_T_501, 7, 0) @[axi4_to_ahb.scala 166:42]
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node _T_503 = eq(_T_502, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:49]
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node _T_503 = eq(_T_502, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:49]
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node _T_504 = bits(_T_503, 0, 0) @[Bitwise.scala 72:15]
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node _T_504 = bits(_T_503, 0, 0) @[Bitwise.scala 72:15]
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@ -1082,162 +1081,162 @@ circuit axi4_to_ahb :
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node _T_528 = mux(_T_527, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_528 = mux(_T_527, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_529 = and(UInt<2>("h01"), _T_528) @[axi4_to_ahb.scala 168:21]
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node _T_529 = and(UInt<2>("h01"), _T_528) @[axi4_to_ahb.scala 168:21]
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node _T_530 = or(_T_515, _T_529) @[axi4_to_ahb.scala 167:93]
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node _T_530 = or(_T_515, _T_529) @[axi4_to_ahb.scala 167:93]
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node _T_531 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:161]
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node _T_531 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:161]
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node _T_532 = mux(_T_500, _T_530, _T_531) @[axi4_to_ahb.scala 348:21]
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node _T_532 = mux(_T_500, _T_530, _T_531) @[axi4_to_ahb.scala 346:21]
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buf_size_in <= _T_532 @[axi4_to_ahb.scala 348:15]
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buf_size_in <= _T_532 @[axi4_to_ahb.scala 346:15]
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node _T_533 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 349:32]
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node _T_533 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 347:32]
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node _T_534 = eq(_T_533, UInt<1>("h00")) @[axi4_to_ahb.scala 349:39]
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node _T_534 = eq(_T_533, UInt<1>("h00")) @[axi4_to_ahb.scala 347:39]
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node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 350:17]
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node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:17]
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node _T_536 = eq(_T_535, UInt<1>("h00")) @[axi4_to_ahb.scala 350:24]
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node _T_536 = eq(_T_535, UInt<1>("h00")) @[axi4_to_ahb.scala 348:24]
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node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 349:48]
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node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 347:48]
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node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 350:47]
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node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:47]
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node _T_539 = eq(_T_538, UInt<2>("h01")) @[axi4_to_ahb.scala 350:54]
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node _T_539 = eq(_T_538, UInt<2>("h01")) @[axi4_to_ahb.scala 348:54]
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node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 350:33]
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node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 348:33]
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node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 350:86]
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node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 348:86]
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node _T_542 = eq(_T_541, UInt<2>("h02")) @[axi4_to_ahb.scala 350:93]
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node _T_542 = eq(_T_541, UInt<2>("h02")) @[axi4_to_ahb.scala 348:93]
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node _T_543 = or(_T_540, _T_542) @[axi4_to_ahb.scala 350:72]
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node _T_543 = or(_T_540, _T_542) @[axi4_to_ahb.scala 348:72]
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node _T_544 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:18]
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node _T_544 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:18]
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node _T_545 = eq(_T_544, UInt<2>("h03")) @[axi4_to_ahb.scala 351:25]
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node _T_545 = eq(_T_544, UInt<2>("h03")) @[axi4_to_ahb.scala 349:25]
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node _T_546 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:55]
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node _T_546 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:55]
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node _T_547 = eq(_T_546, UInt<2>("h03")) @[axi4_to_ahb.scala 351:62]
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node _T_547 = eq(_T_546, UInt<2>("h03")) @[axi4_to_ahb.scala 349:62]
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node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:90]
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node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:90]
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node _T_549 = eq(_T_548, UInt<4>("h0c")) @[axi4_to_ahb.scala 351:97]
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node _T_549 = eq(_T_548, UInt<4>("h0c")) @[axi4_to_ahb.scala 349:97]
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node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 351:74]
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node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 349:74]
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node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:125]
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node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:125]
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node _T_552 = eq(_T_551, UInt<6>("h030")) @[axi4_to_ahb.scala 351:132]
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node _T_552 = eq(_T_551, UInt<6>("h030")) @[axi4_to_ahb.scala 349:132]
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node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 351:109]
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node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 349:109]
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node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:161]
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node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:161]
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node _T_555 = eq(_T_554, UInt<8>("h0c0")) @[axi4_to_ahb.scala 351:168]
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node _T_555 = eq(_T_554, UInt<8>("h0c0")) @[axi4_to_ahb.scala 349:168]
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node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 351:145]
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node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 349:145]
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node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:21]
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node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:21]
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node _T_558 = eq(_T_557, UInt<4>("h0f")) @[axi4_to_ahb.scala 352:28]
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node _T_558 = eq(_T_557, UInt<4>("h0f")) @[axi4_to_ahb.scala 350:28]
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node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 351:181]
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node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 349:181]
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node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:56]
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node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:56]
|
||||||
node _T_561 = eq(_T_560, UInt<8>("h0f0")) @[axi4_to_ahb.scala 352:63]
|
node _T_561 = eq(_T_560, UInt<8>("h0f0")) @[axi4_to_ahb.scala 350:63]
|
||||||
node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 352:40]
|
node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 350:40]
|
||||||
node _T_563 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:92]
|
node _T_563 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:92]
|
||||||
node _T_564 = eq(_T_563, UInt<8>("h0ff")) @[axi4_to_ahb.scala 352:99]
|
node _T_564 = eq(_T_563, UInt<8>("h0ff")) @[axi4_to_ahb.scala 350:99]
|
||||||
node _T_565 = or(_T_562, _T_564) @[axi4_to_ahb.scala 352:76]
|
node _T_565 = or(_T_562, _T_564) @[axi4_to_ahb.scala 350:76]
|
||||||
node _T_566 = and(_T_545, _T_565) @[axi4_to_ahb.scala 351:38]
|
node _T_566 = and(_T_545, _T_565) @[axi4_to_ahb.scala 349:38]
|
||||||
node _T_567 = or(_T_543, _T_566) @[axi4_to_ahb.scala 350:106]
|
node _T_567 = or(_T_543, _T_566) @[axi4_to_ahb.scala 348:106]
|
||||||
buf_aligned_in <= _T_567 @[axi4_to_ahb.scala 349:18]
|
buf_aligned_in <= _T_567 @[axi4_to_ahb.scala 347:18]
|
||||||
node _T_568 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 354:39]
|
node _T_568 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 352:39]
|
||||||
node _T_569 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 354:58]
|
node _T_569 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 352:58]
|
||||||
node _T_570 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 354:83]
|
node _T_570 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:83]
|
||||||
node _T_571 = cat(_T_569, _T_570) @[Cat.scala 29:58]
|
node _T_571 = cat(_T_569, _T_570) @[Cat.scala 29:58]
|
||||||
node _T_572 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 354:104]
|
node _T_572 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 352:104]
|
||||||
node _T_573 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 354:129]
|
node _T_573 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 352:129]
|
||||||
node _T_574 = cat(_T_572, _T_573) @[Cat.scala 29:58]
|
node _T_574 = cat(_T_572, _T_573) @[Cat.scala 29:58]
|
||||||
node _T_575 = mux(_T_568, _T_571, _T_574) @[axi4_to_ahb.scala 354:22]
|
node _T_575 = mux(_T_568, _T_571, _T_574) @[axi4_to_ahb.scala 352:22]
|
||||||
io.ahb_haddr <= _T_575 @[axi4_to_ahb.scala 354:16]
|
io.ahb_haddr <= _T_575 @[axi4_to_ahb.scala 352:16]
|
||||||
node _T_576 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 355:39]
|
node _T_576 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39]
|
||||||
node _T_577 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15]
|
node _T_577 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_578 = mux(_T_577, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
node _T_578 = mux(_T_577, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_579 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 355:90]
|
node _T_579 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 353:90]
|
||||||
node _T_580 = and(_T_578, _T_579) @[axi4_to_ahb.scala 355:77]
|
node _T_580 = and(_T_578, _T_579) @[axi4_to_ahb.scala 353:77]
|
||||||
node _T_581 = cat(UInt<1>("h00"), _T_580) @[Cat.scala 29:58]
|
node _T_581 = cat(UInt<1>("h00"), _T_580) @[Cat.scala 29:58]
|
||||||
node _T_582 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15]
|
node _T_582 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_583 = mux(_T_582, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
node _T_583 = mux(_T_582, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_584 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 355:144]
|
node _T_584 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 353:144]
|
||||||
node _T_585 = and(_T_583, _T_584) @[axi4_to_ahb.scala 355:134]
|
node _T_585 = and(_T_583, _T_584) @[axi4_to_ahb.scala 353:134]
|
||||||
node _T_586 = cat(UInt<1>("h00"), _T_585) @[Cat.scala 29:58]
|
node _T_586 = cat(UInt<1>("h00"), _T_585) @[Cat.scala 29:58]
|
||||||
node _T_587 = mux(_T_576, _T_581, _T_586) @[axi4_to_ahb.scala 355:22]
|
node _T_587 = mux(_T_576, _T_581, _T_586) @[axi4_to_ahb.scala 353:22]
|
||||||
io.ahb_hsize <= _T_587 @[axi4_to_ahb.scala 355:16]
|
io.ahb_hsize <= _T_587 @[axi4_to_ahb.scala 353:16]
|
||||||
io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 357:17]
|
io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 355:17]
|
||||||
io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 358:20]
|
io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 356:20]
|
||||||
node _T_588 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 359:47]
|
node _T_588 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 357:47]
|
||||||
node _T_589 = not(_T_588) @[axi4_to_ahb.scala 359:33]
|
node _T_589 = not(_T_588) @[axi4_to_ahb.scala 357:33]
|
||||||
node _T_590 = cat(UInt<1>("h01"), _T_589) @[Cat.scala 29:58]
|
node _T_590 = cat(UInt<1>("h01"), _T_589) @[Cat.scala 29:58]
|
||||||
io.ahb_hprot <= _T_590 @[axi4_to_ahb.scala 359:16]
|
io.ahb_hprot <= _T_590 @[axi4_to_ahb.scala 357:16]
|
||||||
node _T_591 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 360:40]
|
node _T_591 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:40]
|
||||||
node _T_592 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 360:55]
|
node _T_592 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 358:55]
|
||||||
node _T_593 = eq(_T_592, UInt<1>("h01")) @[axi4_to_ahb.scala 360:62]
|
node _T_593 = eq(_T_592, UInt<1>("h01")) @[axi4_to_ahb.scala 358:62]
|
||||||
node _T_594 = mux(_T_591, _T_593, buf_write) @[axi4_to_ahb.scala 360:23]
|
node _T_594 = mux(_T_591, _T_593, buf_write) @[axi4_to_ahb.scala 358:23]
|
||||||
io.ahb_hwrite <= _T_594 @[axi4_to_ahb.scala 360:17]
|
io.ahb_hwrite <= _T_594 @[axi4_to_ahb.scala 358:17]
|
||||||
node _T_595 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 361:28]
|
node _T_595 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 359:28]
|
||||||
io.ahb_hwdata <= _T_595 @[axi4_to_ahb.scala 361:17]
|
io.ahb_hwdata <= _T_595 @[axi4_to_ahb.scala 359:17]
|
||||||
slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 363:15]
|
slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 361:15]
|
||||||
node _T_596 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 364:43]
|
node _T_596 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 362:43]
|
||||||
node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 364:23]
|
node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 362:23]
|
||||||
node _T_598 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15]
|
node _T_598 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15]
|
||||||
node _T_599 = mux(_T_598, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
node _T_599 = mux(_T_598, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||||||
node _T_600 = and(_T_599, UInt<2>("h02")) @[axi4_to_ahb.scala 364:88]
|
node _T_600 = and(_T_599, UInt<2>("h02")) @[axi4_to_ahb.scala 362:88]
|
||||||
node _T_601 = cat(_T_597, _T_600) @[Cat.scala 29:58]
|
node _T_601 = cat(_T_597, _T_600) @[Cat.scala 29:58]
|
||||||
slave_opc <= _T_601 @[axi4_to_ahb.scala 364:13]
|
slave_opc <= _T_601 @[axi4_to_ahb.scala 362:13]
|
||||||
node _T_602 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 365:41]
|
node _T_602 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 363:41]
|
||||||
node _T_603 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 365:66]
|
node _T_603 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 363:66]
|
||||||
node _T_604 = cat(_T_603, _T_603) @[Cat.scala 29:58]
|
node _T_604 = cat(_T_603, _T_603) @[Cat.scala 29:58]
|
||||||
node _T_605 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 365:91]
|
node _T_605 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 363:91]
|
||||||
node _T_606 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 365:110]
|
node _T_606 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 363:110]
|
||||||
node _T_607 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 365:131]
|
node _T_607 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 363:131]
|
||||||
node _T_608 = mux(_T_605, _T_606, _T_607) @[axi4_to_ahb.scala 365:79]
|
node _T_608 = mux(_T_605, _T_606, _T_607) @[axi4_to_ahb.scala 363:79]
|
||||||
node _T_609 = mux(_T_602, _T_604, _T_608) @[axi4_to_ahb.scala 365:21]
|
node _T_609 = mux(_T_602, _T_604, _T_608) @[axi4_to_ahb.scala 363:21]
|
||||||
slave_rdata <= _T_609 @[axi4_to_ahb.scala 365:15]
|
slave_rdata <= _T_609 @[axi4_to_ahb.scala 363:15]
|
||||||
node _T_610 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 366:26]
|
node _T_610 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 364:26]
|
||||||
slave_tag <= _T_610 @[axi4_to_ahb.scala 366:13]
|
slave_tag <= _T_610 @[axi4_to_ahb.scala 364:13]
|
||||||
node _T_611 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 368:33]
|
node _T_611 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 366:33]
|
||||||
node _T_612 = neq(_T_611, UInt<1>("h00")) @[axi4_to_ahb.scala 368:40]
|
node _T_612 = neq(_T_611, UInt<1>("h00")) @[axi4_to_ahb.scala 366:40]
|
||||||
node _T_613 = and(_T_612, io.ahb_hready) @[axi4_to_ahb.scala 368:52]
|
node _T_613 = and(_T_612, io.ahb_hready) @[axi4_to_ahb.scala 366:52]
|
||||||
node _T_614 = and(_T_613, io.ahb_hwrite) @[axi4_to_ahb.scala 368:68]
|
node _T_614 = and(_T_613, io.ahb_hwrite) @[axi4_to_ahb.scala 366:68]
|
||||||
last_addr_en <= _T_614 @[axi4_to_ahb.scala 368:16]
|
last_addr_en <= _T_614 @[axi4_to_ahb.scala 366:16]
|
||||||
node _T_615 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 370:30]
|
node _T_615 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 368:30]
|
||||||
node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 370:47]
|
node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 368:47]
|
||||||
wrbuf_en <= _T_616 @[axi4_to_ahb.scala 370:12]
|
wrbuf_en <= _T_616 @[axi4_to_ahb.scala 368:12]
|
||||||
node _T_617 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 371:34]
|
node _T_617 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 369:34]
|
||||||
node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 371:50]
|
node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 369:50]
|
||||||
wrbuf_data_en <= _T_618 @[axi4_to_ahb.scala 371:17]
|
wrbuf_data_en <= _T_618 @[axi4_to_ahb.scala 369:17]
|
||||||
node _T_619 = and(master_valid, master_ready) @[axi4_to_ahb.scala 372:34]
|
node _T_619 = and(master_valid, master_ready) @[axi4_to_ahb.scala 370:34]
|
||||||
node _T_620 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 372:62]
|
node _T_620 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 370:62]
|
||||||
node _T_621 = eq(_T_620, UInt<1>("h01")) @[axi4_to_ahb.scala 372:69]
|
node _T_621 = eq(_T_620, UInt<1>("h01")) @[axi4_to_ahb.scala 370:69]
|
||||||
node _T_622 = and(_T_619, _T_621) @[axi4_to_ahb.scala 372:49]
|
node _T_622 = and(_T_619, _T_621) @[axi4_to_ahb.scala 370:49]
|
||||||
wrbuf_cmd_sent <= _T_622 @[axi4_to_ahb.scala 372:18]
|
wrbuf_cmd_sent <= _T_622 @[axi4_to_ahb.scala 370:18]
|
||||||
node _T_623 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 373:33]
|
node _T_623 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 371:33]
|
||||||
node _T_624 = and(wrbuf_cmd_sent, _T_623) @[axi4_to_ahb.scala 373:31]
|
node _T_624 = and(wrbuf_cmd_sent, _T_623) @[axi4_to_ahb.scala 371:31]
|
||||||
wrbuf_rst <= _T_624 @[axi4_to_ahb.scala 373:13]
|
wrbuf_rst <= _T_624 @[axi4_to_ahb.scala 371:13]
|
||||||
node _T_625 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 375:35]
|
node _T_625 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 373:35]
|
||||||
node _T_626 = and(wrbuf_vld, _T_625) @[axi4_to_ahb.scala 375:33]
|
node _T_626 = and(wrbuf_vld, _T_625) @[axi4_to_ahb.scala 373:33]
|
||||||
node _T_627 = eq(_T_626, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21]
|
node _T_627 = eq(_T_626, UInt<1>("h00")) @[axi4_to_ahb.scala 373:21]
|
||||||
node _T_628 = and(_T_627, master_ready) @[axi4_to_ahb.scala 375:52]
|
node _T_628 = and(_T_627, master_ready) @[axi4_to_ahb.scala 373:52]
|
||||||
io.axi_awready <= _T_628 @[axi4_to_ahb.scala 375:18]
|
io.axi_awready <= _T_628 @[axi4_to_ahb.scala 373:18]
|
||||||
node _T_629 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 376:39]
|
node _T_629 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:39]
|
||||||
node _T_630 = and(wrbuf_data_vld, _T_629) @[axi4_to_ahb.scala 376:37]
|
node _T_630 = and(wrbuf_data_vld, _T_629) @[axi4_to_ahb.scala 374:37]
|
||||||
node _T_631 = eq(_T_630, UInt<1>("h00")) @[axi4_to_ahb.scala 376:20]
|
node _T_631 = eq(_T_630, UInt<1>("h00")) @[axi4_to_ahb.scala 374:20]
|
||||||
node _T_632 = and(_T_631, master_ready) @[axi4_to_ahb.scala 376:56]
|
node _T_632 = and(_T_631, master_ready) @[axi4_to_ahb.scala 374:56]
|
||||||
io.axi_wready <= _T_632 @[axi4_to_ahb.scala 376:17]
|
io.axi_wready <= _T_632 @[axi4_to_ahb.scala 374:17]
|
||||||
node _T_633 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 377:33]
|
node _T_633 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 375:33]
|
||||||
node _T_634 = eq(_T_633, UInt<1>("h00")) @[axi4_to_ahb.scala 377:21]
|
node _T_634 = eq(_T_633, UInt<1>("h00")) @[axi4_to_ahb.scala 375:21]
|
||||||
node _T_635 = and(_T_634, master_ready) @[axi4_to_ahb.scala 377:51]
|
node _T_635 = and(_T_634, master_ready) @[axi4_to_ahb.scala 375:51]
|
||||||
io.axi_arready <= _T_635 @[axi4_to_ahb.scala 377:18]
|
io.axi_arready <= _T_635 @[axi4_to_ahb.scala 375:18]
|
||||||
io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 378:16]
|
io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 376:16]
|
||||||
node _T_636 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 381:68]
|
node _T_636 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 379:68]
|
||||||
node _T_637 = mux(_T_636, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 381:52]
|
node _T_637 = mux(_T_636, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 379:52]
|
||||||
node _T_638 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 381:88]
|
node _T_638 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 379:88]
|
||||||
node _T_639 = and(_T_637, _T_638) @[axi4_to_ahb.scala 381:86]
|
node _T_639 = and(_T_637, _T_638) @[axi4_to_ahb.scala 379:86]
|
||||||
reg _T_640 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 381:48]
|
reg _T_640 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:48]
|
||||||
_T_640 <= _T_639 @[axi4_to_ahb.scala 381:48]
|
_T_640 <= _T_639 @[axi4_to_ahb.scala 379:48]
|
||||||
wrbuf_vld <= _T_640 @[axi4_to_ahb.scala 381:18]
|
wrbuf_vld <= _T_640 @[axi4_to_ahb.scala 379:18]
|
||||||
node _T_641 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 382:73]
|
node _T_641 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 380:73]
|
||||||
node _T_642 = mux(_T_641, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 382:52]
|
node _T_642 = mux(_T_641, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 380:52]
|
||||||
node _T_643 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 382:99]
|
node _T_643 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 380:99]
|
||||||
node _T_644 = and(_T_642, _T_643) @[axi4_to_ahb.scala 382:97]
|
node _T_644 = and(_T_642, _T_643) @[axi4_to_ahb.scala 380:97]
|
||||||
reg _T_645 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 382:48]
|
reg _T_645 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 380:48]
|
||||||
_T_645 <= _T_644 @[axi4_to_ahb.scala 382:48]
|
_T_645 <= _T_644 @[axi4_to_ahb.scala 380:48]
|
||||||
wrbuf_data_vld <= _T_645 @[axi4_to_ahb.scala 382:18]
|
wrbuf_data_vld <= _T_645 @[axi4_to_ahb.scala 380:18]
|
||||||
node _T_646 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 384:57]
|
node _T_646 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 382:57]
|
||||||
node _T_647 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 384:91]
|
node _T_647 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:91]
|
||||||
reg _T_648 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_648 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_647 : @[Reg.scala 28:19]
|
when _T_647 : @[Reg.scala 28:19]
|
||||||
_T_648 <= _T_646 @[Reg.scala 28:23]
|
_T_648 <= _T_646 @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
wrbuf_tag <= _T_648 @[axi4_to_ahb.scala 384:13]
|
wrbuf_tag <= _T_648 @[axi4_to_ahb.scala 382:13]
|
||||||
node _T_649 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 385:60]
|
node _T_649 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 383:60]
|
||||||
node _T_650 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 385:88]
|
node _T_650 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 383:88]
|
||||||
reg _T_651 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_651 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_650 : @[Reg.scala 28:19]
|
when _T_650 : @[Reg.scala 28:19]
|
||||||
_T_651 <= _T_649 @[Reg.scala 28:23]
|
_T_651 <= _T_649 @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
wrbuf_size <= _T_651 @[axi4_to_ahb.scala 385:14]
|
wrbuf_size <= _T_651 @[axi4_to_ahb.scala 383:14]
|
||||||
node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 387:48]
|
node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 385:48]
|
||||||
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
|
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
|
||||||
rvclkhdr_2.clock <= clock
|
rvclkhdr_2.clock <= clock
|
||||||
rvclkhdr_2.reset <= reset
|
rvclkhdr_2.reset <= reset
|
||||||
|
|
@ -1246,8 +1245,8 @@ circuit axi4_to_ahb :
|
||||||
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||||||
reg _T_653 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
reg _T_653 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||||||
_T_653 <= io.axi_awaddr @[el2_lib.scala 514:16]
|
_T_653 <= io.axi_awaddr @[el2_lib.scala 514:16]
|
||||||
wrbuf_addr <= _T_653 @[axi4_to_ahb.scala 387:14]
|
wrbuf_addr <= _T_653 @[axi4_to_ahb.scala 385:14]
|
||||||
node _T_654 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 388:52]
|
node _T_654 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 386:52]
|
||||||
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
|
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
|
||||||
rvclkhdr_3.clock <= clock
|
rvclkhdr_3.clock <= clock
|
||||||
rvclkhdr_3.reset <= reset
|
rvclkhdr_3.reset <= reset
|
||||||
|
|
@ -1256,37 +1255,37 @@ circuit axi4_to_ahb :
|
||||||
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||||||
reg _T_655 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
reg _T_655 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||||||
_T_655 <= io.axi_wdata @[el2_lib.scala 514:16]
|
_T_655 <= io.axi_wdata @[el2_lib.scala 514:16]
|
||||||
wrbuf_data <= _T_655 @[axi4_to_ahb.scala 388:14]
|
wrbuf_data <= _T_655 @[axi4_to_ahb.scala 386:14]
|
||||||
node _T_656 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 391:27]
|
node _T_656 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 389:27]
|
||||||
node _T_657 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 391:60]
|
node _T_657 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 389:60]
|
||||||
reg _T_658 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_658 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_657 : @[Reg.scala 28:19]
|
when _T_657 : @[Reg.scala 28:19]
|
||||||
_T_658 <= _T_656 @[Reg.scala 28:23]
|
_T_658 <= _T_656 @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
wrbuf_byteen <= _T_658 @[axi4_to_ahb.scala 390:16]
|
wrbuf_byteen <= _T_658 @[axi4_to_ahb.scala 388:16]
|
||||||
node _T_659 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 394:27]
|
node _T_659 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 392:27]
|
||||||
node _T_660 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 394:60]
|
node _T_660 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 392:60]
|
||||||
reg _T_661 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_661 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_660 : @[Reg.scala 28:19]
|
when _T_660 : @[Reg.scala 28:19]
|
||||||
_T_661 <= _T_659 @[Reg.scala 28:23]
|
_T_661 <= _T_659 @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
last_bus_addr <= _T_661 @[axi4_to_ahb.scala 393:17]
|
last_bus_addr <= _T_661 @[axi4_to_ahb.scala 391:17]
|
||||||
node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 402:50]
|
node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 400:50]
|
||||||
reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_662 : @[Reg.scala 28:19]
|
when _T_662 : @[Reg.scala 28:19]
|
||||||
_T_663 <= buf_write_in @[Reg.scala 28:23]
|
_T_663 <= buf_write_in @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
buf_write <= _T_663 @[axi4_to_ahb.scala 401:13]
|
buf_write <= _T_663 @[axi4_to_ahb.scala 399:13]
|
||||||
node _T_664 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 405:25]
|
node _T_664 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 403:25]
|
||||||
node _T_665 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 405:60]
|
node _T_665 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 403:60]
|
||||||
reg _T_666 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_666 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_665 : @[Reg.scala 28:19]
|
when _T_665 : @[Reg.scala 28:19]
|
||||||
_T_666 <= _T_664 @[Reg.scala 28:23]
|
_T_666 <= _T_664 @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
buf_tag <= _T_666 @[axi4_to_ahb.scala 404:11]
|
buf_tag <= _T_666 @[axi4_to_ahb.scala 402:11]
|
||||||
node _T_667 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 408:33]
|
node _T_667 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 406:33]
|
||||||
node _T_668 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 408:52]
|
node _T_668 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 406:52]
|
||||||
node _T_669 = bits(_T_668, 0, 0) @[axi4_to_ahb.scala 408:69]
|
node _T_669 = bits(_T_668, 0, 0) @[axi4_to_ahb.scala 406:69]
|
||||||
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
|
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
|
||||||
rvclkhdr_4.clock <= clock
|
rvclkhdr_4.clock <= clock
|
||||||
rvclkhdr_4.reset <= reset
|
rvclkhdr_4.reset <= reset
|
||||||
|
|
@ -1295,30 +1294,30 @@ circuit axi4_to_ahb :
|
||||||
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||||||
reg _T_670 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
reg _T_670 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||||||
_T_670 <= _T_667 @[el2_lib.scala 514:16]
|
_T_670 <= _T_667 @[el2_lib.scala 514:16]
|
||||||
buf_addr <= _T_670 @[axi4_to_ahb.scala 408:12]
|
buf_addr <= _T_670 @[axi4_to_ahb.scala 406:12]
|
||||||
node _T_671 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 411:26]
|
node _T_671 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 409:26]
|
||||||
node _T_672 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 411:55]
|
node _T_672 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 409:55]
|
||||||
reg _T_673 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_673 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_672 : @[Reg.scala 28:19]
|
when _T_672 : @[Reg.scala 28:19]
|
||||||
_T_673 <= _T_671 @[Reg.scala 28:23]
|
_T_673 <= _T_671 @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
buf_size <= _T_673 @[axi4_to_ahb.scala 410:12]
|
buf_size <= _T_673 @[axi4_to_ahb.scala 408:12]
|
||||||
node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 414:52]
|
node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 412:52]
|
||||||
reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_674 : @[Reg.scala 28:19]
|
when _T_674 : @[Reg.scala 28:19]
|
||||||
_T_675 <= buf_aligned_in @[Reg.scala 28:23]
|
_T_675 <= buf_aligned_in @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
buf_aligned <= _T_675 @[axi4_to_ahb.scala 413:15]
|
buf_aligned <= _T_675 @[axi4_to_ahb.scala 411:15]
|
||||||
node _T_676 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 417:28]
|
node _T_676 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 415:28]
|
||||||
node _T_677 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 417:57]
|
node _T_677 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 415:57]
|
||||||
reg _T_678 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_678 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_677 : @[Reg.scala 28:19]
|
when _T_677 : @[Reg.scala 28:19]
|
||||||
_T_678 <= _T_676 @[Reg.scala 28:23]
|
_T_678 <= _T_676 @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
buf_byteen <= _T_678 @[axi4_to_ahb.scala 416:14]
|
buf_byteen <= _T_678 @[axi4_to_ahb.scala 414:14]
|
||||||
node _T_679 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 420:33]
|
node _T_679 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 418:33]
|
||||||
node _T_680 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 420:57]
|
node _T_680 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 418:57]
|
||||||
node _T_681 = bits(_T_680, 0, 0) @[axi4_to_ahb.scala 420:80]
|
node _T_681 = bits(_T_680, 0, 0) @[axi4_to_ahb.scala 418:80]
|
||||||
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23]
|
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23]
|
||||||
rvclkhdr_5.clock <= clock
|
rvclkhdr_5.clock <= clock
|
||||||
rvclkhdr_5.reset <= reset
|
rvclkhdr_5.reset <= reset
|
||||||
|
|
@ -1327,96 +1326,96 @@ circuit axi4_to_ahb :
|
||||||
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||||||
reg _T_682 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
reg _T_682 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||||||
_T_682 <= _T_679 @[el2_lib.scala 514:16]
|
_T_682 <= _T_679 @[el2_lib.scala 514:16]
|
||||||
buf_data <= _T_682 @[axi4_to_ahb.scala 420:12]
|
buf_data <= _T_682 @[axi4_to_ahb.scala 418:12]
|
||||||
node _T_683 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 423:50]
|
node _T_683 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 421:50]
|
||||||
reg _T_684 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_684 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_683 : @[Reg.scala 28:19]
|
when _T_683 : @[Reg.scala 28:19]
|
||||||
_T_684 <= buf_write @[Reg.scala 28:23]
|
_T_684 <= buf_write @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
slvbuf_write <= _T_684 @[axi4_to_ahb.scala 422:16]
|
slvbuf_write <= _T_684 @[axi4_to_ahb.scala 420:16]
|
||||||
node _T_685 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 426:22]
|
node _T_685 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 424:22]
|
||||||
node _T_686 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 426:60]
|
node _T_686 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 424:60]
|
||||||
reg _T_687 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_687 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_686 : @[Reg.scala 28:19]
|
when _T_686 : @[Reg.scala 28:19]
|
||||||
_T_687 <= _T_685 @[Reg.scala 28:23]
|
_T_687 <= _T_685 @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
slvbuf_tag <= _T_687 @[axi4_to_ahb.scala 425:14]
|
slvbuf_tag <= _T_687 @[axi4_to_ahb.scala 423:14]
|
||||||
node _T_688 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 429:59]
|
node _T_688 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 427:59]
|
||||||
reg _T_689 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_689 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_688 : @[Reg.scala 28:19]
|
when _T_688 : @[Reg.scala 28:19]
|
||||||
_T_689 <= slvbuf_error_in @[Reg.scala 28:23]
|
_T_689 <= slvbuf_error_in @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
slvbuf_error <= _T_689 @[axi4_to_ahb.scala 428:16]
|
slvbuf_error <= _T_689 @[axi4_to_ahb.scala 426:16]
|
||||||
node _T_690 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 433:32]
|
node _T_690 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 431:32]
|
||||||
node _T_691 = mux(_T_690, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 433:16]
|
node _T_691 = mux(_T_690, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 431:16]
|
||||||
node _T_692 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 433:52]
|
node _T_692 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 431:52]
|
||||||
node _T_693 = and(_T_691, _T_692) @[axi4_to_ahb.scala 433:50]
|
node _T_693 = and(_T_691, _T_692) @[axi4_to_ahb.scala 431:50]
|
||||||
reg _T_694 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 433:12]
|
reg _T_694 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 431:12]
|
||||||
_T_694 <= _T_693 @[axi4_to_ahb.scala 433:12]
|
_T_694 <= _T_693 @[axi4_to_ahb.scala 431:12]
|
||||||
cmd_doneQ <= _T_694 @[axi4_to_ahb.scala 432:13]
|
cmd_doneQ <= _T_694 @[axi4_to_ahb.scala 430:13]
|
||||||
node _T_695 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 437:31]
|
node _T_695 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 435:31]
|
||||||
node _T_696 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 437:70]
|
node _T_696 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 435:70]
|
||||||
reg _T_697 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
reg _T_697 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||||
when _T_696 : @[Reg.scala 28:19]
|
when _T_696 : @[Reg.scala 28:19]
|
||||||
_T_697 <= _T_695 @[Reg.scala 28:23]
|
_T_697 <= _T_695 @[Reg.scala 28:23]
|
||||||
skip @[Reg.scala 28:19]
|
skip @[Reg.scala 28:19]
|
||||||
buf_cmd_byte_ptrQ <= _T_697 @[axi4_to_ahb.scala 436:21]
|
buf_cmd_byte_ptrQ <= _T_697 @[axi4_to_ahb.scala 434:21]
|
||||||
reg _T_698 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 442:12]
|
reg _T_698 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 440:12]
|
||||||
_T_698 <= io.ahb_hready @[axi4_to_ahb.scala 442:12]
|
_T_698 <= io.ahb_hready @[axi4_to_ahb.scala 440:12]
|
||||||
ahb_hready_q <= _T_698 @[axi4_to_ahb.scala 441:16]
|
ahb_hready_q <= _T_698 @[axi4_to_ahb.scala 439:16]
|
||||||
node _T_699 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 445:26]
|
node _T_699 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 443:26]
|
||||||
reg _T_700 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 445:12]
|
reg _T_700 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 443:12]
|
||||||
_T_700 <= _T_699 @[axi4_to_ahb.scala 445:12]
|
_T_700 <= _T_699 @[axi4_to_ahb.scala 443:12]
|
||||||
ahb_htrans_q <= _T_700 @[axi4_to_ahb.scala 444:16]
|
ahb_htrans_q <= _T_700 @[axi4_to_ahb.scala 442:16]
|
||||||
reg _T_701 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 448:12]
|
reg _T_701 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 446:12]
|
||||||
_T_701 <= io.ahb_hwrite @[axi4_to_ahb.scala 448:12]
|
_T_701 <= io.ahb_hwrite @[axi4_to_ahb.scala 446:12]
|
||||||
ahb_hwrite_q <= _T_701 @[axi4_to_ahb.scala 447:16]
|
ahb_hwrite_q <= _T_701 @[axi4_to_ahb.scala 445:16]
|
||||||
reg _T_702 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 451:12]
|
reg _T_702 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 449:12]
|
||||||
_T_702 <= io.ahb_hresp @[axi4_to_ahb.scala 451:12]
|
_T_702 <= io.ahb_hresp @[axi4_to_ahb.scala 449:12]
|
||||||
ahb_hresp_q <= _T_702 @[axi4_to_ahb.scala 450:15]
|
ahb_hresp_q <= _T_702 @[axi4_to_ahb.scala 448:15]
|
||||||
node _T_703 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 454:26]
|
node _T_703 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 452:26]
|
||||||
reg _T_704 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 454:12]
|
reg _T_704 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 452:12]
|
||||||
_T_704 <= _T_703 @[axi4_to_ahb.scala 454:12]
|
_T_704 <= _T_703 @[axi4_to_ahb.scala 452:12]
|
||||||
ahb_hrdata_q <= _T_704 @[axi4_to_ahb.scala 453:16]
|
ahb_hrdata_q <= _T_704 @[axi4_to_ahb.scala 451:16]
|
||||||
node _T_705 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 457:43]
|
node _T_705 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 455:43]
|
||||||
node _T_706 = or(_T_705, io.clk_override) @[axi4_to_ahb.scala 457:58]
|
node _T_706 = or(_T_705, io.clk_override) @[axi4_to_ahb.scala 455:58]
|
||||||
node _T_707 = and(io.bus_clk_en, _T_706) @[axi4_to_ahb.scala 457:30]
|
node _T_707 = and(io.bus_clk_en, _T_706) @[axi4_to_ahb.scala 455:30]
|
||||||
buf_clken <= _T_707 @[axi4_to_ahb.scala 457:13]
|
buf_clken <= _T_707 @[axi4_to_ahb.scala 455:13]
|
||||||
node _T_708 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 458:69]
|
node _T_708 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 456:69]
|
||||||
node _T_709 = and(io.ahb_hready, _T_708) @[axi4_to_ahb.scala 458:54]
|
node _T_709 = and(io.ahb_hready, _T_708) @[axi4_to_ahb.scala 456:54]
|
||||||
node _T_710 = or(_T_709, io.clk_override) @[axi4_to_ahb.scala 458:74]
|
node _T_710 = or(_T_709, io.clk_override) @[axi4_to_ahb.scala 456:74]
|
||||||
node _T_711 = and(io.bus_clk_en, _T_710) @[axi4_to_ahb.scala 458:36]
|
node _T_711 = and(io.bus_clk_en, _T_710) @[axi4_to_ahb.scala 456:36]
|
||||||
ahbm_addr_clken <= _T_711 @[axi4_to_ahb.scala 458:19]
|
ahbm_addr_clken <= _T_711 @[axi4_to_ahb.scala 456:19]
|
||||||
node _T_712 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 459:50]
|
node _T_712 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 457:50]
|
||||||
node _T_713 = or(_T_712, io.clk_override) @[axi4_to_ahb.scala 459:60]
|
node _T_713 = or(_T_712, io.clk_override) @[axi4_to_ahb.scala 457:60]
|
||||||
node _T_714 = and(io.bus_clk_en, _T_713) @[axi4_to_ahb.scala 459:36]
|
node _T_714 = and(io.bus_clk_en, _T_713) @[axi4_to_ahb.scala 457:36]
|
||||||
ahbm_data_clken <= _T_714 @[axi4_to_ahb.scala 459:19]
|
ahbm_data_clken <= _T_714 @[axi4_to_ahb.scala 457:19]
|
||||||
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22]
|
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22]
|
||||||
rvclkhdr_6.clock <= clock
|
rvclkhdr_6.clock <= clock
|
||||||
rvclkhdr_6.reset <= reset
|
rvclkhdr_6.reset <= reset
|
||||||
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17]
|
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17]
|
||||||
rvclkhdr_6.io.en <= buf_clken @[el2_lib.scala 485:16]
|
rvclkhdr_6.io.en <= buf_clken @[el2_lib.scala 485:16]
|
||||||
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
||||||
buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 462:12]
|
buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 460:12]
|
||||||
inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22]
|
inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22]
|
||||||
rvclkhdr_7.clock <= clock
|
rvclkhdr_7.clock <= clock
|
||||||
rvclkhdr_7.reset <= reset
|
rvclkhdr_7.reset <= reset
|
||||||
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17]
|
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17]
|
||||||
rvclkhdr_7.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
|
rvclkhdr_7.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
|
||||||
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
||||||
ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 463:12]
|
ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 461:12]
|
||||||
inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22]
|
inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22]
|
||||||
rvclkhdr_8.clock <= clock
|
rvclkhdr_8.clock <= clock
|
||||||
rvclkhdr_8.reset <= reset
|
rvclkhdr_8.reset <= reset
|
||||||
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17]
|
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17]
|
||||||
rvclkhdr_8.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16]
|
rvclkhdr_8.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16]
|
||||||
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
||||||
ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 464:17]
|
ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 462:17]
|
||||||
inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22]
|
inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22]
|
||||||
rvclkhdr_9.clock <= clock
|
rvclkhdr_9.clock <= clock
|
||||||
rvclkhdr_9.reset <= reset
|
rvclkhdr_9.reset <= reset
|
||||||
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17]
|
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17]
|
||||||
rvclkhdr_9.io.en <= ahbm_data_clken @[el2_lib.scala 485:16]
|
rvclkhdr_9.io.en <= ahbm_data_clken @[el2_lib.scala 485:16]
|
||||||
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
|
||||||
ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 465:17]
|
ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 463:17]
|
||||||
|
|
||||||
|
|
|
||||||
166
axi4_to_ahb.v
166
axi4_to_ahb.v
|
|
@ -132,25 +132,25 @@ module axi4_to_ahb(
|
||||||
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22]
|
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22]
|
||||||
wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22]
|
wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22]
|
||||||
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22]
|
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22]
|
||||||
wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 62:22 axi4_to_ahb.scala 463:12]
|
wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 62:22 axi4_to_ahb.scala 461:12]
|
||||||
reg [2:0] buf_state; // @[axi4_to_ahb.scala 68:45]
|
reg [2:0] buf_state; // @[axi4_to_ahb.scala 68:45]
|
||||||
wire _T_47 = 3'h0 == buf_state; // @[Conditional.scala 37:30]
|
wire _T_47 = 3'h0 == buf_state; // @[Conditional.scala 37:30]
|
||||||
wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 88:21 axi4_to_ahb.scala 220:11]
|
wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 88:21 axi4_to_ahb.scala 220:11]
|
||||||
reg wrbuf_vld; // @[axi4_to_ahb.scala 381:48]
|
reg wrbuf_vld; // @[axi4_to_ahb.scala 379:48]
|
||||||
reg wrbuf_data_vld; // @[axi4_to_ahb.scala 382:48]
|
reg wrbuf_data_vld; // @[axi4_to_ahb.scala 380:48]
|
||||||
wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 197:27]
|
wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 197:27]
|
||||||
wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 198:30]
|
wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 198:30]
|
||||||
wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30]
|
wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30]
|
||||||
reg ahb_hready_q; // @[axi4_to_ahb.scala 442:12]
|
reg ahb_hready_q; // @[axi4_to_ahb.scala 440:12]
|
||||||
reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 445:12]
|
reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 443:12]
|
||||||
wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 260:58]
|
wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 260:58]
|
||||||
wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 260:36]
|
wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 260:36]
|
||||||
wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 63:27 axi4_to_ahb.scala 464:17]
|
wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 63:27 axi4_to_ahb.scala 462:17]
|
||||||
reg ahb_hwrite_q; // @[axi4_to_ahb.scala 448:12]
|
reg ahb_hwrite_q; // @[axi4_to_ahb.scala 446:12]
|
||||||
wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 260:72]
|
wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 260:72]
|
||||||
wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 260:70]
|
wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 260:70]
|
||||||
wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
|
wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
|
||||||
reg ahb_hresp_q; // @[axi4_to_ahb.scala 451:12]
|
reg ahb_hresp_q; // @[axi4_to_ahb.scala 449:12]
|
||||||
wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 274:37]
|
wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 274:37]
|
||||||
wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
|
wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
|
||||||
wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
|
wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
|
||||||
|
|
@ -165,7 +165,7 @@ module axi4_to_ahb(
|
||||||
wire _GEN_79 = _T_134 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
|
wire _GEN_79 = _T_134 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
|
||||||
wire _GEN_95 = _T_99 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
|
wire _GEN_95 = _T_99 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
|
||||||
wire trxn_done = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
|
wire trxn_done = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
|
||||||
reg cmd_doneQ; // @[axi4_to_ahb.scala 433:12]
|
reg cmd_doneQ; // @[axi4_to_ahb.scala 431:12]
|
||||||
wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 316:34]
|
wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 316:34]
|
||||||
wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 316:50]
|
wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 316:50]
|
||||||
wire _T_441 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
|
wire _T_441 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
|
||||||
|
|
@ -242,23 +242,23 @@ module axi4_to_ahb(
|
||||||
wire _GEN_94 = _T_99 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
|
wire _GEN_94 = _T_99 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
|
||||||
wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
|
wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
|
||||||
wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 207:32]
|
wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 207:32]
|
||||||
wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 462:12]
|
wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 460:12]
|
||||||
reg slvbuf_write; // @[Reg.scala 27:20]
|
reg slvbuf_write; // @[Reg.scala 27:20]
|
||||||
wire [1:0] _T_597 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 364:23]
|
wire [1:0] _T_597 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 362:23]
|
||||||
reg slvbuf_error; // @[Reg.scala 27:20]
|
reg slvbuf_error; // @[Reg.scala 27:20]
|
||||||
wire [1:0] _T_599 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
wire [1:0] _T_599 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [1:0] _T_600 = _T_599 & 2'h2; // @[axi4_to_ahb.scala 364:88]
|
wire [1:0] _T_600 = _T_599 & 2'h2; // @[axi4_to_ahb.scala 362:88]
|
||||||
wire [3:0] slave_opc = {_T_597,_T_600}; // @[Cat.scala 29:58]
|
wire [3:0] slave_opc = {_T_597,_T_600}; // @[Cat.scala 29:58]
|
||||||
wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 208:49]
|
wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 208:49]
|
||||||
reg slvbuf_tag; // @[Reg.scala 27:20]
|
reg slvbuf_tag; // @[Reg.scala 27:20]
|
||||||
wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 211:65]
|
wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 211:65]
|
||||||
reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
|
reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
|
||||||
wire [63:0] _T_604 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
|
wire [63:0] _T_604 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
|
||||||
wire _T_605 = buf_state == 3'h5; // @[axi4_to_ahb.scala 365:91]
|
wire _T_605 = buf_state == 3'h5; // @[axi4_to_ahb.scala 363:91]
|
||||||
reg [63:0] buf_data; // @[el2_lib.scala 514:16]
|
reg [63:0] buf_data; // @[el2_lib.scala 514:16]
|
||||||
wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 465:17]
|
wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 463:17]
|
||||||
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 454:12]
|
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 452:12]
|
||||||
wire [63:0] _T_608 = _T_605 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 365:79]
|
wire [63:0] _T_608 = _T_605 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 363:79]
|
||||||
wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 218:56]
|
wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 218:56]
|
||||||
wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 218:91]
|
wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 218:91]
|
||||||
wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 218:74]
|
wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 218:74]
|
||||||
|
|
@ -406,29 +406,29 @@ module axi4_to_ahb(
|
||||||
wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58]
|
wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58]
|
||||||
wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
|
wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
|
||||||
wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
|
wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
|
||||||
wire _T_536 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 350:24]
|
wire _T_536 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 348:24]
|
||||||
wire _T_537 = _T_101 | _T_536; // @[axi4_to_ahb.scala 349:48]
|
wire _T_537 = _T_101 | _T_536; // @[axi4_to_ahb.scala 347:48]
|
||||||
wire _T_539 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 350:54]
|
wire _T_539 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 348:54]
|
||||||
wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 350:33]
|
wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 348:33]
|
||||||
wire _T_542 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 350:93]
|
wire _T_542 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 348:93]
|
||||||
wire _T_543 = _T_540 | _T_542; // @[axi4_to_ahb.scala 350:72]
|
wire _T_543 = _T_540 | _T_542; // @[axi4_to_ahb.scala 348:72]
|
||||||
wire _T_545 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 351:25]
|
wire _T_545 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 349:25]
|
||||||
wire _T_547 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 351:62]
|
wire _T_547 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 349:62]
|
||||||
wire _T_549 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 351:97]
|
wire _T_549 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 349:97]
|
||||||
wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 351:74]
|
wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 349:74]
|
||||||
wire _T_552 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 351:132]
|
wire _T_552 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 349:132]
|
||||||
wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 351:109]
|
wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 349:109]
|
||||||
wire _T_555 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 351:168]
|
wire _T_555 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 349:168]
|
||||||
wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 351:145]
|
wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 349:145]
|
||||||
wire _T_558 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 352:28]
|
wire _T_558 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 350:28]
|
||||||
wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 351:181]
|
wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 349:181]
|
||||||
wire _T_561 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 352:63]
|
wire _T_561 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 350:63]
|
||||||
wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 352:40]
|
wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 350:40]
|
||||||
wire _T_564 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 352:99]
|
wire _T_564 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 350:99]
|
||||||
wire _T_565 = _T_562 | _T_564; // @[axi4_to_ahb.scala 352:76]
|
wire _T_565 = _T_562 | _T_564; // @[axi4_to_ahb.scala 350:76]
|
||||||
wire _T_566 = _T_545 & _T_565; // @[axi4_to_ahb.scala 351:38]
|
wire _T_566 = _T_545 & _T_565; // @[axi4_to_ahb.scala 349:38]
|
||||||
wire buf_aligned_in = _T_543 | _T_566; // @[axi4_to_ahb.scala 350:106]
|
wire buf_aligned_in = _T_543 | _T_566; // @[axi4_to_ahb.scala 348:106]
|
||||||
wire _T_445 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 344:60]
|
wire _T_445 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 342:60]
|
||||||
wire [2:0] _T_462 = _T_549 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
wire [2:0] _T_462 = _T_549 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [2:0] _T_463 = 3'h2 & _T_462; // @[axi4_to_ahb.scala 174:15]
|
wire [2:0] _T_463 = 3'h2 & _T_462; // @[axi4_to_ahb.scala 174:15]
|
||||||
wire _T_469 = _T_561 | _T_547; // @[axi4_to_ahb.scala 175:56]
|
wire _T_469 = _T_561 | _T_547; // @[axi4_to_ahb.scala 175:56]
|
||||||
|
|
@ -438,10 +438,10 @@ module axi4_to_ahb(
|
||||||
wire [2:0] _T_477 = _T_555 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
wire [2:0] _T_477 = _T_555 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [2:0] _T_478 = 3'h6 & _T_477; // @[axi4_to_ahb.scala 176:17]
|
wire [2:0] _T_478 = 3'h6 & _T_477; // @[axi4_to_ahb.scala 176:17]
|
||||||
wire [2:0] _T_479 = _T_473 | _T_478; // @[axi4_to_ahb.scala 175:96]
|
wire [2:0] _T_479 = _T_473 | _T_478; // @[axi4_to_ahb.scala 175:96]
|
||||||
wire [2:0] _T_486 = _T_445 ? _T_479 : master_addr[2:0]; // @[axi4_to_ahb.scala 344:43]
|
wire [2:0] _T_486 = _T_445 ? _T_479 : master_addr[2:0]; // @[axi4_to_ahb.scala 342:43]
|
||||||
wire _T_490 = buf_state == 3'h3; // @[axi4_to_ahb.scala 347:33]
|
wire _T_490 = buf_state == 3'h3; // @[axi4_to_ahb.scala 345:33]
|
||||||
wire _T_496 = buf_aligned_in & _T_545; // @[axi4_to_ahb.scala 348:38]
|
wire _T_496 = buf_aligned_in & _T_545; // @[axi4_to_ahb.scala 346:38]
|
||||||
wire _T_499 = _T_496 & _T_49; // @[axi4_to_ahb.scala 348:71]
|
wire _T_499 = _T_496 & _T_49; // @[axi4_to_ahb.scala 346:71]
|
||||||
wire [1:0] _T_505 = _T_564 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
wire [1:0] _T_505 = _T_564 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||||
wire _T_511 = _T_561 | _T_558; // @[axi4_to_ahb.scala 167:55]
|
wire _T_511 = _T_561 | _T_558; // @[axi4_to_ahb.scala 167:55]
|
||||||
wire [1:0] _T_513 = _T_511 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
wire [1:0] _T_513 = _T_511 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||||
|
|
@ -453,45 +453,45 @@ module axi4_to_ahb(
|
||||||
wire [1:0] _T_528 = _T_526 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
wire [1:0] _T_528 = _T_526 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [1:0] _T_529 = 2'h1 & _T_528; // @[axi4_to_ahb.scala 168:21]
|
wire [1:0] _T_529 = 2'h1 & _T_528; // @[axi4_to_ahb.scala 168:21]
|
||||||
wire [1:0] _T_530 = _T_515 | _T_529; // @[axi4_to_ahb.scala 167:93]
|
wire [1:0] _T_530 = _T_515 | _T_529; // @[axi4_to_ahb.scala 167:93]
|
||||||
wire [1:0] _T_532 = _T_499 ? _T_530 : master_size[1:0]; // @[axi4_to_ahb.scala 348:21]
|
wire [1:0] _T_532 = _T_499 ? _T_530 : master_size[1:0]; // @[axi4_to_ahb.scala 346:21]
|
||||||
wire [31:0] _T_571 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
|
wire [31:0] _T_571 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
|
||||||
wire [31:0] _T_574 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
|
wire [31:0] _T_574 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
|
||||||
wire [1:0] _T_578 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
wire [1:0] _T_578 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||||
wire [2:0] buf_size_in = {{1'd0}, _T_532}; // @[axi4_to_ahb.scala 348:15]
|
wire [2:0] buf_size_in = {{1'd0}, _T_532}; // @[axi4_to_ahb.scala 346:15]
|
||||||
wire [1:0] _T_580 = _T_578 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 355:77]
|
wire [1:0] _T_580 = _T_578 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 353:77]
|
||||||
wire [2:0] _T_581 = {1'h0,_T_580}; // @[Cat.scala 29:58]
|
wire [2:0] _T_581 = {1'h0,_T_580}; // @[Cat.scala 29:58]
|
||||||
wire [1:0] _T_583 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
wire [1:0] _T_583 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||||
reg [1:0] buf_size; // @[Reg.scala 27:20]
|
reg [1:0] buf_size; // @[Reg.scala 27:20]
|
||||||
wire [1:0] _T_585 = _T_583 & buf_size; // @[axi4_to_ahb.scala 355:134]
|
wire [1:0] _T_585 = _T_583 & buf_size; // @[axi4_to_ahb.scala 353:134]
|
||||||
wire [2:0] _T_586 = {1'h0,_T_585}; // @[Cat.scala 29:58]
|
wire [2:0] _T_586 = {1'h0,_T_585}; // @[Cat.scala 29:58]
|
||||||
wire _T_589 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 359:33]
|
wire _T_589 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 357:33]
|
||||||
wire [1:0] _T_590 = {1'h1,_T_589}; // @[Cat.scala 29:58]
|
wire [1:0] _T_590 = {1'h1,_T_589}; // @[Cat.scala 29:58]
|
||||||
reg buf_write; // @[Reg.scala 27:20]
|
reg buf_write; // @[Reg.scala 27:20]
|
||||||
wire _T_612 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 368:40]
|
wire _T_612 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 366:40]
|
||||||
wire _T_613 = _T_612 & io_ahb_hready; // @[axi4_to_ahb.scala 368:52]
|
wire _T_613 = _T_612 & io_ahb_hready; // @[axi4_to_ahb.scala 366:52]
|
||||||
wire last_addr_en = _T_613 & io_ahb_hwrite; // @[axi4_to_ahb.scala 368:68]
|
wire last_addr_en = _T_613 & io_ahb_hwrite; // @[axi4_to_ahb.scala 366:68]
|
||||||
wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 370:47]
|
wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 368:47]
|
||||||
wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 371:50]
|
wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 369:50]
|
||||||
wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 372:49]
|
wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 370:49]
|
||||||
wire _T_623 = ~wrbuf_en; // @[axi4_to_ahb.scala 373:33]
|
wire _T_623 = ~wrbuf_en; // @[axi4_to_ahb.scala 371:33]
|
||||||
wire wrbuf_rst = wrbuf_cmd_sent & _T_623; // @[axi4_to_ahb.scala 373:31]
|
wire wrbuf_rst = wrbuf_cmd_sent & _T_623; // @[axi4_to_ahb.scala 371:31]
|
||||||
wire _T_625 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 375:35]
|
wire _T_625 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 373:35]
|
||||||
wire _T_626 = wrbuf_vld & _T_625; // @[axi4_to_ahb.scala 375:33]
|
wire _T_626 = wrbuf_vld & _T_625; // @[axi4_to_ahb.scala 373:33]
|
||||||
wire _T_627 = ~_T_626; // @[axi4_to_ahb.scala 375:21]
|
wire _T_627 = ~_T_626; // @[axi4_to_ahb.scala 373:21]
|
||||||
wire _T_630 = wrbuf_data_vld & _T_625; // @[axi4_to_ahb.scala 376:37]
|
wire _T_630 = wrbuf_data_vld & _T_625; // @[axi4_to_ahb.scala 374:37]
|
||||||
wire _T_631 = ~_T_630; // @[axi4_to_ahb.scala 376:20]
|
wire _T_631 = ~_T_630; // @[axi4_to_ahb.scala 374:20]
|
||||||
wire _T_634 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 377:21]
|
wire _T_634 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 375:21]
|
||||||
wire _T_637 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 381:52]
|
wire _T_637 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 379:52]
|
||||||
wire _T_638 = ~wrbuf_rst; // @[axi4_to_ahb.scala 381:88]
|
wire _T_638 = ~wrbuf_rst; // @[axi4_to_ahb.scala 379:88]
|
||||||
wire _T_642 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 382:52]
|
wire _T_642 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 380:52]
|
||||||
reg buf_tag; // @[Reg.scala 27:20]
|
reg buf_tag; // @[Reg.scala 27:20]
|
||||||
wire _T_692 = ~slave_valid_pre; // @[axi4_to_ahb.scala 433:52]
|
wire _T_692 = ~slave_valid_pre; // @[axi4_to_ahb.scala 431:52]
|
||||||
wire _T_705 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 457:43]
|
wire _T_705 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 455:43]
|
||||||
wire _T_706 = _T_705 | io_clk_override; // @[axi4_to_ahb.scala 457:58]
|
wire _T_706 = _T_705 | io_clk_override; // @[axi4_to_ahb.scala 455:58]
|
||||||
wire _T_709 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 458:54]
|
wire _T_709 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 456:54]
|
||||||
wire _T_710 = _T_709 | io_clk_override; // @[axi4_to_ahb.scala 458:74]
|
wire _T_710 = _T_709 | io_clk_override; // @[axi4_to_ahb.scala 456:74]
|
||||||
wire _T_712 = buf_state != 3'h0; // @[axi4_to_ahb.scala 459:50]
|
wire _T_712 = buf_state != 3'h0; // @[axi4_to_ahb.scala 457:50]
|
||||||
wire _T_713 = _T_712 | io_clk_override; // @[axi4_to_ahb.scala 459:60]
|
wire _T_713 = _T_712 | io_clk_override; // @[axi4_to_ahb.scala 457:60]
|
||||||
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
||||||
.io_l1clk(rvclkhdr_io_l1clk),
|
.io_l1clk(rvclkhdr_io_l1clk),
|
||||||
.io_clk(rvclkhdr_io_clk),
|
.io_clk(rvclkhdr_io_clk),
|
||||||
|
|
@ -552,25 +552,25 @@ module axi4_to_ahb(
|
||||||
.io_en(rvclkhdr_9_io_en),
|
.io_en(rvclkhdr_9_io_en),
|
||||||
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
||||||
);
|
);
|
||||||
assign io_axi_awready = _T_627 & master_ready; // @[axi4_to_ahb.scala 375:18]
|
assign io_axi_awready = _T_627 & master_ready; // @[axi4_to_ahb.scala 373:18]
|
||||||
assign io_axi_wready = _T_631 & master_ready; // @[axi4_to_ahb.scala 376:17]
|
assign io_axi_wready = _T_631 & master_ready; // @[axi4_to_ahb.scala 374:17]
|
||||||
assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 207:17]
|
assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 207:17]
|
||||||
assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 208:16]
|
assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 208:16]
|
||||||
assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 209:14]
|
assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 209:14]
|
||||||
assign io_axi_arready = _T_634 & master_ready; // @[axi4_to_ahb.scala 377:18]
|
assign io_axi_arready = _T_634 & master_ready; // @[axi4_to_ahb.scala 375:18]
|
||||||
assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 211:17]
|
assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 211:17]
|
||||||
assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 213:14]
|
assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 213:14]
|
||||||
assign io_axi_rdata = slvbuf_error ? _T_604 : _T_608; // @[axi4_to_ahb.scala 214:16]
|
assign io_axi_rdata = slvbuf_error ? _T_604 : _T_608; // @[axi4_to_ahb.scala 214:16]
|
||||||
assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 212:16]
|
assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 212:16]
|
||||||
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 378:16]
|
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 376:16]
|
||||||
assign io_ahb_haddr = bypass_en ? _T_571 : _T_574; // @[axi4_to_ahb.scala 354:16]
|
assign io_ahb_haddr = bypass_en ? _T_571 : _T_574; // @[axi4_to_ahb.scala 352:16]
|
||||||
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 357:17]
|
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 355:17]
|
||||||
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 358:20]
|
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 356:20]
|
||||||
assign io_ahb_hprot = {{2'd0}, _T_590}; // @[axi4_to_ahb.scala 359:16]
|
assign io_ahb_hprot = {{2'd0}, _T_590}; // @[axi4_to_ahb.scala 357:16]
|
||||||
assign io_ahb_hsize = bypass_en ? _T_581 : _T_586; // @[axi4_to_ahb.scala 355:16]
|
assign io_ahb_hsize = bypass_en ? _T_581 : _T_586; // @[axi4_to_ahb.scala 353:16]
|
||||||
assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 224:17 axi4_to_ahb.scala 255:21 axi4_to_ahb.scala 267:21 axi4_to_ahb.scala 282:21 axi4_to_ahb.scala 292:21 axi4_to_ahb.scala 312:21 axi4_to_ahb.scala 326:21]
|
assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 224:17 axi4_to_ahb.scala 255:21 axi4_to_ahb.scala 267:21 axi4_to_ahb.scala 282:21 axi4_to_ahb.scala 292:21 axi4_to_ahb.scala 312:21 axi4_to_ahb.scala 326:21]
|
||||||
assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 360:17]
|
assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 358:17]
|
||||||
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 361:17]
|
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 359:17]
|
||||||
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
||||||
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
|
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
|
||||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
||||||
|
|
|
||||||
|
|
@ -57,15 +57,15 @@ class axi4_to_ahb_IO extends Bundle with Config {
|
||||||
|
|
||||||
class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config {
|
class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config {
|
||||||
val io = IO(new axi4_to_ahb_IO)
|
val io = IO(new axi4_to_ahb_IO)
|
||||||
val buf_rst = WireInit(Bool(), init = false.B)
|
val buf_rst = WireInit(0.U(3.W))
|
||||||
val buf_state_en = WireInit(Bool(), init = false.B)
|
val buf_state_en = WireInit(Bool(), init = false.B)
|
||||||
val ahbm_clk = Wire(Clock())
|
val ahbm_clk = Wire(Clock())
|
||||||
val ahbm_addr_clk = Wire(Clock())
|
val ahbm_addr_clk = Wire(Clock())
|
||||||
val ahbm_data_clk = Wire(Clock())
|
val ahbm_data_clk = Wire(Clock())
|
||||||
val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8)
|
val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8)
|
||||||
val buf_state = WireInit(idle)
|
val buf_state = WireInit(0.U(3.W))
|
||||||
val buf_nxtstate = WireInit(idle)
|
val buf_nxtstate = WireInit(0.U(3.W))
|
||||||
buf_state := withClock(ahbm_clk) { RegNext(Mux((buf_state_en & !buf_rst).asBool ,buf_nxtstate,buf_state) , 0.U) }
|
buf_state := withClock(ahbm_clk) { RegNext((Mux(buf_state_en.asBool() ,buf_nxtstate,buf_state) & ~buf_rst), 0.U) }
|
||||||
//logic signals
|
//logic signals
|
||||||
val slave_valid = WireInit(Bool(), init = false.B)
|
val slave_valid = WireInit(Bool(), init = false.B)
|
||||||
val slave_ready = WireInit(Bool(), init = false.B)
|
val slave_ready = WireInit(Bool(), init = false.B)
|
||||||
|
|
@ -338,8 +338,6 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
||||||
slave_valid_pre := true.B
|
slave_valid_pre := true.B
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
buf_rst := false.B
|
|
||||||
cmd_done_rst := slave_valid_pre
|
cmd_done_rst := slave_valid_pre
|
||||||
buf_addr_in := Cat(master_addr(31,3),Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0)))
|
buf_addr_in := Cat(master_addr(31,3),Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0)))
|
||||||
buf_tag_in := master_tag(TAG - 1, 0)
|
buf_tag_in := master_tag(TAG - 1, 0)
|
||||||
|
|
|
||||||
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Reference in New Issue