Hard-coded values

el2_ifu_iccm_mem.fir

@@ -511,76 +511,86 @@ circuit el2_ifu_iccm_mem :
     node _T_374 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48]
     reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 103:34]
     iccm_rd_addr_hi_q <= _T_374 @[el2_ifu_iccm_mem.scala 103:34]
-    node _T_375 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:86]
+    node _T_375 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 105:86]
-    node _T_376 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
+    node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:104]
-    node _T_377 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:86]
+    node _T_377 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 105:151]
-    node _T_378 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
+    node _T_378 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 105:86]
-    node _T_379 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:86]
+    node _T_379 = eq(_T_378, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:104]
-    node _T_380 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
+    node _T_380 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 105:151]
-    node _T_381 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:86]
+    node _T_381 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 105:86]
-    node _T_382 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
+    node _T_382 = eq(_T_381, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:104]
-    node _T_383 = mux(_T_375, _T_376, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_383 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 105:151]
-    node _T_384 = mux(_T_377, _T_378, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_384 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 105:86]
-    node _T_385 = mux(_T_379, _T_380, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_385 = eq(_T_384, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:104]
-    node _T_386 = mux(_T_381, _T_382, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_386 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 105:151]
-    node _T_387 = or(_T_383, _T_384) @[Mux.scala 27:72]
+    node _T_387 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_388 = or(_T_387, _T_385) @[Mux.scala 27:72]
+    node _T_388 = mux(_T_379, _T_380, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_389 = or(_T_388, _T_386) @[Mux.scala 27:72]
+    node _T_389 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72]
-    wire _T_390 : UInt<32> @[Mux.scala 27:72]
+    node _T_390 = mux(_T_385, _T_386, UInt<1>("h00")) @[Mux.scala 27:72]
-    _T_390 <= _T_389 @[Mux.scala 27:72]
+    node _T_391 = or(_T_387, _T_388) @[Mux.scala 27:72]
-    node _T_391 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
+    node _T_392 = or(_T_391, _T_389) @[Mux.scala 27:72]
-    node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77]
+    node _T_393 = or(_T_392, _T_390) @[Mux.scala 27:72]
-    node _T_393 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
+    wire _T_394 : UInt<32> @[Mux.scala 27:72]
-    node _T_394 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
+    _T_394 <= _T_393 @[Mux.scala 27:72]
-    node _T_395 = eq(_T_394, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77]
+    node _T_395 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
-    node _T_396 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
+    node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77]
-    node _T_397 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
+    node _T_397 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
-    node _T_398 = eq(_T_397, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77]
+    node _T_398 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
-    node _T_399 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
+    node _T_399 = eq(_T_398, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77]
-    node _T_400 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
+    node _T_400 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
-    node _T_401 = eq(_T_400, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77]
+    node _T_401 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
-    node _T_402 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
+    node _T_402 = eq(_T_401, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77]
-    node _T_403 = mux(_T_392, _T_393, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_403 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
-    node _T_404 = mux(_T_395, _T_396, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_404 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 106:59]
-    node _T_405 = mux(_T_398, _T_399, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_405 = eq(_T_404, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77]
-    node _T_406 = mux(_T_401, _T_402, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_406 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
-    node _T_407 = or(_T_403, _T_404) @[Mux.scala 27:72]
+    node _T_407 = mux(_T_396, _T_397, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_408 = or(_T_407, _T_405) @[Mux.scala 27:72]
+    node _T_408 = mux(_T_399, _T_400, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_409 = or(_T_408, _T_406) @[Mux.scala 27:72]
+    node _T_409 = mux(_T_402, _T_403, UInt<1>("h00")) @[Mux.scala 27:72]
-    wire _T_410 : UInt<32> @[Mux.scala 27:72]
+    node _T_410 = mux(_T_405, _T_406, UInt<1>("h00")) @[Mux.scala 27:72]
-    _T_410 <= _T_409 @[Mux.scala 27:72]
+    node _T_411 = or(_T_407, _T_408) @[Mux.scala 27:72]
-    node iccm_rd_data_pre = cat(_T_390, _T_410) @[Cat.scala 29:58]
+    node _T_412 = or(_T_411, _T_409) @[Mux.scala 27:72]
-    node _T_411 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 108:43]
+    node _T_413 = or(_T_412, _T_410) @[Mux.scala 27:72]
-    node _T_412 = bits(_T_411, 0, 0) @[el2_ifu_iccm_mem.scala 108:53]
+    wire _T_414 : UInt<32> @[Mux.scala 27:72]
-    node _T_413 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+    _T_414 <= _T_413 @[Mux.scala 27:72]
-    node _T_414 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 108:89]
+    node iccm_rd_data_pre = cat(_T_394, _T_414) @[Cat.scala 29:58]
-    node _T_415 = cat(_T_413, _T_414) @[Cat.scala 29:58]
+    node _T_415 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 108:43]
-    node _T_416 = mux(_T_412, _T_415, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 108:25]
+    node _T_416 = bits(_T_415, 0, 0) @[el2_ifu_iccm_mem.scala 108:53]
-    io.iccm_rd_data <= _T_416 @[el2_ifu_iccm_mem.scala 108:19]
+    node _T_417 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
-    node _T_417 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:85]
+    node _T_418 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 108:89]
-    node _T_418 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:85]
+    node _T_419 = cat(_T_417, _T_418) @[Cat.scala 29:58]
-    node _T_419 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:85]
+    node _T_420 = mux(_T_416, _T_419, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 108:25]
-    node _T_420 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:85]
+    io.iccm_rd_data <= _T_420 @[el2_ifu_iccm_mem.scala 108:19]
-    node _T_421 = mux(_T_417, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_421 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:85]
-    node _T_422 = mux(_T_418, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_422 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:85]
-    node _T_423 = mux(_T_419, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_423 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:85]
-    node _T_424 = mux(_T_420, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_424 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:85]
-    node _T_425 = or(_T_421, _T_422) @[Mux.scala 27:72]
+    node _T_425 = mux(_T_421, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72]
+    node _T_426 = mux(_T_422, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_427 = or(_T_426, _T_424) @[Mux.scala 27:72]
+    node _T_427 = mux(_T_423, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
-    wire _T_428 : UInt<39> @[Mux.scala 27:72]
+    node _T_428 = mux(_T_424, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
-    _T_428 <= _T_427 @[Mux.scala 27:72]
+    node _T_429 = or(_T_425, _T_426) @[Mux.scala 27:72]
-    node _T_429 = bits(iccm_rd_addr_lo_q, 1, 1) @[el2_ifu_iccm_mem.scala 110:49]
+    node _T_430 = or(_T_429, _T_427) @[Mux.scala 27:72]
-    node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:31]
+    node _T_431 = or(_T_430, _T_428) @[Mux.scala 27:72]
-    node _T_431 = eq(_T_430, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:65]
+    wire _T_432 : UInt<39> @[Mux.scala 27:72]
-    node _T_432 = bits(iccm_rd_addr_lo_q, 1, 1) @[el2_ifu_iccm_mem.scala 110:49]
+    _T_432 <= _T_431 @[Mux.scala 27:72]
-    node _T_433 = eq(_T_432, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:31]
+    node _T_433 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
-    node _T_434 = eq(_T_433, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:65]
+    node _T_434 = eq(_T_433, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:79]
-    node _T_435 = mux(_T_431, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_435 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
-    node _T_436 = mux(_T_434, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_436 = eq(_T_435, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:79]
-    node _T_437 = or(_T_435, _T_436) @[Mux.scala 27:72]
+    node _T_437 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
-    wire _T_438 : UInt<39> @[Mux.scala 27:72]
+    node _T_438 = eq(_T_437, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:79]
-    _T_438 <= _T_437 @[Mux.scala 27:72]
+    node _T_439 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
-    node _T_439 = cat(_T_428, _T_438) @[Cat.scala 29:58]
+    node _T_440 = eq(_T_439, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:79]
-    io.iccm_rd_data_ecc <= _T_439 @[el2_ifu_iccm_mem.scala 109:23]
+    node _T_441 = mux(_T_434, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_442 = mux(_T_436, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_443 = mux(_T_438, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_444 = mux(_T_440, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_445 = or(_T_441, _T_442) @[Mux.scala 27:72]
+    node _T_446 = or(_T_445, _T_443) @[Mux.scala 27:72]
+    node _T_447 = or(_T_446, _T_444) @[Mux.scala 27:72]
+    wire _T_448 : UInt<39> @[Mux.scala 27:72]
+    _T_448 <= _T_447 @[Mux.scala 27:72]
+    node _T_449 = cat(_T_432, _T_448) @[Cat.scala 29:58]
+    io.iccm_rd_data_ecc <= _T_449 @[el2_ifu_iccm_mem.scala 109:23]
     

el2_ifu_iccm_mem.v

@@ -239,42 +239,48 @@ module el2_ifu_iccm_mem(
   reg [2:0] _T_373; // @[Reg.scala 27:20]
   reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34]
   reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 103:34]
-  wire  _T_375 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 105:86]
+  wire  _T_376 = iccm_rd_addr_lo_q[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 105:104]
-  wire  _T_377 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 105:86]
+  wire  _T_379 = iccm_rd_addr_lo_q[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 105:104]
-  wire  _T_379 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 105:86]
+  wire  _T_382 = iccm_rd_addr_lo_q[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 105:104]
-  wire  _T_381 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 105:86]
+  wire  _T_385 = iccm_rd_addr_lo_q[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 105:104]
-  wire [31:0] _T_383 = _T_375 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_387 = _T_376 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_384 = _T_377 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_388 = _T_379 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_385 = _T_379 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_389 = _T_382 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_386 = _T_381 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_390 = _T_385 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_387 = _T_383 | _T_384; // @[Mux.scala 27:72]
+  wire [31:0] _T_391 = _T_387 | _T_388; // @[Mux.scala 27:72]
-  wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72]
+  wire [31:0] _T_392 = _T_391 | _T_389; // @[Mux.scala 27:72]
-  wire [31:0] _T_389 = _T_388 | _T_386; // @[Mux.scala 27:72]
+  wire [31:0] _T_393 = _T_392 | _T_390; // @[Mux.scala 27:72]
-  wire  _T_392 = iccm_rd_addr_lo_q[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77]
+  wire [31:0] _T_407 = _T_376 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire  _T_395 = iccm_rd_addr_lo_q[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77]
+  wire [31:0] _T_408 = _T_379 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire  _T_398 = iccm_rd_addr_lo_q[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77]
+  wire [31:0] _T_409 = _T_382 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire  _T_401 = iccm_rd_addr_lo_q[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77]
+  wire [31:0] _T_410 = _T_385 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_403 = _T_392 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_411 = _T_407 | _T_408; // @[Mux.scala 27:72]
-  wire [31:0] _T_404 = _T_395 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_412 = _T_411 | _T_409; // @[Mux.scala 27:72]
-  wire [31:0] _T_405 = _T_398 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_413 = _T_412 | _T_410; // @[Mux.scala 27:72]
-  wire [31:0] _T_406 = _T_401 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [63:0] iccm_rd_data_pre = {_T_393,_T_413}; // @[Cat.scala 29:58]
-  wire [31:0] _T_407 = _T_403 | _T_404; // @[Mux.scala 27:72]
+  wire [63:0] _T_419 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_408 = _T_407 | _T_405; // @[Mux.scala 27:72]
+  wire  _T_421 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 109:85]
-  wire [31:0] _T_409 = _T_408 | _T_406; // @[Mux.scala 27:72]
+  wire  _T_422 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 109:85]
-  wire [63:0] iccm_rd_data_pre = {_T_389,_T_409}; // @[Cat.scala 29:58]
+  wire  _T_423 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 109:85]
-  wire [63:0] _T_415 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
+  wire  _T_424 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 109:85]
-  wire [38:0] _T_421 = _T_375 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_425 = _T_421 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_422 = _T_377 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_426 = _T_422 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_423 = _T_379 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_427 = _T_423 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_424 = _T_381 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_428 = _T_424 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_425 = _T_421 | _T_422; // @[Mux.scala 27:72]
+  wire [38:0] _T_429 = _T_425 | _T_426; // @[Mux.scala 27:72]
-  wire [38:0] _T_426 = _T_425 | _T_423; // @[Mux.scala 27:72]
+  wire [38:0] _T_430 = _T_429 | _T_427; // @[Mux.scala 27:72]
-  wire [38:0] _T_427 = _T_426 | _T_424; // @[Mux.scala 27:72]
+  wire [38:0] _T_431 = _T_430 | _T_428; // @[Mux.scala 27:72]
-  wire  _T_430 = ~iccm_rd_addr_lo_q[1]; // @[el2_ifu_iccm_mem.scala 110:31]
+  wire  _T_434 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 110:79]
-  wire  _T_431 = ~_T_430; // @[el2_ifu_iccm_mem.scala 110:65]
+  wire  _T_436 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 110:79]
-  wire [38:0] _T_435 = _T_431 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
+  wire  _T_438 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 110:79]
-  wire [38:0] _T_436 = _T_430 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
+  wire  _T_440 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 110:79]
-  wire [38:0] _T_437 = _T_435 | _T_436; // @[Mux.scala 27:72]
+  wire [38:0] _T_441 = _T_434 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_442 = _T_436 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_443 = _T_438 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_444 = _T_440 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_445 = _T_441 | _T_442; // @[Mux.scala 27:72]
+  wire [38:0] _T_446 = _T_445 | _T_443; // @[Mux.scala 27:72]
+  wire [38:0] _T_447 = _T_446 | _T_444; // @[Mux.scala 27:72]
   assign _T_85__T_105_addr = _T_85__T_105_addr_pipe_0;
   assign _T_85__T_105_data = _T_85[_T_85__T_105_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
   assign _T_85__T_101_data = io_iccm_wr_data[38:0];
@@ -299,8 +305,8 @@ module el2_ifu_iccm_mem(
   assign _T_88__T_104_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_83;
   assign _T_88__T_104_mask = 1'h1;
   assign _T_88__T_104_en = iccm_clken_3 & wren_bank_3;
-  assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_415 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 108:19]
+  assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_419 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 108:19]
-  assign io_iccm_rd_data_ecc = {_T_427,_T_437}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 109:23]
+  assign io_iccm_rd_data_ecc = {_T_431,_T_447}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 109:23]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif

src/main/scala/ifu/el2_ifu_iccm_mem.scala

@@ -101,13 +101,13 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
 
   val iccm_rd_addr_lo_q = RegNext(RegEnable(io.iccm_rw_addr(ICCM_BANK_HI-1,0), 0.U, 1.U.asBool), 0.U)
   val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U)
-
+  //val hig_q_vec = (0 until ICCM_NUM_BANKS)
-  val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))),
+  val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(if(i==3) 0 else i+1)(31,0))),
   Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(i)(31,0))))
 
   io.iccm_rd_data := Mux(iccm_rd_addr_lo_q(0).asBool(),Cat(Fill(16,0.U),iccm_rd_data_pre(63,16)) ,iccm_rd_data_pre)
   io.iccm_rd_data_ecc :=Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i))),
-    Mux1H((0 until 2).map(i=>(!iccm_rd_addr_lo_q(ICCM_BANK_HI-2)===i.U)->iccm_bank_dout_fn(i+2))))
+    Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-2,0)===i.U)->iccm_bank_dout_fn(i))))
 }