From 190229bf7f3f53f5c87b51289036e04f24518548 Mon Sep 17 00:00:00 2001
From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com>
Date: Fri, 25 Sep 2020 21:01:14 +0500
Subject: [PATCH] Update el2_ifu_aln_ctl.scala

---
 src/main/scala/ifu/el2_ifu_aln_ctl.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
index aeb3d5e6..458c9ad7 100644
--- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
@@ -377,7 +377,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   f2pc := RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool)
   f2pc := RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool)
   f2pc := RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool)
-}
+}/*
 object ifu_aln extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl()))
-}
\ No newline at end of file
+}*/