diff --git a/src/main/scala/ifu/el2_ifu_compress.scala b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
similarity index 99%
rename from src/main/scala/ifu/el2_ifu_compress.scala
rename to src/main/scala/ifu/el2_ifu_compress_ctl.scala
index 70ad77d0..f15b3e1b 100644
--- a/src/main/scala/ifu/el2_ifu_compress.scala
+++ b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
@@ -223,4 +223,4 @@ class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Mod
 
 object ifu_compress extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress(64, true)))
-}
\ No newline at end of file
+}