From 195b0904c31dd527cedda00329a62302c1f43099 Mon Sep 17 00:00:00 2001
From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com>
Date: Thu, 24 Sep 2020 11:02:59 +0500
Subject: [PATCH] Rename el2_ifu_compress.scala to el2_ifu_compress_ctl.scala

---
 .../ifu/{el2_ifu_compress.scala => el2_ifu_compress_ctl.scala}  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 rename src/main/scala/ifu/{el2_ifu_compress.scala => el2_ifu_compress_ctl.scala} (99%)

diff --git a/src/main/scala/ifu/el2_ifu_compress.scala b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
similarity index 99%
rename from src/main/scala/ifu/el2_ifu_compress.scala
rename to src/main/scala/ifu/el2_ifu_compress_ctl.scala
index 70ad77d0..f15b3e1b 100644
--- a/src/main/scala/ifu/el2_ifu_compress.scala
+++ b/src/main/scala/ifu/el2_ifu_compress_ctl.scala
@@ -223,4 +223,4 @@ class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Mod
 
 object ifu_compress extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress(64, true)))
-}
\ No newline at end of file
+}