Bug fixed
This commit is contained in:
waleed-lm
parent
effba077f4
commit
1a16fe4178
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@ -1,77 +1,9 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_1",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_hit",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_0",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_perr",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid",
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"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
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"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
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"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
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"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_1",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_0",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr"
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]
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},
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{
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2482
EL2_IC_TAG.fir
2482
EL2_IC_TAG.fir
File diff suppressed because it is too large
Load Diff
372
EL2_IC_TAG.v
372
EL2_IC_TAG.v
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@ -1,136 +1,13 @@
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module rvecc_decode(
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input [31:0] io_din,
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input [6:0] io_ecc_in,
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output [6:0] io_ecc_out,
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output [31:0] io_dout,
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output io_single_ecc_error
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);
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wire w0_0 = io_din[0]; // @[beh_lib.scala 239:37]
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wire w0_1 = io_din[1]; // @[beh_lib.scala 239:37]
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wire w1_1 = io_din[2]; // @[beh_lib.scala 240:37]
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wire w0_2 = io_din[3]; // @[beh_lib.scala 239:37]
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wire w0_3 = io_din[4]; // @[beh_lib.scala 239:37]
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wire w1_3 = io_din[5]; // @[beh_lib.scala 240:37]
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wire w0_4 = io_din[6]; // @[beh_lib.scala 239:37]
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wire w2_3 = io_din[7]; // @[beh_lib.scala 241:37]
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wire w0_5 = io_din[8]; // @[beh_lib.scala 239:37]
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wire w1_5 = io_din[9]; // @[beh_lib.scala 240:37]
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wire w0_6 = io_din[10]; // @[beh_lib.scala 239:37]
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wire w0_7 = io_din[11]; // @[beh_lib.scala 239:37]
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wire w1_7 = io_din[12]; // @[beh_lib.scala 240:37]
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wire w0_8 = io_din[13]; // @[beh_lib.scala 239:37]
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wire w2_7 = io_din[14]; // @[beh_lib.scala 241:37]
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wire w0_9 = io_din[15]; // @[beh_lib.scala 239:37]
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wire w1_9 = io_din[16]; // @[beh_lib.scala 240:37]
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wire w0_10 = io_din[17]; // @[beh_lib.scala 239:37]
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wire w3_7 = io_din[18]; // @[beh_lib.scala 242:37]
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wire w0_11 = io_din[19]; // @[beh_lib.scala 239:37]
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wire w1_11 = io_din[20]; // @[beh_lib.scala 240:37]
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wire w0_12 = io_din[21]; // @[beh_lib.scala 239:37]
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wire w2_11 = io_din[22]; // @[beh_lib.scala 241:37]
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wire w0_13 = io_din[23]; // @[beh_lib.scala 239:37]
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wire w1_13 = io_din[24]; // @[beh_lib.scala 240:37]
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wire w0_14 = io_din[25]; // @[beh_lib.scala 239:37]
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wire w0_15 = io_din[26]; // @[beh_lib.scala 239:37]
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wire w1_15 = io_din[27]; // @[beh_lib.scala 240:37]
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wire w0_16 = io_din[28]; // @[beh_lib.scala 239:37]
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wire w2_15 = io_din[29]; // @[beh_lib.scala 241:37]
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wire w0_17 = io_din[30]; // @[beh_lib.scala 239:37]
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wire w1_17 = io_din[31]; // @[beh_lib.scala 240:37]
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wire [5:0] _T_100 = {w1_17,w0_17,w2_15,w0_16,w1_15,w0_15}; // @[beh_lib.scala 247:86]
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wire _T_101 = ^_T_100; // @[beh_lib.scala 247:93]
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wire _T_102 = io_ecc_in[5] ^ _T_101; // @[beh_lib.scala 247:81]
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wire [6:0] _T_109 = {w0_10,w1_9,w0_9,w2_7,w0_8,w1_7,w0_7}; // @[beh_lib.scala 247:116]
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wire [14:0] _T_117 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_109}; // @[beh_lib.scala 247:116]
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wire _T_118 = ^_T_117; // @[beh_lib.scala 247:123]
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wire _T_119 = io_ecc_in[4] ^ _T_118; // @[beh_lib.scala 247:111]
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wire [6:0] _T_126 = {w0_6,w1_5,w0_5,w2_3,w0_4,w1_3,w0_3}; // @[beh_lib.scala 247:146]
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wire [14:0] _T_134 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_126}; // @[beh_lib.scala 247:146]
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wire _T_135 = ^_T_134; // @[beh_lib.scala 247:153]
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wire _T_136 = io_ecc_in[3] ^ _T_135; // @[beh_lib.scala 247:141]
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wire [8:0] _T_145 = {w0_9,w2_7,w0_6,w1_5,w0_5,w2_3,w0_2,w1_1,w0_1}; // @[beh_lib.scala 247:176]
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wire [17:0] _T_154 = {w1_17,w0_17,w2_15,w0_14,w1_13,w0_13,w2_11,w0_10,w1_9,_T_145}; // @[beh_lib.scala 247:176]
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wire _T_155 = ^_T_154; // @[beh_lib.scala 247:183]
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wire _T_156 = io_ecc_in[2] ^ _T_155; // @[beh_lib.scala 247:171]
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wire [8:0] _T_165 = {w0_8,w1_7,w0_6,w1_5,w0_4,w1_3,w0_2,w1_1,w0_0}; // @[beh_lib.scala 247:206]
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wire [17:0] _T_174 = {w1_17,w0_16,w1_15,w0_14,w1_13,w0_12,w1_11,w0_10,w1_9,_T_165}; // @[beh_lib.scala 247:206]
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wire _T_175 = ^_T_174; // @[beh_lib.scala 247:213]
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wire _T_176 = io_ecc_in[1] ^ _T_175; // @[beh_lib.scala 247:201]
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wire [8:0] _T_185 = {w0_8,w0_7,w0_6,w0_5,w0_4,w0_3,w0_2,w0_1,w0_0}; // @[beh_lib.scala 247:236]
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wire [17:0] _T_194 = {w0_17,w0_16,w0_15,w0_14,w0_13,w0_12,w0_11,w0_10,w0_9,_T_185}; // @[beh_lib.scala 247:236]
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wire _T_195 = ^_T_194; // @[beh_lib.scala 247:243]
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wire _T_196 = io_ecc_in[0] ^ _T_195; // @[beh_lib.scala 247:231]
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wire [6:0] ecc_check = {1'h0,_T_102,_T_119,_T_136,_T_156,_T_176,_T_196}; // @[Cat.scala 29:58]
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wire error_mask_0 = ecc_check[5:0] == 6'h1; // @[beh_lib.scala 255:39]
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wire error_mask_1 = ecc_check[5:0] == 6'h2; // @[beh_lib.scala 255:39]
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wire error_mask_2 = ecc_check[5:0] == 6'h3; // @[beh_lib.scala 255:39]
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wire error_mask_3 = ecc_check[5:0] == 6'h4; // @[beh_lib.scala 255:39]
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wire error_mask_4 = ecc_check[5:0] == 6'h5; // @[beh_lib.scala 255:39]
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wire error_mask_5 = ecc_check[5:0] == 6'h6; // @[beh_lib.scala 255:39]
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wire error_mask_6 = ecc_check[5:0] == 6'h7; // @[beh_lib.scala 255:39]
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wire error_mask_7 = ecc_check[5:0] == 6'h8; // @[beh_lib.scala 255:39]
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wire error_mask_8 = ecc_check[5:0] == 6'h9; // @[beh_lib.scala 255:39]
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wire error_mask_9 = ecc_check[5:0] == 6'ha; // @[beh_lib.scala 255:39]
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wire error_mask_10 = ecc_check[5:0] == 6'hb; // @[beh_lib.scala 255:39]
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wire error_mask_11 = ecc_check[5:0] == 6'hc; // @[beh_lib.scala 255:39]
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wire error_mask_12 = ecc_check[5:0] == 6'hd; // @[beh_lib.scala 255:39]
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wire error_mask_13 = ecc_check[5:0] == 6'he; // @[beh_lib.scala 255:39]
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wire error_mask_14 = ecc_check[5:0] == 6'hf; // @[beh_lib.scala 255:39]
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wire error_mask_15 = ecc_check[5:0] == 6'h10; // @[beh_lib.scala 255:39]
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wire error_mask_16 = ecc_check[5:0] == 6'h11; // @[beh_lib.scala 255:39]
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wire error_mask_17 = ecc_check[5:0] == 6'h12; // @[beh_lib.scala 255:39]
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wire error_mask_18 = ecc_check[5:0] == 6'h13; // @[beh_lib.scala 255:39]
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wire error_mask_19 = ecc_check[5:0] == 6'h14; // @[beh_lib.scala 255:39]
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wire error_mask_20 = ecc_check[5:0] == 6'h15; // @[beh_lib.scala 255:39]
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wire error_mask_21 = ecc_check[5:0] == 6'h16; // @[beh_lib.scala 255:39]
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wire error_mask_22 = ecc_check[5:0] == 6'h17; // @[beh_lib.scala 255:39]
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wire error_mask_23 = ecc_check[5:0] == 6'h18; // @[beh_lib.scala 255:39]
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wire error_mask_24 = ecc_check[5:0] == 6'h19; // @[beh_lib.scala 255:39]
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wire error_mask_25 = ecc_check[5:0] == 6'h1a; // @[beh_lib.scala 255:39]
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wire error_mask_26 = ecc_check[5:0] == 6'h1b; // @[beh_lib.scala 255:39]
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wire error_mask_27 = ecc_check[5:0] == 6'h1c; // @[beh_lib.scala 255:39]
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wire error_mask_28 = ecc_check[5:0] == 6'h1d; // @[beh_lib.scala 255:39]
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wire error_mask_29 = ecc_check[5:0] == 6'h1e; // @[beh_lib.scala 255:39]
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wire error_mask_30 = ecc_check[5:0] == 6'h1f; // @[beh_lib.scala 255:39]
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wire error_mask_31 = ecc_check[5:0] == 6'h20; // @[beh_lib.scala 255:39]
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wire error_mask_32 = ecc_check[5:0] == 6'h21; // @[beh_lib.scala 255:39]
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wire error_mask_33 = ecc_check[5:0] == 6'h22; // @[beh_lib.scala 255:39]
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wire error_mask_34 = ecc_check[5:0] == 6'h23; // @[beh_lib.scala 255:39]
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wire error_mask_35 = ecc_check[5:0] == 6'h24; // @[beh_lib.scala 255:39]
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wire error_mask_36 = ecc_check[5:0] == 6'h25; // @[beh_lib.scala 255:39]
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wire error_mask_37 = ecc_check[5:0] == 6'h26; // @[beh_lib.scala 255:39]
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wire error_mask_38 = ecc_check[5:0] == 6'h27; // @[beh_lib.scala 255:39]
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wire [7:0] _T_310 = {io_ecc_in[3],io_din[3:1],io_ecc_in[2],w0_0,io_ecc_in[1:0]}; // @[Cat.scala 29:58]
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wire [38:0] din_plus_parity = {io_ecc_in[6],io_din[31:26],io_ecc_in[5],io_din[25:11],io_ecc_in[4],io_din[10:4],_T_310}; // @[Cat.scala 29:58]
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wire [9:0] _T_333 = {error_mask_18,error_mask_17,error_mask_16,error_mask_15,error_mask_14,error_mask_13,error_mask_12,error_mask_11,error_mask_10,error_mask_9}; // @[beh_lib.scala 258:70]
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wire [18:0] _T_334 = {_T_333,error_mask_8,error_mask_7,error_mask_6,error_mask_5,error_mask_4,error_mask_3,error_mask_2,error_mask_1,error_mask_0}; // @[beh_lib.scala 258:70]
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wire [9:0] _T_343 = {error_mask_28,error_mask_27,error_mask_26,error_mask_25,error_mask_24,error_mask_23,error_mask_22,error_mask_21,error_mask_20,error_mask_19}; // @[beh_lib.scala 258:70]
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wire [9:0] _T_352 = {error_mask_38,error_mask_37,error_mask_36,error_mask_35,error_mask_34,error_mask_33,error_mask_32,error_mask_31,error_mask_30,error_mask_29}; // @[beh_lib.scala 258:70]
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wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[beh_lib.scala 258:70]
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wire [38:0] _T_355 = _T_354 ^ din_plus_parity; // @[beh_lib.scala 258:77]
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wire [38:0] dout_plus_parity = io_single_ecc_error ? _T_355 : din_plus_parity; // @[beh_lib.scala 258:29]
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wire [3:0] _T_361 = {dout_plus_parity[6:4],dout_plus_parity[2]}; // @[Cat.scala 29:58]
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wire [27:0] _T_363 = {dout_plus_parity[37:32],dout_plus_parity[30:16],dout_plus_parity[14:8]}; // @[Cat.scala 29:58]
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wire _T_367 = ecc_check == 7'h40; // @[beh_lib.scala 261:60]
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wire _T_368 = dout_plus_parity[38] ^ _T_367; // @[beh_lib.scala 261:42]
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wire [3:0] _T_375 = {dout_plus_parity[7],dout_plus_parity[3],dout_plus_parity[1:0]}; // @[Cat.scala 29:58]
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wire [2:0] _T_377 = {_T_368,dout_plus_parity[31],dout_plus_parity[15]}; // @[Cat.scala 29:58]
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assign io_ecc_out = {_T_377,_T_375}; // @[beh_lib.scala 248:14 beh_lib.scala 261:14]
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assign io_dout = {_T_363,_T_361}; // @[beh_lib.scala 260:11]
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assign io_single_ecc_error = 1'h0; // @[beh_lib.scala 250:23]
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endmodule
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module EL2_IC_TAG(
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input clock,
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input reset,
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input io_clk,
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input io_rst_l,
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input io_clk_override,
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input io_dec_tlu_core_ecc_disable,
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input [31:0] io_ic_rw_addr,
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input [28:0] io_ic_rw_addr,
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input [1:0] io_ic_wr_en,
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input [1:0] io_ic_tag_valid,
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input io_ic_rd_en,
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input [12:0] io_ic_debug_addr,
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input [9:0] io_ic_debug_addr,
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input io_ic_debug_rd_en,
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input io_ic_debug_wr_en,
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input io_ic_debug_tag_array,
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@ -140,245 +17,10 @@ module EL2_IC_TAG(
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output [1:0] io_ic_rd_hit,
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output io_ic_tag_perr,
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input io_scan_mode,
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output [25:0] io_test,
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output [31:0] io_test_ecc_data_out_0,
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output [31:0] io_test_ecc_data_out_1,
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output [6:0] io_test_ecc_out_0,
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output [6:0] io_test_ecc_out_1,
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output io_test_ecc_sb_out_0,
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output io_test_ecc_sb_out_1,
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output io_test_ecc_db_out_0,
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output io_test_ecc_db_out_1
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output [28:0] io_test
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);
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`ifdef RANDOMIZE_MEM_INIT
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reg [31:0] _RAND_0;
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reg [31:0] _RAND_2;
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`endif // RANDOMIZE_MEM_INIT
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`ifdef RANDOMIZE_REG_INIT
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reg [31:0] _RAND_1;
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reg [31:0] _RAND_3;
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reg [31:0] _RAND_4;
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reg [31:0] _RAND_5;
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`endif // RANDOMIZE_REG_INIT
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reg [25:0] ic_way_tag_0 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
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wire [25:0] ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
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||||
wire [6:0] ic_way_tag_0_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire [25:0] ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire [6:0] ic_way_tag_0__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire ic_way_tag_0__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire ic_way_tag_0__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
reg [6:0] ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
|
||||
reg [25:0] ic_way_tag_1 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire [25:0] ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire [6:0] ic_way_tag_1_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire [25:0] ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire [6:0] ic_way_tag_1__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire ic_way_tag_1__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
wire ic_way_tag_1__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
reg [6:0] ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
|
||||
wire [31:0] rvecc_decode_io_din; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire [6:0] rvecc_decode_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire [6:0] rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire [31:0] rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire rvecc_decode_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire [31:0] rvecc_decode_1_io_din; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire [6:0] rvecc_decode_1_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire [6:0] rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire [31:0] rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire rvecc_decode_1_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
|
||||
wire _T_2 = io_ic_rw_addr[5:4] == 2'h1; // @[el2_ifu_ic_mem.scala 73:93]
|
||||
wire [1:0] _T_4 = {_T_2,_T_2}; // @[Cat.scala 29:58]
|
||||
wire [1:0] ic_tag_wren = io_ic_wr_en & _T_4; // @[el2_ifu_ic_mem.scala 73:33]
|
||||
wire _T_5 = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 75:68]
|
||||
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
|
||||
wire [1:0] ic_debug_rd_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 75:93]
|
||||
wire _T_8 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 76:68]
|
||||
wire [1:0] _T_10 = {_T_8,_T_8}; // @[Cat.scala 29:58]
|
||||
wire [1:0] ic_debug_wr_way_en = _T_10 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 76:93]
|
||||
wire _T_11 = io_ic_rd_en | io_clk_override; // @[el2_ifu_ic_mem.scala 77:55]
|
||||
wire [1:0] _T_13 = {_T_11,_T_11}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_14 = _T_13 | io_ic_wr_en; // @[el2_ifu_ic_mem.scala 77:74]
|
||||
wire [1:0] _T_15 = _T_14 | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 77:88]
|
||||
wire [1:0] ic_tag_clken = _T_15 | ic_debug_rd_way_en; // @[el2_ifu_ic_mem.scala 77:109]
|
||||
reg [31:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 80:30]
|
||||
wire [1:0] ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 82:35]
|
||||
wire [31:0] _T_30 = {13'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
|
||||
wire [8:0] _T_134 = {_T_30[16],_T_30[14],_T_30[12],_T_30[10],_T_30[8],_T_30[6],_T_30[5],_T_30[3],_T_30[1]}; // @[el2_lib.scala 211:22]
|
||||
wire [17:0] _T_143 = {_T_30[31],_T_30[30],_T_30[28],_T_30[27],_T_30[25],_T_30[23],_T_30[21],_T_30[20],_T_30[18],_T_134}; // @[el2_lib.scala 211:22]
|
||||
wire _T_144 = ^_T_143; // @[el2_lib.scala 211:29]
|
||||
wire [8:0] _T_152 = {_T_30[15],_T_30[14],_T_30[11],_T_30[10],_T_30[7],_T_30[6],_T_30[4],_T_30[3],_T_30[0]}; // @[el2_lib.scala 211:39]
|
||||
wire [17:0] _T_161 = {_T_30[31],_T_30[29],_T_30[28],_T_30[26],_T_30[25],_T_30[22],_T_30[21],_T_30[19],_T_30[18],_T_152}; // @[el2_lib.scala 211:39]
|
||||
wire _T_162 = ^_T_161; // @[el2_lib.scala 211:46]
|
||||
wire [8:0] _T_170 = {_T_30[15],_T_30[14],_T_30[9],_T_30[8],_T_30[7],_T_30[6],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:56]
|
||||
wire [17:0] _T_179 = {_T_30[30],_T_30[29],_T_30[28],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[17],_T_30[16],_T_170}; // @[el2_lib.scala 211:56]
|
||||
wire _T_180 = ^_T_179; // @[el2_lib.scala 211:63]
|
||||
wire [6:0] _T_186 = {_T_30[12],_T_30[11],_T_30[10],_T_30[9],_T_30[8],_T_30[7],_T_30[6]}; // @[el2_lib.scala 211:73]
|
||||
wire [14:0] _T_194 = {_T_30[27],_T_30[26],_T_30[25],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[13],_T_186}; // @[el2_lib.scala 211:73]
|
||||
wire _T_195 = ^_T_194; // @[el2_lib.scala 211:80]
|
||||
wire [14:0] _T_209 = {_T_30[20],_T_30[19],_T_30[18],_T_30[17],_T_30[16],_T_30[15],_T_30[14],_T_30[13],_T_186}; // @[el2_lib.scala 211:90]
|
||||
wire _T_210 = ^_T_209; // @[el2_lib.scala 211:97]
|
||||
wire [5:0] _T_215 = {_T_30[5],_T_30[4],_T_30[3],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:107]
|
||||
wire _T_216 = ^_T_215; // @[el2_lib.scala 211:114]
|
||||
wire [5:0] _T_221 = {_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
|
||||
wire _T_222 = ^_T_30; // @[el2_lib.scala 212:13]
|
||||
wire _T_223 = ^_T_221; // @[el2_lib.scala 212:23]
|
||||
wire _T_224 = _T_222 ^ _T_223; // @[el2_lib.scala 212:18]
|
||||
wire [6:0] _T_225 = {_T_224,_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
|
||||
wire [25:0] _T_229 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58]
|
||||
wire [25:0] _T_463 = {_T_225[4:0],2'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
|
||||
wire _T_478 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 119:44]
|
||||
reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 123:38]
|
||||
wire [25:0] _GEN_17 = ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 137:75]
|
||||
wire [25:0] _GEN_18 = ic_way_tag_0_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
|
||||
wire [36:0] w_tout_0 = {_GEN_18[25:21],_GEN_18[18:0],13'h0}; // @[Cat.scala 29:58]
|
||||
wire [25:0] _GEN_22 = ic_way_tag_1_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
|
||||
wire [36:0] w_tout_1 = {_GEN_22[25:21],_GEN_22[18:0],13'h0}; // @[Cat.scala 29:58]
|
||||
wire ic_tag_way_perr_0 = io_test_ecc_sb_out_0 | io_test_ecc_db_out_0; // @[el2_ifu_ic_mem.scala 165:54]
|
||||
wire ic_tag_way_perr_1 = io_test_ecc_sb_out_1 | io_test_ecc_db_out_1; // @[el2_ifu_ic_mem.scala 165:54]
|
||||
wire [9:0] _T_533 = {ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_542 = {_T_533,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
|
||||
wire [25:0] _T_549 = {_T_542,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
|
||||
wire [25:0] _T_550 = _T_549 & ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
|
||||
wire [9:0] _T_561 = {ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_570 = {_T_561,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
|
||||
wire [25:0] _T_577 = {_T_570,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
|
||||
wire [25:0] _T_578 = _T_577 & ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
|
||||
wire [36:0] _T_636 = w_tout_0 & w_tout_1; // @[el2_ifu_ic_mem.scala 176:31]
|
||||
wire [1:0] _T_637 = {ic_tag_way_perr_0,ic_tag_way_perr_1}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_638 = _T_637 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 177:55]
|
||||
wire _T_642 = w_tout_0[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
|
||||
wire [1:0] _GEN_25 = {{1'd0}, _T_642}; // @[el2_ifu_ic_mem.scala 179:133]
|
||||
wire [1:0] _T_643 = _GEN_25 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
|
||||
wire _T_646 = w_tout_1[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
|
||||
wire [1:0] _GEN_26 = {{1'd0}, _T_646}; // @[el2_ifu_ic_mem.scala 179:133]
|
||||
wire [1:0] _T_647 = _GEN_26 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
|
||||
wire [3:0] _T_649 = {_T_643,_T_647}; // @[Cat.scala 29:58]
|
||||
rvecc_decode rvecc_decode ( // @[el2_ifu_ic_mem.scala 149:27]
|
||||
.io_din(rvecc_decode_io_din),
|
||||
.io_ecc_in(rvecc_decode_io_ecc_in),
|
||||
.io_ecc_out(rvecc_decode_io_ecc_out),
|
||||
.io_dout(rvecc_decode_io_dout),
|
||||
.io_single_ecc_error(rvecc_decode_io_single_ecc_error)
|
||||
);
|
||||
rvecc_decode rvecc_decode_1 ( // @[el2_ifu_ic_mem.scala 149:27]
|
||||
.io_din(rvecc_decode_1_io_din),
|
||||
.io_ecc_in(rvecc_decode_1_io_ecc_in),
|
||||
.io_ecc_out(rvecc_decode_1_io_ecc_out),
|
||||
.io_dout(rvecc_decode_1_io_dout),
|
||||
.io_single_ecc_error(rvecc_decode_1_io_single_ecc_error)
|
||||
);
|
||||
assign ic_way_tag_0_ic_tag_data_raw_addr = ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
|
||||
assign ic_way_tag_0_ic_tag_data_raw_data = ic_way_tag_0[ic_way_tag_0_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
assign ic_way_tag_0__T_487_data = _T_8 ? _T_229 : _T_463;
|
||||
assign ic_way_tag_0__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
|
||||
assign ic_way_tag_0__T_487_mask = ic_tag_wren_q[0] & ic_tag_clken[0];
|
||||
assign ic_way_tag_0__T_487_en = 1'h1;
|
||||
assign ic_way_tag_1_ic_tag_data_raw_addr = ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
|
||||
assign ic_way_tag_1_ic_tag_data_raw_data = ic_way_tag_1[ic_way_tag_1_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
assign ic_way_tag_1__T_487_data = _T_8 ? _T_229 : _T_463;
|
||||
assign ic_way_tag_1__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
|
||||
assign ic_way_tag_1__T_487_mask = ic_tag_wren_q[1] & ic_tag_clken[1];
|
||||
assign ic_way_tag_1__T_487_en = 1'h1;
|
||||
assign io_ictag_debug_rd_data = _T_550 | _T_578; // @[el2_ifu_ic_mem.scala 175:26]
|
||||
assign io_ic_rd_hit = _T_649[1:0]; // @[el2_ifu_ic_mem.scala 179:16]
|
||||
assign io_ic_tag_perr = |_T_638; // @[el2_ifu_ic_mem.scala 177:18]
|
||||
assign io_test = _T_636[25:0]; // @[el2_ifu_ic_mem.scala 176:13]
|
||||
assign io_test_ecc_data_out_0 = rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
|
||||
assign io_test_ecc_data_out_1 = rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
|
||||
assign io_test_ecc_out_0 = rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
|
||||
assign io_test_ecc_out_1 = rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
|
||||
assign io_test_ecc_sb_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
|
||||
assign io_test_ecc_sb_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
|
||||
assign io_test_ecc_db_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
|
||||
assign io_test_ecc_db_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
|
||||
assign rvecc_decode_io_din = {11'h0,ic_way_tag_0_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
|
||||
assign rvecc_decode_io_ecc_in = {2'h0,ic_way_tag_0_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
|
||||
assign rvecc_decode_1_io_din = {11'h0,ic_way_tag_1_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
|
||||
assign rvecc_decode_1_io_ecc_in = {2'h0,ic_way_tag_1_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifndef RANDOM
|
||||
`define RANDOM $random
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
integer initvar;
|
||||
`endif
|
||||
`ifndef SYNTHESIS
|
||||
`ifdef FIRRTL_BEFORE_INITIAL
|
||||
`FIRRTL_BEFORE_INITIAL
|
||||
`endif
|
||||
initial begin
|
||||
`ifdef RANDOMIZE
|
||||
`ifdef INIT_RANDOM
|
||||
`INIT_RANDOM
|
||||
`endif
|
||||
`ifndef VERILATOR
|
||||
`ifdef RANDOMIZE_DELAY
|
||||
#`RANDOMIZE_DELAY begin end
|
||||
`else
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
_RAND_0 = {1{`RANDOM}};
|
||||
for (initvar = 0; initvar < 128; initvar = initvar+1)
|
||||
ic_way_tag_0[initvar] = _RAND_0[25:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
for (initvar = 0; initvar < 128; initvar = initvar+1)
|
||||
ic_way_tag_1[initvar] = _RAND_2[25:0];
|
||||
`endif // RANDOMIZE_MEM_INIT
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 = _RAND_1[6:0];
|
||||
_RAND_3 = {1{`RANDOM}};
|
||||
ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 = _RAND_3[6:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
ic_rw_addr_ff = _RAND_4[31:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
ic_debug_rd_way_en_ff = _RAND_5[1:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if(ic_way_tag_0__T_487_en & ic_way_tag_0__T_487_mask) begin
|
||||
ic_way_tag_0[ic_way_tag_0__T_487_addr] <= ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
end
|
||||
if (_T_478) begin
|
||||
ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
|
||||
end else begin
|
||||
ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
|
||||
end
|
||||
if(ic_way_tag_1__T_487_en & ic_way_tag_1__T_487_mask) begin
|
||||
ic_way_tag_1[ic_way_tag_1__T_487_addr] <= ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
|
||||
end
|
||||
if (_T_478) begin
|
||||
ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
|
||||
end else begin
|
||||
ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
|
||||
end
|
||||
if (reset) begin
|
||||
ic_rw_addr_ff <= 32'h0;
|
||||
end else begin
|
||||
ic_rw_addr_ff <= io_ic_rw_addr;
|
||||
end
|
||||
if (reset) begin
|
||||
ic_debug_rd_way_en_ff <= 2'h0;
|
||||
end else begin
|
||||
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
|
||||
end
|
||||
end
|
||||
assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 65:26]
|
||||
assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 66:16]
|
||||
assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 67:18]
|
||||
assign io_test = io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 87:11]
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -85,186 +85,187 @@ circuit el2_ifu_ifc_ctl :
|
|||
node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
|
||||
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
|
||||
node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
|
||||
node _T_27 = bits(address_upper, 5, 5) @[el2_ifu_ifc_ctl.scala 78:38]
|
||||
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:83]
|
||||
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:62]
|
||||
node _T_30 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:129]
|
||||
node _T_31 = and(_T_29, _T_30) @[el2_ifu_ifc_ctl.scala 78:108]
|
||||
fetch_addr_next_0 <= _T_31 @[el2_ifu_ifc_ctl.scala 78:21]
|
||||
node _T_32 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
|
||||
fetch_addr_next <= _T_32 @[el2_ifu_ifc_ctl.scala 80:19]
|
||||
node _T_33 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
|
||||
io.ifc_fetch_req_bf_raw <= _T_33 @[el2_ifu_ifc_ctl.scala 82:27]
|
||||
node _T_34 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
|
||||
node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
|
||||
node _T_36 = and(fb_full_f_ns, _T_35) @[el2_ifu_ifc_ctl.scala 84:68]
|
||||
node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
|
||||
node _T_38 = and(io.ifc_fetch_req_bf_raw, _T_37) @[el2_ifu_ifc_ctl.scala 84:51]
|
||||
node _T_39 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
|
||||
node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctl.scala 84:114]
|
||||
node _T_41 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
|
||||
node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctl.scala 85:16]
|
||||
node _T_43 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
|
||||
node _T_44 = and(_T_42, _T_43) @[el2_ifu_ifc_ctl.scala 85:37]
|
||||
io.ifc_fetch_req_bf <= _T_44 @[el2_ifu_ifc_ctl.scala 84:23]
|
||||
node _T_45 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
|
||||
fetch_bf_en <= _T_45 @[el2_ifu_ifc_ctl.scala 87:15]
|
||||
node _T_46 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
|
||||
node _T_47 = and(io.ifc_fetch_req_f, _T_46) @[el2_ifu_ifc_ctl.scala 89:32]
|
||||
node _T_48 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
|
||||
node _T_49 = and(_T_47, _T_48) @[el2_ifu_ifc_ctl.scala 89:47]
|
||||
miss_f <= _T_49 @[el2_ifu_ifc_ctl.scala 89:10]
|
||||
node _T_50 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
|
||||
node _T_51 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
|
||||
node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctl.scala 91:61]
|
||||
node _T_53 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
|
||||
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctl.scala 91:74]
|
||||
node _T_55 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
|
||||
node _T_56 = and(_T_54, _T_55) @[el2_ifu_ifc_ctl.scala 91:84]
|
||||
mb_empty_mod <= _T_56 @[el2_ifu_ifc_ctl.scala 91:16]
|
||||
node _T_57 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
|
||||
goto_idle <= _T_57 @[el2_ifu_ifc_ctl.scala 93:13]
|
||||
node _T_58 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
|
||||
node _T_59 = and(io.exu_flush_final, _T_58) @[el2_ifu_ifc_ctl.scala 95:36]
|
||||
node _T_60 = and(_T_59, idle) @[el2_ifu_ifc_ctl.scala 95:67]
|
||||
leave_idle <= _T_60 @[el2_ifu_ifc_ctl.scala 95:14]
|
||||
node _T_61 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
|
||||
node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
|
||||
node _T_63 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
|
||||
node _T_64 = and(_T_62, _T_63) @[el2_ifu_ifc_ctl.scala 97:33]
|
||||
node _T_65 = and(_T_64, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
|
||||
node _T_66 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
|
||||
node _T_67 = and(_T_65, _T_66) @[el2_ifu_ifc_ctl.scala 97:53]
|
||||
node _T_68 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
|
||||
node _T_69 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
|
||||
node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctl.scala 98:15]
|
||||
node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
|
||||
node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctl.scala 98:31]
|
||||
node next_state_1 = or(_T_67, _T_72) @[el2_ifu_ifc_ctl.scala 97:67]
|
||||
node _T_73 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
|
||||
node _T_74 = and(_T_73, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
|
||||
node _T_75 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
|
||||
node _T_76 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
|
||||
node _T_77 = and(_T_75, _T_76) @[el2_ifu_ifc_ctl.scala 100:60]
|
||||
node next_state_0 = or(_T_74, _T_77) @[el2_ifu_ifc_ctl.scala 100:48]
|
||||
node _T_78 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
|
||||
reg _T_79 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
_T_79 <= _T_78 @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
state <= _T_79 @[el2_ifu_ifc_ctl.scala 102:9]
|
||||
node _T_27 = bits(address_upper, 4, 4) @[el2_ifu_ifc_ctl.scala 78:39]
|
||||
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84]
|
||||
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63]
|
||||
node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24]
|
||||
node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:130]
|
||||
node _T_32 = and(_T_30, _T_31) @[el2_ifu_ifc_ctl.scala 78:109]
|
||||
fetch_addr_next_0 <= _T_32 @[el2_ifu_ifc_ctl.scala 78:21]
|
||||
node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
|
||||
fetch_addr_next <= _T_33 @[el2_ifu_ifc_ctl.scala 80:19]
|
||||
node _T_34 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
|
||||
io.ifc_fetch_req_bf_raw <= _T_34 @[el2_ifu_ifc_ctl.scala 82:27]
|
||||
node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
|
||||
node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
|
||||
node _T_37 = and(fb_full_f_ns, _T_36) @[el2_ifu_ifc_ctl.scala 84:68]
|
||||
node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
|
||||
node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[el2_ifu_ifc_ctl.scala 84:51]
|
||||
node _T_40 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
|
||||
node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctl.scala 84:114]
|
||||
node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
|
||||
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctl.scala 85:16]
|
||||
node _T_44 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
|
||||
node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctl.scala 85:37]
|
||||
io.ifc_fetch_req_bf <= _T_45 @[el2_ifu_ifc_ctl.scala 84:23]
|
||||
node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
|
||||
fetch_bf_en <= _T_46 @[el2_ifu_ifc_ctl.scala 87:15]
|
||||
node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
|
||||
node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[el2_ifu_ifc_ctl.scala 89:32]
|
||||
node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
|
||||
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 89:47]
|
||||
miss_f <= _T_50 @[el2_ifu_ifc_ctl.scala 89:10]
|
||||
node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
|
||||
node _T_52 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
|
||||
node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctl.scala 91:61]
|
||||
node _T_54 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
|
||||
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctl.scala 91:74]
|
||||
node _T_56 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
|
||||
node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctl.scala 91:84]
|
||||
mb_empty_mod <= _T_57 @[el2_ifu_ifc_ctl.scala 91:16]
|
||||
node _T_58 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
|
||||
goto_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 93:13]
|
||||
node _T_59 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
|
||||
node _T_60 = and(io.exu_flush_final, _T_59) @[el2_ifu_ifc_ctl.scala 95:36]
|
||||
node _T_61 = and(_T_60, idle) @[el2_ifu_ifc_ctl.scala 95:67]
|
||||
leave_idle <= _T_61 @[el2_ifu_ifc_ctl.scala 95:14]
|
||||
node _T_62 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
|
||||
node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
|
||||
node _T_64 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
|
||||
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 97:33]
|
||||
node _T_66 = and(_T_65, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
|
||||
node _T_67 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
|
||||
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 97:53]
|
||||
node _T_69 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
|
||||
node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
|
||||
node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctl.scala 98:15]
|
||||
node _T_72 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
|
||||
node _T_73 = and(_T_71, _T_72) @[el2_ifu_ifc_ctl.scala 98:31]
|
||||
node next_state_1 = or(_T_68, _T_73) @[el2_ifu_ifc_ctl.scala 97:67]
|
||||
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
|
||||
node _T_75 = and(_T_74, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
|
||||
node _T_76 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
|
||||
node _T_77 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
|
||||
node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 100:60]
|
||||
node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 100:48]
|
||||
node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
|
||||
reg _T_80 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
_T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
state <= _T_80 @[el2_ifu_ifc_ctl.scala 102:9]
|
||||
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
|
||||
node _T_80 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
|
||||
node _T_81 = and(io.ifu_fb_consume1, _T_80) @[el2_ifu_ifc_ctl.scala 106:36]
|
||||
node _T_82 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
|
||||
node _T_83 = or(_T_82, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
|
||||
node _T_84 = and(_T_81, _T_83) @[el2_ifu_ifc_ctl.scala 106:58]
|
||||
node _T_85 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
|
||||
node _T_86 = or(_T_84, _T_85) @[el2_ifu_ifc_ctl.scala 106:92]
|
||||
fb_right <= _T_86 @[el2_ifu_ifc_ctl.scala 106:12]
|
||||
node _T_87 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
|
||||
node _T_88 = or(_T_87, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
|
||||
node _T_89 = and(io.ifu_fb_consume2, _T_88) @[el2_ifu_ifc_ctl.scala 109:36]
|
||||
fb_right2 <= _T_89 @[el2_ifu_ifc_ctl.scala 109:13]
|
||||
node _T_90 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
|
||||
node _T_91 = eq(_T_90, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
|
||||
node _T_92 = and(io.ifc_fetch_req_f, _T_91) @[el2_ifu_ifc_ctl.scala 110:33]
|
||||
node _T_93 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
|
||||
node _T_94 = and(_T_92, _T_93) @[el2_ifu_ifc_ctl.scala 110:78]
|
||||
fb_left <= _T_94 @[el2_ifu_ifc_ctl.scala 110:11]
|
||||
node _T_95 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
|
||||
node _T_96 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
|
||||
node _T_97 = and(_T_96, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
|
||||
node _T_98 = bits(_T_97, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
|
||||
node _T_99 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
|
||||
node _T_100 = cat(UInt<1>("h00"), _T_99) @[Cat.scala 29:58]
|
||||
node _T_101 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
|
||||
node _T_102 = and(_T_101, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
|
||||
node _T_103 = bits(_T_102, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
|
||||
node _T_104 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
|
||||
node _T_105 = cat(UInt<2>("h00"), _T_104) @[Cat.scala 29:58]
|
||||
node _T_106 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
|
||||
node _T_107 = and(_T_106, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
|
||||
node _T_108 = bits(_T_107, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
|
||||
node _T_109 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
|
||||
node _T_110 = cat(_T_109, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_111 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
|
||||
node _T_112 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
|
||||
node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctl.scala 116:16]
|
||||
node _T_114 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
|
||||
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctl.scala 116:28]
|
||||
node _T_116 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
|
||||
node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctl.scala 116:41]
|
||||
node _T_118 = bits(_T_117, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
|
||||
node _T_119 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
|
||||
node _T_120 = mux(_T_95, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_121 = mux(_T_98, _T_100, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_122 = mux(_T_103, _T_105, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_123 = mux(_T_108, _T_110, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_124 = mux(_T_118, _T_119, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_125 = or(_T_120, _T_121) @[Mux.scala 27:72]
|
||||
node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
|
||||
node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
|
||||
node _T_82 = and(io.ifu_fb_consume1, _T_81) @[el2_ifu_ifc_ctl.scala 106:36]
|
||||
node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
|
||||
node _T_84 = or(_T_83, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
|
||||
node _T_85 = and(_T_82, _T_84) @[el2_ifu_ifc_ctl.scala 106:58]
|
||||
node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
|
||||
node _T_87 = or(_T_85, _T_86) @[el2_ifu_ifc_ctl.scala 106:92]
|
||||
fb_right <= _T_87 @[el2_ifu_ifc_ctl.scala 106:12]
|
||||
node _T_88 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
|
||||
node _T_89 = or(_T_88, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
|
||||
node _T_90 = and(io.ifu_fb_consume2, _T_89) @[el2_ifu_ifc_ctl.scala 109:36]
|
||||
fb_right2 <= _T_90 @[el2_ifu_ifc_ctl.scala 109:13]
|
||||
node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
|
||||
node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
|
||||
node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[el2_ifu_ifc_ctl.scala 110:33]
|
||||
node _T_94 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
|
||||
node _T_95 = and(_T_93, _T_94) @[el2_ifu_ifc_ctl.scala 110:78]
|
||||
fb_left <= _T_95 @[el2_ifu_ifc_ctl.scala 110:11]
|
||||
node _T_96 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
|
||||
node _T_97 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
|
||||
node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
|
||||
node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
|
||||
node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
|
||||
node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58]
|
||||
node _T_102 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
|
||||
node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
|
||||
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
|
||||
node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
|
||||
node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58]
|
||||
node _T_107 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
|
||||
node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
|
||||
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
|
||||
node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
|
||||
node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_112 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
|
||||
node _T_113 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
|
||||
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctl.scala 116:16]
|
||||
node _T_115 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
|
||||
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctl.scala 116:28]
|
||||
node _T_117 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
|
||||
node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctl.scala 116:41]
|
||||
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
|
||||
node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
|
||||
node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72]
|
||||
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
|
||||
node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
|
||||
wire _T_129 : UInt<4> @[Mux.scala 27:72]
|
||||
_T_129 <= _T_128 @[Mux.scala 27:72]
|
||||
fb_write_ns <= _T_129 @[el2_ifu_ifc_ctl.scala 112:15]
|
||||
node _T_130 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
|
||||
reg _T_131 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
|
||||
_T_131 <= _T_130 @[el2_ifu_ifc_ctl.scala 119:26]
|
||||
fb_full_f_ns <= _T_131 @[el2_ifu_ifc_ctl.scala 119:16]
|
||||
node _T_132 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
|
||||
idle <= _T_132 @[el2_ifu_ifc_ctl.scala 121:8]
|
||||
node _T_133 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
|
||||
wfm <= _T_133 @[el2_ifu_ifc_ctl.scala 122:7]
|
||||
node _T_134 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
|
||||
fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctl.scala 124:16]
|
||||
node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
|
||||
wire _T_130 : UInt<4> @[Mux.scala 27:72]
|
||||
_T_130 <= _T_129 @[Mux.scala 27:72]
|
||||
fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 112:15]
|
||||
node _T_131 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
|
||||
reg _T_132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
|
||||
_T_132 <= _T_131 @[el2_ifu_ifc_ctl.scala 119:26]
|
||||
fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctl.scala 119:16]
|
||||
node _T_133 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
|
||||
idle <= _T_133 @[el2_ifu_ifc_ctl.scala 121:8]
|
||||
node _T_134 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
|
||||
wfm <= _T_134 @[el2_ifu_ifc_ctl.scala 122:7]
|
||||
node _T_135 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
|
||||
fb_full_f_ns <= _T_135 @[el2_ifu_ifc_ctl.scala 124:16]
|
||||
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 125:26]
|
||||
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 125:26]
|
||||
reg _T_135 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
_T_135 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
fb_write_f <= _T_135 @[el2_ifu_ifc_ctl.scala 126:14]
|
||||
node _T_136 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
|
||||
node _T_137 = or(_T_136, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
|
||||
node _T_138 = eq(_T_137, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
|
||||
node _T_139 = and(fb_full_f, _T_138) @[el2_ifu_ifc_ctl.scala 129:17]
|
||||
node _T_140 = or(_T_139, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
|
||||
node _T_141 = and(io.ifc_fetch_req_bf_raw, _T_140) @[el2_ifu_ifc_ctl.scala 128:60]
|
||||
node _T_142 = or(wfm, _T_141) @[el2_ifu_ifc_ctl.scala 128:33]
|
||||
io.ifu_pmu_fetch_stall <= _T_142 @[el2_ifu_ifc_ctl.scala 128:26]
|
||||
node _T_143 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_144 = bits(_T_143, 31, 28) @[el2_lib.scala 211:25]
|
||||
node iccm_acc_in_region_bf = eq(_T_144, UInt<4>("h0e")) @[el2_lib.scala 211:47]
|
||||
node _T_145 = bits(_T_143, 31, 16) @[el2_lib.scala 214:14]
|
||||
node iccm_acc_in_range_bf = eq(_T_145, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
|
||||
reg _T_136 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
_T_136 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
fb_write_f <= _T_136 @[el2_ifu_ifc_ctl.scala 126:14]
|
||||
node _T_137 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
|
||||
node _T_138 = or(_T_137, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
|
||||
node _T_139 = eq(_T_138, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
|
||||
node _T_140 = and(fb_full_f, _T_139) @[el2_ifu_ifc_ctl.scala 129:17]
|
||||
node _T_141 = or(_T_140, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
|
||||
node _T_142 = and(io.ifc_fetch_req_bf_raw, _T_141) @[el2_ifu_ifc_ctl.scala 128:60]
|
||||
node _T_143 = or(wfm, _T_142) @[el2_ifu_ifc_ctl.scala 128:33]
|
||||
io.ifu_pmu_fetch_stall <= _T_143 @[el2_ifu_ifc_ctl.scala 128:26]
|
||||
node _T_144 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_145 = bits(_T_144, 31, 28) @[el2_lib.scala 211:25]
|
||||
node iccm_acc_in_region_bf = eq(_T_145, UInt<4>("h0e")) @[el2_lib.scala 211:47]
|
||||
node _T_146 = bits(_T_144, 31, 16) @[el2_lib.scala 214:14]
|
||||
node iccm_acc_in_range_bf = eq(_T_146, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
|
||||
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 134:25]
|
||||
node _T_146 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
|
||||
node _T_147 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
|
||||
node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
|
||||
node _T_149 = and(fb_full_f, _T_148) @[el2_ifu_ifc_ctl.scala 136:16]
|
||||
node _T_150 = or(_T_146, _T_149) @[el2_ifu_ifc_ctl.scala 135:53]
|
||||
node _T_151 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
|
||||
node _T_152 = and(wfm, _T_151) @[el2_ifu_ifc_ctl.scala 137:11]
|
||||
node _T_153 = or(_T_150, _T_152) @[el2_ifu_ifc_ctl.scala 136:62]
|
||||
node _T_154 = or(_T_153, idle) @[el2_ifu_ifc_ctl.scala 137:35]
|
||||
node _T_155 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
|
||||
node _T_156 = and(_T_154, _T_155) @[el2_ifu_ifc_ctl.scala 137:44]
|
||||
node _T_157 = or(_T_156, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
|
||||
io.ifc_dma_access_ok <= _T_157 @[el2_ifu_ifc_ctl.scala 135:24]
|
||||
node _T_158 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
|
||||
node _T_159 = and(_T_158, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
|
||||
io.ifc_region_acc_fault_bf <= _T_159 @[el2_ifu_ifc_ctl.scala 139:30]
|
||||
node _T_160 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
|
||||
node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_162 = dshr(io.dec_tlu_mrac_ff, _T_161) @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
node _T_163 = bits(_T_162, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
node _T_164 = not(_T_163) @[el2_ifu_ifc_ctl.scala 140:34]
|
||||
io.ifc_fetch_uncacheable_bf <= _T_164 @[el2_ifu_ifc_ctl.scala 140:31]
|
||||
reg _T_165 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
_T_165 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
io.ifc_fetch_req_f <= _T_165 @[el2_ifu_ifc_ctl.scala 142:22]
|
||||
node _T_166 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
|
||||
reg _T_167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_166 : @[Reg.scala 28:19]
|
||||
_T_167 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||
node _T_147 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
|
||||
node _T_148 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
|
||||
node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
|
||||
node _T_150 = and(fb_full_f, _T_149) @[el2_ifu_ifc_ctl.scala 136:16]
|
||||
node _T_151 = or(_T_147, _T_150) @[el2_ifu_ifc_ctl.scala 135:53]
|
||||
node _T_152 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
|
||||
node _T_153 = and(wfm, _T_152) @[el2_ifu_ifc_ctl.scala 137:11]
|
||||
node _T_154 = or(_T_151, _T_153) @[el2_ifu_ifc_ctl.scala 136:62]
|
||||
node _T_155 = or(_T_154, idle) @[el2_ifu_ifc_ctl.scala 137:35]
|
||||
node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
|
||||
node _T_157 = and(_T_155, _T_156) @[el2_ifu_ifc_ctl.scala 137:44]
|
||||
node _T_158 = or(_T_157, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
|
||||
io.ifc_dma_access_ok <= _T_158 @[el2_ifu_ifc_ctl.scala 135:24]
|
||||
node _T_159 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
|
||||
node _T_160 = and(_T_159, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
|
||||
io.ifc_region_acc_fault_bf <= _T_160 @[el2_ifu_ifc_ctl.scala 139:30]
|
||||
node _T_161 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
|
||||
node _T_162 = cat(_T_161, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_163 = dshr(io.dec_tlu_mrac_ff, _T_162) @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
node _T_165 = not(_T_164) @[el2_ifu_ifc_ctl.scala 140:34]
|
||||
io.ifc_fetch_uncacheable_bf <= _T_165 @[el2_ifu_ifc_ctl.scala 140:31]
|
||||
reg _T_166 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
_T_166 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
io.ifc_fetch_req_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:22]
|
||||
node _T_167 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
|
||||
reg _T_168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_167 : @[Reg.scala 28:19]
|
||||
_T_168 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
io.ifc_fetch_addr_f <= _T_167 @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
io.ifc_fetch_addr_f <= _T_168 @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
|
||||
|
|
|
|||
|
|
@ -55,115 +55,116 @@ module el2_ifu_ifc_ctl(
|
|||
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
|
||||
wire _T_29 = address_upper[5] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:62]
|
||||
wire fetch_addr_next_0 = _T_29 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:108]
|
||||
wire _T_29 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
|
||||
wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
|
||||
wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
|
||||
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
|
||||
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 121:17]
|
||||
wire _T_34 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
|
||||
wire _T_35 = ~_T_34; // @[el2_ifu_ifc_ctl.scala 84:70]
|
||||
wire [3:0] _T_120 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire _T_80 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
|
||||
wire _T_81 = io_ifu_fb_consume1 & _T_80; // @[el2_ifu_ifc_ctl.scala 106:36]
|
||||
wire _T_47 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
|
||||
wire miss_f = _T_47 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
|
||||
wire _T_83 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
|
||||
wire _T_84 = _T_81 & _T_83; // @[el2_ifu_ifc_ctl.scala 106:58]
|
||||
wire _T_85 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
|
||||
wire fb_right = _T_84 | _T_85; // @[el2_ifu_ifc_ctl.scala 106:92]
|
||||
wire _T_97 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
|
||||
wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
|
||||
wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70]
|
||||
wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
|
||||
wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 106:36]
|
||||
wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
|
||||
wire miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
|
||||
wire _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
|
||||
wire _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 106:58]
|
||||
wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
|
||||
wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92]
|
||||
wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
|
||||
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
wire [3:0] _T_100 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_121 = _T_97 ? _T_100 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_125 = _T_120 | _T_121; // @[Mux.scala 27:72]
|
||||
wire fb_right2 = io_ifu_fb_consume2 & _T_83; // @[el2_ifu_ifc_ctl.scala 109:36]
|
||||
wire _T_102 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
|
||||
wire [3:0] _T_105 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_122 = _T_102 ? _T_105 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_126 = _T_125 | _T_122; // @[Mux.scala 27:72]
|
||||
wire _T_90 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
|
||||
wire _T_91 = ~_T_90; // @[el2_ifu_ifc_ctl.scala 110:35]
|
||||
wire _T_92 = io_ifc_fetch_req_f & _T_91; // @[el2_ifu_ifc_ctl.scala 110:33]
|
||||
wire _T_93 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
|
||||
wire fb_left = _T_92 & _T_93; // @[el2_ifu_ifc_ctl.scala 110:78]
|
||||
wire _T_107 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
|
||||
wire [3:0] _T_110 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_123 = _T_107 ? _T_110 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72]
|
||||
wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 109:36]
|
||||
wire _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
|
||||
wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72]
|
||||
wire _T_112 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
|
||||
wire _T_113 = _T_2 & _T_112; // @[el2_ifu_ifc_ctl.scala 116:16]
|
||||
wire _T_114 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
|
||||
wire _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctl.scala 116:28]
|
||||
wire _T_116 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
|
||||
wire _T_117 = _T_115 & _T_116; // @[el2_ifu_ifc_ctl.scala 116:41]
|
||||
wire [3:0] _T_124 = _T_117 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] fb_write_ns = _T_127 | _T_124; // @[Mux.scala 27:72]
|
||||
wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
|
||||
wire _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 110:35]
|
||||
wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 110:33]
|
||||
wire _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
|
||||
wire fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 110:78]
|
||||
wire _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
|
||||
wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
|
||||
wire _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
|
||||
wire _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 116:16]
|
||||
wire _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
|
||||
wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 116:28]
|
||||
wire _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
|
||||
wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41]
|
||||
wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72]
|
||||
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 124:30]
|
||||
wire _T_36 = fb_full_f_ns & _T_35; // @[el2_ifu_ifc_ctl.scala 84:68]
|
||||
wire _T_37 = ~_T_36; // @[el2_ifu_ifc_ctl.scala 84:53]
|
||||
wire _T_38 = io_ifc_fetch_req_bf_raw & _T_37; // @[el2_ifu_ifc_ctl.scala 84:51]
|
||||
wire _T_39 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
|
||||
wire _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctl.scala 84:114]
|
||||
wire _T_41 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
|
||||
wire _T_42 = _T_40 & _T_41; // @[el2_ifu_ifc_ctl.scala 85:16]
|
||||
wire _T_43 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
|
||||
wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68]
|
||||
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53]
|
||||
wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51]
|
||||
wire _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
|
||||
wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 84:114]
|
||||
wire _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
|
||||
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16]
|
||||
wire _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
|
||||
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 87:37]
|
||||
wire _T_50 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
|
||||
wire _T_52 = _T_50 & _T_39; // @[el2_ifu_ifc_ctl.scala 91:61]
|
||||
wire _T_54 = _T_52 & _T_93; // @[el2_ifu_ifc_ctl.scala 91:74]
|
||||
wire _T_55 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
|
||||
wire mb_empty_mod = _T_54 & _T_55; // @[el2_ifu_ifc_ctl.scala 91:84]
|
||||
wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
|
||||
wire _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61]
|
||||
wire _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74]
|
||||
wire _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
|
||||
wire mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 91:84]
|
||||
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35]
|
||||
wire _T_59 = io_exu_flush_final & _T_43; // @[el2_ifu_ifc_ctl.scala 95:36]
|
||||
wire leave_idle = _T_59 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
|
||||
wire _T_62 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
|
||||
wire _T_64 = _T_62 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
|
||||
wire _T_65 = _T_64 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
|
||||
wire _T_66 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
|
||||
wire _T_67 = _T_65 & _T_66; // @[el2_ifu_ifc_ctl.scala 97:53]
|
||||
wire _T_69 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
|
||||
wire _T_70 = state[1] & _T_69; // @[el2_ifu_ifc_ctl.scala 98:15]
|
||||
wire _T_72 = _T_70 & _T_66; // @[el2_ifu_ifc_ctl.scala 98:31]
|
||||
wire next_state_1 = _T_67 | _T_72; // @[el2_ifu_ifc_ctl.scala 97:67]
|
||||
wire _T_74 = _T_66 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
|
||||
wire _T_77 = state[0] & _T_66; // @[el2_ifu_ifc_ctl.scala 100:60]
|
||||
wire next_state_0 = _T_74 | _T_77; // @[el2_ifu_ifc_ctl.scala 100:48]
|
||||
wire _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 95:36]
|
||||
wire leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
|
||||
wire _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
|
||||
wire _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
|
||||
wire _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
|
||||
wire _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
|
||||
wire _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 97:53]
|
||||
wire _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
|
||||
wire _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 98:15]
|
||||
wire _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:31]
|
||||
wire next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 97:67]
|
||||
wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
|
||||
wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60]
|
||||
wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48]
|
||||
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 122:16]
|
||||
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 125:26]
|
||||
wire _T_137 = _T_34 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 129:61]
|
||||
wire _T_138 = ~_T_137; // @[el2_ifu_ifc_ctl.scala 129:19]
|
||||
wire _T_139 = fb_full_f & _T_138; // @[el2_ifu_ifc_ctl.scala 129:17]
|
||||
wire _T_140 = _T_139 | dma_stall; // @[el2_ifu_ifc_ctl.scala 129:84]
|
||||
wire _T_141 = io_ifc_fetch_req_bf_raw & _T_140; // @[el2_ifu_ifc_ctl.scala 128:60]
|
||||
wire [31:0] _T_143 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||
wire iccm_acc_in_region_bf = _T_143[31:28] == 4'he; // @[el2_lib.scala 211:47]
|
||||
wire iccm_acc_in_range_bf = _T_143[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
|
||||
wire _T_146 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 135:30]
|
||||
wire _T_149 = fb_full_f & _T_35; // @[el2_ifu_ifc_ctl.scala 136:16]
|
||||
wire _T_150 = _T_146 | _T_149; // @[el2_ifu_ifc_ctl.scala 135:53]
|
||||
wire _T_151 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 137:13]
|
||||
wire _T_152 = wfm & _T_151; // @[el2_ifu_ifc_ctl.scala 137:11]
|
||||
wire _T_153 = _T_150 | _T_152; // @[el2_ifu_ifc_ctl.scala 136:62]
|
||||
wire _T_154 = _T_153 | idle; // @[el2_ifu_ifc_ctl.scala 137:35]
|
||||
wire _T_156 = _T_154 & _T_2; // @[el2_ifu_ifc_ctl.scala 137:44]
|
||||
wire _T_158 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 139:33]
|
||||
wire [4:0] _T_161 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_162 = io_dec_tlu_mrac_ff >> _T_161; // @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
reg _T_165; // @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
reg [30:0] _T_167; // @[Reg.scala 27:20]
|
||||
assign io_ifc_fetch_addr_f = _T_167; // @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
wire _T_138 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 129:61]
|
||||
wire _T_139 = ~_T_138; // @[el2_ifu_ifc_ctl.scala 129:19]
|
||||
wire _T_140 = fb_full_f & _T_139; // @[el2_ifu_ifc_ctl.scala 129:17]
|
||||
wire _T_141 = _T_140 | dma_stall; // @[el2_ifu_ifc_ctl.scala 129:84]
|
||||
wire _T_142 = io_ifc_fetch_req_bf_raw & _T_141; // @[el2_ifu_ifc_ctl.scala 128:60]
|
||||
wire [31:0] _T_144 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||
wire iccm_acc_in_region_bf = _T_144[31:28] == 4'he; // @[el2_lib.scala 211:47]
|
||||
wire iccm_acc_in_range_bf = _T_144[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
|
||||
wire _T_147 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 135:30]
|
||||
wire _T_150 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 136:16]
|
||||
wire _T_151 = _T_147 | _T_150; // @[el2_ifu_ifc_ctl.scala 135:53]
|
||||
wire _T_152 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 137:13]
|
||||
wire _T_153 = wfm & _T_152; // @[el2_ifu_ifc_ctl.scala 137:11]
|
||||
wire _T_154 = _T_151 | _T_153; // @[el2_ifu_ifc_ctl.scala 136:62]
|
||||
wire _T_155 = _T_154 | idle; // @[el2_ifu_ifc_ctl.scala 137:35]
|
||||
wire _T_157 = _T_155 & _T_2; // @[el2_ifu_ifc_ctl.scala 137:44]
|
||||
wire _T_159 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 139:33]
|
||||
wire [4:0] _T_162 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_163 = io_dec_tlu_mrac_ff >> _T_162; // @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
reg _T_166; // @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
reg [30:0] _T_168; // @[Reg.scala 27:20]
|
||||
assign io_ifc_fetch_addr_f = _T_168; // @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
|
||||
assign io_ifc_fetch_req_f = _T_165; // @[el2_ifu_ifc_ctl.scala 142:22]
|
||||
assign io_ifu_pmu_fetch_stall = wfm | _T_141; // @[el2_ifu_ifc_ctl.scala 128:26]
|
||||
assign io_ifc_fetch_uncacheable_bf = ~_T_162[0]; // @[el2_ifu_ifc_ctl.scala 140:31]
|
||||
assign io_ifc_fetch_req_bf = _T_42 & _T_43; // @[el2_ifu_ifc_ctl.scala 84:23]
|
||||
assign io_ifc_fetch_req_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:22]
|
||||
assign io_ifu_pmu_fetch_stall = wfm | _T_142; // @[el2_ifu_ifc_ctl.scala 128:26]
|
||||
assign io_ifc_fetch_uncacheable_bf = ~_T_163[0]; // @[el2_ifu_ifc_ctl.scala 140:31]
|
||||
assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23]
|
||||
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
|
||||
assign io_ifc_iccm_access_bf = _T_143[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 134:25]
|
||||
assign io_ifc_region_acc_fault_bf = _T_158 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 139:30]
|
||||
assign io_ifc_dma_access_ok = _T_156 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 135:24]
|
||||
assign io_ifc_iccm_access_bf = _T_144[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 134:25]
|
||||
assign io_ifc_region_acc_fault_bf = _T_159 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 139:30]
|
||||
assign io_ifc_dma_access_ok = _T_157 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 135:24]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -210,9 +211,9 @@ initial begin
|
|||
_RAND_4 = {1{`RANDOM}};
|
||||
fb_full_f = _RAND_4[0:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
_T_165 = _RAND_5[0:0];
|
||||
_T_166 = _RAND_5[0:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
_T_167 = _RAND_6[30:0];
|
||||
_T_168 = _RAND_6[30:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
dma_iccm_stall_any_f = 1'h0;
|
||||
|
|
@ -230,10 +231,10 @@ initial begin
|
|||
fb_full_f = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_165 = 1'h0;
|
||||
_T_166 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_167 = 31'h0;
|
||||
_T_168 = 31'h0;
|
||||
end
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
|
|
@ -252,7 +253,7 @@ end // initial
|
|||
if (reset) begin
|
||||
miss_a <= 1'h0;
|
||||
end else begin
|
||||
miss_a <= _T_47 & _T_2;
|
||||
miss_a <= _T_48 & _T_2;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
|
|
@ -266,7 +267,7 @@ end // initial
|
|||
if (reset) begin
|
||||
fb_write_f <= 4'h0;
|
||||
end else begin
|
||||
fb_write_f <= _T_127 | _T_124;
|
||||
fb_write_f <= _T_128 | _T_125;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
|
|
@ -278,16 +279,16 @@ end // initial
|
|||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_165 <= 1'h0;
|
||||
_T_166 <= 1'h0;
|
||||
end else begin
|
||||
_T_165 <= io_ifc_fetch_req_bf;
|
||||
_T_166 <= io_ifc_fetch_req_bf;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_167 <= 31'h0;
|
||||
_T_168 <= 31'h0;
|
||||
end else if (fetch_bf_en) begin
|
||||
_T_167 <= io_ifc_fetch_addr_bf;
|
||||
_T_168 <= io_ifc_fetch_addr_bf;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ class EL2_IC_TAG extends Module with el2_lib with param {
|
|||
val io = IO(new Bundle{
|
||||
val clk_override = Input(Bool())
|
||||
val dec_tlu_core_ecc_disable = Input(Bool())
|
||||
val ic_rw_addr = Input(UInt(28.W))
|
||||
val ic_rw_addr = Input(UInt(29.W)) // 32:3
|
||||
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_rd_en = Input(Bool())
|
||||
|
|
@ -53,16 +53,43 @@ class EL2_IC_TAG extends Module with el2_lib with param {
|
|||
val ic_debug_wr_en = Input(Bool())
|
||||
val ic_debug_tag_array = Input(Bool())
|
||||
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
// val ictag_debug_rd_data = Output(UInt(26.W))
|
||||
val ictag_debug_rd_data = Output(UInt(26.W))
|
||||
val ic_debug_wr_data = Input(UInt(71.W))
|
||||
// val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
// val ic_tag_perr = Output(Bool())
|
||||
val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_tag_perr = Output(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
val test = Output(UInt())
|
||||
|
||||
})
|
||||
|
||||
// val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U))
|
||||
// val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en |
|
||||
io.ictag_debug_rd_data := 0.U
|
||||
io.ic_rd_hit := 0.U
|
||||
io.ic_tag_perr := 0.U
|
||||
val ic_debug_wr_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ic_debug_rd_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U))
|
||||
val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_rd_way_en
|
||||
|
||||
val ic_rd_en_ff = RegNext(io.ic_rd_en, 0.U)
|
||||
val ic_rw_addr_ff = RegNext(io.ic_rw_addr(31-ICACHE_TAG_LO, 0), 0.U)
|
||||
|
||||
val PAD_BITS = 21 - (32 - ICACHE_TAG_LO)
|
||||
|
||||
ic_debug_rd_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way
|
||||
ic_debug_wr_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
|
||||
|
||||
val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en
|
||||
|
||||
val ic_tag_ecc = rvecc_encode(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3)))
|
||||
|
||||
val ic_tag_wr_data = Mux((io.ic_debug_wr_en & io.ic_debug_tag_array).asBool, Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)),
|
||||
Cat(ic_tag_ecc(4,0),io.ic_rw_addr(31-3,ICACHE_TAG_LO-3)))
|
||||
io.test := io.ic_rw_addr
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way
|
||||
// val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
|
||||
// val ic_tag_clken = repl(ICACHE_NUM_WAYS,io.ic_rd_en | io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_wr_way_en | ic_debug_rd_way_en
|
||||
|
|
@ -215,10 +242,7 @@ class EL2_IC_DATA extends Module with el2_lib {
|
|||
|
||||
val ic_rw_addr_bank_q = VecInit(Mux((!ic_rw_addr_wrap).asBool,ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1),
|
||||
Cat(ic_rw_addr_q(ICACHE_INDEX_HI-1, ICACHE_TAG_INDEX_LO-1) , ic_rw_addr_q_inc(ICACHE_TAG_INDEX_LO-2,ICACHE_DATA_INDEX_LO-1))),
|
||||
ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1)
|
||||
)
|
||||
|
||||
|
||||
ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1))
|
||||
|
||||
val ic_b_rden_ff = RegNext(ic_b_rden, 0.U)
|
||||
val ic_rw_addr_ff = RegNext(ic_rw_addr_q(ICACHE_TAG_INDEX_LO-2,0), 0.U)
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
|
||||
|
||||
val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
|
||||
fetch_addr_next_0 := (address_upper(ICACHE_TAG_INDEX_LO-1) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
|
||||
fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
|
||||
|
||||
fetch_addr_next := Cat(address_upper, fetch_addr_next_0)
|
||||
|
||||
|
|
|
|||
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Reference in New Issue