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Jahanzaib Rasheed
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import chisel3._
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import chisel3.util._
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import lib._
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import include._
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import snapshot._
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class el2_lsu_clkdomain extends Module {
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val io = IO (new Bundle {
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/* Implicit
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val clk = Input(Clock()) // clock
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val rst_l = Input(1.W) // reset
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*/
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val free_clk = Input(Clock()) // clock
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// Inputs
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val clk_override = Input(Bool()) // chciken bit to turn off clock gating
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val addr_in_dccm_m = Input(Bool()) // address in dccm
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val dma_dccm_req = Input(Bool()) // dma is active
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val ldst_stbuf_reqvld_r = Input(Bool()) // allocating in to the store queue
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val stbuf_reqvld_any = Input(Bool()) // stbuf is draining
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val stbuf_reqvld_flushed_any = Input(Bool())// instruction going to stbuf is flushed
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val lsu_busreq_r = Input(Bool()) // busreq in r
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val lsu_bus_buffer_pend_any = Input(Bool())// bus buffer has a pending bus entry
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val lsu_bus_buffer_empty_any = Input(Bool())// external bus buffer is empty
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val lsu_stbuf_empty_any = Input(Bool()) // stbuf is empty
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val lsu_bus_clk_en = Input(Bool()) // bus clock enable
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val lsu_p = new el2_lsu_pkt_t // lsu packet in decode
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val lsu_pkt_d = new el2_lsu_pkt_t // lsu packet in d
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val lsu_pkt_m = new el2_lsu_pkt_t // lsu packet in m
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val lsu_pkt_r = new el2_lsu_pkt_t // lsu packet in r
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// Outputs
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val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock
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val lsu_c1_r_clk = Output(Clock()) // r pipe single pulse clock
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val lsu_c2_m_clk = Output(Clock()) // m pipe double pulse clock
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val lsu_c2_r_clk = Output(Clock()) // r pipe double pulse clock
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val lsu_store_c1_m_clk = Output(Clock()) // store in m
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val lsu_store_c1_r_clk = Output(Clock()) // store in r
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val lsu_stbuf_c1_clk = Output(Clock())
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val lsu_bus_obuf_c1_clk = Output(Clock()) // ibuf clock
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val lsu_bus_ibuf_c1_clk = Output(Clock()) // ibuf clock
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val lsu_bus_buf_c1_clk = Output(Clock()) // ibuf clock
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val lsu_busm_clk = Output(Clock()) // bus clock
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val lsu_free_c2_clk = Output(Clock())
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val scan_mode = Input(Bool())
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})
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val lsu_c1_d_clken = 0.U
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val lsu_c1_m_clken = 0.U
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val lsu_c1_r_clken = 0.U
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val lsu_c2_m_clken = 0.U
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val lsu_c2_r_clken = 0.U
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val lsu_c1_d_clken_q = 0.U
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val lsu_c1_m_clken_q = 0.U
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val lsu_c1_r_clken_q = 0.U
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val lsu_store_c1_m_clken = 0.U
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val lsu_store_c1_r_clken = 0.U
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val lsu_stbuf_c1_clken = 0.U
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val lsu_bus_ibuf_c1_clken = 0.U
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val lsu_bus_obuf_c1_clken = 0.U
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val lsu_bus_buf_c1_clken = 0.U
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val lsu_free_c1_clken = 0.U
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val lsu_free_c1_clken_q = 0.U
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val lsu_free_c2_clken = 0.U
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//-------------------------------------------------------------------------------------------
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// Clock Enable Logic
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//-------------------------------------------------------------------------------------------
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lsu_c1_d_clken := lsu_p.valid | io.dma_dccm_req | io.clk_override
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lsu_c1_m_clken := lsu_pkt_d.valid | lsu_c1_d_clken_q | io.clk_override
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lsu_c1_r_clken := lsu_pkt_m.valid | lsu_c1_m_clken_q | io.clk_override
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lsu_c2_m_clken := lsu_c1_m_clken | lsu_c1_m_clken_q | io.clk_override
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lsu_c2_r_clken := lsu_c1_r_clken | lsu_c1_r_clken_q | io.clk_override
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lsu_store_c1_m_clken := ((lsu_c1_m_clken & lsu_pkt_d.store) | io.clk_override)
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lsu_store_c1_r_clken := ((lsu_c1_r_clken & lsu_pkt_m.store) | io.clk_override)
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lsu_stbuf_c1_clken := io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override
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lsu_bus_ibuf_c1_clken := io.lsu_busreq_r | io.clk_override
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lsu_bus_obuf_c1_clken := (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en
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lsu_bus_buf_c1_clken := ~io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override
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lsu_free_c1_clken := (lsu_p.valid | lsu_pkt_d.valid | lsu_pkt_m.valid | lsu_pkt_r.valid) | ~io.lsu_bus_buffer_empty_any | ~io.lsu_stbuf_empty_any | io.clk_override
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lsu_free_c2_clken := lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override
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/*
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// Flops
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rvdff #(1) lsu_free_c1_clkenff (.din(lsu_free_c1_clken), dout(lsu_free_c1_clken_q), clk(free_clk), *)
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rvdff #(1) lsu_c1_d_clkenff (.din(lsu_c1_d_clken), dout(lsu_c1_d_clken_q), clk(lsu_free_c2_clk), *)
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rvdff #(1) lsu_c1_m_clkenff (.din(lsu_c1_m_clken), dout(lsu_c1_m_clken_q), clk(lsu_free_c2_clk), *)
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rvdff #(1) lsu_c1_r_clkenff (.din(lsu_c1_r_clken), dout(lsu_c1_r_clken_q), clk(lsu_free_c2_clk), *)
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// Clock Headers
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rvoclkhdr lsu_c1m_cgc ( .en(lsu_c1_m_clken), l1clk(lsu_c1_m_clk), * )
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rvoclkhdr lsu_c1r_cgc ( .en(lsu_c1_r_clken), l1clk(lsu_c1_r_clk), * )
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rvoclkhdr lsu_c2m_cgc ( .en(lsu_c2_m_clken), l1clk(lsu_c2_m_clk), * )
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rvoclkhdr lsu_c2r_cgc ( .en(lsu_c2_r_clken), l1clk(lsu_c2_r_clk), * )
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rvoclkhdr lsu_store_c1m_cgc (.en(lsu_store_c1_m_clken), l1clk(lsu_store_c1_m_clk), *)
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rvoclkhdr lsu_store_c1r_cgc (.en(lsu_store_c1_r_clken), l1clk(lsu_store_c1_r_clk), *)
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rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), l1clk(lsu_stbuf_c1_clk), * )
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rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), l1clk(lsu_bus_ibuf_c1_clk), * )
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rvclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), l1clk(lsu_bus_obuf_c1_clk), * )
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rvoclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken) =
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val .l1clk(lsu_bus_buf_c1_clk), * )
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rvclkhdr lsu_busm_cgc (.en(lsu_bus_clk_en), l1clk(lsu_busm_clk), *)
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rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), l1clk(lsu_free_c2_clk), *)
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*/
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}
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