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dccm_ctl with rvdffe

This commit is contained in:
​Laraib Khan 2020-12-23 10:56:05 +05:00
parent 248ab0784b
commit 1b7a0b47e1
7 changed files with 61 additions and 72 deletions
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48
lsu_dccm_ctl.fir
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@ -980,14 +980,14 @@ circuit lsu_dccm_ctl :
node _T_814 = or(_T_813, io.clk_override) @[lsu_dccm_ctl.scala 157:145]
node _T_815 = bits(_T_814, 0, 0) @[lib.scala 8:44]
node _T_816 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr of rvclkhdr @[lib.scala 368:23]
inst rvclkhdr of rvclkhdr @[lib.scala 377:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 370:18]
rvclkhdr.io.en <= _T_815 @[lib.scala 371:17]
rvclkhdr.io.scan_mode <= _T_816 @[lib.scala 372:24]
reg _T_817 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_817 <= lsu_ld_data_corr_m @[lib.scala 374:16]
rvclkhdr.io.clk <= clock @[lib.scala 379:18]
rvclkhdr.io.en <= _T_815 @[lib.scala 380:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
reg _T_817 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_817 <= lsu_ld_data_corr_m @[lib.scala 383:16]
io.lsu_ld_data_corr_r <= _T_817 @[lsu_dccm_ctl.scala 157:28]
node _T_818 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 158:63]
node _T_819 = mul(UInt<4>("h08"), _T_818) @[lsu_dccm_ctl.scala 158:49]
@ -1671,14 +1671,14 @@ circuit lsu_dccm_ctl :
node _T_1432 = or(_T_1431, io.clk_override) @[lsu_dccm_ctl.scala 262:343]
node _T_1433 = bits(_T_1432, 0, 0) @[lib.scala 8:44]
node _T_1434 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 377:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_1.io.en <= _T_1433 @[lib.scala 371:17]
rvclkhdr_1.io.scan_mode <= _T_1434 @[lib.scala 372:24]
reg _T_1435 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_1435 <= _T_1429 @[lib.scala 374:16]
rvclkhdr_1.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_1.io.en <= _T_1433 @[lib.scala 380:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
reg _T_1435 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_1435 <= _T_1429 @[lib.scala 383:16]
io.store_data_hi_r <= _T_1435 @[lsu_dccm_ctl.scala 262:29]
node _T_1436 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105]
node _T_1437 = bits(store_byteen_ext_r, 0, 0) @[lsu_dccm_ctl.scala 263:150]
@ -2227,26 +2227,26 @@ circuit lsu_dccm_ctl :
node _T_1944 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 285:90]
node _T_1945 = bits(_T_1944, 0, 0) @[lib.scala 8:44]
node _T_1946 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 285:128]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 377:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_2.io.en <= _T_1945 @[lib.scala 371:17]
rvclkhdr_2.io.scan_mode <= _T_1946 @[lib.scala 372:24]
reg _T_1947 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_1947 <= _T_1943 @[lib.scala 374:16]
rvclkhdr_2.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_2.io.en <= _T_1945 @[lib.scala 380:17]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
reg _T_1947 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_1947 <= _T_1943 @[lib.scala 383:16]
ld_sec_addr_hi_r_ff <= _T_1947 @[lsu_dccm_ctl.scala 285:25]
node _T_1948 = bits(io.lsu_addr_r, 15, 0) @[lsu_dccm_ctl.scala 286:48]
node _T_1949 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 286:90]
node _T_1950 = bits(_T_1949, 0, 0) @[lib.scala 8:44]
node _T_1951 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 286:128]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 377:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
rvclkhdr_3.io.en <= _T_1950 @[lib.scala 371:17]
rvclkhdr_3.io.scan_mode <= _T_1951 @[lib.scala 372:24]
reg _T_1952 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
_T_1952 <= _T_1948 @[lib.scala 374:16]
rvclkhdr_3.io.clk <= clock @[lib.scala 379:18]
rvclkhdr_3.io.en <= _T_1950 @[lib.scala 380:17]
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 381:24]
reg _T_1952 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 383:16]
_T_1952 <= _T_1948 @[lib.scala 383:16]
ld_sec_addr_lo_r_ff <= _T_1952 @[lsu_dccm_ctl.scala 286:25]

81
lsu_dccm_ctl.v
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@ -1,8 +1,7 @@
module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
@ -17,7 +16,7 @@ module rvclkhdr(
assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module lsu_dccm_ctl(
input clock,
@ -171,22 +170,18 @@ module lsu_dccm_ctl(
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_io_en; // @[lib.scala 368:23]
wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_1_io_en; // @[lib.scala 368:23]
wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_2_io_en; // @[lib.scala 368:23]
wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 368:23]
wire rvclkhdr_3_io_en; // @[lib.scala 368:23]
wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
wire rvclkhdr_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_io_en; // @[lib.scala 377:23]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_1_io_en; // @[lib.scala 377:23]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_2_io_en; // @[lib.scala 377:23]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 377:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 377:23]
wire rvclkhdr_3_io_en; // @[lib.scala 377:23]
wire [63:0] picm_rd_data_m = {io_lsu_pic_picm_rd_data,io_lsu_pic_picm_rd_data}; // @[Cat.scala 29:58]
wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58]
wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58]
@ -531,7 +526,7 @@ module lsu_dccm_ctl(
wire [63:0] lsu_rdata_m = _T_805 | _T_809; // @[Bitwise.scala 103:39]
wire _T_812 = io_addr_in_pic_m | io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 157:123]
wire _T_813 = _T & _T_812; // @[lsu_dccm_ctl.scala 157:103]
reg [63:0] _T_817; // @[lib.scala 374:16]
reg [63:0] _T_817; // @[lib.scala 383:16]
wire [3:0] _GEN_58 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_dccm_ctl.scala 158:49]
wire [5:0] _T_819 = 4'h8 * _GEN_58; // @[lsu_dccm_ctl.scala 158:49]
wire [63:0] _T_820 = lsu_rdata_m >> _T_819; // @[lsu_dccm_ctl.scala 158:43]
@ -601,8 +596,8 @@ module lsu_dccm_ctl(
wire _T_903 = lsu_dccm_rden_d & _T_902; // @[lsu_dccm_ctl.scala 180:22]
wire _T_904 = _T_894 | _T_903; // @[lsu_dccm_ctl.scala 179:124]
wire _T_906 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[lsu_dccm_ctl.scala 185:41]
reg [15:0] ld_sec_addr_lo_r_ff; // @[lib.scala 374:16]
reg [15:0] ld_sec_addr_hi_r_ff; // @[lib.scala 374:16]
reg [15:0] ld_sec_addr_lo_r_ff; // @[lib.scala 383:16]
reg [15:0] ld_sec_addr_hi_r_ff; // @[lib.scala 383:16]
wire [15:0] _T_913 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[lsu_dccm_ctl.scala 189:8]
wire [15:0] _T_917 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 190:8]
wire [15:0] _T_923 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[lsu_dccm_ctl.scala 193:8]
@ -834,7 +829,7 @@ module lsu_dccm_ctl(
wire [31:0] _T_1428 = _T_1426 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
wire _T_1430 = io_ldst_dual_m & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 262:295]
wire _T_1431 = _T_1430 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 262:316]
reg [31:0] _T_1435; // @[lib.scala 374:16]
reg [31:0] _T_1435; // @[lib.scala 383:16]
wire _T_1436 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[lsu_dccm_ctl.scala 263:105]
wire [7:0] store_byteen_ext_r = {{1'd0}, _T_998}; // @[lsu_dccm_ctl.scala 222:22]
wire _T_1438 = ~store_byteen_ext_r[0]; // @[lsu_dccm_ctl.scala 263:131]
@ -1067,29 +1062,25 @@ module lsu_dccm_ctl(
wire [31:0] _T_1931 = {17'h0,_T_1930}; // @[Cat.scala 29:58]
reg _T_1938; // @[lsu_dccm_ctl.scala 280:61]
reg _T_1939; // @[lsu_dccm_ctl.scala 281:61]
rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_1 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_2 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
rvclkhdr rvclkhdr_3 ( // @[lib.scala 377:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
.io_en(rvclkhdr_3_io_en)
);
assign io_dccm_rdata_hi_r = 32'h0; // @[lsu_dccm_ctl.scala 150:28]
assign io_dccm_rdata_lo_r = 32'h0; // @[lsu_dccm_ctl.scala 149:28]
@ -1131,18 +1122,14 @@ module lsu_dccm_ctl(
assign io_lsu_pic_picm_rdaddr = 32'hf00c0000 | _T_1924; // @[lsu_dccm_ctl.scala 275:35]
assign io_lsu_pic_picm_wraddr = 32'hf00c0000 | _T_1931; // @[lsu_dccm_ctl.scala 276:35]
assign io_lsu_pic_picm_wr_data = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[lsu_dccm_ctl.scala 278:35]
assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_io_en = _T_813 | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_1_io_en = _T_1431 | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
assign rvclkhdr_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_io_en = _T_813 | io_clk_override; // @[lib.scala 380:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_1_io_en = _T_1431 | io_clk_override; // @[lib.scala 380:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 380:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 379:18]
assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 380:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif

4
src/main/scala/lsu/lsu_dccm_ctl.scala
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@ -297,4 +297,6 @@ class lsu_dccm_ctl extends Module with RequireAsyncReset with lib
}
}
object dccm_ctl extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_dccm_ctl()))
}

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target/scala-2.12/classes/lsu/dccm_ctl$.class Normal file
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target/scala-2.12/classes/lsu/dccm_ctl$delayedInit$body.class Normal file
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target/scala-2.12/classes/lsu/dccm_ctl.class Normal file
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target/scala-2.12/classes/lsu/lsu_dccm_ctl.class
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