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DEC bug removed

This commit is contained in:
​Laraib Khan 2020-12-17 15:24:04 +05:00
parent d2c1fc52db
commit 1badd94e5d
4 changed files with 2594 additions and 2593 deletions
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3543
quasar_wrapper.fir
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1640
quasar_wrapper.v
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4
src/main/scala/dec/dec_tlu_ctl.scala
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@ -2126,7 +2126,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm
val dicad1_raw = WireInit(UInt(7.W),0.U) val dicad1_raw = WireInit(UInt(7.W),0.U)
val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1)
val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(70,64)) val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(6,0), io.ifu_ic_debug_rd_data(70,64))
dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)}
dicad1 := Cat(0.U(25.W), dicad1_raw) dicad1 := Cat(0.U(25.W), dicad1_raw)
@ -2498,7 +2498,7 @@ for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)}
io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W),
io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W),
io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W),
io.csr_pkt.csr_mimpid.asBool -> 0x1.U(32.W), io.csr_pkt.csr_mimpid.asBool -> 0x2.U(32.W),
io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)),
io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)),
io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)),

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target/scala-2.12/classes/dec/csr_tlu.class
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