diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir
index 1ede13f4..c97b0322 100644
--- a/el2_ifu_mem_ctl.fir
+++ b/el2_ifu_mem_ctl.fir
@@ -461,12 +461,12 @@ circuit el2_ifu_mem_ctl :
     node imb_in = mux(_T_269, imb_scnd_ff, _T_271) @[el2_ifu_mem_ctl.scala 292:19]
     wire ifu_wr_cumulative_err_data : UInt<1>
     ifu_wr_cumulative_err_data <= UInt<1>("h00")
-    node _T_272 = bits(imb_ff, 12, 6) @[el2_ifu_mem_ctl.scala 294:38]
-    node _T_273 = bits(imb_scnd_ff, 12, 6) @[el2_ifu_mem_ctl.scala 294:89]
-    node _T_274 = eq(_T_272, _T_273) @[el2_ifu_mem_ctl.scala 294:75]
-    node _T_275 = and(_T_274, scnd_miss_req) @[el2_ifu_mem_ctl.scala 294:127]
-    node _T_276 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 294:145]
-    node scnd_miss_index_match = and(_T_275, _T_276) @[el2_ifu_mem_ctl.scala 294:143]
+    node _T_272 = bits(imb_ff, 11, 5) @[el2_ifu_mem_ctl.scala 294:38]
+    node _T_273 = bits(imb_scnd_ff, 11, 5) @[el2_ifu_mem_ctl.scala 294:93]
+    node _T_274 = eq(_T_272, _T_273) @[el2_ifu_mem_ctl.scala 294:79]
+    node _T_275 = and(_T_274, scnd_miss_req) @[el2_ifu_mem_ctl.scala 294:135]
+    node _T_276 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 294:153]
+    node scnd_miss_index_match = and(_T_275, _T_276) @[el2_ifu_mem_ctl.scala 294:151]
     wire way_status_mb_ff : UInt<1>
     way_status_mb_ff <= UInt<1>("h00")
     wire way_status_rep_new : UInt<1>
diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v
index 32590062..0031366a 100644
--- a/el2_ifu_mem_ctl.v
+++ b/el2_ifu_mem_ctl.v
@@ -1781,16 +1781,16 @@ module el2_ifu_mem_ctl(
   wire  _T_264 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 290:94]
   wire  _T_268 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 291:84]
   wire  uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[el2_ifu_mem_ctl.scala 291:32]
-  wire  _T_274 = imb_ff[12:6] == imb_scnd_ff[12:6]; // @[el2_ifu_mem_ctl.scala 294:75]
-  wire  _T_275 = _T_274 & scnd_miss_req; // @[el2_ifu_mem_ctl.scala 294:127]
+  wire  _T_274 = imb_ff[11:5] == imb_scnd_ff[11:5]; // @[el2_ifu_mem_ctl.scala 294:79]
+  wire  _T_275 = _T_274 & scnd_miss_req; // @[el2_ifu_mem_ctl.scala 294:135]
   reg [1:0] ifu_bus_rresp_ff; // @[Reg.scala 27:20]
   wire  _T_2662 = |ifu_bus_rresp_ff; // @[el2_ifu_mem_ctl.scala 622:48]
   wire  _T_2663 = _T_2662 & ifu_bus_rvalid_ff; // @[el2_ifu_mem_ctl.scala 622:52]
   wire  bus_ifu_wr_data_error_ff = _T_2663 & miss_pending; // @[el2_ifu_mem_ctl.scala 622:73]
   reg  ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 367:61]
   wire  ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 366:55]
-  wire  _T_276 = ~ifu_wr_cumulative_err_data; // @[el2_ifu_mem_ctl.scala 294:145]
-  wire  scnd_miss_index_match = _T_275 & _T_276; // @[el2_ifu_mem_ctl.scala 294:143]
+  wire  _T_276 = ~ifu_wr_cumulative_err_data; // @[el2_ifu_mem_ctl.scala 294:153]
+  wire  scnd_miss_index_match = _T_275 & _T_276; // @[el2_ifu_mem_ctl.scala 294:151]
   wire  _T_277 = ~scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 297:47]
   wire  _T_278 = scnd_miss_req & _T_277; // @[el2_ifu_mem_ctl.scala 297:45]
   wire  _T_280 = scnd_miss_req & scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 298:26]
diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
index 4a98f29b..b0781317 100644
--- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
@@ -291,7 +291,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   val uncacheable_miss_in = Mux(scnd_miss_req.asBool, uncacheable_miss_scnd_ff, Mux(sel_hold_imb.asBool, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf))
   val imb_in = Mux(scnd_miss_req.asBool, imb_scnd_ff, Mux(sel_hold_imb.asBool, imb_ff, io.ifc_fetch_addr_bf))
   val ifu_wr_cumulative_err_data = WireInit(Bool(), 0.U)
-  val scnd_miss_index_match = (imb_ff(ICACHE_INDEX_HI,ICACHE_TAG_INDEX_LO)===imb_scnd_ff(ICACHE_INDEX_HI,ICACHE_TAG_INDEX_LO))& scnd_miss_req & !ifu_wr_cumulative_err_data
+  val scnd_miss_index_match = (imb_ff(ICACHE_INDEX_HI-1,ICACHE_TAG_INDEX_LO-1)===imb_scnd_ff(ICACHE_INDEX_HI-1,ICACHE_TAG_INDEX_LO-1))& scnd_miss_req & !ifu_wr_cumulative_err_data
   val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
   val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
   val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff,
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
index 4ffd7486..0f08d305 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class differ