From 1c84acbbfc679ee58564ccca7606210206edea67 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Fri, 8 Jan 2021 09:09:54 +0500 Subject: [PATCH] All 5 dividers added with LEC --- exu_div_ctl.fir | 3588 +++++++++-------- exu_div_ctl.v | 1428 +++---- src/main/scala/exu/exu_div_ctl.scala | 414 +- .../classes/exu/exu_div_cls$$anon$7.class | Bin 1694 -> 1694 bytes .../scala-2.12/classes/exu/exu_div_cls.class | Bin 11057 -> 11057 bytes .../exu_div_existing_1bit_cheapshortq.class | Bin 112188 -> 112188 bytes .../exu_div_new_1bit_fullshortq$$anon$3.class | Bin 2817 -> 2817 bytes .../exu/exu_div_new_1bit_fullshortq.class | Bin 104405 -> 104405 bytes .../exu_div_new_2bit_fullshortq$$anon$4.class | Bin 2817 -> 2817 bytes .../exu/exu_div_new_2bit_fullshortq.class | Bin 108459 -> 108459 bytes .../exu_div_new_3bit_fullshortq$$anon$5.class | Bin 2817 -> 2817 bytes .../exu/exu_div_new_3bit_fullshortq.class | Bin 116620 -> 116620 bytes .../exu_div_new_4bit_fullshortq$$anon$6.class | Bin 2817 -> 2817 bytes .../exu/exu_div_new_4bit_fullshortq.class | Bin 126213 -> 126062 bytes 14 files changed, 2722 insertions(+), 2708 deletions(-) diff --git a/exu_div_ctl.fir b/exu_div_ctl.fir index ef8c60a8..71c1f16a 100644 --- a/exu_div_ctl.fir +++ b/exu_div_ctl.fir @@ -9,70 +9,70 @@ circuit exu_div_ctl : cls_zeros <= UInt<5>("h00") wire cls_ones : UInt<5> cls_ones <= UInt<5>("h00") - node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 956:54] - node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 956:54] - node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 956:54] - node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 956:54] - node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 956:54] - node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 956:54] - node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 956:54] - node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 956:54] - node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 956:54] - node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 956:54] - node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 956:54] - node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 956:54] - node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 956:54] - node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 956:54] - node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 956:54] - node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 956:54] - node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 956:54] - node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 956:54] - node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 956:54] - node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 956:54] - node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 956:54] - node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 956:54] - node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 956:54] - node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 956:54] - node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 956:54] - node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 956:54] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 956:54] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 956:54] - node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 956:54] - node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 956:54] - node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 956:54] - node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 956:54] - node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] + node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 950:54] + node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 950:54] + node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 950:54] + node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 950:54] + node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 950:54] + node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 950:54] + node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 950:54] + node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 950:54] + node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 950:54] + node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 950:54] + node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 950:54] + node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 950:54] + node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 950:54] + node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 950:54] + node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 950:54] + node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 950:54] + node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 950:54] + node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 950:54] + node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 950:54] + node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 950:54] + node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 950:54] + node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 950:54] + node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 950:54] + node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 950:54] + node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 950:54] + node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 950:54] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 950:54] + node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 950:54] + node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 950:54] + node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 950:54] + node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 950:54] + node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 950:54] + node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -138,167 +138,167 @@ circuit exu_div_ctl : node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72] wire _T_127 : UInt<5> @[Mux.scala 27:72] _T_127 <= _T_126 @[Mux.scala 27:72] - cls_zeros <= _T_127 @[exu_div_ctl.scala 956:13] - node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 958:18] - node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 958:25] - when _T_129 : @[exu_div_ctl.scala 958:44] - cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 958:55] - skip @[exu_div_ctl.scala 958:44] - else : @[exu_div_ctl.scala 959:15] - node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 959:66] + cls_zeros <= _T_127 @[exu_div_ctl.scala 950:13] + node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 952:18] + node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 952:25] + when _T_129 : @[exu_div_ctl.scala 952:44] + cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 952:55] + skip @[exu_div_ctl.scala 952:44] + else : @[exu_div_ctl.scala 953:15] + node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 953:66] node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58] - node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 959:76] - node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 959:66] + node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 953:76] + node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 953:66] node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 959:76] - node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 959:66] + node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 953:76] + node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 953:66] node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 959:76] - node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 959:66] + node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 953:76] + node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 953:66] node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 959:76] - node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 959:66] + node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 953:76] + node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 953:66] node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 959:76] - node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 959:66] + node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 953:76] + node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 953:66] node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 959:76] - node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 959:66] + node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 953:76] + node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 953:66] node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 959:76] - node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 959:66] + node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 953:76] + node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 953:66] node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 959:76] - node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 959:66] + node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 953:76] + node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 953:66] node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 959:76] - node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 959:66] + node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 953:76] + node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 953:66] node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 959:76] - node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 959:66] + node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 953:76] + node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 953:66] node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12] node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 959:76] - node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 959:66] + node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 953:76] + node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 953:66] node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 959:76] - node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 959:66] + node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 953:76] + node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 953:66] node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12] node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 959:76] - node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 959:66] + node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 953:76] + node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 953:66] node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12] node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 959:76] - node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 959:66] + node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 953:76] + node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 953:66] node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12] node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 959:76] - node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 959:66] + node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 953:76] + node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 953:66] node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 959:76] - node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 959:66] + node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 953:76] + node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 953:66] node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 959:76] - node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 959:66] + node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 953:76] + node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 953:66] node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12] node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 959:76] - node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 959:66] + node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 953:76] + node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 953:66] node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 959:76] - node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 959:66] + node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 953:76] + node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 953:66] node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 959:76] - node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 959:66] + node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 953:76] + node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 953:66] node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12] node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 959:76] - node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 959:66] + node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 953:76] + node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 953:66] node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12] node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 959:76] - node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 959:66] + node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 953:76] + node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 953:66] node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12] node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 959:76] - node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 959:66] + node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 953:76] + node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 953:66] node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 959:76] - node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 959:66] + node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 953:76] + node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 953:66] node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12] node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 959:76] - node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 959:66] + node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 953:76] + node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 953:66] node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 959:76] - node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 959:66] + node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 953:76] + node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 953:66] node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12] node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 959:76] - node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 959:66] + node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 953:76] + node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 953:66] node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 959:76] - node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 959:66] + node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 953:76] + node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 953:66] node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 959:76] - node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 959:66] + node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 953:76] + node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 953:66] node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 959:76] - node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 959:66] + node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 953:76] + node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 953:66] node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 959:76] - node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 959:102] + node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 953:76] + node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 953:102] node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -362,11 +362,11 @@ circuit exu_div_ctl : node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72] wire _T_345 : UInt<5> @[Mux.scala 27:72] _T_345 <= _T_344 @[Mux.scala 27:72] - cls_ones <= _T_345 @[exu_div_ctl.scala 959:25] - skip @[exu_div_ctl.scala 959:15] - node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 960:27] - node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 960:16] - io.cls <= _T_347 @[exu_div_ctl.scala 960:10] + cls_ones <= _T_345 @[exu_div_ctl.scala 953:25] + skip @[exu_div_ctl.scala 953:15] + node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 954:42] + node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 954:31] + io.cls <= _T_347 @[exu_div_ctl.scala 954:25] module exu_div_cls_1 : input clock : Clock @@ -377,70 +377,70 @@ circuit exu_div_ctl : cls_zeros <= UInt<5>("h00") wire cls_ones : UInt<5> cls_ones <= UInt<5>("h00") - node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 956:54] - node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 956:54] - node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 956:54] - node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 956:54] - node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 956:54] - node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 956:54] - node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 956:54] - node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 956:54] - node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 956:54] - node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 956:54] - node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 956:54] - node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 956:54] - node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 956:54] - node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 956:54] - node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 956:54] - node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 956:54] - node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 956:54] - node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 956:54] - node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 956:54] - node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 956:54] - node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 956:54] - node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 956:54] - node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 956:54] - node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 956:54] - node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 956:54] - node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 956:54] - node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 956:54] - node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 956:54] - node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 956:54] - node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 956:54] - node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 956:54] - node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] - node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 956:54] - node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 956:63] + node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 950:54] + node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 950:54] + node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 950:54] + node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 950:54] + node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 950:54] + node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 950:54] + node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 950:54] + node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 950:54] + node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 950:54] + node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 950:54] + node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 950:54] + node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 950:54] + node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 950:54] + node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 950:54] + node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 950:54] + node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 950:54] + node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 950:54] + node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 950:54] + node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 950:54] + node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 950:54] + node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 950:54] + node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 950:54] + node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 950:54] + node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 950:54] + node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 950:54] + node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 950:54] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 950:54] + node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 950:54] + node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 950:54] + node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 950:54] + node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 950:54] + node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] + node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 950:54] + node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 950:63] node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -506,167 +506,167 @@ circuit exu_div_ctl : node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72] wire _T_127 : UInt<5> @[Mux.scala 27:72] _T_127 <= _T_126 @[Mux.scala 27:72] - cls_zeros <= _T_127 @[exu_div_ctl.scala 956:13] - node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 958:18] - node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 958:25] - when _T_129 : @[exu_div_ctl.scala 958:44] - cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 958:55] - skip @[exu_div_ctl.scala 958:44] - else : @[exu_div_ctl.scala 959:15] - node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 959:66] + cls_zeros <= _T_127 @[exu_div_ctl.scala 950:13] + node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 952:18] + node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 952:25] + when _T_129 : @[exu_div_ctl.scala 952:44] + cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 952:55] + skip @[exu_div_ctl.scala 952:44] + else : @[exu_div_ctl.scala 953:15] + node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 953:66] node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58] - node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 959:76] - node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 959:66] + node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 953:76] + node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 953:66] node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 959:76] - node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 959:66] + node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 953:76] + node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 953:66] node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 959:76] - node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 959:66] + node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 953:76] + node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 953:66] node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 959:76] - node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 959:66] + node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 953:76] + node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 953:66] node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 959:76] - node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 959:66] + node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 953:76] + node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 953:66] node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 959:76] - node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 959:66] + node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 953:76] + node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 953:66] node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 959:76] - node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 959:66] + node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 953:76] + node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 953:66] node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 959:76] - node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 959:66] + node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 953:76] + node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 953:66] node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 959:76] - node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 959:66] + node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 953:76] + node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 953:66] node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 959:76] - node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 959:66] + node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 953:76] + node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 953:66] node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12] node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 959:76] - node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 959:66] + node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 953:76] + node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 953:66] node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 959:76] - node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 959:66] + node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 953:76] + node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 953:66] node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12] node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 959:76] - node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 959:66] + node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 953:76] + node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 953:66] node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12] node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 959:76] - node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 959:66] + node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 953:76] + node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 953:66] node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12] node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 959:76] - node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 959:66] + node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 953:76] + node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 953:66] node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 959:76] - node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 959:66] + node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 953:76] + node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 953:66] node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 959:76] - node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 959:66] + node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 953:76] + node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 953:66] node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12] node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 959:76] - node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 959:66] + node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 953:76] + node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 953:66] node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 959:76] - node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 959:66] + node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 953:76] + node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 953:66] node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 959:76] - node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 959:66] + node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 953:76] + node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 953:66] node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12] node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 959:76] - node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 959:66] + node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 953:76] + node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 953:66] node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12] node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 959:76] - node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 959:66] + node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 953:76] + node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 953:66] node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12] node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 959:76] - node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 959:66] + node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 953:76] + node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 953:66] node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 959:76] - node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 959:66] + node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 953:76] + node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 953:66] node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12] node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 959:76] - node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 959:66] + node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 953:76] + node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 953:66] node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 959:76] - node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 959:66] + node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 953:76] + node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 953:66] node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12] node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 959:76] - node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 959:66] + node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 953:76] + node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 953:66] node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 959:76] - node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 959:66] + node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 953:76] + node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 953:66] node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 959:76] - node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 959:66] + node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 953:76] + node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 953:66] node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 959:76] - node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 959:102] - node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 959:66] + node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 953:76] + node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 953:102] + node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 953:66] node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 959:76] - node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 959:102] + node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 953:76] + node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 953:102] node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -730,11 +730,11 @@ circuit exu_div_ctl : node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72] wire _T_345 : UInt<5> @[Mux.scala 27:72] _T_345 <= _T_344 @[Mux.scala 27:72] - cls_ones <= _T_345 @[exu_div_ctl.scala 959:25] - skip @[exu_div_ctl.scala 959:15] - node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 960:27] - node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 960:16] - io.cls <= _T_347 @[exu_div_ctl.scala 960:10] + cls_ones <= _T_345 @[exu_div_ctl.scala 953:25] + skip @[exu_div_ctl.scala 953:15] + node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 954:42] + node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 954:31] + io.cls <= _T_347 @[exu_div_ctl.scala 954:25] extmodule gated_latch : output Q : Clock @@ -1043,480 +1043,480 @@ circuit exu_div_ctl : shortq_decode <= UInt<5>("h00") wire shortq_shift_ff : UInt<5> shortq_shift_ff <= UInt<5>("h00") - node _T = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 777:35] - node valid_ff_in = and(io.valid_in, _T) @[exu_div_ctl.scala 777:33] - node _T_1 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 778:35] - node _T_2 = bits(control_ff, 2, 2) @[exu_div_ctl.scala 778:60] - node _T_3 = and(_T_1, _T_2) @[exu_div_ctl.scala 778:48] - node _T_4 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 778:80] - node _T_5 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 778:112] - node _T_6 = and(_T_4, _T_5) @[exu_div_ctl.scala 778:96] - node _T_7 = or(_T_3, _T_6) @[exu_div_ctl.scala 778:65] - node _T_8 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 778:120] - node _T_9 = bits(control_ff, 1, 1) @[exu_div_ctl.scala 778:145] - node _T_10 = and(_T_8, _T_9) @[exu_div_ctl.scala 778:133] - node _T_11 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 778:165] - node _T_12 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 778:197] - node _T_13 = and(_T_11, _T_12) @[exu_div_ctl.scala 778:181] - node _T_14 = or(_T_10, _T_13) @[exu_div_ctl.scala 778:150] - node _T_15 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 778:205] - node _T_16 = bits(control_ff, 0, 0) @[exu_div_ctl.scala 778:230] - node _T_17 = and(_T_15, _T_16) @[exu_div_ctl.scala 778:218] - node _T_18 = and(io.valid_in, io.rem_in) @[exu_div_ctl.scala 778:250] - node _T_19 = or(_T_17, _T_18) @[exu_div_ctl.scala 778:235] + node _T = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 776:44] + node valid_ff_in = and(io.valid_in, _T) @[exu_div_ctl.scala 776:42] + node _T_1 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 777:35] + node _T_2 = bits(control_ff, 2, 2) @[exu_div_ctl.scala 777:60] + node _T_3 = and(_T_1, _T_2) @[exu_div_ctl.scala 777:48] + node _T_4 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 777:80] + node _T_5 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 777:112] + node _T_6 = and(_T_4, _T_5) @[exu_div_ctl.scala 777:96] + node _T_7 = or(_T_3, _T_6) @[exu_div_ctl.scala 777:65] + node _T_8 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 777:120] + node _T_9 = bits(control_ff, 1, 1) @[exu_div_ctl.scala 777:145] + node _T_10 = and(_T_8, _T_9) @[exu_div_ctl.scala 777:133] + node _T_11 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 777:165] + node _T_12 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 777:197] + node _T_13 = and(_T_11, _T_12) @[exu_div_ctl.scala 777:181] + node _T_14 = or(_T_10, _T_13) @[exu_div_ctl.scala 777:150] + node _T_15 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 777:205] + node _T_16 = bits(control_ff, 0, 0) @[exu_div_ctl.scala 777:230] + node _T_17 = and(_T_15, _T_16) @[exu_div_ctl.scala 777:218] + node _T_18 = and(io.valid_in, io.rem_in) @[exu_div_ctl.scala 777:250] + node _T_19 = or(_T_17, _T_18) @[exu_div_ctl.scala 777:235] node _T_20 = cat(_T_7, _T_14) @[Cat.scala 29:58] node control_in = cat(_T_20, _T_19) @[Cat.scala 29:58] - node dividend_sign_ff = bits(control_ff, 2, 2) @[exu_div_ctl.scala 779:40] - node divisor_sign_ff = bits(control_ff, 1, 1) @[exu_div_ctl.scala 780:40] - node rem_ff = bits(control_ff, 0, 0) @[exu_div_ctl.scala 781:40] - node _T_21 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 782:47] - node _T_22 = eq(_T_21, UInt<1>("h00")) @[exu_div_ctl.scala 782:54] - node by_zero_case = and(valid_ff, _T_22) @[exu_div_ctl.scala 782:40] - node _T_23 = bits(a_ff, 31, 4) @[exu_div_ctl.scala 784:30] - node _T_24 = eq(_T_23, UInt<1>("h00")) @[exu_div_ctl.scala 784:37] - node _T_25 = bits(b_ff, 31, 4) @[exu_div_ctl.scala 784:53] - node _T_26 = eq(_T_25, UInt<1>("h00")) @[exu_div_ctl.scala 784:60] - node _T_27 = and(_T_24, _T_26) @[exu_div_ctl.scala 784:46] - node _T_28 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 784:71] - node _T_29 = and(_T_27, _T_28) @[exu_div_ctl.scala 784:69] - node _T_30 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 784:87] - node _T_31 = and(_T_29, _T_30) @[exu_div_ctl.scala 784:85] - node _T_32 = and(_T_31, valid_ff) @[exu_div_ctl.scala 784:95] - node _T_33 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 784:108] - node _T_34 = and(_T_32, _T_33) @[exu_div_ctl.scala 784:106] - node _T_35 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 785:11] - node _T_36 = eq(_T_35, UInt<1>("h00")) @[exu_div_ctl.scala 785:18] - node _T_37 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 785:29] - node _T_38 = and(_T_36, _T_37) @[exu_div_ctl.scala 785:27] - node _T_39 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 785:45] - node _T_40 = and(_T_38, _T_39) @[exu_div_ctl.scala 785:43] - node _T_41 = and(_T_40, valid_ff) @[exu_div_ctl.scala 785:53] - node _T_42 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 785:66] - node _T_43 = and(_T_41, _T_42) @[exu_div_ctl.scala 785:64] - node smallnum_case = or(_T_34, _T_43) @[exu_div_ctl.scala 784:120] - node _T_44 = orr(count_ff) @[exu_div_ctl.scala 786:42] - node running_state = or(_T_44, shortq_enable_ff) @[exu_div_ctl.scala 786:45] - node _T_45 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 787:43] - node _T_46 = or(_T_45, io.cancel) @[exu_div_ctl.scala 787:54] - node _T_47 = or(_T_46, running_state) @[exu_div_ctl.scala 787:66] - node misc_enable = or(_T_47, finish_ff) @[exu_div_ctl.scala 787:82] - node _T_48 = or(smallnum_case, by_zero_case) @[exu_div_ctl.scala 788:45] - node _T_49 = eq(count_ff, UInt<6>("h020")) @[exu_div_ctl.scala 788:72] - node finish_raw = or(_T_48, _T_49) @[exu_div_ctl.scala 788:60] - node _T_50 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 789:43] - node finish = and(finish_raw, _T_50) @[exu_div_ctl.scala 789:41] - node _T_51 = or(valid_ff, running_state) @[exu_div_ctl.scala 790:40] - node _T_52 = eq(finish, UInt<1>("h00")) @[exu_div_ctl.scala 790:59] - node _T_53 = and(_T_51, _T_52) @[exu_div_ctl.scala 790:57] - node _T_54 = eq(finish_ff, UInt<1>("h00")) @[exu_div_ctl.scala 790:69] - node _T_55 = and(_T_53, _T_54) @[exu_div_ctl.scala 790:67] - node _T_56 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 790:82] - node _T_57 = and(_T_55, _T_56) @[exu_div_ctl.scala 790:80] - node _T_58 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 790:95] - node count_enable = and(_T_57, _T_58) @[exu_div_ctl.scala 790:93] + node dividend_sign_ff = bits(control_ff, 2, 2) @[exu_div_ctl.scala 778:40] + node divisor_sign_ff = bits(control_ff, 1, 1) @[exu_div_ctl.scala 779:40] + node rem_ff = bits(control_ff, 0, 0) @[exu_div_ctl.scala 780:40] + node _T_21 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 781:47] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[exu_div_ctl.scala 781:54] + node by_zero_case = and(valid_ff, _T_22) @[exu_div_ctl.scala 781:40] + node _T_23 = bits(a_ff, 31, 4) @[exu_div_ctl.scala 783:30] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[exu_div_ctl.scala 783:37] + node _T_25 = bits(b_ff, 31, 4) @[exu_div_ctl.scala 783:53] + node _T_26 = eq(_T_25, UInt<1>("h00")) @[exu_div_ctl.scala 783:60] + node _T_27 = and(_T_24, _T_26) @[exu_div_ctl.scala 783:46] + node _T_28 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 783:71] + node _T_29 = and(_T_27, _T_28) @[exu_div_ctl.scala 783:69] + node _T_30 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 783:87] + node _T_31 = and(_T_29, _T_30) @[exu_div_ctl.scala 783:85] + node _T_32 = and(_T_31, valid_ff) @[exu_div_ctl.scala 783:95] + node _T_33 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 783:108] + node _T_34 = and(_T_32, _T_33) @[exu_div_ctl.scala 783:106] + node _T_35 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 784:11] + node _T_36 = eq(_T_35, UInt<1>("h00")) @[exu_div_ctl.scala 784:18] + node _T_37 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 784:29] + node _T_38 = and(_T_36, _T_37) @[exu_div_ctl.scala 784:27] + node _T_39 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 784:45] + node _T_40 = and(_T_38, _T_39) @[exu_div_ctl.scala 784:43] + node _T_41 = and(_T_40, valid_ff) @[exu_div_ctl.scala 784:53] + node _T_42 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 784:66] + node _T_43 = and(_T_41, _T_42) @[exu_div_ctl.scala 784:64] + node smallnum_case = or(_T_34, _T_43) @[exu_div_ctl.scala 783:120] + node _T_44 = orr(count_ff) @[exu_div_ctl.scala 785:42] + node running_state = or(_T_44, shortq_enable_ff) @[exu_div_ctl.scala 785:45] + node _T_45 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 786:43] + node _T_46 = or(_T_45, io.cancel) @[exu_div_ctl.scala 786:54] + node _T_47 = or(_T_46, running_state) @[exu_div_ctl.scala 786:66] + node misc_enable = or(_T_47, finish_ff) @[exu_div_ctl.scala 786:82] + node _T_48 = or(smallnum_case, by_zero_case) @[exu_div_ctl.scala 787:45] + node _T_49 = eq(count_ff, UInt<6>("h020")) @[exu_div_ctl.scala 787:72] + node finish_raw = or(_T_48, _T_49) @[exu_div_ctl.scala 787:60] + node _T_50 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 788:43] + node finish = and(finish_raw, _T_50) @[exu_div_ctl.scala 788:41] + node _T_51 = or(valid_ff, running_state) @[exu_div_ctl.scala 789:40] + node _T_52 = eq(finish, UInt<1>("h00")) @[exu_div_ctl.scala 789:59] + node _T_53 = and(_T_51, _T_52) @[exu_div_ctl.scala 789:57] + node _T_54 = eq(finish_ff, UInt<1>("h00")) @[exu_div_ctl.scala 789:69] + node _T_55 = and(_T_53, _T_54) @[exu_div_ctl.scala 789:67] + node _T_56 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 789:82] + node _T_57 = and(_T_55, _T_56) @[exu_div_ctl.scala 789:80] + node _T_58 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 789:95] + node count_enable = and(_T_57, _T_58) @[exu_div_ctl.scala 789:93] node _T_59 = bits(count_enable, 0, 0) @[Bitwise.scala 72:15] node _T_60 = mux(_T_59, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] - node _T_61 = add(count_ff, UInt<7>("h04")) @[exu_div_ctl.scala 791:63] - node _T_62 = tail(_T_61, 1) @[exu_div_ctl.scala 791:63] + node _T_61 = add(count_ff, UInt<7>("h04")) @[exu_div_ctl.scala 790:63] + node _T_62 = tail(_T_61, 1) @[exu_div_ctl.scala 790:63] node _T_63 = cat(UInt<2>("h00"), shortq_shift_ff) @[Cat.scala 29:58] - node _T_64 = add(_T_62, _T_63) @[exu_div_ctl.scala 791:74] - node _T_65 = tail(_T_64, 1) @[exu_div_ctl.scala 791:74] - node count_in = and(_T_60, _T_65) @[exu_div_ctl.scala 791:51] - node a_enable = or(io.valid_in, running_state) @[exu_div_ctl.scala 792:43] - node _T_66 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 793:47] - node a_shift = and(running_state, _T_66) @[exu_div_ctl.scala 793:45] + node _T_64 = add(_T_62, _T_63) @[exu_div_ctl.scala 790:74] + node _T_65 = tail(_T_64, 1) @[exu_div_ctl.scala 790:74] + node count_in = and(_T_60, _T_65) @[exu_div_ctl.scala 790:51] + node a_enable = or(io.valid_in, running_state) @[exu_div_ctl.scala 791:43] + node _T_66 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 792:47] + node a_shift = and(running_state, _T_66) @[exu_div_ctl.scala 792:45] node _T_67 = bits(dividend_sign_ff, 0, 0) @[Bitwise.scala 72:15] node _T_68 = mux(_T_67, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12] - node _T_69 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 794:66] + node _T_69 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 793:66] node _T_70 = cat(_T_68, _T_69) @[Cat.scala 29:58] - node _T_71 = dshl(_T_70, shortq_shift_ff) @[exu_div_ctl.scala 794:74] - ar_shifted <= _T_71 @[exu_div_ctl.scala 794:28] - node _T_72 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 795:61] - node _T_73 = eq(_T_72, UInt<1>("h00")) @[exu_div_ctl.scala 795:42] - node b_twos_comp = and(valid_ff, _T_73) @[exu_div_ctl.scala 795:40] - node _T_74 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 796:62] - node _T_75 = eq(_T_74, UInt<1>("h00")) @[exu_div_ctl.scala 796:43] - node twos_comp_b_sel = and(valid_ff, _T_75) @[exu_div_ctl.scala 796:41] - node _T_76 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 797:30] - node _T_77 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 797:42] - node _T_78 = and(_T_76, _T_77) @[exu_div_ctl.scala 797:40] - node _T_79 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 797:71] - node _T_80 = and(_T_78, _T_79) @[exu_div_ctl.scala 797:50] - node _T_81 = eq(by_zero_case_ff, UInt<1>("h00")) @[exu_div_ctl.scala 797:92] - node twos_comp_q_sel = and(_T_80, _T_81) @[exu_div_ctl.scala 797:90] - node b_enable = or(io.valid_in, b_twos_comp) @[exu_div_ctl.scala 798:43] - node _T_82 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 799:43] - node rq_enable = or(_T_82, running_state) @[exu_div_ctl.scala 799:54] - node _T_83 = and(valid_ff, dividend_sign_ff) @[exu_div_ctl.scala 800:40] - node _T_84 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 800:61] - node r_sign_sel = and(_T_83, _T_84) @[exu_div_ctl.scala 800:59] - node _T_85 = eq(quotient_new, UInt<1>("h00")) @[exu_div_ctl.scala 801:71] - node _T_86 = and(running_state, _T_85) @[exu_div_ctl.scala 801:55] - node _T_87 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_0 = and(_T_86, _T_87) @[exu_div_ctl.scala 801:85] - node _T_88 = eq(quotient_new, UInt<1>("h01")) @[exu_div_ctl.scala 801:71] - node _T_89 = and(running_state, _T_88) @[exu_div_ctl.scala 801:55] - node _T_90 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_1 = and(_T_89, _T_90) @[exu_div_ctl.scala 801:85] - node _T_91 = eq(quotient_new, UInt<2>("h02")) @[exu_div_ctl.scala 801:71] - node _T_92 = and(running_state, _T_91) @[exu_div_ctl.scala 801:55] - node _T_93 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_2 = and(_T_92, _T_93) @[exu_div_ctl.scala 801:85] - node _T_94 = eq(quotient_new, UInt<2>("h03")) @[exu_div_ctl.scala 801:71] - node _T_95 = and(running_state, _T_94) @[exu_div_ctl.scala 801:55] - node _T_96 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_3 = and(_T_95, _T_96) @[exu_div_ctl.scala 801:85] - node _T_97 = eq(quotient_new, UInt<3>("h04")) @[exu_div_ctl.scala 801:71] - node _T_98 = and(running_state, _T_97) @[exu_div_ctl.scala 801:55] - node _T_99 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_4 = and(_T_98, _T_99) @[exu_div_ctl.scala 801:85] - node _T_100 = eq(quotient_new, UInt<3>("h05")) @[exu_div_ctl.scala 801:71] - node _T_101 = and(running_state, _T_100) @[exu_div_ctl.scala 801:55] - node _T_102 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_5 = and(_T_101, _T_102) @[exu_div_ctl.scala 801:85] - node _T_103 = eq(quotient_new, UInt<3>("h06")) @[exu_div_ctl.scala 801:71] - node _T_104 = and(running_state, _T_103) @[exu_div_ctl.scala 801:55] - node _T_105 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_6 = and(_T_104, _T_105) @[exu_div_ctl.scala 801:85] - node _T_106 = eq(quotient_new, UInt<3>("h07")) @[exu_div_ctl.scala 801:71] - node _T_107 = and(running_state, _T_106) @[exu_div_ctl.scala 801:55] - node _T_108 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_7 = and(_T_107, _T_108) @[exu_div_ctl.scala 801:85] - node _T_109 = eq(quotient_new, UInt<4>("h08")) @[exu_div_ctl.scala 801:71] - node _T_110 = and(running_state, _T_109) @[exu_div_ctl.scala 801:55] - node _T_111 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_8 = and(_T_110, _T_111) @[exu_div_ctl.scala 801:85] - node _T_112 = eq(quotient_new, UInt<4>("h09")) @[exu_div_ctl.scala 801:71] - node _T_113 = and(running_state, _T_112) @[exu_div_ctl.scala 801:55] - node _T_114 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_9 = and(_T_113, _T_114) @[exu_div_ctl.scala 801:85] - node _T_115 = eq(quotient_new, UInt<4>("h0a")) @[exu_div_ctl.scala 801:71] - node _T_116 = and(running_state, _T_115) @[exu_div_ctl.scala 801:55] - node _T_117 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_10 = and(_T_116, _T_117) @[exu_div_ctl.scala 801:85] - node _T_118 = eq(quotient_new, UInt<4>("h0b")) @[exu_div_ctl.scala 801:71] - node _T_119 = and(running_state, _T_118) @[exu_div_ctl.scala 801:55] - node _T_120 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_11 = and(_T_119, _T_120) @[exu_div_ctl.scala 801:85] - node _T_121 = eq(quotient_new, UInt<4>("h0c")) @[exu_div_ctl.scala 801:71] - node _T_122 = and(running_state, _T_121) @[exu_div_ctl.scala 801:55] - node _T_123 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_12 = and(_T_122, _T_123) @[exu_div_ctl.scala 801:85] - node _T_124 = eq(quotient_new, UInt<4>("h0d")) @[exu_div_ctl.scala 801:71] - node _T_125 = and(running_state, _T_124) @[exu_div_ctl.scala 801:55] - node _T_126 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_13 = and(_T_125, _T_126) @[exu_div_ctl.scala 801:85] - node _T_127 = eq(quotient_new, UInt<4>("h0e")) @[exu_div_ctl.scala 801:71] - node _T_128 = and(running_state, _T_127) @[exu_div_ctl.scala 801:55] - node _T_129 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_14 = and(_T_128, _T_129) @[exu_div_ctl.scala 801:85] - node _T_130 = eq(quotient_new, UInt<4>("h0f")) @[exu_div_ctl.scala 801:71] - node _T_131 = and(running_state, _T_130) @[exu_div_ctl.scala 801:55] - node _T_132 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 801:87] - node r_adder_sel_15 = and(_T_131, _T_132) @[exu_div_ctl.scala 801:85] - node _T_133 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 802:28] - node _T_134 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 802:39] + node _T_71 = dshl(_T_70, shortq_shift_ff) @[exu_div_ctl.scala 793:74] + ar_shifted <= _T_71 @[exu_div_ctl.scala 793:28] + node _T_72 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 794:61] + node _T_73 = eq(_T_72, UInt<1>("h00")) @[exu_div_ctl.scala 794:42] + node b_twos_comp = and(valid_ff, _T_73) @[exu_div_ctl.scala 794:40] + node _T_74 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 795:62] + node _T_75 = eq(_T_74, UInt<1>("h00")) @[exu_div_ctl.scala 795:43] + node twos_comp_b_sel = and(valid_ff, _T_75) @[exu_div_ctl.scala 795:41] + node _T_76 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 796:30] + node _T_77 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 796:42] + node _T_78 = and(_T_76, _T_77) @[exu_div_ctl.scala 796:40] + node _T_79 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 796:71] + node _T_80 = and(_T_78, _T_79) @[exu_div_ctl.scala 796:50] + node _T_81 = eq(by_zero_case_ff, UInt<1>("h00")) @[exu_div_ctl.scala 796:92] + node twos_comp_q_sel = and(_T_80, _T_81) @[exu_div_ctl.scala 796:90] + node b_enable = or(io.valid_in, b_twos_comp) @[exu_div_ctl.scala 797:43] + node _T_82 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 798:43] + node rq_enable = or(_T_82, running_state) @[exu_div_ctl.scala 798:54] + node _T_83 = and(valid_ff, dividend_sign_ff) @[exu_div_ctl.scala 799:40] + node _T_84 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 799:61] + node r_sign_sel = and(_T_83, _T_84) @[exu_div_ctl.scala 799:59] + node _T_85 = eq(quotient_new, UInt<1>("h00")) @[exu_div_ctl.scala 800:80] + node _T_86 = and(running_state, _T_85) @[exu_div_ctl.scala 800:64] + node _T_87 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_0 = and(_T_86, _T_87) @[exu_div_ctl.scala 800:94] + node _T_88 = eq(quotient_new, UInt<1>("h01")) @[exu_div_ctl.scala 800:80] + node _T_89 = and(running_state, _T_88) @[exu_div_ctl.scala 800:64] + node _T_90 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_1 = and(_T_89, _T_90) @[exu_div_ctl.scala 800:94] + node _T_91 = eq(quotient_new, UInt<2>("h02")) @[exu_div_ctl.scala 800:80] + node _T_92 = and(running_state, _T_91) @[exu_div_ctl.scala 800:64] + node _T_93 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_2 = and(_T_92, _T_93) @[exu_div_ctl.scala 800:94] + node _T_94 = eq(quotient_new, UInt<2>("h03")) @[exu_div_ctl.scala 800:80] + node _T_95 = and(running_state, _T_94) @[exu_div_ctl.scala 800:64] + node _T_96 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_3 = and(_T_95, _T_96) @[exu_div_ctl.scala 800:94] + node _T_97 = eq(quotient_new, UInt<3>("h04")) @[exu_div_ctl.scala 800:80] + node _T_98 = and(running_state, _T_97) @[exu_div_ctl.scala 800:64] + node _T_99 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_4 = and(_T_98, _T_99) @[exu_div_ctl.scala 800:94] + node _T_100 = eq(quotient_new, UInt<3>("h05")) @[exu_div_ctl.scala 800:80] + node _T_101 = and(running_state, _T_100) @[exu_div_ctl.scala 800:64] + node _T_102 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_5 = and(_T_101, _T_102) @[exu_div_ctl.scala 800:94] + node _T_103 = eq(quotient_new, UInt<3>("h06")) @[exu_div_ctl.scala 800:80] + node _T_104 = and(running_state, _T_103) @[exu_div_ctl.scala 800:64] + node _T_105 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_6 = and(_T_104, _T_105) @[exu_div_ctl.scala 800:94] + node _T_106 = eq(quotient_new, UInt<3>("h07")) @[exu_div_ctl.scala 800:80] + node _T_107 = and(running_state, _T_106) @[exu_div_ctl.scala 800:64] + node _T_108 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_7 = and(_T_107, _T_108) @[exu_div_ctl.scala 800:94] + node _T_109 = eq(quotient_new, UInt<4>("h08")) @[exu_div_ctl.scala 800:80] + node _T_110 = and(running_state, _T_109) @[exu_div_ctl.scala 800:64] + node _T_111 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_8 = and(_T_110, _T_111) @[exu_div_ctl.scala 800:94] + node _T_112 = eq(quotient_new, UInt<4>("h09")) @[exu_div_ctl.scala 800:80] + node _T_113 = and(running_state, _T_112) @[exu_div_ctl.scala 800:64] + node _T_114 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_9 = and(_T_113, _T_114) @[exu_div_ctl.scala 800:94] + node _T_115 = eq(quotient_new, UInt<4>("h0a")) @[exu_div_ctl.scala 800:80] + node _T_116 = and(running_state, _T_115) @[exu_div_ctl.scala 800:64] + node _T_117 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_10 = and(_T_116, _T_117) @[exu_div_ctl.scala 800:94] + node _T_118 = eq(quotient_new, UInt<4>("h0b")) @[exu_div_ctl.scala 800:80] + node _T_119 = and(running_state, _T_118) @[exu_div_ctl.scala 800:64] + node _T_120 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_11 = and(_T_119, _T_120) @[exu_div_ctl.scala 800:94] + node _T_121 = eq(quotient_new, UInt<4>("h0c")) @[exu_div_ctl.scala 800:80] + node _T_122 = and(running_state, _T_121) @[exu_div_ctl.scala 800:64] + node _T_123 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_12 = and(_T_122, _T_123) @[exu_div_ctl.scala 800:94] + node _T_124 = eq(quotient_new, UInt<4>("h0d")) @[exu_div_ctl.scala 800:80] + node _T_125 = and(running_state, _T_124) @[exu_div_ctl.scala 800:64] + node _T_126 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_13 = and(_T_125, _T_126) @[exu_div_ctl.scala 800:94] + node _T_127 = eq(quotient_new, UInt<4>("h0e")) @[exu_div_ctl.scala 800:80] + node _T_128 = and(running_state, _T_127) @[exu_div_ctl.scala 800:64] + node _T_129 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_14 = and(_T_128, _T_129) @[exu_div_ctl.scala 800:94] + node _T_130 = eq(quotient_new, UInt<4>("h0f")) @[exu_div_ctl.scala 800:80] + node _T_131 = and(running_state, _T_130) @[exu_div_ctl.scala 800:64] + node _T_132 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 800:96] + node r_adder_sel_15 = and(_T_131, _T_132) @[exu_div_ctl.scala 800:94] + node _T_133 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 801:38] + node _T_134 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 801:49] node _T_135 = cat(_T_133, _T_134) @[Cat.scala 29:58] - node _T_136 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 802:54] - node _T_137 = add(_T_135, _T_136) @[exu_div_ctl.scala 802:48] - node adder1_out = tail(_T_137, 1) @[exu_div_ctl.scala 802:48] - node _T_138 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 803:28] - node _T_139 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 803:39] + node _T_136 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 801:64] + node _T_137 = add(_T_135, _T_136) @[exu_div_ctl.scala 801:58] + node adder1_out = tail(_T_137, 1) @[exu_div_ctl.scala 801:58] + node _T_138 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 802:38] + node _T_139 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 802:49] node _T_140 = cat(_T_138, _T_139) @[Cat.scala 29:58] - node _T_141 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 803:58] + node _T_141 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 802:68] node _T_142 = cat(_T_141, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_143 = add(_T_140, _T_142) @[exu_div_ctl.scala 803:48] - node adder2_out = tail(_T_143, 1) @[exu_div_ctl.scala 803:48] - node _T_144 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 804:28] - node _T_145 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 804:39] + node _T_143 = add(_T_140, _T_142) @[exu_div_ctl.scala 802:58] + node adder2_out = tail(_T_143, 1) @[exu_div_ctl.scala 802:58] + node _T_144 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 803:38] + node _T_145 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 803:49] node _T_146 = cat(_T_144, _T_145) @[Cat.scala 29:58] - node _T_147 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 804:58] + node _T_147 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 803:68] node _T_148 = cat(_T_147, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_149 = add(_T_146, _T_148) @[exu_div_ctl.scala 804:48] - node _T_150 = tail(_T_149, 1) @[exu_div_ctl.scala 804:48] - node _T_151 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 804:76] - node _T_152 = add(_T_150, _T_151) @[exu_div_ctl.scala 804:70] - node adder3_out = tail(_T_152, 1) @[exu_div_ctl.scala 804:70] - node _T_153 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 805:29] - node _T_154 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 805:38] - node _T_155 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 805:49] + node _T_149 = add(_T_146, _T_148) @[exu_div_ctl.scala 803:58] + node _T_150 = tail(_T_149, 1) @[exu_div_ctl.scala 803:58] + node _T_151 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 803:86] + node _T_152 = add(_T_150, _T_151) @[exu_div_ctl.scala 803:80] + node adder3_out = tail(_T_152, 1) @[exu_div_ctl.scala 803:80] + node _T_153 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 804:38] + node _T_154 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 804:47] + node _T_155 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 804:58] node _T_156 = cat(_T_153, _T_154) @[Cat.scala 29:58] node _T_157 = cat(_T_156, _T_155) @[Cat.scala 29:58] - node _T_158 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 805:68] + node _T_158 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 804:77] node _T_159 = cat(_T_158, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_160 = add(_T_157, _T_159) @[exu_div_ctl.scala 805:58] - node adder4_out = tail(_T_160, 1) @[exu_div_ctl.scala 805:58] - node _T_161 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 806:29] - node _T_162 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 806:38] - node _T_163 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 806:49] + node _T_160 = add(_T_157, _T_159) @[exu_div_ctl.scala 804:67] + node adder4_out = tail(_T_160, 1) @[exu_div_ctl.scala 804:67] + node _T_161 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 805:38] + node _T_162 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 805:47] + node _T_163 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 805:58] node _T_164 = cat(_T_161, _T_162) @[Cat.scala 29:58] node _T_165 = cat(_T_164, _T_163) @[Cat.scala 29:58] - node _T_166 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 806:68] + node _T_166 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 805:77] node _T_167 = cat(_T_166, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_168 = add(_T_165, _T_167) @[exu_div_ctl.scala 806:58] - node _T_169 = tail(_T_168, 1) @[exu_div_ctl.scala 806:58] - node _T_170 = add(_T_169, b_ff) @[exu_div_ctl.scala 806:85] - node adder5_out = tail(_T_170, 1) @[exu_div_ctl.scala 806:85] - node _T_171 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 807:29] - node _T_172 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 807:38] - node _T_173 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 807:49] + node _T_168 = add(_T_165, _T_167) @[exu_div_ctl.scala 805:67] + node _T_169 = tail(_T_168, 1) @[exu_div_ctl.scala 805:67] + node _T_170 = add(_T_169, b_ff) @[exu_div_ctl.scala 805:94] + node adder5_out = tail(_T_170, 1) @[exu_div_ctl.scala 805:94] + node _T_171 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 806:38] + node _T_172 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 806:47] + node _T_173 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 806:58] node _T_174 = cat(_T_171, _T_172) @[Cat.scala 29:58] node _T_175 = cat(_T_174, _T_173) @[Cat.scala 29:58] - node _T_176 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 807:68] + node _T_176 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 806:77] node _T_177 = cat(_T_176, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_178 = add(_T_175, _T_177) @[exu_div_ctl.scala 807:58] - node _T_179 = tail(_T_178, 1) @[exu_div_ctl.scala 807:58] - node _T_180 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 807:95] + node _T_178 = add(_T_175, _T_177) @[exu_div_ctl.scala 806:67] + node _T_179 = tail(_T_178, 1) @[exu_div_ctl.scala 806:67] + node _T_180 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 806:104] node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_182 = add(_T_179, _T_181) @[exu_div_ctl.scala 807:85] - node adder6_out = tail(_T_182, 1) @[exu_div_ctl.scala 807:85] - node _T_183 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 808:29] - node _T_184 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 808:38] - node _T_185 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 808:49] + node _T_182 = add(_T_179, _T_181) @[exu_div_ctl.scala 806:94] + node adder6_out = tail(_T_182, 1) @[exu_div_ctl.scala 806:94] + node _T_183 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 807:38] + node _T_184 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 807:47] + node _T_185 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 807:58] node _T_186 = cat(_T_183, _T_184) @[Cat.scala 29:58] node _T_187 = cat(_T_186, _T_185) @[Cat.scala 29:58] - node _T_188 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 808:68] + node _T_188 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 807:77] node _T_189 = cat(_T_188, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_190 = add(_T_187, _T_189) @[exu_div_ctl.scala 808:58] - node _T_191 = tail(_T_190, 1) @[exu_div_ctl.scala 808:58] - node _T_192 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 808:95] + node _T_190 = add(_T_187, _T_189) @[exu_div_ctl.scala 807:67] + node _T_191 = tail(_T_190, 1) @[exu_div_ctl.scala 807:67] + node _T_192 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 807:104] node _T_193 = cat(_T_192, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_194 = add(_T_191, _T_193) @[exu_div_ctl.scala 808:85] - node _T_195 = tail(_T_194, 1) @[exu_div_ctl.scala 808:85] - node _T_196 = add(_T_195, b_ff) @[exu_div_ctl.scala 808:107] - node adder7_out = tail(_T_196, 1) @[exu_div_ctl.scala 808:107] - node _T_197 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 809:29] - node _T_198 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 809:38] - node _T_199 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 809:49] + node _T_194 = add(_T_191, _T_193) @[exu_div_ctl.scala 807:94] + node _T_195 = tail(_T_194, 1) @[exu_div_ctl.scala 807:94] + node _T_196 = add(_T_195, b_ff) @[exu_div_ctl.scala 807:116] + node adder7_out = tail(_T_196, 1) @[exu_div_ctl.scala 807:116] + node _T_197 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 808:38] + node _T_198 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 808:47] + node _T_199 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 808:58] node _T_200 = cat(_T_197, _T_198) @[Cat.scala 29:58] node _T_201 = cat(_T_200, _T_199) @[Cat.scala 29:58] - node _T_202 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 809:68] + node _T_202 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 808:77] node _T_203 = cat(_T_202, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_204 = add(_T_201, _T_203) @[exu_div_ctl.scala 809:58] - node adder8_out = tail(_T_204, 1) @[exu_div_ctl.scala 809:58] - node _T_205 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 810:29] - node _T_206 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 810:38] - node _T_207 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 810:49] + node _T_204 = add(_T_201, _T_203) @[exu_div_ctl.scala 808:67] + node adder8_out = tail(_T_204, 1) @[exu_div_ctl.scala 808:67] + node _T_205 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 809:38] + node _T_206 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 809:47] + node _T_207 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 809:58] node _T_208 = cat(_T_205, _T_206) @[Cat.scala 29:58] node _T_209 = cat(_T_208, _T_207) @[Cat.scala 29:58] - node _T_210 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 810:68] + node _T_210 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 809:77] node _T_211 = cat(_T_210, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_212 = add(_T_209, _T_211) @[exu_div_ctl.scala 810:58] - node _T_213 = tail(_T_212, 1) @[exu_div_ctl.scala 810:58] - node _T_214 = add(_T_213, b_ff) @[exu_div_ctl.scala 810:85] - node adder9_out = tail(_T_214, 1) @[exu_div_ctl.scala 810:85] - node _T_215 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 811:29] - node _T_216 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 811:38] - node _T_217 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 811:49] + node _T_212 = add(_T_209, _T_211) @[exu_div_ctl.scala 809:67] + node _T_213 = tail(_T_212, 1) @[exu_div_ctl.scala 809:67] + node _T_214 = add(_T_213, b_ff) @[exu_div_ctl.scala 809:94] + node adder9_out = tail(_T_214, 1) @[exu_div_ctl.scala 809:94] + node _T_215 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 810:38] + node _T_216 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 810:47] + node _T_217 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 810:58] node _T_218 = cat(_T_215, _T_216) @[Cat.scala 29:58] node _T_219 = cat(_T_218, _T_217) @[Cat.scala 29:58] - node _T_220 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 811:68] + node _T_220 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 810:77] node _T_221 = cat(_T_220, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_222 = add(_T_219, _T_221) @[exu_div_ctl.scala 811:58] - node _T_223 = tail(_T_222, 1) @[exu_div_ctl.scala 811:58] - node _T_224 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 811:95] + node _T_222 = add(_T_219, _T_221) @[exu_div_ctl.scala 810:67] + node _T_223 = tail(_T_222, 1) @[exu_div_ctl.scala 810:67] + node _T_224 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 810:104] node _T_225 = cat(_T_224, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_226 = add(_T_223, _T_225) @[exu_div_ctl.scala 811:85] - node adder10_out = tail(_T_226, 1) @[exu_div_ctl.scala 811:85] - node _T_227 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 812:29] - node _T_228 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 812:38] - node _T_229 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 812:49] + node _T_226 = add(_T_223, _T_225) @[exu_div_ctl.scala 810:94] + node adder10_out = tail(_T_226, 1) @[exu_div_ctl.scala 810:94] + node _T_227 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 811:38] + node _T_228 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 811:47] + node _T_229 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 811:58] node _T_230 = cat(_T_227, _T_228) @[Cat.scala 29:58] node _T_231 = cat(_T_230, _T_229) @[Cat.scala 29:58] - node _T_232 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 812:68] + node _T_232 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 811:77] node _T_233 = cat(_T_232, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_234 = add(_T_231, _T_233) @[exu_div_ctl.scala 812:58] - node _T_235 = tail(_T_234, 1) @[exu_div_ctl.scala 812:58] - node _T_236 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 812:95] + node _T_234 = add(_T_231, _T_233) @[exu_div_ctl.scala 811:67] + node _T_235 = tail(_T_234, 1) @[exu_div_ctl.scala 811:67] + node _T_236 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 811:104] node _T_237 = cat(_T_236, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_238 = add(_T_235, _T_237) @[exu_div_ctl.scala 812:85] - node _T_239 = tail(_T_238, 1) @[exu_div_ctl.scala 812:85] - node _T_240 = add(_T_239, b_ff) @[exu_div_ctl.scala 812:107] - node adder11_out = tail(_T_240, 1) @[exu_div_ctl.scala 812:107] - node _T_241 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 813:29] - node _T_242 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 813:38] - node _T_243 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 813:49] + node _T_238 = add(_T_235, _T_237) @[exu_div_ctl.scala 811:94] + node _T_239 = tail(_T_238, 1) @[exu_div_ctl.scala 811:94] + node _T_240 = add(_T_239, b_ff) @[exu_div_ctl.scala 811:116] + node adder11_out = tail(_T_240, 1) @[exu_div_ctl.scala 811:116] + node _T_241 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 812:38] + node _T_242 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 812:47] + node _T_243 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 812:58] node _T_244 = cat(_T_241, _T_242) @[Cat.scala 29:58] node _T_245 = cat(_T_244, _T_243) @[Cat.scala 29:58] - node _T_246 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 813:68] + node _T_246 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 812:77] node _T_247 = cat(_T_246, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_248 = add(_T_245, _T_247) @[exu_div_ctl.scala 813:58] - node _T_249 = tail(_T_248, 1) @[exu_div_ctl.scala 813:58] - node _T_250 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 813:95] + node _T_248 = add(_T_245, _T_247) @[exu_div_ctl.scala 812:67] + node _T_249 = tail(_T_248, 1) @[exu_div_ctl.scala 812:67] + node _T_250 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 812:104] node _T_251 = cat(_T_250, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_252 = add(_T_249, _T_251) @[exu_div_ctl.scala 813:85] - node adder12_out = tail(_T_252, 1) @[exu_div_ctl.scala 813:85] - node _T_253 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 814:29] - node _T_254 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 814:38] - node _T_255 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 814:49] + node _T_252 = add(_T_249, _T_251) @[exu_div_ctl.scala 812:94] + node adder12_out = tail(_T_252, 1) @[exu_div_ctl.scala 812:94] + node _T_253 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 813:38] + node _T_254 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 813:47] + node _T_255 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 813:58] node _T_256 = cat(_T_253, _T_254) @[Cat.scala 29:58] node _T_257 = cat(_T_256, _T_255) @[Cat.scala 29:58] - node _T_258 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 814:68] + node _T_258 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 813:77] node _T_259 = cat(_T_258, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_260 = add(_T_257, _T_259) @[exu_div_ctl.scala 814:58] - node _T_261 = tail(_T_260, 1) @[exu_div_ctl.scala 814:58] - node _T_262 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 814:95] + node _T_260 = add(_T_257, _T_259) @[exu_div_ctl.scala 813:67] + node _T_261 = tail(_T_260, 1) @[exu_div_ctl.scala 813:67] + node _T_262 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 813:104] node _T_263 = cat(_T_262, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_264 = add(_T_261, _T_263) @[exu_div_ctl.scala 814:85] - node _T_265 = tail(_T_264, 1) @[exu_div_ctl.scala 814:85] - node _T_266 = add(_T_265, b_ff) @[exu_div_ctl.scala 814:112] - node adder13_out = tail(_T_266, 1) @[exu_div_ctl.scala 814:112] - node _T_267 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 815:29] - node _T_268 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 815:38] - node _T_269 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 815:49] + node _T_264 = add(_T_261, _T_263) @[exu_div_ctl.scala 813:94] + node _T_265 = tail(_T_264, 1) @[exu_div_ctl.scala 813:94] + node _T_266 = add(_T_265, b_ff) @[exu_div_ctl.scala 813:121] + node adder13_out = tail(_T_266, 1) @[exu_div_ctl.scala 813:121] + node _T_267 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 814:38] + node _T_268 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 814:47] + node _T_269 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 814:58] node _T_270 = cat(_T_267, _T_268) @[Cat.scala 29:58] node _T_271 = cat(_T_270, _T_269) @[Cat.scala 29:58] - node _T_272 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 815:68] + node _T_272 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 814:77] node _T_273 = cat(_T_272, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_274 = add(_T_271, _T_273) @[exu_div_ctl.scala 815:58] - node _T_275 = tail(_T_274, 1) @[exu_div_ctl.scala 815:58] - node _T_276 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 815:95] + node _T_274 = add(_T_271, _T_273) @[exu_div_ctl.scala 814:67] + node _T_275 = tail(_T_274, 1) @[exu_div_ctl.scala 814:67] + node _T_276 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 814:104] node _T_277 = cat(_T_276, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_278 = add(_T_275, _T_277) @[exu_div_ctl.scala 815:85] - node _T_279 = tail(_T_278, 1) @[exu_div_ctl.scala 815:85] - node _T_280 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 815:122] + node _T_278 = add(_T_275, _T_277) @[exu_div_ctl.scala 814:94] + node _T_279 = tail(_T_278, 1) @[exu_div_ctl.scala 814:94] + node _T_280 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 814:131] node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_282 = add(_T_279, _T_281) @[exu_div_ctl.scala 815:112] - node adder14_out = tail(_T_282, 1) @[exu_div_ctl.scala 815:112] - node _T_283 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 816:29] - node _T_284 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 816:38] - node _T_285 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 816:49] + node _T_282 = add(_T_279, _T_281) @[exu_div_ctl.scala 814:121] + node adder14_out = tail(_T_282, 1) @[exu_div_ctl.scala 814:121] + node _T_283 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 815:38] + node _T_284 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 815:47] + node _T_285 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 815:58] node _T_286 = cat(_T_283, _T_284) @[Cat.scala 29:58] node _T_287 = cat(_T_286, _T_285) @[Cat.scala 29:58] - node _T_288 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 816:68] + node _T_288 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 815:77] node _T_289 = cat(_T_288, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_290 = add(_T_287, _T_289) @[exu_div_ctl.scala 816:58] - node _T_291 = tail(_T_290, 1) @[exu_div_ctl.scala 816:58] - node _T_292 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 816:95] + node _T_290 = add(_T_287, _T_289) @[exu_div_ctl.scala 815:67] + node _T_291 = tail(_T_290, 1) @[exu_div_ctl.scala 815:67] + node _T_292 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 815:104] node _T_293 = cat(_T_292, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_294 = add(_T_291, _T_293) @[exu_div_ctl.scala 816:85] - node _T_295 = tail(_T_294, 1) @[exu_div_ctl.scala 816:85] - node _T_296 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 816:122] + node _T_294 = add(_T_291, _T_293) @[exu_div_ctl.scala 815:94] + node _T_295 = tail(_T_294, 1) @[exu_div_ctl.scala 815:94] + node _T_296 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 815:131] node _T_297 = cat(_T_296, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_298 = add(_T_295, _T_297) @[exu_div_ctl.scala 816:112] - node _T_299 = tail(_T_298, 1) @[exu_div_ctl.scala 816:112] - node _T_300 = add(_T_299, b_ff) @[exu_div_ctl.scala 816:134] - node adder15_out = tail(_T_300, 1) @[exu_div_ctl.scala 816:134] - node _T_301 = bits(adder15_out, 37, 37) @[exu_div_ctl.scala 819:18] - node _T_302 = eq(_T_301, UInt<1>("h00")) @[exu_div_ctl.scala 819:6] - node _T_303 = xor(_T_302, dividend_sign_ff) @[exu_div_ctl.scala 819:23] - node _T_304 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 819:51] - node _T_305 = eq(_T_304, UInt<1>("h00")) @[exu_div_ctl.scala 819:58] - node _T_306 = eq(adder15_out, UInt<1>("h00")) @[exu_div_ctl.scala 819:82] - node _T_307 = and(_T_305, _T_306) @[exu_div_ctl.scala 819:67] - node _T_308 = or(_T_303, _T_307) @[exu_div_ctl.scala 819:43] - node _T_309 = bits(adder14_out, 37, 37) @[exu_div_ctl.scala 820:18] - node _T_310 = eq(_T_309, UInt<1>("h00")) @[exu_div_ctl.scala 820:6] - node _T_311 = xor(_T_310, dividend_sign_ff) @[exu_div_ctl.scala 820:23] - node _T_312 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 820:51] - node _T_313 = eq(_T_312, UInt<1>("h00")) @[exu_div_ctl.scala 820:58] - node _T_314 = eq(adder14_out, UInt<1>("h00")) @[exu_div_ctl.scala 820:82] - node _T_315 = and(_T_313, _T_314) @[exu_div_ctl.scala 820:67] - node _T_316 = or(_T_311, _T_315) @[exu_div_ctl.scala 820:43] - node _T_317 = bits(adder13_out, 37, 37) @[exu_div_ctl.scala 821:18] - node _T_318 = eq(_T_317, UInt<1>("h00")) @[exu_div_ctl.scala 821:6] - node _T_319 = xor(_T_318, dividend_sign_ff) @[exu_div_ctl.scala 821:23] - node _T_320 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 821:51] - node _T_321 = eq(_T_320, UInt<1>("h00")) @[exu_div_ctl.scala 821:58] - node _T_322 = eq(adder13_out, UInt<1>("h00")) @[exu_div_ctl.scala 821:82] - node _T_323 = and(_T_321, _T_322) @[exu_div_ctl.scala 821:67] - node _T_324 = or(_T_319, _T_323) @[exu_div_ctl.scala 821:43] - node _T_325 = bits(adder12_out, 37, 37) @[exu_div_ctl.scala 822:18] - node _T_326 = eq(_T_325, UInt<1>("h00")) @[exu_div_ctl.scala 822:6] - node _T_327 = xor(_T_326, dividend_sign_ff) @[exu_div_ctl.scala 822:23] - node _T_328 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 822:51] - node _T_329 = eq(_T_328, UInt<1>("h00")) @[exu_div_ctl.scala 822:58] - node _T_330 = eq(adder12_out, UInt<1>("h00")) @[exu_div_ctl.scala 822:82] - node _T_331 = and(_T_329, _T_330) @[exu_div_ctl.scala 822:67] - node _T_332 = or(_T_327, _T_331) @[exu_div_ctl.scala 822:43] - node _T_333 = bits(adder11_out, 37, 37) @[exu_div_ctl.scala 823:18] - node _T_334 = eq(_T_333, UInt<1>("h00")) @[exu_div_ctl.scala 823:6] - node _T_335 = xor(_T_334, dividend_sign_ff) @[exu_div_ctl.scala 823:23] - node _T_336 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 823:51] - node _T_337 = eq(_T_336, UInt<1>("h00")) @[exu_div_ctl.scala 823:58] - node _T_338 = eq(adder11_out, UInt<1>("h00")) @[exu_div_ctl.scala 823:82] - node _T_339 = and(_T_337, _T_338) @[exu_div_ctl.scala 823:67] - node _T_340 = or(_T_335, _T_339) @[exu_div_ctl.scala 823:43] - node _T_341 = bits(adder10_out, 37, 37) @[exu_div_ctl.scala 824:18] - node _T_342 = eq(_T_341, UInt<1>("h00")) @[exu_div_ctl.scala 824:6] - node _T_343 = xor(_T_342, dividend_sign_ff) @[exu_div_ctl.scala 824:23] - node _T_344 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 824:51] - node _T_345 = eq(_T_344, UInt<1>("h00")) @[exu_div_ctl.scala 824:58] - node _T_346 = eq(adder10_out, UInt<1>("h00")) @[exu_div_ctl.scala 824:82] - node _T_347 = and(_T_345, _T_346) @[exu_div_ctl.scala 824:67] - node _T_348 = or(_T_343, _T_347) @[exu_div_ctl.scala 824:43] - node _T_349 = bits(adder9_out, 37, 37) @[exu_div_ctl.scala 825:17] - node _T_350 = eq(_T_349, UInt<1>("h00")) @[exu_div_ctl.scala 825:6] - node _T_351 = xor(_T_350, dividend_sign_ff) @[exu_div_ctl.scala 825:22] - node _T_352 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 825:50] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[exu_div_ctl.scala 825:57] - node _T_354 = eq(adder9_out, UInt<1>("h00")) @[exu_div_ctl.scala 825:80] - node _T_355 = and(_T_353, _T_354) @[exu_div_ctl.scala 825:66] - node _T_356 = or(_T_351, _T_355) @[exu_div_ctl.scala 825:42] - node _T_357 = bits(adder8_out, 37, 37) @[exu_div_ctl.scala 826:17] - node _T_358 = eq(_T_357, UInt<1>("h00")) @[exu_div_ctl.scala 826:6] - node _T_359 = xor(_T_358, dividend_sign_ff) @[exu_div_ctl.scala 826:22] - node _T_360 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 826:50] - node _T_361 = eq(_T_360, UInt<1>("h00")) @[exu_div_ctl.scala 826:57] - node _T_362 = eq(adder8_out, UInt<1>("h00")) @[exu_div_ctl.scala 826:80] - node _T_363 = and(_T_361, _T_362) @[exu_div_ctl.scala 826:66] - node _T_364 = or(_T_359, _T_363) @[exu_div_ctl.scala 826:42] - node _T_365 = bits(adder7_out, 37, 37) @[exu_div_ctl.scala 827:17] - node _T_366 = eq(_T_365, UInt<1>("h00")) @[exu_div_ctl.scala 827:6] - node _T_367 = xor(_T_366, dividend_sign_ff) @[exu_div_ctl.scala 827:22] - node _T_368 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 827:50] - node _T_369 = eq(_T_368, UInt<1>("h00")) @[exu_div_ctl.scala 827:57] - node _T_370 = eq(adder7_out, UInt<1>("h00")) @[exu_div_ctl.scala 827:80] - node _T_371 = and(_T_369, _T_370) @[exu_div_ctl.scala 827:66] - node _T_372 = or(_T_367, _T_371) @[exu_div_ctl.scala 827:42] - node _T_373 = bits(adder6_out, 37, 37) @[exu_div_ctl.scala 828:17] - node _T_374 = eq(_T_373, UInt<1>("h00")) @[exu_div_ctl.scala 828:6] - node _T_375 = xor(_T_374, dividend_sign_ff) @[exu_div_ctl.scala 828:22] - node _T_376 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 828:50] - node _T_377 = eq(_T_376, UInt<1>("h00")) @[exu_div_ctl.scala 828:57] - node _T_378 = eq(adder6_out, UInt<1>("h00")) @[exu_div_ctl.scala 828:80] - node _T_379 = and(_T_377, _T_378) @[exu_div_ctl.scala 828:66] - node _T_380 = or(_T_375, _T_379) @[exu_div_ctl.scala 828:42] - node _T_381 = bits(adder5_out, 37, 37) @[exu_div_ctl.scala 829:17] - node _T_382 = eq(_T_381, UInt<1>("h00")) @[exu_div_ctl.scala 829:6] - node _T_383 = xor(_T_382, dividend_sign_ff) @[exu_div_ctl.scala 829:22] - node _T_384 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 829:50] - node _T_385 = eq(_T_384, UInt<1>("h00")) @[exu_div_ctl.scala 829:57] - node _T_386 = eq(adder5_out, UInt<1>("h00")) @[exu_div_ctl.scala 829:80] - node _T_387 = and(_T_385, _T_386) @[exu_div_ctl.scala 829:66] - node _T_388 = or(_T_383, _T_387) @[exu_div_ctl.scala 829:42] - node _T_389 = bits(adder4_out, 37, 37) @[exu_div_ctl.scala 830:17] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[exu_div_ctl.scala 830:6] - node _T_391 = xor(_T_390, dividend_sign_ff) @[exu_div_ctl.scala 830:22] - node _T_392 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 830:50] - node _T_393 = eq(_T_392, UInt<1>("h00")) @[exu_div_ctl.scala 830:57] - node _T_394 = eq(adder4_out, UInt<1>("h00")) @[exu_div_ctl.scala 830:80] - node _T_395 = and(_T_393, _T_394) @[exu_div_ctl.scala 830:66] - node _T_396 = or(_T_391, _T_395) @[exu_div_ctl.scala 830:42] - node _T_397 = bits(adder3_out, 36, 36) @[exu_div_ctl.scala 831:17] - node _T_398 = eq(_T_397, UInt<1>("h00")) @[exu_div_ctl.scala 831:6] - node _T_399 = xor(_T_398, dividend_sign_ff) @[exu_div_ctl.scala 831:22] - node _T_400 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 831:50] - node _T_401 = eq(_T_400, UInt<1>("h00")) @[exu_div_ctl.scala 831:57] - node _T_402 = eq(adder3_out, UInt<1>("h00")) @[exu_div_ctl.scala 831:80] - node _T_403 = and(_T_401, _T_402) @[exu_div_ctl.scala 831:66] - node _T_404 = or(_T_399, _T_403) @[exu_div_ctl.scala 831:42] - node _T_405 = bits(adder2_out, 35, 35) @[exu_div_ctl.scala 832:17] - node _T_406 = eq(_T_405, UInt<1>("h00")) @[exu_div_ctl.scala 832:6] - node _T_407 = xor(_T_406, dividend_sign_ff) @[exu_div_ctl.scala 832:22] - node _T_408 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 832:50] - node _T_409 = eq(_T_408, UInt<1>("h00")) @[exu_div_ctl.scala 832:57] - node _T_410 = eq(adder2_out, UInt<1>("h00")) @[exu_div_ctl.scala 832:80] - node _T_411 = and(_T_409, _T_410) @[exu_div_ctl.scala 832:66] - node _T_412 = or(_T_407, _T_411) @[exu_div_ctl.scala 832:42] - node _T_413 = bits(adder1_out, 34, 34) @[exu_div_ctl.scala 833:17] - node _T_414 = eq(_T_413, UInt<1>("h00")) @[exu_div_ctl.scala 833:6] - node _T_415 = xor(_T_414, dividend_sign_ff) @[exu_div_ctl.scala 833:22] - node _T_416 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 833:50] - node _T_417 = eq(_T_416, UInt<1>("h00")) @[exu_div_ctl.scala 833:57] - node _T_418 = eq(adder1_out, UInt<1>("h00")) @[exu_div_ctl.scala 833:80] - node _T_419 = and(_T_417, _T_418) @[exu_div_ctl.scala 833:66] - node _T_420 = or(_T_415, _T_419) @[exu_div_ctl.scala 833:42] + node _T_298 = add(_T_295, _T_297) @[exu_div_ctl.scala 815:121] + node _T_299 = tail(_T_298, 1) @[exu_div_ctl.scala 815:121] + node _T_300 = add(_T_299, b_ff) @[exu_div_ctl.scala 815:143] + node adder15_out = tail(_T_300, 1) @[exu_div_ctl.scala 815:143] + node _T_301 = bits(adder15_out, 37, 37) @[exu_div_ctl.scala 818:18] + node _T_302 = eq(_T_301, UInt<1>("h00")) @[exu_div_ctl.scala 818:6] + node _T_303 = xor(_T_302, dividend_sign_ff) @[exu_div_ctl.scala 818:23] + node _T_304 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 818:51] + node _T_305 = eq(_T_304, UInt<1>("h00")) @[exu_div_ctl.scala 818:58] + node _T_306 = eq(adder15_out, UInt<1>("h00")) @[exu_div_ctl.scala 818:82] + node _T_307 = and(_T_305, _T_306) @[exu_div_ctl.scala 818:67] + node _T_308 = or(_T_303, _T_307) @[exu_div_ctl.scala 818:43] + node _T_309 = bits(adder14_out, 37, 37) @[exu_div_ctl.scala 819:18] + node _T_310 = eq(_T_309, UInt<1>("h00")) @[exu_div_ctl.scala 819:6] + node _T_311 = xor(_T_310, dividend_sign_ff) @[exu_div_ctl.scala 819:23] + node _T_312 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 819:51] + node _T_313 = eq(_T_312, UInt<1>("h00")) @[exu_div_ctl.scala 819:58] + node _T_314 = eq(adder14_out, UInt<1>("h00")) @[exu_div_ctl.scala 819:82] + node _T_315 = and(_T_313, _T_314) @[exu_div_ctl.scala 819:67] + node _T_316 = or(_T_311, _T_315) @[exu_div_ctl.scala 819:43] + node _T_317 = bits(adder13_out, 37, 37) @[exu_div_ctl.scala 820:18] + node _T_318 = eq(_T_317, UInt<1>("h00")) @[exu_div_ctl.scala 820:6] + node _T_319 = xor(_T_318, dividend_sign_ff) @[exu_div_ctl.scala 820:23] + node _T_320 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 820:51] + node _T_321 = eq(_T_320, UInt<1>("h00")) @[exu_div_ctl.scala 820:58] + node _T_322 = eq(adder13_out, UInt<1>("h00")) @[exu_div_ctl.scala 820:82] + node _T_323 = and(_T_321, _T_322) @[exu_div_ctl.scala 820:67] + node _T_324 = or(_T_319, _T_323) @[exu_div_ctl.scala 820:43] + node _T_325 = bits(adder12_out, 37, 37) @[exu_div_ctl.scala 821:18] + node _T_326 = eq(_T_325, UInt<1>("h00")) @[exu_div_ctl.scala 821:6] + node _T_327 = xor(_T_326, dividend_sign_ff) @[exu_div_ctl.scala 821:23] + node _T_328 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 821:51] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[exu_div_ctl.scala 821:58] + node _T_330 = eq(adder12_out, UInt<1>("h00")) @[exu_div_ctl.scala 821:82] + node _T_331 = and(_T_329, _T_330) @[exu_div_ctl.scala 821:67] + node _T_332 = or(_T_327, _T_331) @[exu_div_ctl.scala 821:43] + node _T_333 = bits(adder11_out, 37, 37) @[exu_div_ctl.scala 822:18] + node _T_334 = eq(_T_333, UInt<1>("h00")) @[exu_div_ctl.scala 822:6] + node _T_335 = xor(_T_334, dividend_sign_ff) @[exu_div_ctl.scala 822:23] + node _T_336 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 822:51] + node _T_337 = eq(_T_336, UInt<1>("h00")) @[exu_div_ctl.scala 822:58] + node _T_338 = eq(adder11_out, UInt<1>("h00")) @[exu_div_ctl.scala 822:82] + node _T_339 = and(_T_337, _T_338) @[exu_div_ctl.scala 822:67] + node _T_340 = or(_T_335, _T_339) @[exu_div_ctl.scala 822:43] + node _T_341 = bits(adder10_out, 37, 37) @[exu_div_ctl.scala 823:18] + node _T_342 = eq(_T_341, UInt<1>("h00")) @[exu_div_ctl.scala 823:6] + node _T_343 = xor(_T_342, dividend_sign_ff) @[exu_div_ctl.scala 823:23] + node _T_344 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 823:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[exu_div_ctl.scala 823:58] + node _T_346 = eq(adder10_out, UInt<1>("h00")) @[exu_div_ctl.scala 823:82] + node _T_347 = and(_T_345, _T_346) @[exu_div_ctl.scala 823:67] + node _T_348 = or(_T_343, _T_347) @[exu_div_ctl.scala 823:43] + node _T_349 = bits(adder9_out, 37, 37) @[exu_div_ctl.scala 824:17] + node _T_350 = eq(_T_349, UInt<1>("h00")) @[exu_div_ctl.scala 824:6] + node _T_351 = xor(_T_350, dividend_sign_ff) @[exu_div_ctl.scala 824:22] + node _T_352 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 824:50] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[exu_div_ctl.scala 824:57] + node _T_354 = eq(adder9_out, UInt<1>("h00")) @[exu_div_ctl.scala 824:80] + node _T_355 = and(_T_353, _T_354) @[exu_div_ctl.scala 824:66] + node _T_356 = or(_T_351, _T_355) @[exu_div_ctl.scala 824:42] + node _T_357 = bits(adder8_out, 37, 37) @[exu_div_ctl.scala 825:17] + node _T_358 = eq(_T_357, UInt<1>("h00")) @[exu_div_ctl.scala 825:6] + node _T_359 = xor(_T_358, dividend_sign_ff) @[exu_div_ctl.scala 825:22] + node _T_360 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 825:50] + node _T_361 = eq(_T_360, UInt<1>("h00")) @[exu_div_ctl.scala 825:57] + node _T_362 = eq(adder8_out, UInt<1>("h00")) @[exu_div_ctl.scala 825:80] + node _T_363 = and(_T_361, _T_362) @[exu_div_ctl.scala 825:66] + node _T_364 = or(_T_359, _T_363) @[exu_div_ctl.scala 825:42] + node _T_365 = bits(adder7_out, 37, 37) @[exu_div_ctl.scala 826:17] + node _T_366 = eq(_T_365, UInt<1>("h00")) @[exu_div_ctl.scala 826:6] + node _T_367 = xor(_T_366, dividend_sign_ff) @[exu_div_ctl.scala 826:22] + node _T_368 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 826:50] + node _T_369 = eq(_T_368, UInt<1>("h00")) @[exu_div_ctl.scala 826:57] + node _T_370 = eq(adder7_out, UInt<1>("h00")) @[exu_div_ctl.scala 826:80] + node _T_371 = and(_T_369, _T_370) @[exu_div_ctl.scala 826:66] + node _T_372 = or(_T_367, _T_371) @[exu_div_ctl.scala 826:42] + node _T_373 = bits(adder6_out, 37, 37) @[exu_div_ctl.scala 827:17] + node _T_374 = eq(_T_373, UInt<1>("h00")) @[exu_div_ctl.scala 827:6] + node _T_375 = xor(_T_374, dividend_sign_ff) @[exu_div_ctl.scala 827:22] + node _T_376 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 827:50] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[exu_div_ctl.scala 827:57] + node _T_378 = eq(adder6_out, UInt<1>("h00")) @[exu_div_ctl.scala 827:80] + node _T_379 = and(_T_377, _T_378) @[exu_div_ctl.scala 827:66] + node _T_380 = or(_T_375, _T_379) @[exu_div_ctl.scala 827:42] + node _T_381 = bits(adder5_out, 37, 37) @[exu_div_ctl.scala 828:17] + node _T_382 = eq(_T_381, UInt<1>("h00")) @[exu_div_ctl.scala 828:6] + node _T_383 = xor(_T_382, dividend_sign_ff) @[exu_div_ctl.scala 828:22] + node _T_384 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 828:50] + node _T_385 = eq(_T_384, UInt<1>("h00")) @[exu_div_ctl.scala 828:57] + node _T_386 = eq(adder5_out, UInt<1>("h00")) @[exu_div_ctl.scala 828:80] + node _T_387 = and(_T_385, _T_386) @[exu_div_ctl.scala 828:66] + node _T_388 = or(_T_383, _T_387) @[exu_div_ctl.scala 828:42] + node _T_389 = bits(adder4_out, 37, 37) @[exu_div_ctl.scala 829:17] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[exu_div_ctl.scala 829:6] + node _T_391 = xor(_T_390, dividend_sign_ff) @[exu_div_ctl.scala 829:22] + node _T_392 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 829:50] + node _T_393 = eq(_T_392, UInt<1>("h00")) @[exu_div_ctl.scala 829:57] + node _T_394 = eq(adder4_out, UInt<1>("h00")) @[exu_div_ctl.scala 829:80] + node _T_395 = and(_T_393, _T_394) @[exu_div_ctl.scala 829:66] + node _T_396 = or(_T_391, _T_395) @[exu_div_ctl.scala 829:42] + node _T_397 = bits(adder3_out, 36, 36) @[exu_div_ctl.scala 830:17] + node _T_398 = eq(_T_397, UInt<1>("h00")) @[exu_div_ctl.scala 830:6] + node _T_399 = xor(_T_398, dividend_sign_ff) @[exu_div_ctl.scala 830:22] + node _T_400 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 830:50] + node _T_401 = eq(_T_400, UInt<1>("h00")) @[exu_div_ctl.scala 830:57] + node _T_402 = eq(adder3_out, UInt<1>("h00")) @[exu_div_ctl.scala 830:80] + node _T_403 = and(_T_401, _T_402) @[exu_div_ctl.scala 830:66] + node _T_404 = or(_T_399, _T_403) @[exu_div_ctl.scala 830:42] + node _T_405 = bits(adder2_out, 35, 35) @[exu_div_ctl.scala 831:17] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[exu_div_ctl.scala 831:6] + node _T_407 = xor(_T_406, dividend_sign_ff) @[exu_div_ctl.scala 831:22] + node _T_408 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 831:50] + node _T_409 = eq(_T_408, UInt<1>("h00")) @[exu_div_ctl.scala 831:57] + node _T_410 = eq(adder2_out, UInt<1>("h00")) @[exu_div_ctl.scala 831:80] + node _T_411 = and(_T_409, _T_410) @[exu_div_ctl.scala 831:66] + node _T_412 = or(_T_407, _T_411) @[exu_div_ctl.scala 831:42] + node _T_413 = bits(adder1_out, 34, 34) @[exu_div_ctl.scala 832:17] + node _T_414 = eq(_T_413, UInt<1>("h00")) @[exu_div_ctl.scala 832:6] + node _T_415 = xor(_T_414, dividend_sign_ff) @[exu_div_ctl.scala 832:22] + node _T_416 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 832:50] + node _T_417 = eq(_T_416, UInt<1>("h00")) @[exu_div_ctl.scala 832:57] + node _T_418 = eq(adder1_out, UInt<1>("h00")) @[exu_div_ctl.scala 832:80] + node _T_419 = and(_T_417, _T_418) @[exu_div_ctl.scala 832:66] + node _T_420 = or(_T_415, _T_419) @[exu_div_ctl.scala 832:42] node _T_421 = cat(_T_420, UInt<1>("h00")) @[Cat.scala 29:58] node _T_422 = cat(_T_404, _T_412) @[Cat.scala 29:58] node _T_423 = cat(_T_422, _T_421) @[Cat.scala 29:58] @@ -1532,41 +1532,41 @@ circuit exu_div_ctl : node _T_433 = cat(_T_432, _T_431) @[Cat.scala 29:58] node _T_434 = cat(_T_433, _T_430) @[Cat.scala 29:58] node _T_435 = cat(_T_434, _T_427) @[Cat.scala 29:58] - quotient_raw <= _T_435 @[exu_div_ctl.scala 818:16] - node _T_436 = bits(quotient_raw, 15, 8) @[exu_div_ctl.scala 836:43] + quotient_raw <= _T_435 @[exu_div_ctl.scala 817:16] + node _T_436 = bits(quotient_raw, 15, 8) @[exu_div_ctl.scala 835:43] node _T_437 = mux(UInt<1>("h00"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] node _T_438 = cat(_T_437, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_439 = eq(_T_436, _T_438) @[exu_div_ctl.scala 836:49] - node _T_440 = bits(_T_439, 0, 0) @[exu_div_ctl.scala 836:78] - node _T_441 = bits(quotient_raw, 15, 9) @[exu_div_ctl.scala 836:43] + node _T_439 = eq(_T_436, _T_438) @[exu_div_ctl.scala 835:49] + node _T_440 = bits(_T_439, 0, 0) @[exu_div_ctl.scala 835:78] + node _T_441 = bits(quotient_raw, 15, 9) @[exu_div_ctl.scala 835:43] node _T_442 = mux(UInt<1>("h00"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] node _T_443 = cat(_T_442, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_444 = eq(_T_441, _T_443) @[exu_div_ctl.scala 836:49] - node _T_445 = bits(_T_444, 0, 0) @[exu_div_ctl.scala 836:78] - node _T_446 = bits(quotient_raw, 15, 10) @[exu_div_ctl.scala 836:43] + node _T_444 = eq(_T_441, _T_443) @[exu_div_ctl.scala 835:49] + node _T_445 = bits(_T_444, 0, 0) @[exu_div_ctl.scala 835:78] + node _T_446 = bits(quotient_raw, 15, 10) @[exu_div_ctl.scala 835:43] node _T_447 = mux(UInt<1>("h00"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] node _T_448 = cat(_T_447, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_449 = eq(_T_446, _T_448) @[exu_div_ctl.scala 836:49] - node _T_450 = bits(_T_449, 0, 0) @[exu_div_ctl.scala 836:78] - node _T_451 = bits(quotient_raw, 15, 11) @[exu_div_ctl.scala 836:43] + node _T_449 = eq(_T_446, _T_448) @[exu_div_ctl.scala 835:49] + node _T_450 = bits(_T_449, 0, 0) @[exu_div_ctl.scala 835:78] + node _T_451 = bits(quotient_raw, 15, 11) @[exu_div_ctl.scala 835:43] node _T_452 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_453 = cat(_T_452, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_454 = eq(_T_451, _T_453) @[exu_div_ctl.scala 836:49] - node _T_455 = bits(_T_454, 0, 0) @[exu_div_ctl.scala 836:78] - node _T_456 = bits(quotient_raw, 15, 12) @[exu_div_ctl.scala 836:43] + node _T_454 = eq(_T_451, _T_453) @[exu_div_ctl.scala 835:49] + node _T_455 = bits(_T_454, 0, 0) @[exu_div_ctl.scala 835:78] + node _T_456 = bits(quotient_raw, 15, 12) @[exu_div_ctl.scala 835:43] node _T_457 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_458 = cat(_T_457, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_459 = eq(_T_456, _T_458) @[exu_div_ctl.scala 836:49] - node _T_460 = bits(_T_459, 0, 0) @[exu_div_ctl.scala 836:78] - node _T_461 = bits(quotient_raw, 15, 13) @[exu_div_ctl.scala 836:43] + node _T_459 = eq(_T_456, _T_458) @[exu_div_ctl.scala 835:49] + node _T_460 = bits(_T_459, 0, 0) @[exu_div_ctl.scala 835:78] + node _T_461 = bits(quotient_raw, 15, 13) @[exu_div_ctl.scala 835:43] node _T_462 = mux(UInt<1>("h00"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_463 = cat(_T_462, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_464 = eq(_T_461, _T_463) @[exu_div_ctl.scala 836:49] - node _T_465 = bits(_T_464, 0, 0) @[exu_div_ctl.scala 836:78] - node _T_466 = bits(quotient_raw, 15, 14) @[exu_div_ctl.scala 836:43] + node _T_464 = eq(_T_461, _T_463) @[exu_div_ctl.scala 835:49] + node _T_465 = bits(_T_464, 0, 0) @[exu_div_ctl.scala 835:78] + node _T_466 = bits(quotient_raw, 15, 14) @[exu_div_ctl.scala 835:43] node _T_467 = cat(UInt<1>("h00"), UInt<1>("h01")) @[Cat.scala 29:58] - node _T_468 = eq(_T_466, _T_467) @[exu_div_ctl.scala 836:49] - node _T_469 = bits(_T_468, 0, 0) @[exu_div_ctl.scala 836:78] + node _T_468 = eq(_T_466, _T_467) @[exu_div_ctl.scala 835:49] + node _T_469 = bits(_T_468, 0, 0) @[exu_div_ctl.scala 835:78] node _T_470 = mux(_T_440, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_471 = mux(_T_445, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_472 = mux(_T_450, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -1582,1060 +1582,1062 @@ circuit exu_div_ctl : node _T_482 = or(_T_481, _T_476) @[Mux.scala 27:72] wire _T_483 : UInt<1> @[Mux.scala 27:72] _T_483 <= _T_482 @[Mux.scala 27:72] - node _T_484 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 836:109] - node _T_485 = eq(_T_484, UInt<1>("h01")) @[exu_div_ctl.scala 836:113] - node _T_486 = or(_T_483, _T_485) @[exu_div_ctl.scala 836:94] - node _T_487 = bits(quotient_raw, 15, 4) @[exu_div_ctl.scala 838:19] - node _T_488 = eq(_T_487, UInt<12>("h01")) @[exu_div_ctl.scala 838:26] - node _T_489 = bits(quotient_raw, 15, 5) @[exu_div_ctl.scala 838:70] - node _T_490 = eq(_T_489, UInt<11>("h01")) @[exu_div_ctl.scala 838:77] - node _T_491 = or(_T_488, _T_490) @[exu_div_ctl.scala 838:54] - node _T_492 = bits(quotient_raw, 15, 6) @[exu_div_ctl.scala 838:121] - node _T_493 = eq(_T_492, UInt<10>("h01")) @[exu_div_ctl.scala 838:128] - node _T_494 = or(_T_491, _T_493) @[exu_div_ctl.scala 838:105] - node _T_495 = bits(quotient_raw, 15, 7) @[exu_div_ctl.scala 839:21] - node _T_496 = eq(_T_495, UInt<9>("h01")) @[exu_div_ctl.scala 839:28] - node _T_497 = or(_T_494, _T_496) @[exu_div_ctl.scala 838:155] - node _T_498 = bits(quotient_raw, 15, 12) @[exu_div_ctl.scala 839:69] - node _T_499 = eq(_T_498, UInt<4>("h01")) @[exu_div_ctl.scala 839:76] - node _T_500 = or(_T_497, _T_499) @[exu_div_ctl.scala 839:53] - node _T_501 = bits(quotient_raw, 15, 13) @[exu_div_ctl.scala 839:112] - node _T_502 = eq(_T_501, UInt<3>("h01")) @[exu_div_ctl.scala 839:119] - node _T_503 = or(_T_500, _T_502) @[exu_div_ctl.scala 839:96] - node _T_504 = bits(quotient_raw, 15, 14) @[exu_div_ctl.scala 840:21] - node _T_505 = eq(_T_504, UInt<2>("h01")) @[exu_div_ctl.scala 840:28] - node _T_506 = or(_T_503, _T_505) @[exu_div_ctl.scala 839:138] - node _T_507 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 840:62] - node _T_508 = eq(_T_507, UInt<1>("h01")) @[exu_div_ctl.scala 840:69] - node _T_509 = or(_T_506, _T_508) @[exu_div_ctl.scala 840:46] - node _T_510 = bits(quotient_raw, 15, 2) @[exu_div_ctl.scala 842:19] - node _T_511 = eq(_T_510, UInt<14>("h01")) @[exu_div_ctl.scala 842:26] - node _T_512 = bits(quotient_raw, 15, 3) @[exu_div_ctl.scala 842:72] - node _T_513 = eq(_T_512, UInt<13>("h01")) @[exu_div_ctl.scala 842:79] - node _T_514 = or(_T_511, _T_513) @[exu_div_ctl.scala 842:56] - node _T_515 = bits(quotient_raw, 15, 6) @[exu_div_ctl.scala 842:125] - node _T_516 = eq(_T_515, UInt<10>("h01")) @[exu_div_ctl.scala 842:132] - node _T_517 = or(_T_514, _T_516) @[exu_div_ctl.scala 842:109] - node _T_518 = bits(quotient_raw, 15, 7) @[exu_div_ctl.scala 843:23] - node _T_519 = eq(_T_518, UInt<9>("h01")) @[exu_div_ctl.scala 843:30] - node _T_520 = or(_T_517, _T_519) @[exu_div_ctl.scala 842:159] - node _T_521 = bits(quotient_raw, 15, 10) @[exu_div_ctl.scala 843:71] - node _T_522 = eq(_T_521, UInt<6>("h01")) @[exu_div_ctl.scala 843:78] - node _T_523 = or(_T_520, _T_522) @[exu_div_ctl.scala 843:55] - node _T_524 = bits(quotient_raw, 15, 11) @[exu_div_ctl.scala 843:116] - node _T_525 = eq(_T_524, UInt<5>("h01")) @[exu_div_ctl.scala 843:123] - node _T_526 = or(_T_523, _T_525) @[exu_div_ctl.scala 843:100] - node _T_527 = bits(quotient_raw, 15, 14) @[exu_div_ctl.scala 844:23] - node _T_528 = eq(_T_527, UInt<2>("h01")) @[exu_div_ctl.scala 844:30] - node _T_529 = or(_T_526, _T_528) @[exu_div_ctl.scala 843:144] - node _T_530 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 844:64] - node _T_531 = eq(_T_530, UInt<1>("h01")) @[exu_div_ctl.scala 844:71] - node _T_532 = or(_T_529, _T_531) @[exu_div_ctl.scala 844:48] - node _T_533 = bits(quotient_raw, 15, 1) @[exu_div_ctl.scala 846:48] - node _T_534 = mux(UInt<1>("h00"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12] - node _T_535 = cat(_T_534, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_536 = eq(_T_533, _T_535) @[exu_div_ctl.scala 846:54] - node _T_537 = bits(_T_536, 0, 0) @[exu_div_ctl.scala 846:83] - node _T_538 = bits(quotient_raw, 15, 3) @[exu_div_ctl.scala 846:48] - node _T_539 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] - node _T_540 = cat(_T_539, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_541 = eq(_T_538, _T_540) @[exu_div_ctl.scala 846:54] - node _T_542 = bits(_T_541, 0, 0) @[exu_div_ctl.scala 846:83] - node _T_543 = bits(quotient_raw, 15, 5) @[exu_div_ctl.scala 846:48] - node _T_544 = mux(UInt<1>("h00"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] - node _T_545 = cat(_T_544, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_546 = eq(_T_543, _T_545) @[exu_div_ctl.scala 846:54] - node _T_547 = bits(_T_546, 0, 0) @[exu_div_ctl.scala 846:83] - node _T_548 = bits(quotient_raw, 15, 7) @[exu_div_ctl.scala 846:48] - node _T_549 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_550 = cat(_T_549, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_551 = eq(_T_548, _T_550) @[exu_div_ctl.scala 846:54] - node _T_552 = bits(_T_551, 0, 0) @[exu_div_ctl.scala 846:83] - node _T_553 = bits(quotient_raw, 15, 9) @[exu_div_ctl.scala 846:48] - node _T_554 = mux(UInt<1>("h00"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_555 = cat(_T_554, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_556 = eq(_T_553, _T_555) @[exu_div_ctl.scala 846:54] - node _T_557 = bits(_T_556, 0, 0) @[exu_div_ctl.scala 846:83] - node _T_558 = bits(quotient_raw, 15, 11) @[exu_div_ctl.scala 846:48] - node _T_559 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_560 = cat(_T_559, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_561 = eq(_T_558, _T_560) @[exu_div_ctl.scala 846:54] - node _T_562 = bits(_T_561, 0, 0) @[exu_div_ctl.scala 846:83] - node _T_563 = bits(quotient_raw, 15, 13) @[exu_div_ctl.scala 846:48] - node _T_564 = mux(UInt<1>("h00"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_565 = cat(_T_564, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_566 = eq(_T_563, _T_565) @[exu_div_ctl.scala 846:54] - node _T_567 = bits(_T_566, 0, 0) @[exu_div_ctl.scala 846:83] - node _T_568 = mux(_T_537, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_569 = mux(_T_542, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_570 = mux(_T_547, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_571 = mux(_T_552, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_572 = mux(_T_557, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_573 = mux(_T_562, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_574 = mux(_T_567, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_575 = or(_T_568, _T_569) @[Mux.scala 27:72] - node _T_576 = or(_T_575, _T_570) @[Mux.scala 27:72] - node _T_577 = or(_T_576, _T_571) @[Mux.scala 27:72] - node _T_578 = or(_T_577, _T_572) @[Mux.scala 27:72] - node _T_579 = or(_T_578, _T_573) @[Mux.scala 27:72] - node _T_580 = or(_T_579, _T_574) @[Mux.scala 27:72] - wire _T_581 : UInt<1> @[Mux.scala 27:72] - _T_581 <= _T_580 @[Mux.scala 27:72] - node _T_582 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 846:114] - node _T_583 = eq(_T_582, UInt<1>("h01")) @[exu_div_ctl.scala 846:118] - node _T_584 = or(_T_581, _T_583) @[exu_div_ctl.scala 846:99] - node _T_585 = cat(_T_532, _T_584) @[Cat.scala 29:58] - node _T_586 = cat(_T_486, _T_509) @[Cat.scala 29:58] - node _T_587 = cat(_T_586, _T_585) @[Cat.scala 29:58] - quotient_new <= _T_587 @[exu_div_ctl.scala 835:16] - node _T_588 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 849:48] - node _T_589 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_590 = mux(twos_comp_b_sel, _T_588, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_591 = or(_T_589, _T_590) @[Mux.scala 27:72] + node _T_484 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 835:109] + node _T_485 = eq(_T_484, UInt<1>("h01")) @[exu_div_ctl.scala 835:113] + node _T_486 = or(_T_483, _T_485) @[exu_div_ctl.scala 835:94] + node _T_487 = bits(quotient_raw, 15, 4) @[exu_div_ctl.scala 836:31] + node _T_488 = eq(_T_487, UInt<12>("h01")) @[exu_div_ctl.scala 836:40] + node _T_489 = bits(quotient_raw, 15, 5) @[exu_div_ctl.scala 836:91] + node _T_490 = eq(_T_489, UInt<11>("h01")) @[exu_div_ctl.scala 836:98] + node _T_491 = bits(quotient_raw, 15, 6) @[exu_div_ctl.scala 836:148] + node _T_492 = eq(_T_491, UInt<10>("h01")) @[exu_div_ctl.scala 836:155] + node _T_493 = bits(quotient_raw, 15, 7) @[exu_div_ctl.scala 836:204] + node _T_494 = eq(_T_493, UInt<9>("h01")) @[exu_div_ctl.scala 836:211] + node _T_495 = bits(quotient_raw, 15, 12) @[exu_div_ctl.scala 837:21] + node _T_496 = eq(_T_495, UInt<4>("h01")) @[exu_div_ctl.scala 837:28] + node _T_497 = bits(quotient_raw, 15, 13) @[exu_div_ctl.scala 837:70] + node _T_498 = eq(_T_497, UInt<3>("h01")) @[exu_div_ctl.scala 837:77] + node _T_499 = bits(quotient_raw, 15, 14) @[exu_div_ctl.scala 837:118] + node _T_500 = eq(_T_499, UInt<2>("h01")) @[exu_div_ctl.scala 837:125] + node _T_501 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 837:165] + node _T_502 = eq(_T_501, UInt<1>("h01")) @[exu_div_ctl.scala 837:172] + node _T_503 = mux(_T_488, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_504 = mux(_T_490, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_505 = mux(_T_492, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_506 = mux(_T_494, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_507 = mux(_T_496, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_508 = mux(_T_498, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_509 = mux(_T_500, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_510 = mux(_T_502, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_511 = or(_T_503, _T_504) @[Mux.scala 27:72] + node _T_512 = or(_T_511, _T_505) @[Mux.scala 27:72] + node _T_513 = or(_T_512, _T_506) @[Mux.scala 27:72] + node _T_514 = or(_T_513, _T_507) @[Mux.scala 27:72] + node _T_515 = or(_T_514, _T_508) @[Mux.scala 27:72] + node _T_516 = or(_T_515, _T_509) @[Mux.scala 27:72] + node _T_517 = or(_T_516, _T_510) @[Mux.scala 27:72] + wire _T_518 : UInt<1> @[Mux.scala 27:72] + _T_518 <= _T_517 @[Mux.scala 27:72] + node _T_519 = bits(quotient_raw, 15, 2) @[exu_div_ctl.scala 838:30] + node _T_520 = eq(_T_519, UInt<14>("h01")) @[exu_div_ctl.scala 838:37] + node _T_521 = bits(quotient_raw, 15, 3) @[exu_div_ctl.scala 838:90] + node _T_522 = eq(_T_521, UInt<13>("h01")) @[exu_div_ctl.scala 838:97] + node _T_523 = bits(quotient_raw, 15, 6) @[exu_div_ctl.scala 838:149] + node _T_524 = eq(_T_523, UInt<10>("h01")) @[exu_div_ctl.scala 838:156] + node _T_525 = bits(quotient_raw, 15, 7) @[exu_div_ctl.scala 838:205] + node _T_526 = eq(_T_525, UInt<9>("h01")) @[exu_div_ctl.scala 838:212] + node _T_527 = bits(quotient_raw, 15, 10) @[exu_div_ctl.scala 839:23] + node _T_528 = eq(_T_527, UInt<6>("h01")) @[exu_div_ctl.scala 839:30] + node _T_529 = bits(quotient_raw, 15, 11) @[exu_div_ctl.scala 839:74] + node _T_530 = eq(_T_529, UInt<5>("h01")) @[exu_div_ctl.scala 839:81] + node _T_531 = bits(quotient_raw, 15, 14) @[exu_div_ctl.scala 839:124] + node _T_532 = eq(_T_531, UInt<2>("h01")) @[exu_div_ctl.scala 839:131] + node _T_533 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 839:171] + node _T_534 = eq(_T_533, UInt<1>("h01")) @[exu_div_ctl.scala 839:178] + node _T_535 = mux(_T_520, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_536 = mux(_T_522, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_537 = mux(_T_524, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_538 = mux(_T_526, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_539 = mux(_T_528, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_540 = mux(_T_530, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_541 = mux(_T_532, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_542 = mux(_T_534, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_543 = or(_T_535, _T_536) @[Mux.scala 27:72] + node _T_544 = or(_T_543, _T_537) @[Mux.scala 27:72] + node _T_545 = or(_T_544, _T_538) @[Mux.scala 27:72] + node _T_546 = or(_T_545, _T_539) @[Mux.scala 27:72] + node _T_547 = or(_T_546, _T_540) @[Mux.scala 27:72] + node _T_548 = or(_T_547, _T_541) @[Mux.scala 27:72] + node _T_549 = or(_T_548, _T_542) @[Mux.scala 27:72] + wire _T_550 : UInt<1> @[Mux.scala 27:72] + _T_550 <= _T_549 @[Mux.scala 27:72] + node _T_551 = bits(quotient_raw, 15, 1) @[exu_div_ctl.scala 840:48] + node _T_552 = mux(UInt<1>("h00"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12] + node _T_553 = cat(_T_552, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_554 = eq(_T_551, _T_553) @[exu_div_ctl.scala 840:54] + node _T_555 = bits(_T_554, 0, 0) @[exu_div_ctl.scala 840:83] + node _T_556 = bits(quotient_raw, 15, 3) @[exu_div_ctl.scala 840:48] + node _T_557 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] + node _T_558 = cat(_T_557, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_559 = eq(_T_556, _T_558) @[exu_div_ctl.scala 840:54] + node _T_560 = bits(_T_559, 0, 0) @[exu_div_ctl.scala 840:83] + node _T_561 = bits(quotient_raw, 15, 5) @[exu_div_ctl.scala 840:48] + node _T_562 = mux(UInt<1>("h00"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_563 = cat(_T_562, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_564 = eq(_T_561, _T_563) @[exu_div_ctl.scala 840:54] + node _T_565 = bits(_T_564, 0, 0) @[exu_div_ctl.scala 840:83] + node _T_566 = bits(quotient_raw, 15, 7) @[exu_div_ctl.scala 840:48] + node _T_567 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_568 = cat(_T_567, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_569 = eq(_T_566, _T_568) @[exu_div_ctl.scala 840:54] + node _T_570 = bits(_T_569, 0, 0) @[exu_div_ctl.scala 840:83] + node _T_571 = bits(quotient_raw, 15, 9) @[exu_div_ctl.scala 840:48] + node _T_572 = mux(UInt<1>("h00"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] + node _T_573 = cat(_T_572, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_574 = eq(_T_571, _T_573) @[exu_div_ctl.scala 840:54] + node _T_575 = bits(_T_574, 0, 0) @[exu_div_ctl.scala 840:83] + node _T_576 = bits(quotient_raw, 15, 11) @[exu_div_ctl.scala 840:48] + node _T_577 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_578 = cat(_T_577, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_579 = eq(_T_576, _T_578) @[exu_div_ctl.scala 840:54] + node _T_580 = bits(_T_579, 0, 0) @[exu_div_ctl.scala 840:83] + node _T_581 = bits(quotient_raw, 15, 13) @[exu_div_ctl.scala 840:48] + node _T_582 = mux(UInt<1>("h00"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = cat(_T_582, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_584 = eq(_T_581, _T_583) @[exu_div_ctl.scala 840:54] + node _T_585 = bits(_T_584, 0, 0) @[exu_div_ctl.scala 840:83] + node _T_586 = mux(_T_555, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_587 = mux(_T_560, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_588 = mux(_T_565, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_589 = mux(_T_570, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_590 = mux(_T_575, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_591 = mux(_T_580, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_592 = mux(_T_585, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_593 = or(_T_586, _T_587) @[Mux.scala 27:72] + node _T_594 = or(_T_593, _T_588) @[Mux.scala 27:72] + node _T_595 = or(_T_594, _T_589) @[Mux.scala 27:72] + node _T_596 = or(_T_595, _T_590) @[Mux.scala 27:72] + node _T_597 = or(_T_596, _T_591) @[Mux.scala 27:72] + node _T_598 = or(_T_597, _T_592) @[Mux.scala 27:72] + wire _T_599 : UInt<1> @[Mux.scala 27:72] + _T_599 <= _T_598 @[Mux.scala 27:72] + node _T_600 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 840:114] + node _T_601 = eq(_T_600, UInt<1>("h01")) @[exu_div_ctl.scala 840:118] + node _T_602 = or(_T_599, _T_601) @[exu_div_ctl.scala 840:99] + node _T_603 = cat(_T_550, _T_602) @[Cat.scala 29:58] + node _T_604 = cat(_T_486, _T_518) @[Cat.scala 29:58] + node _T_605 = cat(_T_604, _T_603) @[Cat.scala 29:58] + quotient_new <= _T_605 @[exu_div_ctl.scala 834:16] + node _T_606 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 843:50] + node _T_607 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_608 = mux(twos_comp_b_sel, _T_606, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_609 = or(_T_607, _T_608) @[Mux.scala 27:72] wire twos_comp_in : UInt<32> @[Mux.scala 27:72] - twos_comp_in <= _T_591 @[Mux.scala 27:72] - wire _T_592 : UInt<1>[31] @[lib.scala 426:20] - node _T_593 = bits(twos_comp_in, 0, 0) @[lib.scala 428:27] - node _T_594 = orr(_T_593) @[lib.scala 428:35] - node _T_595 = bits(twos_comp_in, 1, 1) @[lib.scala 428:44] - node _T_596 = not(_T_595) @[lib.scala 428:40] - node _T_597 = bits(twos_comp_in, 1, 1) @[lib.scala 428:51] - node _T_598 = mux(_T_594, _T_596, _T_597) @[lib.scala 428:23] - _T_592[0] <= _T_598 @[lib.scala 428:17] - node _T_599 = bits(twos_comp_in, 1, 0) @[lib.scala 428:27] - node _T_600 = orr(_T_599) @[lib.scala 428:35] - node _T_601 = bits(twos_comp_in, 2, 2) @[lib.scala 428:44] - node _T_602 = not(_T_601) @[lib.scala 428:40] - node _T_603 = bits(twos_comp_in, 2, 2) @[lib.scala 428:51] - node _T_604 = mux(_T_600, _T_602, _T_603) @[lib.scala 428:23] - _T_592[1] <= _T_604 @[lib.scala 428:17] - node _T_605 = bits(twos_comp_in, 2, 0) @[lib.scala 428:27] - node _T_606 = orr(_T_605) @[lib.scala 428:35] - node _T_607 = bits(twos_comp_in, 3, 3) @[lib.scala 428:44] - node _T_608 = not(_T_607) @[lib.scala 428:40] - node _T_609 = bits(twos_comp_in, 3, 3) @[lib.scala 428:51] - node _T_610 = mux(_T_606, _T_608, _T_609) @[lib.scala 428:23] - _T_592[2] <= _T_610 @[lib.scala 428:17] - node _T_611 = bits(twos_comp_in, 3, 0) @[lib.scala 428:27] + twos_comp_in <= _T_609 @[Mux.scala 27:72] + wire _T_610 : UInt<1>[31] @[lib.scala 426:20] + node _T_611 = bits(twos_comp_in, 0, 0) @[lib.scala 428:27] node _T_612 = orr(_T_611) @[lib.scala 428:35] - node _T_613 = bits(twos_comp_in, 4, 4) @[lib.scala 428:44] + node _T_613 = bits(twos_comp_in, 1, 1) @[lib.scala 428:44] node _T_614 = not(_T_613) @[lib.scala 428:40] - node _T_615 = bits(twos_comp_in, 4, 4) @[lib.scala 428:51] + node _T_615 = bits(twos_comp_in, 1, 1) @[lib.scala 428:51] node _T_616 = mux(_T_612, _T_614, _T_615) @[lib.scala 428:23] - _T_592[3] <= _T_616 @[lib.scala 428:17] - node _T_617 = bits(twos_comp_in, 4, 0) @[lib.scala 428:27] + _T_610[0] <= _T_616 @[lib.scala 428:17] + node _T_617 = bits(twos_comp_in, 1, 0) @[lib.scala 428:27] node _T_618 = orr(_T_617) @[lib.scala 428:35] - node _T_619 = bits(twos_comp_in, 5, 5) @[lib.scala 428:44] + node _T_619 = bits(twos_comp_in, 2, 2) @[lib.scala 428:44] node _T_620 = not(_T_619) @[lib.scala 428:40] - node _T_621 = bits(twos_comp_in, 5, 5) @[lib.scala 428:51] + node _T_621 = bits(twos_comp_in, 2, 2) @[lib.scala 428:51] node _T_622 = mux(_T_618, _T_620, _T_621) @[lib.scala 428:23] - _T_592[4] <= _T_622 @[lib.scala 428:17] - node _T_623 = bits(twos_comp_in, 5, 0) @[lib.scala 428:27] + _T_610[1] <= _T_622 @[lib.scala 428:17] + node _T_623 = bits(twos_comp_in, 2, 0) @[lib.scala 428:27] node _T_624 = orr(_T_623) @[lib.scala 428:35] - node _T_625 = bits(twos_comp_in, 6, 6) @[lib.scala 428:44] + node _T_625 = bits(twos_comp_in, 3, 3) @[lib.scala 428:44] node _T_626 = not(_T_625) @[lib.scala 428:40] - node _T_627 = bits(twos_comp_in, 6, 6) @[lib.scala 428:51] + node _T_627 = bits(twos_comp_in, 3, 3) @[lib.scala 428:51] node _T_628 = mux(_T_624, _T_626, _T_627) @[lib.scala 428:23] - _T_592[5] <= _T_628 @[lib.scala 428:17] - node _T_629 = bits(twos_comp_in, 6, 0) @[lib.scala 428:27] + _T_610[2] <= _T_628 @[lib.scala 428:17] + node _T_629 = bits(twos_comp_in, 3, 0) @[lib.scala 428:27] node _T_630 = orr(_T_629) @[lib.scala 428:35] - node _T_631 = bits(twos_comp_in, 7, 7) @[lib.scala 428:44] + node _T_631 = bits(twos_comp_in, 4, 4) @[lib.scala 428:44] node _T_632 = not(_T_631) @[lib.scala 428:40] - node _T_633 = bits(twos_comp_in, 7, 7) @[lib.scala 428:51] + node _T_633 = bits(twos_comp_in, 4, 4) @[lib.scala 428:51] node _T_634 = mux(_T_630, _T_632, _T_633) @[lib.scala 428:23] - _T_592[6] <= _T_634 @[lib.scala 428:17] - node _T_635 = bits(twos_comp_in, 7, 0) @[lib.scala 428:27] + _T_610[3] <= _T_634 @[lib.scala 428:17] + node _T_635 = bits(twos_comp_in, 4, 0) @[lib.scala 428:27] node _T_636 = orr(_T_635) @[lib.scala 428:35] - node _T_637 = bits(twos_comp_in, 8, 8) @[lib.scala 428:44] + node _T_637 = bits(twos_comp_in, 5, 5) @[lib.scala 428:44] node _T_638 = not(_T_637) @[lib.scala 428:40] - node _T_639 = bits(twos_comp_in, 8, 8) @[lib.scala 428:51] + node _T_639 = bits(twos_comp_in, 5, 5) @[lib.scala 428:51] node _T_640 = mux(_T_636, _T_638, _T_639) @[lib.scala 428:23] - _T_592[7] <= _T_640 @[lib.scala 428:17] - node _T_641 = bits(twos_comp_in, 8, 0) @[lib.scala 428:27] + _T_610[4] <= _T_640 @[lib.scala 428:17] + node _T_641 = bits(twos_comp_in, 5, 0) @[lib.scala 428:27] node _T_642 = orr(_T_641) @[lib.scala 428:35] - node _T_643 = bits(twos_comp_in, 9, 9) @[lib.scala 428:44] + node _T_643 = bits(twos_comp_in, 6, 6) @[lib.scala 428:44] node _T_644 = not(_T_643) @[lib.scala 428:40] - node _T_645 = bits(twos_comp_in, 9, 9) @[lib.scala 428:51] + node _T_645 = bits(twos_comp_in, 6, 6) @[lib.scala 428:51] node _T_646 = mux(_T_642, _T_644, _T_645) @[lib.scala 428:23] - _T_592[8] <= _T_646 @[lib.scala 428:17] - node _T_647 = bits(twos_comp_in, 9, 0) @[lib.scala 428:27] + _T_610[5] <= _T_646 @[lib.scala 428:17] + node _T_647 = bits(twos_comp_in, 6, 0) @[lib.scala 428:27] node _T_648 = orr(_T_647) @[lib.scala 428:35] - node _T_649 = bits(twos_comp_in, 10, 10) @[lib.scala 428:44] + node _T_649 = bits(twos_comp_in, 7, 7) @[lib.scala 428:44] node _T_650 = not(_T_649) @[lib.scala 428:40] - node _T_651 = bits(twos_comp_in, 10, 10) @[lib.scala 428:51] + node _T_651 = bits(twos_comp_in, 7, 7) @[lib.scala 428:51] node _T_652 = mux(_T_648, _T_650, _T_651) @[lib.scala 428:23] - _T_592[9] <= _T_652 @[lib.scala 428:17] - node _T_653 = bits(twos_comp_in, 10, 0) @[lib.scala 428:27] + _T_610[6] <= _T_652 @[lib.scala 428:17] + node _T_653 = bits(twos_comp_in, 7, 0) @[lib.scala 428:27] node _T_654 = orr(_T_653) @[lib.scala 428:35] - node _T_655 = bits(twos_comp_in, 11, 11) @[lib.scala 428:44] + node _T_655 = bits(twos_comp_in, 8, 8) @[lib.scala 428:44] node _T_656 = not(_T_655) @[lib.scala 428:40] - node _T_657 = bits(twos_comp_in, 11, 11) @[lib.scala 428:51] + node _T_657 = bits(twos_comp_in, 8, 8) @[lib.scala 428:51] node _T_658 = mux(_T_654, _T_656, _T_657) @[lib.scala 428:23] - _T_592[10] <= _T_658 @[lib.scala 428:17] - node _T_659 = bits(twos_comp_in, 11, 0) @[lib.scala 428:27] + _T_610[7] <= _T_658 @[lib.scala 428:17] + node _T_659 = bits(twos_comp_in, 8, 0) @[lib.scala 428:27] node _T_660 = orr(_T_659) @[lib.scala 428:35] - node _T_661 = bits(twos_comp_in, 12, 12) @[lib.scala 428:44] + node _T_661 = bits(twos_comp_in, 9, 9) @[lib.scala 428:44] node _T_662 = not(_T_661) @[lib.scala 428:40] - node _T_663 = bits(twos_comp_in, 12, 12) @[lib.scala 428:51] + node _T_663 = bits(twos_comp_in, 9, 9) @[lib.scala 428:51] node _T_664 = mux(_T_660, _T_662, _T_663) @[lib.scala 428:23] - _T_592[11] <= _T_664 @[lib.scala 428:17] - node _T_665 = bits(twos_comp_in, 12, 0) @[lib.scala 428:27] + _T_610[8] <= _T_664 @[lib.scala 428:17] + node _T_665 = bits(twos_comp_in, 9, 0) @[lib.scala 428:27] node _T_666 = orr(_T_665) @[lib.scala 428:35] - node _T_667 = bits(twos_comp_in, 13, 13) @[lib.scala 428:44] + node _T_667 = bits(twos_comp_in, 10, 10) @[lib.scala 428:44] node _T_668 = not(_T_667) @[lib.scala 428:40] - node _T_669 = bits(twos_comp_in, 13, 13) @[lib.scala 428:51] + node _T_669 = bits(twos_comp_in, 10, 10) @[lib.scala 428:51] node _T_670 = mux(_T_666, _T_668, _T_669) @[lib.scala 428:23] - _T_592[12] <= _T_670 @[lib.scala 428:17] - node _T_671 = bits(twos_comp_in, 13, 0) @[lib.scala 428:27] + _T_610[9] <= _T_670 @[lib.scala 428:17] + node _T_671 = bits(twos_comp_in, 10, 0) @[lib.scala 428:27] node _T_672 = orr(_T_671) @[lib.scala 428:35] - node _T_673 = bits(twos_comp_in, 14, 14) @[lib.scala 428:44] + node _T_673 = bits(twos_comp_in, 11, 11) @[lib.scala 428:44] node _T_674 = not(_T_673) @[lib.scala 428:40] - node _T_675 = bits(twos_comp_in, 14, 14) @[lib.scala 428:51] + node _T_675 = bits(twos_comp_in, 11, 11) @[lib.scala 428:51] node _T_676 = mux(_T_672, _T_674, _T_675) @[lib.scala 428:23] - _T_592[13] <= _T_676 @[lib.scala 428:17] - node _T_677 = bits(twos_comp_in, 14, 0) @[lib.scala 428:27] + _T_610[10] <= _T_676 @[lib.scala 428:17] + node _T_677 = bits(twos_comp_in, 11, 0) @[lib.scala 428:27] node _T_678 = orr(_T_677) @[lib.scala 428:35] - node _T_679 = bits(twos_comp_in, 15, 15) @[lib.scala 428:44] + node _T_679 = bits(twos_comp_in, 12, 12) @[lib.scala 428:44] node _T_680 = not(_T_679) @[lib.scala 428:40] - node _T_681 = bits(twos_comp_in, 15, 15) @[lib.scala 428:51] + node _T_681 = bits(twos_comp_in, 12, 12) @[lib.scala 428:51] node _T_682 = mux(_T_678, _T_680, _T_681) @[lib.scala 428:23] - _T_592[14] <= _T_682 @[lib.scala 428:17] - node _T_683 = bits(twos_comp_in, 15, 0) @[lib.scala 428:27] + _T_610[11] <= _T_682 @[lib.scala 428:17] + node _T_683 = bits(twos_comp_in, 12, 0) @[lib.scala 428:27] node _T_684 = orr(_T_683) @[lib.scala 428:35] - node _T_685 = bits(twos_comp_in, 16, 16) @[lib.scala 428:44] + node _T_685 = bits(twos_comp_in, 13, 13) @[lib.scala 428:44] node _T_686 = not(_T_685) @[lib.scala 428:40] - node _T_687 = bits(twos_comp_in, 16, 16) @[lib.scala 428:51] + node _T_687 = bits(twos_comp_in, 13, 13) @[lib.scala 428:51] node _T_688 = mux(_T_684, _T_686, _T_687) @[lib.scala 428:23] - _T_592[15] <= _T_688 @[lib.scala 428:17] - node _T_689 = bits(twos_comp_in, 16, 0) @[lib.scala 428:27] + _T_610[12] <= _T_688 @[lib.scala 428:17] + node _T_689 = bits(twos_comp_in, 13, 0) @[lib.scala 428:27] node _T_690 = orr(_T_689) @[lib.scala 428:35] - node _T_691 = bits(twos_comp_in, 17, 17) @[lib.scala 428:44] + node _T_691 = bits(twos_comp_in, 14, 14) @[lib.scala 428:44] node _T_692 = not(_T_691) @[lib.scala 428:40] - node _T_693 = bits(twos_comp_in, 17, 17) @[lib.scala 428:51] + node _T_693 = bits(twos_comp_in, 14, 14) @[lib.scala 428:51] node _T_694 = mux(_T_690, _T_692, _T_693) @[lib.scala 428:23] - _T_592[16] <= _T_694 @[lib.scala 428:17] - node _T_695 = bits(twos_comp_in, 17, 0) @[lib.scala 428:27] + _T_610[13] <= _T_694 @[lib.scala 428:17] + node _T_695 = bits(twos_comp_in, 14, 0) @[lib.scala 428:27] node _T_696 = orr(_T_695) @[lib.scala 428:35] - node _T_697 = bits(twos_comp_in, 18, 18) @[lib.scala 428:44] + node _T_697 = bits(twos_comp_in, 15, 15) @[lib.scala 428:44] node _T_698 = not(_T_697) @[lib.scala 428:40] - node _T_699 = bits(twos_comp_in, 18, 18) @[lib.scala 428:51] + node _T_699 = bits(twos_comp_in, 15, 15) @[lib.scala 428:51] node _T_700 = mux(_T_696, _T_698, _T_699) @[lib.scala 428:23] - _T_592[17] <= _T_700 @[lib.scala 428:17] - node _T_701 = bits(twos_comp_in, 18, 0) @[lib.scala 428:27] + _T_610[14] <= _T_700 @[lib.scala 428:17] + node _T_701 = bits(twos_comp_in, 15, 0) @[lib.scala 428:27] node _T_702 = orr(_T_701) @[lib.scala 428:35] - node _T_703 = bits(twos_comp_in, 19, 19) @[lib.scala 428:44] + node _T_703 = bits(twos_comp_in, 16, 16) @[lib.scala 428:44] node _T_704 = not(_T_703) @[lib.scala 428:40] - node _T_705 = bits(twos_comp_in, 19, 19) @[lib.scala 428:51] + node _T_705 = bits(twos_comp_in, 16, 16) @[lib.scala 428:51] node _T_706 = mux(_T_702, _T_704, _T_705) @[lib.scala 428:23] - _T_592[18] <= _T_706 @[lib.scala 428:17] - node _T_707 = bits(twos_comp_in, 19, 0) @[lib.scala 428:27] + _T_610[15] <= _T_706 @[lib.scala 428:17] + node _T_707 = bits(twos_comp_in, 16, 0) @[lib.scala 428:27] node _T_708 = orr(_T_707) @[lib.scala 428:35] - node _T_709 = bits(twos_comp_in, 20, 20) @[lib.scala 428:44] + node _T_709 = bits(twos_comp_in, 17, 17) @[lib.scala 428:44] node _T_710 = not(_T_709) @[lib.scala 428:40] - node _T_711 = bits(twos_comp_in, 20, 20) @[lib.scala 428:51] + node _T_711 = bits(twos_comp_in, 17, 17) @[lib.scala 428:51] node _T_712 = mux(_T_708, _T_710, _T_711) @[lib.scala 428:23] - _T_592[19] <= _T_712 @[lib.scala 428:17] - node _T_713 = bits(twos_comp_in, 20, 0) @[lib.scala 428:27] + _T_610[16] <= _T_712 @[lib.scala 428:17] + node _T_713 = bits(twos_comp_in, 17, 0) @[lib.scala 428:27] node _T_714 = orr(_T_713) @[lib.scala 428:35] - node _T_715 = bits(twos_comp_in, 21, 21) @[lib.scala 428:44] + node _T_715 = bits(twos_comp_in, 18, 18) @[lib.scala 428:44] node _T_716 = not(_T_715) @[lib.scala 428:40] - node _T_717 = bits(twos_comp_in, 21, 21) @[lib.scala 428:51] + node _T_717 = bits(twos_comp_in, 18, 18) @[lib.scala 428:51] node _T_718 = mux(_T_714, _T_716, _T_717) @[lib.scala 428:23] - _T_592[20] <= _T_718 @[lib.scala 428:17] - node _T_719 = bits(twos_comp_in, 21, 0) @[lib.scala 428:27] + _T_610[17] <= _T_718 @[lib.scala 428:17] + node _T_719 = bits(twos_comp_in, 18, 0) @[lib.scala 428:27] node _T_720 = orr(_T_719) @[lib.scala 428:35] - node _T_721 = bits(twos_comp_in, 22, 22) @[lib.scala 428:44] + node _T_721 = bits(twos_comp_in, 19, 19) @[lib.scala 428:44] node _T_722 = not(_T_721) @[lib.scala 428:40] - node _T_723 = bits(twos_comp_in, 22, 22) @[lib.scala 428:51] + node _T_723 = bits(twos_comp_in, 19, 19) @[lib.scala 428:51] node _T_724 = mux(_T_720, _T_722, _T_723) @[lib.scala 428:23] - _T_592[21] <= _T_724 @[lib.scala 428:17] - node _T_725 = bits(twos_comp_in, 22, 0) @[lib.scala 428:27] + _T_610[18] <= _T_724 @[lib.scala 428:17] + node _T_725 = bits(twos_comp_in, 19, 0) @[lib.scala 428:27] node _T_726 = orr(_T_725) @[lib.scala 428:35] - node _T_727 = bits(twos_comp_in, 23, 23) @[lib.scala 428:44] + node _T_727 = bits(twos_comp_in, 20, 20) @[lib.scala 428:44] node _T_728 = not(_T_727) @[lib.scala 428:40] - node _T_729 = bits(twos_comp_in, 23, 23) @[lib.scala 428:51] + node _T_729 = bits(twos_comp_in, 20, 20) @[lib.scala 428:51] node _T_730 = mux(_T_726, _T_728, _T_729) @[lib.scala 428:23] - _T_592[22] <= _T_730 @[lib.scala 428:17] - node _T_731 = bits(twos_comp_in, 23, 0) @[lib.scala 428:27] + _T_610[19] <= _T_730 @[lib.scala 428:17] + node _T_731 = bits(twos_comp_in, 20, 0) @[lib.scala 428:27] node _T_732 = orr(_T_731) @[lib.scala 428:35] - node _T_733 = bits(twos_comp_in, 24, 24) @[lib.scala 428:44] + node _T_733 = bits(twos_comp_in, 21, 21) @[lib.scala 428:44] node _T_734 = not(_T_733) @[lib.scala 428:40] - node _T_735 = bits(twos_comp_in, 24, 24) @[lib.scala 428:51] + node _T_735 = bits(twos_comp_in, 21, 21) @[lib.scala 428:51] node _T_736 = mux(_T_732, _T_734, _T_735) @[lib.scala 428:23] - _T_592[23] <= _T_736 @[lib.scala 428:17] - node _T_737 = bits(twos_comp_in, 24, 0) @[lib.scala 428:27] + _T_610[20] <= _T_736 @[lib.scala 428:17] + node _T_737 = bits(twos_comp_in, 21, 0) @[lib.scala 428:27] node _T_738 = orr(_T_737) @[lib.scala 428:35] - node _T_739 = bits(twos_comp_in, 25, 25) @[lib.scala 428:44] + node _T_739 = bits(twos_comp_in, 22, 22) @[lib.scala 428:44] node _T_740 = not(_T_739) @[lib.scala 428:40] - node _T_741 = bits(twos_comp_in, 25, 25) @[lib.scala 428:51] + node _T_741 = bits(twos_comp_in, 22, 22) @[lib.scala 428:51] node _T_742 = mux(_T_738, _T_740, _T_741) @[lib.scala 428:23] - _T_592[24] <= _T_742 @[lib.scala 428:17] - node _T_743 = bits(twos_comp_in, 25, 0) @[lib.scala 428:27] + _T_610[21] <= _T_742 @[lib.scala 428:17] + node _T_743 = bits(twos_comp_in, 22, 0) @[lib.scala 428:27] node _T_744 = orr(_T_743) @[lib.scala 428:35] - node _T_745 = bits(twos_comp_in, 26, 26) @[lib.scala 428:44] + node _T_745 = bits(twos_comp_in, 23, 23) @[lib.scala 428:44] node _T_746 = not(_T_745) @[lib.scala 428:40] - node _T_747 = bits(twos_comp_in, 26, 26) @[lib.scala 428:51] + node _T_747 = bits(twos_comp_in, 23, 23) @[lib.scala 428:51] node _T_748 = mux(_T_744, _T_746, _T_747) @[lib.scala 428:23] - _T_592[25] <= _T_748 @[lib.scala 428:17] - node _T_749 = bits(twos_comp_in, 26, 0) @[lib.scala 428:27] + _T_610[22] <= _T_748 @[lib.scala 428:17] + node _T_749 = bits(twos_comp_in, 23, 0) @[lib.scala 428:27] node _T_750 = orr(_T_749) @[lib.scala 428:35] - node _T_751 = bits(twos_comp_in, 27, 27) @[lib.scala 428:44] + node _T_751 = bits(twos_comp_in, 24, 24) @[lib.scala 428:44] node _T_752 = not(_T_751) @[lib.scala 428:40] - node _T_753 = bits(twos_comp_in, 27, 27) @[lib.scala 428:51] + node _T_753 = bits(twos_comp_in, 24, 24) @[lib.scala 428:51] node _T_754 = mux(_T_750, _T_752, _T_753) @[lib.scala 428:23] - _T_592[26] <= _T_754 @[lib.scala 428:17] - node _T_755 = bits(twos_comp_in, 27, 0) @[lib.scala 428:27] + _T_610[23] <= _T_754 @[lib.scala 428:17] + node _T_755 = bits(twos_comp_in, 24, 0) @[lib.scala 428:27] node _T_756 = orr(_T_755) @[lib.scala 428:35] - node _T_757 = bits(twos_comp_in, 28, 28) @[lib.scala 428:44] + node _T_757 = bits(twos_comp_in, 25, 25) @[lib.scala 428:44] node _T_758 = not(_T_757) @[lib.scala 428:40] - node _T_759 = bits(twos_comp_in, 28, 28) @[lib.scala 428:51] + node _T_759 = bits(twos_comp_in, 25, 25) @[lib.scala 428:51] node _T_760 = mux(_T_756, _T_758, _T_759) @[lib.scala 428:23] - _T_592[27] <= _T_760 @[lib.scala 428:17] - node _T_761 = bits(twos_comp_in, 28, 0) @[lib.scala 428:27] + _T_610[24] <= _T_760 @[lib.scala 428:17] + node _T_761 = bits(twos_comp_in, 25, 0) @[lib.scala 428:27] node _T_762 = orr(_T_761) @[lib.scala 428:35] - node _T_763 = bits(twos_comp_in, 29, 29) @[lib.scala 428:44] + node _T_763 = bits(twos_comp_in, 26, 26) @[lib.scala 428:44] node _T_764 = not(_T_763) @[lib.scala 428:40] - node _T_765 = bits(twos_comp_in, 29, 29) @[lib.scala 428:51] + node _T_765 = bits(twos_comp_in, 26, 26) @[lib.scala 428:51] node _T_766 = mux(_T_762, _T_764, _T_765) @[lib.scala 428:23] - _T_592[28] <= _T_766 @[lib.scala 428:17] - node _T_767 = bits(twos_comp_in, 29, 0) @[lib.scala 428:27] + _T_610[25] <= _T_766 @[lib.scala 428:17] + node _T_767 = bits(twos_comp_in, 26, 0) @[lib.scala 428:27] node _T_768 = orr(_T_767) @[lib.scala 428:35] - node _T_769 = bits(twos_comp_in, 30, 30) @[lib.scala 428:44] + node _T_769 = bits(twos_comp_in, 27, 27) @[lib.scala 428:44] node _T_770 = not(_T_769) @[lib.scala 428:40] - node _T_771 = bits(twos_comp_in, 30, 30) @[lib.scala 428:51] + node _T_771 = bits(twos_comp_in, 27, 27) @[lib.scala 428:51] node _T_772 = mux(_T_768, _T_770, _T_771) @[lib.scala 428:23] - _T_592[29] <= _T_772 @[lib.scala 428:17] - node _T_773 = bits(twos_comp_in, 30, 0) @[lib.scala 428:27] + _T_610[26] <= _T_772 @[lib.scala 428:17] + node _T_773 = bits(twos_comp_in, 27, 0) @[lib.scala 428:27] node _T_774 = orr(_T_773) @[lib.scala 428:35] - node _T_775 = bits(twos_comp_in, 31, 31) @[lib.scala 428:44] + node _T_775 = bits(twos_comp_in, 28, 28) @[lib.scala 428:44] node _T_776 = not(_T_775) @[lib.scala 428:40] - node _T_777 = bits(twos_comp_in, 31, 31) @[lib.scala 428:51] + node _T_777 = bits(twos_comp_in, 28, 28) @[lib.scala 428:51] node _T_778 = mux(_T_774, _T_776, _T_777) @[lib.scala 428:23] - _T_592[30] <= _T_778 @[lib.scala 428:17] - node _T_779 = cat(_T_592[2], _T_592[1]) @[lib.scala 430:14] - node _T_780 = cat(_T_779, _T_592[0]) @[lib.scala 430:14] - node _T_781 = cat(_T_592[4], _T_592[3]) @[lib.scala 430:14] - node _T_782 = cat(_T_592[6], _T_592[5]) @[lib.scala 430:14] - node _T_783 = cat(_T_782, _T_781) @[lib.scala 430:14] - node _T_784 = cat(_T_783, _T_780) @[lib.scala 430:14] - node _T_785 = cat(_T_592[8], _T_592[7]) @[lib.scala 430:14] - node _T_786 = cat(_T_592[10], _T_592[9]) @[lib.scala 430:14] - node _T_787 = cat(_T_786, _T_785) @[lib.scala 430:14] - node _T_788 = cat(_T_592[12], _T_592[11]) @[lib.scala 430:14] - node _T_789 = cat(_T_592[14], _T_592[13]) @[lib.scala 430:14] - node _T_790 = cat(_T_789, _T_788) @[lib.scala 430:14] - node _T_791 = cat(_T_790, _T_787) @[lib.scala 430:14] - node _T_792 = cat(_T_791, _T_784) @[lib.scala 430:14] - node _T_793 = cat(_T_592[16], _T_592[15]) @[lib.scala 430:14] - node _T_794 = cat(_T_592[18], _T_592[17]) @[lib.scala 430:14] - node _T_795 = cat(_T_794, _T_793) @[lib.scala 430:14] - node _T_796 = cat(_T_592[20], _T_592[19]) @[lib.scala 430:14] - node _T_797 = cat(_T_592[22], _T_592[21]) @[lib.scala 430:14] - node _T_798 = cat(_T_797, _T_796) @[lib.scala 430:14] - node _T_799 = cat(_T_798, _T_795) @[lib.scala 430:14] - node _T_800 = cat(_T_592[24], _T_592[23]) @[lib.scala 430:14] - node _T_801 = cat(_T_592[26], _T_592[25]) @[lib.scala 430:14] - node _T_802 = cat(_T_801, _T_800) @[lib.scala 430:14] - node _T_803 = cat(_T_592[28], _T_592[27]) @[lib.scala 430:14] - node _T_804 = cat(_T_592[30], _T_592[29]) @[lib.scala 430:14] + _T_610[27] <= _T_778 @[lib.scala 428:17] + node _T_779 = bits(twos_comp_in, 28, 0) @[lib.scala 428:27] + node _T_780 = orr(_T_779) @[lib.scala 428:35] + node _T_781 = bits(twos_comp_in, 29, 29) @[lib.scala 428:44] + node _T_782 = not(_T_781) @[lib.scala 428:40] + node _T_783 = bits(twos_comp_in, 29, 29) @[lib.scala 428:51] + node _T_784 = mux(_T_780, _T_782, _T_783) @[lib.scala 428:23] + _T_610[28] <= _T_784 @[lib.scala 428:17] + node _T_785 = bits(twos_comp_in, 29, 0) @[lib.scala 428:27] + node _T_786 = orr(_T_785) @[lib.scala 428:35] + node _T_787 = bits(twos_comp_in, 30, 30) @[lib.scala 428:44] + node _T_788 = not(_T_787) @[lib.scala 428:40] + node _T_789 = bits(twos_comp_in, 30, 30) @[lib.scala 428:51] + node _T_790 = mux(_T_786, _T_788, _T_789) @[lib.scala 428:23] + _T_610[29] <= _T_790 @[lib.scala 428:17] + node _T_791 = bits(twos_comp_in, 30, 0) @[lib.scala 428:27] + node _T_792 = orr(_T_791) @[lib.scala 428:35] + node _T_793 = bits(twos_comp_in, 31, 31) @[lib.scala 428:44] + node _T_794 = not(_T_793) @[lib.scala 428:40] + node _T_795 = bits(twos_comp_in, 31, 31) @[lib.scala 428:51] + node _T_796 = mux(_T_792, _T_794, _T_795) @[lib.scala 428:23] + _T_610[30] <= _T_796 @[lib.scala 428:17] + node _T_797 = cat(_T_610[2], _T_610[1]) @[lib.scala 430:14] + node _T_798 = cat(_T_797, _T_610[0]) @[lib.scala 430:14] + node _T_799 = cat(_T_610[4], _T_610[3]) @[lib.scala 430:14] + node _T_800 = cat(_T_610[6], _T_610[5]) @[lib.scala 430:14] + node _T_801 = cat(_T_800, _T_799) @[lib.scala 430:14] + node _T_802 = cat(_T_801, _T_798) @[lib.scala 430:14] + node _T_803 = cat(_T_610[8], _T_610[7]) @[lib.scala 430:14] + node _T_804 = cat(_T_610[10], _T_610[9]) @[lib.scala 430:14] node _T_805 = cat(_T_804, _T_803) @[lib.scala 430:14] - node _T_806 = cat(_T_805, _T_802) @[lib.scala 430:14] - node _T_807 = cat(_T_806, _T_799) @[lib.scala 430:14] - node _T_808 = cat(_T_807, _T_792) @[lib.scala 430:14] - node _T_809 = bits(twos_comp_in, 0, 0) @[lib.scala 430:24] - node twos_comp_out = cat(_T_808, _T_809) @[Cat.scala 29:58] - node _T_810 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 853:6] - node _T_811 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 853:17] - node _T_812 = and(_T_810, _T_811) @[exu_div_ctl.scala 853:15] - node _T_813 = bits(_T_812, 0, 0) @[exu_div_ctl.scala 853:36] - node _T_814 = bits(io.dividend_in, 31, 0) @[exu_div_ctl.scala 853:60] - node _T_815 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 854:53] - node _T_816 = cat(_T_815, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_817 = bits(ar_shifted, 31, 0) @[exu_div_ctl.scala 855:55] - node _T_818 = mux(_T_813, _T_814, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_819 = mux(a_shift, _T_816, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_820 = mux(shortq_enable_ff, _T_817, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_821 = or(_T_818, _T_819) @[Mux.scala 27:72] - node _T_822 = or(_T_821, _T_820) @[Mux.scala 27:72] + node _T_806 = cat(_T_610[12], _T_610[11]) @[lib.scala 430:14] + node _T_807 = cat(_T_610[14], _T_610[13]) @[lib.scala 430:14] + node _T_808 = cat(_T_807, _T_806) @[lib.scala 430:14] + node _T_809 = cat(_T_808, _T_805) @[lib.scala 430:14] + node _T_810 = cat(_T_809, _T_802) @[lib.scala 430:14] + node _T_811 = cat(_T_610[16], _T_610[15]) @[lib.scala 430:14] + node _T_812 = cat(_T_610[18], _T_610[17]) @[lib.scala 430:14] + node _T_813 = cat(_T_812, _T_811) @[lib.scala 430:14] + node _T_814 = cat(_T_610[20], _T_610[19]) @[lib.scala 430:14] + node _T_815 = cat(_T_610[22], _T_610[21]) @[lib.scala 430:14] + node _T_816 = cat(_T_815, _T_814) @[lib.scala 430:14] + node _T_817 = cat(_T_816, _T_813) @[lib.scala 430:14] + node _T_818 = cat(_T_610[24], _T_610[23]) @[lib.scala 430:14] + node _T_819 = cat(_T_610[26], _T_610[25]) @[lib.scala 430:14] + node _T_820 = cat(_T_819, _T_818) @[lib.scala 430:14] + node _T_821 = cat(_T_610[28], _T_610[27]) @[lib.scala 430:14] + node _T_822 = cat(_T_610[30], _T_610[29]) @[lib.scala 430:14] + node _T_823 = cat(_T_822, _T_821) @[lib.scala 430:14] + node _T_824 = cat(_T_823, _T_820) @[lib.scala 430:14] + node _T_825 = cat(_T_824, _T_817) @[lib.scala 430:14] + node _T_826 = cat(_T_825, _T_810) @[lib.scala 430:14] + node _T_827 = bits(twos_comp_in, 0, 0) @[lib.scala 430:24] + node twos_comp_out = cat(_T_826, _T_827) @[Cat.scala 29:58] + node _T_828 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 847:6] + node _T_829 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 847:17] + node _T_830 = and(_T_828, _T_829) @[exu_div_ctl.scala 847:15] + node _T_831 = bits(_T_830, 0, 0) @[exu_div_ctl.scala 847:36] + node _T_832 = bits(io.dividend_in, 31, 0) @[exu_div_ctl.scala 847:60] + node _T_833 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 848:54] + node _T_834 = cat(_T_833, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_835 = bits(ar_shifted, 31, 0) @[exu_div_ctl.scala 849:56] + node _T_836 = mux(_T_831, _T_832, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_837 = mux(a_shift, _T_834, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_838 = mux(shortq_enable_ff, _T_835, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_839 = or(_T_836, _T_837) @[Mux.scala 27:72] + node _T_840 = or(_T_839, _T_838) @[Mux.scala 27:72] wire a_in : UInt<32> @[Mux.scala 27:72] - a_in <= _T_822 @[Mux.scala 27:72] - node _T_823 = eq(b_twos_comp, UInt<1>("h00")) @[exu_div_ctl.scala 858:5] - node _T_824 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 858:78] - node _T_825 = and(io.signed_in, _T_824) @[exu_div_ctl.scala 858:63] - node _T_826 = bits(io.divisor_in, 31, 0) @[exu_div_ctl.scala 858:96] - node _T_827 = cat(_T_825, _T_826) @[Cat.scala 29:58] - node _T_828 = eq(divisor_sign_ff, UInt<1>("h00")) @[exu_div_ctl.scala 859:49] - node _T_829 = bits(twos_comp_out, 31, 0) @[exu_div_ctl.scala 859:79] - node _T_830 = cat(_T_828, _T_829) @[Cat.scala 29:58] - node _T_831 = mux(_T_823, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_832 = mux(b_twos_comp, _T_830, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_833 = or(_T_831, _T_832) @[Mux.scala 27:72] + a_in <= _T_840 @[Mux.scala 27:72] + node _T_841 = eq(b_twos_comp, UInt<1>("h00")) @[exu_div_ctl.scala 852:5] + node _T_842 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 852:78] + node _T_843 = and(io.signed_in, _T_842) @[exu_div_ctl.scala 852:63] + node _T_844 = bits(io.divisor_in, 31, 0) @[exu_div_ctl.scala 852:96] + node _T_845 = cat(_T_843, _T_844) @[Cat.scala 29:58] + node _T_846 = eq(divisor_sign_ff, UInt<1>("h00")) @[exu_div_ctl.scala 853:50] + node _T_847 = bits(twos_comp_out, 31, 0) @[exu_div_ctl.scala 853:80] + node _T_848 = cat(_T_846, _T_847) @[Cat.scala 29:58] + node _T_849 = mux(_T_841, _T_845, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_850 = mux(b_twos_comp, _T_848, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_851 = or(_T_849, _T_850) @[Mux.scala 27:72] wire b_in : UInt<33> @[Mux.scala 27:72] - b_in <= _T_833 @[Mux.scala 27:72] - node _T_834 = mux(UInt<1>("h01"), UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12] - node _T_835 = bits(r_ff, 28, 0) @[exu_div_ctl.scala 863:54] - node _T_836 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 863:65] - node _T_837 = cat(_T_835, _T_836) @[Cat.scala 29:58] - node _T_838 = bits(adder1_out, 32, 0) @[exu_div_ctl.scala 864:56] - node _T_839 = bits(adder2_out, 32, 0) @[exu_div_ctl.scala 865:56] - node _T_840 = bits(adder3_out, 32, 0) @[exu_div_ctl.scala 866:56] - node _T_841 = bits(adder4_out, 32, 0) @[exu_div_ctl.scala 867:56] - node _T_842 = bits(adder5_out, 32, 0) @[exu_div_ctl.scala 868:56] - node _T_843 = bits(adder6_out, 32, 0) @[exu_div_ctl.scala 869:56] - node _T_844 = bits(adder7_out, 32, 0) @[exu_div_ctl.scala 870:56] - node _T_845 = bits(adder8_out, 32, 0) @[exu_div_ctl.scala 871:56] - node _T_846 = bits(adder9_out, 32, 0) @[exu_div_ctl.scala 872:56] - node _T_847 = bits(adder10_out, 32, 0) @[exu_div_ctl.scala 873:57] - node _T_848 = bits(adder11_out, 32, 0) @[exu_div_ctl.scala 874:57] - node _T_849 = bits(adder12_out, 32, 0) @[exu_div_ctl.scala 875:57] - node _T_850 = bits(adder13_out, 32, 0) @[exu_div_ctl.scala 876:57] - node _T_851 = bits(adder14_out, 32, 0) @[exu_div_ctl.scala 877:57] - node _T_852 = bits(adder15_out, 32, 0) @[exu_div_ctl.scala 878:57] - node _T_853 = bits(ar_shifted, 64, 32) @[exu_div_ctl.scala 879:56] - node _T_854 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 880:58] - node _T_855 = cat(UInt<1>("h00"), _T_854) @[Cat.scala 29:58] - node _T_856 = mux(r_sign_sel, _T_834, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_857 = mux(r_adder_sel_0, _T_837, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_858 = mux(r_adder_sel_1, _T_838, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_859 = mux(r_adder_sel_2, _T_839, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_860 = mux(r_adder_sel_3, _T_840, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_861 = mux(r_adder_sel_4, _T_841, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_862 = mux(r_adder_sel_5, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_863 = mux(r_adder_sel_6, _T_843, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_864 = mux(r_adder_sel_7, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_865 = mux(r_adder_sel_8, _T_845, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_866 = mux(r_adder_sel_9, _T_846, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_867 = mux(r_adder_sel_10, _T_847, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_868 = mux(r_adder_sel_11, _T_848, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_869 = mux(r_adder_sel_12, _T_849, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_870 = mux(r_adder_sel_13, _T_850, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_871 = mux(r_adder_sel_14, _T_851, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_872 = mux(r_adder_sel_15, _T_852, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_873 = mux(shortq_enable_ff, _T_853, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_874 = mux(by_zero_case, _T_855, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_875 = or(_T_856, _T_857) @[Mux.scala 27:72] - node _T_876 = or(_T_875, _T_858) @[Mux.scala 27:72] - node _T_877 = or(_T_876, _T_859) @[Mux.scala 27:72] - node _T_878 = or(_T_877, _T_860) @[Mux.scala 27:72] - node _T_879 = or(_T_878, _T_861) @[Mux.scala 27:72] - node _T_880 = or(_T_879, _T_862) @[Mux.scala 27:72] - node _T_881 = or(_T_880, _T_863) @[Mux.scala 27:72] - node _T_882 = or(_T_881, _T_864) @[Mux.scala 27:72] - node _T_883 = or(_T_882, _T_865) @[Mux.scala 27:72] - node _T_884 = or(_T_883, _T_866) @[Mux.scala 27:72] - node _T_885 = or(_T_884, _T_867) @[Mux.scala 27:72] - node _T_886 = or(_T_885, _T_868) @[Mux.scala 27:72] - node _T_887 = or(_T_886, _T_869) @[Mux.scala 27:72] - node _T_888 = or(_T_887, _T_870) @[Mux.scala 27:72] - node _T_889 = or(_T_888, _T_871) @[Mux.scala 27:72] - node _T_890 = or(_T_889, _T_872) @[Mux.scala 27:72] - node _T_891 = or(_T_890, _T_873) @[Mux.scala 27:72] - node _T_892 = or(_T_891, _T_874) @[Mux.scala 27:72] + b_in <= _T_851 @[Mux.scala 27:72] + node _T_852 = mux(UInt<1>("h01"), UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12] + node _T_853 = bits(r_ff, 28, 0) @[exu_div_ctl.scala 857:54] + node _T_854 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 857:65] + node _T_855 = cat(_T_853, _T_854) @[Cat.scala 29:58] + node _T_856 = bits(adder1_out, 32, 0) @[exu_div_ctl.scala 858:56] + node _T_857 = bits(adder2_out, 32, 0) @[exu_div_ctl.scala 859:56] + node _T_858 = bits(adder3_out, 32, 0) @[exu_div_ctl.scala 860:56] + node _T_859 = bits(adder4_out, 32, 0) @[exu_div_ctl.scala 861:56] + node _T_860 = bits(adder5_out, 32, 0) @[exu_div_ctl.scala 862:56] + node _T_861 = bits(adder6_out, 32, 0) @[exu_div_ctl.scala 863:56] + node _T_862 = bits(adder7_out, 32, 0) @[exu_div_ctl.scala 864:56] + node _T_863 = bits(adder8_out, 32, 0) @[exu_div_ctl.scala 865:56] + node _T_864 = bits(adder9_out, 32, 0) @[exu_div_ctl.scala 866:56] + node _T_865 = bits(adder10_out, 32, 0) @[exu_div_ctl.scala 867:57] + node _T_866 = bits(adder11_out, 32, 0) @[exu_div_ctl.scala 868:57] + node _T_867 = bits(adder12_out, 32, 0) @[exu_div_ctl.scala 869:57] + node _T_868 = bits(adder13_out, 32, 0) @[exu_div_ctl.scala 870:57] + node _T_869 = bits(adder14_out, 32, 0) @[exu_div_ctl.scala 871:57] + node _T_870 = bits(adder15_out, 32, 0) @[exu_div_ctl.scala 872:57] + node _T_871 = bits(ar_shifted, 64, 32) @[exu_div_ctl.scala 873:56] + node _T_872 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 874:58] + node _T_873 = cat(UInt<1>("h00"), _T_872) @[Cat.scala 29:58] + node _T_874 = mux(r_sign_sel, _T_852, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_875 = mux(r_adder_sel_0, _T_855, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_876 = mux(r_adder_sel_1, _T_856, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_877 = mux(r_adder_sel_2, _T_857, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_878 = mux(r_adder_sel_3, _T_858, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_879 = mux(r_adder_sel_4, _T_859, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_880 = mux(r_adder_sel_5, _T_860, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_881 = mux(r_adder_sel_6, _T_861, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_882 = mux(r_adder_sel_7, _T_862, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_883 = mux(r_adder_sel_8, _T_863, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_884 = mux(r_adder_sel_9, _T_864, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_885 = mux(r_adder_sel_10, _T_865, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_886 = mux(r_adder_sel_11, _T_866, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_887 = mux(r_adder_sel_12, _T_867, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_888 = mux(r_adder_sel_13, _T_868, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_889 = mux(r_adder_sel_14, _T_869, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_890 = mux(r_adder_sel_15, _T_870, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_891 = mux(shortq_enable_ff, _T_871, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_892 = mux(by_zero_case, _T_873, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_893 = or(_T_874, _T_875) @[Mux.scala 27:72] + node _T_894 = or(_T_893, _T_876) @[Mux.scala 27:72] + node _T_895 = or(_T_894, _T_877) @[Mux.scala 27:72] + node _T_896 = or(_T_895, _T_878) @[Mux.scala 27:72] + node _T_897 = or(_T_896, _T_879) @[Mux.scala 27:72] + node _T_898 = or(_T_897, _T_880) @[Mux.scala 27:72] + node _T_899 = or(_T_898, _T_881) @[Mux.scala 27:72] + node _T_900 = or(_T_899, _T_882) @[Mux.scala 27:72] + node _T_901 = or(_T_900, _T_883) @[Mux.scala 27:72] + node _T_902 = or(_T_901, _T_884) @[Mux.scala 27:72] + node _T_903 = or(_T_902, _T_885) @[Mux.scala 27:72] + node _T_904 = or(_T_903, _T_886) @[Mux.scala 27:72] + node _T_905 = or(_T_904, _T_887) @[Mux.scala 27:72] + node _T_906 = or(_T_905, _T_888) @[Mux.scala 27:72] + node _T_907 = or(_T_906, _T_889) @[Mux.scala 27:72] + node _T_908 = or(_T_907, _T_890) @[Mux.scala 27:72] + node _T_909 = or(_T_908, _T_891) @[Mux.scala 27:72] + node _T_910 = or(_T_909, _T_892) @[Mux.scala 27:72] wire r_in : UInt<33> @[Mux.scala 27:72] - r_in <= _T_892 @[Mux.scala 27:72] - node _T_893 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 883:5] - node _T_894 = bits(q_ff, 27, 0) @[exu_div_ctl.scala 883:55] - node _T_895 = cat(_T_894, quotient_new) @[Cat.scala 29:58] - node _T_896 = cat(UInt<28>("h00"), smallnum) @[Cat.scala 29:58] - node _T_897 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_898 = mux(_T_893, _T_895, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_899 = mux(smallnum_case, _T_896, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_900 = mux(by_zero_case, _T_897, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_901 = or(_T_898, _T_899) @[Mux.scala 27:72] - node _T_902 = or(_T_901, _T_900) @[Mux.scala 27:72] + r_in <= _T_910 @[Mux.scala 27:72] + node _T_911 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 877:5] + node _T_912 = bits(q_ff, 27, 0) @[exu_div_ctl.scala 877:54] + node _T_913 = cat(_T_912, quotient_new) @[Cat.scala 29:58] + node _T_914 = cat(UInt<28>("h00"), smallnum) @[Cat.scala 29:58] + node _T_915 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_916 = mux(_T_911, _T_913, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_917 = mux(smallnum_case, _T_914, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_918 = mux(by_zero_case, _T_915, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_919 = or(_T_916, _T_917) @[Mux.scala 27:72] + node _T_920 = or(_T_919, _T_918) @[Mux.scala 27:72] wire q_in : UInt<32> @[Mux.scala 27:72] - q_in <= _T_902 @[Mux.scala 27:72] - node _T_903 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 887:31] - node _T_904 = and(finish_ff, _T_903) @[exu_div_ctl.scala 887:29] - io.valid_out <= _T_904 @[exu_div_ctl.scala 887:16] - node _T_905 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 889:6] - node _T_906 = eq(twos_comp_q_sel, UInt<1>("h00")) @[exu_div_ctl.scala 889:16] - node _T_907 = and(_T_905, _T_906) @[exu_div_ctl.scala 889:14] - node _T_908 = bits(_T_907, 0, 0) @[exu_div_ctl.scala 889:40] - node _T_909 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 890:48] - node _T_910 = mux(_T_908, q_ff, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_911 = mux(rem_ff, _T_909, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_912 = mux(twos_comp_q_sel, twos_comp_out, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_913 = or(_T_910, _T_911) @[Mux.scala 27:72] - node _T_914 = or(_T_913, _T_912) @[Mux.scala 27:72] - wire _T_915 : UInt<32> @[Mux.scala 27:72] - _T_915 <= _T_914 @[Mux.scala 27:72] - io.data_out <= _T_915 @[exu_div_ctl.scala 888:15] - node _T_916 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_917 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_918 = eq(_T_917, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_919 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_921 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_922 = eq(_T_921, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_923 = and(_T_918, _T_920) @[exu_div_ctl.scala 895:95] - node _T_924 = and(_T_923, _T_922) @[exu_div_ctl.scala 895:95] - node _T_925 = and(_T_916, _T_924) @[exu_div_ctl.scala 896:11] - node _T_926 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_927 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_928 = eq(_T_927, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_929 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_930 = eq(_T_929, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_931 = and(_T_928, _T_930) @[exu_div_ctl.scala 895:95] - node _T_932 = and(_T_926, _T_931) @[exu_div_ctl.scala 896:11] - node _T_933 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 901:38] - node _T_934 = eq(_T_933, UInt<1>("h00")) @[exu_div_ctl.scala 901:33] - node _T_935 = and(_T_932, _T_934) @[exu_div_ctl.scala 901:31] - node _T_936 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_937 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_938 = eq(_T_937, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_939 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_940 = eq(_T_939, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_941 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_942 = eq(_T_941, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_943 = and(_T_938, _T_940) @[exu_div_ctl.scala 895:95] - node _T_944 = and(_T_943, _T_942) @[exu_div_ctl.scala 895:95] - node _T_945 = and(_T_936, _T_944) @[exu_div_ctl.scala 896:11] - node _T_946 = or(_T_935, _T_945) @[exu_div_ctl.scala 901:42] - node _T_947 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_948 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_949 = and(_T_947, _T_948) @[exu_div_ctl.scala 894:95] - node _T_950 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_951 = eq(_T_950, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_952 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_953 = eq(_T_952, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_954 = and(_T_951, _T_953) @[exu_div_ctl.scala 895:95] - node _T_955 = and(_T_949, _T_954) @[exu_div_ctl.scala 896:11] - node _T_956 = or(_T_946, _T_955) @[exu_div_ctl.scala 901:75] - node _T_957 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_958 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_959 = eq(_T_958, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_960 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_961 = eq(_T_960, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_962 = and(_T_959, _T_961) @[exu_div_ctl.scala 895:95] - node _T_963 = and(_T_957, _T_962) @[exu_div_ctl.scala 896:11] - node _T_964 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 903:38] - node _T_965 = eq(_T_964, UInt<1>("h00")) @[exu_div_ctl.scala 903:33] - node _T_966 = and(_T_963, _T_965) @[exu_div_ctl.scala 903:31] - node _T_967 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_968 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_969 = eq(_T_968, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_970 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_971 = eq(_T_970, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_972 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_973 = eq(_T_972, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_974 = and(_T_969, _T_971) @[exu_div_ctl.scala 895:95] - node _T_975 = and(_T_974, _T_973) @[exu_div_ctl.scala 895:95] - node _T_976 = and(_T_967, _T_975) @[exu_div_ctl.scala 896:11] - node _T_977 = or(_T_966, _T_976) @[exu_div_ctl.scala 903:42] - node _T_978 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_979 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_981 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_982 = eq(_T_981, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_983 = and(_T_980, _T_982) @[exu_div_ctl.scala 895:95] - node _T_984 = and(_T_978, _T_983) @[exu_div_ctl.scala 896:11] - node _T_985 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 903:113] - node _T_986 = eq(_T_985, UInt<1>("h00")) @[exu_div_ctl.scala 903:108] - node _T_987 = and(_T_984, _T_986) @[exu_div_ctl.scala 903:106] - node _T_988 = or(_T_977, _T_987) @[exu_div_ctl.scala 903:78] - node _T_989 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_990 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:75] - node _T_991 = eq(_T_990, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_992 = and(_T_989, _T_991) @[exu_div_ctl.scala 894:95] - node _T_993 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_994 = eq(_T_993, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_995 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_996 = eq(_T_995, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_997 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:58] - node _T_998 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 895:58] - node _T_999 = and(_T_994, _T_996) @[exu_div_ctl.scala 895:95] - node _T_1000 = and(_T_999, _T_997) @[exu_div_ctl.scala 895:95] - node _T_1001 = and(_T_1000, _T_998) @[exu_div_ctl.scala 895:95] - node _T_1002 = and(_T_992, _T_1001) @[exu_div_ctl.scala 896:11] - node _T_1003 = or(_T_988, _T_1002) @[exu_div_ctl.scala 903:117] - node _T_1004 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:75] - node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1006 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1007 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1008 = and(_T_1005, _T_1006) @[exu_div_ctl.scala 894:95] - node _T_1009 = and(_T_1008, _T_1007) @[exu_div_ctl.scala 894:95] - node _T_1010 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1011 = eq(_T_1010, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1012 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1013 = eq(_T_1012, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1014 = and(_T_1011, _T_1013) @[exu_div_ctl.scala 895:95] - node _T_1015 = and(_T_1009, _T_1014) @[exu_div_ctl.scala 896:11] - node _T_1016 = or(_T_1003, _T_1015) @[exu_div_ctl.scala 904:44] - node _T_1017 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1018 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1019 = and(_T_1017, _T_1018) @[exu_div_ctl.scala 894:95] - node _T_1020 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1021 = eq(_T_1020, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1022 = and(_T_1019, _T_1021) @[exu_div_ctl.scala 896:11] - node _T_1023 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 904:114] - node _T_1024 = eq(_T_1023, UInt<1>("h00")) @[exu_div_ctl.scala 904:109] - node _T_1025 = and(_T_1022, _T_1024) @[exu_div_ctl.scala 904:107] - node _T_1026 = or(_T_1016, _T_1025) @[exu_div_ctl.scala 904:80] - node _T_1027 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1028 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1029 = and(_T_1027, _T_1028) @[exu_div_ctl.scala 894:95] - node _T_1030 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1032 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:58] - node _T_1033 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1034 = eq(_T_1033, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1035 = and(_T_1031, _T_1032) @[exu_div_ctl.scala 895:95] - node _T_1036 = and(_T_1035, _T_1034) @[exu_div_ctl.scala 895:95] - node _T_1037 = and(_T_1029, _T_1036) @[exu_div_ctl.scala 896:11] - node _T_1038 = or(_T_1026, _T_1037) @[exu_div_ctl.scala 904:119] - node _T_1039 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1040 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1041 = and(_T_1039, _T_1040) @[exu_div_ctl.scala 894:95] - node _T_1042 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1043 = eq(_T_1042, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1044 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1045 = eq(_T_1044, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1046 = and(_T_1043, _T_1045) @[exu_div_ctl.scala 895:95] - node _T_1047 = and(_T_1041, _T_1046) @[exu_div_ctl.scala 896:11] - node _T_1048 = or(_T_1038, _T_1047) @[exu_div_ctl.scala 905:44] - node _T_1049 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1050 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1051 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1052 = and(_T_1049, _T_1050) @[exu_div_ctl.scala 894:95] - node _T_1053 = and(_T_1052, _T_1051) @[exu_div_ctl.scala 894:95] - node _T_1054 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1055 = eq(_T_1054, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1056 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:58] - node _T_1057 = and(_T_1055, _T_1056) @[exu_div_ctl.scala 895:95] - node _T_1058 = and(_T_1053, _T_1057) @[exu_div_ctl.scala 896:11] - node _T_1059 = or(_T_1048, _T_1058) @[exu_div_ctl.scala 905:79] - node _T_1060 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1061 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1062 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1063 = and(_T_1060, _T_1061) @[exu_div_ctl.scala 894:95] - node _T_1064 = and(_T_1063, _T_1062) @[exu_div_ctl.scala 894:95] - node _T_1065 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1066 = eq(_T_1065, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1067 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1069 = and(_T_1066, _T_1068) @[exu_div_ctl.scala 895:95] - node _T_1070 = and(_T_1064, _T_1069) @[exu_div_ctl.scala 896:11] - node _T_1071 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1072 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:75] - node _T_1073 = eq(_T_1072, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1074 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1075 = and(_T_1071, _T_1073) @[exu_div_ctl.scala 894:95] - node _T_1076 = and(_T_1075, _T_1074) @[exu_div_ctl.scala 894:95] - node _T_1077 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1078 = eq(_T_1077, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1079 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:58] - node _T_1080 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 895:58] - node _T_1081 = and(_T_1078, _T_1079) @[exu_div_ctl.scala 895:95] - node _T_1082 = and(_T_1081, _T_1080) @[exu_div_ctl.scala 895:95] - node _T_1083 = and(_T_1076, _T_1082) @[exu_div_ctl.scala 896:11] - node _T_1084 = or(_T_1070, _T_1083) @[exu_div_ctl.scala 907:45] - node _T_1085 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1086 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1087 = eq(_T_1086, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1088 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1089 = eq(_T_1088, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1090 = and(_T_1087, _T_1089) @[exu_div_ctl.scala 895:95] - node _T_1091 = and(_T_1085, _T_1090) @[exu_div_ctl.scala 896:11] - node _T_1092 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 907:121] - node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[exu_div_ctl.scala 907:116] - node _T_1094 = and(_T_1091, _T_1093) @[exu_div_ctl.scala 907:114] - node _T_1095 = or(_T_1084, _T_1094) @[exu_div_ctl.scala 907:86] - node _T_1096 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1097 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1098 = eq(_T_1097, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1099 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1100 = eq(_T_1099, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1101 = and(_T_1098, _T_1100) @[exu_div_ctl.scala 895:95] - node _T_1102 = and(_T_1096, _T_1101) @[exu_div_ctl.scala 896:11] - node _T_1103 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 908:40] - node _T_1104 = eq(_T_1103, UInt<1>("h00")) @[exu_div_ctl.scala 908:35] - node _T_1105 = and(_T_1102, _T_1104) @[exu_div_ctl.scala 908:33] - node _T_1106 = or(_T_1095, _T_1105) @[exu_div_ctl.scala 907:129] - node _T_1107 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1108 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1109 = eq(_T_1108, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1110 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1111 = eq(_T_1110, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1112 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1113 = eq(_T_1112, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1114 = and(_T_1109, _T_1111) @[exu_div_ctl.scala 895:95] - node _T_1115 = and(_T_1114, _T_1113) @[exu_div_ctl.scala 895:95] - node _T_1116 = and(_T_1107, _T_1115) @[exu_div_ctl.scala 896:11] - node _T_1117 = or(_T_1106, _T_1116) @[exu_div_ctl.scala 908:47] - node _T_1118 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:75] - node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1120 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1121 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:75] - node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1123 = and(_T_1119, _T_1120) @[exu_div_ctl.scala 894:95] - node _T_1124 = and(_T_1123, _T_1122) @[exu_div_ctl.scala 894:95] - node _T_1125 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1126 = eq(_T_1125, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1127 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1129 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:58] - node _T_1130 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 895:58] - node _T_1131 = and(_T_1126, _T_1128) @[exu_div_ctl.scala 895:95] - node _T_1132 = and(_T_1131, _T_1129) @[exu_div_ctl.scala 895:95] - node _T_1133 = and(_T_1132, _T_1130) @[exu_div_ctl.scala 895:95] - node _T_1134 = and(_T_1124, _T_1133) @[exu_div_ctl.scala 896:11] - node _T_1135 = or(_T_1117, _T_1134) @[exu_div_ctl.scala 908:88] - node _T_1136 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:75] - node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1138 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1139 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1140 = and(_T_1137, _T_1138) @[exu_div_ctl.scala 894:95] - node _T_1141 = and(_T_1140, _T_1139) @[exu_div_ctl.scala 894:95] - node _T_1142 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1144 = and(_T_1141, _T_1143) @[exu_div_ctl.scala 896:11] - node _T_1145 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 909:43] - node _T_1146 = eq(_T_1145, UInt<1>("h00")) @[exu_div_ctl.scala 909:38] - node _T_1147 = and(_T_1144, _T_1146) @[exu_div_ctl.scala 909:36] - node _T_1148 = or(_T_1135, _T_1147) @[exu_div_ctl.scala 908:131] - node _T_1149 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1150 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1152 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1153 = eq(_T_1152, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1154 = and(_T_1151, _T_1153) @[exu_div_ctl.scala 895:95] - node _T_1155 = and(_T_1149, _T_1154) @[exu_div_ctl.scala 896:11] - node _T_1156 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 909:83] - node _T_1157 = eq(_T_1156, UInt<1>("h00")) @[exu_div_ctl.scala 909:78] - node _T_1158 = and(_T_1155, _T_1157) @[exu_div_ctl.scala 909:76] - node _T_1159 = or(_T_1148, _T_1158) @[exu_div_ctl.scala 909:47] - node _T_1160 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1161 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:75] - node _T_1162 = eq(_T_1161, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1163 = and(_T_1160, _T_1162) @[exu_div_ctl.scala 894:95] - node _T_1164 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1166 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:58] - node _T_1167 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:58] - node _T_1168 = and(_T_1165, _T_1166) @[exu_div_ctl.scala 895:95] - node _T_1169 = and(_T_1168, _T_1167) @[exu_div_ctl.scala 895:95] - node _T_1170 = and(_T_1163, _T_1169) @[exu_div_ctl.scala 896:11] - node _T_1171 = or(_T_1159, _T_1170) @[exu_div_ctl.scala 909:88] - node _T_1172 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:75] - node _T_1173 = eq(_T_1172, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1174 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1175 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1176 = and(_T_1173, _T_1174) @[exu_div_ctl.scala 894:95] - node _T_1177 = and(_T_1176, _T_1175) @[exu_div_ctl.scala 894:95] - node _T_1178 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1179 = eq(_T_1178, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1180 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:58] - node _T_1181 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1183 = and(_T_1179, _T_1180) @[exu_div_ctl.scala 895:95] - node _T_1184 = and(_T_1183, _T_1182) @[exu_div_ctl.scala 895:95] - node _T_1185 = and(_T_1177, _T_1184) @[exu_div_ctl.scala 896:11] - node _T_1186 = or(_T_1171, _T_1185) @[exu_div_ctl.scala 909:131] - node _T_1187 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:75] - node _T_1188 = eq(_T_1187, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1189 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1190 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1191 = and(_T_1188, _T_1189) @[exu_div_ctl.scala 894:95] - node _T_1192 = and(_T_1191, _T_1190) @[exu_div_ctl.scala 894:95] - node _T_1193 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1195 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1196 = eq(_T_1195, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1197 = and(_T_1194, _T_1196) @[exu_div_ctl.scala 895:95] - node _T_1198 = and(_T_1192, _T_1197) @[exu_div_ctl.scala 896:11] - node _T_1199 = or(_T_1186, _T_1198) @[exu_div_ctl.scala 910:47] - node _T_1200 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1201 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:75] - node _T_1202 = eq(_T_1201, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1203 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:75] - node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1205 = and(_T_1200, _T_1202) @[exu_div_ctl.scala 894:95] - node _T_1206 = and(_T_1205, _T_1204) @[exu_div_ctl.scala 894:95] - node _T_1207 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1208 = eq(_T_1207, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1209 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:58] - node _T_1210 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 895:58] - node _T_1211 = and(_T_1208, _T_1209) @[exu_div_ctl.scala 895:95] - node _T_1212 = and(_T_1211, _T_1210) @[exu_div_ctl.scala 895:95] - node _T_1213 = and(_T_1206, _T_1212) @[exu_div_ctl.scala 896:11] - node _T_1214 = or(_T_1199, _T_1213) @[exu_div_ctl.scala 910:88] - node _T_1215 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:75] - node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1217 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1218 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1219 = and(_T_1216, _T_1217) @[exu_div_ctl.scala 894:95] - node _T_1220 = and(_T_1219, _T_1218) @[exu_div_ctl.scala 894:95] - node _T_1221 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1222 = eq(_T_1221, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1223 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1224 = eq(_T_1223, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1225 = and(_T_1222, _T_1224) @[exu_div_ctl.scala 895:95] - node _T_1226 = and(_T_1220, _T_1225) @[exu_div_ctl.scala 896:11] - node _T_1227 = or(_T_1214, _T_1226) @[exu_div_ctl.scala 910:131] - node _T_1228 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1229 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1230 = and(_T_1228, _T_1229) @[exu_div_ctl.scala 894:95] - node _T_1231 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1233 = and(_T_1230, _T_1232) @[exu_div_ctl.scala 896:11] - node _T_1234 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 911:82] - node _T_1235 = eq(_T_1234, UInt<1>("h00")) @[exu_div_ctl.scala 911:77] - node _T_1236 = and(_T_1233, _T_1235) @[exu_div_ctl.scala 911:75] - node _T_1237 = or(_T_1227, _T_1236) @[exu_div_ctl.scala 911:47] - node _T_1238 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:75] - node _T_1239 = eq(_T_1238, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1240 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1241 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1242 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1243 = and(_T_1239, _T_1240) @[exu_div_ctl.scala 894:95] - node _T_1244 = and(_T_1243, _T_1241) @[exu_div_ctl.scala 894:95] - node _T_1245 = and(_T_1244, _T_1242) @[exu_div_ctl.scala 894:95] - node _T_1246 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1247 = eq(_T_1246, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1248 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:58] - node _T_1249 = and(_T_1247, _T_1248) @[exu_div_ctl.scala 895:95] - node _T_1250 = and(_T_1245, _T_1249) @[exu_div_ctl.scala 896:11] - node _T_1251 = or(_T_1237, _T_1250) @[exu_div_ctl.scala 911:88] - node _T_1252 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1253 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1254 = and(_T_1252, _T_1253) @[exu_div_ctl.scala 894:95] - node _T_1255 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:58] - node _T_1256 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1258 = and(_T_1255, _T_1257) @[exu_div_ctl.scala 895:95] - node _T_1259 = and(_T_1254, _T_1258) @[exu_div_ctl.scala 896:11] - node _T_1260 = or(_T_1251, _T_1259) @[exu_div_ctl.scala 911:131] - node _T_1261 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1262 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1263 = and(_T_1261, _T_1262) @[exu_div_ctl.scala 894:95] - node _T_1264 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:58] - node _T_1265 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1266 = eq(_T_1265, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1267 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1269 = and(_T_1264, _T_1266) @[exu_div_ctl.scala 895:95] - node _T_1270 = and(_T_1269, _T_1268) @[exu_div_ctl.scala 895:95] - node _T_1271 = and(_T_1263, _T_1270) @[exu_div_ctl.scala 896:11] - node _T_1272 = or(_T_1260, _T_1271) @[exu_div_ctl.scala 912:47] - node _T_1273 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1274 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1275 = and(_T_1273, _T_1274) @[exu_div_ctl.scala 894:95] - node _T_1276 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1277 = eq(_T_1276, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1278 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1279 = eq(_T_1278, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1280 = and(_T_1277, _T_1279) @[exu_div_ctl.scala 895:95] - node _T_1281 = and(_T_1275, _T_1280) @[exu_div_ctl.scala 896:11] - node _T_1282 = or(_T_1272, _T_1281) @[exu_div_ctl.scala 912:88] - node _T_1283 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1284 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:75] - node _T_1285 = eq(_T_1284, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1286 = and(_T_1283, _T_1285) @[exu_div_ctl.scala 894:95] - node _T_1287 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1288 = eq(_T_1287, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1289 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:58] - node _T_1290 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:58] - node _T_1291 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 895:58] - node _T_1292 = and(_T_1288, _T_1289) @[exu_div_ctl.scala 895:95] - node _T_1293 = and(_T_1292, _T_1290) @[exu_div_ctl.scala 895:95] - node _T_1294 = and(_T_1293, _T_1291) @[exu_div_ctl.scala 895:95] - node _T_1295 = and(_T_1286, _T_1294) @[exu_div_ctl.scala 896:11] - node _T_1296 = or(_T_1282, _T_1295) @[exu_div_ctl.scala 912:131] - node _T_1297 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1298 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1299 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1300 = and(_T_1297, _T_1298) @[exu_div_ctl.scala 894:95] - node _T_1301 = and(_T_1300, _T_1299) @[exu_div_ctl.scala 894:95] - node _T_1302 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:58] - node _T_1303 = and(_T_1301, _T_1302) @[exu_div_ctl.scala 896:11] - node _T_1304 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 913:84] - node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[exu_div_ctl.scala 913:79] - node _T_1306 = and(_T_1303, _T_1305) @[exu_div_ctl.scala 913:77] - node _T_1307 = or(_T_1296, _T_1306) @[exu_div_ctl.scala 913:47] - node _T_1308 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1309 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1310 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1311 = and(_T_1308, _T_1309) @[exu_div_ctl.scala 894:95] - node _T_1312 = and(_T_1311, _T_1310) @[exu_div_ctl.scala 894:95] - node _T_1313 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:58] - node _T_1314 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1315 = eq(_T_1314, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1316 = and(_T_1313, _T_1315) @[exu_div_ctl.scala 895:95] - node _T_1317 = and(_T_1312, _T_1316) @[exu_div_ctl.scala 896:11] - node _T_1318 = or(_T_1307, _T_1317) @[exu_div_ctl.scala 913:88] - node _T_1319 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1320 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1321 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1322 = and(_T_1319, _T_1320) @[exu_div_ctl.scala 894:95] - node _T_1323 = and(_T_1322, _T_1321) @[exu_div_ctl.scala 894:95] - node _T_1324 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:58] - node _T_1325 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:75] - node _T_1326 = eq(_T_1325, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1327 = and(_T_1324, _T_1326) @[exu_div_ctl.scala 895:95] - node _T_1328 = and(_T_1323, _T_1327) @[exu_div_ctl.scala 896:11] - node _T_1329 = or(_T_1318, _T_1328) @[exu_div_ctl.scala 913:131] - node _T_1330 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1331 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:75] - node _T_1332 = eq(_T_1331, UInt<1>("h00")) @[exu_div_ctl.scala 894:70] - node _T_1333 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1334 = and(_T_1330, _T_1332) @[exu_div_ctl.scala 894:95] - node _T_1335 = and(_T_1334, _T_1333) @[exu_div_ctl.scala 894:95] - node _T_1336 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:75] - node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1338 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 895:58] - node _T_1339 = and(_T_1337, _T_1338) @[exu_div_ctl.scala 895:95] - node _T_1340 = and(_T_1335, _T_1339) @[exu_div_ctl.scala 896:11] - node _T_1341 = or(_T_1329, _T_1340) @[exu_div_ctl.scala 914:47] - node _T_1342 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1343 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1344 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1345 = and(_T_1342, _T_1343) @[exu_div_ctl.scala 894:95] - node _T_1346 = and(_T_1345, _T_1344) @[exu_div_ctl.scala 894:95] - node _T_1347 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1349 = and(_T_1346, _T_1348) @[exu_div_ctl.scala 896:11] - node _T_1350 = or(_T_1341, _T_1349) @[exu_div_ctl.scala 914:88] - node _T_1351 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1352 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 894:58] - node _T_1353 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1354 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 894:58] - node _T_1355 = and(_T_1351, _T_1352) @[exu_div_ctl.scala 894:95] - node _T_1356 = and(_T_1355, _T_1353) @[exu_div_ctl.scala 894:95] - node _T_1357 = and(_T_1356, _T_1354) @[exu_div_ctl.scala 894:95] - node _T_1358 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 895:58] - node _T_1359 = and(_T_1357, _T_1358) @[exu_div_ctl.scala 896:11] - node _T_1360 = or(_T_1350, _T_1359) @[exu_div_ctl.scala 914:131] - node _T_1361 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 894:58] - node _T_1362 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 894:58] - node _T_1363 = and(_T_1361, _T_1362) @[exu_div_ctl.scala 894:95] - node _T_1364 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 895:75] - node _T_1365 = eq(_T_1364, UInt<1>("h00")) @[exu_div_ctl.scala 895:70] - node _T_1366 = and(_T_1363, _T_1365) @[exu_div_ctl.scala 896:11] - node _T_1367 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 915:81] - node _T_1368 = eq(_T_1367, UInt<1>("h00")) @[exu_div_ctl.scala 915:76] - node _T_1369 = and(_T_1366, _T_1368) @[exu_div_ctl.scala 915:74] - node _T_1370 = or(_T_1360, _T_1369) @[exu_div_ctl.scala 915:47] - node _T_1371 = cat(_T_1059, _T_1370) @[Cat.scala 29:58] - node _T_1372 = cat(_T_925, _T_956) @[Cat.scala 29:58] - node _T_1373 = cat(_T_1372, _T_1371) @[Cat.scala 29:58] - smallnum <= _T_1373 @[exu_div_ctl.scala 898:12] - node _T_1374 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 918:50] - node shortq_dividend = cat(dividend_sign_ff, _T_1374) @[Cat.scala 29:58] - inst a_enc of exu_div_cls @[exu_div_ctl.scala 919:21] + q_in <= _T_920 @[Mux.scala 27:72] + node _T_921 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 881:31] + node _T_922 = and(finish_ff, _T_921) @[exu_div_ctl.scala 881:29] + io.valid_out <= _T_922 @[exu_div_ctl.scala 881:16] + node _T_923 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 883:6] + node _T_924 = eq(twos_comp_q_sel, UInt<1>("h00")) @[exu_div_ctl.scala 883:16] + node _T_925 = and(_T_923, _T_924) @[exu_div_ctl.scala 883:14] + node _T_926 = bits(_T_925, 0, 0) @[exu_div_ctl.scala 883:40] + node _T_927 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 884:50] + node _T_928 = mux(_T_926, q_ff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_929 = mux(rem_ff, _T_927, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_930 = mux(twos_comp_q_sel, twos_comp_out, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_931 = or(_T_928, _T_929) @[Mux.scala 27:72] + node _T_932 = or(_T_931, _T_930) @[Mux.scala 27:72] + wire _T_933 : UInt<32> @[Mux.scala 27:72] + _T_933 <= _T_932 @[Mux.scala 27:72] + io.data_out <= _T_933 @[exu_div_ctl.scala 882:15] + node _T_934 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_935 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_936 = eq(_T_935, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_937 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_938 = eq(_T_937, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_939 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_940 = eq(_T_939, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_941 = and(_T_936, _T_938) @[exu_div_ctl.scala 889:95] + node _T_942 = and(_T_941, _T_940) @[exu_div_ctl.scala 889:95] + node _T_943 = and(_T_934, _T_942) @[exu_div_ctl.scala 890:11] + node _T_944 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_945 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_946 = eq(_T_945, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_947 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_948 = eq(_T_947, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_949 = and(_T_946, _T_948) @[exu_div_ctl.scala 889:95] + node _T_950 = and(_T_944, _T_949) @[exu_div_ctl.scala 890:11] + node _T_951 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 895:38] + node _T_952 = eq(_T_951, UInt<1>("h00")) @[exu_div_ctl.scala 895:33] + node _T_953 = and(_T_950, _T_952) @[exu_div_ctl.scala 895:31] + node _T_954 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_955 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_956 = eq(_T_955, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_957 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_959 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_960 = eq(_T_959, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_961 = and(_T_956, _T_958) @[exu_div_ctl.scala 889:95] + node _T_962 = and(_T_961, _T_960) @[exu_div_ctl.scala 889:95] + node _T_963 = and(_T_954, _T_962) @[exu_div_ctl.scala 890:11] + node _T_964 = or(_T_953, _T_963) @[exu_div_ctl.scala 895:42] + node _T_965 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_966 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_967 = and(_T_965, _T_966) @[exu_div_ctl.scala 888:95] + node _T_968 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_969 = eq(_T_968, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_970 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_972 = and(_T_969, _T_971) @[exu_div_ctl.scala 889:95] + node _T_973 = and(_T_967, _T_972) @[exu_div_ctl.scala 890:11] + node _T_974 = or(_T_964, _T_973) @[exu_div_ctl.scala 895:75] + node _T_975 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_976 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_977 = eq(_T_976, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_978 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_979 = eq(_T_978, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_980 = and(_T_977, _T_979) @[exu_div_ctl.scala 889:95] + node _T_981 = and(_T_975, _T_980) @[exu_div_ctl.scala 890:11] + node _T_982 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 897:38] + node _T_983 = eq(_T_982, UInt<1>("h00")) @[exu_div_ctl.scala 897:33] + node _T_984 = and(_T_981, _T_983) @[exu_div_ctl.scala 897:31] + node _T_985 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_986 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_987 = eq(_T_986, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_988 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_989 = eq(_T_988, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_990 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_991 = eq(_T_990, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_992 = and(_T_987, _T_989) @[exu_div_ctl.scala 889:95] + node _T_993 = and(_T_992, _T_991) @[exu_div_ctl.scala 889:95] + node _T_994 = and(_T_985, _T_993) @[exu_div_ctl.scala 890:11] + node _T_995 = or(_T_984, _T_994) @[exu_div_ctl.scala 897:42] + node _T_996 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_997 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_998 = eq(_T_997, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_999 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1001 = and(_T_998, _T_1000) @[exu_div_ctl.scala 889:95] + node _T_1002 = and(_T_996, _T_1001) @[exu_div_ctl.scala 890:11] + node _T_1003 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 897:113] + node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[exu_div_ctl.scala 897:108] + node _T_1005 = and(_T_1002, _T_1004) @[exu_div_ctl.scala 897:106] + node _T_1006 = or(_T_995, _T_1005) @[exu_div_ctl.scala 897:78] + node _T_1007 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1008 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:75] + node _T_1009 = eq(_T_1008, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1010 = and(_T_1007, _T_1009) @[exu_div_ctl.scala 888:95] + node _T_1011 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1012 = eq(_T_1011, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1013 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1015 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:58] + node _T_1016 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 889:58] + node _T_1017 = and(_T_1012, _T_1014) @[exu_div_ctl.scala 889:95] + node _T_1018 = and(_T_1017, _T_1015) @[exu_div_ctl.scala 889:95] + node _T_1019 = and(_T_1018, _T_1016) @[exu_div_ctl.scala 889:95] + node _T_1020 = and(_T_1010, _T_1019) @[exu_div_ctl.scala 890:11] + node _T_1021 = or(_T_1006, _T_1020) @[exu_div_ctl.scala 897:117] + node _T_1022 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:75] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1024 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1025 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1026 = and(_T_1023, _T_1024) @[exu_div_ctl.scala 888:95] + node _T_1027 = and(_T_1026, _T_1025) @[exu_div_ctl.scala 888:95] + node _T_1028 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1030 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1032 = and(_T_1029, _T_1031) @[exu_div_ctl.scala 889:95] + node _T_1033 = and(_T_1027, _T_1032) @[exu_div_ctl.scala 890:11] + node _T_1034 = or(_T_1021, _T_1033) @[exu_div_ctl.scala 898:44] + node _T_1035 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1036 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1037 = and(_T_1035, _T_1036) @[exu_div_ctl.scala 888:95] + node _T_1038 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1039 = eq(_T_1038, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1040 = and(_T_1037, _T_1039) @[exu_div_ctl.scala 890:11] + node _T_1041 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 898:114] + node _T_1042 = eq(_T_1041, UInt<1>("h00")) @[exu_div_ctl.scala 898:109] + node _T_1043 = and(_T_1040, _T_1042) @[exu_div_ctl.scala 898:107] + node _T_1044 = or(_T_1034, _T_1043) @[exu_div_ctl.scala 898:80] + node _T_1045 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1046 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1047 = and(_T_1045, _T_1046) @[exu_div_ctl.scala 888:95] + node _T_1048 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1049 = eq(_T_1048, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1050 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:58] + node _T_1051 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1053 = and(_T_1049, _T_1050) @[exu_div_ctl.scala 889:95] + node _T_1054 = and(_T_1053, _T_1052) @[exu_div_ctl.scala 889:95] + node _T_1055 = and(_T_1047, _T_1054) @[exu_div_ctl.scala 890:11] + node _T_1056 = or(_T_1044, _T_1055) @[exu_div_ctl.scala 898:119] + node _T_1057 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1058 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1059 = and(_T_1057, _T_1058) @[exu_div_ctl.scala 888:95] + node _T_1060 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1062 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1063 = eq(_T_1062, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1064 = and(_T_1061, _T_1063) @[exu_div_ctl.scala 889:95] + node _T_1065 = and(_T_1059, _T_1064) @[exu_div_ctl.scala 890:11] + node _T_1066 = or(_T_1056, _T_1065) @[exu_div_ctl.scala 899:44] + node _T_1067 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1068 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1069 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1070 = and(_T_1067, _T_1068) @[exu_div_ctl.scala 888:95] + node _T_1071 = and(_T_1070, _T_1069) @[exu_div_ctl.scala 888:95] + node _T_1072 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1073 = eq(_T_1072, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1074 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:58] + node _T_1075 = and(_T_1073, _T_1074) @[exu_div_ctl.scala 889:95] + node _T_1076 = and(_T_1071, _T_1075) @[exu_div_ctl.scala 890:11] + node _T_1077 = or(_T_1066, _T_1076) @[exu_div_ctl.scala 899:79] + node _T_1078 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1079 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1080 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1081 = and(_T_1078, _T_1079) @[exu_div_ctl.scala 888:95] + node _T_1082 = and(_T_1081, _T_1080) @[exu_div_ctl.scala 888:95] + node _T_1083 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1084 = eq(_T_1083, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1085 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1087 = and(_T_1084, _T_1086) @[exu_div_ctl.scala 889:95] + node _T_1088 = and(_T_1082, _T_1087) @[exu_div_ctl.scala 890:11] + node _T_1089 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1090 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:75] + node _T_1091 = eq(_T_1090, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1092 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1093 = and(_T_1089, _T_1091) @[exu_div_ctl.scala 888:95] + node _T_1094 = and(_T_1093, _T_1092) @[exu_div_ctl.scala 888:95] + node _T_1095 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1096 = eq(_T_1095, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1097 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:58] + node _T_1098 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 889:58] + node _T_1099 = and(_T_1096, _T_1097) @[exu_div_ctl.scala 889:95] + node _T_1100 = and(_T_1099, _T_1098) @[exu_div_ctl.scala 889:95] + node _T_1101 = and(_T_1094, _T_1100) @[exu_div_ctl.scala 890:11] + node _T_1102 = or(_T_1088, _T_1101) @[exu_div_ctl.scala 901:45] + node _T_1103 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1104 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1105 = eq(_T_1104, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1106 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1107 = eq(_T_1106, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1108 = and(_T_1105, _T_1107) @[exu_div_ctl.scala 889:95] + node _T_1109 = and(_T_1103, _T_1108) @[exu_div_ctl.scala 890:11] + node _T_1110 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 901:121] + node _T_1111 = eq(_T_1110, UInt<1>("h00")) @[exu_div_ctl.scala 901:116] + node _T_1112 = and(_T_1109, _T_1111) @[exu_div_ctl.scala 901:114] + node _T_1113 = or(_T_1102, _T_1112) @[exu_div_ctl.scala 901:86] + node _T_1114 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1115 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1117 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1118 = eq(_T_1117, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1119 = and(_T_1116, _T_1118) @[exu_div_ctl.scala 889:95] + node _T_1120 = and(_T_1114, _T_1119) @[exu_div_ctl.scala 890:11] + node _T_1121 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 902:40] + node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[exu_div_ctl.scala 902:35] + node _T_1123 = and(_T_1120, _T_1122) @[exu_div_ctl.scala 902:33] + node _T_1124 = or(_T_1113, _T_1123) @[exu_div_ctl.scala 901:129] + node _T_1125 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1126 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1128 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1129 = eq(_T_1128, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1130 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1131 = eq(_T_1130, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1132 = and(_T_1127, _T_1129) @[exu_div_ctl.scala 889:95] + node _T_1133 = and(_T_1132, _T_1131) @[exu_div_ctl.scala 889:95] + node _T_1134 = and(_T_1125, _T_1133) @[exu_div_ctl.scala 890:11] + node _T_1135 = or(_T_1124, _T_1134) @[exu_div_ctl.scala 902:47] + node _T_1136 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:75] + node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1138 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1139 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:75] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1141 = and(_T_1137, _T_1138) @[exu_div_ctl.scala 888:95] + node _T_1142 = and(_T_1141, _T_1140) @[exu_div_ctl.scala 888:95] + node _T_1143 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1145 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1146 = eq(_T_1145, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1147 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:58] + node _T_1148 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 889:58] + node _T_1149 = and(_T_1144, _T_1146) @[exu_div_ctl.scala 889:95] + node _T_1150 = and(_T_1149, _T_1147) @[exu_div_ctl.scala 889:95] + node _T_1151 = and(_T_1150, _T_1148) @[exu_div_ctl.scala 889:95] + node _T_1152 = and(_T_1142, _T_1151) @[exu_div_ctl.scala 890:11] + node _T_1153 = or(_T_1135, _T_1152) @[exu_div_ctl.scala 902:88] + node _T_1154 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:75] + node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1156 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1157 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1158 = and(_T_1155, _T_1156) @[exu_div_ctl.scala 888:95] + node _T_1159 = and(_T_1158, _T_1157) @[exu_div_ctl.scala 888:95] + node _T_1160 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1162 = and(_T_1159, _T_1161) @[exu_div_ctl.scala 890:11] + node _T_1163 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 903:43] + node _T_1164 = eq(_T_1163, UInt<1>("h00")) @[exu_div_ctl.scala 903:38] + node _T_1165 = and(_T_1162, _T_1164) @[exu_div_ctl.scala 903:36] + node _T_1166 = or(_T_1153, _T_1165) @[exu_div_ctl.scala 902:131] + node _T_1167 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1168 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1169 = eq(_T_1168, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1170 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1172 = and(_T_1169, _T_1171) @[exu_div_ctl.scala 889:95] + node _T_1173 = and(_T_1167, _T_1172) @[exu_div_ctl.scala 890:11] + node _T_1174 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 903:83] + node _T_1175 = eq(_T_1174, UInt<1>("h00")) @[exu_div_ctl.scala 903:78] + node _T_1176 = and(_T_1173, _T_1175) @[exu_div_ctl.scala 903:76] + node _T_1177 = or(_T_1166, _T_1176) @[exu_div_ctl.scala 903:47] + node _T_1178 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1179 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:75] + node _T_1180 = eq(_T_1179, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1181 = and(_T_1178, _T_1180) @[exu_div_ctl.scala 888:95] + node _T_1182 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1183 = eq(_T_1182, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1184 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:58] + node _T_1185 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:58] + node _T_1186 = and(_T_1183, _T_1184) @[exu_div_ctl.scala 889:95] + node _T_1187 = and(_T_1186, _T_1185) @[exu_div_ctl.scala 889:95] + node _T_1188 = and(_T_1181, _T_1187) @[exu_div_ctl.scala 890:11] + node _T_1189 = or(_T_1177, _T_1188) @[exu_div_ctl.scala 903:88] + node _T_1190 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:75] + node _T_1191 = eq(_T_1190, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1192 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1193 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1194 = and(_T_1191, _T_1192) @[exu_div_ctl.scala 888:95] + node _T_1195 = and(_T_1194, _T_1193) @[exu_div_ctl.scala 888:95] + node _T_1196 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1197 = eq(_T_1196, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1198 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:58] + node _T_1199 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1200 = eq(_T_1199, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1201 = and(_T_1197, _T_1198) @[exu_div_ctl.scala 889:95] + node _T_1202 = and(_T_1201, _T_1200) @[exu_div_ctl.scala 889:95] + node _T_1203 = and(_T_1195, _T_1202) @[exu_div_ctl.scala 890:11] + node _T_1204 = or(_T_1189, _T_1203) @[exu_div_ctl.scala 903:131] + node _T_1205 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:75] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1207 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1208 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1209 = and(_T_1206, _T_1207) @[exu_div_ctl.scala 888:95] + node _T_1210 = and(_T_1209, _T_1208) @[exu_div_ctl.scala 888:95] + node _T_1211 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1212 = eq(_T_1211, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1213 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1215 = and(_T_1212, _T_1214) @[exu_div_ctl.scala 889:95] + node _T_1216 = and(_T_1210, _T_1215) @[exu_div_ctl.scala 890:11] + node _T_1217 = or(_T_1204, _T_1216) @[exu_div_ctl.scala 904:47] + node _T_1218 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1219 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:75] + node _T_1220 = eq(_T_1219, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1221 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:75] + node _T_1222 = eq(_T_1221, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1223 = and(_T_1218, _T_1220) @[exu_div_ctl.scala 888:95] + node _T_1224 = and(_T_1223, _T_1222) @[exu_div_ctl.scala 888:95] + node _T_1225 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1226 = eq(_T_1225, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1227 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:58] + node _T_1228 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 889:58] + node _T_1229 = and(_T_1226, _T_1227) @[exu_div_ctl.scala 889:95] + node _T_1230 = and(_T_1229, _T_1228) @[exu_div_ctl.scala 889:95] + node _T_1231 = and(_T_1224, _T_1230) @[exu_div_ctl.scala 890:11] + node _T_1232 = or(_T_1217, _T_1231) @[exu_div_ctl.scala 904:88] + node _T_1233 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:75] + node _T_1234 = eq(_T_1233, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1235 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1236 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1237 = and(_T_1234, _T_1235) @[exu_div_ctl.scala 888:95] + node _T_1238 = and(_T_1237, _T_1236) @[exu_div_ctl.scala 888:95] + node _T_1239 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1241 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1243 = and(_T_1240, _T_1242) @[exu_div_ctl.scala 889:95] + node _T_1244 = and(_T_1238, _T_1243) @[exu_div_ctl.scala 890:11] + node _T_1245 = or(_T_1232, _T_1244) @[exu_div_ctl.scala 904:131] + node _T_1246 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1247 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1248 = and(_T_1246, _T_1247) @[exu_div_ctl.scala 888:95] + node _T_1249 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1250 = eq(_T_1249, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1251 = and(_T_1248, _T_1250) @[exu_div_ctl.scala 890:11] + node _T_1252 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 905:82] + node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[exu_div_ctl.scala 905:77] + node _T_1254 = and(_T_1251, _T_1253) @[exu_div_ctl.scala 905:75] + node _T_1255 = or(_T_1245, _T_1254) @[exu_div_ctl.scala 905:47] + node _T_1256 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:75] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1258 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1259 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1260 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1261 = and(_T_1257, _T_1258) @[exu_div_ctl.scala 888:95] + node _T_1262 = and(_T_1261, _T_1259) @[exu_div_ctl.scala 888:95] + node _T_1263 = and(_T_1262, _T_1260) @[exu_div_ctl.scala 888:95] + node _T_1264 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1266 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:58] + node _T_1267 = and(_T_1265, _T_1266) @[exu_div_ctl.scala 889:95] + node _T_1268 = and(_T_1263, _T_1267) @[exu_div_ctl.scala 890:11] + node _T_1269 = or(_T_1255, _T_1268) @[exu_div_ctl.scala 905:88] + node _T_1270 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1271 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1272 = and(_T_1270, _T_1271) @[exu_div_ctl.scala 888:95] + node _T_1273 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:58] + node _T_1274 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1275 = eq(_T_1274, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1276 = and(_T_1273, _T_1275) @[exu_div_ctl.scala 889:95] + node _T_1277 = and(_T_1272, _T_1276) @[exu_div_ctl.scala 890:11] + node _T_1278 = or(_T_1269, _T_1277) @[exu_div_ctl.scala 905:131] + node _T_1279 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1280 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1281 = and(_T_1279, _T_1280) @[exu_div_ctl.scala 888:95] + node _T_1282 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:58] + node _T_1283 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1285 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1287 = and(_T_1282, _T_1284) @[exu_div_ctl.scala 889:95] + node _T_1288 = and(_T_1287, _T_1286) @[exu_div_ctl.scala 889:95] + node _T_1289 = and(_T_1281, _T_1288) @[exu_div_ctl.scala 890:11] + node _T_1290 = or(_T_1278, _T_1289) @[exu_div_ctl.scala 906:47] + node _T_1291 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1292 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1293 = and(_T_1291, _T_1292) @[exu_div_ctl.scala 888:95] + node _T_1294 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1295 = eq(_T_1294, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1296 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1297 = eq(_T_1296, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1298 = and(_T_1295, _T_1297) @[exu_div_ctl.scala 889:95] + node _T_1299 = and(_T_1293, _T_1298) @[exu_div_ctl.scala 890:11] + node _T_1300 = or(_T_1290, _T_1299) @[exu_div_ctl.scala 906:88] + node _T_1301 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1302 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:75] + node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1304 = and(_T_1301, _T_1303) @[exu_div_ctl.scala 888:95] + node _T_1305 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1307 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:58] + node _T_1308 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:58] + node _T_1309 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 889:58] + node _T_1310 = and(_T_1306, _T_1307) @[exu_div_ctl.scala 889:95] + node _T_1311 = and(_T_1310, _T_1308) @[exu_div_ctl.scala 889:95] + node _T_1312 = and(_T_1311, _T_1309) @[exu_div_ctl.scala 889:95] + node _T_1313 = and(_T_1304, _T_1312) @[exu_div_ctl.scala 890:11] + node _T_1314 = or(_T_1300, _T_1313) @[exu_div_ctl.scala 906:131] + node _T_1315 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1316 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1317 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1318 = and(_T_1315, _T_1316) @[exu_div_ctl.scala 888:95] + node _T_1319 = and(_T_1318, _T_1317) @[exu_div_ctl.scala 888:95] + node _T_1320 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:58] + node _T_1321 = and(_T_1319, _T_1320) @[exu_div_ctl.scala 890:11] + node _T_1322 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 907:84] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[exu_div_ctl.scala 907:79] + node _T_1324 = and(_T_1321, _T_1323) @[exu_div_ctl.scala 907:77] + node _T_1325 = or(_T_1314, _T_1324) @[exu_div_ctl.scala 907:47] + node _T_1326 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1327 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1328 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1329 = and(_T_1326, _T_1327) @[exu_div_ctl.scala 888:95] + node _T_1330 = and(_T_1329, _T_1328) @[exu_div_ctl.scala 888:95] + node _T_1331 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:58] + node _T_1332 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1334 = and(_T_1331, _T_1333) @[exu_div_ctl.scala 889:95] + node _T_1335 = and(_T_1330, _T_1334) @[exu_div_ctl.scala 890:11] + node _T_1336 = or(_T_1325, _T_1335) @[exu_div_ctl.scala 907:88] + node _T_1337 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1338 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1339 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1340 = and(_T_1337, _T_1338) @[exu_div_ctl.scala 888:95] + node _T_1341 = and(_T_1340, _T_1339) @[exu_div_ctl.scala 888:95] + node _T_1342 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:58] + node _T_1343 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:75] + node _T_1344 = eq(_T_1343, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1345 = and(_T_1342, _T_1344) @[exu_div_ctl.scala 889:95] + node _T_1346 = and(_T_1341, _T_1345) @[exu_div_ctl.scala 890:11] + node _T_1347 = or(_T_1336, _T_1346) @[exu_div_ctl.scala 907:131] + node _T_1348 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1349 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:75] + node _T_1350 = eq(_T_1349, UInt<1>("h00")) @[exu_div_ctl.scala 888:70] + node _T_1351 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1352 = and(_T_1348, _T_1350) @[exu_div_ctl.scala 888:95] + node _T_1353 = and(_T_1352, _T_1351) @[exu_div_ctl.scala 888:95] + node _T_1354 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:75] + node _T_1355 = eq(_T_1354, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1356 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 889:58] + node _T_1357 = and(_T_1355, _T_1356) @[exu_div_ctl.scala 889:95] + node _T_1358 = and(_T_1353, _T_1357) @[exu_div_ctl.scala 890:11] + node _T_1359 = or(_T_1347, _T_1358) @[exu_div_ctl.scala 908:47] + node _T_1360 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1361 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1362 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1363 = and(_T_1360, _T_1361) @[exu_div_ctl.scala 888:95] + node _T_1364 = and(_T_1363, _T_1362) @[exu_div_ctl.scala 888:95] + node _T_1365 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1366 = eq(_T_1365, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1367 = and(_T_1364, _T_1366) @[exu_div_ctl.scala 890:11] + node _T_1368 = or(_T_1359, _T_1367) @[exu_div_ctl.scala 908:88] + node _T_1369 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1370 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 888:58] + node _T_1371 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1372 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 888:58] + node _T_1373 = and(_T_1369, _T_1370) @[exu_div_ctl.scala 888:95] + node _T_1374 = and(_T_1373, _T_1371) @[exu_div_ctl.scala 888:95] + node _T_1375 = and(_T_1374, _T_1372) @[exu_div_ctl.scala 888:95] + node _T_1376 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 889:58] + node _T_1377 = and(_T_1375, _T_1376) @[exu_div_ctl.scala 890:11] + node _T_1378 = or(_T_1368, _T_1377) @[exu_div_ctl.scala 908:131] + node _T_1379 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 888:58] + node _T_1380 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 888:58] + node _T_1381 = and(_T_1379, _T_1380) @[exu_div_ctl.scala 888:95] + node _T_1382 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 889:75] + node _T_1383 = eq(_T_1382, UInt<1>("h00")) @[exu_div_ctl.scala 889:70] + node _T_1384 = and(_T_1381, _T_1383) @[exu_div_ctl.scala 890:11] + node _T_1385 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 909:81] + node _T_1386 = eq(_T_1385, UInt<1>("h00")) @[exu_div_ctl.scala 909:76] + node _T_1387 = and(_T_1384, _T_1386) @[exu_div_ctl.scala 909:74] + node _T_1388 = or(_T_1378, _T_1387) @[exu_div_ctl.scala 909:47] + node _T_1389 = cat(_T_1077, _T_1388) @[Cat.scala 29:58] + node _T_1390 = cat(_T_943, _T_974) @[Cat.scala 29:58] + node _T_1391 = cat(_T_1390, _T_1389) @[Cat.scala 29:58] + smallnum <= _T_1391 @[exu_div_ctl.scala 892:12] + node _T_1392 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 912:50] + node shortq_dividend = cat(dividend_sign_ff, _T_1392) @[Cat.scala 29:58] + inst a_enc of exu_div_cls @[exu_div_ctl.scala 913:31] a_enc.clock <= clock a_enc.reset <= reset - a_enc.io.operand <= shortq_dividend @[exu_div_ctl.scala 920:20] - inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 922:21] + a_enc.io.operand <= shortq_dividend @[exu_div_ctl.scala 914:23] + inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 916:31] b_enc.clock <= clock b_enc.reset <= reset - node _T_1375 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 923:27] - b_enc.io.operand <= _T_1375 @[exu_div_ctl.scala 923:20] + node _T_1393 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 917:30] + b_enc.io.operand <= _T_1393 @[exu_div_ctl.scala 917:23] node dw_a_enc = cat(UInt<1>("h00"), a_enc.io.cls) @[Cat.scala 29:58] node dw_b_enc = cat(UInt<1>("h00"), b_enc.io.cls) @[Cat.scala 29:58] - node _T_1376 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58] - node _T_1377 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58] - node _T_1378 = sub(_T_1376, _T_1377) @[exu_div_ctl.scala 927:41] - node _T_1379 = tail(_T_1378, 1) @[exu_div_ctl.scala 927:41] - node _T_1380 = add(_T_1379, UInt<7>("h01")) @[exu_div_ctl.scala 927:61] - node dw_shortq_raw = tail(_T_1380, 1) @[exu_div_ctl.scala 927:61] - node _T_1381 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 928:33] - node _T_1382 = bits(_T_1381, 0, 0) @[exu_div_ctl.scala 928:43] - node _T_1383 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 928:63] - node shortq = mux(_T_1382, UInt<1>("h00"), _T_1383) @[exu_div_ctl.scala 928:19] - node _T_1384 = bits(shortq, 5, 5) @[exu_div_ctl.scala 929:38] - node _T_1385 = eq(_T_1384, UInt<1>("h00")) @[exu_div_ctl.scala 929:31] - node _T_1386 = and(valid_ff, _T_1385) @[exu_div_ctl.scala 929:29] - node _T_1387 = bits(shortq, 4, 2) @[exu_div_ctl.scala 929:52] - node _T_1388 = eq(_T_1387, UInt<3>("h07")) @[exu_div_ctl.scala 929:58] - node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[exu_div_ctl.scala 929:44] - node _T_1390 = and(_T_1386, _T_1389) @[exu_div_ctl.scala 929:42] - node _T_1391 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 929:75] - node _T_1392 = and(_T_1390, _T_1391) @[exu_div_ctl.scala 929:73] - shortq_enable <= _T_1392 @[exu_div_ctl.scala 929:17] - node _T_1393 = eq(shortq, UInt<5>("h01f")) @[exu_div_ctl.scala 931:58] - node _T_1394 = eq(shortq, UInt<5>("h01e")) @[exu_div_ctl.scala 931:58] - node _T_1395 = eq(shortq, UInt<5>("h01d")) @[exu_div_ctl.scala 931:58] - node _T_1396 = eq(shortq, UInt<5>("h01c")) @[exu_div_ctl.scala 931:58] - node _T_1397 = eq(shortq, UInt<5>("h01b")) @[exu_div_ctl.scala 931:58] - node _T_1398 = eq(shortq, UInt<5>("h01a")) @[exu_div_ctl.scala 931:58] - node _T_1399 = eq(shortq, UInt<5>("h019")) @[exu_div_ctl.scala 931:58] - node _T_1400 = eq(shortq, UInt<5>("h018")) @[exu_div_ctl.scala 931:58] - node _T_1401 = eq(shortq, UInt<5>("h017")) @[exu_div_ctl.scala 931:58] - node _T_1402 = eq(shortq, UInt<5>("h016")) @[exu_div_ctl.scala 931:58] - node _T_1403 = eq(shortq, UInt<5>("h015")) @[exu_div_ctl.scala 931:58] - node _T_1404 = eq(shortq, UInt<5>("h014")) @[exu_div_ctl.scala 931:58] - node _T_1405 = eq(shortq, UInt<5>("h013")) @[exu_div_ctl.scala 931:58] - node _T_1406 = eq(shortq, UInt<5>("h012")) @[exu_div_ctl.scala 931:58] - node _T_1407 = eq(shortq, UInt<5>("h011")) @[exu_div_ctl.scala 931:58] - node _T_1408 = eq(shortq, UInt<5>("h010")) @[exu_div_ctl.scala 931:58] - node _T_1409 = eq(shortq, UInt<4>("h0f")) @[exu_div_ctl.scala 931:58] - node _T_1410 = eq(shortq, UInt<4>("h0e")) @[exu_div_ctl.scala 931:58] - node _T_1411 = eq(shortq, UInt<4>("h0d")) @[exu_div_ctl.scala 931:58] - node _T_1412 = eq(shortq, UInt<4>("h0c")) @[exu_div_ctl.scala 931:58] - node _T_1413 = eq(shortq, UInt<4>("h0b")) @[exu_div_ctl.scala 931:58] - node _T_1414 = eq(shortq, UInt<4>("h0a")) @[exu_div_ctl.scala 931:58] - node _T_1415 = eq(shortq, UInt<4>("h09")) @[exu_div_ctl.scala 931:58] - node _T_1416 = eq(shortq, UInt<4>("h08")) @[exu_div_ctl.scala 931:58] - node _T_1417 = eq(shortq, UInt<3>("h07")) @[exu_div_ctl.scala 931:58] - node _T_1418 = eq(shortq, UInt<3>("h06")) @[exu_div_ctl.scala 931:58] - node _T_1419 = eq(shortq, UInt<3>("h05")) @[exu_div_ctl.scala 931:58] - node _T_1420 = eq(shortq, UInt<3>("h04")) @[exu_div_ctl.scala 931:58] - node _T_1421 = eq(shortq, UInt<2>("h03")) @[exu_div_ctl.scala 931:58] - node _T_1422 = eq(shortq, UInt<2>("h02")) @[exu_div_ctl.scala 931:58] - node _T_1423 = eq(shortq, UInt<1>("h01")) @[exu_div_ctl.scala 931:58] - node _T_1424 = eq(shortq, UInt<1>("h00")) @[exu_div_ctl.scala 931:58] - node _T_1425 = mux(_T_1393, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1426 = mux(_T_1394, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1427 = mux(_T_1395, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1428 = mux(_T_1396, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1429 = mux(_T_1397, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1430 = mux(_T_1398, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1431 = mux(_T_1399, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1432 = mux(_T_1400, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1433 = mux(_T_1401, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1434 = mux(_T_1402, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1435 = mux(_T_1403, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1436 = mux(_T_1404, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1437 = mux(_T_1405, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1438 = mux(_T_1406, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1439 = mux(_T_1407, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1440 = mux(_T_1408, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1441 = mux(_T_1409, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1442 = mux(_T_1410, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1443 = mux(_T_1411, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1444 = mux(_T_1412, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1445 = mux(_T_1413, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1446 = mux(_T_1414, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1447 = mux(_T_1415, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1448 = mux(_T_1416, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1449 = mux(_T_1417, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1450 = mux(_T_1418, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1451 = mux(_T_1419, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1452 = mux(_T_1420, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1453 = mux(_T_1421, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1454 = mux(_T_1422, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1455 = mux(_T_1423, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1456 = mux(_T_1424, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1457 = or(_T_1425, _T_1426) @[Mux.scala 27:72] - node _T_1458 = or(_T_1457, _T_1427) @[Mux.scala 27:72] - node _T_1459 = or(_T_1458, _T_1428) @[Mux.scala 27:72] - node _T_1460 = or(_T_1459, _T_1429) @[Mux.scala 27:72] - node _T_1461 = or(_T_1460, _T_1430) @[Mux.scala 27:72] - node _T_1462 = or(_T_1461, _T_1431) @[Mux.scala 27:72] - node _T_1463 = or(_T_1462, _T_1432) @[Mux.scala 27:72] - node _T_1464 = or(_T_1463, _T_1433) @[Mux.scala 27:72] - node _T_1465 = or(_T_1464, _T_1434) @[Mux.scala 27:72] - node _T_1466 = or(_T_1465, _T_1435) @[Mux.scala 27:72] - node _T_1467 = or(_T_1466, _T_1436) @[Mux.scala 27:72] - node _T_1468 = or(_T_1467, _T_1437) @[Mux.scala 27:72] - node _T_1469 = or(_T_1468, _T_1438) @[Mux.scala 27:72] - node _T_1470 = or(_T_1469, _T_1439) @[Mux.scala 27:72] - node _T_1471 = or(_T_1470, _T_1440) @[Mux.scala 27:72] - node _T_1472 = or(_T_1471, _T_1441) @[Mux.scala 27:72] - node _T_1473 = or(_T_1472, _T_1442) @[Mux.scala 27:72] - node _T_1474 = or(_T_1473, _T_1443) @[Mux.scala 27:72] - node _T_1475 = or(_T_1474, _T_1444) @[Mux.scala 27:72] + node _T_1394 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58] + node _T_1395 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58] + node _T_1396 = sub(_T_1394, _T_1395) @[exu_div_ctl.scala 921:43] + node _T_1397 = tail(_T_1396, 1) @[exu_div_ctl.scala 921:43] + node _T_1398 = add(_T_1397, UInt<7>("h01")) @[exu_div_ctl.scala 921:63] + node dw_shortq_raw = tail(_T_1398, 1) @[exu_div_ctl.scala 921:63] + node _T_1399 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 922:42] + node _T_1400 = bits(_T_1399, 0, 0) @[exu_div_ctl.scala 922:52] + node _T_1401 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 922:72] + node shortq = mux(_T_1400, UInt<1>("h00"), _T_1401) @[exu_div_ctl.scala 922:28] + node _T_1402 = bits(shortq, 5, 5) @[exu_div_ctl.scala 923:44] + node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[exu_div_ctl.scala 923:37] + node _T_1404 = and(valid_ff, _T_1403) @[exu_div_ctl.scala 923:35] + node _T_1405 = bits(shortq, 4, 2) @[exu_div_ctl.scala 923:58] + node _T_1406 = eq(_T_1405, UInt<3>("h07")) @[exu_div_ctl.scala 923:64] + node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[exu_div_ctl.scala 923:50] + node _T_1408 = and(_T_1404, _T_1407) @[exu_div_ctl.scala 923:48] + node _T_1409 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 923:81] + node _T_1410 = and(_T_1408, _T_1409) @[exu_div_ctl.scala 923:79] + shortq_enable <= _T_1410 @[exu_div_ctl.scala 923:23] + node _T_1411 = eq(shortq, UInt<5>("h01f")) @[exu_div_ctl.scala 925:64] + node _T_1412 = eq(shortq, UInt<5>("h01e")) @[exu_div_ctl.scala 925:64] + node _T_1413 = eq(shortq, UInt<5>("h01d")) @[exu_div_ctl.scala 925:64] + node _T_1414 = eq(shortq, UInt<5>("h01c")) @[exu_div_ctl.scala 925:64] + node _T_1415 = eq(shortq, UInt<5>("h01b")) @[exu_div_ctl.scala 925:64] + node _T_1416 = eq(shortq, UInt<5>("h01a")) @[exu_div_ctl.scala 925:64] + node _T_1417 = eq(shortq, UInt<5>("h019")) @[exu_div_ctl.scala 925:64] + node _T_1418 = eq(shortq, UInt<5>("h018")) @[exu_div_ctl.scala 925:64] + node _T_1419 = eq(shortq, UInt<5>("h017")) @[exu_div_ctl.scala 925:64] + node _T_1420 = eq(shortq, UInt<5>("h016")) @[exu_div_ctl.scala 925:64] + node _T_1421 = eq(shortq, UInt<5>("h015")) @[exu_div_ctl.scala 925:64] + node _T_1422 = eq(shortq, UInt<5>("h014")) @[exu_div_ctl.scala 925:64] + node _T_1423 = eq(shortq, UInt<5>("h013")) @[exu_div_ctl.scala 925:64] + node _T_1424 = eq(shortq, UInt<5>("h012")) @[exu_div_ctl.scala 925:64] + node _T_1425 = eq(shortq, UInt<5>("h011")) @[exu_div_ctl.scala 925:64] + node _T_1426 = eq(shortq, UInt<5>("h010")) @[exu_div_ctl.scala 925:64] + node _T_1427 = eq(shortq, UInt<4>("h0f")) @[exu_div_ctl.scala 925:64] + node _T_1428 = eq(shortq, UInt<4>("h0e")) @[exu_div_ctl.scala 925:64] + node _T_1429 = eq(shortq, UInt<4>("h0d")) @[exu_div_ctl.scala 925:64] + node _T_1430 = eq(shortq, UInt<4>("h0c")) @[exu_div_ctl.scala 925:64] + node _T_1431 = eq(shortq, UInt<4>("h0b")) @[exu_div_ctl.scala 925:64] + node _T_1432 = eq(shortq, UInt<4>("h0a")) @[exu_div_ctl.scala 925:64] + node _T_1433 = eq(shortq, UInt<4>("h09")) @[exu_div_ctl.scala 925:64] + node _T_1434 = eq(shortq, UInt<4>("h08")) @[exu_div_ctl.scala 925:64] + node _T_1435 = eq(shortq, UInt<3>("h07")) @[exu_div_ctl.scala 925:64] + node _T_1436 = eq(shortq, UInt<3>("h06")) @[exu_div_ctl.scala 925:64] + node _T_1437 = eq(shortq, UInt<3>("h05")) @[exu_div_ctl.scala 925:64] + node _T_1438 = eq(shortq, UInt<3>("h04")) @[exu_div_ctl.scala 925:64] + node _T_1439 = eq(shortq, UInt<2>("h03")) @[exu_div_ctl.scala 925:64] + node _T_1440 = eq(shortq, UInt<2>("h02")) @[exu_div_ctl.scala 925:64] + node _T_1441 = eq(shortq, UInt<1>("h01")) @[exu_div_ctl.scala 925:64] + node _T_1442 = eq(shortq, UInt<1>("h00")) @[exu_div_ctl.scala 925:64] + node _T_1443 = mux(_T_1411, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1444 = mux(_T_1412, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1445 = mux(_T_1413, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1446 = mux(_T_1414, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1447 = mux(_T_1415, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1448 = mux(_T_1416, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1449 = mux(_T_1417, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1450 = mux(_T_1418, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1451 = mux(_T_1419, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1452 = mux(_T_1420, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1453 = mux(_T_1421, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1454 = mux(_T_1422, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1455 = mux(_T_1423, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1424, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = mux(_T_1425, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1458 = mux(_T_1426, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1459 = mux(_T_1427, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1460 = mux(_T_1428, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1461 = mux(_T_1429, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1462 = mux(_T_1430, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1463 = mux(_T_1431, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1464 = mux(_T_1432, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1465 = mux(_T_1433, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1466 = mux(_T_1434, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1467 = mux(_T_1435, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1468 = mux(_T_1436, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1469 = mux(_T_1437, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1438, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = mux(_T_1439, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1472 = mux(_T_1440, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1473 = mux(_T_1441, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1474 = mux(_T_1442, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1475 = or(_T_1443, _T_1444) @[Mux.scala 27:72] node _T_1476 = or(_T_1475, _T_1445) @[Mux.scala 27:72] node _T_1477 = or(_T_1476, _T_1446) @[Mux.scala 27:72] node _T_1478 = or(_T_1477, _T_1447) @[Mux.scala 27:72] @@ -2648,145 +2650,163 @@ circuit exu_div_ctl : node _T_1485 = or(_T_1484, _T_1454) @[Mux.scala 27:72] node _T_1486 = or(_T_1485, _T_1455) @[Mux.scala 27:72] node _T_1487 = or(_T_1486, _T_1456) @[Mux.scala 27:72] - wire _T_1488 : UInt<5> @[Mux.scala 27:72] - _T_1488 <= _T_1487 @[Mux.scala 27:72] - shortq_decode <= _T_1488 @[exu_div_ctl.scala 931:17] - node _T_1489 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 932:23] - node _T_1490 = mux(_T_1489, UInt<1>("h00"), shortq_decode) @[exu_div_ctl.scala 932:22] - shortq_shift <= _T_1490 @[exu_div_ctl.scala 932:16] - node _T_1491 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 933:20] - node _T_1492 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 933:30] - node _T_1493 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 933:40] - node _T_1494 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 933:50] - node _T_1495 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 933:60] - node _T_1496 = cat(_T_1494, _T_1495) @[Cat.scala 29:58] - node _T_1497 = cat(_T_1496, b_ff1) @[Cat.scala 29:58] - node _T_1498 = cat(_T_1491, _T_1492) @[Cat.scala 29:58] - node _T_1499 = cat(_T_1498, _T_1493) @[Cat.scala 29:58] - node _T_1500 = cat(_T_1499, _T_1497) @[Cat.scala 29:58] - b_ff <= _T_1500 @[exu_div_ctl.scala 933:8] + node _T_1488 = or(_T_1487, _T_1457) @[Mux.scala 27:72] + node _T_1489 = or(_T_1488, _T_1458) @[Mux.scala 27:72] + node _T_1490 = or(_T_1489, _T_1459) @[Mux.scala 27:72] + node _T_1491 = or(_T_1490, _T_1460) @[Mux.scala 27:72] + node _T_1492 = or(_T_1491, _T_1461) @[Mux.scala 27:72] + node _T_1493 = or(_T_1492, _T_1462) @[Mux.scala 27:72] + node _T_1494 = or(_T_1493, _T_1463) @[Mux.scala 27:72] + node _T_1495 = or(_T_1494, _T_1464) @[Mux.scala 27:72] + node _T_1496 = or(_T_1495, _T_1465) @[Mux.scala 27:72] + node _T_1497 = or(_T_1496, _T_1466) @[Mux.scala 27:72] + node _T_1498 = or(_T_1497, _T_1467) @[Mux.scala 27:72] + node _T_1499 = or(_T_1498, _T_1468) @[Mux.scala 27:72] + node _T_1500 = or(_T_1499, _T_1469) @[Mux.scala 27:72] + node _T_1501 = or(_T_1500, _T_1470) @[Mux.scala 27:72] + node _T_1502 = or(_T_1501, _T_1471) @[Mux.scala 27:72] + node _T_1503 = or(_T_1502, _T_1472) @[Mux.scala 27:72] + node _T_1504 = or(_T_1503, _T_1473) @[Mux.scala 27:72] + node _T_1505 = or(_T_1504, _T_1474) @[Mux.scala 27:72] + wire _T_1506 : UInt<5> @[Mux.scala 27:72] + _T_1506 <= _T_1505 @[Mux.scala 27:72] + shortq_decode <= _T_1506 @[exu_div_ctl.scala 925:23] + node _T_1507 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 926:30] + node _T_1508 = mux(_T_1507, UInt<1>("h00"), shortq_decode) @[exu_div_ctl.scala 926:29] + shortq_shift <= _T_1508 @[exu_div_ctl.scala 926:23] + node _T_1509 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 927:35] + node _T_1510 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 927:45] + node _T_1511 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 927:55] + node _T_1512 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 927:65] + node _T_1513 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 927:75] + node _T_1514 = cat(_T_1512, _T_1513) @[Cat.scala 29:58] + node _T_1515 = cat(_T_1514, b_ff1) @[Cat.scala 29:58] + node _T_1516 = cat(_T_1509, _T_1510) @[Cat.scala 29:58] + node _T_1517 = cat(_T_1516, _T_1511) @[Cat.scala 29:58] + node _T_1518 = cat(_T_1517, _T_1515) @[Cat.scala 29:58] + b_ff <= _T_1518 @[exu_div_ctl.scala 927:23] inst rvclkhdr of rvclkhdr @[lib.scala 390:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 392:18] rvclkhdr.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1501 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1519 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] - _T_1501 <= valid_ff_in @[Reg.scala 28:23] + _T_1519 <= valid_ff_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - valid_ff <= _T_1501 @[exu_div_ctl.scala 934:12] + valid_ff <= _T_1519 @[exu_div_ctl.scala 928:23] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 392:18] rvclkhdr_1.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1502 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1520 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] - _T_1502 <= control_in @[Reg.scala 28:23] + _T_1520 <= control_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - control_ff <= _T_1502 @[exu_div_ctl.scala 935:16] + control_ff <= _T_1520 @[exu_div_ctl.scala 929:23] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 392:18] rvclkhdr_2.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1503 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1521 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] - _T_1503 <= by_zero_case @[Reg.scala 28:23] + _T_1521 <= by_zero_case @[Reg.scala 28:23] skip @[Reg.scala 28:19] - by_zero_case_ff <= _T_1503 @[exu_div_ctl.scala 936:19] + by_zero_case_ff <= _T_1521 @[exu_div_ctl.scala 930:23] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 392:18] rvclkhdr_3.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1504 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1522 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] - _T_1504 <= shortq_enable @[Reg.scala 28:23] + _T_1522 <= shortq_enable @[Reg.scala 28:23] skip @[Reg.scala 28:19] - shortq_enable_ff <= _T_1504 @[exu_div_ctl.scala 937:20] + shortq_enable_ff <= _T_1522 @[exu_div_ctl.scala 931:23] inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 392:18] rvclkhdr_4.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1505 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1523 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] - _T_1505 <= shortq_shift @[Reg.scala 28:23] + _T_1523 <= shortq_shift @[Reg.scala 28:23] skip @[Reg.scala 28:19] - shortq_shift_ff <= _T_1505 @[exu_div_ctl.scala 938:19] + shortq_shift_ff <= _T_1523 @[exu_div_ctl.scala 932:23] inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[lib.scala 392:18] rvclkhdr_5.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1506 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1524 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] - _T_1506 <= finish @[Reg.scala 28:23] + _T_1524 <= finish @[Reg.scala 28:23] skip @[Reg.scala 28:19] - finish_ff <= _T_1506 @[exu_div_ctl.scala 939:13] + finish_ff <= _T_1524 @[exu_div_ctl.scala 933:23] inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[lib.scala 392:18] rvclkhdr_6.io.en <= misc_enable @[lib.scala 393:17] rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1507 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1525 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when misc_enable : @[Reg.scala 28:19] - _T_1507 <= count_in @[Reg.scala 28:23] + _T_1525 <= count_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - count_ff <= _T_1507 @[exu_div_ctl.scala 940:12] + count_ff <= _T_1525 @[exu_div_ctl.scala 934:23] inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 392:18] rvclkhdr_7.io.en <= a_enable @[lib.scala 393:17] rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1508 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1526 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when a_enable : @[Reg.scala 28:19] - _T_1508 <= a_in @[Reg.scala 28:23] + _T_1526 <= a_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - a_ff <= _T_1508 @[exu_div_ctl.scala 942:8] - node _T_1509 = bits(b_in, 32, 0) @[exu_div_ctl.scala 943:23] + a_ff <= _T_1526 @[exu_div_ctl.scala 936:23] + node _T_1527 = bits(b_in, 32, 0) @[exu_div_ctl.scala 937:37] inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 392:18] rvclkhdr_8.io.en <= b_enable @[lib.scala 393:17] rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1510 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1528 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when b_enable : @[Reg.scala 28:19] - _T_1510 <= _T_1509 @[Reg.scala 28:23] + _T_1528 <= _T_1527 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - b_ff1 <= _T_1510 @[exu_div_ctl.scala 943:9] + b_ff1 <= _T_1528 @[exu_div_ctl.scala 937:23] inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 392:18] rvclkhdr_9.io.en <= rq_enable @[lib.scala 393:17] rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1511 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1529 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when rq_enable : @[Reg.scala 28:19] - _T_1511 <= r_in @[Reg.scala 28:23] + _T_1529 <= r_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - r_ff <= _T_1511 @[exu_div_ctl.scala 944:8] + r_ff <= _T_1529 @[exu_div_ctl.scala 938:23] inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 392:18] rvclkhdr_10.io.en <= rq_enable @[lib.scala 393:17] rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24] - reg _T_1512 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1530 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when rq_enable : @[Reg.scala 28:19] - _T_1512 <= q_in @[Reg.scala 28:23] + _T_1530 <= q_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - q_ff <= _T_1512 @[exu_div_ctl.scala 945:8] + q_ff <= _T_1530 @[exu_div_ctl.scala 939:23] module exu_div_ctl : input clock : Clock diff --git a/exu_div_ctl.v b/exu_div_ctl.v index e49b2b34..6386a7e7 100644 --- a/exu_div_ctl.v +++ b/exu_div_ctl.v @@ -2,37 +2,37 @@ module exu_div_cls( input [32:0] io_operand, output [4:0] io_cls ); - wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 956:63] - wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 956:63] - wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 956:63] - wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 956:63] - wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 956:63] - wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 956:63] - wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 956:63] - wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 956:63] - wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 956:63] - wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 956:63] - wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 956:63] - wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 956:63] - wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 956:63] - wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 956:63] - wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 956:63] - wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 956:63] - wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 956:63] - wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 956:63] - wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 956:63] - wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 956:63] - wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 956:63] - wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 956:63] - wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 956:63] - wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 956:63] - wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 956:63] - wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 956:63] - wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 956:63] - wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 956:63] - wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 956:63] - wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 956:63] - wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 956:63] + wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 950:63] + wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 950:63] + wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 950:63] + wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 950:63] + wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 950:63] + wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 950:63] + wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 950:63] + wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 950:63] + wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 950:63] + wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 950:63] + wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 950:63] + wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 950:63] + wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 950:63] + wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 950:63] + wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 950:63] + wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 950:63] + wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 950:63] + wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 950:63] + wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 950:63] + wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 950:63] + wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 950:63] + wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 950:63] + wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 950:63] + wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 950:63] + wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 950:63] + wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 950:63] + wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 950:63] + wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 950:63] + wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 950:63] + wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 950:63] + wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 950:63] wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] @@ -97,37 +97,37 @@ module exu_div_cls( wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72] wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72] wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72] - wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 958:25] - wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 959:76] - wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 959:76] - wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 959:76] - wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 959:76] - wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 959:76] - wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 959:76] - wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 959:76] - wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 959:76] - wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 959:76] - wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 959:76] - wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 959:76] - wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 959:76] - wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 959:76] - wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 959:76] - wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 959:76] - wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 959:76] - wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 959:76] - wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 959:76] - wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 959:76] - wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 959:76] - wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 959:76] - wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 959:76] - wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 959:76] - wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 959:76] - wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 959:76] - wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 959:76] - wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 959:76] - wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 959:76] - wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 959:76] - wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 959:76] + wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 952:25] + wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 953:76] + wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 953:76] + wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 953:76] + wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 953:76] + wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 953:76] + wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 953:76] + wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 953:76] + wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 953:76] + wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 953:76] + wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 953:76] + wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 953:76] + wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 953:76] + wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 953:76] + wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 953:76] + wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 953:76] + wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 953:76] + wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 953:76] + wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 953:76] + wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 953:76] + wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 953:76] + wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 953:76] + wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 953:76] + wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 953:76] + wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 953:76] + wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 953:76] + wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 953:76] + wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 953:76] + wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 953:76] + wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 953:76] + wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 953:76] wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] @@ -190,8 +190,8 @@ module exu_div_cls( wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72] wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72] wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72] - wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 958:44] - assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 960:10] + wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 952:44] + assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 954:25] endmodule module rvclkhdr( input io_clk, @@ -236,10 +236,10 @@ module exu_div_new_4bit_fullshortq( reg [63:0] _RAND_9; reg [31:0] _RAND_10; `endif // RANDOMIZE_REG_INIT - wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 919:21] - wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 919:21] - wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 922:21] - wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 922:21] + wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 913:31] + wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 913:31] + wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 916:31] + wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 916:31] wire rvclkhdr_io_clk; // @[lib.scala 390:23] wire rvclkhdr_io_en; // @[lib.scala 390:23] wire rvclkhdr_1_io_clk; // @[lib.scala 390:23] @@ -262,685 +262,685 @@ module exu_div_new_4bit_fullshortq( wire rvclkhdr_9_io_en; // @[lib.scala 390:23] wire rvclkhdr_10_io_clk; // @[lib.scala 390:23] wire rvclkhdr_10_io_en; // @[lib.scala 390:23] - wire _T = ~io_cancel; // @[exu_div_ctl.scala 777:35] - wire valid_ff_in = io_valid_in & _T; // @[exu_div_ctl.scala 777:33] - wire _T_1 = ~io_valid_in; // @[exu_div_ctl.scala 778:35] + wire _T = ~io_cancel; // @[exu_div_ctl.scala 776:44] + wire valid_ff_in = io_valid_in & _T; // @[exu_div_ctl.scala 776:42] + wire _T_1 = ~io_valid_in; // @[exu_div_ctl.scala 777:35] reg [2:0] control_ff; // @[Reg.scala 27:20] - wire _T_3 = _T_1 & control_ff[2]; // @[exu_div_ctl.scala 778:48] - wire _T_4 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 778:80] - wire _T_6 = _T_4 & io_dividend_in[31]; // @[exu_div_ctl.scala 778:96] - wire _T_7 = _T_3 | _T_6; // @[exu_div_ctl.scala 778:65] - wire _T_10 = _T_1 & control_ff[1]; // @[exu_div_ctl.scala 778:133] - wire _T_13 = _T_4 & io_divisor_in[31]; // @[exu_div_ctl.scala 778:181] - wire _T_14 = _T_10 | _T_13; // @[exu_div_ctl.scala 778:150] - wire _T_17 = _T_1 & control_ff[0]; // @[exu_div_ctl.scala 778:218] - wire _T_18 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 778:250] - wire _T_19 = _T_17 | _T_18; // @[exu_div_ctl.scala 778:235] + wire _T_3 = _T_1 & control_ff[2]; // @[exu_div_ctl.scala 777:48] + wire _T_4 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 777:80] + wire _T_6 = _T_4 & io_dividend_in[31]; // @[exu_div_ctl.scala 777:96] + wire _T_7 = _T_3 | _T_6; // @[exu_div_ctl.scala 777:65] + wire _T_10 = _T_1 & control_ff[1]; // @[exu_div_ctl.scala 777:133] + wire _T_13 = _T_4 & io_divisor_in[31]; // @[exu_div_ctl.scala 777:181] + wire _T_14 = _T_10 | _T_13; // @[exu_div_ctl.scala 777:150] + wire _T_17 = _T_1 & control_ff[0]; // @[exu_div_ctl.scala 777:218] + wire _T_18 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 777:250] + wire _T_19 = _T_17 | _T_18; // @[exu_div_ctl.scala 777:235] wire [2:0] control_in = {_T_7,_T_14,_T_19}; // @[Cat.scala 29:58] reg [32:0] b_ff1; // @[Reg.scala 27:20] wire [37:0] b_ff = {b_ff1[32],b_ff1[32],b_ff1[32],b_ff1[32],b_ff1[32],b_ff1}; // @[Cat.scala 29:58] - wire _T_22 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 782:54] + wire _T_22 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 781:54] reg valid_ff; // @[Reg.scala 27:20] - wire by_zero_case = valid_ff & _T_22; // @[exu_div_ctl.scala 782:40] + wire by_zero_case = valid_ff & _T_22; // @[exu_div_ctl.scala 781:40] reg [31:0] a_ff; // @[Reg.scala 27:20] - wire _T_24 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 784:37] - wire _T_26 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 784:60] - wire _T_27 = _T_24 & _T_26; // @[exu_div_ctl.scala 784:46] - wire _T_28 = ~by_zero_case; // @[exu_div_ctl.scala 784:71] - wire _T_29 = _T_27 & _T_28; // @[exu_div_ctl.scala 784:69] - wire _T_30 = ~control_ff[0]; // @[exu_div_ctl.scala 784:87] - wire _T_31 = _T_29 & _T_30; // @[exu_div_ctl.scala 784:85] - wire _T_32 = _T_31 & valid_ff; // @[exu_div_ctl.scala 784:95] - wire _T_34 = _T_32 & _T; // @[exu_div_ctl.scala 784:106] - wire _T_36 = a_ff == 32'h0; // @[exu_div_ctl.scala 785:18] - wire _T_38 = _T_36 & _T_28; // @[exu_div_ctl.scala 785:27] - wire _T_40 = _T_38 & _T_30; // @[exu_div_ctl.scala 785:43] - wire _T_41 = _T_40 & valid_ff; // @[exu_div_ctl.scala 785:53] - wire _T_43 = _T_41 & _T; // @[exu_div_ctl.scala 785:64] - wire smallnum_case = _T_34 | _T_43; // @[exu_div_ctl.scala 784:120] + wire _T_24 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 783:37] + wire _T_26 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 783:60] + wire _T_27 = _T_24 & _T_26; // @[exu_div_ctl.scala 783:46] + wire _T_28 = ~by_zero_case; // @[exu_div_ctl.scala 783:71] + wire _T_29 = _T_27 & _T_28; // @[exu_div_ctl.scala 783:69] + wire _T_30 = ~control_ff[0]; // @[exu_div_ctl.scala 783:87] + wire _T_31 = _T_29 & _T_30; // @[exu_div_ctl.scala 783:85] + wire _T_32 = _T_31 & valid_ff; // @[exu_div_ctl.scala 783:95] + wire _T_34 = _T_32 & _T; // @[exu_div_ctl.scala 783:106] + wire _T_36 = a_ff == 32'h0; // @[exu_div_ctl.scala 784:18] + wire _T_38 = _T_36 & _T_28; // @[exu_div_ctl.scala 784:27] + wire _T_40 = _T_38 & _T_30; // @[exu_div_ctl.scala 784:43] + wire _T_41 = _T_40 & valid_ff; // @[exu_div_ctl.scala 784:53] + wire _T_43 = _T_41 & _T; // @[exu_div_ctl.scala 784:64] + wire smallnum_case = _T_34 | _T_43; // @[exu_div_ctl.scala 783:120] reg [6:0] count_ff; // @[Reg.scala 27:20] - wire _T_44 = |count_ff; // @[exu_div_ctl.scala 786:42] + wire _T_44 = |count_ff; // @[exu_div_ctl.scala 785:42] reg shortq_enable_ff; // @[Reg.scala 27:20] - wire running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 786:45] - wire _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 787:43] - wire _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 787:54] - wire _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 787:66] + wire running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 785:45] + wire _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 786:43] + wire _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 786:54] + wire _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 786:66] reg finish_ff; // @[Reg.scala 27:20] - wire misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 787:82] - wire _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 788:45] - wire _T_49 = count_ff == 7'h20; // @[exu_div_ctl.scala 788:72] - wire finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 788:60] - wire finish = finish_raw & _T; // @[exu_div_ctl.scala 789:41] - wire _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 790:40] - wire _T_52 = ~finish; // @[exu_div_ctl.scala 790:59] - wire _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 790:57] - wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 790:69] - wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 790:67] - wire _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 790:80] - wire [6:0] _T_1376 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58] - wire [6:0] _T_1377 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58] - wire [6:0] _T_1379 = _T_1376 - _T_1377; // @[exu_div_ctl.scala 927:41] - wire [6:0] dw_shortq_raw = _T_1379 + 7'h1; // @[exu_div_ctl.scala 927:61] - wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 928:19] - wire _T_1385 = ~shortq[5]; // @[exu_div_ctl.scala 929:31] - wire _T_1386 = valid_ff & _T_1385; // @[exu_div_ctl.scala 929:29] - wire _T_1388 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 929:58] - wire _T_1389 = ~_T_1388; // @[exu_div_ctl.scala 929:44] - wire _T_1390 = _T_1386 & _T_1389; // @[exu_div_ctl.scala 929:42] - wire shortq_enable = _T_1390 & _T; // @[exu_div_ctl.scala 929:73] - wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 790:95] - wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 790:93] + wire misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 786:82] + wire _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 787:45] + wire _T_49 = count_ff == 7'h20; // @[exu_div_ctl.scala 787:72] + wire finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 787:60] + wire finish = finish_raw & _T; // @[exu_div_ctl.scala 788:41] + wire _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 789:40] + wire _T_52 = ~finish; // @[exu_div_ctl.scala 789:59] + wire _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 789:57] + wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 789:69] + wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 789:67] + wire _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 789:80] + wire [6:0] _T_1394 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58] + wire [6:0] _T_1395 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58] + wire [6:0] _T_1397 = _T_1394 - _T_1395; // @[exu_div_ctl.scala 921:43] + wire [6:0] dw_shortq_raw = _T_1397 + 7'h1; // @[exu_div_ctl.scala 921:63] + wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 922:28] + wire _T_1403 = ~shortq[5]; // @[exu_div_ctl.scala 923:37] + wire _T_1404 = valid_ff & _T_1403; // @[exu_div_ctl.scala 923:35] + wire _T_1406 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 923:64] + wire _T_1407 = ~_T_1406; // @[exu_div_ctl.scala 923:50] + wire _T_1408 = _T_1404 & _T_1407; // @[exu_div_ctl.scala 923:48] + wire shortq_enable = _T_1408 & _T; // @[exu_div_ctl.scala 923:79] + wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 789:95] + wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 789:93] wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12] - wire [6:0] _T_62 = count_ff + 7'h4; // @[exu_div_ctl.scala 791:63] + wire [6:0] _T_62 = count_ff + 7'h4; // @[exu_div_ctl.scala 790:63] reg [4:0] shortq_shift_ff; // @[Reg.scala 27:20] wire [6:0] _T_63 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58] - wire [6:0] _T_65 = _T_62 + _T_63; // @[exu_div_ctl.scala 791:74] - wire [6:0] count_in = _T_60 & _T_65; // @[exu_div_ctl.scala 791:51] - wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 792:43] - wire _T_66 = ~shortq_enable_ff; // @[exu_div_ctl.scala 793:47] - wire a_shift = running_state & _T_66; // @[exu_div_ctl.scala 793:45] + wire [6:0] _T_65 = _T_62 + _T_63; // @[exu_div_ctl.scala 790:74] + wire [6:0] count_in = _T_60 & _T_65; // @[exu_div_ctl.scala 790:51] + wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 791:43] + wire _T_66 = ~shortq_enable_ff; // @[exu_div_ctl.scala 792:47] + wire a_shift = running_state & _T_66; // @[exu_div_ctl.scala 792:45] wire [32:0] _T_68 = control_ff[2] ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12] wire [64:0] _T_70 = {_T_68,a_ff}; // @[Cat.scala 29:58] - wire [95:0] _GEN_11 = {{31'd0}, _T_70}; // @[exu_div_ctl.scala 794:74] - wire [95:0] _T_71 = _GEN_11 << shortq_shift_ff; // @[exu_div_ctl.scala 794:74] - wire _T_72 = control_ff[2] ^ control_ff[1]; // @[exu_div_ctl.scala 795:61] - wire _T_73 = ~_T_72; // @[exu_div_ctl.scala 795:42] - wire b_twos_comp = valid_ff & _T_73; // @[exu_div_ctl.scala 795:40] - wire _T_76 = ~valid_ff; // @[exu_div_ctl.scala 797:30] - wire _T_78 = _T_76 & _T_30; // @[exu_div_ctl.scala 797:40] - wire _T_80 = _T_78 & _T_72; // @[exu_div_ctl.scala 797:50] + wire [95:0] _GEN_11 = {{31'd0}, _T_70}; // @[exu_div_ctl.scala 793:74] + wire [95:0] _T_71 = _GEN_11 << shortq_shift_ff; // @[exu_div_ctl.scala 793:74] + wire _T_72 = control_ff[2] ^ control_ff[1]; // @[exu_div_ctl.scala 794:61] + wire _T_73 = ~_T_72; // @[exu_div_ctl.scala 794:42] + wire b_twos_comp = valid_ff & _T_73; // @[exu_div_ctl.scala 794:40] + wire _T_76 = ~valid_ff; // @[exu_div_ctl.scala 796:30] + wire _T_78 = _T_76 & _T_30; // @[exu_div_ctl.scala 796:40] + wire _T_80 = _T_78 & _T_72; // @[exu_div_ctl.scala 796:50] reg by_zero_case_ff; // @[Reg.scala 27:20] - wire _T_81 = ~by_zero_case_ff; // @[exu_div_ctl.scala 797:92] - wire twos_comp_q_sel = _T_80 & _T_81; // @[exu_div_ctl.scala 797:90] - wire b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 798:43] - wire rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 799:54] - wire _T_83 = valid_ff & control_ff[2]; // @[exu_div_ctl.scala 800:40] - wire r_sign_sel = _T_83 & _T_28; // @[exu_div_ctl.scala 800:59] + wire _T_81 = ~by_zero_case_ff; // @[exu_div_ctl.scala 796:92] + wire twos_comp_q_sel = _T_80 & _T_81; // @[exu_div_ctl.scala 796:90] + wire b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 797:43] + wire rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 798:54] + wire _T_83 = valid_ff & control_ff[2]; // @[exu_div_ctl.scala 799:40] + wire r_sign_sel = _T_83 & _T_28; // @[exu_div_ctl.scala 799:59] reg [32:0] r_ff; // @[Reg.scala 27:20] wire [37:0] _T_287 = {r_ff[32],r_ff,a_ff[31:28]}; // @[Cat.scala 29:58] wire [37:0] _T_289 = {b_ff[34:0],3'h0}; // @[Cat.scala 29:58] - wire [37:0] _T_291 = _T_287 + _T_289; // @[exu_div_ctl.scala 816:58] + wire [37:0] _T_291 = _T_287 + _T_289; // @[exu_div_ctl.scala 815:67] wire [37:0] _T_293 = {b_ff[35:0],2'h0}; // @[Cat.scala 29:58] - wire [37:0] _T_295 = _T_291 + _T_293; // @[exu_div_ctl.scala 816:85] + wire [37:0] _T_295 = _T_291 + _T_293; // @[exu_div_ctl.scala 815:94] wire [37:0] _T_297 = {b_ff[36:0],1'h0}; // @[Cat.scala 29:58] - wire [37:0] _T_299 = _T_295 + _T_297; // @[exu_div_ctl.scala 816:112] - wire [37:0] adder15_out = _T_299 + b_ff; // @[exu_div_ctl.scala 816:134] - wire _T_302 = ~adder15_out[37]; // @[exu_div_ctl.scala 819:6] - wire _T_303 = _T_302 ^ control_ff[2]; // @[exu_div_ctl.scala 819:23] - wire _T_305 = a_ff[27:0] == 28'h0; // @[exu_div_ctl.scala 819:58] - wire _T_306 = adder15_out == 38'h0; // @[exu_div_ctl.scala 819:82] - wire _T_307 = _T_305 & _T_306; // @[exu_div_ctl.scala 819:67] - wire _T_308 = _T_303 | _T_307; // @[exu_div_ctl.scala 819:43] - wire _T_310 = ~_T_299[37]; // @[exu_div_ctl.scala 820:6] - wire _T_311 = _T_310 ^ control_ff[2]; // @[exu_div_ctl.scala 820:23] - wire _T_314 = _T_299 == 38'h0; // @[exu_div_ctl.scala 820:82] - wire _T_315 = _T_305 & _T_314; // @[exu_div_ctl.scala 820:67] - wire _T_316 = _T_311 | _T_315; // @[exu_div_ctl.scala 820:43] - wire [37:0] adder13_out = _T_295 + b_ff; // @[exu_div_ctl.scala 814:112] - wire _T_318 = ~adder13_out[37]; // @[exu_div_ctl.scala 821:6] - wire _T_319 = _T_318 ^ control_ff[2]; // @[exu_div_ctl.scala 821:23] - wire _T_322 = adder13_out == 38'h0; // @[exu_div_ctl.scala 821:82] - wire _T_323 = _T_305 & _T_322; // @[exu_div_ctl.scala 821:67] - wire _T_324 = _T_319 | _T_323; // @[exu_div_ctl.scala 821:43] - wire _T_326 = ~_T_295[37]; // @[exu_div_ctl.scala 822:6] - wire _T_327 = _T_326 ^ control_ff[2]; // @[exu_div_ctl.scala 822:23] - wire _T_330 = _T_295 == 38'h0; // @[exu_div_ctl.scala 822:82] - wire _T_331 = _T_305 & _T_330; // @[exu_div_ctl.scala 822:67] - wire _T_332 = _T_327 | _T_331; // @[exu_div_ctl.scala 822:43] - wire [37:0] _T_239 = _T_291 + _T_297; // @[exu_div_ctl.scala 812:85] - wire [37:0] adder11_out = _T_239 + b_ff; // @[exu_div_ctl.scala 812:107] - wire _T_334 = ~adder11_out[37]; // @[exu_div_ctl.scala 823:6] - wire _T_335 = _T_334 ^ control_ff[2]; // @[exu_div_ctl.scala 823:23] - wire _T_338 = adder11_out == 38'h0; // @[exu_div_ctl.scala 823:82] - wire _T_339 = _T_305 & _T_338; // @[exu_div_ctl.scala 823:67] - wire _T_340 = _T_335 | _T_339; // @[exu_div_ctl.scala 823:43] - wire _T_342 = ~_T_239[37]; // @[exu_div_ctl.scala 824:6] - wire _T_343 = _T_342 ^ control_ff[2]; // @[exu_div_ctl.scala 824:23] - wire _T_346 = _T_239 == 38'h0; // @[exu_div_ctl.scala 824:82] - wire _T_347 = _T_305 & _T_346; // @[exu_div_ctl.scala 824:67] - wire _T_348 = _T_343 | _T_347; // @[exu_div_ctl.scala 824:43] - wire [37:0] adder9_out = _T_291 + b_ff; // @[exu_div_ctl.scala 810:85] - wire _T_350 = ~adder9_out[37]; // @[exu_div_ctl.scala 825:6] - wire _T_351 = _T_350 ^ control_ff[2]; // @[exu_div_ctl.scala 825:22] - wire _T_354 = adder9_out == 38'h0; // @[exu_div_ctl.scala 825:80] - wire _T_355 = _T_305 & _T_354; // @[exu_div_ctl.scala 825:66] - wire _T_356 = _T_351 | _T_355; // @[exu_div_ctl.scala 825:42] - wire _T_358 = ~_T_291[37]; // @[exu_div_ctl.scala 826:6] - wire _T_359 = _T_358 ^ control_ff[2]; // @[exu_div_ctl.scala 826:22] - wire _T_362 = _T_291 == 38'h0; // @[exu_div_ctl.scala 826:80] - wire _T_363 = _T_305 & _T_362; // @[exu_div_ctl.scala 826:66] - wire _T_364 = _T_359 | _T_363; // @[exu_div_ctl.scala 826:42] - wire [37:0] _T_191 = _T_287 + _T_293; // @[exu_div_ctl.scala 808:58] - wire [37:0] _T_195 = _T_191 + _T_297; // @[exu_div_ctl.scala 808:85] - wire [37:0] adder7_out = _T_195 + b_ff; // @[exu_div_ctl.scala 808:107] - wire _T_366 = ~adder7_out[37]; // @[exu_div_ctl.scala 827:6] - wire _T_367 = _T_366 ^ control_ff[2]; // @[exu_div_ctl.scala 827:22] - wire _T_370 = adder7_out == 38'h0; // @[exu_div_ctl.scala 827:80] - wire _T_371 = _T_305 & _T_370; // @[exu_div_ctl.scala 827:66] - wire _T_372 = _T_367 | _T_371; // @[exu_div_ctl.scala 827:42] - wire _T_374 = ~_T_195[37]; // @[exu_div_ctl.scala 828:6] - wire _T_375 = _T_374 ^ control_ff[2]; // @[exu_div_ctl.scala 828:22] - wire _T_378 = _T_195 == 38'h0; // @[exu_div_ctl.scala 828:80] - wire _T_379 = _T_305 & _T_378; // @[exu_div_ctl.scala 828:66] - wire _T_380 = _T_375 | _T_379; // @[exu_div_ctl.scala 828:42] - wire [37:0] adder5_out = _T_191 + b_ff; // @[exu_div_ctl.scala 806:85] - wire _T_382 = ~adder5_out[37]; // @[exu_div_ctl.scala 829:6] - wire _T_383 = _T_382 ^ control_ff[2]; // @[exu_div_ctl.scala 829:22] - wire _T_386 = adder5_out == 38'h0; // @[exu_div_ctl.scala 829:80] - wire _T_387 = _T_305 & _T_386; // @[exu_div_ctl.scala 829:66] - wire _T_388 = _T_383 | _T_387; // @[exu_div_ctl.scala 829:42] - wire _T_390 = ~_T_191[37]; // @[exu_div_ctl.scala 830:6] - wire _T_391 = _T_390 ^ control_ff[2]; // @[exu_div_ctl.scala 830:22] - wire _T_394 = _T_191 == 38'h0; // @[exu_div_ctl.scala 830:80] - wire _T_395 = _T_305 & _T_394; // @[exu_div_ctl.scala 830:66] - wire _T_396 = _T_391 | _T_395; // @[exu_div_ctl.scala 830:42] + wire [37:0] _T_299 = _T_295 + _T_297; // @[exu_div_ctl.scala 815:121] + wire [37:0] adder15_out = _T_299 + b_ff; // @[exu_div_ctl.scala 815:143] + wire _T_302 = ~adder15_out[37]; // @[exu_div_ctl.scala 818:6] + wire _T_303 = _T_302 ^ control_ff[2]; // @[exu_div_ctl.scala 818:23] + wire _T_305 = a_ff[27:0] == 28'h0; // @[exu_div_ctl.scala 818:58] + wire _T_306 = adder15_out == 38'h0; // @[exu_div_ctl.scala 818:82] + wire _T_307 = _T_305 & _T_306; // @[exu_div_ctl.scala 818:67] + wire _T_308 = _T_303 | _T_307; // @[exu_div_ctl.scala 818:43] + wire _T_310 = ~_T_299[37]; // @[exu_div_ctl.scala 819:6] + wire _T_311 = _T_310 ^ control_ff[2]; // @[exu_div_ctl.scala 819:23] + wire _T_314 = _T_299 == 38'h0; // @[exu_div_ctl.scala 819:82] + wire _T_315 = _T_305 & _T_314; // @[exu_div_ctl.scala 819:67] + wire _T_316 = _T_311 | _T_315; // @[exu_div_ctl.scala 819:43] + wire [37:0] adder13_out = _T_295 + b_ff; // @[exu_div_ctl.scala 813:121] + wire _T_318 = ~adder13_out[37]; // @[exu_div_ctl.scala 820:6] + wire _T_319 = _T_318 ^ control_ff[2]; // @[exu_div_ctl.scala 820:23] + wire _T_322 = adder13_out == 38'h0; // @[exu_div_ctl.scala 820:82] + wire _T_323 = _T_305 & _T_322; // @[exu_div_ctl.scala 820:67] + wire _T_324 = _T_319 | _T_323; // @[exu_div_ctl.scala 820:43] + wire _T_326 = ~_T_295[37]; // @[exu_div_ctl.scala 821:6] + wire _T_327 = _T_326 ^ control_ff[2]; // @[exu_div_ctl.scala 821:23] + wire _T_330 = _T_295 == 38'h0; // @[exu_div_ctl.scala 821:82] + wire _T_331 = _T_305 & _T_330; // @[exu_div_ctl.scala 821:67] + wire _T_332 = _T_327 | _T_331; // @[exu_div_ctl.scala 821:43] + wire [37:0] _T_239 = _T_291 + _T_297; // @[exu_div_ctl.scala 811:94] + wire [37:0] adder11_out = _T_239 + b_ff; // @[exu_div_ctl.scala 811:116] + wire _T_334 = ~adder11_out[37]; // @[exu_div_ctl.scala 822:6] + wire _T_335 = _T_334 ^ control_ff[2]; // @[exu_div_ctl.scala 822:23] + wire _T_338 = adder11_out == 38'h0; // @[exu_div_ctl.scala 822:82] + wire _T_339 = _T_305 & _T_338; // @[exu_div_ctl.scala 822:67] + wire _T_340 = _T_335 | _T_339; // @[exu_div_ctl.scala 822:43] + wire _T_342 = ~_T_239[37]; // @[exu_div_ctl.scala 823:6] + wire _T_343 = _T_342 ^ control_ff[2]; // @[exu_div_ctl.scala 823:23] + wire _T_346 = _T_239 == 38'h0; // @[exu_div_ctl.scala 823:82] + wire _T_347 = _T_305 & _T_346; // @[exu_div_ctl.scala 823:67] + wire _T_348 = _T_343 | _T_347; // @[exu_div_ctl.scala 823:43] + wire [37:0] adder9_out = _T_291 + b_ff; // @[exu_div_ctl.scala 809:94] + wire _T_350 = ~adder9_out[37]; // @[exu_div_ctl.scala 824:6] + wire _T_351 = _T_350 ^ control_ff[2]; // @[exu_div_ctl.scala 824:22] + wire _T_354 = adder9_out == 38'h0; // @[exu_div_ctl.scala 824:80] + wire _T_355 = _T_305 & _T_354; // @[exu_div_ctl.scala 824:66] + wire _T_356 = _T_351 | _T_355; // @[exu_div_ctl.scala 824:42] + wire _T_358 = ~_T_291[37]; // @[exu_div_ctl.scala 825:6] + wire _T_359 = _T_358 ^ control_ff[2]; // @[exu_div_ctl.scala 825:22] + wire _T_362 = _T_291 == 38'h0; // @[exu_div_ctl.scala 825:80] + wire _T_363 = _T_305 & _T_362; // @[exu_div_ctl.scala 825:66] + wire _T_364 = _T_359 | _T_363; // @[exu_div_ctl.scala 825:42] + wire [37:0] _T_191 = _T_287 + _T_293; // @[exu_div_ctl.scala 807:67] + wire [37:0] _T_195 = _T_191 + _T_297; // @[exu_div_ctl.scala 807:94] + wire [37:0] adder7_out = _T_195 + b_ff; // @[exu_div_ctl.scala 807:116] + wire _T_366 = ~adder7_out[37]; // @[exu_div_ctl.scala 826:6] + wire _T_367 = _T_366 ^ control_ff[2]; // @[exu_div_ctl.scala 826:22] + wire _T_370 = adder7_out == 38'h0; // @[exu_div_ctl.scala 826:80] + wire _T_371 = _T_305 & _T_370; // @[exu_div_ctl.scala 826:66] + wire _T_372 = _T_367 | _T_371; // @[exu_div_ctl.scala 826:42] + wire _T_374 = ~_T_195[37]; // @[exu_div_ctl.scala 827:6] + wire _T_375 = _T_374 ^ control_ff[2]; // @[exu_div_ctl.scala 827:22] + wire _T_378 = _T_195 == 38'h0; // @[exu_div_ctl.scala 827:80] + wire _T_379 = _T_305 & _T_378; // @[exu_div_ctl.scala 827:66] + wire _T_380 = _T_375 | _T_379; // @[exu_div_ctl.scala 827:42] + wire [37:0] adder5_out = _T_191 + b_ff; // @[exu_div_ctl.scala 805:94] + wire _T_382 = ~adder5_out[37]; // @[exu_div_ctl.scala 828:6] + wire _T_383 = _T_382 ^ control_ff[2]; // @[exu_div_ctl.scala 828:22] + wire _T_386 = adder5_out == 38'h0; // @[exu_div_ctl.scala 828:80] + wire _T_387 = _T_305 & _T_386; // @[exu_div_ctl.scala 828:66] + wire _T_388 = _T_383 | _T_387; // @[exu_div_ctl.scala 828:42] + wire _T_390 = ~_T_191[37]; // @[exu_div_ctl.scala 829:6] + wire _T_391 = _T_390 ^ control_ff[2]; // @[exu_div_ctl.scala 829:22] + wire _T_394 = _T_191 == 38'h0; // @[exu_div_ctl.scala 829:80] + wire _T_395 = _T_305 & _T_394; // @[exu_div_ctl.scala 829:66] + wire _T_396 = _T_391 | _T_395; // @[exu_div_ctl.scala 829:42] wire [36:0] _T_146 = {r_ff,a_ff[31:28]}; // @[Cat.scala 29:58] wire [36:0] _T_148 = {b_ff[35:0],1'h0}; // @[Cat.scala 29:58] - wire [36:0] _T_150 = _T_146 + _T_148; // @[exu_div_ctl.scala 804:48] - wire [36:0] adder3_out = _T_150 + b_ff[36:0]; // @[exu_div_ctl.scala 804:70] - wire _T_398 = ~adder3_out[36]; // @[exu_div_ctl.scala 831:6] - wire _T_399 = _T_398 ^ control_ff[2]; // @[exu_div_ctl.scala 831:22] - wire _T_402 = adder3_out == 37'h0; // @[exu_div_ctl.scala 831:80] - wire _T_403 = _T_305 & _T_402; // @[exu_div_ctl.scala 831:66] - wire _T_404 = _T_399 | _T_403; // @[exu_div_ctl.scala 831:42] + wire [36:0] _T_150 = _T_146 + _T_148; // @[exu_div_ctl.scala 803:58] + wire [36:0] adder3_out = _T_150 + b_ff[36:0]; // @[exu_div_ctl.scala 803:80] + wire _T_398 = ~adder3_out[36]; // @[exu_div_ctl.scala 830:6] + wire _T_399 = _T_398 ^ control_ff[2]; // @[exu_div_ctl.scala 830:22] + wire _T_402 = adder3_out == 37'h0; // @[exu_div_ctl.scala 830:80] + wire _T_403 = _T_305 & _T_402; // @[exu_div_ctl.scala 830:66] + wire _T_404 = _T_399 | _T_403; // @[exu_div_ctl.scala 830:42] wire [35:0] _T_140 = {r_ff[31:0],a_ff[31:28]}; // @[Cat.scala 29:58] wire [35:0] _T_142 = {b_ff[34:0],1'h0}; // @[Cat.scala 29:58] - wire [35:0] adder2_out = _T_140 + _T_142; // @[exu_div_ctl.scala 803:48] - wire _T_406 = ~adder2_out[35]; // @[exu_div_ctl.scala 832:6] - wire _T_407 = _T_406 ^ control_ff[2]; // @[exu_div_ctl.scala 832:22] - wire _T_410 = adder2_out == 36'h0; // @[exu_div_ctl.scala 832:80] - wire _T_411 = _T_305 & _T_410; // @[exu_div_ctl.scala 832:66] - wire _T_412 = _T_407 | _T_411; // @[exu_div_ctl.scala 832:42] + wire [35:0] adder2_out = _T_140 + _T_142; // @[exu_div_ctl.scala 802:58] + wire _T_406 = ~adder2_out[35]; // @[exu_div_ctl.scala 831:6] + wire _T_407 = _T_406 ^ control_ff[2]; // @[exu_div_ctl.scala 831:22] + wire _T_410 = adder2_out == 36'h0; // @[exu_div_ctl.scala 831:80] + wire _T_411 = _T_305 & _T_410; // @[exu_div_ctl.scala 831:66] + wire _T_412 = _T_407 | _T_411; // @[exu_div_ctl.scala 831:42] wire [34:0] _T_135 = {r_ff[30:0],a_ff[31:28]}; // @[Cat.scala 29:58] - wire [34:0] adder1_out = _T_135 + b_ff[34:0]; // @[exu_div_ctl.scala 802:48] - wire _T_414 = ~adder1_out[34]; // @[exu_div_ctl.scala 833:6] - wire _T_415 = _T_414 ^ control_ff[2]; // @[exu_div_ctl.scala 833:22] - wire _T_418 = adder1_out == 35'h0; // @[exu_div_ctl.scala 833:80] - wire _T_419 = _T_305 & _T_418; // @[exu_div_ctl.scala 833:66] - wire _T_420 = _T_415 | _T_419; // @[exu_div_ctl.scala 833:42] + wire [34:0] adder1_out = _T_135 + b_ff[34:0]; // @[exu_div_ctl.scala 801:58] + wire _T_414 = ~adder1_out[34]; // @[exu_div_ctl.scala 832:6] + wire _T_415 = _T_414 ^ control_ff[2]; // @[exu_div_ctl.scala 832:22] + wire _T_418 = adder1_out == 35'h0; // @[exu_div_ctl.scala 832:80] + wire _T_419 = _T_305 & _T_418; // @[exu_div_ctl.scala 832:66] + wire _T_420 = _T_415 | _T_419; // @[exu_div_ctl.scala 832:42] wire [7:0] _T_427 = {_T_372,_T_380,_T_388,_T_396,_T_404,_T_412,_T_420,1'h0}; // @[Cat.scala 29:58] wire [15:0] quotient_raw = {_T_308,_T_316,_T_324,_T_332,_T_340,_T_348,_T_356,_T_364,_T_427}; // @[Cat.scala 29:58] - wire _T_439 = quotient_raw[15:8] == 8'h1; // @[exu_div_ctl.scala 836:49] - wire _T_444 = quotient_raw[15:9] == 7'h1; // @[exu_div_ctl.scala 836:49] + wire _T_439 = quotient_raw[15:8] == 8'h1; // @[exu_div_ctl.scala 835:49] + wire _T_444 = quotient_raw[15:9] == 7'h1; // @[exu_div_ctl.scala 835:49] wire _T_477 = _T_439 | _T_444; // @[Mux.scala 27:72] - wire _T_449 = quotient_raw[15:10] == 6'h1; // @[exu_div_ctl.scala 836:49] + wire _T_449 = quotient_raw[15:10] == 6'h1; // @[exu_div_ctl.scala 835:49] wire _T_478 = _T_477 | _T_449; // @[Mux.scala 27:72] - wire _T_454 = quotient_raw[15:11] == 5'h1; // @[exu_div_ctl.scala 836:49] + wire _T_454 = quotient_raw[15:11] == 5'h1; // @[exu_div_ctl.scala 835:49] wire _T_479 = _T_478 | _T_454; // @[Mux.scala 27:72] - wire _T_459 = quotient_raw[15:12] == 4'h1; // @[exu_div_ctl.scala 836:49] + wire _T_459 = quotient_raw[15:12] == 4'h1; // @[exu_div_ctl.scala 835:49] wire _T_480 = _T_479 | _T_459; // @[Mux.scala 27:72] - wire _T_464 = quotient_raw[15:13] == 3'h1; // @[exu_div_ctl.scala 836:49] + wire _T_464 = quotient_raw[15:13] == 3'h1; // @[exu_div_ctl.scala 835:49] wire _T_481 = _T_480 | _T_464; // @[Mux.scala 27:72] - wire _T_468 = quotient_raw[15:14] == 2'h1; // @[exu_div_ctl.scala 836:49] + wire _T_468 = quotient_raw[15:14] == 2'h1; // @[exu_div_ctl.scala 835:49] wire _T_482 = _T_481 | _T_468; // @[Mux.scala 27:72] - wire _T_486 = _T_482 | quotient_raw[15]; // @[exu_div_ctl.scala 836:94] - wire _T_488 = quotient_raw[15:4] == 12'h1; // @[exu_div_ctl.scala 838:26] - wire _T_490 = quotient_raw[15:5] == 11'h1; // @[exu_div_ctl.scala 838:77] - wire _T_491 = _T_488 | _T_490; // @[exu_div_ctl.scala 838:54] - wire _T_493 = quotient_raw[15:6] == 10'h1; // @[exu_div_ctl.scala 838:128] - wire _T_494 = _T_491 | _T_493; // @[exu_div_ctl.scala 838:105] - wire _T_496 = quotient_raw[15:7] == 9'h1; // @[exu_div_ctl.scala 839:28] - wire _T_497 = _T_494 | _T_496; // @[exu_div_ctl.scala 838:155] - wire _T_500 = _T_497 | _T_459; // @[exu_div_ctl.scala 839:53] - wire _T_503 = _T_500 | _T_464; // @[exu_div_ctl.scala 839:96] - wire _T_506 = _T_503 | _T_468; // @[exu_div_ctl.scala 839:138] - wire _T_509 = _T_506 | quotient_raw[15]; // @[exu_div_ctl.scala 840:46] - wire _T_511 = quotient_raw[15:2] == 14'h1; // @[exu_div_ctl.scala 842:26] - wire _T_513 = quotient_raw[15:3] == 13'h1; // @[exu_div_ctl.scala 842:79] - wire _T_514 = _T_511 | _T_513; // @[exu_div_ctl.scala 842:56] - wire _T_517 = _T_514 | _T_493; // @[exu_div_ctl.scala 842:109] - wire _T_520 = _T_517 | _T_496; // @[exu_div_ctl.scala 842:159] - wire _T_523 = _T_520 | _T_449; // @[exu_div_ctl.scala 843:55] - wire _T_526 = _T_523 | _T_454; // @[exu_div_ctl.scala 843:100] - wire _T_529 = _T_526 | _T_468; // @[exu_div_ctl.scala 843:144] - wire _T_532 = _T_529 | quotient_raw[15]; // @[exu_div_ctl.scala 844:48] - wire _T_536 = quotient_raw[15:1] == 15'h1; // @[exu_div_ctl.scala 846:54] - wire _T_575 = _T_536 | _T_513; // @[Mux.scala 27:72] - wire _T_576 = _T_575 | _T_490; // @[Mux.scala 27:72] - wire _T_577 = _T_576 | _T_496; // @[Mux.scala 27:72] - wire _T_578 = _T_577 | _T_444; // @[Mux.scala 27:72] - wire _T_579 = _T_578 | _T_454; // @[Mux.scala 27:72] - wire _T_580 = _T_579 | _T_464; // @[Mux.scala 27:72] - wire _T_584 = _T_580 | quotient_raw[15]; // @[exu_div_ctl.scala 846:99] - wire [3:0] quotient_new = {_T_486,_T_509,_T_532,_T_584}; // @[Cat.scala 29:58] - wire _T_85 = quotient_new == 4'h0; // @[exu_div_ctl.scala 801:71] - wire _T_86 = running_state & _T_85; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_0 = _T_86 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_88 = quotient_new == 4'h1; // @[exu_div_ctl.scala 801:71] - wire _T_89 = running_state & _T_88; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_1 = _T_89 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_91 = quotient_new == 4'h2; // @[exu_div_ctl.scala 801:71] - wire _T_92 = running_state & _T_91; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_2 = _T_92 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_94 = quotient_new == 4'h3; // @[exu_div_ctl.scala 801:71] - wire _T_95 = running_state & _T_94; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_3 = _T_95 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_97 = quotient_new == 4'h4; // @[exu_div_ctl.scala 801:71] - wire _T_98 = running_state & _T_97; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_4 = _T_98 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_100 = quotient_new == 4'h5; // @[exu_div_ctl.scala 801:71] - wire _T_101 = running_state & _T_100; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_5 = _T_101 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_103 = quotient_new == 4'h6; // @[exu_div_ctl.scala 801:71] - wire _T_104 = running_state & _T_103; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_6 = _T_104 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_106 = quotient_new == 4'h7; // @[exu_div_ctl.scala 801:71] - wire _T_107 = running_state & _T_106; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_7 = _T_107 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_109 = quotient_new == 4'h8; // @[exu_div_ctl.scala 801:71] - wire _T_110 = running_state & _T_109; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_8 = _T_110 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_112 = quotient_new == 4'h9; // @[exu_div_ctl.scala 801:71] - wire _T_113 = running_state & _T_112; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_9 = _T_113 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_115 = quotient_new == 4'ha; // @[exu_div_ctl.scala 801:71] - wire _T_116 = running_state & _T_115; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_10 = _T_116 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_118 = quotient_new == 4'hb; // @[exu_div_ctl.scala 801:71] - wire _T_119 = running_state & _T_118; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_11 = _T_119 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_121 = quotient_new == 4'hc; // @[exu_div_ctl.scala 801:71] - wire _T_122 = running_state & _T_121; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_12 = _T_122 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_124 = quotient_new == 4'hd; // @[exu_div_ctl.scala 801:71] - wire _T_125 = running_state & _T_124; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_13 = _T_125 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_127 = quotient_new == 4'he; // @[exu_div_ctl.scala 801:71] - wire _T_128 = running_state & _T_127; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_14 = _T_128 & _T_66; // @[exu_div_ctl.scala 801:85] - wire _T_130 = quotient_new == 4'hf; // @[exu_div_ctl.scala 801:71] - wire _T_131 = running_state & _T_130; // @[exu_div_ctl.scala 801:55] - wire r_adder_sel_15 = _T_131 & _T_66; // @[exu_div_ctl.scala 801:85] + wire _T_486 = _T_482 | quotient_raw[15]; // @[exu_div_ctl.scala 835:94] + wire _T_488 = quotient_raw[15:4] == 12'h1; // @[exu_div_ctl.scala 836:40] + wire _T_490 = quotient_raw[15:5] == 11'h1; // @[exu_div_ctl.scala 836:98] + wire _T_511 = _T_488 | _T_490; // @[Mux.scala 27:72] + wire _T_492 = quotient_raw[15:6] == 10'h1; // @[exu_div_ctl.scala 836:155] + wire _T_512 = _T_511 | _T_492; // @[Mux.scala 27:72] + wire _T_494 = quotient_raw[15:7] == 9'h1; // @[exu_div_ctl.scala 836:211] + wire _T_513 = _T_512 | _T_494; // @[Mux.scala 27:72] + wire _T_514 = _T_513 | _T_459; // @[Mux.scala 27:72] + wire _T_515 = _T_514 | _T_464; // @[Mux.scala 27:72] + wire _T_516 = _T_515 | _T_468; // @[Mux.scala 27:72] + wire _T_517 = _T_516 | quotient_raw[15]; // @[Mux.scala 27:72] + wire _T_520 = quotient_raw[15:2] == 14'h1; // @[exu_div_ctl.scala 838:37] + wire _T_522 = quotient_raw[15:3] == 13'h1; // @[exu_div_ctl.scala 838:97] + wire _T_543 = _T_520 | _T_522; // @[Mux.scala 27:72] + wire _T_544 = _T_543 | _T_492; // @[Mux.scala 27:72] + wire _T_545 = _T_544 | _T_494; // @[Mux.scala 27:72] + wire _T_546 = _T_545 | _T_449; // @[Mux.scala 27:72] + wire _T_547 = _T_546 | _T_454; // @[Mux.scala 27:72] + wire _T_548 = _T_547 | _T_468; // @[Mux.scala 27:72] + wire _T_549 = _T_548 | quotient_raw[15]; // @[Mux.scala 27:72] + wire _T_554 = quotient_raw[15:1] == 15'h1; // @[exu_div_ctl.scala 840:54] + wire _T_593 = _T_554 | _T_522; // @[Mux.scala 27:72] + wire _T_594 = _T_593 | _T_490; // @[Mux.scala 27:72] + wire _T_595 = _T_594 | _T_494; // @[Mux.scala 27:72] + wire _T_596 = _T_595 | _T_444; // @[Mux.scala 27:72] + wire _T_597 = _T_596 | _T_454; // @[Mux.scala 27:72] + wire _T_598 = _T_597 | _T_464; // @[Mux.scala 27:72] + wire _T_602 = _T_598 | quotient_raw[15]; // @[exu_div_ctl.scala 840:99] + wire [3:0] quotient_new = {_T_486,_T_517,_T_549,_T_602}; // @[Cat.scala 29:58] + wire _T_85 = quotient_new == 4'h0; // @[exu_div_ctl.scala 800:80] + wire _T_86 = running_state & _T_85; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_0 = _T_86 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_88 = quotient_new == 4'h1; // @[exu_div_ctl.scala 800:80] + wire _T_89 = running_state & _T_88; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_1 = _T_89 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_91 = quotient_new == 4'h2; // @[exu_div_ctl.scala 800:80] + wire _T_92 = running_state & _T_91; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_2 = _T_92 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_94 = quotient_new == 4'h3; // @[exu_div_ctl.scala 800:80] + wire _T_95 = running_state & _T_94; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_3 = _T_95 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_97 = quotient_new == 4'h4; // @[exu_div_ctl.scala 800:80] + wire _T_98 = running_state & _T_97; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_4 = _T_98 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_100 = quotient_new == 4'h5; // @[exu_div_ctl.scala 800:80] + wire _T_101 = running_state & _T_100; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_5 = _T_101 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_103 = quotient_new == 4'h6; // @[exu_div_ctl.scala 800:80] + wire _T_104 = running_state & _T_103; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_6 = _T_104 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_106 = quotient_new == 4'h7; // @[exu_div_ctl.scala 800:80] + wire _T_107 = running_state & _T_106; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_7 = _T_107 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_109 = quotient_new == 4'h8; // @[exu_div_ctl.scala 800:80] + wire _T_110 = running_state & _T_109; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_8 = _T_110 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_112 = quotient_new == 4'h9; // @[exu_div_ctl.scala 800:80] + wire _T_113 = running_state & _T_112; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_9 = _T_113 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_115 = quotient_new == 4'ha; // @[exu_div_ctl.scala 800:80] + wire _T_116 = running_state & _T_115; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_10 = _T_116 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_118 = quotient_new == 4'hb; // @[exu_div_ctl.scala 800:80] + wire _T_119 = running_state & _T_118; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_11 = _T_119 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_121 = quotient_new == 4'hc; // @[exu_div_ctl.scala 800:80] + wire _T_122 = running_state & _T_121; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_12 = _T_122 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_124 = quotient_new == 4'hd; // @[exu_div_ctl.scala 800:80] + wire _T_125 = running_state & _T_124; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_13 = _T_125 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_127 = quotient_new == 4'he; // @[exu_div_ctl.scala 800:80] + wire _T_128 = running_state & _T_127; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_14 = _T_128 & _T_66; // @[exu_div_ctl.scala 800:94] + wire _T_130 = quotient_new == 4'hf; // @[exu_div_ctl.scala 800:80] + wire _T_131 = running_state & _T_130; // @[exu_div_ctl.scala 800:64] + wire r_adder_sel_15 = _T_131 & _T_66; // @[exu_div_ctl.scala 800:94] reg [31:0] q_ff; // @[Reg.scala 27:20] - wire [31:0] _T_589 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_590 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] twos_comp_in = _T_589 | _T_590; // @[Mux.scala 27:72] - wire _T_594 = |twos_comp_in[0]; // @[lib.scala 428:35] - wire _T_596 = ~twos_comp_in[1]; // @[lib.scala 428:40] - wire _T_598 = _T_594 ? _T_596 : twos_comp_in[1]; // @[lib.scala 428:23] - wire _T_600 = |twos_comp_in[1:0]; // @[lib.scala 428:35] - wire _T_602 = ~twos_comp_in[2]; // @[lib.scala 428:40] - wire _T_604 = _T_600 ? _T_602 : twos_comp_in[2]; // @[lib.scala 428:23] - wire _T_606 = |twos_comp_in[2:0]; // @[lib.scala 428:35] - wire _T_608 = ~twos_comp_in[3]; // @[lib.scala 428:40] - wire _T_610 = _T_606 ? _T_608 : twos_comp_in[3]; // @[lib.scala 428:23] - wire _T_612 = |twos_comp_in[3:0]; // @[lib.scala 428:35] - wire _T_614 = ~twos_comp_in[4]; // @[lib.scala 428:40] - wire _T_616 = _T_612 ? _T_614 : twos_comp_in[4]; // @[lib.scala 428:23] - wire _T_618 = |twos_comp_in[4:0]; // @[lib.scala 428:35] - wire _T_620 = ~twos_comp_in[5]; // @[lib.scala 428:40] - wire _T_622 = _T_618 ? _T_620 : twos_comp_in[5]; // @[lib.scala 428:23] - wire _T_624 = |twos_comp_in[5:0]; // @[lib.scala 428:35] - wire _T_626 = ~twos_comp_in[6]; // @[lib.scala 428:40] - wire _T_628 = _T_624 ? _T_626 : twos_comp_in[6]; // @[lib.scala 428:23] - wire _T_630 = |twos_comp_in[6:0]; // @[lib.scala 428:35] - wire _T_632 = ~twos_comp_in[7]; // @[lib.scala 428:40] - wire _T_634 = _T_630 ? _T_632 : twos_comp_in[7]; // @[lib.scala 428:23] - wire _T_636 = |twos_comp_in[7:0]; // @[lib.scala 428:35] - wire _T_638 = ~twos_comp_in[8]; // @[lib.scala 428:40] - wire _T_640 = _T_636 ? _T_638 : twos_comp_in[8]; // @[lib.scala 428:23] - wire _T_642 = |twos_comp_in[8:0]; // @[lib.scala 428:35] - wire _T_644 = ~twos_comp_in[9]; // @[lib.scala 428:40] - wire _T_646 = _T_642 ? _T_644 : twos_comp_in[9]; // @[lib.scala 428:23] - wire _T_648 = |twos_comp_in[9:0]; // @[lib.scala 428:35] - wire _T_650 = ~twos_comp_in[10]; // @[lib.scala 428:40] - wire _T_652 = _T_648 ? _T_650 : twos_comp_in[10]; // @[lib.scala 428:23] - wire _T_654 = |twos_comp_in[10:0]; // @[lib.scala 428:35] - wire _T_656 = ~twos_comp_in[11]; // @[lib.scala 428:40] - wire _T_658 = _T_654 ? _T_656 : twos_comp_in[11]; // @[lib.scala 428:23] - wire _T_660 = |twos_comp_in[11:0]; // @[lib.scala 428:35] - wire _T_662 = ~twos_comp_in[12]; // @[lib.scala 428:40] - wire _T_664 = _T_660 ? _T_662 : twos_comp_in[12]; // @[lib.scala 428:23] - wire _T_666 = |twos_comp_in[12:0]; // @[lib.scala 428:35] - wire _T_668 = ~twos_comp_in[13]; // @[lib.scala 428:40] - wire _T_670 = _T_666 ? _T_668 : twos_comp_in[13]; // @[lib.scala 428:23] - wire _T_672 = |twos_comp_in[13:0]; // @[lib.scala 428:35] - wire _T_674 = ~twos_comp_in[14]; // @[lib.scala 428:40] - wire _T_676 = _T_672 ? _T_674 : twos_comp_in[14]; // @[lib.scala 428:23] - wire _T_678 = |twos_comp_in[14:0]; // @[lib.scala 428:35] - wire _T_680 = ~twos_comp_in[15]; // @[lib.scala 428:40] - wire _T_682 = _T_678 ? _T_680 : twos_comp_in[15]; // @[lib.scala 428:23] - wire _T_684 = |twos_comp_in[15:0]; // @[lib.scala 428:35] - wire _T_686 = ~twos_comp_in[16]; // @[lib.scala 428:40] - wire _T_688 = _T_684 ? _T_686 : twos_comp_in[16]; // @[lib.scala 428:23] - wire _T_690 = |twos_comp_in[16:0]; // @[lib.scala 428:35] - wire _T_692 = ~twos_comp_in[17]; // @[lib.scala 428:40] - wire _T_694 = _T_690 ? _T_692 : twos_comp_in[17]; // @[lib.scala 428:23] - wire _T_696 = |twos_comp_in[17:0]; // @[lib.scala 428:35] - wire _T_698 = ~twos_comp_in[18]; // @[lib.scala 428:40] - wire _T_700 = _T_696 ? _T_698 : twos_comp_in[18]; // @[lib.scala 428:23] - wire _T_702 = |twos_comp_in[18:0]; // @[lib.scala 428:35] - wire _T_704 = ~twos_comp_in[19]; // @[lib.scala 428:40] - wire _T_706 = _T_702 ? _T_704 : twos_comp_in[19]; // @[lib.scala 428:23] - wire _T_708 = |twos_comp_in[19:0]; // @[lib.scala 428:35] - wire _T_710 = ~twos_comp_in[20]; // @[lib.scala 428:40] - wire _T_712 = _T_708 ? _T_710 : twos_comp_in[20]; // @[lib.scala 428:23] - wire _T_714 = |twos_comp_in[20:0]; // @[lib.scala 428:35] - wire _T_716 = ~twos_comp_in[21]; // @[lib.scala 428:40] - wire _T_718 = _T_714 ? _T_716 : twos_comp_in[21]; // @[lib.scala 428:23] - wire _T_720 = |twos_comp_in[21:0]; // @[lib.scala 428:35] - wire _T_722 = ~twos_comp_in[22]; // @[lib.scala 428:40] - wire _T_724 = _T_720 ? _T_722 : twos_comp_in[22]; // @[lib.scala 428:23] - wire _T_726 = |twos_comp_in[22:0]; // @[lib.scala 428:35] - wire _T_728 = ~twos_comp_in[23]; // @[lib.scala 428:40] - wire _T_730 = _T_726 ? _T_728 : twos_comp_in[23]; // @[lib.scala 428:23] - wire _T_732 = |twos_comp_in[23:0]; // @[lib.scala 428:35] - wire _T_734 = ~twos_comp_in[24]; // @[lib.scala 428:40] - wire _T_736 = _T_732 ? _T_734 : twos_comp_in[24]; // @[lib.scala 428:23] - wire _T_738 = |twos_comp_in[24:0]; // @[lib.scala 428:35] - wire _T_740 = ~twos_comp_in[25]; // @[lib.scala 428:40] - wire _T_742 = _T_738 ? _T_740 : twos_comp_in[25]; // @[lib.scala 428:23] - wire _T_744 = |twos_comp_in[25:0]; // @[lib.scala 428:35] - wire _T_746 = ~twos_comp_in[26]; // @[lib.scala 428:40] - wire _T_748 = _T_744 ? _T_746 : twos_comp_in[26]; // @[lib.scala 428:23] - wire _T_750 = |twos_comp_in[26:0]; // @[lib.scala 428:35] - wire _T_752 = ~twos_comp_in[27]; // @[lib.scala 428:40] - wire _T_754 = _T_750 ? _T_752 : twos_comp_in[27]; // @[lib.scala 428:23] - wire _T_756 = |twos_comp_in[27:0]; // @[lib.scala 428:35] - wire _T_758 = ~twos_comp_in[28]; // @[lib.scala 428:40] - wire _T_760 = _T_756 ? _T_758 : twos_comp_in[28]; // @[lib.scala 428:23] - wire _T_762 = |twos_comp_in[28:0]; // @[lib.scala 428:35] - wire _T_764 = ~twos_comp_in[29]; // @[lib.scala 428:40] - wire _T_766 = _T_762 ? _T_764 : twos_comp_in[29]; // @[lib.scala 428:23] - wire _T_768 = |twos_comp_in[29:0]; // @[lib.scala 428:35] - wire _T_770 = ~twos_comp_in[30]; // @[lib.scala 428:40] - wire _T_772 = _T_768 ? _T_770 : twos_comp_in[30]; // @[lib.scala 428:23] - wire _T_774 = |twos_comp_in[30:0]; // @[lib.scala 428:35] - wire _T_776 = ~twos_comp_in[31]; // @[lib.scala 428:40] - wire _T_778 = _T_774 ? _T_776 : twos_comp_in[31]; // @[lib.scala 428:23] - wire [6:0] _T_784 = {_T_634,_T_628,_T_622,_T_616,_T_610,_T_604,_T_598}; // @[lib.scala 430:14] - wire [14:0] _T_792 = {_T_682,_T_676,_T_670,_T_664,_T_658,_T_652,_T_646,_T_640,_T_784}; // @[lib.scala 430:14] - wire [7:0] _T_799 = {_T_730,_T_724,_T_718,_T_712,_T_706,_T_700,_T_694,_T_688}; // @[lib.scala 430:14] - wire [30:0] _T_808 = {_T_778,_T_772,_T_766,_T_760,_T_754,_T_748,_T_742,_T_736,_T_799,_T_792}; // @[lib.scala 430:14] - wire [31:0] twos_comp_out = {_T_808,twos_comp_in[0]}; // @[Cat.scala 29:58] - wire _T_810 = ~a_shift; // @[exu_div_ctl.scala 853:6] - wire _T_812 = _T_810 & _T_66; // @[exu_div_ctl.scala 853:15] - wire [31:0] _T_816 = {a_ff[27:0],4'h0}; // @[Cat.scala 29:58] - wire [64:0] ar_shifted = _T_71[64:0]; // @[exu_div_ctl.scala 794:28] - wire [31:0] _T_818 = _T_812 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_819 = a_shift ? _T_816 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_820 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_821 = _T_818 | _T_819; // @[Mux.scala 27:72] - wire [31:0] a_in = _T_821 | _T_820; // @[Mux.scala 27:72] - wire _T_823 = ~b_twos_comp; // @[exu_div_ctl.scala 858:5] - wire _T_825 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 858:63] - wire [32:0] _T_827 = {_T_825,io_divisor_in}; // @[Cat.scala 29:58] - wire _T_828 = ~control_ff[1]; // @[exu_div_ctl.scala 859:49] - wire [32:0] _T_830 = {_T_828,_T_808,twos_comp_in[0]}; // @[Cat.scala 29:58] - wire [32:0] _T_831 = _T_823 ? _T_827 : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_832 = b_twos_comp ? _T_830 : 33'h0; // @[Mux.scala 27:72] - wire [32:0] b_in = _T_831 | _T_832; // @[Mux.scala 27:72] - wire [32:0] _T_837 = {r_ff[28:0],a_ff[31:28]}; // @[Cat.scala 29:58] - wire [32:0] _T_855 = {1'h0,a_ff}; // @[Cat.scala 29:58] - wire [32:0] _T_856 = r_sign_sel ? 33'h1ffffffff : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_857 = r_adder_sel_0 ? _T_837 : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_858 = r_adder_sel_1 ? adder1_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_859 = r_adder_sel_2 ? adder2_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_860 = r_adder_sel_3 ? adder3_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_861 = r_adder_sel_4 ? _T_191[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_862 = r_adder_sel_5 ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_863 = r_adder_sel_6 ? _T_195[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_864 = r_adder_sel_7 ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_865 = r_adder_sel_8 ? _T_291[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_866 = r_adder_sel_9 ? adder9_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_867 = r_adder_sel_10 ? _T_239[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_868 = r_adder_sel_11 ? adder11_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_869 = r_adder_sel_12 ? _T_295[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_870 = r_adder_sel_13 ? adder13_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_871 = r_adder_sel_14 ? _T_299[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_872 = r_adder_sel_15 ? adder15_out[32:0] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_873 = shortq_enable_ff ? ar_shifted[64:32] : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_874 = by_zero_case ? _T_855 : 33'h0; // @[Mux.scala 27:72] - wire [32:0] _T_875 = _T_856 | _T_857; // @[Mux.scala 27:72] - wire [32:0] _T_876 = _T_875 | _T_858; // @[Mux.scala 27:72] - wire [32:0] _T_877 = _T_876 | _T_859; // @[Mux.scala 27:72] - wire [32:0] _T_878 = _T_877 | _T_860; // @[Mux.scala 27:72] - wire [32:0] _T_879 = _T_878 | _T_861; // @[Mux.scala 27:72] - wire [32:0] _T_880 = _T_879 | _T_862; // @[Mux.scala 27:72] - wire [32:0] _T_881 = _T_880 | _T_863; // @[Mux.scala 27:72] - wire [32:0] _T_882 = _T_881 | _T_864; // @[Mux.scala 27:72] - wire [32:0] _T_883 = _T_882 | _T_865; // @[Mux.scala 27:72] - wire [32:0] _T_884 = _T_883 | _T_866; // @[Mux.scala 27:72] - wire [32:0] _T_885 = _T_884 | _T_867; // @[Mux.scala 27:72] - wire [32:0] _T_886 = _T_885 | _T_868; // @[Mux.scala 27:72] - wire [32:0] _T_887 = _T_886 | _T_869; // @[Mux.scala 27:72] - wire [32:0] _T_888 = _T_887 | _T_870; // @[Mux.scala 27:72] - wire [32:0] _T_889 = _T_888 | _T_871; // @[Mux.scala 27:72] - wire [32:0] _T_890 = _T_889 | _T_872; // @[Mux.scala 27:72] - wire [32:0] _T_891 = _T_890 | _T_873; // @[Mux.scala 27:72] - wire [32:0] r_in = _T_891 | _T_874; // @[Mux.scala 27:72] - wire [31:0] _T_895 = {q_ff[27:0],_T_486,_T_509,_T_532,_T_584}; // @[Cat.scala 29:58] - wire _T_918 = ~b_ff[3]; // @[exu_div_ctl.scala 895:70] - wire _T_920 = ~b_ff[2]; // @[exu_div_ctl.scala 895:70] - wire _T_923 = _T_918 & _T_920; // @[exu_div_ctl.scala 895:95] - wire _T_922 = ~b_ff[1]; // @[exu_div_ctl.scala 895:70] - wire _T_924 = _T_923 & _T_922; // @[exu_div_ctl.scala 895:95] - wire _T_925 = a_ff[3] & _T_924; // @[exu_div_ctl.scala 896:11] - wire _T_932 = a_ff[3] & _T_923; // @[exu_div_ctl.scala 896:11] - wire _T_934 = ~b_ff[0]; // @[exu_div_ctl.scala 901:33] - wire _T_935 = _T_932 & _T_934; // @[exu_div_ctl.scala 901:31] - wire _T_945 = a_ff[2] & _T_924; // @[exu_div_ctl.scala 896:11] - wire _T_946 = _T_935 | _T_945; // @[exu_div_ctl.scala 901:42] - wire _T_949 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 894:95] - wire _T_955 = _T_949 & _T_923; // @[exu_div_ctl.scala 896:11] - wire _T_956 = _T_946 | _T_955; // @[exu_div_ctl.scala 901:75] - wire _T_963 = a_ff[2] & _T_923; // @[exu_div_ctl.scala 896:11] - wire _T_966 = _T_963 & _T_934; // @[exu_div_ctl.scala 903:31] - wire _T_976 = a_ff[1] & _T_924; // @[exu_div_ctl.scala 896:11] - wire _T_977 = _T_966 | _T_976; // @[exu_div_ctl.scala 903:42] - wire _T_983 = _T_918 & _T_922; // @[exu_div_ctl.scala 895:95] - wire _T_984 = a_ff[3] & _T_983; // @[exu_div_ctl.scala 896:11] - wire _T_987 = _T_984 & _T_934; // @[exu_div_ctl.scala 903:106] - wire _T_988 = _T_977 | _T_987; // @[exu_div_ctl.scala 903:78] - wire _T_991 = ~a_ff[2]; // @[exu_div_ctl.scala 894:70] - wire _T_992 = a_ff[3] & _T_991; // @[exu_div_ctl.scala 894:95] - wire _T_1000 = _T_923 & b_ff[1]; // @[exu_div_ctl.scala 895:95] - wire _T_1001 = _T_1000 & b_ff[0]; // @[exu_div_ctl.scala 895:95] - wire _T_1002 = _T_992 & _T_1001; // @[exu_div_ctl.scala 896:11] - wire _T_1003 = _T_988 | _T_1002; // @[exu_div_ctl.scala 903:117] - wire _T_1005 = ~a_ff[3]; // @[exu_div_ctl.scala 894:70] - wire _T_1008 = _T_1005 & a_ff[2]; // @[exu_div_ctl.scala 894:95] - wire _T_1009 = _T_1008 & a_ff[1]; // @[exu_div_ctl.scala 894:95] - wire _T_1015 = _T_1009 & _T_923; // @[exu_div_ctl.scala 896:11] - wire _T_1016 = _T_1003 | _T_1015; // @[exu_div_ctl.scala 904:44] - wire _T_1022 = _T_949 & _T_918; // @[exu_div_ctl.scala 896:11] - wire _T_1025 = _T_1022 & _T_934; // @[exu_div_ctl.scala 904:107] - wire _T_1026 = _T_1016 | _T_1025; // @[exu_div_ctl.scala 904:80] - wire _T_1035 = _T_918 & b_ff[2]; // @[exu_div_ctl.scala 895:95] - wire _T_1036 = _T_1035 & _T_922; // @[exu_div_ctl.scala 895:95] - wire _T_1037 = _T_949 & _T_1036; // @[exu_div_ctl.scala 896:11] - wire _T_1038 = _T_1026 | _T_1037; // @[exu_div_ctl.scala 904:119] - wire _T_1041 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 894:95] - wire _T_1047 = _T_1041 & _T_983; // @[exu_div_ctl.scala 896:11] - wire _T_1048 = _T_1038 | _T_1047; // @[exu_div_ctl.scala 905:44] - wire _T_1053 = _T_949 & a_ff[1]; // @[exu_div_ctl.scala 894:95] - wire _T_1058 = _T_1053 & _T_1035; // @[exu_div_ctl.scala 896:11] - wire _T_1059 = _T_1048 | _T_1058; // @[exu_div_ctl.scala 905:79] - wire _T_1063 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 894:95] - wire _T_1064 = _T_1063 & a_ff[0]; // @[exu_div_ctl.scala 894:95] - wire _T_1070 = _T_1064 & _T_983; // @[exu_div_ctl.scala 896:11] - wire _T_1076 = _T_992 & a_ff[0]; // @[exu_div_ctl.scala 894:95] - wire _T_1081 = _T_918 & b_ff[1]; // @[exu_div_ctl.scala 895:95] - wire _T_1082 = _T_1081 & b_ff[0]; // @[exu_div_ctl.scala 895:95] - wire _T_1083 = _T_1076 & _T_1082; // @[exu_div_ctl.scala 896:11] - wire _T_1084 = _T_1070 | _T_1083; // @[exu_div_ctl.scala 907:45] - wire _T_1091 = a_ff[2] & _T_983; // @[exu_div_ctl.scala 896:11] - wire _T_1094 = _T_1091 & _T_934; // @[exu_div_ctl.scala 907:114] - wire _T_1095 = _T_1084 | _T_1094; // @[exu_div_ctl.scala 907:86] - wire _T_1102 = a_ff[1] & _T_923; // @[exu_div_ctl.scala 896:11] - wire _T_1105 = _T_1102 & _T_934; // @[exu_div_ctl.scala 908:33] - wire _T_1106 = _T_1095 | _T_1105; // @[exu_div_ctl.scala 907:129] - wire _T_1116 = a_ff[0] & _T_924; // @[exu_div_ctl.scala 896:11] - wire _T_1117 = _T_1106 | _T_1116; // @[exu_div_ctl.scala 908:47] - wire _T_1122 = ~a_ff[1]; // @[exu_div_ctl.scala 894:70] - wire _T_1124 = _T_1008 & _T_1122; // @[exu_div_ctl.scala 894:95] - wire _T_1134 = _T_1124 & _T_1001; // @[exu_div_ctl.scala 896:11] - wire _T_1135 = _T_1117 | _T_1134; // @[exu_div_ctl.scala 908:88] - wire _T_1144 = _T_1009 & _T_918; // @[exu_div_ctl.scala 896:11] - wire _T_1147 = _T_1144 & _T_934; // @[exu_div_ctl.scala 909:36] - wire _T_1148 = _T_1135 | _T_1147; // @[exu_div_ctl.scala 908:131] - wire _T_1154 = _T_920 & _T_922; // @[exu_div_ctl.scala 895:95] - wire _T_1155 = a_ff[3] & _T_1154; // @[exu_div_ctl.scala 896:11] - wire _T_1158 = _T_1155 & _T_934; // @[exu_div_ctl.scala 909:76] - wire _T_1159 = _T_1148 | _T_1158; // @[exu_div_ctl.scala 909:47] - wire _T_1169 = _T_1035 & b_ff[1]; // @[exu_div_ctl.scala 895:95] - wire _T_1170 = _T_992 & _T_1169; // @[exu_div_ctl.scala 896:11] - wire _T_1171 = _T_1159 | _T_1170; // @[exu_div_ctl.scala 909:88] - wire _T_1185 = _T_1009 & _T_1036; // @[exu_div_ctl.scala 896:11] - wire _T_1186 = _T_1171 | _T_1185; // @[exu_div_ctl.scala 909:131] - wire _T_1192 = _T_1008 & a_ff[0]; // @[exu_div_ctl.scala 894:95] - wire _T_1198 = _T_1192 & _T_983; // @[exu_div_ctl.scala 896:11] - wire _T_1199 = _T_1186 | _T_1198; // @[exu_div_ctl.scala 910:47] - wire _T_1206 = _T_992 & _T_1122; // @[exu_div_ctl.scala 894:95] - wire _T_1212 = _T_1035 & b_ff[0]; // @[exu_div_ctl.scala 895:95] - wire _T_1213 = _T_1206 & _T_1212; // @[exu_div_ctl.scala 896:11] - wire _T_1214 = _T_1199 | _T_1213; // @[exu_div_ctl.scala 910:88] - wire _T_1219 = _T_991 & a_ff[1]; // @[exu_div_ctl.scala 894:95] - wire _T_1220 = _T_1219 & a_ff[0]; // @[exu_div_ctl.scala 894:95] - wire _T_1226 = _T_1220 & _T_923; // @[exu_div_ctl.scala 896:11] - wire _T_1227 = _T_1214 | _T_1226; // @[exu_div_ctl.scala 910:131] - wire _T_1233 = _T_949 & _T_922; // @[exu_div_ctl.scala 896:11] - wire _T_1236 = _T_1233 & _T_934; // @[exu_div_ctl.scala 911:75] - wire _T_1237 = _T_1227 | _T_1236; // @[exu_div_ctl.scala 911:47] - wire _T_1245 = _T_1009 & a_ff[0]; // @[exu_div_ctl.scala 894:95] - wire _T_1250 = _T_1245 & _T_1035; // @[exu_div_ctl.scala 896:11] - wire _T_1251 = _T_1237 | _T_1250; // @[exu_div_ctl.scala 911:88] - wire _T_1258 = b_ff[3] & _T_920; // @[exu_div_ctl.scala 895:95] - wire _T_1259 = _T_949 & _T_1258; // @[exu_div_ctl.scala 896:11] - wire _T_1260 = _T_1251 | _T_1259; // @[exu_div_ctl.scala 911:131] - wire _T_1270 = _T_1258 & _T_922; // @[exu_div_ctl.scala 895:95] - wire _T_1271 = _T_1041 & _T_1270; // @[exu_div_ctl.scala 896:11] - wire _T_1272 = _T_1260 | _T_1271; // @[exu_div_ctl.scala 912:47] - wire _T_1275 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 894:95] - wire _T_1281 = _T_1275 & _T_1154; // @[exu_div_ctl.scala 896:11] - wire _T_1282 = _T_1272 | _T_1281; // @[exu_div_ctl.scala 912:88] - wire _T_1286 = a_ff[3] & _T_1122; // @[exu_div_ctl.scala 894:95] - wire _T_1294 = _T_1169 & b_ff[0]; // @[exu_div_ctl.scala 895:95] - wire _T_1295 = _T_1286 & _T_1294; // @[exu_div_ctl.scala 896:11] - wire _T_1296 = _T_1282 | _T_1295; // @[exu_div_ctl.scala 912:131] - wire _T_1303 = _T_1053 & b_ff[3]; // @[exu_div_ctl.scala 896:11] - wire _T_1306 = _T_1303 & _T_934; // @[exu_div_ctl.scala 913:77] - wire _T_1307 = _T_1296 | _T_1306; // @[exu_div_ctl.scala 913:47] - wire _T_1316 = b_ff[3] & _T_922; // @[exu_div_ctl.scala 895:95] - wire _T_1317 = _T_1053 & _T_1316; // @[exu_div_ctl.scala 896:11] - wire _T_1318 = _T_1307 | _T_1317; // @[exu_div_ctl.scala 913:88] - wire _T_1323 = _T_949 & a_ff[0]; // @[exu_div_ctl.scala 894:95] - wire _T_1328 = _T_1323 & _T_1316; // @[exu_div_ctl.scala 896:11] - wire _T_1329 = _T_1318 | _T_1328; // @[exu_div_ctl.scala 913:131] - wire _T_1335 = _T_992 & a_ff[1]; // @[exu_div_ctl.scala 894:95] - wire _T_1340 = _T_1335 & _T_1081; // @[exu_div_ctl.scala 896:11] - wire _T_1341 = _T_1329 | _T_1340; // @[exu_div_ctl.scala 914:47] - wire _T_1346 = _T_1041 & a_ff[0]; // @[exu_div_ctl.scala 894:95] - wire _T_1349 = _T_1346 & _T_920; // @[exu_div_ctl.scala 896:11] - wire _T_1350 = _T_1341 | _T_1349; // @[exu_div_ctl.scala 914:88] - wire _T_1357 = _T_1053 & a_ff[0]; // @[exu_div_ctl.scala 894:95] - wire _T_1359 = _T_1357 & b_ff[3]; // @[exu_div_ctl.scala 896:11] - wire _T_1360 = _T_1350 | _T_1359; // @[exu_div_ctl.scala 914:131] - wire _T_1366 = _T_1041 & _T_920; // @[exu_div_ctl.scala 896:11] - wire _T_1369 = _T_1366 & _T_934; // @[exu_div_ctl.scala 915:74] - wire _T_1370 = _T_1360 | _T_1369; // @[exu_div_ctl.scala 915:47] - wire [31:0] _T_896 = {28'h0,_T_925,_T_956,_T_1059,_T_1370}; // @[Cat.scala 29:58] - wire [31:0] _T_898 = _T_76 ? _T_895 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_899 = smallnum_case ? _T_896 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_900 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_901 = _T_898 | _T_899; // @[Mux.scala 27:72] - wire [31:0] q_in = _T_901 | _T_900; // @[Mux.scala 27:72] - wire _T_906 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 889:16] - wire _T_907 = _T_30 & _T_906; // @[exu_div_ctl.scala 889:14] - wire [31:0] _T_910 = _T_907 ? q_ff : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_911 = control_ff[0] ? r_ff[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_912 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_913 = _T_910 | _T_911; // @[Mux.scala 27:72] - wire _T_1397 = shortq == 6'h1b; // @[exu_div_ctl.scala 931:58] - wire _T_1398 = shortq == 6'h1a; // @[exu_div_ctl.scala 931:58] - wire _T_1399 = shortq == 6'h19; // @[exu_div_ctl.scala 931:58] - wire _T_1400 = shortq == 6'h18; // @[exu_div_ctl.scala 931:58] - wire _T_1401 = shortq == 6'h17; // @[exu_div_ctl.scala 931:58] - wire _T_1402 = shortq == 6'h16; // @[exu_div_ctl.scala 931:58] - wire _T_1403 = shortq == 6'h15; // @[exu_div_ctl.scala 931:58] - wire _T_1404 = shortq == 6'h14; // @[exu_div_ctl.scala 931:58] - wire _T_1405 = shortq == 6'h13; // @[exu_div_ctl.scala 931:58] - wire _T_1406 = shortq == 6'h12; // @[exu_div_ctl.scala 931:58] - wire _T_1407 = shortq == 6'h11; // @[exu_div_ctl.scala 931:58] - wire _T_1408 = shortq == 6'h10; // @[exu_div_ctl.scala 931:58] - wire _T_1409 = shortq == 6'hf; // @[exu_div_ctl.scala 931:58] - wire _T_1410 = shortq == 6'he; // @[exu_div_ctl.scala 931:58] - wire _T_1411 = shortq == 6'hd; // @[exu_div_ctl.scala 931:58] - wire _T_1412 = shortq == 6'hc; // @[exu_div_ctl.scala 931:58] - wire _T_1413 = shortq == 6'hb; // @[exu_div_ctl.scala 931:58] - wire _T_1414 = shortq == 6'ha; // @[exu_div_ctl.scala 931:58] - wire _T_1415 = shortq == 6'h9; // @[exu_div_ctl.scala 931:58] - wire _T_1416 = shortq == 6'h8; // @[exu_div_ctl.scala 931:58] - wire _T_1417 = shortq == 6'h7; // @[exu_div_ctl.scala 931:58] - wire _T_1418 = shortq == 6'h6; // @[exu_div_ctl.scala 931:58] - wire _T_1419 = shortq == 6'h5; // @[exu_div_ctl.scala 931:58] - wire _T_1420 = shortq == 6'h4; // @[exu_div_ctl.scala 931:58] - wire _T_1421 = shortq == 6'h3; // @[exu_div_ctl.scala 931:58] - wire _T_1422 = shortq == 6'h2; // @[exu_div_ctl.scala 931:58] - wire _T_1423 = shortq == 6'h1; // @[exu_div_ctl.scala 931:58] - wire _T_1424 = shortq == 6'h0; // @[exu_div_ctl.scala 931:58] - wire [2:0] _T_1429 = _T_1397 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_1430 = _T_1398 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_1431 = _T_1399 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_1432 = _T_1400 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1433 = _T_1401 ? 4'h8 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1434 = _T_1402 ? 4'h8 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1435 = _T_1403 ? 4'h8 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1436 = _T_1404 ? 4'h8 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1437 = _T_1405 ? 4'hc : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1438 = _T_1406 ? 4'hc : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1439 = _T_1407 ? 4'hc : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_1440 = _T_1408 ? 4'hc : 4'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1441 = _T_1409 ? 5'h10 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1442 = _T_1410 ? 5'h10 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1443 = _T_1411 ? 5'h10 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1444 = _T_1412 ? 5'h10 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1445 = _T_1413 ? 5'h14 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1446 = _T_1414 ? 5'h14 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1447 = _T_1415 ? 5'h14 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1448 = _T_1416 ? 5'h14 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1449 = _T_1417 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1450 = _T_1418 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1451 = _T_1419 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1452 = _T_1420 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1453 = _T_1421 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1454 = _T_1422 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1455 = _T_1423 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] - wire [4:0] _T_1456 = _T_1424 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] - wire [2:0] _T_1461 = _T_1429 | _T_1430; // @[Mux.scala 27:72] - wire [2:0] _T_1462 = _T_1461 | _T_1431; // @[Mux.scala 27:72] - wire [2:0] _T_1463 = _T_1462 | _T_1432; // @[Mux.scala 27:72] - wire [3:0] _GEN_12 = {{1'd0}, _T_1463}; // @[Mux.scala 27:72] - wire [3:0] _T_1464 = _GEN_12 | _T_1433; // @[Mux.scala 27:72] - wire [3:0] _T_1465 = _T_1464 | _T_1434; // @[Mux.scala 27:72] - wire [3:0] _T_1466 = _T_1465 | _T_1435; // @[Mux.scala 27:72] - wire [3:0] _T_1467 = _T_1466 | _T_1436; // @[Mux.scala 27:72] - wire [3:0] _T_1468 = _T_1467 | _T_1437; // @[Mux.scala 27:72] - wire [3:0] _T_1469 = _T_1468 | _T_1438; // @[Mux.scala 27:72] - wire [3:0] _T_1470 = _T_1469 | _T_1439; // @[Mux.scala 27:72] - wire [3:0] _T_1471 = _T_1470 | _T_1440; // @[Mux.scala 27:72] - wire [4:0] _GEN_13 = {{1'd0}, _T_1471}; // @[Mux.scala 27:72] - wire [4:0] _T_1472 = _GEN_13 | _T_1441; // @[Mux.scala 27:72] - wire [4:0] _T_1473 = _T_1472 | _T_1442; // @[Mux.scala 27:72] - wire [4:0] _T_1474 = _T_1473 | _T_1443; // @[Mux.scala 27:72] - wire [4:0] _T_1475 = _T_1474 | _T_1444; // @[Mux.scala 27:72] - wire [4:0] _T_1476 = _T_1475 | _T_1445; // @[Mux.scala 27:72] - wire [4:0] _T_1477 = _T_1476 | _T_1446; // @[Mux.scala 27:72] - wire [4:0] _T_1478 = _T_1477 | _T_1447; // @[Mux.scala 27:72] - wire [4:0] _T_1479 = _T_1478 | _T_1448; // @[Mux.scala 27:72] - wire [4:0] _T_1480 = _T_1479 | _T_1449; // @[Mux.scala 27:72] - wire [4:0] _T_1481 = _T_1480 | _T_1450; // @[Mux.scala 27:72] - wire [4:0] _T_1482 = _T_1481 | _T_1451; // @[Mux.scala 27:72] - wire [4:0] _T_1483 = _T_1482 | _T_1452; // @[Mux.scala 27:72] - wire [4:0] _T_1484 = _T_1483 | _T_1453; // @[Mux.scala 27:72] - wire [4:0] _T_1485 = _T_1484 | _T_1454; // @[Mux.scala 27:72] - wire [4:0] _T_1486 = _T_1485 | _T_1455; // @[Mux.scala 27:72] - wire [4:0] shortq_decode = _T_1486 | _T_1456; // @[Mux.scala 27:72] - exu_div_cls a_enc ( // @[exu_div_ctl.scala 919:21] + wire [31:0] _T_607 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_608 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] twos_comp_in = _T_607 | _T_608; // @[Mux.scala 27:72] + wire _T_612 = |twos_comp_in[0]; // @[lib.scala 428:35] + wire _T_614 = ~twos_comp_in[1]; // @[lib.scala 428:40] + wire _T_616 = _T_612 ? _T_614 : twos_comp_in[1]; // @[lib.scala 428:23] + wire _T_618 = |twos_comp_in[1:0]; // @[lib.scala 428:35] + wire _T_620 = ~twos_comp_in[2]; // @[lib.scala 428:40] + wire _T_622 = _T_618 ? _T_620 : twos_comp_in[2]; // @[lib.scala 428:23] + wire _T_624 = |twos_comp_in[2:0]; // @[lib.scala 428:35] + wire _T_626 = ~twos_comp_in[3]; // @[lib.scala 428:40] + wire _T_628 = _T_624 ? _T_626 : twos_comp_in[3]; // @[lib.scala 428:23] + wire _T_630 = |twos_comp_in[3:0]; // @[lib.scala 428:35] + wire _T_632 = ~twos_comp_in[4]; // @[lib.scala 428:40] + wire _T_634 = _T_630 ? _T_632 : twos_comp_in[4]; // @[lib.scala 428:23] + wire _T_636 = |twos_comp_in[4:0]; // @[lib.scala 428:35] + wire _T_638 = ~twos_comp_in[5]; // @[lib.scala 428:40] + wire _T_640 = _T_636 ? _T_638 : twos_comp_in[5]; // @[lib.scala 428:23] + wire _T_642 = |twos_comp_in[5:0]; // @[lib.scala 428:35] + wire _T_644 = ~twos_comp_in[6]; // @[lib.scala 428:40] + wire _T_646 = _T_642 ? _T_644 : twos_comp_in[6]; // @[lib.scala 428:23] + wire _T_648 = |twos_comp_in[6:0]; // @[lib.scala 428:35] + wire _T_650 = ~twos_comp_in[7]; // @[lib.scala 428:40] + wire _T_652 = _T_648 ? _T_650 : twos_comp_in[7]; // @[lib.scala 428:23] + wire _T_654 = |twos_comp_in[7:0]; // @[lib.scala 428:35] + wire _T_656 = ~twos_comp_in[8]; // @[lib.scala 428:40] + wire _T_658 = _T_654 ? _T_656 : twos_comp_in[8]; // @[lib.scala 428:23] + wire _T_660 = |twos_comp_in[8:0]; // @[lib.scala 428:35] + wire _T_662 = ~twos_comp_in[9]; // @[lib.scala 428:40] + wire _T_664 = _T_660 ? _T_662 : twos_comp_in[9]; // @[lib.scala 428:23] + wire _T_666 = |twos_comp_in[9:0]; // @[lib.scala 428:35] + wire _T_668 = ~twos_comp_in[10]; // @[lib.scala 428:40] + wire _T_670 = _T_666 ? _T_668 : twos_comp_in[10]; // @[lib.scala 428:23] + wire _T_672 = |twos_comp_in[10:0]; // @[lib.scala 428:35] + wire _T_674 = ~twos_comp_in[11]; // @[lib.scala 428:40] + wire _T_676 = _T_672 ? _T_674 : twos_comp_in[11]; // @[lib.scala 428:23] + wire _T_678 = |twos_comp_in[11:0]; // @[lib.scala 428:35] + wire _T_680 = ~twos_comp_in[12]; // @[lib.scala 428:40] + wire _T_682 = _T_678 ? _T_680 : twos_comp_in[12]; // @[lib.scala 428:23] + wire _T_684 = |twos_comp_in[12:0]; // @[lib.scala 428:35] + wire _T_686 = ~twos_comp_in[13]; // @[lib.scala 428:40] + wire _T_688 = _T_684 ? _T_686 : twos_comp_in[13]; // @[lib.scala 428:23] + wire _T_690 = |twos_comp_in[13:0]; // @[lib.scala 428:35] + wire _T_692 = ~twos_comp_in[14]; // @[lib.scala 428:40] + wire _T_694 = _T_690 ? _T_692 : twos_comp_in[14]; // @[lib.scala 428:23] + wire _T_696 = |twos_comp_in[14:0]; // @[lib.scala 428:35] + wire _T_698 = ~twos_comp_in[15]; // @[lib.scala 428:40] + wire _T_700 = _T_696 ? _T_698 : twos_comp_in[15]; // @[lib.scala 428:23] + wire _T_702 = |twos_comp_in[15:0]; // @[lib.scala 428:35] + wire _T_704 = ~twos_comp_in[16]; // @[lib.scala 428:40] + wire _T_706 = _T_702 ? _T_704 : twos_comp_in[16]; // @[lib.scala 428:23] + wire _T_708 = |twos_comp_in[16:0]; // @[lib.scala 428:35] + wire _T_710 = ~twos_comp_in[17]; // @[lib.scala 428:40] + wire _T_712 = _T_708 ? _T_710 : twos_comp_in[17]; // @[lib.scala 428:23] + wire _T_714 = |twos_comp_in[17:0]; // @[lib.scala 428:35] + wire _T_716 = ~twos_comp_in[18]; // @[lib.scala 428:40] + wire _T_718 = _T_714 ? _T_716 : twos_comp_in[18]; // @[lib.scala 428:23] + wire _T_720 = |twos_comp_in[18:0]; // @[lib.scala 428:35] + wire _T_722 = ~twos_comp_in[19]; // @[lib.scala 428:40] + wire _T_724 = _T_720 ? _T_722 : twos_comp_in[19]; // @[lib.scala 428:23] + wire _T_726 = |twos_comp_in[19:0]; // @[lib.scala 428:35] + wire _T_728 = ~twos_comp_in[20]; // @[lib.scala 428:40] + wire _T_730 = _T_726 ? _T_728 : twos_comp_in[20]; // @[lib.scala 428:23] + wire _T_732 = |twos_comp_in[20:0]; // @[lib.scala 428:35] + wire _T_734 = ~twos_comp_in[21]; // @[lib.scala 428:40] + wire _T_736 = _T_732 ? _T_734 : twos_comp_in[21]; // @[lib.scala 428:23] + wire _T_738 = |twos_comp_in[21:0]; // @[lib.scala 428:35] + wire _T_740 = ~twos_comp_in[22]; // @[lib.scala 428:40] + wire _T_742 = _T_738 ? _T_740 : twos_comp_in[22]; // @[lib.scala 428:23] + wire _T_744 = |twos_comp_in[22:0]; // @[lib.scala 428:35] + wire _T_746 = ~twos_comp_in[23]; // @[lib.scala 428:40] + wire _T_748 = _T_744 ? _T_746 : twos_comp_in[23]; // @[lib.scala 428:23] + wire _T_750 = |twos_comp_in[23:0]; // @[lib.scala 428:35] + wire _T_752 = ~twos_comp_in[24]; // @[lib.scala 428:40] + wire _T_754 = _T_750 ? _T_752 : twos_comp_in[24]; // @[lib.scala 428:23] + wire _T_756 = |twos_comp_in[24:0]; // @[lib.scala 428:35] + wire _T_758 = ~twos_comp_in[25]; // @[lib.scala 428:40] + wire _T_760 = _T_756 ? _T_758 : twos_comp_in[25]; // @[lib.scala 428:23] + wire _T_762 = |twos_comp_in[25:0]; // @[lib.scala 428:35] + wire _T_764 = ~twos_comp_in[26]; // @[lib.scala 428:40] + wire _T_766 = _T_762 ? _T_764 : twos_comp_in[26]; // @[lib.scala 428:23] + wire _T_768 = |twos_comp_in[26:0]; // @[lib.scala 428:35] + wire _T_770 = ~twos_comp_in[27]; // @[lib.scala 428:40] + wire _T_772 = _T_768 ? _T_770 : twos_comp_in[27]; // @[lib.scala 428:23] + wire _T_774 = |twos_comp_in[27:0]; // @[lib.scala 428:35] + wire _T_776 = ~twos_comp_in[28]; // @[lib.scala 428:40] + wire _T_778 = _T_774 ? _T_776 : twos_comp_in[28]; // @[lib.scala 428:23] + wire _T_780 = |twos_comp_in[28:0]; // @[lib.scala 428:35] + wire _T_782 = ~twos_comp_in[29]; // @[lib.scala 428:40] + wire _T_784 = _T_780 ? _T_782 : twos_comp_in[29]; // @[lib.scala 428:23] + wire _T_786 = |twos_comp_in[29:0]; // @[lib.scala 428:35] + wire _T_788 = ~twos_comp_in[30]; // @[lib.scala 428:40] + wire _T_790 = _T_786 ? _T_788 : twos_comp_in[30]; // @[lib.scala 428:23] + wire _T_792 = |twos_comp_in[30:0]; // @[lib.scala 428:35] + wire _T_794 = ~twos_comp_in[31]; // @[lib.scala 428:40] + wire _T_796 = _T_792 ? _T_794 : twos_comp_in[31]; // @[lib.scala 428:23] + wire [6:0] _T_802 = {_T_652,_T_646,_T_640,_T_634,_T_628,_T_622,_T_616}; // @[lib.scala 430:14] + wire [14:0] _T_810 = {_T_700,_T_694,_T_688,_T_682,_T_676,_T_670,_T_664,_T_658,_T_802}; // @[lib.scala 430:14] + wire [7:0] _T_817 = {_T_748,_T_742,_T_736,_T_730,_T_724,_T_718,_T_712,_T_706}; // @[lib.scala 430:14] + wire [30:0] _T_826 = {_T_796,_T_790,_T_784,_T_778,_T_772,_T_766,_T_760,_T_754,_T_817,_T_810}; // @[lib.scala 430:14] + wire [31:0] twos_comp_out = {_T_826,twos_comp_in[0]}; // @[Cat.scala 29:58] + wire _T_828 = ~a_shift; // @[exu_div_ctl.scala 847:6] + wire _T_830 = _T_828 & _T_66; // @[exu_div_ctl.scala 847:15] + wire [31:0] _T_834 = {a_ff[27:0],4'h0}; // @[Cat.scala 29:58] + wire [64:0] ar_shifted = _T_71[64:0]; // @[exu_div_ctl.scala 793:28] + wire [31:0] _T_836 = _T_830 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_837 = a_shift ? _T_834 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_838 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_839 = _T_836 | _T_837; // @[Mux.scala 27:72] + wire [31:0] a_in = _T_839 | _T_838; // @[Mux.scala 27:72] + wire _T_841 = ~b_twos_comp; // @[exu_div_ctl.scala 852:5] + wire _T_843 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 852:63] + wire [32:0] _T_845 = {_T_843,io_divisor_in}; // @[Cat.scala 29:58] + wire _T_846 = ~control_ff[1]; // @[exu_div_ctl.scala 853:50] + wire [32:0] _T_848 = {_T_846,_T_826,twos_comp_in[0]}; // @[Cat.scala 29:58] + wire [32:0] _T_849 = _T_841 ? _T_845 : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_850 = b_twos_comp ? _T_848 : 33'h0; // @[Mux.scala 27:72] + wire [32:0] b_in = _T_849 | _T_850; // @[Mux.scala 27:72] + wire [32:0] _T_855 = {r_ff[28:0],a_ff[31:28]}; // @[Cat.scala 29:58] + wire [32:0] _T_873 = {1'h0,a_ff}; // @[Cat.scala 29:58] + wire [32:0] _T_874 = r_sign_sel ? 33'h1ffffffff : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_875 = r_adder_sel_0 ? _T_855 : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_876 = r_adder_sel_1 ? adder1_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_877 = r_adder_sel_2 ? adder2_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_878 = r_adder_sel_3 ? adder3_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_879 = r_adder_sel_4 ? _T_191[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_880 = r_adder_sel_5 ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_881 = r_adder_sel_6 ? _T_195[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_882 = r_adder_sel_7 ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_883 = r_adder_sel_8 ? _T_291[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_884 = r_adder_sel_9 ? adder9_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_885 = r_adder_sel_10 ? _T_239[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_886 = r_adder_sel_11 ? adder11_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_887 = r_adder_sel_12 ? _T_295[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_888 = r_adder_sel_13 ? adder13_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_889 = r_adder_sel_14 ? _T_299[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_890 = r_adder_sel_15 ? adder15_out[32:0] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_891 = shortq_enable_ff ? ar_shifted[64:32] : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_892 = by_zero_case ? _T_873 : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_893 = _T_874 | _T_875; // @[Mux.scala 27:72] + wire [32:0] _T_894 = _T_893 | _T_876; // @[Mux.scala 27:72] + wire [32:0] _T_895 = _T_894 | _T_877; // @[Mux.scala 27:72] + wire [32:0] _T_896 = _T_895 | _T_878; // @[Mux.scala 27:72] + wire [32:0] _T_897 = _T_896 | _T_879; // @[Mux.scala 27:72] + wire [32:0] _T_898 = _T_897 | _T_880; // @[Mux.scala 27:72] + wire [32:0] _T_899 = _T_898 | _T_881; // @[Mux.scala 27:72] + wire [32:0] _T_900 = _T_899 | _T_882; // @[Mux.scala 27:72] + wire [32:0] _T_901 = _T_900 | _T_883; // @[Mux.scala 27:72] + wire [32:0] _T_902 = _T_901 | _T_884; // @[Mux.scala 27:72] + wire [32:0] _T_903 = _T_902 | _T_885; // @[Mux.scala 27:72] + wire [32:0] _T_904 = _T_903 | _T_886; // @[Mux.scala 27:72] + wire [32:0] _T_905 = _T_904 | _T_887; // @[Mux.scala 27:72] + wire [32:0] _T_906 = _T_905 | _T_888; // @[Mux.scala 27:72] + wire [32:0] _T_907 = _T_906 | _T_889; // @[Mux.scala 27:72] + wire [32:0] _T_908 = _T_907 | _T_890; // @[Mux.scala 27:72] + wire [32:0] _T_909 = _T_908 | _T_891; // @[Mux.scala 27:72] + wire [32:0] r_in = _T_909 | _T_892; // @[Mux.scala 27:72] + wire [31:0] _T_913 = {q_ff[27:0],_T_486,_T_517,_T_549,_T_602}; // @[Cat.scala 29:58] + wire _T_936 = ~b_ff[3]; // @[exu_div_ctl.scala 889:70] + wire _T_938 = ~b_ff[2]; // @[exu_div_ctl.scala 889:70] + wire _T_941 = _T_936 & _T_938; // @[exu_div_ctl.scala 889:95] + wire _T_940 = ~b_ff[1]; // @[exu_div_ctl.scala 889:70] + wire _T_942 = _T_941 & _T_940; // @[exu_div_ctl.scala 889:95] + wire _T_943 = a_ff[3] & _T_942; // @[exu_div_ctl.scala 890:11] + wire _T_950 = a_ff[3] & _T_941; // @[exu_div_ctl.scala 890:11] + wire _T_952 = ~b_ff[0]; // @[exu_div_ctl.scala 895:33] + wire _T_953 = _T_950 & _T_952; // @[exu_div_ctl.scala 895:31] + wire _T_963 = a_ff[2] & _T_942; // @[exu_div_ctl.scala 890:11] + wire _T_964 = _T_953 | _T_963; // @[exu_div_ctl.scala 895:42] + wire _T_967 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 888:95] + wire _T_973 = _T_967 & _T_941; // @[exu_div_ctl.scala 890:11] + wire _T_974 = _T_964 | _T_973; // @[exu_div_ctl.scala 895:75] + wire _T_981 = a_ff[2] & _T_941; // @[exu_div_ctl.scala 890:11] + wire _T_984 = _T_981 & _T_952; // @[exu_div_ctl.scala 897:31] + wire _T_994 = a_ff[1] & _T_942; // @[exu_div_ctl.scala 890:11] + wire _T_995 = _T_984 | _T_994; // @[exu_div_ctl.scala 897:42] + wire _T_1001 = _T_936 & _T_940; // @[exu_div_ctl.scala 889:95] + wire _T_1002 = a_ff[3] & _T_1001; // @[exu_div_ctl.scala 890:11] + wire _T_1005 = _T_1002 & _T_952; // @[exu_div_ctl.scala 897:106] + wire _T_1006 = _T_995 | _T_1005; // @[exu_div_ctl.scala 897:78] + wire _T_1009 = ~a_ff[2]; // @[exu_div_ctl.scala 888:70] + wire _T_1010 = a_ff[3] & _T_1009; // @[exu_div_ctl.scala 888:95] + wire _T_1018 = _T_941 & b_ff[1]; // @[exu_div_ctl.scala 889:95] + wire _T_1019 = _T_1018 & b_ff[0]; // @[exu_div_ctl.scala 889:95] + wire _T_1020 = _T_1010 & _T_1019; // @[exu_div_ctl.scala 890:11] + wire _T_1021 = _T_1006 | _T_1020; // @[exu_div_ctl.scala 897:117] + wire _T_1023 = ~a_ff[3]; // @[exu_div_ctl.scala 888:70] + wire _T_1026 = _T_1023 & a_ff[2]; // @[exu_div_ctl.scala 888:95] + wire _T_1027 = _T_1026 & a_ff[1]; // @[exu_div_ctl.scala 888:95] + wire _T_1033 = _T_1027 & _T_941; // @[exu_div_ctl.scala 890:11] + wire _T_1034 = _T_1021 | _T_1033; // @[exu_div_ctl.scala 898:44] + wire _T_1040 = _T_967 & _T_936; // @[exu_div_ctl.scala 890:11] + wire _T_1043 = _T_1040 & _T_952; // @[exu_div_ctl.scala 898:107] + wire _T_1044 = _T_1034 | _T_1043; // @[exu_div_ctl.scala 898:80] + wire _T_1053 = _T_936 & b_ff[2]; // @[exu_div_ctl.scala 889:95] + wire _T_1054 = _T_1053 & _T_940; // @[exu_div_ctl.scala 889:95] + wire _T_1055 = _T_967 & _T_1054; // @[exu_div_ctl.scala 890:11] + wire _T_1056 = _T_1044 | _T_1055; // @[exu_div_ctl.scala 898:119] + wire _T_1059 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 888:95] + wire _T_1065 = _T_1059 & _T_1001; // @[exu_div_ctl.scala 890:11] + wire _T_1066 = _T_1056 | _T_1065; // @[exu_div_ctl.scala 899:44] + wire _T_1071 = _T_967 & a_ff[1]; // @[exu_div_ctl.scala 888:95] + wire _T_1076 = _T_1071 & _T_1053; // @[exu_div_ctl.scala 890:11] + wire _T_1077 = _T_1066 | _T_1076; // @[exu_div_ctl.scala 899:79] + wire _T_1081 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 888:95] + wire _T_1082 = _T_1081 & a_ff[0]; // @[exu_div_ctl.scala 888:95] + wire _T_1088 = _T_1082 & _T_1001; // @[exu_div_ctl.scala 890:11] + wire _T_1094 = _T_1010 & a_ff[0]; // @[exu_div_ctl.scala 888:95] + wire _T_1099 = _T_936 & b_ff[1]; // @[exu_div_ctl.scala 889:95] + wire _T_1100 = _T_1099 & b_ff[0]; // @[exu_div_ctl.scala 889:95] + wire _T_1101 = _T_1094 & _T_1100; // @[exu_div_ctl.scala 890:11] + wire _T_1102 = _T_1088 | _T_1101; // @[exu_div_ctl.scala 901:45] + wire _T_1109 = a_ff[2] & _T_1001; // @[exu_div_ctl.scala 890:11] + wire _T_1112 = _T_1109 & _T_952; // @[exu_div_ctl.scala 901:114] + wire _T_1113 = _T_1102 | _T_1112; // @[exu_div_ctl.scala 901:86] + wire _T_1120 = a_ff[1] & _T_941; // @[exu_div_ctl.scala 890:11] + wire _T_1123 = _T_1120 & _T_952; // @[exu_div_ctl.scala 902:33] + wire _T_1124 = _T_1113 | _T_1123; // @[exu_div_ctl.scala 901:129] + wire _T_1134 = a_ff[0] & _T_942; // @[exu_div_ctl.scala 890:11] + wire _T_1135 = _T_1124 | _T_1134; // @[exu_div_ctl.scala 902:47] + wire _T_1140 = ~a_ff[1]; // @[exu_div_ctl.scala 888:70] + wire _T_1142 = _T_1026 & _T_1140; // @[exu_div_ctl.scala 888:95] + wire _T_1152 = _T_1142 & _T_1019; // @[exu_div_ctl.scala 890:11] + wire _T_1153 = _T_1135 | _T_1152; // @[exu_div_ctl.scala 902:88] + wire _T_1162 = _T_1027 & _T_936; // @[exu_div_ctl.scala 890:11] + wire _T_1165 = _T_1162 & _T_952; // @[exu_div_ctl.scala 903:36] + wire _T_1166 = _T_1153 | _T_1165; // @[exu_div_ctl.scala 902:131] + wire _T_1172 = _T_938 & _T_940; // @[exu_div_ctl.scala 889:95] + wire _T_1173 = a_ff[3] & _T_1172; // @[exu_div_ctl.scala 890:11] + wire _T_1176 = _T_1173 & _T_952; // @[exu_div_ctl.scala 903:76] + wire _T_1177 = _T_1166 | _T_1176; // @[exu_div_ctl.scala 903:47] + wire _T_1187 = _T_1053 & b_ff[1]; // @[exu_div_ctl.scala 889:95] + wire _T_1188 = _T_1010 & _T_1187; // @[exu_div_ctl.scala 890:11] + wire _T_1189 = _T_1177 | _T_1188; // @[exu_div_ctl.scala 903:88] + wire _T_1203 = _T_1027 & _T_1054; // @[exu_div_ctl.scala 890:11] + wire _T_1204 = _T_1189 | _T_1203; // @[exu_div_ctl.scala 903:131] + wire _T_1210 = _T_1026 & a_ff[0]; // @[exu_div_ctl.scala 888:95] + wire _T_1216 = _T_1210 & _T_1001; // @[exu_div_ctl.scala 890:11] + wire _T_1217 = _T_1204 | _T_1216; // @[exu_div_ctl.scala 904:47] + wire _T_1224 = _T_1010 & _T_1140; // @[exu_div_ctl.scala 888:95] + wire _T_1230 = _T_1053 & b_ff[0]; // @[exu_div_ctl.scala 889:95] + wire _T_1231 = _T_1224 & _T_1230; // @[exu_div_ctl.scala 890:11] + wire _T_1232 = _T_1217 | _T_1231; // @[exu_div_ctl.scala 904:88] + wire _T_1237 = _T_1009 & a_ff[1]; // @[exu_div_ctl.scala 888:95] + wire _T_1238 = _T_1237 & a_ff[0]; // @[exu_div_ctl.scala 888:95] + wire _T_1244 = _T_1238 & _T_941; // @[exu_div_ctl.scala 890:11] + wire _T_1245 = _T_1232 | _T_1244; // @[exu_div_ctl.scala 904:131] + wire _T_1251 = _T_967 & _T_940; // @[exu_div_ctl.scala 890:11] + wire _T_1254 = _T_1251 & _T_952; // @[exu_div_ctl.scala 905:75] + wire _T_1255 = _T_1245 | _T_1254; // @[exu_div_ctl.scala 905:47] + wire _T_1263 = _T_1027 & a_ff[0]; // @[exu_div_ctl.scala 888:95] + wire _T_1268 = _T_1263 & _T_1053; // @[exu_div_ctl.scala 890:11] + wire _T_1269 = _T_1255 | _T_1268; // @[exu_div_ctl.scala 905:88] + wire _T_1276 = b_ff[3] & _T_938; // @[exu_div_ctl.scala 889:95] + wire _T_1277 = _T_967 & _T_1276; // @[exu_div_ctl.scala 890:11] + wire _T_1278 = _T_1269 | _T_1277; // @[exu_div_ctl.scala 905:131] + wire _T_1288 = _T_1276 & _T_940; // @[exu_div_ctl.scala 889:95] + wire _T_1289 = _T_1059 & _T_1288; // @[exu_div_ctl.scala 890:11] + wire _T_1290 = _T_1278 | _T_1289; // @[exu_div_ctl.scala 906:47] + wire _T_1293 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 888:95] + wire _T_1299 = _T_1293 & _T_1172; // @[exu_div_ctl.scala 890:11] + wire _T_1300 = _T_1290 | _T_1299; // @[exu_div_ctl.scala 906:88] + wire _T_1304 = a_ff[3] & _T_1140; // @[exu_div_ctl.scala 888:95] + wire _T_1312 = _T_1187 & b_ff[0]; // @[exu_div_ctl.scala 889:95] + wire _T_1313 = _T_1304 & _T_1312; // @[exu_div_ctl.scala 890:11] + wire _T_1314 = _T_1300 | _T_1313; // @[exu_div_ctl.scala 906:131] + wire _T_1321 = _T_1071 & b_ff[3]; // @[exu_div_ctl.scala 890:11] + wire _T_1324 = _T_1321 & _T_952; // @[exu_div_ctl.scala 907:77] + wire _T_1325 = _T_1314 | _T_1324; // @[exu_div_ctl.scala 907:47] + wire _T_1334 = b_ff[3] & _T_940; // @[exu_div_ctl.scala 889:95] + wire _T_1335 = _T_1071 & _T_1334; // @[exu_div_ctl.scala 890:11] + wire _T_1336 = _T_1325 | _T_1335; // @[exu_div_ctl.scala 907:88] + wire _T_1341 = _T_967 & a_ff[0]; // @[exu_div_ctl.scala 888:95] + wire _T_1346 = _T_1341 & _T_1334; // @[exu_div_ctl.scala 890:11] + wire _T_1347 = _T_1336 | _T_1346; // @[exu_div_ctl.scala 907:131] + wire _T_1353 = _T_1010 & a_ff[1]; // @[exu_div_ctl.scala 888:95] + wire _T_1358 = _T_1353 & _T_1099; // @[exu_div_ctl.scala 890:11] + wire _T_1359 = _T_1347 | _T_1358; // @[exu_div_ctl.scala 908:47] + wire _T_1364 = _T_1059 & a_ff[0]; // @[exu_div_ctl.scala 888:95] + wire _T_1367 = _T_1364 & _T_938; // @[exu_div_ctl.scala 890:11] + wire _T_1368 = _T_1359 | _T_1367; // @[exu_div_ctl.scala 908:88] + wire _T_1375 = _T_1071 & a_ff[0]; // @[exu_div_ctl.scala 888:95] + wire _T_1377 = _T_1375 & b_ff[3]; // @[exu_div_ctl.scala 890:11] + wire _T_1378 = _T_1368 | _T_1377; // @[exu_div_ctl.scala 908:131] + wire _T_1384 = _T_1059 & _T_938; // @[exu_div_ctl.scala 890:11] + wire _T_1387 = _T_1384 & _T_952; // @[exu_div_ctl.scala 909:74] + wire _T_1388 = _T_1378 | _T_1387; // @[exu_div_ctl.scala 909:47] + wire [31:0] _T_914 = {28'h0,_T_943,_T_974,_T_1077,_T_1388}; // @[Cat.scala 29:58] + wire [31:0] _T_916 = _T_76 ? _T_913 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_917 = smallnum_case ? _T_914 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_918 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_919 = _T_916 | _T_917; // @[Mux.scala 27:72] + wire [31:0] q_in = _T_919 | _T_918; // @[Mux.scala 27:72] + wire _T_924 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 883:16] + wire _T_925 = _T_30 & _T_924; // @[exu_div_ctl.scala 883:14] + wire [31:0] _T_928 = _T_925 ? q_ff : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_929 = control_ff[0] ? r_ff[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_930 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_931 = _T_928 | _T_929; // @[Mux.scala 27:72] + wire _T_1415 = shortq == 6'h1b; // @[exu_div_ctl.scala 925:64] + wire _T_1416 = shortq == 6'h1a; // @[exu_div_ctl.scala 925:64] + wire _T_1417 = shortq == 6'h19; // @[exu_div_ctl.scala 925:64] + wire _T_1418 = shortq == 6'h18; // @[exu_div_ctl.scala 925:64] + wire _T_1419 = shortq == 6'h17; // @[exu_div_ctl.scala 925:64] + wire _T_1420 = shortq == 6'h16; // @[exu_div_ctl.scala 925:64] + wire _T_1421 = shortq == 6'h15; // @[exu_div_ctl.scala 925:64] + wire _T_1422 = shortq == 6'h14; // @[exu_div_ctl.scala 925:64] + wire _T_1423 = shortq == 6'h13; // @[exu_div_ctl.scala 925:64] + wire _T_1424 = shortq == 6'h12; // @[exu_div_ctl.scala 925:64] + wire _T_1425 = shortq == 6'h11; // @[exu_div_ctl.scala 925:64] + wire _T_1426 = shortq == 6'h10; // @[exu_div_ctl.scala 925:64] + wire _T_1427 = shortq == 6'hf; // @[exu_div_ctl.scala 925:64] + wire _T_1428 = shortq == 6'he; // @[exu_div_ctl.scala 925:64] + wire _T_1429 = shortq == 6'hd; // @[exu_div_ctl.scala 925:64] + wire _T_1430 = shortq == 6'hc; // @[exu_div_ctl.scala 925:64] + wire _T_1431 = shortq == 6'hb; // @[exu_div_ctl.scala 925:64] + wire _T_1432 = shortq == 6'ha; // @[exu_div_ctl.scala 925:64] + wire _T_1433 = shortq == 6'h9; // @[exu_div_ctl.scala 925:64] + wire _T_1434 = shortq == 6'h8; // @[exu_div_ctl.scala 925:64] + wire _T_1435 = shortq == 6'h7; // @[exu_div_ctl.scala 925:64] + wire _T_1436 = shortq == 6'h6; // @[exu_div_ctl.scala 925:64] + wire _T_1437 = shortq == 6'h5; // @[exu_div_ctl.scala 925:64] + wire _T_1438 = shortq == 6'h4; // @[exu_div_ctl.scala 925:64] + wire _T_1439 = shortq == 6'h3; // @[exu_div_ctl.scala 925:64] + wire _T_1440 = shortq == 6'h2; // @[exu_div_ctl.scala 925:64] + wire _T_1441 = shortq == 6'h1; // @[exu_div_ctl.scala 925:64] + wire _T_1442 = shortq == 6'h0; // @[exu_div_ctl.scala 925:64] + wire [2:0] _T_1447 = _T_1415 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1448 = _T_1416 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1449 = _T_1417 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1450 = _T_1418 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1451 = _T_1419 ? 4'h8 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1452 = _T_1420 ? 4'h8 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1453 = _T_1421 ? 4'h8 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1454 = _T_1422 ? 4'h8 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1455 = _T_1423 ? 4'hc : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1456 = _T_1424 ? 4'hc : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1457 = _T_1425 ? 4'hc : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1458 = _T_1426 ? 4'hc : 4'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1459 = _T_1427 ? 5'h10 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1460 = _T_1428 ? 5'h10 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1461 = _T_1429 ? 5'h10 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1462 = _T_1430 ? 5'h10 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1463 = _T_1431 ? 5'h14 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1464 = _T_1432 ? 5'h14 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1465 = _T_1433 ? 5'h14 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1466 = _T_1434 ? 5'h14 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1467 = _T_1435 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1468 = _T_1436 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1469 = _T_1437 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1470 = _T_1438 ? 5'h18 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1471 = _T_1439 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1472 = _T_1440 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1473 = _T_1441 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_1474 = _T_1442 ? 5'h1c : 5'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1479 = _T_1447 | _T_1448; // @[Mux.scala 27:72] + wire [2:0] _T_1480 = _T_1479 | _T_1449; // @[Mux.scala 27:72] + wire [2:0] _T_1481 = _T_1480 | _T_1450; // @[Mux.scala 27:72] + wire [3:0] _GEN_12 = {{1'd0}, _T_1481}; // @[Mux.scala 27:72] + wire [3:0] _T_1482 = _GEN_12 | _T_1451; // @[Mux.scala 27:72] + wire [3:0] _T_1483 = _T_1482 | _T_1452; // @[Mux.scala 27:72] + wire [3:0] _T_1484 = _T_1483 | _T_1453; // @[Mux.scala 27:72] + wire [3:0] _T_1485 = _T_1484 | _T_1454; // @[Mux.scala 27:72] + wire [3:0] _T_1486 = _T_1485 | _T_1455; // @[Mux.scala 27:72] + wire [3:0] _T_1487 = _T_1486 | _T_1456; // @[Mux.scala 27:72] + wire [3:0] _T_1488 = _T_1487 | _T_1457; // @[Mux.scala 27:72] + wire [3:0] _T_1489 = _T_1488 | _T_1458; // @[Mux.scala 27:72] + wire [4:0] _GEN_13 = {{1'd0}, _T_1489}; // @[Mux.scala 27:72] + wire [4:0] _T_1490 = _GEN_13 | _T_1459; // @[Mux.scala 27:72] + wire [4:0] _T_1491 = _T_1490 | _T_1460; // @[Mux.scala 27:72] + wire [4:0] _T_1492 = _T_1491 | _T_1461; // @[Mux.scala 27:72] + wire [4:0] _T_1493 = _T_1492 | _T_1462; // @[Mux.scala 27:72] + wire [4:0] _T_1494 = _T_1493 | _T_1463; // @[Mux.scala 27:72] + wire [4:0] _T_1495 = _T_1494 | _T_1464; // @[Mux.scala 27:72] + wire [4:0] _T_1496 = _T_1495 | _T_1465; // @[Mux.scala 27:72] + wire [4:0] _T_1497 = _T_1496 | _T_1466; // @[Mux.scala 27:72] + wire [4:0] _T_1498 = _T_1497 | _T_1467; // @[Mux.scala 27:72] + wire [4:0] _T_1499 = _T_1498 | _T_1468; // @[Mux.scala 27:72] + wire [4:0] _T_1500 = _T_1499 | _T_1469; // @[Mux.scala 27:72] + wire [4:0] _T_1501 = _T_1500 | _T_1470; // @[Mux.scala 27:72] + wire [4:0] _T_1502 = _T_1501 | _T_1471; // @[Mux.scala 27:72] + wire [4:0] _T_1503 = _T_1502 | _T_1472; // @[Mux.scala 27:72] + wire [4:0] _T_1504 = _T_1503 | _T_1473; // @[Mux.scala 27:72] + wire [4:0] shortq_decode = _T_1504 | _T_1474; // @[Mux.scala 27:72] + exu_div_cls a_enc ( // @[exu_div_ctl.scala 913:31] .io_operand(a_enc_io_operand), .io_cls(a_enc_io_cls) ); - exu_div_cls b_enc ( // @[exu_div_ctl.scala 922:21] + exu_div_cls b_enc ( // @[exu_div_ctl.scala 916:31] .io_operand(b_enc_io_operand), .io_cls(b_enc_io_cls) ); @@ -988,10 +988,10 @@ module exu_div_new_4bit_fullshortq( .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en) ); - assign io_data_out = _T_913 | _T_912; // @[exu_div_ctl.scala 888:15] - assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 887:16] - assign a_enc_io_operand = {control_ff[2],a_ff}; // @[exu_div_ctl.scala 920:20] - assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 923:20] + assign io_data_out = _T_931 | _T_930; // @[exu_div_ctl.scala 882:15] + assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 881:16] + assign a_enc_io_operand = {control_ff[2],a_ff}; // @[exu_div_ctl.scala 914:23] + assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 917:23] assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18] assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18] diff --git a/src/main/scala/exu/exu_div_ctl.scala b/src/main/scala/exu/exu_div_ctl.scala index 7dd8d148..d6db0cfc 100644 --- a/src/main/scala/exu/exu_div_ctl.scala +++ b/src/main/scala/exu/exu_div_ctl.scala @@ -171,29 +171,29 @@ class exu_div_existing_1bit_cheapshortq extends Module with RequireAsyncReset wi val a_cls = Cat(0.U(2.W), Mux1H(Seq ( !short_dividend(32).asBool -> (short_dividend(31,24) =/= Fill(8,0.U)), - short_dividend(32).asBool -> (short_dividend(31,23) =/= Fill(9,1.U)) + short_dividend(32).asBool -> (short_dividend(31,23) =/= Fill(9,1.U)) )), Mux1H(Seq ( !short_dividend(32).asBool -> (short_dividend(23,16) =/= Fill(8,0.U)), - short_dividend(32).asBool -> (short_dividend(22,15) =/= Fill(8,1.U)) + short_dividend(32).asBool -> (short_dividend(22,15) =/= Fill(8,1.U)) )), Mux1H(Seq ( !short_dividend(32).asBool -> (short_dividend(15,8) =/= Fill(8,0.U)), - short_dividend(32).asBool -> (short_dividend(14,7) =/= Fill(8,1.U)) + short_dividend(32).asBool -> (short_dividend(14,7) =/= Fill(8,1.U)) )) ) val b_cls = Cat(0.U(2.W), Mux1H(Seq ( !m_ff(32).asBool -> (m_ff(31,24) =/= Fill(8,0.U)), - m_ff(32).asBool -> (m_ff(31,24) =/= Fill(8,1.U)) + m_ff(32).asBool -> (m_ff(31,24) =/= Fill(8,1.U)) )), Mux1H(Seq ( !m_ff(32).asBool -> (m_ff(23,16) =/= Fill(8,0.U)), - m_ff(32).asBool -> (m_ff(23,16) =/= Fill(8,1.U)) + m_ff(32).asBool -> (m_ff(23,16) =/= Fill(8,1.U)) )), Mux1H(Seq ( !m_ff(32).asBool -> (m_ff(15,8) =/= Fill(8,0.U)), - m_ff(32).asBool -> (m_ff(15,8) =/= Fill(8,1.U)) + m_ff(32).asBool -> (m_ff(15,8) =/= Fill(8,1.U)) )) ) val shortq_raw = Cat( @@ -209,7 +209,7 @@ class exu_div_existing_1bit_cheapshortq extends Module with RequireAsyncReset wi ( (a_cls(2,0) === "b001".U ) & (b_cls(2,0) === "b001".U ) ) | ( (a_cls(2,0) === "b000".U ) & (b_cls(2,0) === "b000".U ) ) , - ( (a_cls(2) === "b1".U ) & (b_cls(2,1) === "b01".U ) ) | // Shift by 16 + ( (a_cls(2) === "b1".U ) & (b_cls(2,1) === "b01".U ) ) | // Shift by 16 ( (a_cls(2,1) === "b01".U ) & (b_cls(2,0) === "b001".U ) ) | ( (a_cls(2,0) === "b001".U ) & (b_cls(2,0) === "b000".U ) ) , @@ -230,13 +230,13 @@ class exu_div_existing_1bit_cheapshortq extends Module with RequireAsyncReset wi val finish = smallnum_case | Mux(!rem_ff ,count === 32.U(6.W) ,count === 33.U(6.W)) val div_clken = io.valid_in | run_state | finish | finish_ff val run_in = (io.valid_in | run_state) & !finish & !io.cancel - count_in := Fill(6,(run_state & !finish & !io.cancel & !shortq_enable)) & (count + Cat(0.U,shortq_shift_ff(4,0)) + (1.U)(6.W)) - io.valid_out := finish_ff & !io.cancel + count_in := Fill(6,(run_state & !finish & !io.cancel & !shortq_enable)) & (count + Cat(0.U,shortq_shift_ff(4,0)) + (1.U)(6.W)) + io.valid_out := finish_ff & !io.cancel val sign_eff = io.signed_in & (io.divisor_in =/= 0.U(32.W)) q_in := Mux1H(Seq( - (!run_state).asBool -> Cat(0.U(1.W),io.dividend_in) , - (run_state & (valid_ff_x | shortq_enable_ff)).asBool -> (Cat(dividend_eff(31,0),!a_in(32)) << shortq_shift_ff(4,0)) , + (!run_state).asBool -> Cat(0.U(1.W),io.dividend_in) , + (run_state & (valid_ff_x | shortq_enable_ff)).asBool -> (Cat(dividend_eff(31,0),!a_in(32)) << shortq_shift_ff(4,0)) , (run_state & !(valid_ff_x | shortq_enable_ff)).asBool -> Cat(q_ff(31,0),!a_in(32)) )) val qff_enable = io.valid_in | (run_state & !shortq_enable) @@ -263,22 +263,21 @@ class exu_div_existing_1bit_cheapshortq extends Module with RequireAsyncReset wi rem_ff.asBool -> a_ff_eff , (!smallnum_case_ff & !rem_ff).asBool -> q_ff_eff )) - valid_ff_x := rvdffe(io.valid_in & !io.cancel, div_clken,clock,io.scan_mode) - finish_ff := rvdffe(finish & !io.cancel, div_clken,clock,io.scan_mode) - run_state := rvdffe(run_in,div_clken,clock,io.scan_mode) - count := rvdffe(count_in, div_clken,clock,io.scan_mode) - dividend_neg_ff := rvdffe((io.valid_in & io.dividend_in(31)) | (!io.valid_in & dividend_neg_ff), div_clken,clock,io.scan_mode) - divisor_neg_ff := rvdffe((io.valid_in & io.divisor_in(31)) | (!io.valid_in & divisor_neg_ff), div_clken,clock,io.scan_mode) - sign_ff := rvdffe((io.valid_in & sign_eff) | (!io.valid_in & sign_ff), div_clken,clock,io.scan_mode) - rem_ff := rvdffe((io.valid_in & io.rem_in) | (!io.valid_in & rem_ff), div_clken,clock,io.scan_mode) + valid_ff_x := rvdffe(io.valid_in & !io.cancel, div_clken,clock,io.scan_mode) + finish_ff := rvdffe(finish & !io.cancel, div_clken,clock,io.scan_mode) + run_state := rvdffe(run_in,div_clken,clock,io.scan_mode) + count := rvdffe(count_in, div_clken,clock,io.scan_mode) + dividend_neg_ff := rvdffe((io.valid_in & io.dividend_in(31)) | (!io.valid_in & dividend_neg_ff), div_clken,clock,io.scan_mode) + divisor_neg_ff := rvdffe((io.valid_in & io.divisor_in(31)) | (!io.valid_in & divisor_neg_ff), div_clken,clock,io.scan_mode) + sign_ff := rvdffe((io.valid_in & sign_eff) | (!io.valid_in & sign_ff), div_clken,clock,io.scan_mode) + rem_ff := rvdffe((io.valid_in & io.rem_in) | (!io.valid_in & rem_ff), div_clken,clock,io.scan_mode) smallnum_case_ff := rvdffe(smallnum_case, div_clken,clock,io.scan_mode) - smallnum_ff := rvdffe(smallnum, div_clken,clock,io.scan_mode) + smallnum_ff := rvdffe(smallnum, div_clken,clock,io.scan_mode) shortq_enable_ff := rvdffe(shortq_enable, div_clken,clock,io.scan_mode) - shortq_shift_xx := rvdffe(shortq_shift, div_clken,clock,io.scan_mode) - - q_ff := rvdffe(q_in, qff_enable,clock,io.scan_mode) - a_ff := rvdffe(a_in, aff_enable,clock,io.scan_mode) - m_ff := rvdffe(Cat(io.signed_in & io.divisor_in(31), io.divisor_in(31,0)), io.valid_in,clock,io.scan_mode) + shortq_shift_xx := rvdffe(shortq_shift, div_clken,clock,io.scan_mode) + q_ff := rvdffe(q_in, qff_enable,clock,io.scan_mode) + a_ff := rvdffe(a_in, aff_enable,clock,io.scan_mode) + m_ff := rvdffe(Cat(io.signed_in & io.divisor_in(31), io.divisor_in(31,0)), io.valid_in,clock,io.scan_mode) } /////////////////////////////////////////////// 1 BIT FULL DIVIDER////////////////////////////////// @@ -396,30 +395,30 @@ class exu_div_new_1bit_fullshortq extends Module with RequireAsyncReset with lib pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0)) val shortq_dividend = Cat(dividend_sign_ff,a_ff) - val a_enc = Module(new exu_div_cls) - a_enc.io.operand := shortq_dividend - val dw_a_enc1 = a_enc.io.cls - val b_enc = Module(new exu_div_cls) - b_enc.io.operand := b_ff - val dw_b_enc1 = b_enc.io.cls - val dw_a_enc = Cat (0.U, dw_a_enc1) - val dw_b_enc = Cat (0.U, dw_b_enc1) + val a_enc = Module(new exu_div_cls) + a_enc.io.operand := shortq_dividend + val dw_a_enc1 = a_enc.io.cls + val b_enc = Module(new exu_div_cls) + b_enc.io.operand := b_ff + val dw_b_enc1 = b_enc.io.cls + val dw_a_enc = Cat (0.U, dw_a_enc1) + val dw_b_enc = Cat (0.U, dw_b_enc1) val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W) - val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0)) - shortq_enable := valid_ff & !shortq(5) & !(shortq(4,1) === "b1111".U) & !io.cancel - val shortq_shift = Mux(!shortq_enable,0.U,("b11111".U - shortq(4,0))) - valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode) - control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode) - by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode) - shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode) - shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode) - finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode) - count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode) + val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0)) + shortq_enable := valid_ff & !shortq(5) & !(shortq(4,1) === "b1111".U) & !io.cancel + val shortq_shift = Mux(!shortq_enable,0.U,("b11111".U - shortq(4,0))) + valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode) + control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode) + by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode) + shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode) + shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode) + finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode) + count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode) - a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode) - b_ff := rvdffe(b_in, b_enable,clock,io.scan_mode) - r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode) - q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode) + a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode) + b_ff := rvdffe(b_in, b_enable,clock,io.scan_mode) + r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode) + q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode) } /////////////////////////////////////////////// 2 BIT FULL DIVIDER////////////////////////////////// class exu_div_new_2bit_fullshortq extends Module with RequireAsyncReset with lib { @@ -478,48 +477,48 @@ class exu_div_new_2bit_fullshortq extends Module with RequireAsyncReset with lib val r_adder1_sel = running_state & (quotient_new === 1.U) & !shortq_enable_ff val r_adder2_sel = running_state & (quotient_new === 2.U) & !shortq_enable_ff val r_adder3_sel = running_state & (quotient_new === 3.U) & !shortq_enable_ff - val adder1_out = Cat(r_ff(30,0),a_ff(31,30)) + b_ff(32,0) - val adder2_out = Cat(r_ff(31,0),a_ff(31,30)) + Cat(b_ff(32,0),0.U) - val adder3_out = Cat(r_ff(31),r_ff(31,0),a_ff(31,30)) + Cat(b_ff(33,0),0.U) + b_ff - quotient_raw := Cat((!adder3_out(34) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder3_out === 0.U)), + val adder1_out = Cat(r_ff(30,0),a_ff(31,30)) + b_ff(32,0) + val adder2_out = Cat(r_ff(31,0),a_ff(31,30)) + Cat(b_ff(32,0),0.U) + val adder3_out = Cat(r_ff(31),r_ff(31,0),a_ff(31,30)) + Cat(b_ff(33,0),0.U) + b_ff + quotient_raw := Cat((!adder3_out(34) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder3_out === 0.U)), (!adder2_out(33) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder2_out === 0.U)), (!adder1_out(32) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder1_out === 0.U)),0.U) - quotient_new := Cat ((quotient_raw(3) | quotient_raw(2)) , (quotient_raw(3) |(!quotient_raw(2) & quotient_raw(1)))) + quotient_new := Cat ((quotient_raw(3) | quotient_raw(2)) , (quotient_raw(3) |(!quotient_raw(2) & quotient_raw(1)))) val twos_comp_in = Mux1H(Seq ( - twos_comp_q_sel -> q_ff, - twos_comp_b_sel -> b_ff(31,0) + twos_comp_q_sel -> q_ff, + twos_comp_b_sel -> b_ff(31,0) )) val twos_comp_out = rvtwoscomp(twos_comp_in) val a_in = Mux1H(Seq ( (!a_shift & !shortq_enable_ff).asBool -> io.dividend_in, - a_shift -> Cat(a_ff(29,0),0.U(2.W)), - shortq_enable_ff -> ar_shifted(31,0) + a_shift -> Cat(a_ff(29,0),0.U(2.W)), + shortq_enable_ff -> ar_shifted(31,0) )) val b_in = Mux1H(Seq ( - !b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)), - b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0)) + !b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)), + b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0)) )) val r_in = Mux1H (Seq( - r_sign_sel -> "hffffffff".U(32.W), - r_restore_sel -> Cat(r_ff(29,0),a_ff(31,30)), - r_adder1_sel -> adder1_out(31,0), - r_adder2_sel -> adder2_out(31,0), - r_adder3_sel -> adder3_out(31,0), - shortq_enable_ff -> ar_shifted(63,32), - by_zero_case -> a_ff + r_sign_sel -> "hffffffff".U(32.W), + r_restore_sel -> Cat(r_ff(29,0),a_ff(31,30)), + r_adder1_sel -> adder1_out(31,0), + r_adder2_sel -> adder2_out(31,0), + r_adder3_sel -> adder3_out(31,0), + shortq_enable_ff -> ar_shifted(63,32), + by_zero_case -> a_ff )) val q_in = Mux1H (Seq( - !valid_ff -> Cat(q_ff(29,0),quotient_new), - smallnum_case -> Cat(0.U(28.W),smallnum), - by_zero_case -> Fill(32,1.U) + !valid_ff -> Cat(q_ff(29,0),quotient_new), + smallnum_case -> Cat(0.U(28.W),smallnum), + by_zero_case -> Fill(32,1.U) )) io.valid_out := finish_ff & !io.cancel io.data_out := Mux1H(Seq( (!rem_ff & !twos_comp_q_sel).asBool() -> q_ff, - rem_ff -> r_ff, - twos_comp_q_sel -> twos_comp_out + rem_ff -> r_ff, + twos_comp_q_sel -> twos_comp_out )) def pat1(x : List[Int], y : List[Int]) = { val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_) @@ -546,31 +545,31 @@ class exu_div_new_2bit_fullshortq extends Module with RequireAsyncReset with lib pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0)) val shortq_dividend = Cat(dividend_sign_ff,a_ff) - val a_enc = Module(new exu_div_cls) - a_enc.io.operand := shortq_dividend - val dw_a_enc1 = a_enc.io.cls - val b_enc = Module(new exu_div_cls) - b_enc.io.operand := b_ff(32,0) - val dw_b_enc1 = b_enc.io.cls - val dw_a_enc = Cat (0.U, dw_a_enc1) - val dw_b_enc = Cat (0.U, dw_b_enc1) - val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W) - val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0)) - shortq_enable := valid_ff & !shortq(5) & !(shortq(4,1) === "b1111".U) & !io.cancel - val shortq_shift = Mux(!shortq_enable,0.U,("b11111".U - shortq(4,0))) - b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1) - valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode) - control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode) - by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode) - shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode) - shortq_shift_ff := Cat(rvdffe(shortq_shift(4,1), misc_enable,clock,io.scan_mode),0.U) - finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode) - count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode) + val a_enc = Module(new exu_div_cls) + a_enc.io.operand := shortq_dividend + val dw_a_enc1 = a_enc.io.cls + val b_enc = Module(new exu_div_cls) + b_enc.io.operand := b_ff(32,0) + val dw_b_enc1 = b_enc.io.cls + val dw_a_enc = Cat (0.U, dw_a_enc1) + val dw_b_enc = Cat (0.U, dw_b_enc1) + val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W) + val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0)) + shortq_enable := valid_ff & !shortq(5) & !(shortq(4,1) === "b1111".U) & !io.cancel + val shortq_shift = Mux(!shortq_enable,0.U,("b11111".U - shortq(4,0))) + b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1) + valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode) + control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode) + by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode) + shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode) + shortq_shift_ff := Cat(rvdffe(shortq_shift(4,1), misc_enable,clock,io.scan_mode),0.U) + finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode) + count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode) - a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode) - b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode) - r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode) - q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode) + a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode) + b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode) + r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode) + q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode) } /////////////////////////////////////////////// 3 BIT FULL DIVIDER////////////////////////////////// @@ -649,42 +648,42 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib (quotient_raw(7) | quotient_raw(6) |(!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(3) & quotient_raw(2))), (quotient_raw(7) | (!quotient_raw(6) & quotient_raw(5)) | (!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(2) & quotient_raw(1)))) val twos_comp_in = Mux1H(Seq ( - twos_comp_q_sel -> q_ff, - twos_comp_b_sel -> b_ff(31,0) + twos_comp_q_sel -> q_ff, + twos_comp_b_sel -> b_ff(31,0) )) val twos_comp_out = rvtwoscomp(twos_comp_in) val a_in = Mux1H(Seq ( (!a_shift & !shortq_enable_ff).asBool -> Cat(io.signed_in & io.dividend_in(31),io.dividend_in(31,0)), - a_shift -> Cat(a_ff(29,0),0.U(3.W)), - shortq_enable_ff -> ar_shifted(32,0) + a_shift -> Cat(a_ff(29,0),0.U(3.W)), + shortq_enable_ff -> ar_shifted(32,0) )) val b_in = Mux1H(Seq ( - !b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)), - b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0)) + !b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)), + b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0)) )) val r_in = Mux1H (Seq( - r_sign_sel -> Fill(33,1.U), - r_adder_sel(0) -> Cat(r_ff(29,0),a_ff(32,30)), - r_adder_sel(1) -> adder1_out(32,0), - r_adder_sel(2) -> adder2_out(32,0), - r_adder_sel(3) -> adder3_out(32,0), - r_adder_sel(4) -> adder4_out(32,0), - r_adder_sel(5) -> adder5_out(32,0), - r_adder_sel(6) -> adder6_out(32,0), - r_adder_sel(7) -> adder7_out(32,0), - shortq_enable_ff -> ar_shifted(65,33), - by_zero_case -> Cat(0.U,a_ff(31,0)) + r_sign_sel -> Fill(33,1.U), + r_adder_sel(0) -> Cat(r_ff(29,0),a_ff(32,30)), + r_adder_sel(1) -> adder1_out(32,0), + r_adder_sel(2) -> adder2_out(32,0), + r_adder_sel(3) -> adder3_out(32,0), + r_adder_sel(4) -> adder4_out(32,0), + r_adder_sel(5) -> adder5_out(32,0), + r_adder_sel(6) -> adder6_out(32,0), + r_adder_sel(7) -> adder7_out(32,0), + shortq_enable_ff -> ar_shifted(65,33), + by_zero_case -> Cat(0.U,a_ff(31,0)) )) val q_in = Mux1H (Seq( - !valid_ff -> Cat(q_ff(28,0),quotient_new), - smallnum_case -> Cat(0.U(28.W),smallnum), - by_zero_case -> Fill(32,1.U) + !valid_ff -> Cat(q_ff(28,0),quotient_new), + smallnum_case -> Cat(0.U(28.W),smallnum), + by_zero_case -> Fill(32,1.U) )) io.valid_out := finish_ff & !io.cancel io.data_out := Mux1H(Seq( (!rem_ff & !twos_comp_q_sel).asBool() -> q_ff, - rem_ff -> r_ff(31,0), - twos_comp_q_sel -> twos_comp_out + rem_ff -> r_ff(31,0), + twos_comp_q_sel -> twos_comp_out )) def pat1(x : List[Int], y : List[Int]) = { val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_) @@ -711,48 +710,48 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0)) val shortq_dividend = Cat(dividend_sign_ff,a_ff(31,0)) - val a_enc = Module(new exu_div_cls) - a_enc.io.operand := shortq_dividend - val dw_a_enc1 = a_enc.io.cls - val b_enc = Module(new exu_div_cls) - b_enc.io.operand := b_ff(32,0) - val dw_b_enc1 = b_enc.io.cls - val dw_a_enc = Cat (0.U, dw_a_enc1) - val dw_b_enc = Cat (0.U, dw_b_enc1) + val a_enc = Module(new exu_div_cls) + a_enc.io.operand := shortq_dividend + val dw_a_enc1 = a_enc.io.cls + val b_enc = Module(new exu_div_cls) + b_enc.io.operand := b_ff(32,0) + val dw_b_enc1 = b_enc.io.cls + val dw_a_enc = Cat (0.U, dw_a_enc1) + val dw_b_enc = Cat (0.U, dw_b_enc1) val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W) - val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0)) - shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) === "b111".U) & !io.cancel - val list = Array(27,27,27,27,27,27,24,24,24,21,21,21,18,18,18,15,15,15,12,12,12,9,9,9,6,6,6,3,0,0,0,0) - shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U)) - shortq_shift := Mux(!shortq_enable,0.U,shortq_decode) - b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1) - valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode) - control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode) - by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode) - shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode) - shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode) - finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode) - count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode) + val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0)) + shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) === "b111".U) & !io.cancel + val list = Array(27,27,27,27,27,27,24,24,24,21,21,21,18,18,18,15,15,15,12,12,12,9,9,9,6,6,6,3,0,0,0,0) + shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U)) + shortq_shift := Mux(!shortq_enable,0.U,shortq_decode) + b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1) + valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode) + control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode) + by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode) + shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode) + shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode) + finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode) + count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode) - a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode) - b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode) - r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode) - q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode) + a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode) + b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode) + r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode) + q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode) } /////////////////////////////////////////////// 4 BIT FULL DIVIDER////////////////////////////////// class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib { val io = IO(new Bundle { - val scan_mode = Input(Bool()) - val cancel = Input(Bool()) - val valid_in = Input(Bool()) - val signed_in = Input(Bool()) - val rem_in = Input(Bool()) + val scan_mode = Input(Bool()) + val cancel = Input(Bool()) + val valid_in = Input(Bool()) + val signed_in = Input(Bool()) + val rem_in = Input(Bool()) val dividend_in = Input(UInt(32.W)) - val divisor_in = Input(UInt(32.W)) - val data_out = Output(UInt(32.W)) - val valid_out = Output(UInt(1.W)) + val divisor_in = Input(UInt(32.W)) + val data_out = Output(UInt(32.W)) + val valid_out = Output(UInt(1.W)) }) val valid_ff = WireInit(Bool(),init=false.B) @@ -774,7 +773,7 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib val shortq_shift = WireInit(0.U(5.W)) val shortq_decode = WireInit(0.U(5.W)) val shortq_shift_ff = WireInit(0.U(5.W)) - val valid_ff_in = io.valid_in & !io.cancel + val valid_ff_in = io.valid_in & !io.cancel val control_in = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in & io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in)) val dividend_sign_ff = control_ff(2) val divisor_sign_ff = control_ff(1) @@ -798,22 +797,22 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib val b_enable = io.valid_in | b_twos_comp val rq_enable = io.valid_in | valid_ff | running_state val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case - val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff)) - val adder1_out = Cat(r_ff(30,0),a_ff(31,28)) + b_ff(34,0) - val adder2_out = Cat(r_ff(31,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U) - val adder3_out = Cat(r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U) + b_ff(36,0) - val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) - val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff - val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) - val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff - val adder8_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) - val adder9_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + b_ff - val adder10_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(36,0),0.U) - val adder11_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(36,0),0.U) + b_ff - val adder12_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) - val adder13_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff - val adder14_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) - val adder15_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff + val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff)) + val adder1_out = Cat(r_ff(30,0),a_ff(31,28)) + b_ff(34,0) + val adder2_out = Cat(r_ff(31,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U) + val adder3_out = Cat(r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U) + b_ff(36,0) + val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff + val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff + val adder8_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + val adder9_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + b_ff + val adder10_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(36,0),0.U) + val adder11_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(36,0),0.U) + b_ff + val adder12_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + val adder13_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff + val adder14_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + val adder15_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff quotient_raw := Cat( (!adder15_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder15_out === 0.U)), @@ -834,29 +833,24 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib quotient_new := Cat( (Mux1H((8 to 14).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U)) | (quotient_raw(15)===1.U)), - - ( quotient_raw(15,4) === "b000000000001".U(12.W))| ( quotient_raw(15,5) === "b00000000001".U(11.W)) | ( quotient_raw(15,6) === "b0000000001".U(10.W)) | - ( quotient_raw(15,7) === "b000000001".U(9.W)) | ( quotient_raw(15,12)=== "b0001".U(4.W)) | ( quotient_raw(15,13)=== "b001".U(3.W)) | - ( quotient_raw(15,14)=== "b01".U(2.W)) | ( quotient_raw(15) === "b1".U), - - ( quotient_raw(15,2) === "b00000000000001".U(14.W))| ( quotient_raw(15,3) === "b0000000000001".U(13.W)) | ( quotient_raw(15,6) === "b0000000001".U(10.W)) | - ( quotient_raw(15,7) === "b000000001".U(9.W)) | ( quotient_raw(15,10)=== "b000001".U(6.W)) | ( quotient_raw(15,11)=== "b00001".U(5.W)) | - ( quotient_raw(15,14)=== "b01".U(2.W)) | ( quotient_raw(15) === "b1".U), - + Mux1H (Seq(( quotient_raw(15,4) === "b000000000001".U(12.W)) -> 1.U, ( quotient_raw(15,5) === "b00000000001".U(11.W)) -> 1.U, ( quotient_raw(15,6) === "b0000000001".U(10.W)) -> 1.U, ( quotient_raw(15,7) === "b000000001".U(9.W)) -> 1.U, + ( quotient_raw(15,12)=== "b0001".U(4.W)) -> 1.U, ( quotient_raw(15,13)=== "b001".U(3.W)) -> 1.U, ( quotient_raw(15,14)=== "b01".U(2.W)) -> 1.U, ( quotient_raw(15) === "b1".U) -> 1.U)), + Mux1H(Seq(( quotient_raw(15,2) === "b00000000000001".U(14.W)) -> 1.U, ( quotient_raw(15,3) === "b0000000000001".U(13.W)) -> 1.U, ( quotient_raw(15,6) === "b0000000001".U(10.W)) -> 1.U, ( quotient_raw(15,7) === "b000000001".U(9.W)) -> 1.U, + ( quotient_raw(15,10)=== "b000001".U(6.W)) -> 1.U, ( quotient_raw(15,11)=== "b00001".U(5.W)) -> 1.U, ( quotient_raw(15,14)=== "b01".U(2.W)) -> 1.U, ( quotient_raw(15) === "b1".U) -> 1.U)), (Mux1H((1 to 13 by 2).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U)) | (quotient_raw(15)===1.U) )) val twos_comp_in = Mux1H(Seq ( twos_comp_q_sel -> q_ff, - twos_comp_b_sel -> b_ff(31,0) + twos_comp_b_sel -> b_ff(31,0) )) val twos_comp_out = rvtwoscomp(twos_comp_in) val a_in = Mux1H(Seq ( (!a_shift & !shortq_enable_ff).asBool -> io.dividend_in(31,0), - a_shift -> Cat(a_ff(27,0),0.U(4.W)), - shortq_enable_ff -> ar_shifted(31,0) + a_shift -> Cat(a_ff(27,0),0.U(4.W)), + shortq_enable_ff -> ar_shifted(31,0) )) val b_in = Mux1H(Seq ( !b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)), - b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0)) + b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0)) )) val r_in = Mux1H (Seq( r_sign_sel -> Fill(33,1.U), @@ -880,15 +874,15 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib by_zero_case -> Cat(0.U,a_ff(31,0)) )) val q_in = Mux1H (Seq( - !valid_ff -> Cat(q_ff(27,0),quotient_new), + !valid_ff -> Cat(q_ff(27,0),quotient_new), smallnum_case -> Cat(0.U(28.W),smallnum), by_zero_case -> Fill(32,1.U) )) io.valid_out := finish_ff & !io.cancel io.data_out := Mux1H(Seq( (!rem_ff & !twos_comp_q_sel).asBool() -> q_ff, - rem_ff -> r_ff(31,0), - twos_comp_q_sel -> twos_comp_out + rem_ff -> r_ff(31,0), + twos_comp_q_sel -> twos_comp_out )) def pat1(x : List[Int], y : List[Int]) = { val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_) @@ -916,33 +910,33 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib val shortq_dividend = Cat(dividend_sign_ff,a_ff(31,0)) - val a_enc = Module(new exu_div_cls) - a_enc.io.operand := shortq_dividend - val dw_a_enc1 = a_enc.io.cls - val b_enc = Module(new exu_div_cls) - b_enc.io.operand := b_ff(32,0) - val dw_b_enc1 = b_enc.io.cls - val dw_a_enc = Cat (0.U, dw_a_enc1) - val dw_b_enc = Cat (0.U, dw_b_enc1) - val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W) - val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0)) - shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) === "b111".U) & !io.cancel - val list = Array(28,28,28,28,24,24,24,24,20,20,20,20,16,16,16,16,12,12,12,12,8,8,8,8,4,4,4,4,0,0,0,0) - shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U)) - shortq_shift := Mux(!shortq_enable,0.U,shortq_decode) - b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1) - valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode) - control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode) - by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode) - shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode) - shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode) - finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode) - count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode) + val a_enc = Module(new exu_div_cls) + a_enc.io.operand := shortq_dividend + val dw_a_enc1 = a_enc.io.cls + val b_enc = Module(new exu_div_cls) + b_enc.io.operand := b_ff(32,0) + val dw_b_enc1 = b_enc.io.cls + val dw_a_enc = Cat (0.U, dw_a_enc1) + val dw_b_enc = Cat (0.U, dw_b_enc1) + val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W) + val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0)) + shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) === "b111".U) & !io.cancel + val list = Array(28,28,28,28,24,24,24,24,20,20,20,20,16,16,16,16,12,12,12,12,8,8,8,8,4,4,4,4,0,0,0,0) + shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U)) + shortq_shift := Mux(!shortq_enable,0.U,shortq_decode) + b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1) + valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode) + control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode) + by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode) + shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode) + shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode) + finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode) + count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode) - a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode) - b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode) - r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode) - q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode) + a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode) + b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode) + r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode) + q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode) } class exu_div_cls extends Module{ @@ -957,5 +951,5 @@ class exu_div_cls extends Module{ when(io.operand(31,0) === "hffffffff".U) { cls_ones := 31.U} .otherwise{cls_ones := Mux1H((1 until 32).map(i=> (io.operand(31,31-i) === Cat(Fill(i,1.U),0.U)).asBool -> (i-1).U ))} - io.cls := Mux(io.operand(32),cls_ones,cls_zeros) -} \ No newline at end of file + io.cls := Mux(io.operand(32),cls_ones,cls_zeros) +} \ No newline at end of file diff --git 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