diff --git a/el2_ifu_aln_ctl.fir b/el2_ifu_aln_ctl.fir
index 071ed1c6..c554f7dc 100644
--- a/el2_ifu_aln_ctl.fir
+++ b/el2_ifu_aln_ctl.fir
@@ -1996,7 +1996,7 @@ circuit el2_ifu_aln_ctl :
   module el2_ifu_aln_ctl : 
     input clock : Clock
     input reset : UInt<1>
-    output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<32>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<32>, way : UInt<1>, ret : UInt<1>}}
+    output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<32>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}
     
     wire error_stall_in : UInt<1>
     error_stall_in <= UInt<1>("h00")
@@ -2905,34 +2905,34 @@ circuit el2_ifu_aln_ctl :
     wire _T_671 : UInt<1> @[Mux.scala 27:72]
     _T_671 <= _T_670 @[Mux.scala 27:72]
     io.ifu_i0_dbecc <= _T_671 @[el2_ifu_aln_ctl.scala 330:19]
-    node _T_672 = bits(f0pc, 8, 1) @[el2_lib.scala 186:12]
-    node _T_673 = bits(f0pc, 16, 9) @[el2_lib.scala 186:50]
-    node _T_674 = xor(_T_672, _T_673) @[el2_lib.scala 186:46]
-    node _T_675 = bits(f0pc, 24, 17) @[el2_lib.scala 186:88]
-    node firstpc_hash = xor(_T_674, _T_675) @[el2_lib.scala 186:84]
-    node _T_676 = bits(secondpc, 8, 1) @[el2_lib.scala 186:12]
-    node _T_677 = bits(secondpc, 16, 9) @[el2_lib.scala 186:50]
-    node _T_678 = xor(_T_676, _T_677) @[el2_lib.scala 186:46]
-    node _T_679 = bits(secondpc, 24, 17) @[el2_lib.scala 186:88]
-    node secondpc_hash = xor(_T_678, _T_679) @[el2_lib.scala 186:84]
-    node _T_680 = bits(f0pc, 13, 9) @[el2_lib.scala 177:32]
-    node _T_681 = bits(f0pc, 18, 14) @[el2_lib.scala 177:32]
-    node _T_682 = bits(f0pc, 23, 19) @[el2_lib.scala 177:32]
-    wire _T_683 : UInt<5>[3] @[el2_lib.scala 177:24]
-    _T_683[0] <= _T_680 @[el2_lib.scala 177:24]
-    _T_683[1] <= _T_681 @[el2_lib.scala 177:24]
-    _T_683[2] <= _T_682 @[el2_lib.scala 177:24]
-    node _T_684 = xor(_T_683[0], _T_683[1]) @[el2_lib.scala 177:111]
-    node firstbrtag_hash = xor(_T_684, _T_683[2]) @[el2_lib.scala 177:111]
-    node _T_685 = bits(secondpc, 13, 9) @[el2_lib.scala 177:32]
-    node _T_686 = bits(secondpc, 18, 14) @[el2_lib.scala 177:32]
-    node _T_687 = bits(secondpc, 23, 19) @[el2_lib.scala 177:32]
-    wire _T_688 : UInt<5>[3] @[el2_lib.scala 177:24]
-    _T_688[0] <= _T_685 @[el2_lib.scala 177:24]
-    _T_688[1] <= _T_686 @[el2_lib.scala 177:24]
-    _T_688[2] <= _T_687 @[el2_lib.scala 177:24]
-    node _T_689 = xor(_T_688[0], _T_688[1]) @[el2_lib.scala 177:111]
-    node secondbrtag_hash = xor(_T_689, _T_688[2]) @[el2_lib.scala 177:111]
+    node _T_672 = bits(f0pc, 8, 1) @[el2_lib.scala 191:12]
+    node _T_673 = bits(f0pc, 16, 9) @[el2_lib.scala 191:50]
+    node _T_674 = xor(_T_672, _T_673) @[el2_lib.scala 191:46]
+    node _T_675 = bits(f0pc, 24, 17) @[el2_lib.scala 191:88]
+    node firstpc_hash = xor(_T_674, _T_675) @[el2_lib.scala 191:84]
+    node _T_676 = bits(secondpc, 8, 1) @[el2_lib.scala 191:12]
+    node _T_677 = bits(secondpc, 16, 9) @[el2_lib.scala 191:50]
+    node _T_678 = xor(_T_676, _T_677) @[el2_lib.scala 191:46]
+    node _T_679 = bits(secondpc, 24, 17) @[el2_lib.scala 191:88]
+    node secondpc_hash = xor(_T_678, _T_679) @[el2_lib.scala 191:84]
+    node _T_680 = bits(f0pc, 13, 9) @[el2_lib.scala 182:32]
+    node _T_681 = bits(f0pc, 18, 14) @[el2_lib.scala 182:32]
+    node _T_682 = bits(f0pc, 23, 19) @[el2_lib.scala 182:32]
+    wire _T_683 : UInt<5>[3] @[el2_lib.scala 182:24]
+    _T_683[0] <= _T_680 @[el2_lib.scala 182:24]
+    _T_683[1] <= _T_681 @[el2_lib.scala 182:24]
+    _T_683[2] <= _T_682 @[el2_lib.scala 182:24]
+    node _T_684 = xor(_T_683[0], _T_683[1]) @[el2_lib.scala 182:111]
+    node firstbrtag_hash = xor(_T_684, _T_683[2]) @[el2_lib.scala 182:111]
+    node _T_685 = bits(secondpc, 13, 9) @[el2_lib.scala 182:32]
+    node _T_686 = bits(secondpc, 18, 14) @[el2_lib.scala 182:32]
+    node _T_687 = bits(secondpc, 23, 19) @[el2_lib.scala 182:32]
+    wire _T_688 : UInt<5>[3] @[el2_lib.scala 182:24]
+    _T_688[0] <= _T_685 @[el2_lib.scala 182:24]
+    _T_688[1] <= _T_686 @[el2_lib.scala 182:24]
+    _T_688[2] <= _T_687 @[el2_lib.scala 182:24]
+    node _T_689 = xor(_T_688[0], _T_688[1]) @[el2_lib.scala 182:111]
+    node secondbrtag_hash = xor(_T_689, _T_688[2]) @[el2_lib.scala 182:111]
     node _T_690 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:42]
     node _T_691 = and(first2B, _T_690) @[el2_ifu_aln_ctl.scala 340:30]
     node _T_692 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 340:70]
diff --git a/el2_ifu_aln_ctl.v b/el2_ifu_aln_ctl.v
index e73f213e..a4465583 100644
--- a/el2_ifu_aln_ctl.v
+++ b/el2_ifu_aln_ctl.v
@@ -551,7 +551,7 @@ module el2_ifu_aln_ctl(
   output        io_i0_brp_br_error,
   output        io_i0_brp_br_start_error,
   output        io_i0_brp_bank,
-  output [31:0] io_i0_brp_prett,
+  output [30:0] io_i0_brp_prett,
   output        io_i0_brp_way,
   output        io_i0_brp_ret
 );
@@ -725,7 +725,6 @@ module el2_ifu_aln_ctl(
   wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f[31:1],io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
   wire  f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 194:25]
   wire  f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 201:25]
-  wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 204:25]
   wire [5:0] _T_299 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58]
   wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_299}; // @[Cat.scala 29:58]
   reg [11:0] brdata1; // @[Reg.scala 27:20]
@@ -846,7 +845,7 @@ module el2_ifu_aln_ctl(
   assign io_i0_brp_br_error = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 358:22]
   assign io_i0_brp_br_start_error = 1'h0; // @[el2_ifu_aln_ctl.scala 352:29]
   assign io_i0_brp_bank = 1'h0; // @[el2_ifu_aln_ctl.scala 354:29]
-  assign io_i0_brp_prett = {{1'd0}, f0prett}; // @[el2_ifu_aln_ctl.scala 350:19]
+  assign io_i0_brp_prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 350:19]
   assign io_i0_brp_way = alignway[0]; // @[el2_ifu_aln_ctl.scala 344:17]
   assign io_i0_brp_ret = alignret[0]; // @[el2_ifu_aln_ctl.scala 342:17]
   assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 101:23]
diff --git a/el2_ifu_mem_ctl.anno.json b/el2_ifu_mem_ctl.anno.json
index c2ed12d7..ff1d29fd 100644
--- a/el2_ifu_mem_ctl.anno.json
+++ b/el2_ifu_mem_ctl.anno.json
@@ -1,8 +1,69 @@
 [
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_f",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_dma_active",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_flush_err_wb"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_async_error_start",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_type_f",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
+    "sources":[
+      "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata"
+    ]
+  },
   {
     "class":"firrtl.EmitCircuitAnnotation",
     "emitter":"firrtl.VerilogEmitter"
   },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"el2_ifu_mem_ctl.TEC_RV_ICG",
+    "resourceId":"/vsrc/TEC_RV_ICG.v"
+  },
   {
     "class":"firrtl.options.TargetDirAnnotation",
     "directory":"."
diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir
index f6604c0b..dffe6be7 100644
--- a/el2_ifu_mem_ctl.fir
+++ b/el2_ifu_mem_ctl.fir
@@ -1,83 +1,2086 @@
 ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
 circuit el2_ifu_mem_ctl : 
+  extmodule TEC_RV_ICG : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
+  extmodule TEC_RV_ICG_1 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 403:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 404:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 405:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 406:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 407:18]
+    
   module el2_ifu_mem_ctl : 
     input clock : Clock
     input reset : UInt<1>
-    output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>}
+    output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>}
     
-    io.ic_debug_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 126:20]
-    io.ic_debug_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 127:20]
-    io.ic_debug_tag_array <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 128:24]
-    io.ifu_miss_state_idle <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 129:25]
-    io.ifu_ic_mb_empty <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 130:21]
-    io.ic_dma_active <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 131:19]
-    io.ic_write_stall <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 132:20]
-    io.ifu_pmu_ic_miss <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 133:21]
-    io.ifu_pmu_ic_hit <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 134:20]
-    io.ifu_pmu_bus_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:23]
-    io.ifu_pmu_bus_busy <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:22]
-    io.ifu_pmu_bus_trxn <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:22]
-    io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:21]
-    io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:18]
-    io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:20]
-    io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:19]
-    io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:20]
-    io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:21]
-    io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:20]
-    io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:21]
-    io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:20]
-    io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:19]
-    io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:20]
-    io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 149:19]
-    io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 150:19]
-    io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 151:19]
-    io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 152:20]
-    io.ifu_axi_arvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 153:21]
-    io.ic_debug_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 154:19]
-    io.ifu_axi_arid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 155:18]
-    io.ifu_axi_araddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 156:20]
-    io.ifu_axi_arregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 157:22]
-    io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 158:19]
-    io.ifu_axi_arsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 159:20]
-    io.ifu_axi_arburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 160:21]
-    io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 161:20]
-    io.ifu_axi_arcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 162:21]
-    io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 163:20]
-    io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 164:19]
-    io.ifu_axi_rready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 165:20]
-    io.iccm_dma_ecc_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 166:24]
-    io.iccm_dma_rvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 167:21]
-    io.iccm_dma_rdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 168:20]
-    io.iccm_dma_rtag <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 169:19]
-    io.iccm_ready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 170:16]
-    io.ic_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 171:16]
-    io.ic_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 172:14]
-    io.ic_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 173:14]
-    io.ic_wr_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 174:16]
-    io.ic_wr_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 174:16]
-    io.ic_debug_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 175:22]
-    io.ifu_ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 176:26]
-    io.ic_tag_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 177:18]
-    io.iccm_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 178:18]
-    io.iccm_wren <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 179:15]
-    io.iccm_rden <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 180:15]
-    io.iccm_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 181:18]
-    io.iccm_wr_size <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 182:18]
-    io.ic_hit_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 183:14]
-    io.ic_access_fault_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 184:23]
-    io.ic_access_fault_type_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 185:28]
-    io.iccm_rd_ecc_single_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 186:28]
-    io.iccm_rd_ecc_double_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 187:28]
-    io.ic_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 188:20]
-    io.ifu_async_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 189:27]
-    io.iccm_dma_sb_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 190:23]
-    io.ic_fetch_val_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 191:20]
-    io.ic_data_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 192:15]
-    io.ic_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 193:20]
-    io.ic_sel_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 194:24]
-    io.ifu_ic_debug_rd_data_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 195:32]
-    io.iccm_buf_correct_ecc <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 196:26]
-    io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 197:27]
-    io.ic_debug_way <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 198:18]
-    io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 199:22]
+    io.ic_debug_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 128:20]
+    io.ic_debug_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 129:20]
+    io.ic_debug_tag_array <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 130:24]
+    io.ifu_miss_state_idle <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 131:25]
+    io.ifu_ic_mb_empty <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 132:21]
+    io.ic_dma_active <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 133:19]
+    io.ic_write_stall <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 134:20]
+    io.ifu_pmu_ic_miss <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:21]
+    io.ifu_pmu_ic_hit <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:20]
+    io.ifu_pmu_bus_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:23]
+    io.ifu_pmu_bus_busy <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:22]
+    io.ifu_pmu_bus_trxn <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:22]
+    io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:21]
+    io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:18]
+    io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:20]
+    io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:19]
+    io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:20]
+    io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:21]
+    io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:20]
+    io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:21]
+    io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:20]
+    io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 149:19]
+    io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 150:20]
+    io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 151:19]
+    io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 152:19]
+    io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 153:19]
+    io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 154:20]
+    io.ifu_axi_arvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 155:21]
+    io.ic_debug_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 156:19]
+    io.ifu_axi_arid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 157:18]
+    io.ifu_axi_araddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 158:20]
+    io.ifu_axi_arregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 159:22]
+    io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 160:19]
+    io.ifu_axi_arsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 161:20]
+    io.ifu_axi_arburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 162:21]
+    io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 163:20]
+    io.ifu_axi_arcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 164:21]
+    io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 165:20]
+    io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 166:19]
+    io.ifu_axi_rready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 167:20]
+    io.iccm_dma_ecc_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 168:24]
+    io.iccm_dma_rvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 169:21]
+    io.iccm_dma_rdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 170:20]
+    io.iccm_dma_rtag <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 171:19]
+    io.iccm_ready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 172:16]
+    io.ic_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 173:16]
+    io.ic_wr_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 174:14]
+    io.ic_rd_en <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 175:14]
+    io.ic_wr_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 176:16]
+    io.ic_wr_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 176:16]
+    io.ic_debug_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 177:22]
+    io.ifu_ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 178:26]
+    io.ic_tag_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 179:18]
+    io.iccm_rw_addr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 180:18]
+    io.iccm_wren <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 181:15]
+    io.iccm_rden <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 182:15]
+    io.iccm_wr_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 183:18]
+    io.iccm_wr_size <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 184:18]
+    io.ic_hit_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 185:14]
+    io.ic_access_fault_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 186:23]
+    io.ic_access_fault_type_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 187:28]
+    io.iccm_rd_ecc_single_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 188:28]
+    io.iccm_rd_ecc_double_err <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 189:28]
+    io.ic_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 190:20]
+    io.ifu_async_error_start <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 191:27]
+    io.iccm_dma_sb_error <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 192:23]
+    io.ic_fetch_val_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 193:20]
+    io.ic_data_f <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 194:15]
+    io.ic_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 195:20]
+    io.ic_sel_premux_data <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 196:24]
+    io.ifu_ic_debug_rd_data_valid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 197:32]
+    io.iccm_buf_correct_ecc <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 198:26]
+    io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 199:27]
+    io.ic_debug_way <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 200:18]
+    io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 201:22]
+    wire iccm_single_ecc_error : UInt<2>
+    iccm_single_ecc_error <= UInt<1>("h00")
+    wire ifc_fetch_req_f : UInt<1>
+    ifc_fetch_req_f <= UInt<1>("h00")
+    wire miss_pending : UInt<1>
+    miss_pending <= UInt<1>("h00")
+    wire scnd_miss_req : UInt<1>
+    scnd_miss_req <= UInt<1>("h00")
+    wire dma_iccm_req_f : UInt<1>
+    dma_iccm_req_f <= UInt<1>("h00")
+    wire iccm_correct_ecc : UInt<1>
+    iccm_correct_ecc <= UInt<1>("h00")
+    wire perr_state : UInt<3>
+    perr_state <= UInt<1>("h00")
+    wire err_stop_state : UInt<2>
+    err_stop_state <= UInt<1>("h00")
+    wire err_stop_fetch : UInt<1>
+    err_stop_fetch <= UInt<1>("h00")
+    wire miss_state : UInt<3>
+    miss_state <= UInt<1>("h00")
+    wire miss_nxtstate : UInt<3>
+    miss_nxtstate <= UInt<1>("h00")
+    wire miss_state_en : UInt<1>
+    miss_state_en <= UInt<1>("h00")
+    wire ifu_bus_rsp_valid : UInt<1>
+    ifu_bus_rsp_valid <= UInt<1>("h00")
+    wire bus_ifu_bus_clk_en : UInt<1>
+    bus_ifu_bus_clk_en <= UInt<1>("h00")
+    wire ifu_bus_rsp_ready : UInt<1>
+    ifu_bus_rsp_ready <= UInt<1>("h00")
+    wire uncacheable_miss_ff : UInt<1>
+    uncacheable_miss_ff <= UInt<1>("h00")
+    wire ic_act_miss_f : UInt<1>
+    ic_act_miss_f <= UInt<1>("h00")
+    wire ic_byp_hit_f : UInt<1>
+    ic_byp_hit_f <= UInt<1>("h00")
+    wire bus_new_data_beat_count : UInt<3>
+    bus_new_data_beat_count <= UInt<1>("h00")
+    wire bus_ifu_wr_en_ff : UInt<1>
+    bus_ifu_wr_en_ff <= UInt<1>("h00")
+    wire last_beat : UInt<1>
+    last_beat <= UInt<1>("h00")
+    wire last_data_recieved_ff : UInt<1>
+    last_data_recieved_ff <= UInt<1>("h00")
+    wire stream_eol_f : UInt<1>
+    stream_eol_f <= UInt<1>("h00")
+    wire ic_miss_under_miss_f : UInt<1>
+    ic_miss_under_miss_f <= UInt<1>("h00")
+    wire ic_ignore_2nd_miss_f : UInt<1>
+    ic_ignore_2nd_miss_f <= UInt<1>("h00")
+    reg flush_final_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 234:30]
+    flush_final_f <= io.exu_flush_final @[el2_ifu_mem_ctl.scala 234:30]
+    node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 235:53]
+    node _T_1 = or(_T, miss_pending) @[el2_ifu_mem_ctl.scala 235:71]
+    node _T_2 = or(_T_1, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 235:86]
+    node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[el2_ifu_mem_ctl.scala 235:107]
+    node debug_c1_clken = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 236:42]
+    inst rvclkhdr of rvclkhdr @[el2_lib.scala 412:22]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr.io.en <= debug_c1_clken @[el2_lib.scala 414:16]
+    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    node _T_3 = bits(fetch_bf_f_c1_clken, 0, 0) @[el2_ifu_mem_ctl.scala 238:63]
+    inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 412:22]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 413:17]
+    rvclkhdr_1.io.en <= _T_3 @[el2_lib.scala 414:16]
+    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 415:23]
+    node _T_4 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 239:52]
+    node _T_5 = bits(dma_iccm_req_f, 0, 0) @[el2_ifu_mem_ctl.scala 239:78]
+    node _T_6 = and(_T_4, _T_5) @[el2_ifu_mem_ctl.scala 239:55]
+    io.iccm_dma_sb_error <= _T_6 @[el2_ifu_mem_ctl.scala 239:24]
+    node _T_7 = or(io.iccm_rd_ecc_single_err, io.ic_error_start) @[el2_ifu_mem_ctl.scala 240:57]
+    io.ifu_async_error_start <= _T_7 @[el2_ifu_mem_ctl.scala 240:28]
+    node _T_8 = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 241:54]
+    node _T_9 = or(iccm_correct_ecc, _T_8) @[el2_ifu_mem_ctl.scala 241:40]
+    node _T_10 = eq(err_stop_state, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 241:90]
+    node _T_11 = or(_T_9, _T_10) @[el2_ifu_mem_ctl.scala 241:72]
+    node _T_12 = or(_T_11, err_stop_fetch) @[el2_ifu_mem_ctl.scala 241:112]
+    node _T_13 = or(_T_12, io.dec_tlu_flush_err_wb) @[el2_ifu_mem_ctl.scala 241:129]
+    io.ic_dma_active <= _T_13 @[el2_ifu_mem_ctl.scala 241:20]
+    node _T_14 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 242:44]
+    node _T_15 = and(_T_14, ifu_bus_rsp_ready) @[el2_ifu_mem_ctl.scala 242:65]
+    node _T_16 = andr(bus_new_data_beat_count) @[el2_ifu_mem_ctl.scala 242:111]
+    node _T_17 = and(_T_15, _T_16) @[el2_ifu_mem_ctl.scala 242:85]
+    node _T_18 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 243:39]
+    node _T_19 = eq(miss_nxtstate, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 243:71]
+    node _T_20 = or(_T_18, _T_19) @[el2_ifu_mem_ctl.scala 243:55]
+    node _T_21 = dshr(uncacheable_miss_ff, _T_20) @[el2_ifu_mem_ctl.scala 243:26]
+    node _T_22 = bits(_T_21, 0, 0) @[el2_ifu_mem_ctl.scala 243:26]
+    node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 243:5]
+    node _T_24 = and(_T_17, _T_23) @[el2_ifu_mem_ctl.scala 242:116]
+    node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 243:91]
+    node scnd_miss_req_in = and(_T_24, _T_25) @[el2_ifu_mem_ctl.scala 243:89]
+    node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[el2_ifu_mem_ctl.scala 245:52]
+    node _T_26 = eq(UInt<3>("h00"), miss_state) @[Conditional.scala 37:30]
+    when _T_26 : @[Conditional.scala 40:58]
+      node _T_27 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 249:45]
+      node _T_28 = and(ic_act_miss_f, _T_27) @[el2_ifu_mem_ctl.scala 249:43]
+      node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_mem_ctl.scala 249:66]
+      node _T_30 = mux(_T_29, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 249:27]
+      miss_nxtstate <= _T_30 @[el2_ifu_mem_ctl.scala 249:21]
+      node _T_31 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 250:40]
+      node _T_32 = and(ic_act_miss_f, _T_31) @[el2_ifu_mem_ctl.scala 250:38]
+      miss_state_en <= _T_32 @[el2_ifu_mem_ctl.scala 250:21]
+      skip @[Conditional.scala 40:58]
+    else : @[Conditional.scala 39:67]
+      node _T_33 = eq(UInt<3>("h01"), miss_state) @[Conditional.scala 37:30]
+      when _T_33 : @[Conditional.scala 39:67]
+        node _T_34 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 252:112]
+        node _T_35 = or(last_data_recieved_ff, _T_34) @[el2_ifu_mem_ctl.scala 252:92]
+        node _T_36 = and(ic_byp_hit_f, _T_35) @[el2_ifu_mem_ctl.scala 252:66]
+        node _T_37 = and(_T_36, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 252:126]
+        node _T_38 = or(io.dec_tlu_force_halt, _T_37) @[el2_ifu_mem_ctl.scala 252:51]
+        node _T_39 = bits(_T_38, 0, 0) @[el2_ifu_mem_ctl.scala 252:150]
+        node _T_40 = eq(last_data_recieved_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 253:30]
+        node _T_41 = and(ic_byp_hit_f, _T_40) @[el2_ifu_mem_ctl.scala 253:27]
+        node _T_42 = and(_T_41, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 253:53]
+        node _T_43 = bits(_T_42, 0, 0) @[el2_ifu_mem_ctl.scala 253:77]
+        node _T_44 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 254:16]
+        node _T_45 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 254:32]
+        node _T_46 = and(_T_44, _T_45) @[el2_ifu_mem_ctl.scala 254:30]
+        node _T_47 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 254:72]
+        node _T_48 = and(_T_46, _T_47) @[el2_ifu_mem_ctl.scala 254:52]
+        node _T_49 = and(_T_48, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 254:85]
+        node _T_50 = bits(_T_49, 0, 0) @[el2_ifu_mem_ctl.scala 254:109]
+        node _T_51 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 255:36]
+        node _T_52 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 255:51]
+        node _T_53 = and(_T_51, _T_52) @[el2_ifu_mem_ctl.scala 255:49]
+        node _T_54 = bits(_T_53, 0, 0) @[el2_ifu_mem_ctl.scala 255:73]
+        node _T_55 = or(ic_byp_hit_f, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 256:34]
+        node _T_56 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:56]
+        node _T_57 = and(_T_55, _T_56) @[el2_ifu_mem_ctl.scala 256:54]
+        node _T_58 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 256:97]
+        node _T_59 = eq(_T_58, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:78]
+        node _T_60 = and(_T_57, _T_59) @[el2_ifu_mem_ctl.scala 256:76]
+        node _T_61 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:112]
+        node _T_62 = and(_T_60, _T_61) @[el2_ifu_mem_ctl.scala 256:110]
+        node _T_63 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:136]
+        node _T_64 = and(_T_62, _T_63) @[el2_ifu_mem_ctl.scala 256:134]
+        node _T_65 = bits(_T_64, 0, 0) @[el2_ifu_mem_ctl.scala 256:158]
+        node _T_66 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:22]
+        node _T_67 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:40]
+        node _T_68 = and(_T_66, _T_67) @[el2_ifu_mem_ctl.scala 257:37]
+        node _T_69 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 257:81]
+        node _T_70 = and(_T_68, _T_69) @[el2_ifu_mem_ctl.scala 257:60]
+        node _T_71 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:102]
+        node _T_72 = and(_T_70, _T_71) @[el2_ifu_mem_ctl.scala 257:100]
+        node _T_73 = bits(_T_72, 0, 0) @[el2_ifu_mem_ctl.scala 257:124]
+        node _T_74 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 258:44]
+        node _T_75 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 258:89]
+        node _T_76 = eq(_T_75, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 258:70]
+        node _T_77 = and(_T_74, _T_76) @[el2_ifu_mem_ctl.scala 258:68]
+        node _T_78 = bits(_T_77, 0, 0) @[el2_ifu_mem_ctl.scala 258:103]
+        node _T_79 = mux(_T_78, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 258:22]
+        node _T_80 = mux(_T_73, UInt<3>("h00"), _T_79) @[el2_ifu_mem_ctl.scala 257:20]
+        node _T_81 = mux(_T_65, UInt<3>("h06"), _T_80) @[el2_ifu_mem_ctl.scala 256:18]
+        node _T_82 = mux(_T_54, UInt<3>("h00"), _T_81) @[el2_ifu_mem_ctl.scala 255:16]
+        node _T_83 = mux(_T_50, UInt<3>("h01"), _T_82) @[el2_ifu_mem_ctl.scala 254:14]
+        node _T_84 = mux(_T_43, UInt<3>("h03"), _T_83) @[el2_ifu_mem_ctl.scala 253:12]
+        node _T_85 = mux(_T_39, UInt<3>("h00"), _T_84) @[el2_ifu_mem_ctl.scala 252:27]
+        miss_nxtstate <= _T_85 @[el2_ifu_mem_ctl.scala 252:21]
+        node _T_86 = or(io.dec_tlu_force_halt, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 259:46]
+        node _T_87 = or(_T_86, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 259:67]
+        node _T_88 = or(_T_87, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 259:82]
+        node _T_89 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 259:125]
+        node _T_90 = or(_T_88, _T_89) @[el2_ifu_mem_ctl.scala 259:105]
+        node _T_91 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 259:160]
+        node _T_92 = and(bus_ifu_wr_en_ff, _T_91) @[el2_ifu_mem_ctl.scala 259:158]
+        node _T_93 = or(_T_90, _T_92) @[el2_ifu_mem_ctl.scala 259:138]
+        miss_state_en <= _T_93 @[el2_ifu_mem_ctl.scala 259:21]
+        skip @[Conditional.scala 39:67]
+      else : @[Conditional.scala 39:67]
+        node _T_94 = eq(UInt<3>("h04"), miss_state) @[Conditional.scala 37:30]
+        when _T_94 : @[Conditional.scala 39:67]
+          miss_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 262:21]
+          node _T_95 = or(io.exu_flush_final, flush_final_f) @[el2_ifu_mem_ctl.scala 263:43]
+          node _T_96 = or(_T_95, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 263:59]
+          node _T_97 = or(_T_96, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 263:74]
+          miss_state_en <= _T_97 @[el2_ifu_mem_ctl.scala 263:21]
+          skip @[Conditional.scala 39:67]
+        else : @[Conditional.scala 39:67]
+          node _T_98 = eq(UInt<3>("h06"), miss_state) @[Conditional.scala 37:30]
+          when _T_98 : @[Conditional.scala 39:67]
+            node _T_99 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 266:49]
+            node _T_100 = or(_T_99, stream_eol_f) @[el2_ifu_mem_ctl.scala 266:72]
+            node _T_101 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 266:108]
+            node _T_102 = eq(_T_101, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 266:89]
+            node _T_103 = and(_T_100, _T_102) @[el2_ifu_mem_ctl.scala 266:87]
+            node _T_104 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 266:124]
+            node _T_105 = and(_T_103, _T_104) @[el2_ifu_mem_ctl.scala 266:122]
+            node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_mem_ctl.scala 266:148]
+            node _T_107 = mux(_T_106, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 266:27]
+            miss_nxtstate <= _T_107 @[el2_ifu_mem_ctl.scala 266:21]
+            node _T_108 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 267:43]
+            node _T_109 = or(_T_108, stream_eol_f) @[el2_ifu_mem_ctl.scala 267:67]
+            node _T_110 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 267:105]
+            node _T_111 = or(_T_109, _T_110) @[el2_ifu_mem_ctl.scala 267:84]
+            node _T_112 = or(_T_111, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 267:118]
+            miss_state_en <= _T_112 @[el2_ifu_mem_ctl.scala 267:21]
+            skip @[Conditional.scala 39:67]
+          else : @[Conditional.scala 39:67]
+            node _T_113 = eq(UInt<3>("h03"), miss_state) @[Conditional.scala 37:30]
+            when _T_113 : @[Conditional.scala 39:67]
+              node _T_114 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 270:69]
+              node _T_115 = eq(_T_114, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 270:50]
+              node _T_116 = and(io.exu_flush_final, _T_115) @[el2_ifu_mem_ctl.scala 270:48]
+              node _T_117 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 270:84]
+              node _T_118 = and(_T_116, _T_117) @[el2_ifu_mem_ctl.scala 270:82]
+              node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_mem_ctl.scala 270:108]
+              node _T_120 = mux(_T_119, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 270:27]
+              miss_nxtstate <= _T_120 @[el2_ifu_mem_ctl.scala 270:21]
+              node _T_121 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 271:63]
+              node _T_122 = or(io.exu_flush_final, _T_121) @[el2_ifu_mem_ctl.scala 271:43]
+              node _T_123 = or(_T_122, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 271:76]
+              miss_state_en <= _T_123 @[el2_ifu_mem_ctl.scala 271:21]
+              skip @[Conditional.scala 39:67]
+            else : @[Conditional.scala 39:67]
+              node _T_124 = eq(UInt<3>("h02"), miss_state) @[Conditional.scala 37:30]
+              when _T_124 : @[Conditional.scala 39:67]
+                node _T_125 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 274:71]
+                node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 274:52]
+                node _T_127 = and(ic_miss_under_miss_f, _T_126) @[el2_ifu_mem_ctl.scala 274:50]
+                node _T_128 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 274:86]
+                node _T_129 = and(_T_127, _T_128) @[el2_ifu_mem_ctl.scala 274:84]
+                node _T_130 = bits(_T_129, 0, 0) @[el2_ifu_mem_ctl.scala 274:110]
+                node _T_131 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 275:56]
+                node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 275:37]
+                node _T_133 = and(ic_ignore_2nd_miss_f, _T_132) @[el2_ifu_mem_ctl.scala 275:35]
+                node _T_134 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 275:71]
+                node _T_135 = and(_T_133, _T_134) @[el2_ifu_mem_ctl.scala 275:69]
+                node _T_136 = bits(_T_135, 0, 0) @[el2_ifu_mem_ctl.scala 275:95]
+                node _T_137 = mux(_T_136, UInt<3>("h07"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 275:12]
+                node _T_138 = mux(_T_130, UInt<3>("h05"), _T_137) @[el2_ifu_mem_ctl.scala 274:27]
+                miss_nxtstate <= _T_138 @[el2_ifu_mem_ctl.scala 274:21]
+                node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 276:42]
+                node _T_140 = or(_T_139, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 276:55]
+                node _T_141 = or(_T_140, ic_ignore_2nd_miss_f) @[el2_ifu_mem_ctl.scala 276:78]
+                node _T_142 = or(_T_141, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 276:101]
+                miss_state_en <= _T_142 @[el2_ifu_mem_ctl.scala 276:21]
+                skip @[Conditional.scala 39:67]
+              else : @[Conditional.scala 39:67]
+                node _T_143 = eq(UInt<3>("h05"), miss_state) @[Conditional.scala 37:30]
+                when _T_143 : @[Conditional.scala 39:67]
+                  node _T_144 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 280:31]
+                  node _T_145 = bits(_T_144, 0, 0) @[el2_ifu_mem_ctl.scala 280:44]
+                  node _T_146 = mux(_T_145, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 280:12]
+                  node _T_147 = mux(io.exu_flush_final, _T_146, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 279:62]
+                  node _T_148 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_147) @[el2_ifu_mem_ctl.scala 279:27]
+                  miss_nxtstate <= _T_148 @[el2_ifu_mem_ctl.scala 279:21]
+                  node _T_149 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 281:42]
+                  node _T_150 = or(_T_149, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 281:55]
+                  node _T_151 = or(_T_150, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 281:76]
+                  miss_state_en <= _T_151 @[el2_ifu_mem_ctl.scala 281:21]
+                  skip @[Conditional.scala 39:67]
+                else : @[Conditional.scala 39:67]
+                  node _T_152 = eq(UInt<3>("h07"), miss_state) @[Conditional.scala 37:30]
+                  when _T_152 : @[Conditional.scala 39:67]
+                    node _T_153 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 285:31]
+                    node _T_154 = bits(_T_153, 0, 0) @[el2_ifu_mem_ctl.scala 285:44]
+                    node _T_155 = mux(_T_154, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 285:12]
+                    node _T_156 = mux(io.exu_flush_final, _T_155, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 284:62]
+                    node _T_157 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_156) @[el2_ifu_mem_ctl.scala 284:27]
+                    miss_nxtstate <= _T_157 @[el2_ifu_mem_ctl.scala 284:21]
+                    node _T_158 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 286:42]
+                    node _T_159 = or(_T_158, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 286:55]
+                    node _T_160 = or(_T_159, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 286:76]
+                    miss_state_en <= _T_160 @[el2_ifu_mem_ctl.scala 286:21]
+                    skip @[Conditional.scala 39:67]
+    node _T_161 = bits(miss_state_en, 0, 0) @[el2_ifu_mem_ctl.scala 289:61]
+    reg _T_162 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_161 : @[Reg.scala 28:19]
+      _T_162 <= miss_nxtstate @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    miss_state <= _T_162 @[el2_ifu_mem_ctl.scala 289:14]
+    wire crit_byp_hit_f : UInt<1>
+    crit_byp_hit_f <= UInt<1>("h00")
+    wire way_status_mb_scnd_ff : UInt<1>
+    way_status_mb_scnd_ff <= UInt<1>("h00")
+    wire way_status : UInt<1>
+    way_status <= UInt<1>("h00")
+    wire tagv_mb_scnd_ff : UInt<2>
+    tagv_mb_scnd_ff <= UInt<1>("h00")
+    wire ic_tag_valid : UInt<2>
+    ic_tag_valid <= UInt<1>("h00")
+    wire uncacheable_miss_scnd_ff : UInt<1>
+    uncacheable_miss_scnd_ff <= UInt<1>("h00")
+    wire imb_scnd_ff : UInt<31>
+    imb_scnd_ff <= UInt<1>("h00")
+    wire reset_all_tags : UInt<1>
+    reset_all_tags <= UInt<1>("h00")
+    wire bus_rd_addr_count : UInt<3>
+    bus_rd_addr_count <= UInt<1>("h00")
+    wire ifu_bus_rid_ff : UInt<3>
+    ifu_bus_rid_ff <= UInt<1>("h00")
+    node _T_163 = neq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 300:30]
+    miss_pending <= _T_163 @[el2_ifu_mem_ctl.scala 300:16]
+    node _T_164 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 301:39]
+    node _T_165 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 301:73]
+    node _T_166 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 301:95]
+    node _T_167 = and(_T_165, _T_166) @[el2_ifu_mem_ctl.scala 301:93]
+    node crit_wd_byp_ok_ff = or(_T_164, _T_167) @[el2_ifu_mem_ctl.scala 301:58]
+    node _T_168 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 302:57]
+    node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 302:38]
+    node _T_170 = and(miss_pending, _T_169) @[el2_ifu_mem_ctl.scala 302:36]
+    node _T_171 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 302:86]
+    node _T_172 = and(_T_171, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 302:106]
+    node _T_173 = eq(_T_172, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 302:72]
+    node _T_174 = and(_T_170, _T_173) @[el2_ifu_mem_ctl.scala 302:70]
+    node _T_175 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 303:37]
+    node _T_176 = and(_T_175, crit_byp_hit_f) @[el2_ifu_mem_ctl.scala 303:57]
+    node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 303:23]
+    node _T_178 = and(_T_174, _T_177) @[el2_ifu_mem_ctl.scala 302:128]
+    node _T_179 = or(_T_178, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 303:77]
+    node _T_180 = eq(miss_nxtstate, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 304:36]
+    node _T_181 = and(miss_pending, _T_180) @[el2_ifu_mem_ctl.scala 304:19]
+    node sel_hold_imb = or(_T_179, _T_181) @[el2_ifu_mem_ctl.scala 303:93]
+    node _T_182 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 306:40]
+    node _T_183 = or(_T_182, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 306:57]
+    node _T_184 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 306:83]
+    node sel_hold_imb_scnd = and(_T_183, _T_184) @[el2_ifu_mem_ctl.scala 306:81]
+    node _T_185 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 307:46]
+    node way_status_mb_scnd_in = mux(_T_185, way_status_mb_scnd_ff, way_status) @[el2_ifu_mem_ctl.scala 307:34]
+    node _T_186 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 309:40]
+    node _T_187 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 309:96]
+    node _T_188 = bits(_T_187, 0, 0) @[Bitwise.scala 72:15]
+    node _T_189 = mux(_T_188, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_190 = and(_T_189, ic_tag_valid) @[el2_ifu_mem_ctl.scala 309:113]
+    node tagv_mb_scnd_in = mux(_T_186, tagv_mb_scnd_ff, _T_190) @[el2_ifu_mem_ctl.scala 309:28]
+    node _T_191 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 310:56]
+    node uncacheable_miss_scnd_in = mux(_T_191, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 310:37]
+    reg _T_192 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 311:38]
+    _T_192 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 311:38]
+    uncacheable_miss_scnd_ff <= _T_192 @[el2_ifu_mem_ctl.scala 311:28]
+    node _T_193 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 312:43]
+    node imb_scnd_in = mux(_T_193, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 312:24]
+    reg _T_194 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 313:25]
+    _T_194 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 313:25]
+    imb_scnd_ff <= _T_194 @[el2_ifu_mem_ctl.scala 313:15]
+    reg _T_195 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 314:35]
+    _T_195 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 314:35]
+    way_status_mb_scnd_ff <= _T_195 @[el2_ifu_mem_ctl.scala 314:25]
+    reg _T_196 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 315:29]
+    _T_196 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 315:29]
+    tagv_mb_scnd_ff <= _T_196 @[el2_ifu_mem_ctl.scala 315:19]
+    node _T_197 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15]
+    node _T_198 = mux(_T_197, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_198) @[el2_ifu_mem_ctl.scala 318:45]
+    wire ifc_iccm_access_f : UInt<1>
+    ifc_iccm_access_f <= UInt<1>("h00")
+    wire ifc_region_acc_fault_final_f : UInt<1>
+    ifc_region_acc_fault_final_f <= UInt<1>("h00")
+    node _T_199 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:48]
+    node _T_200 = and(ifc_fetch_req_f, _T_199) @[el2_ifu_mem_ctl.scala 321:46]
+    node _T_201 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:69]
+    node fetch_req_icache_f = and(_T_200, _T_201) @[el2_ifu_mem_ctl.scala 321:67]
+    node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 322:46]
+    node _T_202 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 323:45]
+    node _T_203 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 323:73]
+    node _T_204 = or(_T_202, _T_203) @[el2_ifu_mem_ctl.scala 323:59]
+    node _T_205 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 323:105]
+    node _T_206 = or(_T_204, _T_205) @[el2_ifu_mem_ctl.scala 323:91]
+    node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_206) @[el2_ifu_mem_ctl.scala 323:41]
+    wire stream_hit_f : UInt<1>
+    stream_hit_f <= UInt<1>("h00")
+    node _T_207 = or(crit_byp_hit_f, stream_hit_f) @[el2_ifu_mem_ctl.scala 325:35]
+    node _T_208 = and(_T_207, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 325:52]
+    node _T_209 = and(_T_208, miss_pending) @[el2_ifu_mem_ctl.scala 325:73]
+    ic_byp_hit_f <= _T_209 @[el2_ifu_mem_ctl.scala 325:16]
+    wire sel_mb_addr_ff : UInt<1>
+    sel_mb_addr_ff <= UInt<1>("h00")
+    wire imb_ff : UInt<31>
+    imb_ff <= UInt<1>("h00")
+    wire ifu_fetch_addr_int_f : UInt<31>
+    ifu_fetch_addr_int_f <= UInt<1>("h00")
+    node _T_210 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 329:35]
+    node _T_211 = and(_T_210, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 329:39]
+    node _T_212 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:62]
+    node _T_213 = and(_T_211, _T_212) @[el2_ifu_mem_ctl.scala 329:60]
+    node _T_214 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:81]
+    node _T_215 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 329:108]
+    node _T_216 = or(_T_214, _T_215) @[el2_ifu_mem_ctl.scala 329:95]
+    node _T_217 = and(_T_213, _T_216) @[el2_ifu_mem_ctl.scala 329:78]
+    node _T_218 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:128]
+    node ic_act_hit_f = and(_T_217, _T_218) @[el2_ifu_mem_ctl.scala 329:126]
+    node _T_219 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 330:37]
+    node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:23]
+    node _T_221 = or(_T_220, reset_all_tags) @[el2_ifu_mem_ctl.scala 330:41]
+    node _T_222 = and(_T_221, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 330:59]
+    node _T_223 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:82]
+    node _T_224 = and(_T_222, _T_223) @[el2_ifu_mem_ctl.scala 330:80]
+    node _T_225 = or(_T_224, scnd_miss_req) @[el2_ifu_mem_ctl.scala 330:97]
+    node _T_226 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:116]
+    node _T_227 = and(_T_225, _T_226) @[el2_ifu_mem_ctl.scala 330:114]
+    ic_act_miss_f <= _T_227 @[el2_ifu_mem_ctl.scala 330:17]
+    node _T_228 = eq(io.ic_rd_hit, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 331:28]
+    node _T_229 = or(_T_228, reset_all_tags) @[el2_ifu_mem_ctl.scala 331:42]
+    node _T_230 = and(_T_229, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 331:60]
+    node _T_231 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 331:94]
+    node _T_232 = and(_T_230, _T_231) @[el2_ifu_mem_ctl.scala 331:81]
+    node _T_233 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 332:12]
+    node _T_234 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 332:63]
+    node _T_235 = neq(_T_233, _T_234) @[el2_ifu_mem_ctl.scala 332:39]
+    node _T_236 = and(_T_232, _T_235) @[el2_ifu_mem_ctl.scala 331:111]
+    node _T_237 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:93]
+    node _T_238 = and(_T_236, _T_237) @[el2_ifu_mem_ctl.scala 332:91]
+    node _T_239 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:116]
+    node _T_240 = and(_T_238, _T_239) @[el2_ifu_mem_ctl.scala 332:114]
+    node _T_241 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 332:134]
+    node _T_242 = and(_T_240, _T_241) @[el2_ifu_mem_ctl.scala 332:132]
+    ic_miss_under_miss_f <= _T_242 @[el2_ifu_mem_ctl.scala 331:24]
+    node _T_243 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 333:42]
+    node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 333:28]
+    node _T_245 = or(_T_244, reset_all_tags) @[el2_ifu_mem_ctl.scala 333:46]
+    node _T_246 = and(_T_245, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 333:64]
+    node _T_247 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 333:99]
+    node _T_248 = and(_T_246, _T_247) @[el2_ifu_mem_ctl.scala 333:85]
+    node _T_249 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 334:13]
+    node _T_250 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 334:62]
+    node _T_251 = eq(_T_249, _T_250) @[el2_ifu_mem_ctl.scala 334:39]
+    node _T_252 = or(_T_251, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 334:91]
+    node _T_253 = and(_T_248, _T_252) @[el2_ifu_mem_ctl.scala 333:117]
+    ic_ignore_2nd_miss_f <= _T_253 @[el2_ifu_mem_ctl.scala 333:24]
+    node _T_254 = or(ic_act_hit_f, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 336:31]
+    node _T_255 = or(_T_254, ic_iccm_hit_f) @[el2_ifu_mem_ctl.scala 336:46]
+    node _T_256 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 336:94]
+    node _T_257 = or(_T_255, _T_256) @[el2_ifu_mem_ctl.scala 336:62]
+    io.ic_hit_f <= _T_257 @[el2_ifu_mem_ctl.scala 336:15]
+    node _T_258 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 337:47]
+    node _T_259 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 337:98]
+    node _T_260 = mux(_T_259, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 337:84]
+    node uncacheable_miss_in = mux(_T_258, uncacheable_miss_scnd_ff, _T_260) @[el2_ifu_mem_ctl.scala 337:32]
+    node _T_261 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 338:34]
+    node _T_262 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 338:72]
+    node _T_263 = mux(_T_262, imb_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 338:58]
+    node imb_in = mux(_T_261, imb_scnd_ff, _T_263) @[el2_ifu_mem_ctl.scala 338:19]
+    wire ifu_wr_cumulative_err_data : UInt<1>
+    ifu_wr_cumulative_err_data <= UInt<1>("h00")
+    node _T_264 = bits(imb_ff, 12, 6) @[el2_ifu_mem_ctl.scala 340:38]
+    node _T_265 = bits(imb_scnd_ff, 12, 6) @[el2_ifu_mem_ctl.scala 340:89]
+    node _T_266 = eq(_T_264, _T_265) @[el2_ifu_mem_ctl.scala 340:75]
+    node _T_267 = and(_T_266, scnd_miss_req) @[el2_ifu_mem_ctl.scala 340:127]
+    node _T_268 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 340:145]
+    node scnd_miss_index_match = and(_T_267, _T_268) @[el2_ifu_mem_ctl.scala 340:143]
+    wire way_status_mb_ff : UInt<1>
+    way_status_mb_ff <= UInt<1>("h00")
+    wire way_status_rep_new : UInt<1>
+    way_status_rep_new <= UInt<1>("h00")
+    node _T_269 = eq(scnd_miss_index_match, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 343:47]
+    node _T_270 = and(scnd_miss_req, _T_269) @[el2_ifu_mem_ctl.scala 343:45]
+    node _T_271 = bits(_T_270, 0, 0) @[el2_ifu_mem_ctl.scala 343:71]
+    node _T_272 = and(scnd_miss_req, scnd_miss_index_match) @[el2_ifu_mem_ctl.scala 344:26]
+    node _T_273 = bits(_T_272, 0, 0) @[el2_ifu_mem_ctl.scala 344:52]
+    node _T_274 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 345:26]
+    node _T_275 = mux(_T_274, way_status_mb_ff, way_status) @[el2_ifu_mem_ctl.scala 345:12]
+    node _T_276 = mux(_T_273, way_status_rep_new, _T_275) @[el2_ifu_mem_ctl.scala 344:10]
+    node way_status_mb_in = mux(_T_271, way_status_mb_scnd_ff, _T_276) @[el2_ifu_mem_ctl.scala 343:29]
+    wire replace_way_mb_any : UInt<2>
+    replace_way_mb_any <= UInt<1>("h00")
+    wire tagv_mb_ff : UInt<2>
+    tagv_mb_ff <= UInt<1>("h00")
+    node _T_277 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 348:38]
+    node _T_278 = bits(scnd_miss_index_match, 0, 0) @[Bitwise.scala 72:15]
+    node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_280 = and(_T_279, replace_way_mb_any) @[el2_ifu_mem_ctl.scala 348:110]
+    node _T_281 = or(tagv_mb_scnd_ff, _T_280) @[el2_ifu_mem_ctl.scala 348:62]
+    node _T_282 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 349:20]
+    node _T_283 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 349:77]
+    node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15]
+    node _T_285 = mux(_T_284, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_286 = and(ic_tag_valid, _T_285) @[el2_ifu_mem_ctl.scala 349:53]
+    node _T_287 = mux(_T_282, tagv_mb_ff, _T_286) @[el2_ifu_mem_ctl.scala 349:6]
+    node tagv_mb_in = mux(_T_277, _T_281, _T_287) @[el2_ifu_mem_ctl.scala 348:23]
+    wire scnd_miss_req_q : UInt<1>
+    scnd_miss_req_q <= UInt<1>("h00")
+    wire reset_ic_ff : UInt<1>
+    reset_ic_ff <= UInt<1>("h00")
+    node _T_288 = eq(scnd_miss_req_q, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 352:36]
+    node _T_289 = and(miss_pending, _T_288) @[el2_ifu_mem_ctl.scala 352:34]
+    node _T_290 = or(reset_all_tags, reset_ic_ff) @[el2_ifu_mem_ctl.scala 352:72]
+    node reset_ic_in = and(_T_289, _T_290) @[el2_ifu_mem_ctl.scala 352:53]
+    reg _T_291 : UInt, clock @[el2_ifu_mem_ctl.scala 353:25]
+    _T_291 <= reset_ic_in @[el2_ifu_mem_ctl.scala 353:25]
+    reset_ic_ff <= _T_291 @[el2_ifu_mem_ctl.scala 353:15]
+    reg fetch_uncacheable_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 354:37]
+    fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 354:37]
+    reg _T_292 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 355:34]
+    _T_292 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 355:34]
+    ifu_fetch_addr_int_f <= _T_292 @[el2_ifu_mem_ctl.scala 355:24]
+    reg _T_293 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 357:33]
+    _T_293 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 357:33]
+    uncacheable_miss_ff <= _T_293 @[el2_ifu_mem_ctl.scala 357:23]
+    reg _T_294 : UInt, clock @[el2_ifu_mem_ctl.scala 358:20]
+    _T_294 <= imb_in @[el2_ifu_mem_ctl.scala 358:20]
+    imb_ff <= _T_294 @[el2_ifu_mem_ctl.scala 358:10]
+    wire miss_addr : UInt<26>
+    miss_addr <= UInt<1>("h00")
+    node _T_295 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 360:26]
+    node _T_296 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 360:47]
+    node _T_297 = bits(scnd_miss_req_q, 0, 0) @[el2_ifu_mem_ctl.scala 361:25]
+    node _T_298 = bits(imb_scnd_ff, 30, 5) @[el2_ifu_mem_ctl.scala 361:44]
+    node _T_299 = mux(_T_297, _T_298, miss_addr) @[el2_ifu_mem_ctl.scala 361:8]
+    node miss_addr_in = mux(_T_295, _T_296, _T_299) @[el2_ifu_mem_ctl.scala 360:25]
+    reg _T_300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 362:23]
+    _T_300 <= miss_addr_in @[el2_ifu_mem_ctl.scala 362:23]
+    miss_addr <= _T_300 @[el2_ifu_mem_ctl.scala 362:13]
+    reg _T_301 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 363:30]
+    _T_301 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 363:30]
+    way_status_mb_ff <= _T_301 @[el2_ifu_mem_ctl.scala 363:20]
+    reg _T_302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 364:24]
+    _T_302 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 364:24]
+    tagv_mb_ff <= _T_302 @[el2_ifu_mem_ctl.scala 364:14]
+    wire stream_miss_f : UInt<1>
+    stream_miss_f <= UInt<1>("h00")
+    node _T_303 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 366:68]
+    node _T_304 = and(_T_303, flush_final_f) @[el2_ifu_mem_ctl.scala 366:87]
+    node _T_305 = eq(_T_304, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 366:55]
+    node _T_306 = and(io.ifc_fetch_req_bf, _T_305) @[el2_ifu_mem_ctl.scala 366:53]
+    node _T_307 = eq(stream_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 366:106]
+    node ifc_fetch_req_qual_bf = and(_T_306, _T_307) @[el2_ifu_mem_ctl.scala 366:104]
+    reg ifc_fetch_req_f_raw : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 367:36]
+    ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[el2_ifu_mem_ctl.scala 367:36]
+    node _T_308 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 368:44]
+    node _T_309 = and(ifc_fetch_req_f_raw, _T_308) @[el2_ifu_mem_ctl.scala 368:42]
+    ifc_fetch_req_f <= _T_309 @[el2_ifu_mem_ctl.scala 368:19]
+    reg _T_310 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 369:31]
+    _T_310 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 369:31]
+    ifc_iccm_access_f <= _T_310 @[el2_ifu_mem_ctl.scala 369:21]
+    wire ifc_region_acc_fault_final_bf : UInt<1>
+    ifc_region_acc_fault_final_bf <= UInt<1>("h00")
+    reg _T_311 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 371:42]
+    _T_311 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 371:42]
+    ifc_region_acc_fault_final_f <= _T_311 @[el2_ifu_mem_ctl.scala 371:32]
+    reg ifc_region_acc_fault_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 372:39]
+    ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 372:39]
+    node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58]
+    node _T_312 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 374:38]
+    node _T_313 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 374:68]
+    node _T_314 = or(_T_312, _T_313) @[el2_ifu_mem_ctl.scala 374:55]
+    node _T_315 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 374:103]
+    node _T_316 = eq(_T_315, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 374:84]
+    node _T_317 = and(_T_314, _T_316) @[el2_ifu_mem_ctl.scala 374:82]
+    node _T_318 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 374:119]
+    node ifu_ic_mb_empty = or(_T_317, _T_318) @[el2_ifu_mem_ctl.scala 374:117]
+    node ifu_miss_state_idle = eq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 375:40]
+    wire write_ic_16_bytes : UInt<1>
+    write_ic_16_bytes <= UInt<1>("h00")
+    wire reset_tag_valid_for_miss : UInt<1>
+    reset_tag_valid_for_miss <= UInt<1>("h00")
+    node _T_319 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 378:35]
+    node _T_320 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 378:57]
+    node _T_321 = and(_T_319, _T_320) @[el2_ifu_mem_ctl.scala 378:55]
+    node sel_mb_addr = or(_T_321, reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 378:79]
+    node _T_322 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 379:50]
+    node _T_323 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 379:68]
+    node _T_324 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 379:124]
+    node _T_325 = cat(_T_323, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
+    node _T_326 = cat(_T_325, _T_324) @[Cat.scala 29:58]
+    node _T_327 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 380:50]
+    node _T_328 = eq(_T_327, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 380:37]
+    node _T_329 = mux(_T_322, _T_326, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_330 = mux(_T_328, ifu_fetch_addr_int_f, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_331 = or(_T_329, _T_330) @[Mux.scala 27:72]
+    wire ic_rw_addr : UInt<31> @[Mux.scala 27:72]
+    ic_rw_addr <= _T_331 @[Mux.scala 27:72]
+    reg _T_332 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 382:51]
+    _T_332 <= sel_mb_addr @[el2_ifu_mem_ctl.scala 382:51]
+    sel_mb_addr_ff <= _T_332 @[el2_ifu_mem_ctl.scala 382:18]
+    wire ifu_bus_rdata_ff : UInt<64>
+    ifu_bus_rdata_ff <= UInt<1>("h00")
+    wire ic_miss_buff_half : UInt<64>
+    ic_miss_buff_half <= UInt<1>("h00")
+    wire _T_333 : UInt<1>[35] @[el2_lib.scala 322:18]
+    wire _T_334 : UInt<1>[35] @[el2_lib.scala 323:18]
+    wire _T_335 : UInt<1>[35] @[el2_lib.scala 324:18]
+    wire _T_336 : UInt<1>[31] @[el2_lib.scala 325:18]
+    wire _T_337 : UInt<1>[31] @[el2_lib.scala 326:18]
+    wire _T_338 : UInt<1>[31] @[el2_lib.scala 327:18]
+    wire _T_339 : UInt<1>[7] @[el2_lib.scala 328:18]
+    node _T_340 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 335:36]
+    _T_333[0] <= _T_340 @[el2_lib.scala 335:30]
+    node _T_341 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 336:36]
+    _T_334[0] <= _T_341 @[el2_lib.scala 336:30]
+    node _T_342 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 335:36]
+    _T_333[1] <= _T_342 @[el2_lib.scala 335:30]
+    node _T_343 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 337:36]
+    _T_335[0] <= _T_343 @[el2_lib.scala 337:30]
+    node _T_344 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 336:36]
+    _T_334[1] <= _T_344 @[el2_lib.scala 336:30]
+    node _T_345 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 337:36]
+    _T_335[1] <= _T_345 @[el2_lib.scala 337:30]
+    node _T_346 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 335:36]
+    _T_333[2] <= _T_346 @[el2_lib.scala 335:30]
+    node _T_347 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 336:36]
+    _T_334[2] <= _T_347 @[el2_lib.scala 336:30]
+    node _T_348 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 337:36]
+    _T_335[2] <= _T_348 @[el2_lib.scala 337:30]
+    node _T_349 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 335:36]
+    _T_333[3] <= _T_349 @[el2_lib.scala 335:30]
+    node _T_350 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 338:36]
+    _T_336[0] <= _T_350 @[el2_lib.scala 338:30]
+    node _T_351 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 336:36]
+    _T_334[3] <= _T_351 @[el2_lib.scala 336:30]
+    node _T_352 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 338:36]
+    _T_336[1] <= _T_352 @[el2_lib.scala 338:30]
+    node _T_353 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 335:36]
+    _T_333[4] <= _T_353 @[el2_lib.scala 335:30]
+    node _T_354 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 336:36]
+    _T_334[4] <= _T_354 @[el2_lib.scala 336:30]
+    node _T_355 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 338:36]
+    _T_336[2] <= _T_355 @[el2_lib.scala 338:30]
+    node _T_356 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 337:36]
+    _T_335[3] <= _T_356 @[el2_lib.scala 337:30]
+    node _T_357 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 338:36]
+    _T_336[3] <= _T_357 @[el2_lib.scala 338:30]
+    node _T_358 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 335:36]
+    _T_333[5] <= _T_358 @[el2_lib.scala 335:30]
+    node _T_359 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 337:36]
+    _T_335[4] <= _T_359 @[el2_lib.scala 337:30]
+    node _T_360 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 338:36]
+    _T_336[4] <= _T_360 @[el2_lib.scala 338:30]
+    node _T_361 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 336:36]
+    _T_334[5] <= _T_361 @[el2_lib.scala 336:30]
+    node _T_362 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 337:36]
+    _T_335[5] <= _T_362 @[el2_lib.scala 337:30]
+    node _T_363 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 338:36]
+    _T_336[5] <= _T_363 @[el2_lib.scala 338:30]
+    node _T_364 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 335:36]
+    _T_333[6] <= _T_364 @[el2_lib.scala 335:30]
+    node _T_365 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 336:36]
+    _T_334[6] <= _T_365 @[el2_lib.scala 336:30]
+    node _T_366 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 337:36]
+    _T_335[6] <= _T_366 @[el2_lib.scala 337:30]
+    node _T_367 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 338:36]
+    _T_336[6] <= _T_367 @[el2_lib.scala 338:30]
+    node _T_368 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 335:36]
+    _T_333[7] <= _T_368 @[el2_lib.scala 335:30]
+    node _T_369 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 339:36]
+    _T_337[0] <= _T_369 @[el2_lib.scala 339:30]
+    node _T_370 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 336:36]
+    _T_334[7] <= _T_370 @[el2_lib.scala 336:30]
+    node _T_371 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 339:36]
+    _T_337[1] <= _T_371 @[el2_lib.scala 339:30]
+    node _T_372 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 335:36]
+    _T_333[8] <= _T_372 @[el2_lib.scala 335:30]
+    node _T_373 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 336:36]
+    _T_334[8] <= _T_373 @[el2_lib.scala 336:30]
+    node _T_374 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 339:36]
+    _T_337[2] <= _T_374 @[el2_lib.scala 339:30]
+    node _T_375 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 337:36]
+    _T_335[7] <= _T_375 @[el2_lib.scala 337:30]
+    node _T_376 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 339:36]
+    _T_337[3] <= _T_376 @[el2_lib.scala 339:30]
+    node _T_377 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 335:36]
+    _T_333[9] <= _T_377 @[el2_lib.scala 335:30]
+    node _T_378 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 337:36]
+    _T_335[8] <= _T_378 @[el2_lib.scala 337:30]
+    node _T_379 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 339:36]
+    _T_337[4] <= _T_379 @[el2_lib.scala 339:30]
+    node _T_380 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 336:36]
+    _T_334[9] <= _T_380 @[el2_lib.scala 336:30]
+    node _T_381 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 337:36]
+    _T_335[9] <= _T_381 @[el2_lib.scala 337:30]
+    node _T_382 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 339:36]
+    _T_337[5] <= _T_382 @[el2_lib.scala 339:30]
+    node _T_383 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 335:36]
+    _T_333[10] <= _T_383 @[el2_lib.scala 335:30]
+    node _T_384 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 336:36]
+    _T_334[10] <= _T_384 @[el2_lib.scala 336:30]
+    node _T_385 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 337:36]
+    _T_335[10] <= _T_385 @[el2_lib.scala 337:30]
+    node _T_386 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 339:36]
+    _T_337[6] <= _T_386 @[el2_lib.scala 339:30]
+    node _T_387 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 338:36]
+    _T_336[7] <= _T_387 @[el2_lib.scala 338:30]
+    node _T_388 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 339:36]
+    _T_337[7] <= _T_388 @[el2_lib.scala 339:30]
+    node _T_389 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 335:36]
+    _T_333[11] <= _T_389 @[el2_lib.scala 335:30]
+    node _T_390 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 338:36]
+    _T_336[8] <= _T_390 @[el2_lib.scala 338:30]
+    node _T_391 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 339:36]
+    _T_337[8] <= _T_391 @[el2_lib.scala 339:30]
+    node _T_392 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 336:36]
+    _T_334[11] <= _T_392 @[el2_lib.scala 336:30]
+    node _T_393 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 338:36]
+    _T_336[9] <= _T_393 @[el2_lib.scala 338:30]
+    node _T_394 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 339:36]
+    _T_337[9] <= _T_394 @[el2_lib.scala 339:30]
+    node _T_395 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 335:36]
+    _T_333[12] <= _T_395 @[el2_lib.scala 335:30]
+    node _T_396 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 336:36]
+    _T_334[12] <= _T_396 @[el2_lib.scala 336:30]
+    node _T_397 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 338:36]
+    _T_336[10] <= _T_397 @[el2_lib.scala 338:30]
+    node _T_398 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 339:36]
+    _T_337[10] <= _T_398 @[el2_lib.scala 339:30]
+    node _T_399 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 337:36]
+    _T_335[11] <= _T_399 @[el2_lib.scala 337:30]
+    node _T_400 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 338:36]
+    _T_336[11] <= _T_400 @[el2_lib.scala 338:30]
+    node _T_401 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 339:36]
+    _T_337[11] <= _T_401 @[el2_lib.scala 339:30]
+    node _T_402 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 335:36]
+    _T_333[13] <= _T_402 @[el2_lib.scala 335:30]
+    node _T_403 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 337:36]
+    _T_335[12] <= _T_403 @[el2_lib.scala 337:30]
+    node _T_404 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 338:36]
+    _T_336[12] <= _T_404 @[el2_lib.scala 338:30]
+    node _T_405 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 339:36]
+    _T_337[12] <= _T_405 @[el2_lib.scala 339:30]
+    node _T_406 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 336:36]
+    _T_334[13] <= _T_406 @[el2_lib.scala 336:30]
+    node _T_407 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 337:36]
+    _T_335[13] <= _T_407 @[el2_lib.scala 337:30]
+    node _T_408 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 338:36]
+    _T_336[13] <= _T_408 @[el2_lib.scala 338:30]
+    node _T_409 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 339:36]
+    _T_337[13] <= _T_409 @[el2_lib.scala 339:30]
+    node _T_410 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 335:36]
+    _T_333[14] <= _T_410 @[el2_lib.scala 335:30]
+    node _T_411 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 336:36]
+    _T_334[14] <= _T_411 @[el2_lib.scala 336:30]
+    node _T_412 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 337:36]
+    _T_335[14] <= _T_412 @[el2_lib.scala 337:30]
+    node _T_413 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 338:36]
+    _T_336[14] <= _T_413 @[el2_lib.scala 338:30]
+    node _T_414 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 339:36]
+    _T_337[14] <= _T_414 @[el2_lib.scala 339:30]
+    node _T_415 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 335:36]
+    _T_333[15] <= _T_415 @[el2_lib.scala 335:30]
+    node _T_416 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 340:36]
+    _T_338[0] <= _T_416 @[el2_lib.scala 340:30]
+    node _T_417 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 336:36]
+    _T_334[15] <= _T_417 @[el2_lib.scala 336:30]
+    node _T_418 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 340:36]
+    _T_338[1] <= _T_418 @[el2_lib.scala 340:30]
+    node _T_419 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 335:36]
+    _T_333[16] <= _T_419 @[el2_lib.scala 335:30]
+    node _T_420 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 336:36]
+    _T_334[16] <= _T_420 @[el2_lib.scala 336:30]
+    node _T_421 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 340:36]
+    _T_338[2] <= _T_421 @[el2_lib.scala 340:30]
+    node _T_422 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 337:36]
+    _T_335[15] <= _T_422 @[el2_lib.scala 337:30]
+    node _T_423 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 340:36]
+    _T_338[3] <= _T_423 @[el2_lib.scala 340:30]
+    node _T_424 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 335:36]
+    _T_333[17] <= _T_424 @[el2_lib.scala 335:30]
+    node _T_425 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 337:36]
+    _T_335[16] <= _T_425 @[el2_lib.scala 337:30]
+    node _T_426 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 340:36]
+    _T_338[4] <= _T_426 @[el2_lib.scala 340:30]
+    node _T_427 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 336:36]
+    _T_334[17] <= _T_427 @[el2_lib.scala 336:30]
+    node _T_428 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 337:36]
+    _T_335[17] <= _T_428 @[el2_lib.scala 337:30]
+    node _T_429 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 340:36]
+    _T_338[5] <= _T_429 @[el2_lib.scala 340:30]
+    node _T_430 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 335:36]
+    _T_333[18] <= _T_430 @[el2_lib.scala 335:30]
+    node _T_431 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 336:36]
+    _T_334[18] <= _T_431 @[el2_lib.scala 336:30]
+    node _T_432 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 337:36]
+    _T_335[18] <= _T_432 @[el2_lib.scala 337:30]
+    node _T_433 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 340:36]
+    _T_338[6] <= _T_433 @[el2_lib.scala 340:30]
+    node _T_434 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 338:36]
+    _T_336[15] <= _T_434 @[el2_lib.scala 338:30]
+    node _T_435 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 340:36]
+    _T_338[7] <= _T_435 @[el2_lib.scala 340:30]
+    node _T_436 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 335:36]
+    _T_333[19] <= _T_436 @[el2_lib.scala 335:30]
+    node _T_437 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 338:36]
+    _T_336[16] <= _T_437 @[el2_lib.scala 338:30]
+    node _T_438 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 340:36]
+    _T_338[8] <= _T_438 @[el2_lib.scala 340:30]
+    node _T_439 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 336:36]
+    _T_334[19] <= _T_439 @[el2_lib.scala 336:30]
+    node _T_440 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 338:36]
+    _T_336[17] <= _T_440 @[el2_lib.scala 338:30]
+    node _T_441 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 340:36]
+    _T_338[9] <= _T_441 @[el2_lib.scala 340:30]
+    node _T_442 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 335:36]
+    _T_333[20] <= _T_442 @[el2_lib.scala 335:30]
+    node _T_443 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 336:36]
+    _T_334[20] <= _T_443 @[el2_lib.scala 336:30]
+    node _T_444 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 338:36]
+    _T_336[18] <= _T_444 @[el2_lib.scala 338:30]
+    node _T_445 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 340:36]
+    _T_338[10] <= _T_445 @[el2_lib.scala 340:30]
+    node _T_446 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 337:36]
+    _T_335[19] <= _T_446 @[el2_lib.scala 337:30]
+    node _T_447 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 338:36]
+    _T_336[19] <= _T_447 @[el2_lib.scala 338:30]
+    node _T_448 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 340:36]
+    _T_338[11] <= _T_448 @[el2_lib.scala 340:30]
+    node _T_449 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 335:36]
+    _T_333[21] <= _T_449 @[el2_lib.scala 335:30]
+    node _T_450 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 337:36]
+    _T_335[20] <= _T_450 @[el2_lib.scala 337:30]
+    node _T_451 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 338:36]
+    _T_336[20] <= _T_451 @[el2_lib.scala 338:30]
+    node _T_452 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 340:36]
+    _T_338[12] <= _T_452 @[el2_lib.scala 340:30]
+    node _T_453 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 336:36]
+    _T_334[21] <= _T_453 @[el2_lib.scala 336:30]
+    node _T_454 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 337:36]
+    _T_335[21] <= _T_454 @[el2_lib.scala 337:30]
+    node _T_455 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 338:36]
+    _T_336[21] <= _T_455 @[el2_lib.scala 338:30]
+    node _T_456 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 340:36]
+    _T_338[13] <= _T_456 @[el2_lib.scala 340:30]
+    node _T_457 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 335:36]
+    _T_333[22] <= _T_457 @[el2_lib.scala 335:30]
+    node _T_458 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 336:36]
+    _T_334[22] <= _T_458 @[el2_lib.scala 336:30]
+    node _T_459 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 337:36]
+    _T_335[22] <= _T_459 @[el2_lib.scala 337:30]
+    node _T_460 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 338:36]
+    _T_336[22] <= _T_460 @[el2_lib.scala 338:30]
+    node _T_461 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 340:36]
+    _T_338[14] <= _T_461 @[el2_lib.scala 340:30]
+    node _T_462 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 339:36]
+    _T_337[15] <= _T_462 @[el2_lib.scala 339:30]
+    node _T_463 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 340:36]
+    _T_338[15] <= _T_463 @[el2_lib.scala 340:30]
+    node _T_464 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 335:36]
+    _T_333[23] <= _T_464 @[el2_lib.scala 335:30]
+    node _T_465 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 339:36]
+    _T_337[16] <= _T_465 @[el2_lib.scala 339:30]
+    node _T_466 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 340:36]
+    _T_338[16] <= _T_466 @[el2_lib.scala 340:30]
+    node _T_467 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 336:36]
+    _T_334[23] <= _T_467 @[el2_lib.scala 336:30]
+    node _T_468 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 339:36]
+    _T_337[17] <= _T_468 @[el2_lib.scala 339:30]
+    node _T_469 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 340:36]
+    _T_338[17] <= _T_469 @[el2_lib.scala 340:30]
+    node _T_470 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 335:36]
+    _T_333[24] <= _T_470 @[el2_lib.scala 335:30]
+    node _T_471 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 336:36]
+    _T_334[24] <= _T_471 @[el2_lib.scala 336:30]
+    node _T_472 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 339:36]
+    _T_337[18] <= _T_472 @[el2_lib.scala 339:30]
+    node _T_473 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 340:36]
+    _T_338[18] <= _T_473 @[el2_lib.scala 340:30]
+    node _T_474 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 337:36]
+    _T_335[23] <= _T_474 @[el2_lib.scala 337:30]
+    node _T_475 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 339:36]
+    _T_337[19] <= _T_475 @[el2_lib.scala 339:30]
+    node _T_476 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 340:36]
+    _T_338[19] <= _T_476 @[el2_lib.scala 340:30]
+    node _T_477 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 335:36]
+    _T_333[25] <= _T_477 @[el2_lib.scala 335:30]
+    node _T_478 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 337:36]
+    _T_335[24] <= _T_478 @[el2_lib.scala 337:30]
+    node _T_479 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 339:36]
+    _T_337[20] <= _T_479 @[el2_lib.scala 339:30]
+    node _T_480 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 340:36]
+    _T_338[20] <= _T_480 @[el2_lib.scala 340:30]
+    node _T_481 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 336:36]
+    _T_334[25] <= _T_481 @[el2_lib.scala 336:30]
+    node _T_482 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 337:36]
+    _T_335[25] <= _T_482 @[el2_lib.scala 337:30]
+    node _T_483 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 339:36]
+    _T_337[21] <= _T_483 @[el2_lib.scala 339:30]
+    node _T_484 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 340:36]
+    _T_338[21] <= _T_484 @[el2_lib.scala 340:30]
+    node _T_485 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 335:36]
+    _T_333[26] <= _T_485 @[el2_lib.scala 335:30]
+    node _T_486 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 336:36]
+    _T_334[26] <= _T_486 @[el2_lib.scala 336:30]
+    node _T_487 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 337:36]
+    _T_335[26] <= _T_487 @[el2_lib.scala 337:30]
+    node _T_488 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 339:36]
+    _T_337[22] <= _T_488 @[el2_lib.scala 339:30]
+    node _T_489 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 340:36]
+    _T_338[22] <= _T_489 @[el2_lib.scala 340:30]
+    node _T_490 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 338:36]
+    _T_336[23] <= _T_490 @[el2_lib.scala 338:30]
+    node _T_491 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 339:36]
+    _T_337[23] <= _T_491 @[el2_lib.scala 339:30]
+    node _T_492 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 340:36]
+    _T_338[23] <= _T_492 @[el2_lib.scala 340:30]
+    node _T_493 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 335:36]
+    _T_333[27] <= _T_493 @[el2_lib.scala 335:30]
+    node _T_494 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 338:36]
+    _T_336[24] <= _T_494 @[el2_lib.scala 338:30]
+    node _T_495 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 339:36]
+    _T_337[24] <= _T_495 @[el2_lib.scala 339:30]
+    node _T_496 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 340:36]
+    _T_338[24] <= _T_496 @[el2_lib.scala 340:30]
+    node _T_497 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 336:36]
+    _T_334[27] <= _T_497 @[el2_lib.scala 336:30]
+    node _T_498 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 338:36]
+    _T_336[25] <= _T_498 @[el2_lib.scala 338:30]
+    node _T_499 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 339:36]
+    _T_337[25] <= _T_499 @[el2_lib.scala 339:30]
+    node _T_500 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 340:36]
+    _T_338[25] <= _T_500 @[el2_lib.scala 340:30]
+    node _T_501 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 335:36]
+    _T_333[28] <= _T_501 @[el2_lib.scala 335:30]
+    node _T_502 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 336:36]
+    _T_334[28] <= _T_502 @[el2_lib.scala 336:30]
+    node _T_503 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 338:36]
+    _T_336[26] <= _T_503 @[el2_lib.scala 338:30]
+    node _T_504 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 339:36]
+    _T_337[26] <= _T_504 @[el2_lib.scala 339:30]
+    node _T_505 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 340:36]
+    _T_338[26] <= _T_505 @[el2_lib.scala 340:30]
+    node _T_506 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 337:36]
+    _T_335[27] <= _T_506 @[el2_lib.scala 337:30]
+    node _T_507 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 338:36]
+    _T_336[27] <= _T_507 @[el2_lib.scala 338:30]
+    node _T_508 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 339:36]
+    _T_337[27] <= _T_508 @[el2_lib.scala 339:30]
+    node _T_509 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 340:36]
+    _T_338[27] <= _T_509 @[el2_lib.scala 340:30]
+    node _T_510 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 335:36]
+    _T_333[29] <= _T_510 @[el2_lib.scala 335:30]
+    node _T_511 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 337:36]
+    _T_335[28] <= _T_511 @[el2_lib.scala 337:30]
+    node _T_512 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 338:36]
+    _T_336[28] <= _T_512 @[el2_lib.scala 338:30]
+    node _T_513 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 339:36]
+    _T_337[28] <= _T_513 @[el2_lib.scala 339:30]
+    node _T_514 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 340:36]
+    _T_338[28] <= _T_514 @[el2_lib.scala 340:30]
+    node _T_515 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 336:36]
+    _T_334[29] <= _T_515 @[el2_lib.scala 336:30]
+    node _T_516 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 337:36]
+    _T_335[29] <= _T_516 @[el2_lib.scala 337:30]
+    node _T_517 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 338:36]
+    _T_336[29] <= _T_517 @[el2_lib.scala 338:30]
+    node _T_518 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 339:36]
+    _T_337[29] <= _T_518 @[el2_lib.scala 339:30]
+    node _T_519 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 340:36]
+    _T_338[29] <= _T_519 @[el2_lib.scala 340:30]
+    node _T_520 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 335:36]
+    _T_333[30] <= _T_520 @[el2_lib.scala 335:30]
+    node _T_521 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 336:36]
+    _T_334[30] <= _T_521 @[el2_lib.scala 336:30]
+    node _T_522 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 337:36]
+    _T_335[30] <= _T_522 @[el2_lib.scala 337:30]
+    node _T_523 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 338:36]
+    _T_336[30] <= _T_523 @[el2_lib.scala 338:30]
+    node _T_524 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 339:36]
+    _T_337[30] <= _T_524 @[el2_lib.scala 339:30]
+    node _T_525 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 340:36]
+    _T_338[30] <= _T_525 @[el2_lib.scala 340:30]
+    node _T_526 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 335:36]
+    _T_333[31] <= _T_526 @[el2_lib.scala 335:30]
+    node _T_527 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 341:36]
+    _T_339[0] <= _T_527 @[el2_lib.scala 341:30]
+    node _T_528 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 336:36]
+    _T_334[31] <= _T_528 @[el2_lib.scala 336:30]
+    node _T_529 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 341:36]
+    _T_339[1] <= _T_529 @[el2_lib.scala 341:30]
+    node _T_530 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 335:36]
+    _T_333[32] <= _T_530 @[el2_lib.scala 335:30]
+    node _T_531 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 336:36]
+    _T_334[32] <= _T_531 @[el2_lib.scala 336:30]
+    node _T_532 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 341:36]
+    _T_339[2] <= _T_532 @[el2_lib.scala 341:30]
+    node _T_533 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 337:36]
+    _T_335[31] <= _T_533 @[el2_lib.scala 337:30]
+    node _T_534 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 341:36]
+    _T_339[3] <= _T_534 @[el2_lib.scala 341:30]
+    node _T_535 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 335:36]
+    _T_333[33] <= _T_535 @[el2_lib.scala 335:30]
+    node _T_536 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 337:36]
+    _T_335[32] <= _T_536 @[el2_lib.scala 337:30]
+    node _T_537 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 341:36]
+    _T_339[4] <= _T_537 @[el2_lib.scala 341:30]
+    node _T_538 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 336:36]
+    _T_334[33] <= _T_538 @[el2_lib.scala 336:30]
+    node _T_539 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 337:36]
+    _T_335[33] <= _T_539 @[el2_lib.scala 337:30]
+    node _T_540 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 341:36]
+    _T_339[5] <= _T_540 @[el2_lib.scala 341:30]
+    node _T_541 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 335:36]
+    _T_333[34] <= _T_541 @[el2_lib.scala 335:30]
+    node _T_542 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 336:36]
+    _T_334[34] <= _T_542 @[el2_lib.scala 336:30]
+    node _T_543 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 337:36]
+    _T_335[34] <= _T_543 @[el2_lib.scala 337:30]
+    node _T_544 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 341:36]
+    _T_339[6] <= _T_544 @[el2_lib.scala 341:30]
+    node _T_545 = cat(_T_333[1], _T_333[0]) @[el2_lib.scala 343:27]
+    node _T_546 = cat(_T_333[3], _T_333[2]) @[el2_lib.scala 343:27]
+    node _T_547 = cat(_T_546, _T_545) @[el2_lib.scala 343:27]
+    node _T_548 = cat(_T_333[5], _T_333[4]) @[el2_lib.scala 343:27]
+    node _T_549 = cat(_T_333[7], _T_333[6]) @[el2_lib.scala 343:27]
+    node _T_550 = cat(_T_549, _T_548) @[el2_lib.scala 343:27]
+    node _T_551 = cat(_T_550, _T_547) @[el2_lib.scala 343:27]
+    node _T_552 = cat(_T_333[9], _T_333[8]) @[el2_lib.scala 343:27]
+    node _T_553 = cat(_T_333[11], _T_333[10]) @[el2_lib.scala 343:27]
+    node _T_554 = cat(_T_553, _T_552) @[el2_lib.scala 343:27]
+    node _T_555 = cat(_T_333[13], _T_333[12]) @[el2_lib.scala 343:27]
+    node _T_556 = cat(_T_333[16], _T_333[15]) @[el2_lib.scala 343:27]
+    node _T_557 = cat(_T_556, _T_333[14]) @[el2_lib.scala 343:27]
+    node _T_558 = cat(_T_557, _T_555) @[el2_lib.scala 343:27]
+    node _T_559 = cat(_T_558, _T_554) @[el2_lib.scala 343:27]
+    node _T_560 = cat(_T_559, _T_551) @[el2_lib.scala 343:27]
+    node _T_561 = cat(_T_333[18], _T_333[17]) @[el2_lib.scala 343:27]
+    node _T_562 = cat(_T_333[20], _T_333[19]) @[el2_lib.scala 343:27]
+    node _T_563 = cat(_T_562, _T_561) @[el2_lib.scala 343:27]
+    node _T_564 = cat(_T_333[22], _T_333[21]) @[el2_lib.scala 343:27]
+    node _T_565 = cat(_T_333[25], _T_333[24]) @[el2_lib.scala 343:27]
+    node _T_566 = cat(_T_565, _T_333[23]) @[el2_lib.scala 343:27]
+    node _T_567 = cat(_T_566, _T_564) @[el2_lib.scala 343:27]
+    node _T_568 = cat(_T_567, _T_563) @[el2_lib.scala 343:27]
+    node _T_569 = cat(_T_333[27], _T_333[26]) @[el2_lib.scala 343:27]
+    node _T_570 = cat(_T_333[29], _T_333[28]) @[el2_lib.scala 343:27]
+    node _T_571 = cat(_T_570, _T_569) @[el2_lib.scala 343:27]
+    node _T_572 = cat(_T_333[31], _T_333[30]) @[el2_lib.scala 343:27]
+    node _T_573 = cat(_T_333[34], _T_333[33]) @[el2_lib.scala 343:27]
+    node _T_574 = cat(_T_573, _T_333[32]) @[el2_lib.scala 343:27]
+    node _T_575 = cat(_T_574, _T_572) @[el2_lib.scala 343:27]
+    node _T_576 = cat(_T_575, _T_571) @[el2_lib.scala 343:27]
+    node _T_577 = cat(_T_576, _T_568) @[el2_lib.scala 343:27]
+    node _T_578 = cat(_T_577, _T_560) @[el2_lib.scala 343:27]
+    node _T_579 = xorr(_T_578) @[el2_lib.scala 343:34]
+    node _T_580 = cat(_T_334[1], _T_334[0]) @[el2_lib.scala 343:44]
+    node _T_581 = cat(_T_334[3], _T_334[2]) @[el2_lib.scala 343:44]
+    node _T_582 = cat(_T_581, _T_580) @[el2_lib.scala 343:44]
+    node _T_583 = cat(_T_334[5], _T_334[4]) @[el2_lib.scala 343:44]
+    node _T_584 = cat(_T_334[7], _T_334[6]) @[el2_lib.scala 343:44]
+    node _T_585 = cat(_T_584, _T_583) @[el2_lib.scala 343:44]
+    node _T_586 = cat(_T_585, _T_582) @[el2_lib.scala 343:44]
+    node _T_587 = cat(_T_334[9], _T_334[8]) @[el2_lib.scala 343:44]
+    node _T_588 = cat(_T_334[11], _T_334[10]) @[el2_lib.scala 343:44]
+    node _T_589 = cat(_T_588, _T_587) @[el2_lib.scala 343:44]
+    node _T_590 = cat(_T_334[13], _T_334[12]) @[el2_lib.scala 343:44]
+    node _T_591 = cat(_T_334[16], _T_334[15]) @[el2_lib.scala 343:44]
+    node _T_592 = cat(_T_591, _T_334[14]) @[el2_lib.scala 343:44]
+    node _T_593 = cat(_T_592, _T_590) @[el2_lib.scala 343:44]
+    node _T_594 = cat(_T_593, _T_589) @[el2_lib.scala 343:44]
+    node _T_595 = cat(_T_594, _T_586) @[el2_lib.scala 343:44]
+    node _T_596 = cat(_T_334[18], _T_334[17]) @[el2_lib.scala 343:44]
+    node _T_597 = cat(_T_334[20], _T_334[19]) @[el2_lib.scala 343:44]
+    node _T_598 = cat(_T_597, _T_596) @[el2_lib.scala 343:44]
+    node _T_599 = cat(_T_334[22], _T_334[21]) @[el2_lib.scala 343:44]
+    node _T_600 = cat(_T_334[25], _T_334[24]) @[el2_lib.scala 343:44]
+    node _T_601 = cat(_T_600, _T_334[23]) @[el2_lib.scala 343:44]
+    node _T_602 = cat(_T_601, _T_599) @[el2_lib.scala 343:44]
+    node _T_603 = cat(_T_602, _T_598) @[el2_lib.scala 343:44]
+    node _T_604 = cat(_T_334[27], _T_334[26]) @[el2_lib.scala 343:44]
+    node _T_605 = cat(_T_334[29], _T_334[28]) @[el2_lib.scala 343:44]
+    node _T_606 = cat(_T_605, _T_604) @[el2_lib.scala 343:44]
+    node _T_607 = cat(_T_334[31], _T_334[30]) @[el2_lib.scala 343:44]
+    node _T_608 = cat(_T_334[34], _T_334[33]) @[el2_lib.scala 343:44]
+    node _T_609 = cat(_T_608, _T_334[32]) @[el2_lib.scala 343:44]
+    node _T_610 = cat(_T_609, _T_607) @[el2_lib.scala 343:44]
+    node _T_611 = cat(_T_610, _T_606) @[el2_lib.scala 343:44]
+    node _T_612 = cat(_T_611, _T_603) @[el2_lib.scala 343:44]
+    node _T_613 = cat(_T_612, _T_595) @[el2_lib.scala 343:44]
+    node _T_614 = xorr(_T_613) @[el2_lib.scala 343:51]
+    node _T_615 = cat(_T_335[1], _T_335[0]) @[el2_lib.scala 343:61]
+    node _T_616 = cat(_T_335[3], _T_335[2]) @[el2_lib.scala 343:61]
+    node _T_617 = cat(_T_616, _T_615) @[el2_lib.scala 343:61]
+    node _T_618 = cat(_T_335[5], _T_335[4]) @[el2_lib.scala 343:61]
+    node _T_619 = cat(_T_335[7], _T_335[6]) @[el2_lib.scala 343:61]
+    node _T_620 = cat(_T_619, _T_618) @[el2_lib.scala 343:61]
+    node _T_621 = cat(_T_620, _T_617) @[el2_lib.scala 343:61]
+    node _T_622 = cat(_T_335[9], _T_335[8]) @[el2_lib.scala 343:61]
+    node _T_623 = cat(_T_335[11], _T_335[10]) @[el2_lib.scala 343:61]
+    node _T_624 = cat(_T_623, _T_622) @[el2_lib.scala 343:61]
+    node _T_625 = cat(_T_335[13], _T_335[12]) @[el2_lib.scala 343:61]
+    node _T_626 = cat(_T_335[16], _T_335[15]) @[el2_lib.scala 343:61]
+    node _T_627 = cat(_T_626, _T_335[14]) @[el2_lib.scala 343:61]
+    node _T_628 = cat(_T_627, _T_625) @[el2_lib.scala 343:61]
+    node _T_629 = cat(_T_628, _T_624) @[el2_lib.scala 343:61]
+    node _T_630 = cat(_T_629, _T_621) @[el2_lib.scala 343:61]
+    node _T_631 = cat(_T_335[18], _T_335[17]) @[el2_lib.scala 343:61]
+    node _T_632 = cat(_T_335[20], _T_335[19]) @[el2_lib.scala 343:61]
+    node _T_633 = cat(_T_632, _T_631) @[el2_lib.scala 343:61]
+    node _T_634 = cat(_T_335[22], _T_335[21]) @[el2_lib.scala 343:61]
+    node _T_635 = cat(_T_335[25], _T_335[24]) @[el2_lib.scala 343:61]
+    node _T_636 = cat(_T_635, _T_335[23]) @[el2_lib.scala 343:61]
+    node _T_637 = cat(_T_636, _T_634) @[el2_lib.scala 343:61]
+    node _T_638 = cat(_T_637, _T_633) @[el2_lib.scala 343:61]
+    node _T_639 = cat(_T_335[27], _T_335[26]) @[el2_lib.scala 343:61]
+    node _T_640 = cat(_T_335[29], _T_335[28]) @[el2_lib.scala 343:61]
+    node _T_641 = cat(_T_640, _T_639) @[el2_lib.scala 343:61]
+    node _T_642 = cat(_T_335[31], _T_335[30]) @[el2_lib.scala 343:61]
+    node _T_643 = cat(_T_335[34], _T_335[33]) @[el2_lib.scala 343:61]
+    node _T_644 = cat(_T_643, _T_335[32]) @[el2_lib.scala 343:61]
+    node _T_645 = cat(_T_644, _T_642) @[el2_lib.scala 343:61]
+    node _T_646 = cat(_T_645, _T_641) @[el2_lib.scala 343:61]
+    node _T_647 = cat(_T_646, _T_638) @[el2_lib.scala 343:61]
+    node _T_648 = cat(_T_647, _T_630) @[el2_lib.scala 343:61]
+    node _T_649 = xorr(_T_648) @[el2_lib.scala 343:68]
+    node _T_650 = cat(_T_336[2], _T_336[1]) @[el2_lib.scala 343:78]
+    node _T_651 = cat(_T_650, _T_336[0]) @[el2_lib.scala 343:78]
+    node _T_652 = cat(_T_336[4], _T_336[3]) @[el2_lib.scala 343:78]
+    node _T_653 = cat(_T_336[6], _T_336[5]) @[el2_lib.scala 343:78]
+    node _T_654 = cat(_T_653, _T_652) @[el2_lib.scala 343:78]
+    node _T_655 = cat(_T_654, _T_651) @[el2_lib.scala 343:78]
+    node _T_656 = cat(_T_336[8], _T_336[7]) @[el2_lib.scala 343:78]
+    node _T_657 = cat(_T_336[10], _T_336[9]) @[el2_lib.scala 343:78]
+    node _T_658 = cat(_T_657, _T_656) @[el2_lib.scala 343:78]
+    node _T_659 = cat(_T_336[12], _T_336[11]) @[el2_lib.scala 343:78]
+    node _T_660 = cat(_T_336[14], _T_336[13]) @[el2_lib.scala 343:78]
+    node _T_661 = cat(_T_660, _T_659) @[el2_lib.scala 343:78]
+    node _T_662 = cat(_T_661, _T_658) @[el2_lib.scala 343:78]
+    node _T_663 = cat(_T_662, _T_655) @[el2_lib.scala 343:78]
+    node _T_664 = cat(_T_336[16], _T_336[15]) @[el2_lib.scala 343:78]
+    node _T_665 = cat(_T_336[18], _T_336[17]) @[el2_lib.scala 343:78]
+    node _T_666 = cat(_T_665, _T_664) @[el2_lib.scala 343:78]
+    node _T_667 = cat(_T_336[20], _T_336[19]) @[el2_lib.scala 343:78]
+    node _T_668 = cat(_T_336[22], _T_336[21]) @[el2_lib.scala 343:78]
+    node _T_669 = cat(_T_668, _T_667) @[el2_lib.scala 343:78]
+    node _T_670 = cat(_T_669, _T_666) @[el2_lib.scala 343:78]
+    node _T_671 = cat(_T_336[24], _T_336[23]) @[el2_lib.scala 343:78]
+    node _T_672 = cat(_T_336[26], _T_336[25]) @[el2_lib.scala 343:78]
+    node _T_673 = cat(_T_672, _T_671) @[el2_lib.scala 343:78]
+    node _T_674 = cat(_T_336[28], _T_336[27]) @[el2_lib.scala 343:78]
+    node _T_675 = cat(_T_336[30], _T_336[29]) @[el2_lib.scala 343:78]
+    node _T_676 = cat(_T_675, _T_674) @[el2_lib.scala 343:78]
+    node _T_677 = cat(_T_676, _T_673) @[el2_lib.scala 343:78]
+    node _T_678 = cat(_T_677, _T_670) @[el2_lib.scala 343:78]
+    node _T_679 = cat(_T_678, _T_663) @[el2_lib.scala 343:78]
+    node _T_680 = xorr(_T_679) @[el2_lib.scala 343:85]
+    node _T_681 = cat(_T_337[2], _T_337[1]) @[el2_lib.scala 343:95]
+    node _T_682 = cat(_T_681, _T_337[0]) @[el2_lib.scala 343:95]
+    node _T_683 = cat(_T_337[4], _T_337[3]) @[el2_lib.scala 343:95]
+    node _T_684 = cat(_T_337[6], _T_337[5]) @[el2_lib.scala 343:95]
+    node _T_685 = cat(_T_684, _T_683) @[el2_lib.scala 343:95]
+    node _T_686 = cat(_T_685, _T_682) @[el2_lib.scala 343:95]
+    node _T_687 = cat(_T_337[8], _T_337[7]) @[el2_lib.scala 343:95]
+    node _T_688 = cat(_T_337[10], _T_337[9]) @[el2_lib.scala 343:95]
+    node _T_689 = cat(_T_688, _T_687) @[el2_lib.scala 343:95]
+    node _T_690 = cat(_T_337[12], _T_337[11]) @[el2_lib.scala 343:95]
+    node _T_691 = cat(_T_337[14], _T_337[13]) @[el2_lib.scala 343:95]
+    node _T_692 = cat(_T_691, _T_690) @[el2_lib.scala 343:95]
+    node _T_693 = cat(_T_692, _T_689) @[el2_lib.scala 343:95]
+    node _T_694 = cat(_T_693, _T_686) @[el2_lib.scala 343:95]
+    node _T_695 = cat(_T_337[16], _T_337[15]) @[el2_lib.scala 343:95]
+    node _T_696 = cat(_T_337[18], _T_337[17]) @[el2_lib.scala 343:95]
+    node _T_697 = cat(_T_696, _T_695) @[el2_lib.scala 343:95]
+    node _T_698 = cat(_T_337[20], _T_337[19]) @[el2_lib.scala 343:95]
+    node _T_699 = cat(_T_337[22], _T_337[21]) @[el2_lib.scala 343:95]
+    node _T_700 = cat(_T_699, _T_698) @[el2_lib.scala 343:95]
+    node _T_701 = cat(_T_700, _T_697) @[el2_lib.scala 343:95]
+    node _T_702 = cat(_T_337[24], _T_337[23]) @[el2_lib.scala 343:95]
+    node _T_703 = cat(_T_337[26], _T_337[25]) @[el2_lib.scala 343:95]
+    node _T_704 = cat(_T_703, _T_702) @[el2_lib.scala 343:95]
+    node _T_705 = cat(_T_337[28], _T_337[27]) @[el2_lib.scala 343:95]
+    node _T_706 = cat(_T_337[30], _T_337[29]) @[el2_lib.scala 343:95]
+    node _T_707 = cat(_T_706, _T_705) @[el2_lib.scala 343:95]
+    node _T_708 = cat(_T_707, _T_704) @[el2_lib.scala 343:95]
+    node _T_709 = cat(_T_708, _T_701) @[el2_lib.scala 343:95]
+    node _T_710 = cat(_T_709, _T_694) @[el2_lib.scala 343:95]
+    node _T_711 = xorr(_T_710) @[el2_lib.scala 343:102]
+    node _T_712 = cat(_T_338[2], _T_338[1]) @[el2_lib.scala 343:112]
+    node _T_713 = cat(_T_712, _T_338[0]) @[el2_lib.scala 343:112]
+    node _T_714 = cat(_T_338[4], _T_338[3]) @[el2_lib.scala 343:112]
+    node _T_715 = cat(_T_338[6], _T_338[5]) @[el2_lib.scala 343:112]
+    node _T_716 = cat(_T_715, _T_714) @[el2_lib.scala 343:112]
+    node _T_717 = cat(_T_716, _T_713) @[el2_lib.scala 343:112]
+    node _T_718 = cat(_T_338[8], _T_338[7]) @[el2_lib.scala 343:112]
+    node _T_719 = cat(_T_338[10], _T_338[9]) @[el2_lib.scala 343:112]
+    node _T_720 = cat(_T_719, _T_718) @[el2_lib.scala 343:112]
+    node _T_721 = cat(_T_338[12], _T_338[11]) @[el2_lib.scala 343:112]
+    node _T_722 = cat(_T_338[14], _T_338[13]) @[el2_lib.scala 343:112]
+    node _T_723 = cat(_T_722, _T_721) @[el2_lib.scala 343:112]
+    node _T_724 = cat(_T_723, _T_720) @[el2_lib.scala 343:112]
+    node _T_725 = cat(_T_724, _T_717) @[el2_lib.scala 343:112]
+    node _T_726 = cat(_T_338[16], _T_338[15]) @[el2_lib.scala 343:112]
+    node _T_727 = cat(_T_338[18], _T_338[17]) @[el2_lib.scala 343:112]
+    node _T_728 = cat(_T_727, _T_726) @[el2_lib.scala 343:112]
+    node _T_729 = cat(_T_338[20], _T_338[19]) @[el2_lib.scala 343:112]
+    node _T_730 = cat(_T_338[22], _T_338[21]) @[el2_lib.scala 343:112]
+    node _T_731 = cat(_T_730, _T_729) @[el2_lib.scala 343:112]
+    node _T_732 = cat(_T_731, _T_728) @[el2_lib.scala 343:112]
+    node _T_733 = cat(_T_338[24], _T_338[23]) @[el2_lib.scala 343:112]
+    node _T_734 = cat(_T_338[26], _T_338[25]) @[el2_lib.scala 343:112]
+    node _T_735 = cat(_T_734, _T_733) @[el2_lib.scala 343:112]
+    node _T_736 = cat(_T_338[28], _T_338[27]) @[el2_lib.scala 343:112]
+    node _T_737 = cat(_T_338[30], _T_338[29]) @[el2_lib.scala 343:112]
+    node _T_738 = cat(_T_737, _T_736) @[el2_lib.scala 343:112]
+    node _T_739 = cat(_T_738, _T_735) @[el2_lib.scala 343:112]
+    node _T_740 = cat(_T_739, _T_732) @[el2_lib.scala 343:112]
+    node _T_741 = cat(_T_740, _T_725) @[el2_lib.scala 343:112]
+    node _T_742 = xorr(_T_741) @[el2_lib.scala 343:119]
+    node _T_743 = cat(_T_339[2], _T_339[1]) @[el2_lib.scala 343:129]
+    node _T_744 = cat(_T_743, _T_339[0]) @[el2_lib.scala 343:129]
+    node _T_745 = cat(_T_339[4], _T_339[3]) @[el2_lib.scala 343:129]
+    node _T_746 = cat(_T_339[6], _T_339[5]) @[el2_lib.scala 343:129]
+    node _T_747 = cat(_T_746, _T_745) @[el2_lib.scala 343:129]
+    node _T_748 = cat(_T_747, _T_744) @[el2_lib.scala 343:129]
+    node _T_749 = xorr(_T_748) @[el2_lib.scala 343:136]
+    node _T_750 = cat(_T_711, _T_742) @[Cat.scala 29:58]
+    node _T_751 = cat(_T_750, _T_749) @[Cat.scala 29:58]
+    node _T_752 = cat(_T_649, _T_680) @[Cat.scala 29:58]
+    node _T_753 = cat(_T_579, _T_614) @[Cat.scala 29:58]
+    node _T_754 = cat(_T_753, _T_752) @[Cat.scala 29:58]
+    node ic_wr_ecc = cat(_T_754, _T_751) @[Cat.scala 29:58]
+    wire _T_755 : UInt<1>[35] @[el2_lib.scala 322:18]
+    wire _T_756 : UInt<1>[35] @[el2_lib.scala 323:18]
+    wire _T_757 : UInt<1>[35] @[el2_lib.scala 324:18]
+    wire _T_758 : UInt<1>[31] @[el2_lib.scala 325:18]
+    wire _T_759 : UInt<1>[31] @[el2_lib.scala 326:18]
+    wire _T_760 : UInt<1>[31] @[el2_lib.scala 327:18]
+    wire _T_761 : UInt<1>[7] @[el2_lib.scala 328:18]
+    node _T_762 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 335:36]
+    _T_755[0] <= _T_762 @[el2_lib.scala 335:30]
+    node _T_763 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 336:36]
+    _T_756[0] <= _T_763 @[el2_lib.scala 336:30]
+    node _T_764 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 335:36]
+    _T_755[1] <= _T_764 @[el2_lib.scala 335:30]
+    node _T_765 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 337:36]
+    _T_757[0] <= _T_765 @[el2_lib.scala 337:30]
+    node _T_766 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 336:36]
+    _T_756[1] <= _T_766 @[el2_lib.scala 336:30]
+    node _T_767 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 337:36]
+    _T_757[1] <= _T_767 @[el2_lib.scala 337:30]
+    node _T_768 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 335:36]
+    _T_755[2] <= _T_768 @[el2_lib.scala 335:30]
+    node _T_769 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 336:36]
+    _T_756[2] <= _T_769 @[el2_lib.scala 336:30]
+    node _T_770 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 337:36]
+    _T_757[2] <= _T_770 @[el2_lib.scala 337:30]
+    node _T_771 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 335:36]
+    _T_755[3] <= _T_771 @[el2_lib.scala 335:30]
+    node _T_772 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 338:36]
+    _T_758[0] <= _T_772 @[el2_lib.scala 338:30]
+    node _T_773 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 336:36]
+    _T_756[3] <= _T_773 @[el2_lib.scala 336:30]
+    node _T_774 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 338:36]
+    _T_758[1] <= _T_774 @[el2_lib.scala 338:30]
+    node _T_775 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 335:36]
+    _T_755[4] <= _T_775 @[el2_lib.scala 335:30]
+    node _T_776 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 336:36]
+    _T_756[4] <= _T_776 @[el2_lib.scala 336:30]
+    node _T_777 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 338:36]
+    _T_758[2] <= _T_777 @[el2_lib.scala 338:30]
+    node _T_778 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 337:36]
+    _T_757[3] <= _T_778 @[el2_lib.scala 337:30]
+    node _T_779 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 338:36]
+    _T_758[3] <= _T_779 @[el2_lib.scala 338:30]
+    node _T_780 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 335:36]
+    _T_755[5] <= _T_780 @[el2_lib.scala 335:30]
+    node _T_781 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 337:36]
+    _T_757[4] <= _T_781 @[el2_lib.scala 337:30]
+    node _T_782 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 338:36]
+    _T_758[4] <= _T_782 @[el2_lib.scala 338:30]
+    node _T_783 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 336:36]
+    _T_756[5] <= _T_783 @[el2_lib.scala 336:30]
+    node _T_784 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 337:36]
+    _T_757[5] <= _T_784 @[el2_lib.scala 337:30]
+    node _T_785 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 338:36]
+    _T_758[5] <= _T_785 @[el2_lib.scala 338:30]
+    node _T_786 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 335:36]
+    _T_755[6] <= _T_786 @[el2_lib.scala 335:30]
+    node _T_787 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 336:36]
+    _T_756[6] <= _T_787 @[el2_lib.scala 336:30]
+    node _T_788 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 337:36]
+    _T_757[6] <= _T_788 @[el2_lib.scala 337:30]
+    node _T_789 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 338:36]
+    _T_758[6] <= _T_789 @[el2_lib.scala 338:30]
+    node _T_790 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 335:36]
+    _T_755[7] <= _T_790 @[el2_lib.scala 335:30]
+    node _T_791 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 339:36]
+    _T_759[0] <= _T_791 @[el2_lib.scala 339:30]
+    node _T_792 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 336:36]
+    _T_756[7] <= _T_792 @[el2_lib.scala 336:30]
+    node _T_793 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 339:36]
+    _T_759[1] <= _T_793 @[el2_lib.scala 339:30]
+    node _T_794 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 335:36]
+    _T_755[8] <= _T_794 @[el2_lib.scala 335:30]
+    node _T_795 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 336:36]
+    _T_756[8] <= _T_795 @[el2_lib.scala 336:30]
+    node _T_796 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 339:36]
+    _T_759[2] <= _T_796 @[el2_lib.scala 339:30]
+    node _T_797 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 337:36]
+    _T_757[7] <= _T_797 @[el2_lib.scala 337:30]
+    node _T_798 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 339:36]
+    _T_759[3] <= _T_798 @[el2_lib.scala 339:30]
+    node _T_799 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 335:36]
+    _T_755[9] <= _T_799 @[el2_lib.scala 335:30]
+    node _T_800 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 337:36]
+    _T_757[8] <= _T_800 @[el2_lib.scala 337:30]
+    node _T_801 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 339:36]
+    _T_759[4] <= _T_801 @[el2_lib.scala 339:30]
+    node _T_802 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 336:36]
+    _T_756[9] <= _T_802 @[el2_lib.scala 336:30]
+    node _T_803 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 337:36]
+    _T_757[9] <= _T_803 @[el2_lib.scala 337:30]
+    node _T_804 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 339:36]
+    _T_759[5] <= _T_804 @[el2_lib.scala 339:30]
+    node _T_805 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 335:36]
+    _T_755[10] <= _T_805 @[el2_lib.scala 335:30]
+    node _T_806 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 336:36]
+    _T_756[10] <= _T_806 @[el2_lib.scala 336:30]
+    node _T_807 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 337:36]
+    _T_757[10] <= _T_807 @[el2_lib.scala 337:30]
+    node _T_808 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 339:36]
+    _T_759[6] <= _T_808 @[el2_lib.scala 339:30]
+    node _T_809 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 338:36]
+    _T_758[7] <= _T_809 @[el2_lib.scala 338:30]
+    node _T_810 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 339:36]
+    _T_759[7] <= _T_810 @[el2_lib.scala 339:30]
+    node _T_811 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 335:36]
+    _T_755[11] <= _T_811 @[el2_lib.scala 335:30]
+    node _T_812 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 338:36]
+    _T_758[8] <= _T_812 @[el2_lib.scala 338:30]
+    node _T_813 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 339:36]
+    _T_759[8] <= _T_813 @[el2_lib.scala 339:30]
+    node _T_814 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 336:36]
+    _T_756[11] <= _T_814 @[el2_lib.scala 336:30]
+    node _T_815 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 338:36]
+    _T_758[9] <= _T_815 @[el2_lib.scala 338:30]
+    node _T_816 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 339:36]
+    _T_759[9] <= _T_816 @[el2_lib.scala 339:30]
+    node _T_817 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 335:36]
+    _T_755[12] <= _T_817 @[el2_lib.scala 335:30]
+    node _T_818 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 336:36]
+    _T_756[12] <= _T_818 @[el2_lib.scala 336:30]
+    node _T_819 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 338:36]
+    _T_758[10] <= _T_819 @[el2_lib.scala 338:30]
+    node _T_820 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 339:36]
+    _T_759[10] <= _T_820 @[el2_lib.scala 339:30]
+    node _T_821 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 337:36]
+    _T_757[11] <= _T_821 @[el2_lib.scala 337:30]
+    node _T_822 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 338:36]
+    _T_758[11] <= _T_822 @[el2_lib.scala 338:30]
+    node _T_823 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 339:36]
+    _T_759[11] <= _T_823 @[el2_lib.scala 339:30]
+    node _T_824 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 335:36]
+    _T_755[13] <= _T_824 @[el2_lib.scala 335:30]
+    node _T_825 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 337:36]
+    _T_757[12] <= _T_825 @[el2_lib.scala 337:30]
+    node _T_826 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 338:36]
+    _T_758[12] <= _T_826 @[el2_lib.scala 338:30]
+    node _T_827 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 339:36]
+    _T_759[12] <= _T_827 @[el2_lib.scala 339:30]
+    node _T_828 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 336:36]
+    _T_756[13] <= _T_828 @[el2_lib.scala 336:30]
+    node _T_829 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 337:36]
+    _T_757[13] <= _T_829 @[el2_lib.scala 337:30]
+    node _T_830 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 338:36]
+    _T_758[13] <= _T_830 @[el2_lib.scala 338:30]
+    node _T_831 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 339:36]
+    _T_759[13] <= _T_831 @[el2_lib.scala 339:30]
+    node _T_832 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 335:36]
+    _T_755[14] <= _T_832 @[el2_lib.scala 335:30]
+    node _T_833 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 336:36]
+    _T_756[14] <= _T_833 @[el2_lib.scala 336:30]
+    node _T_834 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 337:36]
+    _T_757[14] <= _T_834 @[el2_lib.scala 337:30]
+    node _T_835 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 338:36]
+    _T_758[14] <= _T_835 @[el2_lib.scala 338:30]
+    node _T_836 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 339:36]
+    _T_759[14] <= _T_836 @[el2_lib.scala 339:30]
+    node _T_837 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 335:36]
+    _T_755[15] <= _T_837 @[el2_lib.scala 335:30]
+    node _T_838 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 340:36]
+    _T_760[0] <= _T_838 @[el2_lib.scala 340:30]
+    node _T_839 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 336:36]
+    _T_756[15] <= _T_839 @[el2_lib.scala 336:30]
+    node _T_840 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 340:36]
+    _T_760[1] <= _T_840 @[el2_lib.scala 340:30]
+    node _T_841 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 335:36]
+    _T_755[16] <= _T_841 @[el2_lib.scala 335:30]
+    node _T_842 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 336:36]
+    _T_756[16] <= _T_842 @[el2_lib.scala 336:30]
+    node _T_843 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 340:36]
+    _T_760[2] <= _T_843 @[el2_lib.scala 340:30]
+    node _T_844 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 337:36]
+    _T_757[15] <= _T_844 @[el2_lib.scala 337:30]
+    node _T_845 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 340:36]
+    _T_760[3] <= _T_845 @[el2_lib.scala 340:30]
+    node _T_846 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 335:36]
+    _T_755[17] <= _T_846 @[el2_lib.scala 335:30]
+    node _T_847 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 337:36]
+    _T_757[16] <= _T_847 @[el2_lib.scala 337:30]
+    node _T_848 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 340:36]
+    _T_760[4] <= _T_848 @[el2_lib.scala 340:30]
+    node _T_849 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 336:36]
+    _T_756[17] <= _T_849 @[el2_lib.scala 336:30]
+    node _T_850 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 337:36]
+    _T_757[17] <= _T_850 @[el2_lib.scala 337:30]
+    node _T_851 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 340:36]
+    _T_760[5] <= _T_851 @[el2_lib.scala 340:30]
+    node _T_852 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 335:36]
+    _T_755[18] <= _T_852 @[el2_lib.scala 335:30]
+    node _T_853 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 336:36]
+    _T_756[18] <= _T_853 @[el2_lib.scala 336:30]
+    node _T_854 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 337:36]
+    _T_757[18] <= _T_854 @[el2_lib.scala 337:30]
+    node _T_855 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 340:36]
+    _T_760[6] <= _T_855 @[el2_lib.scala 340:30]
+    node _T_856 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 338:36]
+    _T_758[15] <= _T_856 @[el2_lib.scala 338:30]
+    node _T_857 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 340:36]
+    _T_760[7] <= _T_857 @[el2_lib.scala 340:30]
+    node _T_858 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 335:36]
+    _T_755[19] <= _T_858 @[el2_lib.scala 335:30]
+    node _T_859 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 338:36]
+    _T_758[16] <= _T_859 @[el2_lib.scala 338:30]
+    node _T_860 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 340:36]
+    _T_760[8] <= _T_860 @[el2_lib.scala 340:30]
+    node _T_861 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 336:36]
+    _T_756[19] <= _T_861 @[el2_lib.scala 336:30]
+    node _T_862 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 338:36]
+    _T_758[17] <= _T_862 @[el2_lib.scala 338:30]
+    node _T_863 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 340:36]
+    _T_760[9] <= _T_863 @[el2_lib.scala 340:30]
+    node _T_864 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 335:36]
+    _T_755[20] <= _T_864 @[el2_lib.scala 335:30]
+    node _T_865 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 336:36]
+    _T_756[20] <= _T_865 @[el2_lib.scala 336:30]
+    node _T_866 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 338:36]
+    _T_758[18] <= _T_866 @[el2_lib.scala 338:30]
+    node _T_867 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 340:36]
+    _T_760[10] <= _T_867 @[el2_lib.scala 340:30]
+    node _T_868 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 337:36]
+    _T_757[19] <= _T_868 @[el2_lib.scala 337:30]
+    node _T_869 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 338:36]
+    _T_758[19] <= _T_869 @[el2_lib.scala 338:30]
+    node _T_870 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 340:36]
+    _T_760[11] <= _T_870 @[el2_lib.scala 340:30]
+    node _T_871 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 335:36]
+    _T_755[21] <= _T_871 @[el2_lib.scala 335:30]
+    node _T_872 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 337:36]
+    _T_757[20] <= _T_872 @[el2_lib.scala 337:30]
+    node _T_873 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 338:36]
+    _T_758[20] <= _T_873 @[el2_lib.scala 338:30]
+    node _T_874 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 340:36]
+    _T_760[12] <= _T_874 @[el2_lib.scala 340:30]
+    node _T_875 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 336:36]
+    _T_756[21] <= _T_875 @[el2_lib.scala 336:30]
+    node _T_876 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 337:36]
+    _T_757[21] <= _T_876 @[el2_lib.scala 337:30]
+    node _T_877 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 338:36]
+    _T_758[21] <= _T_877 @[el2_lib.scala 338:30]
+    node _T_878 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 340:36]
+    _T_760[13] <= _T_878 @[el2_lib.scala 340:30]
+    node _T_879 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 335:36]
+    _T_755[22] <= _T_879 @[el2_lib.scala 335:30]
+    node _T_880 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 336:36]
+    _T_756[22] <= _T_880 @[el2_lib.scala 336:30]
+    node _T_881 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 337:36]
+    _T_757[22] <= _T_881 @[el2_lib.scala 337:30]
+    node _T_882 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 338:36]
+    _T_758[22] <= _T_882 @[el2_lib.scala 338:30]
+    node _T_883 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 340:36]
+    _T_760[14] <= _T_883 @[el2_lib.scala 340:30]
+    node _T_884 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 339:36]
+    _T_759[15] <= _T_884 @[el2_lib.scala 339:30]
+    node _T_885 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 340:36]
+    _T_760[15] <= _T_885 @[el2_lib.scala 340:30]
+    node _T_886 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 335:36]
+    _T_755[23] <= _T_886 @[el2_lib.scala 335:30]
+    node _T_887 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 339:36]
+    _T_759[16] <= _T_887 @[el2_lib.scala 339:30]
+    node _T_888 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 340:36]
+    _T_760[16] <= _T_888 @[el2_lib.scala 340:30]
+    node _T_889 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 336:36]
+    _T_756[23] <= _T_889 @[el2_lib.scala 336:30]
+    node _T_890 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 339:36]
+    _T_759[17] <= _T_890 @[el2_lib.scala 339:30]
+    node _T_891 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 340:36]
+    _T_760[17] <= _T_891 @[el2_lib.scala 340:30]
+    node _T_892 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 335:36]
+    _T_755[24] <= _T_892 @[el2_lib.scala 335:30]
+    node _T_893 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 336:36]
+    _T_756[24] <= _T_893 @[el2_lib.scala 336:30]
+    node _T_894 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 339:36]
+    _T_759[18] <= _T_894 @[el2_lib.scala 339:30]
+    node _T_895 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 340:36]
+    _T_760[18] <= _T_895 @[el2_lib.scala 340:30]
+    node _T_896 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 337:36]
+    _T_757[23] <= _T_896 @[el2_lib.scala 337:30]
+    node _T_897 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 339:36]
+    _T_759[19] <= _T_897 @[el2_lib.scala 339:30]
+    node _T_898 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 340:36]
+    _T_760[19] <= _T_898 @[el2_lib.scala 340:30]
+    node _T_899 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 335:36]
+    _T_755[25] <= _T_899 @[el2_lib.scala 335:30]
+    node _T_900 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 337:36]
+    _T_757[24] <= _T_900 @[el2_lib.scala 337:30]
+    node _T_901 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 339:36]
+    _T_759[20] <= _T_901 @[el2_lib.scala 339:30]
+    node _T_902 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 340:36]
+    _T_760[20] <= _T_902 @[el2_lib.scala 340:30]
+    node _T_903 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 336:36]
+    _T_756[25] <= _T_903 @[el2_lib.scala 336:30]
+    node _T_904 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 337:36]
+    _T_757[25] <= _T_904 @[el2_lib.scala 337:30]
+    node _T_905 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 339:36]
+    _T_759[21] <= _T_905 @[el2_lib.scala 339:30]
+    node _T_906 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 340:36]
+    _T_760[21] <= _T_906 @[el2_lib.scala 340:30]
+    node _T_907 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 335:36]
+    _T_755[26] <= _T_907 @[el2_lib.scala 335:30]
+    node _T_908 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 336:36]
+    _T_756[26] <= _T_908 @[el2_lib.scala 336:30]
+    node _T_909 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 337:36]
+    _T_757[26] <= _T_909 @[el2_lib.scala 337:30]
+    node _T_910 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 339:36]
+    _T_759[22] <= _T_910 @[el2_lib.scala 339:30]
+    node _T_911 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 340:36]
+    _T_760[22] <= _T_911 @[el2_lib.scala 340:30]
+    node _T_912 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 338:36]
+    _T_758[23] <= _T_912 @[el2_lib.scala 338:30]
+    node _T_913 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 339:36]
+    _T_759[23] <= _T_913 @[el2_lib.scala 339:30]
+    node _T_914 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 340:36]
+    _T_760[23] <= _T_914 @[el2_lib.scala 340:30]
+    node _T_915 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 335:36]
+    _T_755[27] <= _T_915 @[el2_lib.scala 335:30]
+    node _T_916 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 338:36]
+    _T_758[24] <= _T_916 @[el2_lib.scala 338:30]
+    node _T_917 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 339:36]
+    _T_759[24] <= _T_917 @[el2_lib.scala 339:30]
+    node _T_918 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 340:36]
+    _T_760[24] <= _T_918 @[el2_lib.scala 340:30]
+    node _T_919 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 336:36]
+    _T_756[27] <= _T_919 @[el2_lib.scala 336:30]
+    node _T_920 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 338:36]
+    _T_758[25] <= _T_920 @[el2_lib.scala 338:30]
+    node _T_921 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 339:36]
+    _T_759[25] <= _T_921 @[el2_lib.scala 339:30]
+    node _T_922 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 340:36]
+    _T_760[25] <= _T_922 @[el2_lib.scala 340:30]
+    node _T_923 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 335:36]
+    _T_755[28] <= _T_923 @[el2_lib.scala 335:30]
+    node _T_924 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 336:36]
+    _T_756[28] <= _T_924 @[el2_lib.scala 336:30]
+    node _T_925 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 338:36]
+    _T_758[26] <= _T_925 @[el2_lib.scala 338:30]
+    node _T_926 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 339:36]
+    _T_759[26] <= _T_926 @[el2_lib.scala 339:30]
+    node _T_927 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 340:36]
+    _T_760[26] <= _T_927 @[el2_lib.scala 340:30]
+    node _T_928 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 337:36]
+    _T_757[27] <= _T_928 @[el2_lib.scala 337:30]
+    node _T_929 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 338:36]
+    _T_758[27] <= _T_929 @[el2_lib.scala 338:30]
+    node _T_930 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 339:36]
+    _T_759[27] <= _T_930 @[el2_lib.scala 339:30]
+    node _T_931 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 340:36]
+    _T_760[27] <= _T_931 @[el2_lib.scala 340:30]
+    node _T_932 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 335:36]
+    _T_755[29] <= _T_932 @[el2_lib.scala 335:30]
+    node _T_933 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 337:36]
+    _T_757[28] <= _T_933 @[el2_lib.scala 337:30]
+    node _T_934 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 338:36]
+    _T_758[28] <= _T_934 @[el2_lib.scala 338:30]
+    node _T_935 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 339:36]
+    _T_759[28] <= _T_935 @[el2_lib.scala 339:30]
+    node _T_936 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 340:36]
+    _T_760[28] <= _T_936 @[el2_lib.scala 340:30]
+    node _T_937 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 336:36]
+    _T_756[29] <= _T_937 @[el2_lib.scala 336:30]
+    node _T_938 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 337:36]
+    _T_757[29] <= _T_938 @[el2_lib.scala 337:30]
+    node _T_939 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 338:36]
+    _T_758[29] <= _T_939 @[el2_lib.scala 338:30]
+    node _T_940 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 339:36]
+    _T_759[29] <= _T_940 @[el2_lib.scala 339:30]
+    node _T_941 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 340:36]
+    _T_760[29] <= _T_941 @[el2_lib.scala 340:30]
+    node _T_942 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 335:36]
+    _T_755[30] <= _T_942 @[el2_lib.scala 335:30]
+    node _T_943 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 336:36]
+    _T_756[30] <= _T_943 @[el2_lib.scala 336:30]
+    node _T_944 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 337:36]
+    _T_757[30] <= _T_944 @[el2_lib.scala 337:30]
+    node _T_945 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 338:36]
+    _T_758[30] <= _T_945 @[el2_lib.scala 338:30]
+    node _T_946 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 339:36]
+    _T_759[30] <= _T_946 @[el2_lib.scala 339:30]
+    node _T_947 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 340:36]
+    _T_760[30] <= _T_947 @[el2_lib.scala 340:30]
+    node _T_948 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 335:36]
+    _T_755[31] <= _T_948 @[el2_lib.scala 335:30]
+    node _T_949 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 341:36]
+    _T_761[0] <= _T_949 @[el2_lib.scala 341:30]
+    node _T_950 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 336:36]
+    _T_756[31] <= _T_950 @[el2_lib.scala 336:30]
+    node _T_951 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 341:36]
+    _T_761[1] <= _T_951 @[el2_lib.scala 341:30]
+    node _T_952 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 335:36]
+    _T_755[32] <= _T_952 @[el2_lib.scala 335:30]
+    node _T_953 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 336:36]
+    _T_756[32] <= _T_953 @[el2_lib.scala 336:30]
+    node _T_954 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 341:36]
+    _T_761[2] <= _T_954 @[el2_lib.scala 341:30]
+    node _T_955 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 337:36]
+    _T_757[31] <= _T_955 @[el2_lib.scala 337:30]
+    node _T_956 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 341:36]
+    _T_761[3] <= _T_956 @[el2_lib.scala 341:30]
+    node _T_957 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 335:36]
+    _T_755[33] <= _T_957 @[el2_lib.scala 335:30]
+    node _T_958 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 337:36]
+    _T_757[32] <= _T_958 @[el2_lib.scala 337:30]
+    node _T_959 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 341:36]
+    _T_761[4] <= _T_959 @[el2_lib.scala 341:30]
+    node _T_960 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 336:36]
+    _T_756[33] <= _T_960 @[el2_lib.scala 336:30]
+    node _T_961 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 337:36]
+    _T_757[33] <= _T_961 @[el2_lib.scala 337:30]
+    node _T_962 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 341:36]
+    _T_761[5] <= _T_962 @[el2_lib.scala 341:30]
+    node _T_963 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 335:36]
+    _T_755[34] <= _T_963 @[el2_lib.scala 335:30]
+    node _T_964 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 336:36]
+    _T_756[34] <= _T_964 @[el2_lib.scala 336:30]
+    node _T_965 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 337:36]
+    _T_757[34] <= _T_965 @[el2_lib.scala 337:30]
+    node _T_966 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 341:36]
+    _T_761[6] <= _T_966 @[el2_lib.scala 341:30]
+    node _T_967 = cat(_T_755[1], _T_755[0]) @[el2_lib.scala 343:27]
+    node _T_968 = cat(_T_755[3], _T_755[2]) @[el2_lib.scala 343:27]
+    node _T_969 = cat(_T_968, _T_967) @[el2_lib.scala 343:27]
+    node _T_970 = cat(_T_755[5], _T_755[4]) @[el2_lib.scala 343:27]
+    node _T_971 = cat(_T_755[7], _T_755[6]) @[el2_lib.scala 343:27]
+    node _T_972 = cat(_T_971, _T_970) @[el2_lib.scala 343:27]
+    node _T_973 = cat(_T_972, _T_969) @[el2_lib.scala 343:27]
+    node _T_974 = cat(_T_755[9], _T_755[8]) @[el2_lib.scala 343:27]
+    node _T_975 = cat(_T_755[11], _T_755[10]) @[el2_lib.scala 343:27]
+    node _T_976 = cat(_T_975, _T_974) @[el2_lib.scala 343:27]
+    node _T_977 = cat(_T_755[13], _T_755[12]) @[el2_lib.scala 343:27]
+    node _T_978 = cat(_T_755[16], _T_755[15]) @[el2_lib.scala 343:27]
+    node _T_979 = cat(_T_978, _T_755[14]) @[el2_lib.scala 343:27]
+    node _T_980 = cat(_T_979, _T_977) @[el2_lib.scala 343:27]
+    node _T_981 = cat(_T_980, _T_976) @[el2_lib.scala 343:27]
+    node _T_982 = cat(_T_981, _T_973) @[el2_lib.scala 343:27]
+    node _T_983 = cat(_T_755[18], _T_755[17]) @[el2_lib.scala 343:27]
+    node _T_984 = cat(_T_755[20], _T_755[19]) @[el2_lib.scala 343:27]
+    node _T_985 = cat(_T_984, _T_983) @[el2_lib.scala 343:27]
+    node _T_986 = cat(_T_755[22], _T_755[21]) @[el2_lib.scala 343:27]
+    node _T_987 = cat(_T_755[25], _T_755[24]) @[el2_lib.scala 343:27]
+    node _T_988 = cat(_T_987, _T_755[23]) @[el2_lib.scala 343:27]
+    node _T_989 = cat(_T_988, _T_986) @[el2_lib.scala 343:27]
+    node _T_990 = cat(_T_989, _T_985) @[el2_lib.scala 343:27]
+    node _T_991 = cat(_T_755[27], _T_755[26]) @[el2_lib.scala 343:27]
+    node _T_992 = cat(_T_755[29], _T_755[28]) @[el2_lib.scala 343:27]
+    node _T_993 = cat(_T_992, _T_991) @[el2_lib.scala 343:27]
+    node _T_994 = cat(_T_755[31], _T_755[30]) @[el2_lib.scala 343:27]
+    node _T_995 = cat(_T_755[34], _T_755[33]) @[el2_lib.scala 343:27]
+    node _T_996 = cat(_T_995, _T_755[32]) @[el2_lib.scala 343:27]
+    node _T_997 = cat(_T_996, _T_994) @[el2_lib.scala 343:27]
+    node _T_998 = cat(_T_997, _T_993) @[el2_lib.scala 343:27]
+    node _T_999 = cat(_T_998, _T_990) @[el2_lib.scala 343:27]
+    node _T_1000 = cat(_T_999, _T_982) @[el2_lib.scala 343:27]
+    node _T_1001 = xorr(_T_1000) @[el2_lib.scala 343:34]
+    node _T_1002 = cat(_T_756[1], _T_756[0]) @[el2_lib.scala 343:44]
+    node _T_1003 = cat(_T_756[3], _T_756[2]) @[el2_lib.scala 343:44]
+    node _T_1004 = cat(_T_1003, _T_1002) @[el2_lib.scala 343:44]
+    node _T_1005 = cat(_T_756[5], _T_756[4]) @[el2_lib.scala 343:44]
+    node _T_1006 = cat(_T_756[7], _T_756[6]) @[el2_lib.scala 343:44]
+    node _T_1007 = cat(_T_1006, _T_1005) @[el2_lib.scala 343:44]
+    node _T_1008 = cat(_T_1007, _T_1004) @[el2_lib.scala 343:44]
+    node _T_1009 = cat(_T_756[9], _T_756[8]) @[el2_lib.scala 343:44]
+    node _T_1010 = cat(_T_756[11], _T_756[10]) @[el2_lib.scala 343:44]
+    node _T_1011 = cat(_T_1010, _T_1009) @[el2_lib.scala 343:44]
+    node _T_1012 = cat(_T_756[13], _T_756[12]) @[el2_lib.scala 343:44]
+    node _T_1013 = cat(_T_756[16], _T_756[15]) @[el2_lib.scala 343:44]
+    node _T_1014 = cat(_T_1013, _T_756[14]) @[el2_lib.scala 343:44]
+    node _T_1015 = cat(_T_1014, _T_1012) @[el2_lib.scala 343:44]
+    node _T_1016 = cat(_T_1015, _T_1011) @[el2_lib.scala 343:44]
+    node _T_1017 = cat(_T_1016, _T_1008) @[el2_lib.scala 343:44]
+    node _T_1018 = cat(_T_756[18], _T_756[17]) @[el2_lib.scala 343:44]
+    node _T_1019 = cat(_T_756[20], _T_756[19]) @[el2_lib.scala 343:44]
+    node _T_1020 = cat(_T_1019, _T_1018) @[el2_lib.scala 343:44]
+    node _T_1021 = cat(_T_756[22], _T_756[21]) @[el2_lib.scala 343:44]
+    node _T_1022 = cat(_T_756[25], _T_756[24]) @[el2_lib.scala 343:44]
+    node _T_1023 = cat(_T_1022, _T_756[23]) @[el2_lib.scala 343:44]
+    node _T_1024 = cat(_T_1023, _T_1021) @[el2_lib.scala 343:44]
+    node _T_1025 = cat(_T_1024, _T_1020) @[el2_lib.scala 343:44]
+    node _T_1026 = cat(_T_756[27], _T_756[26]) @[el2_lib.scala 343:44]
+    node _T_1027 = cat(_T_756[29], _T_756[28]) @[el2_lib.scala 343:44]
+    node _T_1028 = cat(_T_1027, _T_1026) @[el2_lib.scala 343:44]
+    node _T_1029 = cat(_T_756[31], _T_756[30]) @[el2_lib.scala 343:44]
+    node _T_1030 = cat(_T_756[34], _T_756[33]) @[el2_lib.scala 343:44]
+    node _T_1031 = cat(_T_1030, _T_756[32]) @[el2_lib.scala 343:44]
+    node _T_1032 = cat(_T_1031, _T_1029) @[el2_lib.scala 343:44]
+    node _T_1033 = cat(_T_1032, _T_1028) @[el2_lib.scala 343:44]
+    node _T_1034 = cat(_T_1033, _T_1025) @[el2_lib.scala 343:44]
+    node _T_1035 = cat(_T_1034, _T_1017) @[el2_lib.scala 343:44]
+    node _T_1036 = xorr(_T_1035) @[el2_lib.scala 343:51]
+    node _T_1037 = cat(_T_757[1], _T_757[0]) @[el2_lib.scala 343:61]
+    node _T_1038 = cat(_T_757[3], _T_757[2]) @[el2_lib.scala 343:61]
+    node _T_1039 = cat(_T_1038, _T_1037) @[el2_lib.scala 343:61]
+    node _T_1040 = cat(_T_757[5], _T_757[4]) @[el2_lib.scala 343:61]
+    node _T_1041 = cat(_T_757[7], _T_757[6]) @[el2_lib.scala 343:61]
+    node _T_1042 = cat(_T_1041, _T_1040) @[el2_lib.scala 343:61]
+    node _T_1043 = cat(_T_1042, _T_1039) @[el2_lib.scala 343:61]
+    node _T_1044 = cat(_T_757[9], _T_757[8]) @[el2_lib.scala 343:61]
+    node _T_1045 = cat(_T_757[11], _T_757[10]) @[el2_lib.scala 343:61]
+    node _T_1046 = cat(_T_1045, _T_1044) @[el2_lib.scala 343:61]
+    node _T_1047 = cat(_T_757[13], _T_757[12]) @[el2_lib.scala 343:61]
+    node _T_1048 = cat(_T_757[16], _T_757[15]) @[el2_lib.scala 343:61]
+    node _T_1049 = cat(_T_1048, _T_757[14]) @[el2_lib.scala 343:61]
+    node _T_1050 = cat(_T_1049, _T_1047) @[el2_lib.scala 343:61]
+    node _T_1051 = cat(_T_1050, _T_1046) @[el2_lib.scala 343:61]
+    node _T_1052 = cat(_T_1051, _T_1043) @[el2_lib.scala 343:61]
+    node _T_1053 = cat(_T_757[18], _T_757[17]) @[el2_lib.scala 343:61]
+    node _T_1054 = cat(_T_757[20], _T_757[19]) @[el2_lib.scala 343:61]
+    node _T_1055 = cat(_T_1054, _T_1053) @[el2_lib.scala 343:61]
+    node _T_1056 = cat(_T_757[22], _T_757[21]) @[el2_lib.scala 343:61]
+    node _T_1057 = cat(_T_757[25], _T_757[24]) @[el2_lib.scala 343:61]
+    node _T_1058 = cat(_T_1057, _T_757[23]) @[el2_lib.scala 343:61]
+    node _T_1059 = cat(_T_1058, _T_1056) @[el2_lib.scala 343:61]
+    node _T_1060 = cat(_T_1059, _T_1055) @[el2_lib.scala 343:61]
+    node _T_1061 = cat(_T_757[27], _T_757[26]) @[el2_lib.scala 343:61]
+    node _T_1062 = cat(_T_757[29], _T_757[28]) @[el2_lib.scala 343:61]
+    node _T_1063 = cat(_T_1062, _T_1061) @[el2_lib.scala 343:61]
+    node _T_1064 = cat(_T_757[31], _T_757[30]) @[el2_lib.scala 343:61]
+    node _T_1065 = cat(_T_757[34], _T_757[33]) @[el2_lib.scala 343:61]
+    node _T_1066 = cat(_T_1065, _T_757[32]) @[el2_lib.scala 343:61]
+    node _T_1067 = cat(_T_1066, _T_1064) @[el2_lib.scala 343:61]
+    node _T_1068 = cat(_T_1067, _T_1063) @[el2_lib.scala 343:61]
+    node _T_1069 = cat(_T_1068, _T_1060) @[el2_lib.scala 343:61]
+    node _T_1070 = cat(_T_1069, _T_1052) @[el2_lib.scala 343:61]
+    node _T_1071 = xorr(_T_1070) @[el2_lib.scala 343:68]
+    node _T_1072 = cat(_T_758[2], _T_758[1]) @[el2_lib.scala 343:78]
+    node _T_1073 = cat(_T_1072, _T_758[0]) @[el2_lib.scala 343:78]
+    node _T_1074 = cat(_T_758[4], _T_758[3]) @[el2_lib.scala 343:78]
+    node _T_1075 = cat(_T_758[6], _T_758[5]) @[el2_lib.scala 343:78]
+    node _T_1076 = cat(_T_1075, _T_1074) @[el2_lib.scala 343:78]
+    node _T_1077 = cat(_T_1076, _T_1073) @[el2_lib.scala 343:78]
+    node _T_1078 = cat(_T_758[8], _T_758[7]) @[el2_lib.scala 343:78]
+    node _T_1079 = cat(_T_758[10], _T_758[9]) @[el2_lib.scala 343:78]
+    node _T_1080 = cat(_T_1079, _T_1078) @[el2_lib.scala 343:78]
+    node _T_1081 = cat(_T_758[12], _T_758[11]) @[el2_lib.scala 343:78]
+    node _T_1082 = cat(_T_758[14], _T_758[13]) @[el2_lib.scala 343:78]
+    node _T_1083 = cat(_T_1082, _T_1081) @[el2_lib.scala 343:78]
+    node _T_1084 = cat(_T_1083, _T_1080) @[el2_lib.scala 343:78]
+    node _T_1085 = cat(_T_1084, _T_1077) @[el2_lib.scala 343:78]
+    node _T_1086 = cat(_T_758[16], _T_758[15]) @[el2_lib.scala 343:78]
+    node _T_1087 = cat(_T_758[18], _T_758[17]) @[el2_lib.scala 343:78]
+    node _T_1088 = cat(_T_1087, _T_1086) @[el2_lib.scala 343:78]
+    node _T_1089 = cat(_T_758[20], _T_758[19]) @[el2_lib.scala 343:78]
+    node _T_1090 = cat(_T_758[22], _T_758[21]) @[el2_lib.scala 343:78]
+    node _T_1091 = cat(_T_1090, _T_1089) @[el2_lib.scala 343:78]
+    node _T_1092 = cat(_T_1091, _T_1088) @[el2_lib.scala 343:78]
+    node _T_1093 = cat(_T_758[24], _T_758[23]) @[el2_lib.scala 343:78]
+    node _T_1094 = cat(_T_758[26], _T_758[25]) @[el2_lib.scala 343:78]
+    node _T_1095 = cat(_T_1094, _T_1093) @[el2_lib.scala 343:78]
+    node _T_1096 = cat(_T_758[28], _T_758[27]) @[el2_lib.scala 343:78]
+    node _T_1097 = cat(_T_758[30], _T_758[29]) @[el2_lib.scala 343:78]
+    node _T_1098 = cat(_T_1097, _T_1096) @[el2_lib.scala 343:78]
+    node _T_1099 = cat(_T_1098, _T_1095) @[el2_lib.scala 343:78]
+    node _T_1100 = cat(_T_1099, _T_1092) @[el2_lib.scala 343:78]
+    node _T_1101 = cat(_T_1100, _T_1085) @[el2_lib.scala 343:78]
+    node _T_1102 = xorr(_T_1101) @[el2_lib.scala 343:85]
+    node _T_1103 = cat(_T_759[2], _T_759[1]) @[el2_lib.scala 343:95]
+    node _T_1104 = cat(_T_1103, _T_759[0]) @[el2_lib.scala 343:95]
+    node _T_1105 = cat(_T_759[4], _T_759[3]) @[el2_lib.scala 343:95]
+    node _T_1106 = cat(_T_759[6], _T_759[5]) @[el2_lib.scala 343:95]
+    node _T_1107 = cat(_T_1106, _T_1105) @[el2_lib.scala 343:95]
+    node _T_1108 = cat(_T_1107, _T_1104) @[el2_lib.scala 343:95]
+    node _T_1109 = cat(_T_759[8], _T_759[7]) @[el2_lib.scala 343:95]
+    node _T_1110 = cat(_T_759[10], _T_759[9]) @[el2_lib.scala 343:95]
+    node _T_1111 = cat(_T_1110, _T_1109) @[el2_lib.scala 343:95]
+    node _T_1112 = cat(_T_759[12], _T_759[11]) @[el2_lib.scala 343:95]
+    node _T_1113 = cat(_T_759[14], _T_759[13]) @[el2_lib.scala 343:95]
+    node _T_1114 = cat(_T_1113, _T_1112) @[el2_lib.scala 343:95]
+    node _T_1115 = cat(_T_1114, _T_1111) @[el2_lib.scala 343:95]
+    node _T_1116 = cat(_T_1115, _T_1108) @[el2_lib.scala 343:95]
+    node _T_1117 = cat(_T_759[16], _T_759[15]) @[el2_lib.scala 343:95]
+    node _T_1118 = cat(_T_759[18], _T_759[17]) @[el2_lib.scala 343:95]
+    node _T_1119 = cat(_T_1118, _T_1117) @[el2_lib.scala 343:95]
+    node _T_1120 = cat(_T_759[20], _T_759[19]) @[el2_lib.scala 343:95]
+    node _T_1121 = cat(_T_759[22], _T_759[21]) @[el2_lib.scala 343:95]
+    node _T_1122 = cat(_T_1121, _T_1120) @[el2_lib.scala 343:95]
+    node _T_1123 = cat(_T_1122, _T_1119) @[el2_lib.scala 343:95]
+    node _T_1124 = cat(_T_759[24], _T_759[23]) @[el2_lib.scala 343:95]
+    node _T_1125 = cat(_T_759[26], _T_759[25]) @[el2_lib.scala 343:95]
+    node _T_1126 = cat(_T_1125, _T_1124) @[el2_lib.scala 343:95]
+    node _T_1127 = cat(_T_759[28], _T_759[27]) @[el2_lib.scala 343:95]
+    node _T_1128 = cat(_T_759[30], _T_759[29]) @[el2_lib.scala 343:95]
+    node _T_1129 = cat(_T_1128, _T_1127) @[el2_lib.scala 343:95]
+    node _T_1130 = cat(_T_1129, _T_1126) @[el2_lib.scala 343:95]
+    node _T_1131 = cat(_T_1130, _T_1123) @[el2_lib.scala 343:95]
+    node _T_1132 = cat(_T_1131, _T_1116) @[el2_lib.scala 343:95]
+    node _T_1133 = xorr(_T_1132) @[el2_lib.scala 343:102]
+    node _T_1134 = cat(_T_760[2], _T_760[1]) @[el2_lib.scala 343:112]
+    node _T_1135 = cat(_T_1134, _T_760[0]) @[el2_lib.scala 343:112]
+    node _T_1136 = cat(_T_760[4], _T_760[3]) @[el2_lib.scala 343:112]
+    node _T_1137 = cat(_T_760[6], _T_760[5]) @[el2_lib.scala 343:112]
+    node _T_1138 = cat(_T_1137, _T_1136) @[el2_lib.scala 343:112]
+    node _T_1139 = cat(_T_1138, _T_1135) @[el2_lib.scala 343:112]
+    node _T_1140 = cat(_T_760[8], _T_760[7]) @[el2_lib.scala 343:112]
+    node _T_1141 = cat(_T_760[10], _T_760[9]) @[el2_lib.scala 343:112]
+    node _T_1142 = cat(_T_1141, _T_1140) @[el2_lib.scala 343:112]
+    node _T_1143 = cat(_T_760[12], _T_760[11]) @[el2_lib.scala 343:112]
+    node _T_1144 = cat(_T_760[14], _T_760[13]) @[el2_lib.scala 343:112]
+    node _T_1145 = cat(_T_1144, _T_1143) @[el2_lib.scala 343:112]
+    node _T_1146 = cat(_T_1145, _T_1142) @[el2_lib.scala 343:112]
+    node _T_1147 = cat(_T_1146, _T_1139) @[el2_lib.scala 343:112]
+    node _T_1148 = cat(_T_760[16], _T_760[15]) @[el2_lib.scala 343:112]
+    node _T_1149 = cat(_T_760[18], _T_760[17]) @[el2_lib.scala 343:112]
+    node _T_1150 = cat(_T_1149, _T_1148) @[el2_lib.scala 343:112]
+    node _T_1151 = cat(_T_760[20], _T_760[19]) @[el2_lib.scala 343:112]
+    node _T_1152 = cat(_T_760[22], _T_760[21]) @[el2_lib.scala 343:112]
+    node _T_1153 = cat(_T_1152, _T_1151) @[el2_lib.scala 343:112]
+    node _T_1154 = cat(_T_1153, _T_1150) @[el2_lib.scala 343:112]
+    node _T_1155 = cat(_T_760[24], _T_760[23]) @[el2_lib.scala 343:112]
+    node _T_1156 = cat(_T_760[26], _T_760[25]) @[el2_lib.scala 343:112]
+    node _T_1157 = cat(_T_1156, _T_1155) @[el2_lib.scala 343:112]
+    node _T_1158 = cat(_T_760[28], _T_760[27]) @[el2_lib.scala 343:112]
+    node _T_1159 = cat(_T_760[30], _T_760[29]) @[el2_lib.scala 343:112]
+    node _T_1160 = cat(_T_1159, _T_1158) @[el2_lib.scala 343:112]
+    node _T_1161 = cat(_T_1160, _T_1157) @[el2_lib.scala 343:112]
+    node _T_1162 = cat(_T_1161, _T_1154) @[el2_lib.scala 343:112]
+    node _T_1163 = cat(_T_1162, _T_1147) @[el2_lib.scala 343:112]
+    node _T_1164 = xorr(_T_1163) @[el2_lib.scala 343:119]
+    node _T_1165 = cat(_T_761[2], _T_761[1]) @[el2_lib.scala 343:129]
+    node _T_1166 = cat(_T_1165, _T_761[0]) @[el2_lib.scala 343:129]
+    node _T_1167 = cat(_T_761[4], _T_761[3]) @[el2_lib.scala 343:129]
+    node _T_1168 = cat(_T_761[6], _T_761[5]) @[el2_lib.scala 343:129]
+    node _T_1169 = cat(_T_1168, _T_1167) @[el2_lib.scala 343:129]
+    node _T_1170 = cat(_T_1169, _T_1166) @[el2_lib.scala 343:129]
+    node _T_1171 = xorr(_T_1170) @[el2_lib.scala 343:136]
+    node _T_1172 = cat(_T_1133, _T_1164) @[Cat.scala 29:58]
+    node _T_1173 = cat(_T_1172, _T_1171) @[Cat.scala 29:58]
+    node _T_1174 = cat(_T_1071, _T_1102) @[Cat.scala 29:58]
+    node _T_1175 = cat(_T_1001, _T_1036) @[Cat.scala 29:58]
+    node _T_1176 = cat(_T_1175, _T_1174) @[Cat.scala 29:58]
+    node ic_miss_buff_ecc = cat(_T_1176, _T_1173) @[Cat.scala 29:58]
+    wire ic_wr_16bytes_data : UInt<142>
+    ic_wr_16bytes_data <= UInt<1>("h00")
+    node _T_1177 = bits(ic_wr_16bytes_data, 70, 0) @[el2_ifu_mem_ctl.scala 388:72]
+    node _T_1178 = bits(ic_wr_16bytes_data, 141, 71) @[el2_ifu_mem_ctl.scala 388:72]
+    io.ic_wr_data[0] <= _T_1177 @[el2_ifu_mem_ctl.scala 388:17]
+    io.ic_wr_data[1] <= _T_1178 @[el2_ifu_mem_ctl.scala 388:17]
+    io.ic_debug_wr_data <= io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_ifu_mem_ctl.scala 389:23]
+    wire ic_rd_parity_final_err : UInt<1>
+    ic_rd_parity_final_err <= UInt<1>("h00")
+    node _T_1179 = orr(io.ic_eccerr) @[el2_ifu_mem_ctl.scala 391:56]
+    node _T_1180 = and(_T_1179, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 391:83]
+    node _T_1181 = or(_T_1180, ic_rd_parity_final_err) @[el2_ifu_mem_ctl.scala 391:99]
+    io.ic_error_start <= _T_1181 @[el2_ifu_mem_ctl.scala 391:21]
+    wire ic_debug_tag_val_rd_out : UInt<1>
+    ic_debug_tag_val_rd_out <= UInt<1>("h00")
+    wire ic_debug_ict_array_sel_ff : UInt<1>
+    ic_debug_ict_array_sel_ff <= UInt<1>("h00")
+    node _T_1182 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[el2_ifu_mem_ctl.scala 394:63]
+    node _T_1183 = bits(io.ictag_debug_rd_data, 25, 21) @[el2_ifu_mem_ctl.scala 394:121]
+    node _T_1184 = bits(io.ictag_debug_rd_data, 20, 0) @[el2_ifu_mem_ctl.scala 394:161]
+    node _T_1185 = cat(UInt<3>("h00"), ic_debug_tag_val_rd_out) @[Cat.scala 29:58]
+    node _T_1186 = cat(UInt<1>("h00"), way_status) @[Cat.scala 29:58]
+    node _T_1187 = cat(_T_1186, _T_1185) @[Cat.scala 29:58]
+    node _T_1188 = cat(UInt<32>("h00"), _T_1184) @[Cat.scala 29:58]
+    node _T_1189 = cat(UInt<2>("h00"), _T_1183) @[Cat.scala 29:58]
+    node _T_1190 = cat(_T_1189, _T_1188) @[Cat.scala 29:58]
+    node _T_1191 = cat(_T_1190, _T_1187) @[Cat.scala 29:58]
+    node ifu_ic_debug_rd_data_in = mux(_T_1182, _T_1191, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 394:36]
+    reg _T_1192 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 397:37]
+    _T_1192 <= ifu_ic_debug_rd_data_in @[el2_ifu_mem_ctl.scala 397:37]
+    io.ifu_ic_debug_rd_data <= _T_1192 @[el2_ifu_mem_ctl.scala 397:27]
+    node _T_1193 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 398:74]
+    node _T_1194 = xorr(_T_1193) @[el2_lib.scala 203:13]
+    node _T_1195 = bits(ifu_bus_rdata_ff, 31, 16) @[el2_ifu_mem_ctl.scala 398:74]
+    node _T_1196 = xorr(_T_1195) @[el2_lib.scala 203:13]
+    node _T_1197 = bits(ifu_bus_rdata_ff, 47, 32) @[el2_ifu_mem_ctl.scala 398:74]
+    node _T_1198 = xorr(_T_1197) @[el2_lib.scala 203:13]
+    node _T_1199 = bits(ifu_bus_rdata_ff, 63, 48) @[el2_ifu_mem_ctl.scala 398:74]
+    node _T_1200 = xorr(_T_1199) @[el2_lib.scala 203:13]
+    node _T_1201 = cat(_T_1200, _T_1198) @[Cat.scala 29:58]
+    node _T_1202 = cat(_T_1201, _T_1196) @[Cat.scala 29:58]
+    node ic_wr_parity = cat(_T_1202, _T_1194) @[Cat.scala 29:58]
+    node _T_1203 = bits(ic_miss_buff_half, 15, 0) @[el2_ifu_mem_ctl.scala 399:82]
+    node _T_1204 = xorr(_T_1203) @[el2_lib.scala 203:13]
+    node _T_1205 = bits(ic_miss_buff_half, 31, 16) @[el2_ifu_mem_ctl.scala 399:82]
+    node _T_1206 = xorr(_T_1205) @[el2_lib.scala 203:13]
+    node _T_1207 = bits(ic_miss_buff_half, 47, 32) @[el2_ifu_mem_ctl.scala 399:82]
+    node _T_1208 = xorr(_T_1207) @[el2_lib.scala 203:13]
+    node _T_1209 = bits(ic_miss_buff_half, 63, 48) @[el2_ifu_mem_ctl.scala 399:82]
+    node _T_1210 = xorr(_T_1209) @[el2_lib.scala 203:13]
+    node _T_1211 = cat(_T_1210, _T_1208) @[Cat.scala 29:58]
+    node _T_1212 = cat(_T_1211, _T_1206) @[Cat.scala 29:58]
+    node ic_miss_buff_parity = cat(_T_1212, _T_1204) @[Cat.scala 29:58]
+    node _T_1213 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 401:43]
+    node _T_1214 = bits(_T_1213, 0, 0) @[el2_ifu_mem_ctl.scala 401:47]
+    node _T_1215 = bits(ifu_bus_rdata_ff, 63, 0) @[el2_ifu_mem_ctl.scala 401:117]
+    node _T_1216 = bits(ic_miss_buff_half, 63, 0) @[el2_ifu_mem_ctl.scala 401:201]
+    node _T_1217 = cat(ic_miss_buff_ecc, _T_1216) @[Cat.scala 29:58]
+    node _T_1218 = cat(ic_wr_ecc, _T_1215) @[Cat.scala 29:58]
+    node _T_1219 = cat(_T_1218, _T_1217) @[Cat.scala 29:58]
+    node _T_1220 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58]
+    node _T_1221 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58]
+    node _T_1222 = cat(_T_1221, _T_1220) @[Cat.scala 29:58]
+    node _T_1223 = mux(_T_1214, _T_1219, _T_1222) @[el2_ifu_mem_ctl.scala 401:28]
+    ic_wr_16bytes_data <= _T_1223 @[el2_ifu_mem_ctl.scala 401:22]
+    wire bus_ifu_wr_data_error_ff : UInt<1>
+    bus_ifu_wr_data_error_ff <= UInt<1>("h00")
+    wire ifu_wr_data_comb_err_ff : UInt<1>
+    ifu_wr_data_comb_err_ff <= UInt<1>("h00")
+    wire reset_beat_cnt : UInt<1>
+    reset_beat_cnt <= UInt<1>("h00")
+    node _T_1224 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 407:53]
+    node _T_1225 = eq(reset_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 407:82]
+    node ifu_wr_cumulative_err = and(_T_1224, _T_1225) @[el2_ifu_mem_ctl.scala 407:80]
+    node _T_1226 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 408:55]
+    ifu_wr_cumulative_err_data <= _T_1226 @[el2_ifu_mem_ctl.scala 408:30]
+    reg _T_1227 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 409:61]
+    _T_1227 <= ifu_wr_cumulative_err @[el2_ifu_mem_ctl.scala 409:61]
+    ifu_wr_data_comb_err_ff <= _T_1227 @[el2_ifu_mem_ctl.scala 409:27]
+    wire ic_crit_wd_rdy : UInt<1>
+    ic_crit_wd_rdy <= UInt<1>("h00")
+    wire ifu_byp_data_err_new : UInt<1>
+    ifu_byp_data_err_new <= UInt<1>("h00")
+    node _T_1228 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 412:51]
+    node _T_1229 = or(ic_crit_wd_rdy, _T_1228) @[el2_ifu_mem_ctl.scala 412:38]
+    node _T_1230 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 412:77]
+    node _T_1231 = or(_T_1229, _T_1230) @[el2_ifu_mem_ctl.scala 412:64]
+    node _T_1232 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 412:98]
+    node sel_byp_data = and(_T_1231, _T_1232) @[el2_ifu_mem_ctl.scala 412:96]
+    node _T_1233 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 413:51]
+    node _T_1234 = or(ic_crit_wd_rdy, _T_1233) @[el2_ifu_mem_ctl.scala 413:38]
+    node _T_1235 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 413:77]
+    node _T_1236 = or(_T_1234, _T_1235) @[el2_ifu_mem_ctl.scala 413:64]
+    node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 413:21]
+    node _T_1238 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 413:98]
+    node sel_ic_data = and(_T_1237, _T_1238) @[el2_ifu_mem_ctl.scala 413:96]
+    wire ic_byp_data_only_new : UInt<80>
+    ic_byp_data_only_new <= UInt<1>("h00")
+    node _T_1239 = or(fetch_req_iccm_f, sel_ic_data) @[el2_ifu_mem_ctl.scala 417:81]
+    node _T_1240 = or(sel_byp_data, _T_1239) @[el2_ifu_mem_ctl.scala 417:47]
+    node _T_1241 = bits(_T_1240, 0, 0) @[el2_ifu_mem_ctl.scala 417:140]
+    node _T_1242 = bits(fetch_req_iccm_f, 0, 0) @[Bitwise.scala 72:15]
+    node _T_1243 = mux(_T_1242, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
+    node _T_1244 = and(_T_1243, io.iccm_rd_data) @[el2_ifu_mem_ctl.scala 419:64]
+    node _T_1245 = bits(sel_byp_data, 0, 0) @[Bitwise.scala 72:15]
+    node _T_1246 = mux(_T_1245, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
+    node _T_1247 = and(_T_1246, ic_byp_data_only_new) @[el2_ifu_mem_ctl.scala 419:109]
+    node ic_premux_data = or(_T_1244, _T_1247) @[el2_ifu_mem_ctl.scala 419:83]
+    node ic_sel_premux_data = or(fetch_req_iccm_f, sel_byp_data) @[el2_ifu_mem_ctl.scala 421:58]
+    node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[el2_ifu_mem_ctl.scala 423:42]
+    node _T_1248 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 425:40]
+    node fetch_req_f_qual = and(io.ic_hit_f, _T_1248) @[el2_ifu_mem_ctl.scala 425:38]
+    wire ifc_region_acc_fault_memory_f : UInt<1>
+    ifc_region_acc_fault_memory_f <= UInt<1>("h00")
+    node _T_1249 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 427:57]
+    node _T_1250 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 427:82]
+    node _T_1251 = and(_T_1249, _T_1250) @[el2_ifu_mem_ctl.scala 427:80]
+    io.ic_access_fault_f <= _T_1251 @[el2_ifu_mem_ctl.scala 427:24]
+    node _T_1252 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[el2_ifu_mem_ctl.scala 428:62]
+    node _T_1253 = bits(ifc_region_acc_fault_f, 0, 0) @[el2_ifu_mem_ctl.scala 429:32]
+    node _T_1254 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[el2_ifu_mem_ctl.scala 430:47]
+    node _T_1255 = mux(_T_1254, UInt<2>("h03"), UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 430:10]
+    node _T_1256 = mux(_T_1253, UInt<2>("h02"), _T_1255) @[el2_ifu_mem_ctl.scala 429:8]
+    node _T_1257 = mux(_T_1252, UInt<1>("h01"), _T_1256) @[el2_ifu_mem_ctl.scala 428:35]
+    io.ic_access_fault_type_f <= _T_1257 @[el2_ifu_mem_ctl.scala 428:29]
     
diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v
index 2e7706c0..fcb2eea1 100644
--- a/el2_ifu_mem_ctl.v
+++ b/el2_ifu_mem_ctl.v
@@ -1,3 +1,22 @@
+module rvclkhdr(
+  input   io_clk,
+  input   io_en,
+  input   io_scan_mode
+);
+  wire  clkhdr_Q; // @[el2_lib.scala 403:26]
+  wire  clkhdr_CK; // @[el2_lib.scala 403:26]
+  wire  clkhdr_EN; // @[el2_lib.scala 403:26]
+  wire  clkhdr_SE; // @[el2_lib.scala 403:26]
+  TEC_RV_ICG clkhdr ( // @[el2_lib.scala 403:26]
+    .Q(clkhdr_Q),
+    .CK(clkhdr_CK),
+    .EN(clkhdr_EN),
+    .SE(clkhdr_SE)
+  );
+  assign clkhdr_CK = io_clk; // @[el2_lib.scala 405:18]
+  assign clkhdr_EN = io_en; // @[el2_lib.scala 406:18]
+  assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 407:18]
+endmodule
 module el2_ifu_mem_ctl(
   input         clock,
   input         reset,
@@ -119,81 +138,379 @@ module el2_ifu_mem_ctl(
   input         io_dec_tlu_core_ecc_disable,
   output        io_ifu_ic_debug_rd_data_valid,
   output        io_iccm_buf_correct_ecc,
-  output        io_iccm_correction_state
+  output        io_iccm_correction_state,
+  input         io_scan_mode
 );
-  assign io_ifu_miss_state_idle = 1'h0; // @[el2_ifu_mem_ctl.scala 129:25]
-  assign io_ifu_ic_mb_empty = 1'h0; // @[el2_ifu_mem_ctl.scala 130:21]
-  assign io_ic_dma_active = 1'h0; // @[el2_ifu_mem_ctl.scala 131:19]
-  assign io_ic_write_stall = 1'h0; // @[el2_ifu_mem_ctl.scala 132:20]
-  assign io_ifu_pmu_ic_miss = 1'h0; // @[el2_ifu_mem_ctl.scala 133:21]
-  assign io_ifu_pmu_ic_hit = 1'h0; // @[el2_ifu_mem_ctl.scala 134:20]
-  assign io_ifu_pmu_bus_error = 1'h0; // @[el2_ifu_mem_ctl.scala 135:23]
-  assign io_ifu_pmu_bus_busy = 1'h0; // @[el2_ifu_mem_ctl.scala 136:22]
-  assign io_ifu_pmu_bus_trxn = 1'h0; // @[el2_ifu_mem_ctl.scala 137:22]
-  assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 138:21]
-  assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 139:18]
-  assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 140:20]
-  assign io_ifu_axi_awregion = 4'h0; // @[el2_ifu_mem_ctl.scala 199:22]
-  assign io_ifu_axi_awlen = 8'h0; // @[el2_ifu_mem_ctl.scala 141:19]
-  assign io_ifu_axi_awsize = 3'h0; // @[el2_ifu_mem_ctl.scala 142:20]
-  assign io_ifu_axi_awburst = 2'h0; // @[el2_ifu_mem_ctl.scala 143:21]
-  assign io_ifu_axi_awlock = 1'h0; // @[el2_ifu_mem_ctl.scala 144:20]
-  assign io_ifu_axi_awcache = 4'h0; // @[el2_ifu_mem_ctl.scala 145:21]
-  assign io_ifu_axi_awprot = 3'h0; // @[el2_ifu_mem_ctl.scala 146:20]
-  assign io_ifu_axi_awqos = 4'h0; // @[el2_ifu_mem_ctl.scala 147:19]
-  assign io_ifu_axi_wvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 148:20]
-  assign io_ifu_axi_wdata = 64'h0; // @[el2_ifu_mem_ctl.scala 149:19]
-  assign io_ifu_axi_wstrb = 8'h0; // @[el2_ifu_mem_ctl.scala 150:19]
-  assign io_ifu_axi_wlast = 1'h0; // @[el2_ifu_mem_ctl.scala 151:19]
-  assign io_ifu_axi_bready = 1'h0; // @[el2_ifu_mem_ctl.scala 152:20]
-  assign io_ifu_axi_arvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 153:21]
-  assign io_ifu_axi_arid = 3'h0; // @[el2_ifu_mem_ctl.scala 155:18]
-  assign io_ifu_axi_araddr = 32'h0; // @[el2_ifu_mem_ctl.scala 156:20]
-  assign io_ifu_axi_arregion = 4'h0; // @[el2_ifu_mem_ctl.scala 157:22]
-  assign io_ifu_axi_arlen = 8'h0; // @[el2_ifu_mem_ctl.scala 158:19]
-  assign io_ifu_axi_arsize = 3'h0; // @[el2_ifu_mem_ctl.scala 159:20]
-  assign io_ifu_axi_arburst = 2'h0; // @[el2_ifu_mem_ctl.scala 160:21]
-  assign io_ifu_axi_arlock = 1'h0; // @[el2_ifu_mem_ctl.scala 161:20]
-  assign io_ifu_axi_arcache = 4'h0; // @[el2_ifu_mem_ctl.scala 162:21]
-  assign io_ifu_axi_arprot = 3'h0; // @[el2_ifu_mem_ctl.scala 163:20]
-  assign io_ifu_axi_arqos = 4'h0; // @[el2_ifu_mem_ctl.scala 164:19]
-  assign io_ifu_axi_rready = 1'h0; // @[el2_ifu_mem_ctl.scala 165:20]
-  assign io_iccm_dma_ecc_error = 1'h0; // @[el2_ifu_mem_ctl.scala 166:24]
-  assign io_iccm_dma_rvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 167:21]
-  assign io_iccm_dma_rdata = 64'h0; // @[el2_ifu_mem_ctl.scala 168:20]
-  assign io_iccm_dma_rtag = 3'h0; // @[el2_ifu_mem_ctl.scala 169:19]
-  assign io_iccm_ready = 1'h0; // @[el2_ifu_mem_ctl.scala 170:16]
-  assign io_ic_rw_addr = 31'h0; // @[el2_ifu_mem_ctl.scala 171:16]
-  assign io_ic_wr_en = 2'h0; // @[el2_ifu_mem_ctl.scala 172:14]
-  assign io_ic_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 173:14]
-  assign io_ic_wr_data_0 = 71'h0; // @[el2_ifu_mem_ctl.scala 174:16]
-  assign io_ic_wr_data_1 = 71'h0; // @[el2_ifu_mem_ctl.scala 174:16]
-  assign io_ic_debug_wr_data = 71'h0; // @[el2_ifu_mem_ctl.scala 175:22]
-  assign io_ifu_ic_debug_rd_data = 71'h0; // @[el2_ifu_mem_ctl.scala 176:26]
-  assign io_ic_debug_addr = 10'h0; // @[el2_ifu_mem_ctl.scala 154:19]
-  assign io_ic_debug_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 126:20]
-  assign io_ic_debug_wr_en = 1'h0; // @[el2_ifu_mem_ctl.scala 127:20]
-  assign io_ic_debug_tag_array = 1'h0; // @[el2_ifu_mem_ctl.scala 128:24]
-  assign io_ic_debug_way = 2'h0; // @[el2_ifu_mem_ctl.scala 198:18]
-  assign io_ic_tag_valid = 2'h0; // @[el2_ifu_mem_ctl.scala 177:18]
-  assign io_iccm_rw_addr = 15'h0; // @[el2_ifu_mem_ctl.scala 178:18]
-  assign io_iccm_wren = 1'h0; // @[el2_ifu_mem_ctl.scala 179:15]
-  assign io_iccm_rden = 1'h0; // @[el2_ifu_mem_ctl.scala 180:15]
-  assign io_iccm_wr_data = 78'h0; // @[el2_ifu_mem_ctl.scala 181:18]
-  assign io_iccm_wr_size = 3'h0; // @[el2_ifu_mem_ctl.scala 182:18]
-  assign io_ic_hit_f = 1'h0; // @[el2_ifu_mem_ctl.scala 183:14]
-  assign io_ic_access_fault_f = 1'h0; // @[el2_ifu_mem_ctl.scala 184:23]
-  assign io_ic_access_fault_type_f = 2'h0; // @[el2_ifu_mem_ctl.scala 185:28]
-  assign io_iccm_rd_ecc_single_err = 1'h0; // @[el2_ifu_mem_ctl.scala 186:28]
-  assign io_iccm_rd_ecc_double_err = 1'h0; // @[el2_ifu_mem_ctl.scala 187:28]
-  assign io_ic_error_start = 1'h0; // @[el2_ifu_mem_ctl.scala 188:20]
-  assign io_ifu_async_error_start = 1'h0; // @[el2_ifu_mem_ctl.scala 189:27]
-  assign io_iccm_dma_sb_error = 1'h0; // @[el2_ifu_mem_ctl.scala 190:23]
-  assign io_ic_fetch_val_f = 2'h0; // @[el2_ifu_mem_ctl.scala 191:20]
-  assign io_ic_data_f = 32'h0; // @[el2_ifu_mem_ctl.scala 192:15]
-  assign io_ic_premux_data = 64'h0; // @[el2_ifu_mem_ctl.scala 193:20]
-  assign io_ic_sel_premux_data = 1'h0; // @[el2_ifu_mem_ctl.scala 194:24]
-  assign io_ifu_ic_debug_rd_data_valid = 1'h0; // @[el2_ifu_mem_ctl.scala 195:32]
-  assign io_iccm_buf_correct_ecc = 1'h0; // @[el2_ifu_mem_ctl.scala 196:26]
-  assign io_iccm_correction_state = 1'h0; // @[el2_ifu_mem_ctl.scala 197:27]
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [31:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [95:0] _RAND_8;
+`endif // RANDOMIZE_REG_INIT
+  wire  rvclkhdr_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_io_scan_mode; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_1_io_clk; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_1_io_en; // @[el2_lib.scala 412:22]
+  wire  rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 412:22]
+  reg  flush_final_f; // @[el2_ifu_mem_ctl.scala 234:30]
+  reg  ifc_fetch_req_f_raw; // @[el2_ifu_mem_ctl.scala 367:36]
+  wire  _T_308 = ~io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 368:44]
+  wire  ifc_fetch_req_f = ifc_fetch_req_f_raw & _T_308; // @[el2_ifu_mem_ctl.scala 368:42]
+  wire  _T = io_ifc_fetch_req_bf_raw | ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 235:53]
+  reg [2:0] miss_state; // @[Reg.scala 27:20]
+  wire  miss_pending = miss_state != 3'h0; // @[el2_ifu_mem_ctl.scala 300:30]
+  wire  _T_1 = _T | miss_pending; // @[el2_ifu_mem_ctl.scala 235:71]
+  wire  _T_26 = 3'h0 == miss_state; // @[Conditional.scala 37:30]
+  wire  _T_219 = |io_ic_rd_hit; // @[el2_ifu_mem_ctl.scala 330:37]
+  wire  _T_220 = ~_T_219; // @[el2_ifu_mem_ctl.scala 330:23]
+  reg  ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 369:31]
+  wire  _T_199 = ~ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 321:48]
+  wire  fetch_req_icache_f = ifc_fetch_req_f & _T_199; // @[el2_ifu_mem_ctl.scala 321:46]
+  wire  _T_222 = _T_220 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 330:59]
+  wire  _T_223 = ~miss_pending; // @[el2_ifu_mem_ctl.scala 330:82]
+  wire  ic_act_miss_f = _T_222 & _T_223; // @[el2_ifu_mem_ctl.scala 330:80]
+  wire  _T_28 = ic_act_miss_f & _T_308; // @[el2_ifu_mem_ctl.scala 249:43]
+  wire [2:0] _T_30 = _T_28 ? 3'h1 : 3'h2; // @[el2_ifu_mem_ctl.scala 249:27]
+  wire  _T_33 = 3'h1 == miss_state; // @[Conditional.scala 37:30]
+  reg  uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 357:33]
+  wire  _T_52 = ~uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 255:51]
+  wire  ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[el2_ifu_mem_ctl.scala 245:52]
+  wire  _T_74 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 258:44]
+  wire [2:0] _T_79 = _T_74 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 258:22]
+  wire [2:0] _T_85 = io_dec_tlu_force_halt ? 3'h0 : _T_79; // @[el2_ifu_mem_ctl.scala 252:27]
+  wire  _T_94 = 3'h4 == miss_state; // @[Conditional.scala 37:30]
+  wire  _T_98 = 3'h6 == miss_state; // @[Conditional.scala 37:30]
+  wire  _T_104 = ~io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 266:124]
+  wire  _T_105 = _T_74 & _T_104; // @[el2_ifu_mem_ctl.scala 266:122]
+  wire [2:0] _T_107 = _T_105 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 266:27]
+  wire  _T_113 = 3'h3 == miss_state; // @[Conditional.scala 37:30]
+  wire  _T_118 = io_exu_flush_final & _T_104; // @[el2_ifu_mem_ctl.scala 270:82]
+  wire [2:0] _T_120 = _T_118 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 270:27]
+  wire  _T_124 = 3'h2 == miss_state; // @[Conditional.scala 37:30]
+  wire  _T_228 = io_ic_rd_hit == 2'h0; // @[el2_ifu_mem_ctl.scala 331:28]
+  wire  _T_230 = _T_228 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 331:60]
+  wire  _T_231 = miss_state == 3'h2; // @[el2_ifu_mem_ctl.scala 331:94]
+  wire  _T_232 = _T_230 & _T_231; // @[el2_ifu_mem_ctl.scala 331:81]
+  reg [30:0] imb_ff; // @[el2_ifu_mem_ctl.scala 358:20]
+  reg [30:0] ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 355:34]
+  wire  _T_235 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 332:39]
+  wire  _T_236 = _T_232 & _T_235; // @[el2_ifu_mem_ctl.scala 331:111]
+  wire  ic_miss_under_miss_f = _T_236 & _T_52; // @[el2_ifu_mem_ctl.scala 332:91]
+  wire  _T_129 = ic_miss_under_miss_f & _T_104; // @[el2_ifu_mem_ctl.scala 274:84]
+  wire  _T_248 = _T_222 & _T_231; // @[el2_ifu_mem_ctl.scala 333:85]
+  wire  _T_251 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 334:39]
+  wire  _T_252 = _T_251 | uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 334:91]
+  wire  ic_ignore_2nd_miss_f = _T_248 & _T_252; // @[el2_ifu_mem_ctl.scala 333:117]
+  wire  _T_135 = ic_ignore_2nd_miss_f & _T_104; // @[el2_ifu_mem_ctl.scala 275:69]
+  wire [2:0] _T_137 = _T_135 ? 3'h7 : 3'h0; // @[el2_ifu_mem_ctl.scala 275:12]
+  wire [2:0] _T_138 = _T_129 ? 3'h5 : _T_137; // @[el2_ifu_mem_ctl.scala 274:27]
+  wire  _T_143 = 3'h5 == miss_state; // @[Conditional.scala 37:30]
+  wire [2:0] _T_147 = io_exu_flush_final ? 3'h2 : 3'h1; // @[el2_ifu_mem_ctl.scala 279:62]
+  wire [2:0] _T_148 = io_dec_tlu_force_halt ? 3'h0 : _T_147; // @[el2_ifu_mem_ctl.scala 279:27]
+  wire  _T_152 = 3'h7 == miss_state; // @[Conditional.scala 37:30]
+  wire [2:0] _T_156 = io_exu_flush_final ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 284:62]
+  wire [2:0] _T_157 = io_dec_tlu_force_halt ? 3'h0 : _T_156; // @[el2_ifu_mem_ctl.scala 284:27]
+  wire [2:0] _GEN_0 = _T_152 ? _T_157 : 3'h0; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_2 = _T_143 ? _T_148 : _GEN_0; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_4 = _T_124 ? _T_138 : _GEN_2; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_6 = _T_113 ? _T_120 : _GEN_4; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_8 = _T_98 ? _T_107 : _GEN_6; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_10 = _T_94 ? 3'h0 : _GEN_8; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_12 = _T_33 ? _T_85 : _GEN_10; // @[Conditional.scala 39:67]
+  wire [2:0] miss_nxtstate = _T_26 ? _T_30 : _GEN_12; // @[Conditional.scala 40:58]
+  wire  _T_32 = ic_act_miss_f & _T_104; // @[el2_ifu_mem_ctl.scala 250:38]
+  wire  _T_86 = io_dec_tlu_force_halt | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 259:46]
+  wire  _T_88 = _T_86 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 259:82]
+  wire  _T_95 = io_exu_flush_final | flush_final_f; // @[el2_ifu_mem_ctl.scala 263:43]
+  wire  _T_97 = _T_95 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 263:74]
+  wire  _T_112 = _T_74 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 267:118]
+  wire  _T_123 = io_exu_flush_final | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 271:76]
+  wire  _T_141 = ic_miss_under_miss_f | ic_ignore_2nd_miss_f; // @[el2_ifu_mem_ctl.scala 276:78]
+  wire  _T_142 = _T_141 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 276:101]
+  wire  _GEN_1 = _T_152 & _T_123; // @[Conditional.scala 39:67]
+  wire  _GEN_3 = _T_143 ? _T_123 : _GEN_1; // @[Conditional.scala 39:67]
+  wire  _GEN_5 = _T_124 ? _T_142 : _GEN_3; // @[Conditional.scala 39:67]
+  wire  _GEN_7 = _T_113 ? _T_123 : _GEN_5; // @[Conditional.scala 39:67]
+  wire  _GEN_9 = _T_98 ? _T_112 : _GEN_7; // @[Conditional.scala 39:67]
+  wire  _GEN_11 = _T_94 ? _T_97 : _GEN_9; // @[Conditional.scala 39:67]
+  wire  _GEN_13 = _T_33 ? _T_88 : _GEN_11; // @[Conditional.scala 39:67]
+  wire  miss_state_en = _T_26 ? _T_32 : _GEN_13; // @[Conditional.scala 40:58]
+  wire  _T_165 = miss_state == 3'h4; // @[el2_ifu_mem_ctl.scala 301:73]
+  wire  _T_172 = _T_165 & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 302:106]
+  wire  _T_173 = ~_T_172; // @[el2_ifu_mem_ctl.scala 302:72]
+  wire  _T_174 = miss_pending & _T_173; // @[el2_ifu_mem_ctl.scala 302:70]
+  wire  _T_179 = _T_174 | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 303:77]
+  wire  _T_180 = miss_nxtstate == 3'h4; // @[el2_ifu_mem_ctl.scala 304:36]
+  wire  _T_181 = miss_pending & _T_180; // @[el2_ifu_mem_ctl.scala 304:19]
+  wire  sel_hold_imb = _T_179 | _T_181; // @[el2_ifu_mem_ctl.scala 303:93]
+  wire  fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 322:46]
+  wire  _T_204 = _T_223 | _T_231; // @[el2_ifu_mem_ctl.scala 323:59]
+  wire  _T_205 = miss_state == 3'h6; // @[el2_ifu_mem_ctl.scala 323:105]
+  wire  _T_206 = _T_204 | _T_205; // @[el2_ifu_mem_ctl.scala 323:91]
+  wire  ic_iccm_hit_f = fetch_req_iccm_f & _T_206; // @[el2_ifu_mem_ctl.scala 323:41]
+  wire  _T_211 = _T_219 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 329:39]
+  wire  ic_act_hit_f = _T_211 & _T_204; // @[el2_ifu_mem_ctl.scala 329:78]
+  wire  _T_304 = _T_165 & flush_final_f; // @[el2_ifu_mem_ctl.scala 366:87]
+  wire  _T_305 = ~_T_304; // @[el2_ifu_mem_ctl.scala 366:55]
+  wire  ifc_fetch_req_qual_bf = io_ifc_fetch_req_bf & _T_305; // @[el2_ifu_mem_ctl.scala 366:53]
+  reg  ifc_region_acc_fault_f; // @[el2_ifu_mem_ctl.scala 372:39]
+  wire  _T_1179 = |io_ic_eccerr; // @[el2_ifu_mem_ctl.scala 391:56]
+  reg [70:0] _T_1192; // @[el2_ifu_mem_ctl.scala 397:37]
+  wire [1:0] _T_1256 = ifc_region_acc_fault_f ? 2'h2 : 2'h0; // @[el2_ifu_mem_ctl.scala 429:8]
+  rvclkhdr rvclkhdr ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_io_clk),
+    .io_en(rvclkhdr_io_en),
+    .io_scan_mode(rvclkhdr_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 412:22]
+    .io_clk(rvclkhdr_1_io_clk),
+    .io_en(rvclkhdr_1_io_en),
+    .io_scan_mode(rvclkhdr_1_io_scan_mode)
+  );
+  assign io_ifu_miss_state_idle = 1'h0; // @[el2_ifu_mem_ctl.scala 131:25]
+  assign io_ifu_ic_mb_empty = 1'h0; // @[el2_ifu_mem_ctl.scala 132:21]
+  assign io_ic_dma_active = io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 133:19 el2_ifu_mem_ctl.scala 241:20]
+  assign io_ic_write_stall = 1'h0; // @[el2_ifu_mem_ctl.scala 134:20]
+  assign io_ifu_pmu_ic_miss = 1'h0; // @[el2_ifu_mem_ctl.scala 135:21]
+  assign io_ifu_pmu_ic_hit = 1'h0; // @[el2_ifu_mem_ctl.scala 136:20]
+  assign io_ifu_pmu_bus_error = 1'h0; // @[el2_ifu_mem_ctl.scala 137:23]
+  assign io_ifu_pmu_bus_busy = 1'h0; // @[el2_ifu_mem_ctl.scala 138:22]
+  assign io_ifu_pmu_bus_trxn = 1'h0; // @[el2_ifu_mem_ctl.scala 139:22]
+  assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 140:21]
+  assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 141:18]
+  assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 142:20]
+  assign io_ifu_axi_awregion = 4'h0; // @[el2_ifu_mem_ctl.scala 201:22]
+  assign io_ifu_axi_awlen = 8'h0; // @[el2_ifu_mem_ctl.scala 143:19]
+  assign io_ifu_axi_awsize = 3'h0; // @[el2_ifu_mem_ctl.scala 144:20]
+  assign io_ifu_axi_awburst = 2'h0; // @[el2_ifu_mem_ctl.scala 145:21]
+  assign io_ifu_axi_awlock = 1'h0; // @[el2_ifu_mem_ctl.scala 146:20]
+  assign io_ifu_axi_awcache = 4'h0; // @[el2_ifu_mem_ctl.scala 147:21]
+  assign io_ifu_axi_awprot = 3'h0; // @[el2_ifu_mem_ctl.scala 148:20]
+  assign io_ifu_axi_awqos = 4'h0; // @[el2_ifu_mem_ctl.scala 149:19]
+  assign io_ifu_axi_wvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 150:20]
+  assign io_ifu_axi_wdata = 64'h0; // @[el2_ifu_mem_ctl.scala 151:19]
+  assign io_ifu_axi_wstrb = 8'h0; // @[el2_ifu_mem_ctl.scala 152:19]
+  assign io_ifu_axi_wlast = 1'h0; // @[el2_ifu_mem_ctl.scala 153:19]
+  assign io_ifu_axi_bready = 1'h0; // @[el2_ifu_mem_ctl.scala 154:20]
+  assign io_ifu_axi_arvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 155:21]
+  assign io_ifu_axi_arid = 3'h0; // @[el2_ifu_mem_ctl.scala 157:18]
+  assign io_ifu_axi_araddr = 32'h0; // @[el2_ifu_mem_ctl.scala 158:20]
+  assign io_ifu_axi_arregion = 4'h0; // @[el2_ifu_mem_ctl.scala 159:22]
+  assign io_ifu_axi_arlen = 8'h0; // @[el2_ifu_mem_ctl.scala 160:19]
+  assign io_ifu_axi_arsize = 3'h0; // @[el2_ifu_mem_ctl.scala 161:20]
+  assign io_ifu_axi_arburst = 2'h0; // @[el2_ifu_mem_ctl.scala 162:21]
+  assign io_ifu_axi_arlock = 1'h0; // @[el2_ifu_mem_ctl.scala 163:20]
+  assign io_ifu_axi_arcache = 4'h0; // @[el2_ifu_mem_ctl.scala 164:21]
+  assign io_ifu_axi_arprot = 3'h0; // @[el2_ifu_mem_ctl.scala 165:20]
+  assign io_ifu_axi_arqos = 4'h0; // @[el2_ifu_mem_ctl.scala 166:19]
+  assign io_ifu_axi_rready = 1'h0; // @[el2_ifu_mem_ctl.scala 167:20]
+  assign io_iccm_dma_ecc_error = 1'h0; // @[el2_ifu_mem_ctl.scala 168:24]
+  assign io_iccm_dma_rvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 169:21]
+  assign io_iccm_dma_rdata = 64'h0; // @[el2_ifu_mem_ctl.scala 170:20]
+  assign io_iccm_dma_rtag = 3'h0; // @[el2_ifu_mem_ctl.scala 171:19]
+  assign io_iccm_ready = 1'h0; // @[el2_ifu_mem_ctl.scala 172:16]
+  assign io_ic_rw_addr = 31'h0; // @[el2_ifu_mem_ctl.scala 173:16]
+  assign io_ic_wr_en = 2'h0; // @[el2_ifu_mem_ctl.scala 174:14]
+  assign io_ic_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 175:14]
+  assign io_ic_wr_data_0 = 71'h0; // @[el2_ifu_mem_ctl.scala 176:16 el2_ifu_mem_ctl.scala 388:17]
+  assign io_ic_wr_data_1 = 71'h0; // @[el2_ifu_mem_ctl.scala 176:16 el2_ifu_mem_ctl.scala 388:17]
+  assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 177:22 el2_ifu_mem_ctl.scala 389:23]
+  assign io_ifu_ic_debug_rd_data = _T_1192; // @[el2_ifu_mem_ctl.scala 178:26 el2_ifu_mem_ctl.scala 397:27]
+  assign io_ic_debug_addr = 10'h0; // @[el2_ifu_mem_ctl.scala 156:19]
+  assign io_ic_debug_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 128:20]
+  assign io_ic_debug_wr_en = 1'h0; // @[el2_ifu_mem_ctl.scala 129:20]
+  assign io_ic_debug_tag_array = 1'h0; // @[el2_ifu_mem_ctl.scala 130:24]
+  assign io_ic_debug_way = 2'h0; // @[el2_ifu_mem_ctl.scala 200:18]
+  assign io_ic_tag_valid = 2'h0; // @[el2_ifu_mem_ctl.scala 179:18]
+  assign io_iccm_rw_addr = 15'h0; // @[el2_ifu_mem_ctl.scala 180:18]
+  assign io_iccm_wren = 1'h0; // @[el2_ifu_mem_ctl.scala 181:15]
+  assign io_iccm_rden = 1'h0; // @[el2_ifu_mem_ctl.scala 182:15]
+  assign io_iccm_wr_data = 78'h0; // @[el2_ifu_mem_ctl.scala 183:18]
+  assign io_iccm_wr_size = 3'h0; // @[el2_ifu_mem_ctl.scala 184:18]
+  assign io_ic_hit_f = ic_act_hit_f | ic_iccm_hit_f; // @[el2_ifu_mem_ctl.scala 185:14 el2_ifu_mem_ctl.scala 336:15]
+  assign io_ic_access_fault_f = 1'h0; // @[el2_ifu_mem_ctl.scala 186:23 el2_ifu_mem_ctl.scala 427:24]
+  assign io_ic_access_fault_type_f = io_iccm_rd_ecc_double_err ? 2'h1 : _T_1256; // @[el2_ifu_mem_ctl.scala 187:28 el2_ifu_mem_ctl.scala 428:29]
+  assign io_iccm_rd_ecc_single_err = 1'h0; // @[el2_ifu_mem_ctl.scala 188:28]
+  assign io_iccm_rd_ecc_double_err = 1'h0; // @[el2_ifu_mem_ctl.scala 189:28]
+  assign io_ic_error_start = _T_1179 & ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 190:20 el2_ifu_mem_ctl.scala 391:21]
+  assign io_ifu_async_error_start = io_iccm_rd_ecc_single_err | io_ic_error_start; // @[el2_ifu_mem_ctl.scala 191:27 el2_ifu_mem_ctl.scala 240:28]
+  assign io_iccm_dma_sb_error = 1'h0; // @[el2_ifu_mem_ctl.scala 192:23 el2_ifu_mem_ctl.scala 239:24]
+  assign io_ic_fetch_val_f = 2'h0; // @[el2_ifu_mem_ctl.scala 193:20]
+  assign io_ic_data_f = 32'h0; // @[el2_ifu_mem_ctl.scala 194:15]
+  assign io_ic_premux_data = 64'h0; // @[el2_ifu_mem_ctl.scala 195:20]
+  assign io_ic_sel_premux_data = 1'h0; // @[el2_ifu_mem_ctl.scala 196:24]
+  assign io_ifu_ic_debug_rd_data_valid = 1'h0; // @[el2_ifu_mem_ctl.scala 197:32]
+  assign io_iccm_buf_correct_ecc = 1'h0; // @[el2_ifu_mem_ctl.scala 198:26]
+  assign io_iccm_correction_state = 1'h0; // @[el2_ifu_mem_ctl.scala 199:27]
+  assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+  assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 413:17]
+  assign rvclkhdr_1_io_en = _T_1 | io_exu_flush_final; // @[el2_lib.scala 414:16]
+  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  flush_final_f = _RAND_0[0:0];
+  _RAND_1 = {1{`RANDOM}};
+  ifc_fetch_req_f_raw = _RAND_1[0:0];
+  _RAND_2 = {1{`RANDOM}};
+  miss_state = _RAND_2[2:0];
+  _RAND_3 = {1{`RANDOM}};
+  ifc_iccm_access_f = _RAND_3[0:0];
+  _RAND_4 = {1{`RANDOM}};
+  uncacheable_miss_ff = _RAND_4[0:0];
+  _RAND_5 = {1{`RANDOM}};
+  imb_ff = _RAND_5[30:0];
+  _RAND_6 = {1{`RANDOM}};
+  ifu_fetch_addr_int_f = _RAND_6[30:0];
+  _RAND_7 = {1{`RANDOM}};
+  ifc_region_acc_fault_f = _RAND_7[0:0];
+  _RAND_8 = {3{`RANDOM}};
+  _T_1192 = _RAND_8[70:0];
+`endif // RANDOMIZE_REG_INIT
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge clock) begin
+    if (reset) begin
+      flush_final_f <= 1'h0;
+    end else begin
+      flush_final_f <= io_exu_flush_final;
+    end
+    if (reset) begin
+      ifc_fetch_req_f_raw <= 1'h0;
+    end else begin
+      ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf;
+    end
+    if (reset) begin
+      miss_state <= 3'h0;
+    end else if (miss_state_en) begin
+      if (_T_26) begin
+        if (_T_28) begin
+          miss_state <= 3'h1;
+        end else begin
+          miss_state <= 3'h2;
+        end
+      end else if (_T_33) begin
+        if (io_dec_tlu_force_halt) begin
+          miss_state <= 3'h0;
+        end else if (_T_74) begin
+          miss_state <= 3'h2;
+        end else begin
+          miss_state <= 3'h0;
+        end
+      end else if (_T_94) begin
+        miss_state <= 3'h0;
+      end else if (_T_98) begin
+        if (_T_105) begin
+          miss_state <= 3'h2;
+        end else begin
+          miss_state <= 3'h0;
+        end
+      end else if (_T_113) begin
+        if (_T_118) begin
+          miss_state <= 3'h2;
+        end else begin
+          miss_state <= 3'h0;
+        end
+      end else if (_T_124) begin
+        if (_T_129) begin
+          miss_state <= 3'h5;
+        end else if (_T_135) begin
+          miss_state <= 3'h7;
+        end else begin
+          miss_state <= 3'h0;
+        end
+      end else if (_T_143) begin
+        if (io_dec_tlu_force_halt) begin
+          miss_state <= 3'h0;
+        end else if (io_exu_flush_final) begin
+          miss_state <= 3'h2;
+        end else begin
+          miss_state <= 3'h1;
+        end
+      end else if (_T_152) begin
+        if (io_dec_tlu_force_halt) begin
+          miss_state <= 3'h0;
+        end else if (io_exu_flush_final) begin
+          miss_state <= 3'h2;
+        end else begin
+          miss_state <= 3'h0;
+        end
+      end else begin
+        miss_state <= 3'h0;
+      end
+    end
+    if (reset) begin
+      ifc_iccm_access_f <= 1'h0;
+    end else begin
+      ifc_iccm_access_f <= io_ifc_iccm_access_bf;
+    end
+    if (reset) begin
+      uncacheable_miss_ff <= 1'h0;
+    end else if (!(sel_hold_imb)) begin
+      uncacheable_miss_ff <= io_ifc_fetch_uncacheable_bf;
+    end
+    if (!(sel_hold_imb)) begin
+      imb_ff <= io_ifc_fetch_addr_bf;
+    end
+    if (reset) begin
+      ifu_fetch_addr_int_f <= 31'h0;
+    end else begin
+      ifu_fetch_addr_int_f <= io_ifc_fetch_addr_bf;
+    end
+    if (reset) begin
+      ifc_region_acc_fault_f <= 1'h0;
+    end else begin
+      ifc_region_acc_fault_f <= io_ifc_region_acc_fault_bf;
+    end
+    if (reset) begin
+      _T_1192 <= 71'h0;
+    end else begin
+      _T_1192 <= io_ic_debug_rd_data;
+    end
+  end
 endmodule
diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
index 7c3f06f5..f8f45a6b 100644
--- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
@@ -25,7 +25,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
     val dec_i0_decode_d         = Input(Bool())
     val ifu_fetch_data_f        = Input(UInt(32.W))
     val ifu_fetch_val           = Input(UInt(2.W))
-    val ifu_fetch_pc            = Input(UInt(32.W))
+    val ifu_fetch_pc            = Input(UInt(31.W))
     val ifu_i0_valid            = Output(Bool())
     val ifu_i0_icaf             = Output(Bool())
     val ifu_i0_icaf_type        = Output(UInt(2.W))
@@ -84,12 +84,37 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   val brdata0 = WireInit(UInt(12.W), init = 0.U)
   val brdata2 = WireInit(UInt(12.W), init = 0.U)
 
+  val f1pc_in = WireInit(UInt(31.W), 0.U)
+  val f0pc_in = WireInit(UInt(31.W), 0.U)
+  val error_stall = WireInit(Bool(), 0.U)
 
-
-  val error_stall = withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
-  val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
   error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
 
+  error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
+  val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
+  val rdptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
+
+  val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
+  val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
+  val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
+
+  val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
+  val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
+  val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
+
+  val f2pc = RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool)
+  val f1pc = RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool)
+  val f0pc = RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool)
+
+  brdata2 := RegEnable(brdata_in, 0.U, qwen(2))
+  brdata1 := RegEnable(brdata_in, 0.U, qwen(1))
+  brdata0 := RegEnable(brdata_in, 0.U, qwen(0))
+
+  misc2 := RegEnable(misc_data_in, 0.U, qwen(2))
+  misc1 := RegEnable(misc_data_in, 0.U, qwen(1))
+  misc0 := RegEnable(misc_data_in, 0.U, qwen(0))
+
+
   val i0_shift = io.dec_i0_decode_d & ~error_stall
 
   io.ifu_pmu_instr_aligned := i0_shift
@@ -120,16 +145,10 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   val f0_shift_2B = Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0))))
   val f1_shift_2B =  f0val(0) & !f0val(1) & shift_4B
 
-  val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
-  val rdptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
-
-  val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
-  val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
 
 
-  val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
-  val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
-  val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
+
+
 
   val fetch_to_f0        =  !sf0_valid & !sf1_valid & !f2_valid & ifvalid
   val fetch_to_f1        = (!sf0_valid & !sf1_valid &  f2_valid & ifvalid)  |
@@ -259,18 +278,18 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   shift_f2_f0 := !sf0_valid & !sf1_valid &  f2_valid
   shift_f2_f1 := !sf0_valid &  sf1_valid &  f2_valid
 
-  val f0pc = WireInit(UInt(31.W), 0.U)
-  val f2pc = WireInit(UInt(31.W), 0.U)
+  //val f0pc = WireInit(UInt(31.W), 0.U)
+ // val f2pc = WireInit(UInt(31.W), 0.U)
 
   val f0pc_plus1 = f0pc + 1.U
 
   val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, !f1_shift_2B) & f0pc)
 
-  val f1pc_in = Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
+  f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
                           shift_f2_f1.asBool->f2pc,
                           (!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
 
-  val f0pc_in = Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
+  f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
                           shift_f2_f0.asBool->f2pc,
                           shift_f1_f0.asBool->sf1pc,
                           (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
@@ -313,7 +332,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
 
   val alignfromf1 = !f0val(1) & f0val(0)
 
-  val f1pc = WireInit(UInt(31.W), init = 0.U)
+  //val f1pc = WireInit(UInt(31.W), init = 0.U)
 
   val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
 
@@ -364,21 +383,13 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
 
   io.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
 
-  brdata2 := RegEnable(brdata_in, 0.U, qwen(2))
-  brdata1 := RegEnable(brdata_in, 0.U, qwen(1))
-  brdata0 := RegEnable(brdata_in, 0.U, qwen(0))
 
-  misc2 := RegEnable(misc_data_in, 0.U, qwen(2))
-  misc1 := RegEnable(misc_data_in, 0.U, qwen(1))
-  misc0 := RegEnable(misc_data_in, 0.U, qwen(0))
 
   q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2))
   q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1))
   q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0))
 
-  f2pc := RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool)
-  f2pc := RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool)
-  f2pc := RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool)
+
 }
 object ifu_aln extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl()))
diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
index be4913d5..a74fcc93 100644
--- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
@@ -215,12 +215,23 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   val err_stop_fetch = WireInit(Bool(), 0.U)
   val miss_state = WireInit(UInt(3.W), 0.U)
   val miss_nxtstate = WireInit(UInt(3.W), 0.U)
+  val miss_state_en = WireInit(Bool(), 0.U)
   val ifu_bus_rsp_valid = WireInit(Bool(), 0.U)
   val bus_ifu_bus_clk_en = WireInit(Bool(), 0.U)
   val ifu_bus_rsp_ready = WireInit(Bool(), 0.U)
   val uncacheable_miss_ff = WireInit(Bool(), 0.U)
+  val ic_act_miss_f = WireInit(Bool(), 0.U)
+  val ic_byp_hit_f = WireInit(Bool(), 0.U)
   val bus_new_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
+  val bus_ifu_wr_en_ff = WireInit(Bool(), 0.U)
+  val last_beat = WireInit(Bool(), 0.U)
+  val last_data_recieved_ff = WireInit(Bool(), 0.U)
+  //val flush_final_f = WireInit(Bool(), 0.U)
+  val stream_eol_f = WireInit(Bool(), 0.U)
+  val ic_miss_under_miss_f = WireInit(Bool(), 0.U)
+  val ic_ignore_2nd_miss_f = WireInit(Bool(), 0.U)
 
+  val flush_final_f = RegNext(io.exu_flush_final, 0.U)
   val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req
   val debug_c1_clken = io.ic_debug_rd_en | io.ic_debug_wr_en
   val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode)
@@ -233,7 +244,194 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
 
   val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f
 
+  switch(miss_state){
+    is (idle_C){
+      miss_nxtstate := Mux((ic_act_miss_f & !io.exu_flush_final).asBool, crit_byp_ok_C, hit_u_miss_C)
+      miss_state_en := ic_act_miss_f & !io.dec_tlu_force_halt}
+    is (crit_byp_ok_C){
+      miss_nxtstate := Mux((io.dec_tlu_force_halt | ic_byp_hit_f &  (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) &  uncacheable_miss_ff).asBool, idle_C,
+        Mux((ic_byp_hit_f &  !last_data_recieved_ff &  uncacheable_miss_ff).asBool, miss_wait_C,
+          Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) &  uncacheable_miss_ff).asBool, crit_byp_ok_C,
+            Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
+              Mux(((ic_byp_hit_f | bus_ifu_wr_en_ff) & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
+                Mux((!ic_byp_hit_f  &  !io.exu_flush_final &  (bus_ifu_wr_en_ff & last_beat)       & !uncacheable_miss_ff).asBool, idle_C,
+                  Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))
+      miss_state_en := io.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff)
+    }
+    is (crit_wrd_rdy_C){
+      miss_nxtstate := idle_C
+      miss_state_en := io.exu_flush_final | flush_final_f | ic_byp_hit_f | io.dec_tlu_force_halt
+    }
+    is (stream_C){
+      miss_nxtstate := Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f)&(!(bus_ifu_wr_en_ff & last_beat)) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
+      miss_state_en := io.exu_flush_final | ifu_bp_hit_taken_q_f  | stream_eol_f   |  (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt
+    }
+    is (miss_wait_C){
+      miss_nxtstate := Mux((io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
+      miss_state_en := io.exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt
+    }
+    is (hit_u_miss_C){
+      miss_nxtstate := Mux((ic_miss_under_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, scnd_miss_C,
+        Mux((ic_ignore_2nd_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, stall_scnd_miss_C, idle_C))
+      miss_state_en := (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | io.dec_tlu_force_halt
+    }
+    is (scnd_miss_C){
+      miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
+        Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), crit_byp_ok_C))
+      miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt
+    }
+    is (stall_scnd_miss_C){
+      miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
+        Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), idle_C))
+      miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt
+    }
+  }
+  miss_state := RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)
+  val crit_byp_hit_f = WireInit(Bool(), 0.U)
+  val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
+  val way_status = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
+  val tagv_mb_scnd_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
+  val ic_tag_valid = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
+  val uncacheable_miss_scnd_ff = WireInit(Bool(), 0.U)
+  val imb_scnd_ff = WireInit(UInt(31.W), 0.U)
+  val reset_all_tags = WireInit(Bool(), 0.U)
+  val bus_rd_addr_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
+  val ifu_bus_rid_ff = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
+  miss_pending := miss_state =/= idle_C
+  val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f)
+  val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) &
+                      !((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
+    (miss_pending & (miss_nxtstate === crit_wrd_rdy_C))
 
+  val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f
+  val way_status_mb_scnd_in = Mux(miss_state === scnd_miss_C, way_status_mb_scnd_ff, way_status)
+
+  val tagv_mb_scnd_in = Mux(miss_state === scnd_miss_C, tagv_mb_scnd_ff, Fill(ICACHE_NUM_WAYS, !reset_all_tags) & ic_tag_valid)
+  val uncacheable_miss_scnd_in = Mux(sel_hold_imb_scnd.asBool, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf)
+  uncacheable_miss_scnd_ff := RegNext(uncacheable_miss_scnd_in, 0.U)
+  val imb_scnd_in = Mux(sel_hold_imb_scnd.asBool, imb_scnd_ff, io.ifc_fetch_addr_bf)
+  imb_scnd_ff := RegNext(imb_scnd_in, 0.U)
+  way_status_mb_scnd_ff := RegNext(way_status_mb_scnd_in, 0.U)
+  tagv_mb_scnd_ff := RegNext(tagv_mb_scnd_in, 0.U)
+
+  val ic_req_addr_bits_hi_3 = bus_rd_addr_count
+  val ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & Fill(ICACHE_BEAT_BITS, bus_ifu_wr_en_ff)
+  val ifc_iccm_access_f = WireInit(Bool(), 0.U)
+  val ifc_region_acc_fault_final_f = WireInit(Bool(), 0.U)
+  val fetch_req_icache_f   = ifc_fetch_req_f & !ifc_iccm_access_f & !ifc_region_acc_fault_final_f
+  val fetch_req_iccm_f     = ifc_fetch_req_f &  ifc_iccm_access_f
+  val ic_iccm_hit_f = fetch_req_iccm_f  &  (!miss_pending | (miss_state === hit_u_miss_C) | (miss_state === stream_C))
+  val stream_hit_f = WireInit(Bool(), 0.U)
+  ic_byp_hit_f := (crit_byp_hit_f | stream_hit_f)  & fetch_req_icache_f &  miss_pending
+  val sel_mb_addr_ff = WireInit(Bool(), 0.U)
+  val imb_ff = WireInit(UInt(31.W), 0.U)
+  val ifu_fetch_addr_int_f = WireInit(UInt(31.W), 0.U)
+  val ic_act_hit_f = io.ic_rd_hit.orR & fetch_req_icache_f & !reset_all_tags & (!miss_pending | (miss_state===hit_u_miss_C)) & !sel_mb_addr_ff
+  ic_act_miss_f := (((!io.ic_rd_hit.orR | reset_all_tags) & fetch_req_icache_f & !miss_pending) | scnd_miss_req) & !ifc_region_acc_fault_final_f
+  ic_miss_under_miss_f := (!io.ic_rd_hit | reset_all_tags) & fetch_req_icache_f & (miss_state===hit_u_miss_C) &
+    (imb_ff(30,ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(30,ICACHE_TAG_INDEX_LO-1)) & !uncacheable_miss_ff & !sel_mb_addr_ff & !ifc_region_acc_fault_final_f
+  ic_ignore_2nd_miss_f := (!io.ic_rd_hit.orR | reset_all_tags) & fetch_req_icache_f & (miss_state === hit_u_miss_C) &
+    ((imb_ff(30,ICACHE_TAG_INDEX_LO-1)===ifu_fetch_addr_int_f(30,ICACHE_TAG_INDEX_LO-1))  |   uncacheable_miss_ff)
+  // Output
+  io.ic_hit_f := ic_act_hit_f | ic_byp_hit_f | ic_iccm_hit_f | (ifc_region_acc_fault_final_f & ifc_fetch_req_f)
+  val uncacheable_miss_in = Mux(scnd_miss_req.asBool, uncacheable_miss_scnd_ff, Mux(sel_hold_imb.asBool, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf))
+  val imb_in = Mux(scnd_miss_req.asBool, imb_scnd_ff, Mux(sel_hold_imb.asBool, imb_ff, io.ifc_fetch_addr_bf))
+  val ifu_wr_cumulative_err_data = WireInit(Bool(), 0.U)
+  val scnd_miss_index_match = (imb_ff(ICACHE_INDEX_HI,ICACHE_TAG_INDEX_LO)===imb_scnd_ff(ICACHE_INDEX_HI,ICACHE_TAG_INDEX_LO))& scnd_miss_req & !ifu_wr_cumulative_err_data
+  val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
+  val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
+  val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff,
+      Mux((scnd_miss_req &  scnd_miss_index_match).asBool, way_status_rep_new,
+        Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
+  val replace_way_mb_any = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
+  val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
+  val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any),
+  Mux(miss_pending.asBool, tagv_mb_ff, ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
+  val scnd_miss_req_q = WireInit(Bool(), 0.U)
+  val reset_ic_ff = WireInit(Bool(), 0.U)
+  val reset_ic_in = miss_pending & !scnd_miss_req_q &  (reset_all_tags |  reset_ic_ff)
+  reset_ic_ff := RegNext(reset_ic_in)
+  val fetch_uncacheable_ff = RegNext(io.ifc_fetch_uncacheable_bf, 0.U)
+  ifu_fetch_addr_int_f := RegNext(io.ifc_fetch_addr_bf, 0.U)
+  val vaddr_f = ifu_fetch_addr_int_f
+  uncacheable_miss_ff := RegNext(uncacheable_miss_in, 0.U)
+  imb_ff := RegNext(imb_in)
+  val miss_addr = WireInit(UInt((31-ICACHE_BEAT_ADDR_HI).W), 0.U)
+  val miss_addr_in = Mux(!miss_pending, imb_ff(30, ICACHE_BEAT_ADDR_HI),
+    Mux(scnd_miss_req_q.asBool, imb_scnd_ff(30, ICACHE_BEAT_ADDR_HI), miss_addr))
+  miss_addr := RegNext(miss_addr_in, 0.U)
+  way_status_mb_ff := RegNext(way_status_mb_in, 0.U)
+  tagv_mb_ff := RegNext(tagv_mb_in, 0.U)
+  val stream_miss_f = WireInit(Bool(), 0.U)
+  val ifc_fetch_req_qual_bf  = io.ifc_fetch_req_bf  & !((miss_state===crit_wrd_rdy_C) & flush_final_f) & !stream_miss_f
+  val ifc_fetch_req_f_raw = RegNext(ifc_fetch_req_qual_bf, 0.U)
+  ifc_fetch_req_f := ifc_fetch_req_f_raw & !io.exu_flush_final
+  ifc_iccm_access_f := RegNext(io.ifc_iccm_access_bf, 0.U)
+  val ifc_region_acc_fault_final_bf = WireInit(Bool(), 0.U)
+  ifc_region_acc_fault_final_f := RegNext(ifc_region_acc_fault_final_bf, 0.U)
+  val ifc_region_acc_fault_f = RegNext(io.ifc_region_acc_fault_bf, 0.U)
+  val ifu_ic_req_addr_f = Cat(miss_addr, ic_req_addr_bits_hi_3)
+  val ifu_ic_mb_empty = (((miss_state===hit_u_miss_C) | (miss_state===stream_C)) & !(bus_ifu_wr_en_ff & last_beat)) | !miss_pending
+  val ifu_miss_state_idle = miss_state === idle_C
+  val write_ic_16_bytes = WireInit(Bool(), 0.U)
+  val reset_tag_valid_for_miss = WireInit(Bool(), 0.U)
+  val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss
+  val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr.asBool->Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)),
+                                    !sel_mb_addr.asBool->ifu_fetch_addr_int_f))
+  val ic_rw_addr = ifu_ic_rw_int_addr
+  sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)}
+  val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U)
+  val ic_miss_buff_half = WireInit(UInt(64.W), 0.U)
+  val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff)
+  val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half)
+  val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
+  io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
+  io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata
+  val ic_rd_parity_final_err = WireInit(Bool(), 0.U)
+  io.ic_error_start := ((if(ICACHE_ECC)io.ic_eccerr.orR()else io.ic_parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err
+  val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U)
+  val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U)
+  val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U(7-ICACHE_STATUS_BITS), way_status, 0.U(3.W),ic_debug_tag_val_rd_out)
+  else Cat(0.U(6.W),io.ictag_debug_rd_data(21),0.U(32.W),io.ictag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) ,
+    io.ic_debug_rd_data)
+  io.ifu_ic_debug_rd_data := RegNext(ifu_ic_debug_rd_data_in, 0.U)
+  val ic_wr_parity = (0 until 4).map(i=>rveven_paritygen(ifu_bus_rdata_ff((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
+  val ic_miss_buff_parity = (0 until 4).map(i=>rveven_paritygen(ic_miss_buff_half((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
+
+  ic_wr_16bytes_data := Mux(ifu_bus_rid_ff(0).asBool,Cat(if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff(63,0) ,  if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half(63,0)),
+    Cat(if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half, if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff))
+  val bus_ifu_wr_data_error_ff = WireInit(Bool(), 0.U)
+  val ifu_wr_data_comb_err_ff = WireInit(Bool(), 0.U)
+  val reset_beat_cnt = WireInit(Bool(), 0.U)
+  val ifu_wr_data_comb_err = bus_ifu_wr_data_error_ff
+  val ifu_wr_cumulative_err = (ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff) & !reset_beat_cnt
+  ifu_wr_cumulative_err_data :=  ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff
+  ifu_wr_data_comb_err_ff := withClock(io.free_clk) {RegNext(ifu_wr_cumulative_err, 0.U)}
+  val ic_crit_wd_rdy = WireInit(Bool(), 0.U)
+  val ifu_byp_data_err_new = WireInit(Bool(), 0.U)
+  val sel_byp_data = (ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !ifu_byp_data_err_new
+  val sel_ic_data = !(ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !fetch_req_iccm_f
+  val sel_iccm_data = fetch_req_iccm_f
+
+  val ic_byp_data_only_new = WireInit(UInt(80.W), 0.U)
+  val ic_final_data = Mux1H(Seq((sel_byp_data | (if(ICCM_ICACHE) (sel_iccm_data | sel_ic_data) else if(ICACHE_ONLY) sel_ic_data else 0.U)).asBool->
+    (if(ICCM_ICACHE) io.ic_rd_data else ic_byp_data_only_new(63,0))))
+  val ic_premux_data = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm_rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new)
+  else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
+  val ic_sel_premux_data = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U
+
+  val ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new
+  val ic_data_f = ic_final_data
+  val fetch_req_f_qual = io.ic_hit_f & !io.exu_flush_final
+  val ifc_region_acc_fault_memory_f = WireInit(Bool(), 0.U)
+  io.ic_access_fault_f := (ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f) & !io.exu_flush_final
+  io.ic_access_fault_type_f := Mux(io.iccm_rd_ecc_double_err.asBool, 1.U,
+    Mux(ifc_region_acc_fault_f.asBool, 2.U,
+      Mux(ifc_region_acc_fault_memory_f.asBool(), 3.U, 0.U)))
+  val ifu_bp_inst_mask_f = WireInit(Bool(), 0.U)
+  io.ic_fetch_val_f := Cat(fetch_req_f_qual & ifu_bp_inst_mask_f & !(vaddr_f===Fill(ICACHE_BEAT_ADDR_HI,1.U)) & (err_stop_state=/=err_fetch2_C), fetch_req_f_qual)
+  val two_byte_instr = ic_data_f(1,0) =/= 3.U
+  //// Creating full buffer
 }
 object ifu_mem extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl()))
diff --git a/src/main/scala/lib/el2_lib.scala b/src/main/scala/lib/el2_lib.scala
index 7d0b4e9a..e8daebb5 100644
--- a/src/main/scala/lib/el2_lib.scala
+++ b/src/main/scala/lib/el2_lib.scala
@@ -101,7 +101,7 @@ trait param {
   val ICCM_ICACHE            = true   //.U(1.W)
   val ICCM_INDEX_BITS        = 0xC   //.U(4.W)
   val ICCM_NUM_BANKS         = 0x04  //.U(5.W)
-  val ICCM_ONLY              = 0x0   //.U(1.W)
+  val ICCM_ONLY              = false   //.U(1.W)
   val ICCM_REGION            = 0xE   //.U(4.W)
   val ICCM_SADR              = 0xEE000000L //.U(32.W)
   val ICCM_SIZE              = 0x040 //.U(10.W)
@@ -141,7 +141,7 @@ trait param {
   val LSU_NUM_NBLOAD_WIDTH   = 0x2  //.U(3.W)
   val LSU_SB_BITS            = 0x10 //.U(5.W)
   val LSU_STBUF_DEPTH        = 0x4  //.U(4.W)
-  val NO_ICCM_NO_ICACHE      = 0x0  //.U(1.W)
+  val NO_ICCM_NO_ICACHE      = false  //.U(1.W)
   val PIC_2CYCLE             = 0x0  //.U(1.W)
   val PIC_BASE_ADDR          = 0xF00C0000 //.U(32.W)
   val PIC_BITS               = 0x0F  //.U(5.W)
@@ -160,6 +160,11 @@ trait param {
 trait el2_lib extends param{
   def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
 
+  // IMC
+//  def IMC =
+//    (ICCM_ICACHE, ICCM_ONLY, ICACHE_ONLY, NO_ICCM_NO_ICACHE) match {
+//      case ()
+//    }
 
   // Configuration Methods
   def MEM_CAL : (Int, Int, Int, Int)=
@@ -325,7 +330,7 @@ trait el2_lib extends param{
     var j = 0;var k = 0;var m = 0; var n =0;
     var x = 0;var y = 0;var z = 0
 
-    for(i <- 63 to 0)
+    for(i <- 0 to 63)
     {
       if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
       if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
diff --git a/target/scala-2.12/classes/ifu/EL2_IC_DATA.class b/target/scala-2.12/classes/ifu/EL2_IC_DATA.class
index c9da7937..44041a97 100644
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diff --git a/target/scala-2.12/classes/ifu/EL2_IC_TAG.class b/target/scala-2.12/classes/ifu/EL2_IC_TAG.class
index f5ade755..7e09642d 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class
index e22e1e8d..33fa224d 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
index 367e9ef7..e94592f1 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
index 178c8911..820770e1 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_compress_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_compress_ctl.class
index 00066748..56102bce 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_ic_mem.class b/target/scala-2.12/classes/ifu/el2_ifu_ic_mem.class
index 4b3b05e8..44c1a9d5 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class
index 7788e134..02726ab6 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl.class
index 90e3b122..d26d26c6 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
index eb3b4dd2..d7e64294 100644
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diff --git a/target/scala-2.12/classes/ifu/ifu_aln$.class b/target/scala-2.12/classes/ifu/ifu_aln$.class
index 10da7d7e..56c54ba4 100644
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diff --git a/target/scala-2.12/classes/ifu/ifu_aln$delayedInit$body.class b/target/scala-2.12/classes/ifu/ifu_aln$delayedInit$body.class
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diff --git a/target/scala-2.12/classes/ifu/ifu_mem$.class b/target/scala-2.12/classes/ifu/ifu_mem$.class
index 7d7051a7..365f2e37 100644
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diff --git a/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class b/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class
index 1a6e9c16..47b7f4bf 100644
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diff --git a/target/scala-2.12/classes/ifu/test.sc b/target/scala-2.12/classes/ifu/test.sc
deleted file mode 100644
index f6633a75..00000000
--- a/target/scala-2.12/classes/ifu/test.sc
+++ /dev/null
@@ -1 +0,0 @@
-val a = 5
\ No newline at end of file
diff --git a/target/scala-2.12/classes/lib/el2_lib$TEC_RV_ICG$$anon$1.class b/target/scala-2.12/classes/lib/el2_lib$TEC_RV_ICG$$anon$1.class
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