BP updated
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ifu_bp_ctl.fir
45370
ifu_bp_ctl.fir
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Load Diff
27242
ifu_bp_ctl.v
27242
ifu_bp_ctl.v
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Load Diff
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@ -4,13 +4,13 @@ import chisel3.util._
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trait param {
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trait param {
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val BHT_ADDR_HI = 0x9
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val BHT_ADDR_HI = 0x9
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val BHT_ADDR_LO = 0x2
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val BHT_ADDR_LO = 0x2
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val BHT_ARRAY_DEPTH = 0x010
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val BHT_ARRAY_DEPTH = 0x100
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val BHT_GHR_HASH_1 = 0x0
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val BHT_GHR_HASH_1 = 0x0
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val BHT_GHR_SIZE = 0x8
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val BHT_GHR_SIZE = 0x8
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val BHT_SIZE = 0x010
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val BHT_SIZE = 0x200
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val BTB_ADDR_HI = 0x09
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val BTB_ADDR_HI = 0x09
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val BTB_ADDR_LO = 0x2
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val BTB_ADDR_LO = 0x2
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val BTB_ARRAY_DEPTH = 0x010
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val BTB_ARRAY_DEPTH = 0x100
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val BTB_BTAG_FOLD = 0x0
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val BTB_BTAG_FOLD = 0x0
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val BTB_BTAG_SIZE = 0x5
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val BTB_BTAG_SIZE = 0x5
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val BTB_FOLD2_INDEX_HASH = 0x0
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val BTB_FOLD2_INDEX_HASH = 0x0
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@ -20,7 +20,7 @@ trait param {
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val BTB_INDEX2_LO = 0x0A
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val BTB_INDEX2_LO = 0x0A
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val BTB_INDEX3_HI = 0x19
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val BTB_INDEX3_HI = 0x19
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val BTB_INDEX3_LO = 0x12
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val BTB_INDEX3_LO = 0x12
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val BTB_SIZE = 0x010
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val BTB_SIZE = 0x200
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val BUILD_AHB_LITE = 0x0
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val BUILD_AHB_LITE = 0x0
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val BUILD_AXI4 = 0x1
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val BUILD_AXI4 = 0x1
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val BUILD_AXI_NATIVE = 0x1
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val BUILD_AXI_NATIVE = 0x1
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