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QUASAR 2.0 Final

This commit is contained in:
Laraib Khan 2021-04-12 09:40:17 +05:00
parent 0255c7fa9d
commit 21cd2024bb
2 changed files with 2 additions and 3 deletions
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1
design/src/main/scala/ifu/ifu_bp_ctl.scala
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@ -114,7 +114,6 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset {
// Hash the second pc // Hash the second pc
val btb_rd_addr_p1_f = btb_addr_hash(Cat(fetch_addr_p1_f,0.U)) val btb_rd_addr_p1_f = btb_addr_hash(Cat(fetch_addr_p1_f,0.U))
// TODO
val btb_sel_f = Cat(~bht_dir_f(0),bht_dir_f(0)) val btb_sel_f = Cat(~bht_dir_f(0),bht_dir_f(0))
// Checking of the pc is a multiple of 4, if it is fetch-start will be "01" // Checking of the pc is a multiple of 4, if it is fetch-start will be "01"

4
design/src/main/scala/lsu/lsu_bus_intf.scala
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@ -112,10 +112,10 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk
bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
//
bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m
bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r
//
bus_buffer.io.lsu_addr_m := io.lsu_addr_m bus_buffer.io.lsu_addr_m := io.lsu_addr_m
bus_buffer.io.end_addr_m := io.end_addr_m bus_buffer.io.end_addr_m := io.end_addr_m