diff --git a/el2_dec.anno.json b/el2_dec.anno.json index 4a203e13..2a9a9123 100644 --- a/el2_dec.anno.json +++ b/el2_dec.anno.json @@ -1,23 +1,4 @@ [ - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_en_d", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_path_r", @@ -46,7 +27,53 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_lsu_p_bits_half", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_hist", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_hist_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_predict_t", + "sources":[ + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_immed_d", + "sources":[ + "~el2_dec|el2_dec>io_core_id", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_csr_ren_d", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", @@ -55,12 +82,12 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { @@ -74,10 +101,47 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_predict_nt", + "sink":"~el2_dec|el2_dec>io_dec_lsu_offset_d", "sources":[ - "~el2_dec|el2_dec>io_i0_brp_bits_hist", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_br_immed_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_pc4", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_mul_p_bits_rs1_sign", + "sources":[ "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", "~el2_dec|el2_dec>io_ifu_i0_instr", @@ -85,17 +149,12 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_way", - "sources":[ - "~el2_dec|el2_dec>io_exu_i0_br_way_r" + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { @@ -109,147 +168,6 @@ "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_pred_correct_npc_x", - "sources":[ - "~el2_dec|el2_dec>io_exu_i0_pc_x" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_unsign", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_lxor", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_way", - "sources":[ - "~el2_dec|el2_dec>io_i0_brp_bits_way" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_data_d", - "sources":[ - "~el2_dec|el2_dec>io_lsu_nonblock_load_data", - "~el2_dec|el2_dec>io_lsu_result_m", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_lower_r", - "sources":[ - "~el2_dec|el2_dec>io_mpc_reset_run_req", - "~el2_dec|el2_dec>io_lsu_fastint_stall_any", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_lsu_fir_error", - "~el2_dec|el2_dec>io_mhwakeup", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", - "~el2_dec|el2_dec>io_dbg_halt_req", - "~el2_dec|el2_dec>io_ifu_miss_state_idle", - "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_lsu_result_corr_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_sra", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_div_cancel", - "sources":[ - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_mpc_reset_run_req", - "~el2_dec|el2_dec>io_lsu_fastint_stall_any", - "~el2_dec|el2_dec>io_lsu_fir_error", - "~el2_dec|el2_dec>io_mhwakeup", - "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", - "~el2_dec|el2_dec>io_dbg_halt_req", - "~el2_dec|el2_dec>io_ifu_miss_state_idle", - "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_lsu_result_corr_r" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_bypass_data_d", @@ -270,17 +188,76 @@ "~el2_dec|el2_dec>io_exu_i0_br_error_r", "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_div_p_valid", + "sink":"~el2_dec|el2_dec>io_div_p_bits_rem", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_hist", + "sources":[ + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_pred_correct_npc_x", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_pc_x" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_slt", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_br_start_error", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_mul_p_valid", "sources":[ "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", "~el2_dec|el2_dec>io_dbg_cmd_wrdata", @@ -309,18 +286,25 @@ "~el2_dec|el2_dec>io_ifu_i0_instr", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", "~el2_dec|el2_dec>io_lsu_result_corr_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pja", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_prett", + "sources":[ + "~el2_dec|el2_dec>io_i0_brp_prett" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_sub", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", @@ -329,12 +313,451 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_bits_load_ldst_bypass_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_lsu_p_bits_by", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_lower_r", + "sources":[ + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_div_cancel", + "sources":[ + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_en_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_noredir_r", + "sources":[ + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_i0_commit_cmt", + "sources":[ + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_mul_p_bits_low", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_select_pc_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_dbg_rddata", + "sources":[ + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_bypass_en_d", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_csr_write", + "sources":[ + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_lor", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_bge", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_br_error", + "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_pc_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_pc" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_lsu_valid_raw_d", + "sources":[ + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_leak_one_r", + "sources":[ + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_err_r", + "sources":[ + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_en_d", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_data_en", + "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", + "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" ] }, { @@ -371,147 +794,20 @@ "~el2_dec|el2_dec>io_ifu_i0_instr", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", "~el2_dec|el2_dec>io_lsu_result_corr_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_noredir_r", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_middle", "sources":[ - "~el2_dec|el2_dec>io_lsu_fastint_stall_any", - "~el2_dec|el2_dec>io_mpc_reset_run_req", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_lsu_fir_error", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_dbg_halt_req", - "~el2_dec|el2_dec>io_mhwakeup", - "~el2_dec|el2_dec>io_ifu_miss_state_idle", - "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", - "~el2_dec|el2_dec>io_lsu_result_corr_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pcall", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_lor", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_lsu_p_bits_word", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_i0_commit_cmt", - "sources":[ - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_add", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_dbg_rddata", - "sources":[ - "~el2_dec|el2_dec>io_lsu_result_corr_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_jal", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_exu_i0_br_middle_r" ] }, { @@ -525,17 +821,64 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_div_p_bits_unsign", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_way", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_way_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_div_p_valid", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_land", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", @@ -544,12 +887,12 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { @@ -563,155 +906,29 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_immed_d", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_valid", "sources":[ - "~el2_dec|el2_dec>io_core_id", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_exu_i0_br_valid_r", + "~el2_dec|el2_dec>io_exu_i0_br_mp_r", + "~el2_dec|el2_dec>io_exu_pmu_i0_br_ataken" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_br_start_error", - "sources":[ - "~el2_dec|el2_dec>io_lsu_load_stall_any", - "~el2_dec|el2_dec>io_dma_dccm_stall_any", - "~el2_dec|el2_dec>io_lsu_store_stall_any", - "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", - "~el2_dec|el2_dec>io_dbg_cmd_wrdata", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_ifu_i0_valid", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_mpc_reset_run_req", - "~el2_dec|el2_dec>io_lsu_fastint_stall_any", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_lsu_fir_error", - "~el2_dec|el2_dec>io_mhwakeup", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", - "~el2_dec|el2_dec>io_dbg_halt_req", - "~el2_dec|el2_dec>io_ifu_miss_state_idle", - "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", - "~el2_dec|el2_dec>io_lsu_result_corr_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_br_immed_d", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_pc4", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_pc_d", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_pc" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_hist", - "sources":[ - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_lsu_p_bits_load", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_leak_one_r", - "sources":[ - "~el2_dec|el2_dec>io_mpc_reset_run_req", - "~el2_dec|el2_dec>io_lsu_fastint_stall_any", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_lsu_fir_error", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_mhwakeup", - "~el2_dec|el2_dec>io_dbg_halt_req", - "~el2_dec|el2_dec>io_ifu_miss_state_idle", - "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", - "~el2_dec|el2_dec>io_lsu_result_corr_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_en_d", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_data_d", "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_data", + "~el2_dec|el2_dec>io_lsu_result_m", "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", "~el2_dec|el2_dec>io_ifu_i0_instr", @@ -726,33 +943,88 @@ "~el2_dec|el2_dec>io_exu_i0_br_error_r", "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_err_r", + "sink":"~el2_dec|el2_dec>io_i0_ap_blt", "sources":[ - "~el2_dec|el2_dec>io_mpc_reset_run_req", - "~el2_dec|el2_dec>io_lsu_fastint_stall_any", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_lsu_fir_error", - "~el2_dec|el2_dec>io_mhwakeup", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", - "~el2_dec|el2_dec>io_dbg_halt_req", - "~el2_dec|el2_dec>io_ifu_miss_state_idle", - "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_lsu_result_corr_r" + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pja", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_add", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_lxor", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { @@ -766,38 +1038,12 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_bypass_en_d", - "sources":[ - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { @@ -811,17 +1057,17 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_lsu_offset_d", + "sink":"~el2_dec|el2_dec>io_i0_ap_jal", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_instr", "~el2_dec|el2_dec>io_dbg_cmd_valid", @@ -830,152 +1076,49 @@ "~el2_dec|el2_dec>io_dbg_cmd_write", "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_alu_decode_d", + "sink":"~el2_dec|el2_dec>io_lsu_p_bits_word", "sources":[ - "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", - "~el2_dec|el2_dec>io_dbg_cmd_wrdata", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", - "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", "~el2_dec|el2_dec>io_dbg_cmd_valid", "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_mpc_reset_run_req", - "~el2_dec|el2_dec>io_lsu_fastint_stall_any", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_fence_i_r", + "sources":[ "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", "~el2_dec|el2_dec>io_exu_i0_br_error_r", "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_lsu_fir_error", - "~el2_dec|el2_dec>io_mhwakeup", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", - "~el2_dec|el2_dec>io_dbg_halt_req", - "~el2_dec|el2_dec>io_ifu_miss_state_idle", - "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", - "~el2_dec|el2_dec>io_lsu_result_corr_r" + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_lsu_p_bits_unsign", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_way", "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_csr_write", - "sources":[ - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_ctl_en", - "sources":[ - "~el2_dec|el2_dec>io_lsu_load_stall_any", - "~el2_dec|el2_dec>io_dma_dccm_stall_any", - "~el2_dec|el2_dec>io_lsu_store_stall_any", - "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", - "~el2_dec|el2_dec>io_dbg_cmd_wrdata", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", - "~el2_dec|el2_dec>io_ifu_i0_valid", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_mpc_reset_run_req", - "~el2_dec|el2_dec>io_lsu_fastint_stall_any", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_lsu_fir_error", - "~el2_dec|el2_dec>io_mhwakeup", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", - "~el2_dec|el2_dec>io_dbg_halt_req", - "~el2_dec|el2_dec>io_ifu_miss_state_idle", - "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", - "~el2_dec|el2_dec>io_lsu_result_corr_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_select_pc_d", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_way" ] }, { @@ -1012,93 +1155,27 @@ "~el2_dec|el2_dec>io_dbg_halt_req", "~el2_dec|el2_dec>io_ifu_miss_state_idle", "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", "~el2_dec|el2_dec>io_lsu_result_corr_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_valid", + "sink":"~el2_dec|el2_dec>io_i0_predict_index_d", "sources":[ - "~el2_dec|el2_dec>io_exu_i0_br_valid_r", - "~el2_dec|el2_dec>io_exu_i0_br_mp_r", - "~el2_dec|el2_dec>io_exu_pmu_i0_br_ataken" + "~el2_dec|el2_dec>io_ifu_i0_bp_index" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_lsu_p_bits_load_ldst_bypass_d", + "sink":"~el2_dec|el2_dec>io_i0_predict_btag_d", "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_csr_ren_d", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "sources":[ - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_bge", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_br_error", - "sources":[ - "~el2_dec|el2_dec>io_exu_i0_br_error_r" + "~el2_dec|el2_dec>io_ifu_i0_bp_btag" ] }, { @@ -1112,17 +1189,17 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_srl", + "sink":"~el2_dec|el2_dec>io_i0_ap_unsign", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", @@ -1131,47 +1208,105 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_fence_i_r", + "sink":"~el2_dec|el2_dec>io_lsu_p_bits_load", "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_br_error", + "sources":[ + "~el2_dec|el2_dec>io_exu_i0_br_error_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_toffset", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_alu_decode_d", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", + "~el2_dec|el2_dec>io_dbg_cmd_wrdata", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_valid", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_mpc_reset_run_req", + "~el2_dec|el2_dec>io_lsu_fastint_stall_any", "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", "~el2_dec|el2_dec>io_exu_i0_br_error_r", "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid" + "~el2_dec|el2_dec>io_lsu_fir_error", + "~el2_dec|el2_dec>io_mhwakeup", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", + "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", + "~el2_dec|el2_dec>io_dbg_halt_req", + "~el2_dec|el2_dec>io_ifu_miss_state_idle", + "~el2_dec|el2_dec>io_lsu_idle_any", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_lsu_result_corr_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_en_d", + "sink":"~el2_dec|el2_dec>io_gpr_i0_rs2_d", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_instr", "~el2_dec|el2_dec>io_dbg_cmd_valid", "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_dbg_cmd_write" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_sub", + "sink":"~el2_dec|el2_dec>io_lsu_p_bits_store", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", @@ -1180,38 +1315,12 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_slt", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_predict_index_d", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_bp_index" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { @@ -1249,68 +1358,27 @@ "~el2_dec|el2_dec>io_ifu_i0_instr", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", "~el2_dec|el2_dec>io_lsu_result_corr_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_lsu_valid_raw_d", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_br_start_error", "sources":[ + "~el2_dec|el2_dec>io_lsu_load_stall_any", "~el2_dec|el2_dec>io_dma_dccm_stall_any", + "~el2_dec|el2_dec>io_lsu_store_stall_any", "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", "~el2_dec|el2_dec>io_dbg_cmd_wrdata", "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", - "~el2_dec|el2_dec>io_ifu_i0_valid", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_lsu_p_bits_by", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_mul_p_valid", - "sources":[ - "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", - "~el2_dec|el2_dec>io_dbg_cmd_wrdata", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", "~el2_dec|el2_dec>io_ifu_i0_valid", "~el2_dec|el2_dec>io_dbg_cmd_valid", "~el2_dec|el2_dec>io_dbg_cmd_type", @@ -1333,18 +1401,17 @@ "~el2_dec|el2_dec>io_ifu_i0_instr", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", "~el2_dec|el2_dec>io_lsu_result_corr_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_div_p_bits_rem", + "sink":"~el2_dec|el2_dec>io_lsu_p_bits_unsign", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", @@ -1353,143 +1420,12 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_predict_btag_d", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_bp_btag" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_predict_t", - "sources":[ - "~el2_dec|el2_dec>io_i0_brp_bits_hist", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_prett", - "sources":[ - "~el2_dec|el2_dec>io_i0_brp_bits_prett" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_lsu_p_bits_store", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_toffset", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_gpr_i0_rs2_d", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_blt", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_i0_ap_land", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_mul_p_bits_rs2_sign", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { @@ -1501,45 +1437,40 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_br_error", + "sink":"~el2_dec|el2_dec>io_div_p_bits_unsign", "sources":[ - "~el2_dec|el2_dec>io_lsu_load_stall_any", - "~el2_dec|el2_dec>io_dma_dccm_stall_any", - "~el2_dec|el2_dec>io_lsu_store_stall_any", - "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m", - "~el2_dec|el2_dec>io_dbg_cmd_wrdata", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error", - "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", - "~el2_dec|el2_dec>io_ifu_i0_valid", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_mpc_reset_run_req", - "~el2_dec|el2_dec>io_lsu_fastint_stall_any", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", - "~el2_dec|el2_dec>io_exu_i0_br_error_r", - "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", - "~el2_dec|el2_dec>io_lsu_fir_error", - "~el2_dec|el2_dec>io_mhwakeup", - "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", - "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any", - "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any", - "~el2_dec|el2_dec>io_dbg_halt_req", - "~el2_dec|el2_dec>io_ifu_miss_state_idle", - "~el2_dec|el2_dec>io_lsu_idle_any", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_lsu_result_corr_r" + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pret", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { @@ -1553,6 +1484,25 @@ "~el2_dec|el2_dec>io_dbg_cmd_write" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_i0_ap_predict_nt", + "sources":[ + "~el2_dec|el2_dec>io_i0_brp_hist", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_toffset" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_dec|el2_dec>io_dec_dbg_cmd_fail", @@ -1566,14 +1516,45 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_hist", + "sink":"~el2_dec|el2_dec>io_lsu_p_bits_half", "sources":[ - "~el2_dec|el2_dec>io_exu_i0_br_hist_r" + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_data_en", + "sink":"~el2_dec|el2_dec>io_i0_ap_srl", + "sources":[ + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_dec_ctl_en", "sources":[ "~el2_dec|el2_dec>io_lsu_load_stall_any", "~el2_dec|el2_dec>io_dma_dccm_stall_any", @@ -1605,34 +1586,15 @@ "~el2_dec|el2_dec>io_ifu_i0_instr", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist", "~el2_dec|el2_dec>io_lsu_result_corr_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_mul_p_bits_low", - "sources":[ - "~el2_dec|el2_dec>io_ifu_i0_icaf", - "~el2_dec|el2_dec>io_ifu_i0_dbecc", - "~el2_dec|el2_dec>io_ifu_i0_instr", - "~el2_dec|el2_dec>io_dbg_cmd_valid", - "~el2_dec|el2_dec>io_dbg_cmd_type", - "~el2_dec|el2_dec>io_dbg_cmd_addr", - "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", - "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pc4", @@ -1642,7 +1604,7 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_mul_p_bits_rs1_sign", + "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pcall", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", @@ -1651,17 +1613,43 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pret", + "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_en_d", + "sources":[ + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid", + "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error", + "~el2_dec|el2_dec>io_exu_i0_br_error_r", + "~el2_dec|el2_dec>io_exu_i0_br_start_error_r", + "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec|el2_dec>io_mul_p_bits_rs2_sign", "sources":[ "~el2_dec|el2_dec>io_ifu_i0_icaf", "~el2_dec|el2_dec>io_ifu_i0_dbecc", @@ -1670,19 +1658,31 @@ "~el2_dec|el2_dec>io_dbg_cmd_type", "~el2_dec|el2_dec>io_dbg_cmd_addr", "~el2_dec|el2_dec>io_dbg_cmd_write", - "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error", - "~el2_dec|el2_dec>io_i0_brp_bits_br_error", - "~el2_dec|el2_dec>io_i0_brp_bits_ret", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", "~el2_dec|el2_dec>io_i0_brp_valid", - "~el2_dec|el2_dec>io_i0_brp_bits_toffset", - "~el2_dec|el2_dec>io_i0_brp_bits_hist" + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_middle", + "sink":"~el2_dec|el2_dec>io_i0_ap_sra", "sources":[ - "~el2_dec|el2_dec>io_exu_i0_br_middle_r" + "~el2_dec|el2_dec>io_ifu_i0_icaf", + "~el2_dec|el2_dec>io_ifu_i0_dbecc", + "~el2_dec|el2_dec>io_ifu_i0_instr", + "~el2_dec|el2_dec>io_dbg_cmd_valid", + "~el2_dec|el2_dec>io_dbg_cmd_type", + "~el2_dec|el2_dec>io_dbg_cmd_addr", + "~el2_dec|el2_dec>io_dbg_cmd_write", + "~el2_dec|el2_dec>io_i0_brp_br_start_error", + "~el2_dec|el2_dec>io_i0_brp_br_error", + "~el2_dec|el2_dec>io_i0_brp_ret", + "~el2_dec|el2_dec>io_i0_brp_valid", + "~el2_dec|el2_dec>io_i0_brp_toffset", + "~el2_dec|el2_dec>io_i0_brp_hist" ] }, { diff --git a/el2_dec.fir b/el2_dec.fir index 9a41335d..c15f6299 100644 --- a/el2_dec.fir +++ b/el2_dec.fir @@ -3,52 +3,52 @@ circuit el2_dec : module el2_dec_ib_ctl : input clock : Clock input reset : Reset - output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} + output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} - io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 43:31] - io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 44:31] - io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 45:31] - io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 46:31] - io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 47:31] - io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 48:31] - io.dec_i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 50:31] - io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 51:31] - io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 52:31] - node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 66:60] - node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 66:41] - node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 67:38] - node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 67:36] - node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 68:36] - node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 70:55] - node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 70:37] - node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 71:55] - node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 71:37] - node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 72:55] - node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 72:37] - node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 73:55] - node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 73:37] - node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 75:40] - node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 76:40] - node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 79:20] + io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 8:31] + io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 9:31] + io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 10:31] + io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 11:31] + io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 12:31] + io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 13:31] + io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 15:31] + io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 16:31] + io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 17:31] + node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 31:60] + node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 31:41] + node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 32:38] + node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 32:36] + node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 33:36] + node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 35:55] + node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 35:37] + node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 36:55] + node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 36:37] + node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 37:55] + node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 37:37] + node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 38:55] + node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 38:37] + node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 40:40] + node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 41:40] + node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 44:20] node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58] node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58] - node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 80:21] - node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58] - node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58] - node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 81:20] - node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58] - node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 82:21] - node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58] + node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 45:21] + node _T_11 = cat(UInt<3>("h06"), dreg) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, UInt<6>("h033")) @[Cat.scala 29:58] + node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 46:20] + node _T_14 = cat(dcsr, UInt<14>("h02073")) @[Cat.scala 29:58] + node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 47:21] + node _T_16 = cat(dcsr, UInt<13>("h01073")) @[Cat.scala 29:58] node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72] node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] @@ -58,16 +58,16 @@ circuit el2_dec : node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] wire ib0_debug_in : UInt<32> @[Mux.scala 27:72] ib0_debug_in <= _T_23 @[Mux.scala 27:72] - node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 86:47] - io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 86:28] - node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 89:51] - node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 89:43] - io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 89:24] - node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 91:41] - io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 91:22] - node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 92:41] - node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 92:28] - io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 92:22] + node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 51:47] + io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 51:28] + node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 54:51] + node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 54:43] + io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 54:24] + node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 56:41] + io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 56:22] + node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 57:41] + node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 57:28] + io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 57:22] extmodule gated_latch : output Q : Clock @@ -98,2039 +98,2024 @@ circuit el2_dec : input reset : Reset output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} - node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 72:23] - node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 72:35] - node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 72:27] - node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 72:49] - node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:42] - node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:60] - node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 72:53] - node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 72:39] - node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 72:75] - node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:68] - node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:85] - node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 72:78] - node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 72:65] - io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 72:14] - node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 73:51] - node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 73:51] - node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 73:90] - node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 73:90] - node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 73:55] - node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 74:37] - node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 74:37] - node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 73:94] - node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 74:76] - node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 74:76] - node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 74:41] - node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_46 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_47 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_49 = and(_T_45, _T_46) @[el2_dec_dec_ctl.scala 75:38] - node _T_50 = and(_T_49, _T_48) @[el2_dec_dec_ctl.scala 75:38] - node _T_51 = or(_T_43, _T_50) @[el2_dec_dec_ctl.scala 74:80] - node _T_52 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_54 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_55 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_57 = and(_T_53, _T_54) @[el2_dec_dec_ctl.scala 75:76] - node _T_58 = and(_T_57, _T_56) @[el2_dec_dec_ctl.scala 75:76] - node _T_59 = or(_T_51, _T_58) @[el2_dec_dec_ctl.scala 75:42] - node _T_60 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_61 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_62 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_64 = and(_T_60, _T_61) @[el2_dec_dec_ctl.scala 76:37] - node _T_65 = and(_T_64, _T_63) @[el2_dec_dec_ctl.scala 76:37] - node _T_66 = or(_T_59, _T_65) @[el2_dec_dec_ctl.scala 75:80] - node _T_67 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_68 = eq(_T_67, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_69 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_70 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_71 = eq(_T_70, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_72 = and(_T_68, _T_69) @[el2_dec_dec_ctl.scala 76:75] - node _T_73 = and(_T_72, _T_71) @[el2_dec_dec_ctl.scala 76:75] - node _T_74 = or(_T_66, _T_73) @[el2_dec_dec_ctl.scala 76:41] - node _T_75 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_76 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_77 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_79 = and(_T_75, _T_76) @[el2_dec_dec_ctl.scala 77:37] - node _T_80 = and(_T_79, _T_78) @[el2_dec_dec_ctl.scala 77:37] - node _T_81 = or(_T_74, _T_80) @[el2_dec_dec_ctl.scala 76:79] - node _T_82 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_84 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_85 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_87 = and(_T_83, _T_84) @[el2_dec_dec_ctl.scala 77:75] - node _T_88 = and(_T_87, _T_86) @[el2_dec_dec_ctl.scala 77:75] - node _T_89 = or(_T_81, _T_88) @[el2_dec_dec_ctl.scala 77:41] - node _T_90 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_91 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_92 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_94 = and(_T_90, _T_91) @[el2_dec_dec_ctl.scala 78:37] - node _T_95 = and(_T_94, _T_93) @[el2_dec_dec_ctl.scala 78:37] - node _T_96 = or(_T_89, _T_95) @[el2_dec_dec_ctl.scala 77:79] - node _T_97 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_99 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_101 = and(_T_98, _T_100) @[el2_dec_dec_ctl.scala 78:71] - node _T_102 = or(_T_96, _T_101) @[el2_dec_dec_ctl.scala 78:41] - node _T_103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_104 = eq(_T_103, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_105 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_106 = eq(_T_105, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_107 = and(_T_104, _T_106) @[el2_dec_dec_ctl.scala 78:106] - node _T_108 = or(_T_102, _T_107) @[el2_dec_dec_ctl.scala 78:75] - io.out.rs1 <= _T_108 @[el2_dec_dec_ctl.scala 73:14] - node _T_109 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_112 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_114 = and(_T_109, _T_111) @[el2_dec_dec_ctl.scala 79:48] - node _T_115 = and(_T_114, _T_113) @[el2_dec_dec_ctl.scala 79:48] - node _T_116 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_118 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_119 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_121 = and(_T_117, _T_118) @[el2_dec_dec_ctl.scala 79:85] - node _T_122 = and(_T_121, _T_120) @[el2_dec_dec_ctl.scala 79:85] - node _T_123 = or(_T_115, _T_122) @[el2_dec_dec_ctl.scala 79:52] - io.out.rs2 <= _T_123 @[el2_dec_dec_ctl.scala 79:14] - node _T_124 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_126 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_127 = eq(_T_126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_128 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_129 = and(_T_125, _T_127) @[el2_dec_dec_ctl.scala 80:50] - node _T_130 = and(_T_129, _T_128) @[el2_dec_dec_ctl.scala 80:50] - node _T_131 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_132 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_134 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_135 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_137 = and(_T_131, _T_133) @[el2_dec_dec_ctl.scala 80:90] - node _T_138 = and(_T_137, _T_134) @[el2_dec_dec_ctl.scala 80:90] - node _T_139 = and(_T_138, _T_136) @[el2_dec_dec_ctl.scala 80:90] - node _T_140 = or(_T_130, _T_139) @[el2_dec_dec_ctl.scala 80:54] - node _T_141 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_142 = eq(_T_141, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_143 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_144 = eq(_T_143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_145 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_146 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_147 = and(_T_142, _T_144) @[el2_dec_dec_ctl.scala 81:40] - node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 81:40] - node _T_149 = and(_T_148, _T_146) @[el2_dec_dec_ctl.scala 81:40] - node _T_150 = or(_T_140, _T_149) @[el2_dec_dec_ctl.scala 80:94] - node _T_151 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_153 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_155 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_156 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_157 = eq(_T_156, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_158 = and(_T_152, _T_154) @[el2_dec_dec_ctl.scala 81:81] - node _T_159 = and(_T_158, _T_155) @[el2_dec_dec_ctl.scala 81:81] - node _T_160 = and(_T_159, _T_157) @[el2_dec_dec_ctl.scala 81:81] - node _T_161 = or(_T_150, _T_160) @[el2_dec_dec_ctl.scala 81:44] - io.out.imm12 <= _T_161 @[el2_dec_dec_ctl.scala 80:16] - node _T_162 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:24] - node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:17] - node _T_164 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:37] - node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:30] - node _T_166 = and(_T_163, _T_165) @[el2_dec_dec_ctl.scala 82:28] - node _T_167 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:51] - node _T_168 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:63] - node _T_169 = and(_T_167, _T_168) @[el2_dec_dec_ctl.scala 82:55] - node _T_170 = or(_T_166, _T_169) @[el2_dec_dec_ctl.scala 82:42] - node _T_171 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 82:76] - node _T_172 = or(_T_170, _T_171) @[el2_dec_dec_ctl.scala 82:68] - io.out.rd <= _T_172 @[el2_dec_dec_ctl.scala 82:13] - node _T_173 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_175 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_176 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_178 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_179 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_181 = and(_T_174, _T_175) @[el2_dec_dec_ctl.scala 83:58] - node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 83:58] - node _T_183 = and(_T_182, _T_178) @[el2_dec_dec_ctl.scala 83:58] - node _T_184 = and(_T_183, _T_180) @[el2_dec_dec_ctl.scala 83:58] - io.out.shimm5 <= _T_184 @[el2_dec_dec_ctl.scala 83:17] - node _T_185 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 84:26] - node _T_186 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 84:36] - node _T_187 = and(_T_185, _T_186) @[el2_dec_dec_ctl.scala 84:29] - node _T_188 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 84:50] - node _T_189 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 84:60] - node _T_190 = and(_T_188, _T_189) @[el2_dec_dec_ctl.scala 84:53] - node _T_191 = or(_T_187, _T_190) @[el2_dec_dec_ctl.scala 84:41] - io.out.imm20 <= _T_191 @[el2_dec_dec_ctl.scala 84:16] - node _T_192 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:24] - node _T_193 = eq(_T_192, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:17] - node _T_194 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:37] - node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:30] - node _T_196 = and(_T_193, _T_195) @[el2_dec_dec_ctl.scala 85:28] - node _T_197 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 85:49] - node _T_198 = and(_T_196, _T_197) @[el2_dec_dec_ctl.scala 85:41] - node _T_199 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:63] - node _T_200 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:75] - node _T_201 = and(_T_199, _T_200) @[el2_dec_dec_ctl.scala 85:67] - node _T_202 = or(_T_198, _T_201) @[el2_dec_dec_ctl.scala 85:54] - io.out.pc <= _T_202 @[el2_dec_dec_ctl.scala 85:13] - node _T_203 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_204 = eq(_T_203, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_205 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_207 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_209 = and(_T_204, _T_206) @[el2_dec_dec_ctl.scala 86:50] - node _T_210 = and(_T_209, _T_208) @[el2_dec_dec_ctl.scala 86:50] - io.out.load <= _T_210 @[el2_dec_dec_ctl.scala 86:15] - node _T_211 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_213 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_216 = and(_T_212, _T_213) @[el2_dec_dec_ctl.scala 87:50] - node _T_217 = and(_T_216, _T_215) @[el2_dec_dec_ctl.scala 87:50] - io.out.store <= _T_217 @[el2_dec_dec_ctl.scala 87:16] - node _T_218 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_219 = eq(_T_218, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_220 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_221 = eq(_T_220, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_222 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_223 = eq(_T_222, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_224 = and(_T_219, _T_221) @[el2_dec_dec_ctl.scala 88:49] - node _T_225 = and(_T_224, _T_223) @[el2_dec_dec_ctl.scala 88:49] - io.out.lsu <= _T_225 @[el2_dec_dec_ctl.scala 88:14] - node _T_226 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_228 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_230 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_232 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_234 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_235 = and(_T_227, _T_229) @[el2_dec_dec_ctl.scala 89:57] - node _T_236 = and(_T_235, _T_231) @[el2_dec_dec_ctl.scala 89:57] - node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 89:57] - node _T_238 = and(_T_237, _T_234) @[el2_dec_dec_ctl.scala 89:57] - node _T_239 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_241 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_243 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_244 = and(_T_240, _T_242) @[el2_dec_dec_ctl.scala 89:94] - node _T_245 = and(_T_244, _T_243) @[el2_dec_dec_ctl.scala 89:94] - node _T_246 = or(_T_238, _T_245) @[el2_dec_dec_ctl.scala 89:61] - node _T_247 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_249 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_250 = eq(_T_249, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_251 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_253 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_254 = eq(_T_253, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_255 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_257 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_259 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_260 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_261 = eq(_T_260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_262 = and(_T_248, _T_250) @[el2_dec_dec_ctl.scala 90:56] - node _T_263 = and(_T_262, _T_252) @[el2_dec_dec_ctl.scala 90:56] - node _T_264 = and(_T_263, _T_254) @[el2_dec_dec_ctl.scala 90:56] - node _T_265 = and(_T_264, _T_256) @[el2_dec_dec_ctl.scala 90:56] - node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 90:56] - node _T_267 = and(_T_266, _T_259) @[el2_dec_dec_ctl.scala 90:56] - node _T_268 = and(_T_267, _T_261) @[el2_dec_dec_ctl.scala 90:56] - node _T_269 = or(_T_246, _T_268) @[el2_dec_dec_ctl.scala 89:98] - io.out.add <= _T_269 @[el2_dec_dec_ctl.scala 89:14] - node _T_270 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] - node _T_271 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_272 = eq(_T_271, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_273 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_274 = eq(_T_273, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_275 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_276 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_279 = and(_T_270, _T_272) @[el2_dec_dec_ctl.scala 91:57] - node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 91:57] - node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 91:57] - node _T_282 = and(_T_281, _T_276) @[el2_dec_dec_ctl.scala 91:57] - node _T_283 = and(_T_282, _T_278) @[el2_dec_dec_ctl.scala 91:57] - node _T_284 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_286 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_288 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_289 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_290 = eq(_T_289, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_291 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_292 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_294 = and(_T_285, _T_287) @[el2_dec_dec_ctl.scala 91:105] - node _T_295 = and(_T_294, _T_288) @[el2_dec_dec_ctl.scala 91:105] - node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 91:105] - node _T_297 = and(_T_296, _T_291) @[el2_dec_dec_ctl.scala 91:105] - node _T_298 = and(_T_297, _T_293) @[el2_dec_dec_ctl.scala 91:105] - node _T_299 = or(_T_283, _T_298) @[el2_dec_dec_ctl.scala 91:61] - node _T_300 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_302 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_303 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_304 = eq(_T_303, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_305 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_306 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_308 = and(_T_301, _T_302) @[el2_dec_dec_ctl.scala 92:43] - node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 92:43] - node _T_310 = and(_T_309, _T_305) @[el2_dec_dec_ctl.scala 92:43] - node _T_311 = and(_T_310, _T_307) @[el2_dec_dec_ctl.scala 92:43] - node _T_312 = or(_T_299, _T_311) @[el2_dec_dec_ctl.scala 91:109] - node _T_313 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_314 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_316 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_318 = and(_T_313, _T_315) @[el2_dec_dec_ctl.scala 92:80] - node _T_319 = and(_T_318, _T_317) @[el2_dec_dec_ctl.scala 92:80] - node _T_320 = or(_T_312, _T_319) @[el2_dec_dec_ctl.scala 92:47] - io.out.sub <= _T_320 @[el2_dec_dec_ctl.scala 91:14] - node _T_321 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_322 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_323 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_324 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_326 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_328 = and(_T_321, _T_322) @[el2_dec_dec_ctl.scala 93:56] - node _T_329 = and(_T_328, _T_323) @[el2_dec_dec_ctl.scala 93:56] - node _T_330 = and(_T_329, _T_325) @[el2_dec_dec_ctl.scala 93:56] - node _T_331 = and(_T_330, _T_327) @[el2_dec_dec_ctl.scala 93:56] - node _T_332 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_334 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_335 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_336 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_337 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_339 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_341 = and(_T_333, _T_334) @[el2_dec_dec_ctl.scala 93:104] - node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 93:104] - node _T_343 = and(_T_342, _T_336) @[el2_dec_dec_ctl.scala 93:104] - node _T_344 = and(_T_343, _T_338) @[el2_dec_dec_ctl.scala 93:104] - node _T_345 = and(_T_344, _T_340) @[el2_dec_dec_ctl.scala 93:104] - node _T_346 = or(_T_331, _T_345) @[el2_dec_dec_ctl.scala 93:60] - io.out.land <= _T_346 @[el2_dec_dec_ctl.scala 93:15] - node _T_347 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_348 = eq(_T_347, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_349 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_350 = and(_T_348, _T_349) @[el2_dec_dec_ctl.scala 94:45] - node _T_351 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_353 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_354 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_355 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_356 = eq(_T_355, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_357 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_358 = eq(_T_357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_360 = eq(_T_359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_361 = and(_T_352, _T_353) @[el2_dec_dec_ctl.scala 94:94] - node _T_362 = and(_T_361, _T_354) @[el2_dec_dec_ctl.scala 94:94] - node _T_363 = and(_T_362, _T_356) @[el2_dec_dec_ctl.scala 94:94] - node _T_364 = and(_T_363, _T_358) @[el2_dec_dec_ctl.scala 94:94] - node _T_365 = and(_T_364, _T_360) @[el2_dec_dec_ctl.scala 94:94] - node _T_366 = or(_T_350, _T_365) @[el2_dec_dec_ctl.scala 94:49] - node _T_367 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_368 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_369 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_370 = and(_T_367, _T_368) @[el2_dec_dec_ctl.scala 95:34] - node _T_371 = and(_T_370, _T_369) @[el2_dec_dec_ctl.scala 95:34] - node _T_372 = or(_T_366, _T_371) @[el2_dec_dec_ctl.scala 94:98] - node _T_373 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_374 = eq(_T_373, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_375 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_377 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_378 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_379 = and(_T_374, _T_376) @[el2_dec_dec_ctl.scala 95:75] - node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 95:75] - node _T_381 = and(_T_380, _T_378) @[el2_dec_dec_ctl.scala 95:75] - node _T_382 = or(_T_372, _T_381) @[el2_dec_dec_ctl.scala 95:38] - node _T_383 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_384 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_385 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_387 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_389 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_391 = and(_T_383, _T_384) @[el2_dec_dec_ctl.scala 96:44] - node _T_392 = and(_T_391, _T_386) @[el2_dec_dec_ctl.scala 96:44] - node _T_393 = and(_T_392, _T_388) @[el2_dec_dec_ctl.scala 96:44] - node _T_394 = and(_T_393, _T_390) @[el2_dec_dec_ctl.scala 96:44] - node _T_395 = or(_T_382, _T_394) @[el2_dec_dec_ctl.scala 95:79] - io.out.lor <= _T_395 @[el2_dec_dec_ctl.scala 94:14] - node _T_396 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_398 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_399 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_401 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_403 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_404 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_405 = eq(_T_404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_406 = and(_T_397, _T_398) @[el2_dec_dec_ctl.scala 97:61] - node _T_407 = and(_T_406, _T_400) @[el2_dec_dec_ctl.scala 97:61] - node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 97:61] - node _T_409 = and(_T_408, _T_403) @[el2_dec_dec_ctl.scala 97:61] - node _T_410 = and(_T_409, _T_405) @[el2_dec_dec_ctl.scala 97:61] - node _T_411 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_412 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_414 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_415 = eq(_T_414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_416 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_418 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_419 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_421 = and(_T_411, _T_413) @[el2_dec_dec_ctl.scala 97:109] - node _T_422 = and(_T_421, _T_415) @[el2_dec_dec_ctl.scala 97:109] - node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 97:109] - node _T_424 = and(_T_423, _T_418) @[el2_dec_dec_ctl.scala 97:109] - node _T_425 = and(_T_424, _T_420) @[el2_dec_dec_ctl.scala 97:109] - node _T_426 = or(_T_410, _T_425) @[el2_dec_dec_ctl.scala 97:65] - io.out.lxor <= _T_426 @[el2_dec_dec_ctl.scala 97:15] - node _T_427 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_428 = eq(_T_427, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_429 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_431 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_433 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_434 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_436 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_437 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_438 = eq(_T_437, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_439 = and(_T_428, _T_430) @[el2_dec_dec_ctl.scala 98:63] - node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 98:63] - node _T_441 = and(_T_440, _T_433) @[el2_dec_dec_ctl.scala 98:63] - node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 98:63] - node _T_443 = and(_T_442, _T_436) @[el2_dec_dec_ctl.scala 98:63] - node _T_444 = and(_T_443, _T_438) @[el2_dec_dec_ctl.scala 98:63] - io.out.sll <= _T_444 @[el2_dec_dec_ctl.scala 98:14] - node _T_445 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] - node _T_446 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_447 = eq(_T_446, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_448 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_449 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_450 = eq(_T_449, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_451 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_452 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_454 = and(_T_445, _T_447) @[el2_dec_dec_ctl.scala 99:58] - node _T_455 = and(_T_454, _T_448) @[el2_dec_dec_ctl.scala 99:58] - node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 99:58] - node _T_457 = and(_T_456, _T_451) @[el2_dec_dec_ctl.scala 99:58] - node _T_458 = and(_T_457, _T_453) @[el2_dec_dec_ctl.scala 99:58] - io.out.sra <= _T_458 @[el2_dec_dec_ctl.scala 99:14] - node _T_459 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_461 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_463 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_464 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_466 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_467 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_469 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_470 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_471 = eq(_T_470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_472 = and(_T_460, _T_462) @[el2_dec_dec_ctl.scala 100:66] - node _T_473 = and(_T_472, _T_463) @[el2_dec_dec_ctl.scala 100:66] - node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 100:66] - node _T_475 = and(_T_474, _T_466) @[el2_dec_dec_ctl.scala 100:66] - node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 100:66] - node _T_477 = and(_T_476, _T_469) @[el2_dec_dec_ctl.scala 100:66] - node _T_478 = and(_T_477, _T_471) @[el2_dec_dec_ctl.scala 100:66] - io.out.srl <= _T_478 @[el2_dec_dec_ctl.scala 100:14] - node _T_479 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_480 = eq(_T_479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_481 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_482 = eq(_T_481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_483 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_484 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_485 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_487 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_488 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_490 = and(_T_480, _T_482) @[el2_dec_dec_ctl.scala 101:62] - node _T_491 = and(_T_490, _T_483) @[el2_dec_dec_ctl.scala 101:62] - node _T_492 = and(_T_491, _T_484) @[el2_dec_dec_ctl.scala 101:62] - node _T_493 = and(_T_492, _T_486) @[el2_dec_dec_ctl.scala 101:62] - node _T_494 = and(_T_493, _T_487) @[el2_dec_dec_ctl.scala 101:62] - node _T_495 = and(_T_494, _T_489) @[el2_dec_dec_ctl.scala 101:62] - node _T_496 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_498 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_499 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_501 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_502 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_503 = eq(_T_502, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_504 = and(_T_497, _T_498) @[el2_dec_dec_ctl.scala 101:106] - node _T_505 = and(_T_504, _T_500) @[el2_dec_dec_ctl.scala 101:106] - node _T_506 = and(_T_505, _T_501) @[el2_dec_dec_ctl.scala 101:106] - node _T_507 = and(_T_506, _T_503) @[el2_dec_dec_ctl.scala 101:106] - node _T_508 = or(_T_495, _T_507) @[el2_dec_dec_ctl.scala 101:66] - io.out.slt <= _T_508 @[el2_dec_dec_ctl.scala 101:14] - node _T_509 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_510 = eq(_T_509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_511 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_512 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_513 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_515 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_516 = eq(_T_515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_517 = and(_T_510, _T_511) @[el2_dec_dec_ctl.scala 102:59] - node _T_518 = and(_T_517, _T_512) @[el2_dec_dec_ctl.scala 102:59] - node _T_519 = and(_T_518, _T_514) @[el2_dec_dec_ctl.scala 102:59] - node _T_520 = and(_T_519, _T_516) @[el2_dec_dec_ctl.scala 102:59] - node _T_521 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_522 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_523 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_524 = eq(_T_523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_525 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_527 = and(_T_521, _T_522) @[el2_dec_dec_ctl.scala 102:99] - node _T_528 = and(_T_527, _T_524) @[el2_dec_dec_ctl.scala 102:99] - node _T_529 = and(_T_528, _T_526) @[el2_dec_dec_ctl.scala 102:99] - node _T_530 = or(_T_520, _T_529) @[el2_dec_dec_ctl.scala 102:63] - node _T_531 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_532 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_534 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_536 = and(_T_531, _T_533) @[el2_dec_dec_ctl.scala 103:37] - node _T_537 = and(_T_536, _T_535) @[el2_dec_dec_ctl.scala 103:37] - node _T_538 = or(_T_530, _T_537) @[el2_dec_dec_ctl.scala 102:103] - node _T_539 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_540 = eq(_T_539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_541 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_543 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_544 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_545 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_547 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_549 = and(_T_540, _T_542) @[el2_dec_dec_ctl.scala 103:86] - node _T_550 = and(_T_549, _T_543) @[el2_dec_dec_ctl.scala 103:86] - node _T_551 = and(_T_550, _T_544) @[el2_dec_dec_ctl.scala 103:86] - node _T_552 = and(_T_551, _T_546) @[el2_dec_dec_ctl.scala 103:86] - node _T_553 = and(_T_552, _T_548) @[el2_dec_dec_ctl.scala 103:86] - node _T_554 = or(_T_538, _T_553) @[el2_dec_dec_ctl.scala 103:41] - node _T_555 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_556 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_557 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_558 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_560 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_561 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_563 = and(_T_555, _T_556) @[el2_dec_dec_ctl.scala 104:45] - node _T_564 = and(_T_563, _T_557) @[el2_dec_dec_ctl.scala 104:45] - node _T_565 = and(_T_564, _T_559) @[el2_dec_dec_ctl.scala 104:45] - node _T_566 = and(_T_565, _T_560) @[el2_dec_dec_ctl.scala 104:45] - node _T_567 = and(_T_566, _T_562) @[el2_dec_dec_ctl.scala 104:45] - node _T_568 = or(_T_554, _T_567) @[el2_dec_dec_ctl.scala 103:90] - io.out.unsign <= _T_568 @[el2_dec_dec_ctl.scala 102:17] - node _T_569 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_570 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_571 = eq(_T_570, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_572 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_573 = eq(_T_572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_574 = and(_T_569, _T_571) @[el2_dec_dec_ctl.scala 105:51] - node _T_575 = and(_T_574, _T_573) @[el2_dec_dec_ctl.scala 105:51] - io.out.condbr <= _T_575 @[el2_dec_dec_ctl.scala 105:17] - node _T_576 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_577 = eq(_T_576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_578 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_580 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_581 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_583 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_584 = eq(_T_583, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_585 = and(_T_577, _T_579) @[el2_dec_dec_ctl.scala 106:56] - node _T_586 = and(_T_585, _T_580) @[el2_dec_dec_ctl.scala 106:56] - node _T_587 = and(_T_586, _T_582) @[el2_dec_dec_ctl.scala 106:56] - node _T_588 = and(_T_587, _T_584) @[el2_dec_dec_ctl.scala 106:56] - io.out.beq <= _T_588 @[el2_dec_dec_ctl.scala 106:14] - node _T_589 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_590 = eq(_T_589, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_591 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_592 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_593 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_594 = eq(_T_593, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_595 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_597 = and(_T_590, _T_591) @[el2_dec_dec_ctl.scala 107:55] - node _T_598 = and(_T_597, _T_592) @[el2_dec_dec_ctl.scala 107:55] - node _T_599 = and(_T_598, _T_594) @[el2_dec_dec_ctl.scala 107:55] - node _T_600 = and(_T_599, _T_596) @[el2_dec_dec_ctl.scala 107:55] - io.out.bne <= _T_600 @[el2_dec_dec_ctl.scala 107:14] - node _T_601 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_602 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_603 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_604 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_606 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_608 = and(_T_601, _T_602) @[el2_dec_dec_ctl.scala 108:54] - node _T_609 = and(_T_608, _T_603) @[el2_dec_dec_ctl.scala 108:54] - node _T_610 = and(_T_609, _T_605) @[el2_dec_dec_ctl.scala 108:54] - node _T_611 = and(_T_610, _T_607) @[el2_dec_dec_ctl.scala 108:54] - io.out.bge <= _T_611 @[el2_dec_dec_ctl.scala 108:14] - node _T_612 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_613 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_615 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_616 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_617 = eq(_T_616, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_618 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_620 = and(_T_612, _T_614) @[el2_dec_dec_ctl.scala 109:55] - node _T_621 = and(_T_620, _T_615) @[el2_dec_dec_ctl.scala 109:55] - node _T_622 = and(_T_621, _T_617) @[el2_dec_dec_ctl.scala 109:55] - node _T_623 = and(_T_622, _T_619) @[el2_dec_dec_ctl.scala 109:55] - io.out.blt <= _T_623 @[el2_dec_dec_ctl.scala 109:14] - node _T_624 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_625 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_626 = and(_T_624, _T_625) @[el2_dec_dec_ctl.scala 110:44] - io.out.jal <= _T_626 @[el2_dec_dec_ctl.scala 110:14] - node _T_627 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_628 = eq(_T_627, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_629 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_631 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_632 = eq(_T_631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_633 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_635 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_636 = eq(_T_635, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_637 = and(_T_628, _T_630) @[el2_dec_dec_ctl.scala 111:56] - node _T_638 = and(_T_637, _T_632) @[el2_dec_dec_ctl.scala 111:56] - node _T_639 = and(_T_638, _T_634) @[el2_dec_dec_ctl.scala 111:56] - node _T_640 = and(_T_639, _T_636) @[el2_dec_dec_ctl.scala 111:56] - io.out.by <= _T_640 @[el2_dec_dec_ctl.scala 111:13] - node _T_641 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_642 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_644 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_646 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_647 = eq(_T_646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_648 = and(_T_641, _T_643) @[el2_dec_dec_ctl.scala 112:53] - node _T_649 = and(_T_648, _T_645) @[el2_dec_dec_ctl.scala 112:53] - node _T_650 = and(_T_649, _T_647) @[el2_dec_dec_ctl.scala 112:53] - io.out.half <= _T_650 @[el2_dec_dec_ctl.scala 112:15] - node _T_651 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_652 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_654 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_656 = and(_T_651, _T_653) @[el2_dec_dec_ctl.scala 113:50] - node _T_657 = and(_T_656, _T_655) @[el2_dec_dec_ctl.scala 113:50] - io.out.word <= _T_657 @[el2_dec_dec_ctl.scala 113:15] - node _T_658 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_659 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_660 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_661 = and(_T_658, _T_659) @[el2_dec_dec_ctl.scala 114:52] - node _T_662 = and(_T_661, _T_660) @[el2_dec_dec_ctl.scala 114:52] - node _T_663 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_664 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_665 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_666 = and(_T_663, _T_664) @[el2_dec_dec_ctl.scala 114:87] - node _T_667 = and(_T_666, _T_665) @[el2_dec_dec_ctl.scala 114:87] - node _T_668 = or(_T_662, _T_667) @[el2_dec_dec_ctl.scala 114:56] - node _T_669 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_670 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_672 = and(_T_669, _T_670) @[el2_dec_dec_ctl.scala 115:34] - node _T_673 = and(_T_672, _T_671) @[el2_dec_dec_ctl.scala 115:34] - node _T_674 = or(_T_668, _T_673) @[el2_dec_dec_ctl.scala 114:91] - node _T_675 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_676 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_677 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_678 = and(_T_675, _T_676) @[el2_dec_dec_ctl.scala 115:69] - node _T_679 = and(_T_678, _T_677) @[el2_dec_dec_ctl.scala 115:69] - node _T_680 = or(_T_674, _T_679) @[el2_dec_dec_ctl.scala 115:38] - node _T_681 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_682 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_683 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_684 = and(_T_681, _T_682) @[el2_dec_dec_ctl.scala 115:105] - node _T_685 = and(_T_684, _T_683) @[el2_dec_dec_ctl.scala 115:105] - node _T_686 = or(_T_680, _T_685) @[el2_dec_dec_ctl.scala 115:73] - node _T_687 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_688 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_690 = and(_T_687, _T_688) @[el2_dec_dec_ctl.scala 116:35] - node _T_691 = and(_T_690, _T_689) @[el2_dec_dec_ctl.scala 116:35] - node _T_692 = or(_T_686, _T_691) @[el2_dec_dec_ctl.scala 115:109] - io.out.csr_read <= _T_692 @[el2_dec_dec_ctl.scala 114:19] - node _T_693 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_694 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_695 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_696 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_697 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_698 = and(_T_693, _T_694) @[el2_dec_dec_ctl.scala 117:57] - node _T_699 = and(_T_698, _T_695) @[el2_dec_dec_ctl.scala 117:57] - node _T_700 = and(_T_699, _T_696) @[el2_dec_dec_ctl.scala 117:57] - node _T_701 = and(_T_700, _T_697) @[el2_dec_dec_ctl.scala 117:57] - node _T_702 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_703 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_704 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_705 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_706 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_707 = and(_T_702, _T_703) @[el2_dec_dec_ctl.scala 117:99] - node _T_708 = and(_T_707, _T_704) @[el2_dec_dec_ctl.scala 117:99] - node _T_709 = and(_T_708, _T_705) @[el2_dec_dec_ctl.scala 117:99] - node _T_710 = and(_T_709, _T_706) @[el2_dec_dec_ctl.scala 117:99] - node _T_711 = or(_T_701, _T_710) @[el2_dec_dec_ctl.scala 117:61] - node _T_712 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_713 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_714 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_715 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_716 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_717 = and(_T_712, _T_713) @[el2_dec_dec_ctl.scala 118:41] - node _T_718 = and(_T_717, _T_714) @[el2_dec_dec_ctl.scala 118:41] - node _T_719 = and(_T_718, _T_715) @[el2_dec_dec_ctl.scala 118:41] - node _T_720 = and(_T_719, _T_716) @[el2_dec_dec_ctl.scala 118:41] - node _T_721 = or(_T_711, _T_720) @[el2_dec_dec_ctl.scala 117:103] - node _T_722 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_723 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_724 = eq(_T_723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_725 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_726 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_727 = and(_T_722, _T_724) @[el2_dec_dec_ctl.scala 118:81] - node _T_728 = and(_T_727, _T_725) @[el2_dec_dec_ctl.scala 118:81] - node _T_729 = and(_T_728, _T_726) @[el2_dec_dec_ctl.scala 118:81] - node _T_730 = or(_T_721, _T_729) @[el2_dec_dec_ctl.scala 118:45] - node _T_731 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_732 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_733 = eq(_T_732, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_734 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_735 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_736 = and(_T_731, _T_733) @[el2_dec_dec_ctl.scala 119:39] - node _T_737 = and(_T_736, _T_734) @[el2_dec_dec_ctl.scala 119:39] - node _T_738 = and(_T_737, _T_735) @[el2_dec_dec_ctl.scala 119:39] - node _T_739 = or(_T_730, _T_738) @[el2_dec_dec_ctl.scala 118:85] - io.out.csr_clr <= _T_739 @[el2_dec_dec_ctl.scala 117:18] - node _T_740 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_741 = eq(_T_740, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_742 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_743 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_744 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_745 = and(_T_741, _T_742) @[el2_dec_dec_ctl.scala 120:57] - node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 120:57] - node _T_747 = and(_T_746, _T_744) @[el2_dec_dec_ctl.scala 120:57] - io.out.csr_write <= _T_747 @[el2_dec_dec_ctl.scala 120:20] - node _T_748 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_749 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_750 = eq(_T_749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_752 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_753 = and(_T_748, _T_750) @[el2_dec_dec_ctl.scala 121:55] - node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 121:55] - node _T_755 = and(_T_754, _T_752) @[el2_dec_dec_ctl.scala 121:55] - node _T_756 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_757 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_758 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_759 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_760 = and(_T_756, _T_757) @[el2_dec_dec_ctl.scala 121:94] - node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 121:94] - node _T_762 = and(_T_761, _T_759) @[el2_dec_dec_ctl.scala 121:94] - node _T_763 = or(_T_755, _T_762) @[el2_dec_dec_ctl.scala 121:59] - node _T_764 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_765 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_766 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_767 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_768 = and(_T_764, _T_765) @[el2_dec_dec_ctl.scala 122:38] - node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 122:38] - node _T_770 = and(_T_769, _T_767) @[el2_dec_dec_ctl.scala 122:38] - node _T_771 = or(_T_763, _T_770) @[el2_dec_dec_ctl.scala 121:98] - node _T_772 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_773 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_774 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_775 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_776 = and(_T_772, _T_773) @[el2_dec_dec_ctl.scala 122:77] - node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 122:77] - node _T_778 = and(_T_777, _T_775) @[el2_dec_dec_ctl.scala 122:77] - node _T_779 = or(_T_771, _T_778) @[el2_dec_dec_ctl.scala 122:42] - node _T_780 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_781 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_782 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_783 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_784 = and(_T_780, _T_781) @[el2_dec_dec_ctl.scala 123:38] - node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 123:38] - node _T_786 = and(_T_785, _T_783) @[el2_dec_dec_ctl.scala 123:38] - node _T_787 = or(_T_779, _T_786) @[el2_dec_dec_ctl.scala 122:81] - node _T_788 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_789 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_790 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_791 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_792 = and(_T_788, _T_789) @[el2_dec_dec_ctl.scala 123:77] - node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 123:77] - node _T_794 = and(_T_793, _T_791) @[el2_dec_dec_ctl.scala 123:77] - node _T_795 = or(_T_787, _T_794) @[el2_dec_dec_ctl.scala 123:42] - io.out.csr_imm <= _T_795 @[el2_dec_dec_ctl.scala 121:18] - node _T_796 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_797 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_799 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_800 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_801 = and(_T_796, _T_798) @[el2_dec_dec_ctl.scala 124:55] - node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 124:55] - node _T_803 = and(_T_802, _T_800) @[el2_dec_dec_ctl.scala 124:55] - node _T_804 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_805 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_806 = eq(_T_805, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_807 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_808 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_809 = and(_T_804, _T_806) @[el2_dec_dec_ctl.scala 124:95] - node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 124:95] - node _T_811 = and(_T_810, _T_808) @[el2_dec_dec_ctl.scala 124:95] - node _T_812 = or(_T_803, _T_811) @[el2_dec_dec_ctl.scala 124:59] - node _T_813 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_815 = eq(_T_814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_816 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_817 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_818 = and(_T_813, _T_815) @[el2_dec_dec_ctl.scala 125:39] - node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 125:39] - node _T_820 = and(_T_819, _T_817) @[el2_dec_dec_ctl.scala 125:39] - node _T_821 = or(_T_812, _T_820) @[el2_dec_dec_ctl.scala 124:99] - node _T_822 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_823 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_824 = eq(_T_823, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_825 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_826 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_827 = and(_T_822, _T_824) @[el2_dec_dec_ctl.scala 125:79] - node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 125:79] - node _T_829 = and(_T_828, _T_826) @[el2_dec_dec_ctl.scala 125:79] - node _T_830 = or(_T_821, _T_829) @[el2_dec_dec_ctl.scala 125:43] - node _T_831 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_832 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_834 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_835 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_836 = and(_T_831, _T_833) @[el2_dec_dec_ctl.scala 126:39] - node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 126:39] - node _T_838 = and(_T_837, _T_835) @[el2_dec_dec_ctl.scala 126:39] - node _T_839 = or(_T_830, _T_838) @[el2_dec_dec_ctl.scala 125:83] - io.out.csr_set <= _T_839 @[el2_dec_dec_ctl.scala 124:18] - node _T_840 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_841 = eq(_T_840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_842 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] - node _T_843 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_845 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_846 = eq(_T_845, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_847 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_848 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_849 = and(_T_841, _T_842) @[el2_dec_dec_ctl.scala 127:62] - node _T_850 = and(_T_849, _T_844) @[el2_dec_dec_ctl.scala 127:62] - node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 127:62] - node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 127:62] - node _T_853 = and(_T_852, _T_848) @[el2_dec_dec_ctl.scala 127:62] - io.out.ebreak <= _T_853 @[el2_dec_dec_ctl.scala 127:17] - node _T_854 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_856 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] - node _T_857 = eq(_T_856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_858 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_859 = eq(_T_858, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_860 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_861 = eq(_T_860, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_862 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_864 = and(_T_855, _T_857) @[el2_dec_dec_ctl.scala 128:62] - node _T_865 = and(_T_864, _T_859) @[el2_dec_dec_ctl.scala 128:62] - node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 128:62] - node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 128:62] - node _T_868 = and(_T_867, _T_863) @[el2_dec_dec_ctl.scala 128:62] - io.out.ecall <= _T_868 @[el2_dec_dec_ctl.scala 128:16] - node _T_869 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] - node _T_870 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_872 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_873 = eq(_T_872, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_874 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_875 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_876 = and(_T_869, _T_871) @[el2_dec_dec_ctl.scala 129:56] - node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 129:56] - node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 129:56] - node _T_879 = and(_T_878, _T_875) @[el2_dec_dec_ctl.scala 129:56] - io.out.mret <= _T_879 @[el2_dec_dec_ctl.scala 129:15] - node _T_880 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_881 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_883 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_885 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_886 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_887 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_888 = eq(_T_887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_889 = and(_T_880, _T_882) @[el2_dec_dec_ctl.scala 130:57] - node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 130:57] - node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 130:57] - node _T_892 = and(_T_891, _T_886) @[el2_dec_dec_ctl.scala 130:57] - node _T_893 = and(_T_892, _T_888) @[el2_dec_dec_ctl.scala 130:57] - io.out.mul <= _T_893 @[el2_dec_dec_ctl.scala 130:14] - node _T_894 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_895 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_896 = eq(_T_895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_897 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_898 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_902 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_903 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_904 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_905 = eq(_T_904, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_906 = and(_T_894, _T_896) @[el2_dec_dec_ctl.scala 131:69] - node _T_907 = and(_T_906, _T_897) @[el2_dec_dec_ctl.scala 131:69] - node _T_908 = and(_T_907, _T_899) @[el2_dec_dec_ctl.scala 131:69] - node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 131:69] - node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 131:69] - node _T_911 = and(_T_910, _T_903) @[el2_dec_dec_ctl.scala 131:69] - node _T_912 = and(_T_911, _T_905) @[el2_dec_dec_ctl.scala 131:69] - node _T_913 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_914 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_915 = eq(_T_914, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_916 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_917 = eq(_T_916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_918 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_919 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_921 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_922 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_923 = eq(_T_922, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_924 = and(_T_913, _T_915) @[el2_dec_dec_ctl.scala 132:50] - node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 132:50] - node _T_926 = and(_T_925, _T_918) @[el2_dec_dec_ctl.scala 132:50] - node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 132:50] - node _T_928 = and(_T_927, _T_921) @[el2_dec_dec_ctl.scala 132:50] - node _T_929 = and(_T_928, _T_923) @[el2_dec_dec_ctl.scala 132:50] - node _T_930 = or(_T_912, _T_929) @[el2_dec_dec_ctl.scala 131:73] - io.out.rs1_sign <= _T_930 @[el2_dec_dec_ctl.scala 131:19] - node _T_931 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_934 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_935 = eq(_T_934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_936 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_937 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_938 = eq(_T_937, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_939 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_940 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_942 = and(_T_931, _T_933) @[el2_dec_dec_ctl.scala 133:67] - node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 133:67] - node _T_944 = and(_T_943, _T_936) @[el2_dec_dec_ctl.scala 133:67] - node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 133:67] - node _T_946 = and(_T_945, _T_939) @[el2_dec_dec_ctl.scala 133:67] - node _T_947 = and(_T_946, _T_941) @[el2_dec_dec_ctl.scala 133:67] - io.out.rs2_sign <= _T_947 @[el2_dec_dec_ctl.scala 133:19] - node _T_948 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_949 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_950 = eq(_T_949, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_951 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_952 = eq(_T_951, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_953 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_955 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_957 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_959 = and(_T_948, _T_950) @[el2_dec_dec_ctl.scala 134:62] - node _T_960 = and(_T_959, _T_952) @[el2_dec_dec_ctl.scala 134:62] - node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 134:62] - node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 134:62] - node _T_963 = and(_T_962, _T_956) @[el2_dec_dec_ctl.scala 134:62] - node _T_964 = and(_T_963, _T_958) @[el2_dec_dec_ctl.scala 134:62] - io.out.low <= _T_964 @[el2_dec_dec_ctl.scala 134:14] - node _T_965 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_966 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_969 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_970 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_971 = eq(_T_970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_972 = and(_T_965, _T_966) @[el2_dec_dec_ctl.scala 135:54] - node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 135:54] - node _T_974 = and(_T_973, _T_969) @[el2_dec_dec_ctl.scala 135:54] - node _T_975 = and(_T_974, _T_971) @[el2_dec_dec_ctl.scala 135:54] - io.out.div <= _T_975 @[el2_dec_dec_ctl.scala 135:14] - node _T_976 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_977 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_978 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_979 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_981 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_982 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_983 = eq(_T_982, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_984 = and(_T_976, _T_977) @[el2_dec_dec_ctl.scala 136:57] - node _T_985 = and(_T_984, _T_978) @[el2_dec_dec_ctl.scala 136:57] - node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 136:57] - node _T_987 = and(_T_986, _T_981) @[el2_dec_dec_ctl.scala 136:57] - node _T_988 = and(_T_987, _T_983) @[el2_dec_dec_ctl.scala 136:57] - io.out.rem <= _T_988 @[el2_dec_dec_ctl.scala 136:14] - node _T_989 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_990 = eq(_T_989, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_991 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_992 = and(_T_990, _T_991) @[el2_dec_dec_ctl.scala 137:47] - io.out.fence <= _T_992 @[el2_dec_dec_ctl.scala 137:16] - node _T_993 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_994 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_995 = eq(_T_994, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_996 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_997 = and(_T_993, _T_995) @[el2_dec_dec_ctl.scala 138:52] - node _T_998 = and(_T_997, _T_996) @[el2_dec_dec_ctl.scala 138:52] - io.out.fence_i <= _T_998 @[el2_dec_dec_ctl.scala 138:18] - node _T_999 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] - node _T_1000 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] - node _T_1001 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1003 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1005 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1006 = and(_T_999, _T_1000) @[el2_dec_dec_ctl.scala 139:59] - node _T_1007 = and(_T_1006, _T_1002) @[el2_dec_dec_ctl.scala 139:59] - node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 139:59] - node _T_1009 = and(_T_1008, _T_1005) @[el2_dec_dec_ctl.scala 139:59] - node _T_1010 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1011 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1012 = and(_T_1010, _T_1011) @[el2_dec_dec_ctl.scala 139:92] - node _T_1013 = or(_T_1009, _T_1012) @[el2_dec_dec_ctl.scala 139:63] - node _T_1014 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1015 = eq(_T_1014, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1016 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1017 = eq(_T_1016, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1018 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1019 = and(_T_1015, _T_1017) @[el2_dec_dec_ctl.scala 140:37] - node _T_1020 = and(_T_1019, _T_1018) @[el2_dec_dec_ctl.scala 140:37] - node _T_1021 = or(_T_1013, _T_1020) @[el2_dec_dec_ctl.scala 139:96] - node _T_1022 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1024 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1025 = and(_T_1023, _T_1024) @[el2_dec_dec_ctl.scala 140:71] - node _T_1026 = or(_T_1021, _T_1025) @[el2_dec_dec_ctl.scala 140:41] - io.out.pm_alu <= _T_1026 @[el2_dec_dec_ctl.scala 139:17] - node _T_1027 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1028 = eq(_T_1027, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1029 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1030 = and(_T_1028, _T_1029) @[el2_dec_dec_ctl.scala 141:49] - node _T_1031 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1032 = eq(_T_1031, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1033 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_1034 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1035 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1036 = and(_T_1032, _T_1033) @[el2_dec_dec_ctl.scala 141:88] - node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 141:88] - node _T_1038 = and(_T_1037, _T_1035) @[el2_dec_dec_ctl.scala 141:88] - node _T_1039 = or(_T_1030, _T_1038) @[el2_dec_dec_ctl.scala 141:53] - node _T_1040 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1042 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_1043 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1044 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1045 = and(_T_1041, _T_1042) @[el2_dec_dec_ctl.scala 142:38] - node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 142:38] - node _T_1047 = and(_T_1046, _T_1044) @[el2_dec_dec_ctl.scala 142:38] - node _T_1048 = or(_T_1039, _T_1047) @[el2_dec_dec_ctl.scala 141:92] - node _T_1049 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1051 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_1052 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1053 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1054 = and(_T_1050, _T_1051) @[el2_dec_dec_ctl.scala 142:77] - node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 142:77] - node _T_1056 = and(_T_1055, _T_1053) @[el2_dec_dec_ctl.scala 142:77] - node _T_1057 = or(_T_1048, _T_1056) @[el2_dec_dec_ctl.scala 142:42] - node _T_1058 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1059 = eq(_T_1058, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1060 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_1061 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1062 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1063 = and(_T_1059, _T_1060) @[el2_dec_dec_ctl.scala 143:38] - node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 143:38] - node _T_1065 = and(_T_1064, _T_1062) @[el2_dec_dec_ctl.scala 143:38] - node _T_1066 = or(_T_1057, _T_1065) @[el2_dec_dec_ctl.scala 142:81] - node _T_1067 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1069 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_1070 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1071 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1072 = and(_T_1068, _T_1069) @[el2_dec_dec_ctl.scala 143:78] - node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 143:78] - node _T_1074 = and(_T_1073, _T_1071) @[el2_dec_dec_ctl.scala 143:78] - node _T_1075 = or(_T_1066, _T_1074) @[el2_dec_dec_ctl.scala 143:42] - node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1078 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_1079 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1080 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1081 = and(_T_1077, _T_1078) @[el2_dec_dec_ctl.scala 144:39] - node _T_1082 = and(_T_1081, _T_1079) @[el2_dec_dec_ctl.scala 144:39] - node _T_1083 = and(_T_1082, _T_1080) @[el2_dec_dec_ctl.scala 144:39] - node _T_1084 = or(_T_1075, _T_1083) @[el2_dec_dec_ctl.scala 143:82] - node _T_1085 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_1086 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1087 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1088 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1089 = and(_T_1085, _T_1086) @[el2_dec_dec_ctl.scala 144:78] - node _T_1090 = and(_T_1089, _T_1087) @[el2_dec_dec_ctl.scala 144:78] - node _T_1091 = and(_T_1090, _T_1088) @[el2_dec_dec_ctl.scala 144:78] - node _T_1092 = or(_T_1084, _T_1091) @[el2_dec_dec_ctl.scala 144:43] - node _T_1093 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_1094 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1095 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1096 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1097 = and(_T_1093, _T_1094) @[el2_dec_dec_ctl.scala 145:38] - node _T_1098 = and(_T_1097, _T_1095) @[el2_dec_dec_ctl.scala 145:38] - node _T_1099 = and(_T_1098, _T_1096) @[el2_dec_dec_ctl.scala 145:38] - node _T_1100 = or(_T_1092, _T_1099) @[el2_dec_dec_ctl.scala 144:82] - node _T_1101 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_1102 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1104 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1105 = and(_T_1101, _T_1102) @[el2_dec_dec_ctl.scala 145:77] - node _T_1106 = and(_T_1105, _T_1103) @[el2_dec_dec_ctl.scala 145:77] - node _T_1107 = and(_T_1106, _T_1104) @[el2_dec_dec_ctl.scala 145:77] - node _T_1108 = or(_T_1100, _T_1107) @[el2_dec_dec_ctl.scala 145:42] - node _T_1109 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_1110 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1111 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1112 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1113 = and(_T_1109, _T_1110) @[el2_dec_dec_ctl.scala 146:38] - node _T_1114 = and(_T_1113, _T_1111) @[el2_dec_dec_ctl.scala 146:38] - node _T_1115 = and(_T_1114, _T_1112) @[el2_dec_dec_ctl.scala 146:38] - node _T_1116 = or(_T_1108, _T_1115) @[el2_dec_dec_ctl.scala 145:81] - node _T_1117 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_1118 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1119 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1120 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1121 = and(_T_1117, _T_1118) @[el2_dec_dec_ctl.scala 146:77] - node _T_1122 = and(_T_1121, _T_1119) @[el2_dec_dec_ctl.scala 146:77] - node _T_1123 = and(_T_1122, _T_1120) @[el2_dec_dec_ctl.scala 146:77] - node _T_1124 = or(_T_1116, _T_1123) @[el2_dec_dec_ctl.scala 146:42] - io.out.presync <= _T_1124 @[el2_dec_dec_ctl.scala 141:18] - node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_1126 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1128 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1129 = and(_T_1125, _T_1127) @[el2_dec_dec_ctl.scala 147:53] - node _T_1130 = and(_T_1129, _T_1128) @[el2_dec_dec_ctl.scala 147:53] - node _T_1131 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1133 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1135 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1139 = and(_T_1132, _T_1134) @[el2_dec_dec_ctl.scala 147:98] - node _T_1140 = and(_T_1139, _T_1136) @[el2_dec_dec_ctl.scala 147:98] - node _T_1141 = and(_T_1140, _T_1137) @[el2_dec_dec_ctl.scala 147:98] - node _T_1142 = and(_T_1141, _T_1138) @[el2_dec_dec_ctl.scala 147:98] - node _T_1143 = or(_T_1130, _T_1142) @[el2_dec_dec_ctl.scala 147:57] - node _T_1144 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1146 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_1147 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1148 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1149 = and(_T_1145, _T_1146) @[el2_dec_dec_ctl.scala 148:38] - node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 148:38] - node _T_1151 = and(_T_1150, _T_1148) @[el2_dec_dec_ctl.scala 148:38] - node _T_1152 = or(_T_1143, _T_1151) @[el2_dec_dec_ctl.scala 147:102] - node _T_1153 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1155 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_1156 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1157 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1158 = and(_T_1154, _T_1155) @[el2_dec_dec_ctl.scala 148:77] - node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 148:77] - node _T_1160 = and(_T_1159, _T_1157) @[el2_dec_dec_ctl.scala 148:77] - node _T_1161 = or(_T_1152, _T_1160) @[el2_dec_dec_ctl.scala 148:42] - node _T_1162 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1164 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_1165 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1166 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1167 = and(_T_1163, _T_1164) @[el2_dec_dec_ctl.scala 149:38] - node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 149:38] - node _T_1169 = and(_T_1168, _T_1166) @[el2_dec_dec_ctl.scala 149:38] - node _T_1170 = or(_T_1161, _T_1169) @[el2_dec_dec_ctl.scala 148:81] - node _T_1171 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1172 = eq(_T_1171, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1173 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_1174 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1175 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1176 = and(_T_1172, _T_1173) @[el2_dec_dec_ctl.scala 149:78] - node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 149:78] - node _T_1178 = and(_T_1177, _T_1175) @[el2_dec_dec_ctl.scala 149:78] - node _T_1179 = or(_T_1170, _T_1178) @[el2_dec_dec_ctl.scala 149:42] - node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1182 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_1183 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1184 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1185 = and(_T_1181, _T_1182) @[el2_dec_dec_ctl.scala 150:39] - node _T_1186 = and(_T_1185, _T_1183) @[el2_dec_dec_ctl.scala 150:39] - node _T_1187 = and(_T_1186, _T_1184) @[el2_dec_dec_ctl.scala 150:39] - node _T_1188 = or(_T_1179, _T_1187) @[el2_dec_dec_ctl.scala 149:82] - node _T_1189 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_1190 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1191 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1192 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1193 = and(_T_1189, _T_1190) @[el2_dec_dec_ctl.scala 150:78] - node _T_1194 = and(_T_1193, _T_1191) @[el2_dec_dec_ctl.scala 150:78] - node _T_1195 = and(_T_1194, _T_1192) @[el2_dec_dec_ctl.scala 150:78] - node _T_1196 = or(_T_1188, _T_1195) @[el2_dec_dec_ctl.scala 150:43] - node _T_1197 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_1198 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1199 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1200 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1201 = and(_T_1197, _T_1198) @[el2_dec_dec_ctl.scala 151:38] - node _T_1202 = and(_T_1201, _T_1199) @[el2_dec_dec_ctl.scala 151:38] - node _T_1203 = and(_T_1202, _T_1200) @[el2_dec_dec_ctl.scala 151:38] - node _T_1204 = or(_T_1196, _T_1203) @[el2_dec_dec_ctl.scala 150:82] - node _T_1205 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_1206 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1207 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1208 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1209 = and(_T_1205, _T_1206) @[el2_dec_dec_ctl.scala 151:77] - node _T_1210 = and(_T_1209, _T_1207) @[el2_dec_dec_ctl.scala 151:77] - node _T_1211 = and(_T_1210, _T_1208) @[el2_dec_dec_ctl.scala 151:77] - node _T_1212 = or(_T_1204, _T_1211) @[el2_dec_dec_ctl.scala 151:42] - node _T_1213 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_1214 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1215 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1216 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1217 = and(_T_1213, _T_1214) @[el2_dec_dec_ctl.scala 152:38] - node _T_1218 = and(_T_1217, _T_1215) @[el2_dec_dec_ctl.scala 152:38] - node _T_1219 = and(_T_1218, _T_1216) @[el2_dec_dec_ctl.scala 152:38] - node _T_1220 = or(_T_1212, _T_1219) @[el2_dec_dec_ctl.scala 151:81] - node _T_1221 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_1222 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1223 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1224 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1225 = and(_T_1221, _T_1222) @[el2_dec_dec_ctl.scala 152:77] - node _T_1226 = and(_T_1225, _T_1223) @[el2_dec_dec_ctl.scala 152:77] - node _T_1227 = and(_T_1226, _T_1224) @[el2_dec_dec_ctl.scala 152:77] - node _T_1228 = or(_T_1220, _T_1227) @[el2_dec_dec_ctl.scala 152:42] - io.out.postsync <= _T_1228 @[el2_dec_dec_ctl.scala 147:19] - node _T_1229 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1231 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1233 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] - node _T_1234 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] - node _T_1235 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1237 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1238 = eq(_T_1237, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1239 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1241 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1243 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1244 = eq(_T_1243, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1245 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1246 = eq(_T_1245, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1247 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:33] - node _T_1248 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] - node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1250 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1252 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1254 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1256 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1258 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1260 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1262 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1264 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1266 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1267 = eq(_T_1266, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1268 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1269 = eq(_T_1268, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1270 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1273 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1274 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1275 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1279 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1280 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1281 = eq(_T_1280, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1282 = and(_T_1230, _T_1232) @[el2_dec_dec_ctl.scala 153:144] - node _T_1283 = and(_T_1282, _T_1233) @[el2_dec_dec_ctl.scala 153:144] - node _T_1284 = and(_T_1283, _T_1234) @[el2_dec_dec_ctl.scala 153:144] - node _T_1285 = and(_T_1284, _T_1236) @[el2_dec_dec_ctl.scala 153:144] - node _T_1286 = and(_T_1285, _T_1238) @[el2_dec_dec_ctl.scala 153:144] - node _T_1287 = and(_T_1286, _T_1240) @[el2_dec_dec_ctl.scala 153:144] - node _T_1288 = and(_T_1287, _T_1242) @[el2_dec_dec_ctl.scala 153:144] - node _T_1289 = and(_T_1288, _T_1244) @[el2_dec_dec_ctl.scala 153:144] - node _T_1290 = and(_T_1289, _T_1246) @[el2_dec_dec_ctl.scala 153:144] - node _T_1291 = and(_T_1290, _T_1247) @[el2_dec_dec_ctl.scala 153:144] - node _T_1292 = and(_T_1291, _T_1249) @[el2_dec_dec_ctl.scala 153:144] - node _T_1293 = and(_T_1292, _T_1251) @[el2_dec_dec_ctl.scala 153:144] - node _T_1294 = and(_T_1293, _T_1253) @[el2_dec_dec_ctl.scala 153:144] - node _T_1295 = and(_T_1294, _T_1255) @[el2_dec_dec_ctl.scala 153:144] - node _T_1296 = and(_T_1295, _T_1257) @[el2_dec_dec_ctl.scala 153:144] - node _T_1297 = and(_T_1296, _T_1259) @[el2_dec_dec_ctl.scala 153:144] - node _T_1298 = and(_T_1297, _T_1261) @[el2_dec_dec_ctl.scala 153:144] - node _T_1299 = and(_T_1298, _T_1263) @[el2_dec_dec_ctl.scala 153:144] - node _T_1300 = and(_T_1299, _T_1265) @[el2_dec_dec_ctl.scala 153:144] - node _T_1301 = and(_T_1300, _T_1267) @[el2_dec_dec_ctl.scala 153:144] - node _T_1302 = and(_T_1301, _T_1269) @[el2_dec_dec_ctl.scala 153:144] - node _T_1303 = and(_T_1302, _T_1271) @[el2_dec_dec_ctl.scala 153:144] - node _T_1304 = and(_T_1303, _T_1272) @[el2_dec_dec_ctl.scala 153:144] - node _T_1305 = and(_T_1304, _T_1273) @[el2_dec_dec_ctl.scala 153:144] - node _T_1306 = and(_T_1305, _T_1274) @[el2_dec_dec_ctl.scala 153:144] - node _T_1307 = and(_T_1306, _T_1276) @[el2_dec_dec_ctl.scala 153:144] - node _T_1308 = and(_T_1307, _T_1278) @[el2_dec_dec_ctl.scala 153:144] - node _T_1309 = and(_T_1308, _T_1279) @[el2_dec_dec_ctl.scala 153:144] - node _T_1310 = and(_T_1309, _T_1281) @[el2_dec_dec_ctl.scala 153:144] - node _T_1311 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1313 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1315 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1317 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] - node _T_1318 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1320 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1321 = eq(_T_1320, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1322 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1324 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1326 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1328 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] - node _T_1329 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1331 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] - node _T_1332 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1334 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1336 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1338 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1339 = eq(_T_1338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1340 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1342 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1343 = eq(_T_1342, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1344 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1345 = eq(_T_1344, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1346 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1348 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1350 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1352 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1354 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1355 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1356 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1357 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1358 = eq(_T_1357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1360 = eq(_T_1359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1361 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1362 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1364 = and(_T_1312, _T_1314) @[el2_dec_dec_ctl.scala 154:130] - node _T_1365 = and(_T_1364, _T_1316) @[el2_dec_dec_ctl.scala 154:130] - node _T_1366 = and(_T_1365, _T_1317) @[el2_dec_dec_ctl.scala 154:130] - node _T_1367 = and(_T_1366, _T_1319) @[el2_dec_dec_ctl.scala 154:130] - node _T_1368 = and(_T_1367, _T_1321) @[el2_dec_dec_ctl.scala 154:130] - node _T_1369 = and(_T_1368, _T_1323) @[el2_dec_dec_ctl.scala 154:130] - node _T_1370 = and(_T_1369, _T_1325) @[el2_dec_dec_ctl.scala 154:130] - node _T_1371 = and(_T_1370, _T_1327) @[el2_dec_dec_ctl.scala 154:130] - node _T_1372 = and(_T_1371, _T_1328) @[el2_dec_dec_ctl.scala 154:130] - node _T_1373 = and(_T_1372, _T_1330) @[el2_dec_dec_ctl.scala 154:130] - node _T_1374 = and(_T_1373, _T_1331) @[el2_dec_dec_ctl.scala 154:130] - node _T_1375 = and(_T_1374, _T_1333) @[el2_dec_dec_ctl.scala 154:130] - node _T_1376 = and(_T_1375, _T_1335) @[el2_dec_dec_ctl.scala 154:130] - node _T_1377 = and(_T_1376, _T_1337) @[el2_dec_dec_ctl.scala 154:130] - node _T_1378 = and(_T_1377, _T_1339) @[el2_dec_dec_ctl.scala 154:130] - node _T_1379 = and(_T_1378, _T_1341) @[el2_dec_dec_ctl.scala 154:130] - node _T_1380 = and(_T_1379, _T_1343) @[el2_dec_dec_ctl.scala 154:130] - node _T_1381 = and(_T_1380, _T_1345) @[el2_dec_dec_ctl.scala 154:130] - node _T_1382 = and(_T_1381, _T_1347) @[el2_dec_dec_ctl.scala 154:130] - node _T_1383 = and(_T_1382, _T_1349) @[el2_dec_dec_ctl.scala 154:130] - node _T_1384 = and(_T_1383, _T_1351) @[el2_dec_dec_ctl.scala 154:130] - node _T_1385 = and(_T_1384, _T_1353) @[el2_dec_dec_ctl.scala 154:130] - node _T_1386 = and(_T_1385, _T_1354) @[el2_dec_dec_ctl.scala 154:130] - node _T_1387 = and(_T_1386, _T_1355) @[el2_dec_dec_ctl.scala 154:130] - node _T_1388 = and(_T_1387, _T_1356) @[el2_dec_dec_ctl.scala 154:130] - node _T_1389 = and(_T_1388, _T_1358) @[el2_dec_dec_ctl.scala 154:130] - node _T_1390 = and(_T_1389, _T_1360) @[el2_dec_dec_ctl.scala 154:130] - node _T_1391 = and(_T_1390, _T_1361) @[el2_dec_dec_ctl.scala 154:130] - node _T_1392 = and(_T_1391, _T_1363) @[el2_dec_dec_ctl.scala 154:130] - node _T_1393 = or(_T_1310, _T_1392) @[el2_dec_dec_ctl.scala 153:148] - node _T_1394 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1396 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1398 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1400 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1402 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1404 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1406 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1408 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1410 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1412 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1414 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1416 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1418 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1420 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1422 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1424 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1426 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1428 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1430 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1432 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1434 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1436 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1437 = eq(_T_1436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1438 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1439 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1440 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1442 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1444 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1445 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1447 = and(_T_1395, _T_1397) @[el2_dec_dec_ctl.scala 155:127] - node _T_1448 = and(_T_1447, _T_1399) @[el2_dec_dec_ctl.scala 155:127] - node _T_1449 = and(_T_1448, _T_1401) @[el2_dec_dec_ctl.scala 155:127] - node _T_1450 = and(_T_1449, _T_1403) @[el2_dec_dec_ctl.scala 155:127] - node _T_1451 = and(_T_1450, _T_1405) @[el2_dec_dec_ctl.scala 155:127] - node _T_1452 = and(_T_1451, _T_1407) @[el2_dec_dec_ctl.scala 155:127] - node _T_1453 = and(_T_1452, _T_1409) @[el2_dec_dec_ctl.scala 155:127] - node _T_1454 = and(_T_1453, _T_1411) @[el2_dec_dec_ctl.scala 155:127] - node _T_1455 = and(_T_1454, _T_1413) @[el2_dec_dec_ctl.scala 155:127] - node _T_1456 = and(_T_1455, _T_1415) @[el2_dec_dec_ctl.scala 155:127] - node _T_1457 = and(_T_1456, _T_1417) @[el2_dec_dec_ctl.scala 155:127] - node _T_1458 = and(_T_1457, _T_1419) @[el2_dec_dec_ctl.scala 155:127] - node _T_1459 = and(_T_1458, _T_1421) @[el2_dec_dec_ctl.scala 155:127] - node _T_1460 = and(_T_1459, _T_1423) @[el2_dec_dec_ctl.scala 155:127] - node _T_1461 = and(_T_1460, _T_1425) @[el2_dec_dec_ctl.scala 155:127] - node _T_1462 = and(_T_1461, _T_1427) @[el2_dec_dec_ctl.scala 155:127] - node _T_1463 = and(_T_1462, _T_1429) @[el2_dec_dec_ctl.scala 155:127] - node _T_1464 = and(_T_1463, _T_1431) @[el2_dec_dec_ctl.scala 155:127] - node _T_1465 = and(_T_1464, _T_1433) @[el2_dec_dec_ctl.scala 155:127] - node _T_1466 = and(_T_1465, _T_1435) @[el2_dec_dec_ctl.scala 155:127] - node _T_1467 = and(_T_1466, _T_1437) @[el2_dec_dec_ctl.scala 155:127] - node _T_1468 = and(_T_1467, _T_1438) @[el2_dec_dec_ctl.scala 155:127] - node _T_1469 = and(_T_1468, _T_1439) @[el2_dec_dec_ctl.scala 155:127] - node _T_1470 = and(_T_1469, _T_1441) @[el2_dec_dec_ctl.scala 155:127] - node _T_1471 = and(_T_1470, _T_1443) @[el2_dec_dec_ctl.scala 155:127] - node _T_1472 = and(_T_1471, _T_1444) @[el2_dec_dec_ctl.scala 155:127] - node _T_1473 = and(_T_1472, _T_1446) @[el2_dec_dec_ctl.scala 155:127] - node _T_1474 = or(_T_1393, _T_1473) @[el2_dec_dec_ctl.scala 154:134] - node _T_1475 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1477 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1479 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1481 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1483 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1485 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1486 = eq(_T_1485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1487 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1489 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1491 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1492 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1494 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1495 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1497 = and(_T_1476, _T_1478) @[el2_dec_dec_ctl.scala 156:68] - node _T_1498 = and(_T_1497, _T_1480) @[el2_dec_dec_ctl.scala 156:68] - node _T_1499 = and(_T_1498, _T_1482) @[el2_dec_dec_ctl.scala 156:68] - node _T_1500 = and(_T_1499, _T_1484) @[el2_dec_dec_ctl.scala 156:68] - node _T_1501 = and(_T_1500, _T_1486) @[el2_dec_dec_ctl.scala 156:68] - node _T_1502 = and(_T_1501, _T_1488) @[el2_dec_dec_ctl.scala 156:68] - node _T_1503 = and(_T_1502, _T_1490) @[el2_dec_dec_ctl.scala 156:68] - node _T_1504 = and(_T_1503, _T_1491) @[el2_dec_dec_ctl.scala 156:68] - node _T_1505 = and(_T_1504, _T_1493) @[el2_dec_dec_ctl.scala 156:68] - node _T_1506 = and(_T_1505, _T_1494) @[el2_dec_dec_ctl.scala 156:68] - node _T_1507 = and(_T_1506, _T_1496) @[el2_dec_dec_ctl.scala 156:68] - node _T_1508 = or(_T_1474, _T_1507) @[el2_dec_dec_ctl.scala 155:131] - node _T_1509 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1511 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1513 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1515 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1517 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1519 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1520 = eq(_T_1519, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1521 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1523 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1525 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1527 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1529 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1530 = eq(_T_1529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1531 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1532 = eq(_T_1531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1533 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1534 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1536 = and(_T_1510, _T_1512) @[el2_dec_dec_ctl.scala 157:77] - node _T_1537 = and(_T_1536, _T_1514) @[el2_dec_dec_ctl.scala 157:77] - node _T_1538 = and(_T_1537, _T_1516) @[el2_dec_dec_ctl.scala 157:77] - node _T_1539 = and(_T_1538, _T_1518) @[el2_dec_dec_ctl.scala 157:77] - node _T_1540 = and(_T_1539, _T_1520) @[el2_dec_dec_ctl.scala 157:77] - node _T_1541 = and(_T_1540, _T_1522) @[el2_dec_dec_ctl.scala 157:77] - node _T_1542 = and(_T_1541, _T_1524) @[el2_dec_dec_ctl.scala 157:77] - node _T_1543 = and(_T_1542, _T_1526) @[el2_dec_dec_ctl.scala 157:77] - node _T_1544 = and(_T_1543, _T_1528) @[el2_dec_dec_ctl.scala 157:77] - node _T_1545 = and(_T_1544, _T_1530) @[el2_dec_dec_ctl.scala 157:77] - node _T_1546 = and(_T_1545, _T_1532) @[el2_dec_dec_ctl.scala 157:77] - node _T_1547 = and(_T_1546, _T_1533) @[el2_dec_dec_ctl.scala 157:77] - node _T_1548 = and(_T_1547, _T_1535) @[el2_dec_dec_ctl.scala 157:77] - node _T_1549 = or(_T_1508, _T_1548) @[el2_dec_dec_ctl.scala 156:72] - node _T_1550 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1552 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1554 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1556 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1558 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1559 = eq(_T_1558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1560 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1562 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_1563 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1564 = eq(_T_1563, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1565 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_1566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1567 = eq(_T_1566, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1568 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1569 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1571 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1572 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1574 = and(_T_1551, _T_1553) @[el2_dec_dec_ctl.scala 158:74] - node _T_1575 = and(_T_1574, _T_1555) @[el2_dec_dec_ctl.scala 158:74] - node _T_1576 = and(_T_1575, _T_1557) @[el2_dec_dec_ctl.scala 158:74] - node _T_1577 = and(_T_1576, _T_1559) @[el2_dec_dec_ctl.scala 158:74] - node _T_1578 = and(_T_1577, _T_1561) @[el2_dec_dec_ctl.scala 158:74] - node _T_1579 = and(_T_1578, _T_1562) @[el2_dec_dec_ctl.scala 158:74] - node _T_1580 = and(_T_1579, _T_1564) @[el2_dec_dec_ctl.scala 158:74] - node _T_1581 = and(_T_1580, _T_1565) @[el2_dec_dec_ctl.scala 158:74] - node _T_1582 = and(_T_1581, _T_1567) @[el2_dec_dec_ctl.scala 158:74] - node _T_1583 = and(_T_1582, _T_1568) @[el2_dec_dec_ctl.scala 158:74] - node _T_1584 = and(_T_1583, _T_1570) @[el2_dec_dec_ctl.scala 158:74] - node _T_1585 = and(_T_1584, _T_1571) @[el2_dec_dec_ctl.scala 158:74] - node _T_1586 = and(_T_1585, _T_1573) @[el2_dec_dec_ctl.scala 158:74] - node _T_1587 = or(_T_1549, _T_1586) @[el2_dec_dec_ctl.scala 157:81] - node _T_1588 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1590 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1592 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1594 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1596 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1598 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1599 = eq(_T_1598, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1600 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1601 = eq(_T_1600, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1602 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1603 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1604 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1606 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1607 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1609 = and(_T_1589, _T_1591) @[el2_dec_dec_ctl.scala 159:66] - node _T_1610 = and(_T_1609, _T_1593) @[el2_dec_dec_ctl.scala 159:66] - node _T_1611 = and(_T_1610, _T_1595) @[el2_dec_dec_ctl.scala 159:66] - node _T_1612 = and(_T_1611, _T_1597) @[el2_dec_dec_ctl.scala 159:66] - node _T_1613 = and(_T_1612, _T_1599) @[el2_dec_dec_ctl.scala 159:66] - node _T_1614 = and(_T_1613, _T_1601) @[el2_dec_dec_ctl.scala 159:66] - node _T_1615 = and(_T_1614, _T_1602) @[el2_dec_dec_ctl.scala 159:66] - node _T_1616 = and(_T_1615, _T_1603) @[el2_dec_dec_ctl.scala 159:66] - node _T_1617 = and(_T_1616, _T_1605) @[el2_dec_dec_ctl.scala 159:66] - node _T_1618 = and(_T_1617, _T_1606) @[el2_dec_dec_ctl.scala 159:66] - node _T_1619 = and(_T_1618, _T_1608) @[el2_dec_dec_ctl.scala 159:66] - node _T_1620 = or(_T_1587, _T_1619) @[el2_dec_dec_ctl.scala 158:78] - node _T_1621 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1622 = eq(_T_1621, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1623 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1624 = eq(_T_1623, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1625 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1627 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1628 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1629 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1631 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1632 = eq(_T_1631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1633 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1634 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1636 = and(_T_1622, _T_1624) @[el2_dec_dec_ctl.scala 160:54] - node _T_1637 = and(_T_1636, _T_1626) @[el2_dec_dec_ctl.scala 160:54] - node _T_1638 = and(_T_1637, _T_1627) @[el2_dec_dec_ctl.scala 160:54] - node _T_1639 = and(_T_1638, _T_1628) @[el2_dec_dec_ctl.scala 160:54] - node _T_1640 = and(_T_1639, _T_1630) @[el2_dec_dec_ctl.scala 160:54] - node _T_1641 = and(_T_1640, _T_1632) @[el2_dec_dec_ctl.scala 160:54] - node _T_1642 = and(_T_1641, _T_1633) @[el2_dec_dec_ctl.scala 160:54] - node _T_1643 = and(_T_1642, _T_1635) @[el2_dec_dec_ctl.scala 160:54] - node _T_1644 = or(_T_1620, _T_1643) @[el2_dec_dec_ctl.scala 159:70] - node _T_1645 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_1646 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1647 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1648 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1650 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1652 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1653 = eq(_T_1652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1654 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1655 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1656 = eq(_T_1655, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1657 = and(_T_1645, _T_1646) @[el2_dec_dec_ctl.scala 161:48] - node _T_1658 = and(_T_1657, _T_1647) @[el2_dec_dec_ctl.scala 161:48] - node _T_1659 = and(_T_1658, _T_1649) @[el2_dec_dec_ctl.scala 161:48] - node _T_1660 = and(_T_1659, _T_1651) @[el2_dec_dec_ctl.scala 161:48] - node _T_1661 = and(_T_1660, _T_1653) @[el2_dec_dec_ctl.scala 161:48] - node _T_1662 = and(_T_1661, _T_1654) @[el2_dec_dec_ctl.scala 161:48] - node _T_1663 = and(_T_1662, _T_1656) @[el2_dec_dec_ctl.scala 161:48] - node _T_1664 = or(_T_1644, _T_1663) @[el2_dec_dec_ctl.scala 160:58] - node _T_1665 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1666 = eq(_T_1665, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1668 = eq(_T_1667, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1669 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1672 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1673 = eq(_T_1672, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1674 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1675 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1677 = and(_T_1666, _T_1668) @[el2_dec_dec_ctl.scala 162:47] - node _T_1678 = and(_T_1677, _T_1670) @[el2_dec_dec_ctl.scala 162:47] - node _T_1679 = and(_T_1678, _T_1671) @[el2_dec_dec_ctl.scala 162:47] - node _T_1680 = and(_T_1679, _T_1673) @[el2_dec_dec_ctl.scala 162:47] - node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 162:47] - node _T_1682 = and(_T_1681, _T_1676) @[el2_dec_dec_ctl.scala 162:47] - node _T_1683 = or(_T_1664, _T_1682) @[el2_dec_dec_ctl.scala 161:52] - node _T_1684 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1685 = eq(_T_1684, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1686 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1688 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1691 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1693 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1695 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1696 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1697 = eq(_T_1696, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1698 = and(_T_1685, _T_1687) @[el2_dec_dec_ctl.scala 162:99] - node _T_1699 = and(_T_1698, _T_1688) @[el2_dec_dec_ctl.scala 162:99] - node _T_1700 = and(_T_1699, _T_1690) @[el2_dec_dec_ctl.scala 162:99] - node _T_1701 = and(_T_1700, _T_1692) @[el2_dec_dec_ctl.scala 162:99] - node _T_1702 = and(_T_1701, _T_1694) @[el2_dec_dec_ctl.scala 162:99] - node _T_1703 = and(_T_1702, _T_1695) @[el2_dec_dec_ctl.scala 162:99] - node _T_1704 = and(_T_1703, _T_1697) @[el2_dec_dec_ctl.scala 162:99] - node _T_1705 = or(_T_1683, _T_1704) @[el2_dec_dec_ctl.scala 162:51] - node _T_1706 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_1707 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1708 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1709 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1710 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1711 = eq(_T_1710, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1712 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1714 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1715 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1717 = and(_T_1706, _T_1707) @[el2_dec_dec_ctl.scala 163:47] - node _T_1718 = and(_T_1717, _T_1708) @[el2_dec_dec_ctl.scala 163:47] - node _T_1719 = and(_T_1718, _T_1709) @[el2_dec_dec_ctl.scala 163:47] - node _T_1720 = and(_T_1719, _T_1711) @[el2_dec_dec_ctl.scala 163:47] - node _T_1721 = and(_T_1720, _T_1713) @[el2_dec_dec_ctl.scala 163:47] - node _T_1722 = and(_T_1721, _T_1714) @[el2_dec_dec_ctl.scala 163:47] - node _T_1723 = and(_T_1722, _T_1716) @[el2_dec_dec_ctl.scala 163:47] - node _T_1724 = or(_T_1705, _T_1723) @[el2_dec_dec_ctl.scala 162:103] - node _T_1725 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1727 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1729 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1731 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1733 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1735 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1737 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1739 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1741 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1743 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1745 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1747 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] - node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1749 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1751 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1753 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1755 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1757 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1759 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1761 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1762 = eq(_T_1761, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1763 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1764 = eq(_T_1763, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1765 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1767 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1768 = eq(_T_1767, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1769 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1770 = eq(_T_1769, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1771 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1773 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1775 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1777 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1778 = eq(_T_1777, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1779 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1781 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1782 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1783 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1784 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1785 = eq(_T_1784, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1786 = and(_T_1726, _T_1728) @[el2_dec_dec_ctl.scala 164:142] - node _T_1787 = and(_T_1786, _T_1730) @[el2_dec_dec_ctl.scala 164:142] - node _T_1788 = and(_T_1787, _T_1732) @[el2_dec_dec_ctl.scala 164:142] - node _T_1789 = and(_T_1788, _T_1734) @[el2_dec_dec_ctl.scala 164:142] - node _T_1790 = and(_T_1789, _T_1736) @[el2_dec_dec_ctl.scala 164:142] - node _T_1791 = and(_T_1790, _T_1738) @[el2_dec_dec_ctl.scala 164:142] - node _T_1792 = and(_T_1791, _T_1740) @[el2_dec_dec_ctl.scala 164:142] - node _T_1793 = and(_T_1792, _T_1742) @[el2_dec_dec_ctl.scala 164:142] - node _T_1794 = and(_T_1793, _T_1744) @[el2_dec_dec_ctl.scala 164:142] - node _T_1795 = and(_T_1794, _T_1746) @[el2_dec_dec_ctl.scala 164:142] - node _T_1796 = and(_T_1795, _T_1748) @[el2_dec_dec_ctl.scala 164:142] - node _T_1797 = and(_T_1796, _T_1750) @[el2_dec_dec_ctl.scala 164:142] - node _T_1798 = and(_T_1797, _T_1752) @[el2_dec_dec_ctl.scala 164:142] - node _T_1799 = and(_T_1798, _T_1754) @[el2_dec_dec_ctl.scala 164:142] - node _T_1800 = and(_T_1799, _T_1756) @[el2_dec_dec_ctl.scala 164:142] - node _T_1801 = and(_T_1800, _T_1758) @[el2_dec_dec_ctl.scala 164:142] - node _T_1802 = and(_T_1801, _T_1760) @[el2_dec_dec_ctl.scala 164:142] - node _T_1803 = and(_T_1802, _T_1762) @[el2_dec_dec_ctl.scala 164:142] - node _T_1804 = and(_T_1803, _T_1764) @[el2_dec_dec_ctl.scala 164:142] - node _T_1805 = and(_T_1804, _T_1766) @[el2_dec_dec_ctl.scala 164:142] - node _T_1806 = and(_T_1805, _T_1768) @[el2_dec_dec_ctl.scala 164:142] - node _T_1807 = and(_T_1806, _T_1770) @[el2_dec_dec_ctl.scala 164:142] - node _T_1808 = and(_T_1807, _T_1772) @[el2_dec_dec_ctl.scala 164:142] - node _T_1809 = and(_T_1808, _T_1774) @[el2_dec_dec_ctl.scala 164:142] - node _T_1810 = and(_T_1809, _T_1776) @[el2_dec_dec_ctl.scala 164:142] - node _T_1811 = and(_T_1810, _T_1778) @[el2_dec_dec_ctl.scala 164:142] - node _T_1812 = and(_T_1811, _T_1780) @[el2_dec_dec_ctl.scala 164:142] - node _T_1813 = and(_T_1812, _T_1781) @[el2_dec_dec_ctl.scala 164:142] - node _T_1814 = and(_T_1813, _T_1782) @[el2_dec_dec_ctl.scala 164:142] - node _T_1815 = and(_T_1814, _T_1783) @[el2_dec_dec_ctl.scala 164:142] - node _T_1816 = and(_T_1815, _T_1785) @[el2_dec_dec_ctl.scala 164:142] - node _T_1817 = or(_T_1724, _T_1816) @[el2_dec_dec_ctl.scala 163:51] - node _T_1818 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1820 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1822 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1824 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1826 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1828 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1830 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1832 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1833 = eq(_T_1832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1834 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1835 = eq(_T_1834, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1836 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1837 = eq(_T_1836, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1838 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1839 = eq(_T_1838, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1840 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1841 = eq(_T_1840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1842 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1843 = eq(_T_1842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1844 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1846 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1848 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1849 = eq(_T_1848, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1850 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1851 = eq(_T_1850, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1852 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1854 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1855 = eq(_T_1854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1856 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1857 = eq(_T_1856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1858 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1859 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1860 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1861 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1863 = and(_T_1819, _T_1821) @[el2_dec_dec_ctl.scala 165:110] - node _T_1864 = and(_T_1863, _T_1823) @[el2_dec_dec_ctl.scala 165:110] - node _T_1865 = and(_T_1864, _T_1825) @[el2_dec_dec_ctl.scala 165:110] - node _T_1866 = and(_T_1865, _T_1827) @[el2_dec_dec_ctl.scala 165:110] - node _T_1867 = and(_T_1866, _T_1829) @[el2_dec_dec_ctl.scala 165:110] - node _T_1868 = and(_T_1867, _T_1831) @[el2_dec_dec_ctl.scala 165:110] - node _T_1869 = and(_T_1868, _T_1833) @[el2_dec_dec_ctl.scala 165:110] - node _T_1870 = and(_T_1869, _T_1835) @[el2_dec_dec_ctl.scala 165:110] - node _T_1871 = and(_T_1870, _T_1837) @[el2_dec_dec_ctl.scala 165:110] - node _T_1872 = and(_T_1871, _T_1839) @[el2_dec_dec_ctl.scala 165:110] - node _T_1873 = and(_T_1872, _T_1841) @[el2_dec_dec_ctl.scala 165:110] - node _T_1874 = and(_T_1873, _T_1843) @[el2_dec_dec_ctl.scala 165:110] - node _T_1875 = and(_T_1874, _T_1845) @[el2_dec_dec_ctl.scala 165:110] - node _T_1876 = and(_T_1875, _T_1847) @[el2_dec_dec_ctl.scala 165:110] - node _T_1877 = and(_T_1876, _T_1849) @[el2_dec_dec_ctl.scala 165:110] - node _T_1878 = and(_T_1877, _T_1851) @[el2_dec_dec_ctl.scala 165:110] - node _T_1879 = and(_T_1878, _T_1853) @[el2_dec_dec_ctl.scala 165:110] - node _T_1880 = and(_T_1879, _T_1855) @[el2_dec_dec_ctl.scala 165:110] - node _T_1881 = and(_T_1880, _T_1857) @[el2_dec_dec_ctl.scala 165:110] - node _T_1882 = and(_T_1881, _T_1858) @[el2_dec_dec_ctl.scala 165:110] - node _T_1883 = and(_T_1882, _T_1859) @[el2_dec_dec_ctl.scala 165:110] - node _T_1884 = and(_T_1883, _T_1860) @[el2_dec_dec_ctl.scala 165:110] - node _T_1885 = and(_T_1884, _T_1862) @[el2_dec_dec_ctl.scala 165:110] - node _T_1886 = or(_T_1817, _T_1885) @[el2_dec_dec_ctl.scala 164:146] - node _T_1887 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1888 = eq(_T_1887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1889 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1891 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1892 = eq(_T_1891, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1893 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1895 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1897 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1898 = eq(_T_1897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1899 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1900 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1902 = and(_T_1888, _T_1890) @[el2_dec_dec_ctl.scala 166:51] - node _T_1903 = and(_T_1902, _T_1892) @[el2_dec_dec_ctl.scala 166:51] - node _T_1904 = and(_T_1903, _T_1894) @[el2_dec_dec_ctl.scala 166:51] - node _T_1905 = and(_T_1904, _T_1896) @[el2_dec_dec_ctl.scala 166:51] - node _T_1906 = and(_T_1905, _T_1898) @[el2_dec_dec_ctl.scala 166:51] - node _T_1907 = and(_T_1906, _T_1899) @[el2_dec_dec_ctl.scala 166:51] - node _T_1908 = and(_T_1907, _T_1901) @[el2_dec_dec_ctl.scala 166:51] - node _T_1909 = or(_T_1886, _T_1908) @[el2_dec_dec_ctl.scala 165:114] - node _T_1910 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1911 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1912 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1914 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1915 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1916 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1917 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1919 = and(_T_1910, _T_1911) @[el2_dec_dec_ctl.scala 166:95] - node _T_1920 = and(_T_1919, _T_1913) @[el2_dec_dec_ctl.scala 166:95] - node _T_1921 = and(_T_1920, _T_1914) @[el2_dec_dec_ctl.scala 166:95] - node _T_1922 = and(_T_1921, _T_1915) @[el2_dec_dec_ctl.scala 166:95] - node _T_1923 = and(_T_1922, _T_1916) @[el2_dec_dec_ctl.scala 166:95] - node _T_1924 = and(_T_1923, _T_1918) @[el2_dec_dec_ctl.scala 166:95] - node _T_1925 = or(_T_1909, _T_1924) @[el2_dec_dec_ctl.scala 166:55] - node _T_1926 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1927 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1928 = eq(_T_1927, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1929 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1930 = eq(_T_1929, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1931 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1932 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1934 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1935 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1937 = and(_T_1926, _T_1928) @[el2_dec_dec_ctl.scala 167:46] - node _T_1938 = and(_T_1937, _T_1930) @[el2_dec_dec_ctl.scala 167:46] - node _T_1939 = and(_T_1938, _T_1931) @[el2_dec_dec_ctl.scala 167:46] - node _T_1940 = and(_T_1939, _T_1933) @[el2_dec_dec_ctl.scala 167:46] - node _T_1941 = and(_T_1940, _T_1934) @[el2_dec_dec_ctl.scala 167:46] - node _T_1942 = and(_T_1941, _T_1936) @[el2_dec_dec_ctl.scala 167:46] - node _T_1943 = or(_T_1925, _T_1942) @[el2_dec_dec_ctl.scala 166:99] - node _T_1944 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1946 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1947 = eq(_T_1946, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1948 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1949 = eq(_T_1948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1950 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1952 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1954 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1956 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1957 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1959 = and(_T_1945, _T_1947) @[el2_dec_dec_ctl.scala 167:99] - node _T_1960 = and(_T_1959, _T_1949) @[el2_dec_dec_ctl.scala 167:99] - node _T_1961 = and(_T_1960, _T_1951) @[el2_dec_dec_ctl.scala 167:99] - node _T_1962 = and(_T_1961, _T_1953) @[el2_dec_dec_ctl.scala 167:99] - node _T_1963 = and(_T_1962, _T_1955) @[el2_dec_dec_ctl.scala 167:99] - node _T_1964 = and(_T_1963, _T_1956) @[el2_dec_dec_ctl.scala 167:99] - node _T_1965 = and(_T_1964, _T_1958) @[el2_dec_dec_ctl.scala 167:99] - node _T_1966 = or(_T_1943, _T_1965) @[el2_dec_dec_ctl.scala 167:50] - node _T_1967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1974 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1975 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1976 = eq(_T_1975, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1977 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:43] - node _T_1978 = and(_T_1977, _T_1971) @[el2_dec_dec_ctl.scala 168:43] - node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:43] - node _T_1980 = and(_T_1979, _T_1974) @[el2_dec_dec_ctl.scala 168:43] - node _T_1981 = and(_T_1980, _T_1976) @[el2_dec_dec_ctl.scala 168:43] - node _T_1982 = or(_T_1966, _T_1981) @[el2_dec_dec_ctl.scala 167:103] - io.out.legal <= _T_1982 @[el2_dec_dec_ctl.scala 153:16] + node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 20:23] + node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 20:35] + node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 20:27] + node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 20:49] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 20:42] + node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 20:60] + node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 20:53] + node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 20:39] + node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 20:75] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 20:68] + node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 20:85] + node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 20:78] + node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 20:65] + io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 20:14] + node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 17:17] + node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 17:17] + node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 17:17] + node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 17:17] + node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 21:43] + node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 17:17] + node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 17:17] + node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 21:70] + node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 17:17] + node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 17:17] + node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 22:29] + node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_45 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_46 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_48 = and(_T_44, _T_45) @[el2_dec_dec_ctl.scala 17:17] + node _T_49 = and(_T_48, _T_47) @[el2_dec_dec_ctl.scala 17:17] + node _T_50 = or(_T_43, _T_49) @[el2_dec_dec_ctl.scala 22:56] + node _T_51 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_53 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_54 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_56 = and(_T_52, _T_53) @[el2_dec_dec_ctl.scala 17:17] + node _T_57 = and(_T_56, _T_55) @[el2_dec_dec_ctl.scala 17:17] + node _T_58 = or(_T_50, _T_57) @[el2_dec_dec_ctl.scala 23:29] + node _T_59 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_60 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_61 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_63 = and(_T_59, _T_60) @[el2_dec_dec_ctl.scala 17:17] + node _T_64 = and(_T_63, _T_62) @[el2_dec_dec_ctl.scala 17:17] + node _T_65 = or(_T_58, _T_64) @[el2_dec_dec_ctl.scala 23:55] + node _T_66 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_68 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_69 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_70 = eq(_T_69, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_71 = and(_T_67, _T_68) @[el2_dec_dec_ctl.scala 17:17] + node _T_72 = and(_T_71, _T_70) @[el2_dec_dec_ctl.scala 17:17] + node _T_73 = or(_T_65, _T_72) @[el2_dec_dec_ctl.scala 24:29] + node _T_74 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_75 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_76 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_77 = eq(_T_76, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_78 = and(_T_74, _T_75) @[el2_dec_dec_ctl.scala 17:17] + node _T_79 = and(_T_78, _T_77) @[el2_dec_dec_ctl.scala 17:17] + node _T_80 = or(_T_73, _T_79) @[el2_dec_dec_ctl.scala 24:55] + node _T_81 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_83 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_84 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_86 = and(_T_82, _T_83) @[el2_dec_dec_ctl.scala 17:17] + node _T_87 = and(_T_86, _T_85) @[el2_dec_dec_ctl.scala 17:17] + node _T_88 = or(_T_80, _T_87) @[el2_dec_dec_ctl.scala 25:29] + node _T_89 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_90 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_91 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_93 = and(_T_89, _T_90) @[el2_dec_dec_ctl.scala 17:17] + node _T_94 = and(_T_93, _T_92) @[el2_dec_dec_ctl.scala 17:17] + node _T_95 = or(_T_88, _T_94) @[el2_dec_dec_ctl.scala 25:55] + node _T_96 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_97 = eq(_T_96, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_98 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_99 = eq(_T_98, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_100 = and(_T_97, _T_99) @[el2_dec_dec_ctl.scala 17:17] + node _T_101 = or(_T_95, _T_100) @[el2_dec_dec_ctl.scala 26:29] + node _T_102 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_104 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_105 = eq(_T_104, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_106 = and(_T_103, _T_105) @[el2_dec_dec_ctl.scala 17:17] + node _T_107 = or(_T_101, _T_106) @[el2_dec_dec_ctl.scala 26:51] + io.out.rs1 <= _T_107 @[el2_dec_dec_ctl.scala 21:14] + node _T_108 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_109 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_111 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_113 = and(_T_108, _T_110) @[el2_dec_dec_ctl.scala 17:17] + node _T_114 = and(_T_113, _T_112) @[el2_dec_dec_ctl.scala 17:17] + node _T_115 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_117 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_118 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_119 = eq(_T_118, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_120 = and(_T_116, _T_117) @[el2_dec_dec_ctl.scala 17:17] + node _T_121 = and(_T_120, _T_119) @[el2_dec_dec_ctl.scala 17:17] + node _T_122 = or(_T_114, _T_121) @[el2_dec_dec_ctl.scala 27:40] + io.out.rs2 <= _T_122 @[el2_dec_dec_ctl.scala 27:14] + node _T_123 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_125 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_127 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_128 = and(_T_124, _T_126) @[el2_dec_dec_ctl.scala 17:17] + node _T_129 = and(_T_128, _T_127) @[el2_dec_dec_ctl.scala 17:17] + node _T_130 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_131 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_133 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_134 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_136 = and(_T_130, _T_132) @[el2_dec_dec_ctl.scala 17:17] + node _T_137 = and(_T_136, _T_133) @[el2_dec_dec_ctl.scala 17:17] + node _T_138 = and(_T_137, _T_135) @[el2_dec_dec_ctl.scala 17:17] + node _T_139 = or(_T_129, _T_138) @[el2_dec_dec_ctl.scala 28:42] + node _T_140 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_142 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_143 = eq(_T_142, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_144 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_145 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_146 = and(_T_141, _T_143) @[el2_dec_dec_ctl.scala 17:17] + node _T_147 = and(_T_146, _T_144) @[el2_dec_dec_ctl.scala 17:17] + node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 17:17] + node _T_149 = or(_T_139, _T_148) @[el2_dec_dec_ctl.scala 28:70] + node _T_150 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_152 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_154 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_155 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_156 = eq(_T_155, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_157 = and(_T_151, _T_153) @[el2_dec_dec_ctl.scala 17:17] + node _T_158 = and(_T_157, _T_154) @[el2_dec_dec_ctl.scala 17:17] + node _T_159 = and(_T_158, _T_156) @[el2_dec_dec_ctl.scala 17:17] + node _T_160 = or(_T_149, _T_159) @[el2_dec_dec_ctl.scala 29:32] + io.out.imm12 <= _T_160 @[el2_dec_dec_ctl.scala 28:16] + node _T_161 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 30:24] + node _T_162 = eq(_T_161, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 30:17] + node _T_163 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 30:37] + node _T_164 = eq(_T_163, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 30:30] + node _T_165 = and(_T_162, _T_164) @[el2_dec_dec_ctl.scala 30:28] + node _T_166 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 30:51] + node _T_167 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 30:63] + node _T_168 = and(_T_166, _T_167) @[el2_dec_dec_ctl.scala 30:55] + node _T_169 = or(_T_165, _T_168) @[el2_dec_dec_ctl.scala 30:42] + node _T_170 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 30:76] + node _T_171 = or(_T_169, _T_170) @[el2_dec_dec_ctl.scala 30:68] + io.out.rd <= _T_171 @[el2_dec_dec_ctl.scala 30:13] + node _T_172 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_173 = eq(_T_172, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_174 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_175 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_177 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_178 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_180 = and(_T_173, _T_174) @[el2_dec_dec_ctl.scala 17:17] + node _T_181 = and(_T_180, _T_176) @[el2_dec_dec_ctl.scala 17:17] + node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 17:17] + node _T_183 = and(_T_182, _T_179) @[el2_dec_dec_ctl.scala 17:17] + io.out.shimm5 <= _T_183 @[el2_dec_dec_ctl.scala 31:17] + node _T_184 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 32:26] + node _T_185 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 32:36] + node _T_186 = and(_T_184, _T_185) @[el2_dec_dec_ctl.scala 32:29] + node _T_187 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 32:50] + node _T_188 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 32:60] + node _T_189 = and(_T_187, _T_188) @[el2_dec_dec_ctl.scala 32:53] + node _T_190 = or(_T_186, _T_189) @[el2_dec_dec_ctl.scala 32:41] + io.out.imm20 <= _T_190 @[el2_dec_dec_ctl.scala 32:16] + node _T_191 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 33:24] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 33:17] + node _T_193 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 33:37] + node _T_194 = eq(_T_193, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 33:30] + node _T_195 = and(_T_192, _T_194) @[el2_dec_dec_ctl.scala 33:28] + node _T_196 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 33:49] + node _T_197 = and(_T_195, _T_196) @[el2_dec_dec_ctl.scala 33:41] + node _T_198 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 33:63] + node _T_199 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 33:75] + node _T_200 = and(_T_198, _T_199) @[el2_dec_dec_ctl.scala 33:67] + node _T_201 = or(_T_197, _T_200) @[el2_dec_dec_ctl.scala 33:54] + io.out.pc <= _T_201 @[el2_dec_dec_ctl.scala 33:13] + node _T_202 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_203 = eq(_T_202, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_204 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_206 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_208 = and(_T_203, _T_205) @[el2_dec_dec_ctl.scala 17:17] + node _T_209 = and(_T_208, _T_207) @[el2_dec_dec_ctl.scala 17:17] + io.out.load <= _T_209 @[el2_dec_dec_ctl.scala 34:15] + node _T_210 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_212 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_213 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_215 = and(_T_211, _T_212) @[el2_dec_dec_ctl.scala 17:17] + node _T_216 = and(_T_215, _T_214) @[el2_dec_dec_ctl.scala 17:17] + io.out.store <= _T_216 @[el2_dec_dec_ctl.scala 35:16] + node _T_217 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_218 = eq(_T_217, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_219 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_221 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_222 = eq(_T_221, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_223 = and(_T_218, _T_220) @[el2_dec_dec_ctl.scala 17:17] + node _T_224 = and(_T_223, _T_222) @[el2_dec_dec_ctl.scala 17:17] + io.out.lsu <= _T_224 @[el2_dec_dec_ctl.scala 36:14] + node _T_225 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_227 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_229 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_231 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_232 = eq(_T_231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_233 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_234 = and(_T_226, _T_228) @[el2_dec_dec_ctl.scala 17:17] + node _T_235 = and(_T_234, _T_230) @[el2_dec_dec_ctl.scala 17:17] + node _T_236 = and(_T_235, _T_232) @[el2_dec_dec_ctl.scala 17:17] + node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 17:17] + node _T_238 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_240 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_242 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_243 = and(_T_239, _T_241) @[el2_dec_dec_ctl.scala 17:17] + node _T_244 = and(_T_243, _T_242) @[el2_dec_dec_ctl.scala 17:17] + node _T_245 = or(_T_237, _T_244) @[el2_dec_dec_ctl.scala 37:49] + node _T_246 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_247 = eq(_T_246, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_248 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_250 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_251 = eq(_T_250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_252 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_254 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_256 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_258 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_259 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_261 = and(_T_247, _T_249) @[el2_dec_dec_ctl.scala 17:17] + node _T_262 = and(_T_261, _T_251) @[el2_dec_dec_ctl.scala 17:17] + node _T_263 = and(_T_262, _T_253) @[el2_dec_dec_ctl.scala 17:17] + node _T_264 = and(_T_263, _T_255) @[el2_dec_dec_ctl.scala 17:17] + node _T_265 = and(_T_264, _T_257) @[el2_dec_dec_ctl.scala 17:17] + node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 17:17] + node _T_267 = and(_T_266, _T_260) @[el2_dec_dec_ctl.scala 17:17] + node _T_268 = or(_T_245, _T_267) @[el2_dec_dec_ctl.scala 37:74] + io.out.add <= _T_268 @[el2_dec_dec_ctl.scala 37:14] + node _T_269 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:34] + node _T_270 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_274 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_275 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_276 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_278 = and(_T_269, _T_271) @[el2_dec_dec_ctl.scala 17:17] + node _T_279 = and(_T_278, _T_273) @[el2_dec_dec_ctl.scala 17:17] + node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 17:17] + node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 17:17] + node _T_282 = and(_T_281, _T_277) @[el2_dec_dec_ctl.scala 17:17] + node _T_283 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_285 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_286 = eq(_T_285, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_287 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_288 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_290 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_291 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_293 = and(_T_284, _T_286) @[el2_dec_dec_ctl.scala 17:17] + node _T_294 = and(_T_293, _T_287) @[el2_dec_dec_ctl.scala 17:17] + node _T_295 = and(_T_294, _T_289) @[el2_dec_dec_ctl.scala 17:17] + node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 17:17] + node _T_297 = and(_T_296, _T_292) @[el2_dec_dec_ctl.scala 17:17] + node _T_298 = or(_T_282, _T_297) @[el2_dec_dec_ctl.scala 39:49] + node _T_299 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_300 = eq(_T_299, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_301 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_302 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_304 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_305 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_307 = and(_T_300, _T_301) @[el2_dec_dec_ctl.scala 17:17] + node _T_308 = and(_T_307, _T_303) @[el2_dec_dec_ctl.scala 17:17] + node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 17:17] + node _T_310 = and(_T_309, _T_306) @[el2_dec_dec_ctl.scala 17:17] + node _T_311 = or(_T_298, _T_310) @[el2_dec_dec_ctl.scala 39:85] + node _T_312 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_313 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_315 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_316 = eq(_T_315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_317 = and(_T_312, _T_314) @[el2_dec_dec_ctl.scala 17:17] + node _T_318 = and(_T_317, _T_316) @[el2_dec_dec_ctl.scala 17:17] + node _T_319 = or(_T_311, _T_318) @[el2_dec_dec_ctl.scala 40:35] + io.out.sub <= _T_319 @[el2_dec_dec_ctl.scala 39:14] + node _T_320 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_321 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_322 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_323 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_324 = eq(_T_323, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_325 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_326 = eq(_T_325, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_327 = and(_T_320, _T_321) @[el2_dec_dec_ctl.scala 17:17] + node _T_328 = and(_T_327, _T_322) @[el2_dec_dec_ctl.scala 17:17] + node _T_329 = and(_T_328, _T_324) @[el2_dec_dec_ctl.scala 17:17] + node _T_330 = and(_T_329, _T_326) @[el2_dec_dec_ctl.scala 17:17] + node _T_331 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_332 = eq(_T_331, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_333 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_334 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_335 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_336 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_337 = eq(_T_336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_338 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_340 = and(_T_332, _T_333) @[el2_dec_dec_ctl.scala 17:17] + node _T_341 = and(_T_340, _T_334) @[el2_dec_dec_ctl.scala 17:17] + node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 17:17] + node _T_343 = and(_T_342, _T_337) @[el2_dec_dec_ctl.scala 17:17] + node _T_344 = and(_T_343, _T_339) @[el2_dec_dec_ctl.scala 17:17] + node _T_345 = or(_T_330, _T_344) @[el2_dec_dec_ctl.scala 41:48] + io.out.land <= _T_345 @[el2_dec_dec_ctl.scala 41:15] + node _T_346 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_347 = eq(_T_346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_348 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_349 = and(_T_347, _T_348) @[el2_dec_dec_ctl.scala 17:17] + node _T_350 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_351 = eq(_T_350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_352 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_353 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_354 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_356 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_358 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_360 = and(_T_351, _T_352) @[el2_dec_dec_ctl.scala 17:17] + node _T_361 = and(_T_360, _T_353) @[el2_dec_dec_ctl.scala 17:17] + node _T_362 = and(_T_361, _T_355) @[el2_dec_dec_ctl.scala 17:17] + node _T_363 = and(_T_362, _T_357) @[el2_dec_dec_ctl.scala 17:17] + node _T_364 = and(_T_363, _T_359) @[el2_dec_dec_ctl.scala 17:17] + node _T_365 = or(_T_349, _T_364) @[el2_dec_dec_ctl.scala 42:37] + node _T_366 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_367 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_368 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_369 = and(_T_366, _T_367) @[el2_dec_dec_ctl.scala 17:17] + node _T_370 = and(_T_369, _T_368) @[el2_dec_dec_ctl.scala 17:17] + node _T_371 = or(_T_365, _T_370) @[el2_dec_dec_ctl.scala 42:74] + node _T_372 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_374 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_376 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_377 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_378 = and(_T_373, _T_375) @[el2_dec_dec_ctl.scala 17:17] + node _T_379 = and(_T_378, _T_376) @[el2_dec_dec_ctl.scala 17:17] + node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 17:17] + node _T_381 = or(_T_371, _T_380) @[el2_dec_dec_ctl.scala 43:26] + node _T_382 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_383 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_384 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_385 = eq(_T_384, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_386 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_388 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_390 = and(_T_382, _T_383) @[el2_dec_dec_ctl.scala 17:17] + node _T_391 = and(_T_390, _T_385) @[el2_dec_dec_ctl.scala 17:17] + node _T_392 = and(_T_391, _T_387) @[el2_dec_dec_ctl.scala 17:17] + node _T_393 = and(_T_392, _T_389) @[el2_dec_dec_ctl.scala 17:17] + node _T_394 = or(_T_381, _T_393) @[el2_dec_dec_ctl.scala 43:55] + io.out.lor <= _T_394 @[el2_dec_dec_ctl.scala 42:14] + node _T_395 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_397 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_398 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_399 = eq(_T_398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_400 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_401 = eq(_T_400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_402 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_403 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_405 = and(_T_396, _T_397) @[el2_dec_dec_ctl.scala 17:17] + node _T_406 = and(_T_405, _T_399) @[el2_dec_dec_ctl.scala 17:17] + node _T_407 = and(_T_406, _T_401) @[el2_dec_dec_ctl.scala 17:17] + node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 17:17] + node _T_409 = and(_T_408, _T_404) @[el2_dec_dec_ctl.scala 17:17] + node _T_410 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_411 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_412 = eq(_T_411, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_413 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_414 = eq(_T_413, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_415 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_417 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_418 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_420 = and(_T_410, _T_412) @[el2_dec_dec_ctl.scala 17:17] + node _T_421 = and(_T_420, _T_414) @[el2_dec_dec_ctl.scala 17:17] + node _T_422 = and(_T_421, _T_416) @[el2_dec_dec_ctl.scala 17:17] + node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 17:17] + node _T_424 = and(_T_423, _T_419) @[el2_dec_dec_ctl.scala 17:17] + node _T_425 = or(_T_409, _T_424) @[el2_dec_dec_ctl.scala 45:53] + io.out.lxor <= _T_425 @[el2_dec_dec_ctl.scala 45:15] + node _T_426 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_428 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_430 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_431 = eq(_T_430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_432 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_433 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_434 = eq(_T_433, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_435 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_436 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_438 = and(_T_427, _T_429) @[el2_dec_dec_ctl.scala 17:17] + node _T_439 = and(_T_438, _T_431) @[el2_dec_dec_ctl.scala 17:17] + node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 17:17] + node _T_441 = and(_T_440, _T_434) @[el2_dec_dec_ctl.scala 17:17] + node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 17:17] + node _T_443 = and(_T_442, _T_437) @[el2_dec_dec_ctl.scala 17:17] + io.out.sll <= _T_443 @[el2_dec_dec_ctl.scala 46:14] + node _T_444 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:34] + node _T_445 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_447 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_448 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_449 = eq(_T_448, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_450 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_451 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_453 = and(_T_444, _T_446) @[el2_dec_dec_ctl.scala 17:17] + node _T_454 = and(_T_453, _T_447) @[el2_dec_dec_ctl.scala 17:17] + node _T_455 = and(_T_454, _T_449) @[el2_dec_dec_ctl.scala 17:17] + node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 17:17] + node _T_457 = and(_T_456, _T_452) @[el2_dec_dec_ctl.scala 17:17] + io.out.sra <= _T_457 @[el2_dec_dec_ctl.scala 47:14] + node _T_458 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_460 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_461 = eq(_T_460, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_462 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_463 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_464 = eq(_T_463, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_465 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_466 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_468 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_469 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_471 = and(_T_459, _T_461) @[el2_dec_dec_ctl.scala 17:17] + node _T_472 = and(_T_471, _T_462) @[el2_dec_dec_ctl.scala 17:17] + node _T_473 = and(_T_472, _T_464) @[el2_dec_dec_ctl.scala 17:17] + node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 17:17] + node _T_475 = and(_T_474, _T_467) @[el2_dec_dec_ctl.scala 17:17] + node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 17:17] + node _T_477 = and(_T_476, _T_470) @[el2_dec_dec_ctl.scala 17:17] + io.out.srl <= _T_477 @[el2_dec_dec_ctl.scala 48:14] + node _T_478 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_479 = eq(_T_478, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_480 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_482 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_483 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_485 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_486 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_487 = eq(_T_486, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_488 = and(_T_479, _T_481) @[el2_dec_dec_ctl.scala 17:17] + node _T_489 = and(_T_488, _T_482) @[el2_dec_dec_ctl.scala 17:17] + node _T_490 = and(_T_489, _T_484) @[el2_dec_dec_ctl.scala 17:17] + node _T_491 = and(_T_490, _T_485) @[el2_dec_dec_ctl.scala 17:17] + node _T_492 = and(_T_491, _T_487) @[el2_dec_dec_ctl.scala 17:17] + node _T_493 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_495 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_496 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_498 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_499 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_501 = and(_T_494, _T_495) @[el2_dec_dec_ctl.scala 17:17] + node _T_502 = and(_T_501, _T_497) @[el2_dec_dec_ctl.scala 17:17] + node _T_503 = and(_T_502, _T_498) @[el2_dec_dec_ctl.scala 17:17] + node _T_504 = and(_T_503, _T_500) @[el2_dec_dec_ctl.scala 17:17] + node _T_505 = or(_T_492, _T_504) @[el2_dec_dec_ctl.scala 49:51] + io.out.slt <= _T_505 @[el2_dec_dec_ctl.scala 49:14] + node _T_506 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_507 = eq(_T_506, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_508 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_509 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_510 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_511 = eq(_T_510, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_512 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_513 = eq(_T_512, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_514 = and(_T_507, _T_508) @[el2_dec_dec_ctl.scala 17:17] + node _T_515 = and(_T_514, _T_509) @[el2_dec_dec_ctl.scala 17:17] + node _T_516 = and(_T_515, _T_511) @[el2_dec_dec_ctl.scala 17:17] + node _T_517 = and(_T_516, _T_513) @[el2_dec_dec_ctl.scala 17:17] + node _T_518 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_519 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_520 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_522 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_523 = eq(_T_522, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_524 = and(_T_518, _T_519) @[el2_dec_dec_ctl.scala 17:17] + node _T_525 = and(_T_524, _T_521) @[el2_dec_dec_ctl.scala 17:17] + node _T_526 = and(_T_525, _T_523) @[el2_dec_dec_ctl.scala 17:17] + node _T_527 = or(_T_517, _T_526) @[el2_dec_dec_ctl.scala 50:51] + node _T_528 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_529 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_530 = eq(_T_529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_531 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_533 = and(_T_528, _T_530) @[el2_dec_dec_ctl.scala 17:17] + node _T_534 = and(_T_533, _T_532) @[el2_dec_dec_ctl.scala 17:17] + node _T_535 = or(_T_527, _T_534) @[el2_dec_dec_ctl.scala 50:79] + node _T_536 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_537 = eq(_T_536, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_538 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_540 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_541 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_542 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_543 = eq(_T_542, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_544 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_545 = eq(_T_544, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_546 = and(_T_537, _T_539) @[el2_dec_dec_ctl.scala 17:17] + node _T_547 = and(_T_546, _T_540) @[el2_dec_dec_ctl.scala 17:17] + node _T_548 = and(_T_547, _T_541) @[el2_dec_dec_ctl.scala 17:17] + node _T_549 = and(_T_548, _T_543) @[el2_dec_dec_ctl.scala 17:17] + node _T_550 = and(_T_549, _T_545) @[el2_dec_dec_ctl.scala 17:17] + node _T_551 = or(_T_535, _T_550) @[el2_dec_dec_ctl.scala 51:29] + node _T_552 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_553 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_554 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_555 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_557 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_558 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_560 = and(_T_552, _T_553) @[el2_dec_dec_ctl.scala 17:17] + node _T_561 = and(_T_560, _T_554) @[el2_dec_dec_ctl.scala 17:17] + node _T_562 = and(_T_561, _T_556) @[el2_dec_dec_ctl.scala 17:17] + node _T_563 = and(_T_562, _T_557) @[el2_dec_dec_ctl.scala 17:17] + node _T_564 = and(_T_563, _T_559) @[el2_dec_dec_ctl.scala 17:17] + node _T_565 = or(_T_551, _T_564) @[el2_dec_dec_ctl.scala 51:66] + io.out.unsign <= _T_565 @[el2_dec_dec_ctl.scala 50:17] + node _T_566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_567 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_569 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_570 = eq(_T_569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_571 = and(_T_566, _T_568) @[el2_dec_dec_ctl.scala 17:17] + node _T_572 = and(_T_571, _T_570) @[el2_dec_dec_ctl.scala 17:17] + io.out.condbr <= _T_572 @[el2_dec_dec_ctl.scala 53:17] + node _T_573 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_574 = eq(_T_573, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_575 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_576 = eq(_T_575, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_577 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_578 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_580 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_582 = and(_T_574, _T_576) @[el2_dec_dec_ctl.scala 17:17] + node _T_583 = and(_T_582, _T_577) @[el2_dec_dec_ctl.scala 17:17] + node _T_584 = and(_T_583, _T_579) @[el2_dec_dec_ctl.scala 17:17] + node _T_585 = and(_T_584, _T_581) @[el2_dec_dec_ctl.scala 17:17] + io.out.beq <= _T_585 @[el2_dec_dec_ctl.scala 54:14] + node _T_586 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_587 = eq(_T_586, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_588 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_589 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_590 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_591 = eq(_T_590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_592 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_593 = eq(_T_592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_594 = and(_T_587, _T_588) @[el2_dec_dec_ctl.scala 17:17] + node _T_595 = and(_T_594, _T_589) @[el2_dec_dec_ctl.scala 17:17] + node _T_596 = and(_T_595, _T_591) @[el2_dec_dec_ctl.scala 17:17] + node _T_597 = and(_T_596, _T_593) @[el2_dec_dec_ctl.scala 17:17] + io.out.bne <= _T_597 @[el2_dec_dec_ctl.scala 55:14] + node _T_598 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_599 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_600 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_601 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_603 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_605 = and(_T_598, _T_599) @[el2_dec_dec_ctl.scala 17:17] + node _T_606 = and(_T_605, _T_600) @[el2_dec_dec_ctl.scala 17:17] + node _T_607 = and(_T_606, _T_602) @[el2_dec_dec_ctl.scala 17:17] + node _T_608 = and(_T_607, _T_604) @[el2_dec_dec_ctl.scala 17:17] + io.out.bge <= _T_608 @[el2_dec_dec_ctl.scala 56:14] + node _T_609 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_610 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_611 = eq(_T_610, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_612 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_613 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_615 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_616 = eq(_T_615, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_617 = and(_T_609, _T_611) @[el2_dec_dec_ctl.scala 17:17] + node _T_618 = and(_T_617, _T_612) @[el2_dec_dec_ctl.scala 17:17] + node _T_619 = and(_T_618, _T_614) @[el2_dec_dec_ctl.scala 17:17] + node _T_620 = and(_T_619, _T_616) @[el2_dec_dec_ctl.scala 17:17] + io.out.blt <= _T_620 @[el2_dec_dec_ctl.scala 57:14] + node _T_621 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_622 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_623 = and(_T_621, _T_622) @[el2_dec_dec_ctl.scala 17:17] + io.out.jal <= _T_623 @[el2_dec_dec_ctl.scala 58:14] + node _T_624 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_626 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_628 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_629 = eq(_T_628, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_630 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_632 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_634 = and(_T_625, _T_627) @[el2_dec_dec_ctl.scala 17:17] + node _T_635 = and(_T_634, _T_629) @[el2_dec_dec_ctl.scala 17:17] + node _T_636 = and(_T_635, _T_631) @[el2_dec_dec_ctl.scala 17:17] + node _T_637 = and(_T_636, _T_633) @[el2_dec_dec_ctl.scala 17:17] + io.out.by <= _T_637 @[el2_dec_dec_ctl.scala 59:13] + node _T_638 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_639 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_641 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_642 = eq(_T_641, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_643 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_644 = eq(_T_643, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_645 = and(_T_638, _T_640) @[el2_dec_dec_ctl.scala 17:17] + node _T_646 = and(_T_645, _T_642) @[el2_dec_dec_ctl.scala 17:17] + node _T_647 = and(_T_646, _T_644) @[el2_dec_dec_ctl.scala 17:17] + io.out.half <= _T_647 @[el2_dec_dec_ctl.scala 60:15] + node _T_648 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_649 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_650 = eq(_T_649, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_651 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_652 = eq(_T_651, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_653 = and(_T_648, _T_650) @[el2_dec_dec_ctl.scala 17:17] + node _T_654 = and(_T_653, _T_652) @[el2_dec_dec_ctl.scala 17:17] + io.out.word <= _T_654 @[el2_dec_dec_ctl.scala 61:15] + node _T_655 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_656 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_657 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_658 = and(_T_655, _T_656) @[el2_dec_dec_ctl.scala 17:17] + node _T_659 = and(_T_658, _T_657) @[el2_dec_dec_ctl.scala 17:17] + node _T_660 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_661 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_662 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_663 = and(_T_660, _T_661) @[el2_dec_dec_ctl.scala 17:17] + node _T_664 = and(_T_663, _T_662) @[el2_dec_dec_ctl.scala 17:17] + node _T_665 = or(_T_659, _T_664) @[el2_dec_dec_ctl.scala 62:44] + node _T_666 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_668 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_669 = and(_T_666, _T_667) @[el2_dec_dec_ctl.scala 17:17] + node _T_670 = and(_T_669, _T_668) @[el2_dec_dec_ctl.scala 17:17] + node _T_671 = or(_T_665, _T_670) @[el2_dec_dec_ctl.scala 62:67] + node _T_672 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_673 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_674 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_675 = and(_T_672, _T_673) @[el2_dec_dec_ctl.scala 17:17] + node _T_676 = and(_T_675, _T_674) @[el2_dec_dec_ctl.scala 17:17] + node _T_677 = or(_T_671, _T_676) @[el2_dec_dec_ctl.scala 63:26] + node _T_678 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_679 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_680 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_681 = and(_T_678, _T_679) @[el2_dec_dec_ctl.scala 17:17] + node _T_682 = and(_T_681, _T_680) @[el2_dec_dec_ctl.scala 17:17] + node _T_683 = or(_T_677, _T_682) @[el2_dec_dec_ctl.scala 63:49] + node _T_684 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_685 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_686 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_687 = and(_T_684, _T_685) @[el2_dec_dec_ctl.scala 17:17] + node _T_688 = and(_T_687, _T_686) @[el2_dec_dec_ctl.scala 17:17] + node _T_689 = or(_T_683, _T_688) @[el2_dec_dec_ctl.scala 63:73] + io.out.csr_read <= _T_689 @[el2_dec_dec_ctl.scala 62:19] + node _T_690 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_691 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_692 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_693 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_694 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_695 = and(_T_690, _T_691) @[el2_dec_dec_ctl.scala 17:17] + node _T_696 = and(_T_695, _T_692) @[el2_dec_dec_ctl.scala 17:17] + node _T_697 = and(_T_696, _T_693) @[el2_dec_dec_ctl.scala 17:17] + node _T_698 = and(_T_697, _T_694) @[el2_dec_dec_ctl.scala 17:17] + node _T_699 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_700 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_701 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_702 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_703 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_704 = and(_T_699, _T_700) @[el2_dec_dec_ctl.scala 17:17] + node _T_705 = and(_T_704, _T_701) @[el2_dec_dec_ctl.scala 17:17] + node _T_706 = and(_T_705, _T_702) @[el2_dec_dec_ctl.scala 17:17] + node _T_707 = and(_T_706, _T_703) @[el2_dec_dec_ctl.scala 17:17] + node _T_708 = or(_T_698, _T_707) @[el2_dec_dec_ctl.scala 65:49] + node _T_709 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_710 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_711 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_712 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_713 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_714 = and(_T_709, _T_710) @[el2_dec_dec_ctl.scala 17:17] + node _T_715 = and(_T_714, _T_711) @[el2_dec_dec_ctl.scala 17:17] + node _T_716 = and(_T_715, _T_712) @[el2_dec_dec_ctl.scala 17:17] + node _T_717 = and(_T_716, _T_713) @[el2_dec_dec_ctl.scala 17:17] + node _T_718 = or(_T_708, _T_717) @[el2_dec_dec_ctl.scala 65:79] + node _T_719 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_720 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_721 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_722 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_723 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_724 = and(_T_719, _T_720) @[el2_dec_dec_ctl.scala 17:17] + node _T_725 = and(_T_724, _T_721) @[el2_dec_dec_ctl.scala 17:17] + node _T_726 = and(_T_725, _T_722) @[el2_dec_dec_ctl.scala 17:17] + node _T_727 = and(_T_726, _T_723) @[el2_dec_dec_ctl.scala 17:17] + node _T_728 = or(_T_718, _T_727) @[el2_dec_dec_ctl.scala 66:33] + node _T_729 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_730 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_731 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_732 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_733 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_734 = and(_T_729, _T_730) @[el2_dec_dec_ctl.scala 17:17] + node _T_735 = and(_T_734, _T_731) @[el2_dec_dec_ctl.scala 17:17] + node _T_736 = and(_T_735, _T_732) @[el2_dec_dec_ctl.scala 17:17] + node _T_737 = and(_T_736, _T_733) @[el2_dec_dec_ctl.scala 17:17] + node _T_738 = or(_T_728, _T_737) @[el2_dec_dec_ctl.scala 66:63] + io.out.csr_clr <= _T_738 @[el2_dec_dec_ctl.scala 65:18] + node _T_739 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_740 = eq(_T_739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_741 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_742 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_743 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_744 = and(_T_740, _T_741) @[el2_dec_dec_ctl.scala 17:17] + node _T_745 = and(_T_744, _T_742) @[el2_dec_dec_ctl.scala 17:17] + node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 17:17] + io.out.csr_write <= _T_746 @[el2_dec_dec_ctl.scala 68:20] + node _T_747 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_748 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_749 = eq(_T_748, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_750 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_751 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_752 = and(_T_747, _T_749) @[el2_dec_dec_ctl.scala 17:17] + node _T_753 = and(_T_752, _T_750) @[el2_dec_dec_ctl.scala 17:17] + node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 17:17] + node _T_755 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_756 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_757 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_758 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_759 = and(_T_755, _T_756) @[el2_dec_dec_ctl.scala 17:17] + node _T_760 = and(_T_759, _T_757) @[el2_dec_dec_ctl.scala 17:17] + node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 17:17] + node _T_762 = or(_T_754, _T_761) @[el2_dec_dec_ctl.scala 69:47] + node _T_763 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_764 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_765 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_766 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_767 = and(_T_763, _T_764) @[el2_dec_dec_ctl.scala 17:17] + node _T_768 = and(_T_767, _T_765) @[el2_dec_dec_ctl.scala 17:17] + node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 17:17] + node _T_770 = or(_T_762, _T_769) @[el2_dec_dec_ctl.scala 69:74] + node _T_771 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_772 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_773 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_774 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_775 = and(_T_771, _T_772) @[el2_dec_dec_ctl.scala 17:17] + node _T_776 = and(_T_775, _T_773) @[el2_dec_dec_ctl.scala 17:17] + node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 17:17] + node _T_778 = or(_T_770, _T_777) @[el2_dec_dec_ctl.scala 70:30] + node _T_779 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_780 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_781 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_782 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_783 = and(_T_779, _T_780) @[el2_dec_dec_ctl.scala 17:17] + node _T_784 = and(_T_783, _T_781) @[el2_dec_dec_ctl.scala 17:17] + node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 17:17] + node _T_786 = or(_T_778, _T_785) @[el2_dec_dec_ctl.scala 70:57] + node _T_787 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_788 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_789 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_790 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_791 = and(_T_787, _T_788) @[el2_dec_dec_ctl.scala 17:17] + node _T_792 = and(_T_791, _T_789) @[el2_dec_dec_ctl.scala 17:17] + node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 17:17] + node _T_794 = or(_T_786, _T_793) @[el2_dec_dec_ctl.scala 71:30] + io.out.csr_imm <= _T_794 @[el2_dec_dec_ctl.scala 69:18] + node _T_795 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_796 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_798 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_799 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_800 = and(_T_795, _T_797) @[el2_dec_dec_ctl.scala 17:17] + node _T_801 = and(_T_800, _T_798) @[el2_dec_dec_ctl.scala 17:17] + node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 17:17] + node _T_803 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_804 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_805 = eq(_T_804, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_806 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_807 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_808 = and(_T_803, _T_805) @[el2_dec_dec_ctl.scala 17:17] + node _T_809 = and(_T_808, _T_806) @[el2_dec_dec_ctl.scala 17:17] + node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 17:17] + node _T_811 = or(_T_802, _T_810) @[el2_dec_dec_ctl.scala 72:47] + node _T_812 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_813 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_814 = eq(_T_813, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_815 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_816 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_817 = and(_T_812, _T_814) @[el2_dec_dec_ctl.scala 17:17] + node _T_818 = and(_T_817, _T_815) @[el2_dec_dec_ctl.scala 17:17] + node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 17:17] + node _T_820 = or(_T_811, _T_819) @[el2_dec_dec_ctl.scala 72:75] + node _T_821 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_822 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_823 = eq(_T_822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_824 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_825 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_826 = and(_T_821, _T_823) @[el2_dec_dec_ctl.scala 17:17] + node _T_827 = and(_T_826, _T_824) @[el2_dec_dec_ctl.scala 17:17] + node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 17:17] + node _T_829 = or(_T_820, _T_828) @[el2_dec_dec_ctl.scala 73:31] + node _T_830 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_831 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_832 = eq(_T_831, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_833 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_834 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_835 = and(_T_830, _T_832) @[el2_dec_dec_ctl.scala 17:17] + node _T_836 = and(_T_835, _T_833) @[el2_dec_dec_ctl.scala 17:17] + node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 17:17] + node _T_838 = or(_T_829, _T_837) @[el2_dec_dec_ctl.scala 73:59] + io.out.csr_set <= _T_838 @[el2_dec_dec_ctl.scala 72:18] + node _T_839 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_840 = eq(_T_839, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_841 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:34] + node _T_842 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_843 = eq(_T_842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_844 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_845 = eq(_T_844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_846 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_847 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_848 = and(_T_840, _T_841) @[el2_dec_dec_ctl.scala 17:17] + node _T_849 = and(_T_848, _T_843) @[el2_dec_dec_ctl.scala 17:17] + node _T_850 = and(_T_849, _T_845) @[el2_dec_dec_ctl.scala 17:17] + node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 17:17] + node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 17:17] + io.out.ebreak <= _T_852 @[el2_dec_dec_ctl.scala 75:17] + node _T_853 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_854 = eq(_T_853, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_855 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53] + node _T_856 = eq(_T_855, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_857 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_859 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_861 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_862 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_863 = and(_T_854, _T_856) @[el2_dec_dec_ctl.scala 17:17] + node _T_864 = and(_T_863, _T_858) @[el2_dec_dec_ctl.scala 17:17] + node _T_865 = and(_T_864, _T_860) @[el2_dec_dec_ctl.scala 17:17] + node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 17:17] + node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 17:17] + io.out.ecall <= _T_867 @[el2_dec_dec_ctl.scala 76:16] + node _T_868 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:34] + node _T_869 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_870 = eq(_T_869, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_871 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_872 = eq(_T_871, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_873 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_874 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_875 = and(_T_868, _T_870) @[el2_dec_dec_ctl.scala 17:17] + node _T_876 = and(_T_875, _T_872) @[el2_dec_dec_ctl.scala 17:17] + node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 17:17] + node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 17:17] + io.out.mret <= _T_878 @[el2_dec_dec_ctl.scala 77:15] + node _T_879 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_880 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_881 = eq(_T_880, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_882 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_883 = eq(_T_882, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_884 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_885 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_886 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_887 = eq(_T_886, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_888 = and(_T_879, _T_881) @[el2_dec_dec_ctl.scala 17:17] + node _T_889 = and(_T_888, _T_883) @[el2_dec_dec_ctl.scala 17:17] + node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 17:17] + node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 17:17] + node _T_892 = and(_T_891, _T_887) @[el2_dec_dec_ctl.scala 17:17] + io.out.mul <= _T_892 @[el2_dec_dec_ctl.scala 78:14] + node _T_893 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_894 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_896 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_897 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_898 = eq(_T_897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_899 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_900 = eq(_T_899, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_901 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_902 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_903 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_904 = eq(_T_903, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_905 = and(_T_893, _T_895) @[el2_dec_dec_ctl.scala 17:17] + node _T_906 = and(_T_905, _T_896) @[el2_dec_dec_ctl.scala 17:17] + node _T_907 = and(_T_906, _T_898) @[el2_dec_dec_ctl.scala 17:17] + node _T_908 = and(_T_907, _T_900) @[el2_dec_dec_ctl.scala 17:17] + node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 17:17] + node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 17:17] + node _T_911 = and(_T_910, _T_904) @[el2_dec_dec_ctl.scala 17:17] + node _T_912 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_913 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_914 = eq(_T_913, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_915 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_917 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_918 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_919 = eq(_T_918, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_920 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_921 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_922 = eq(_T_921, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_923 = and(_T_912, _T_914) @[el2_dec_dec_ctl.scala 17:17] + node _T_924 = and(_T_923, _T_916) @[el2_dec_dec_ctl.scala 17:17] + node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 17:17] + node _T_926 = and(_T_925, _T_919) @[el2_dec_dec_ctl.scala 17:17] + node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 17:17] + node _T_928 = and(_T_927, _T_922) @[el2_dec_dec_ctl.scala 17:17] + node _T_929 = or(_T_911, _T_928) @[el2_dec_dec_ctl.scala 79:61] + io.out.rs1_sign <= _T_929 @[el2_dec_dec_ctl.scala 79:19] + node _T_930 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_931 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_932 = eq(_T_931, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_933 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_934 = eq(_T_933, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_935 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_936 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_937 = eq(_T_936, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_938 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_939 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_941 = and(_T_930, _T_932) @[el2_dec_dec_ctl.scala 17:17] + node _T_942 = and(_T_941, _T_934) @[el2_dec_dec_ctl.scala 17:17] + node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 17:17] + node _T_944 = and(_T_943, _T_937) @[el2_dec_dec_ctl.scala 17:17] + node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 17:17] + node _T_946 = and(_T_945, _T_940) @[el2_dec_dec_ctl.scala 17:17] + io.out.rs2_sign <= _T_946 @[el2_dec_dec_ctl.scala 81:19] + node _T_947 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_948 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_950 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_952 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_953 = eq(_T_952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_954 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_955 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_956 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_957 = eq(_T_956, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_958 = and(_T_947, _T_949) @[el2_dec_dec_ctl.scala 17:17] + node _T_959 = and(_T_958, _T_951) @[el2_dec_dec_ctl.scala 17:17] + node _T_960 = and(_T_959, _T_953) @[el2_dec_dec_ctl.scala 17:17] + node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 17:17] + node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 17:17] + node _T_963 = and(_T_962, _T_957) @[el2_dec_dec_ctl.scala 17:17] + io.out.low <= _T_963 @[el2_dec_dec_ctl.scala 82:14] + node _T_964 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_965 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_966 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_967 = eq(_T_966, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_968 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_969 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_970 = eq(_T_969, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_971 = and(_T_964, _T_965) @[el2_dec_dec_ctl.scala 17:17] + node _T_972 = and(_T_971, _T_967) @[el2_dec_dec_ctl.scala 17:17] + node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 17:17] + node _T_974 = and(_T_973, _T_970) @[el2_dec_dec_ctl.scala 17:17] + io.out.div <= _T_974 @[el2_dec_dec_ctl.scala 83:14] + node _T_975 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_976 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_977 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_978 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_979 = eq(_T_978, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_980 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_981 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_983 = and(_T_975, _T_976) @[el2_dec_dec_ctl.scala 17:17] + node _T_984 = and(_T_983, _T_977) @[el2_dec_dec_ctl.scala 17:17] + node _T_985 = and(_T_984, _T_979) @[el2_dec_dec_ctl.scala 17:17] + node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 17:17] + node _T_987 = and(_T_986, _T_982) @[el2_dec_dec_ctl.scala 17:17] + io.out.rem <= _T_987 @[el2_dec_dec_ctl.scala 84:14] + node _T_988 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_989 = eq(_T_988, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_990 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_991 = and(_T_989, _T_990) @[el2_dec_dec_ctl.scala 17:17] + io.out.fence <= _T_991 @[el2_dec_dec_ctl.scala 85:16] + node _T_992 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_993 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_995 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_996 = and(_T_992, _T_994) @[el2_dec_dec_ctl.scala 17:17] + node _T_997 = and(_T_996, _T_995) @[el2_dec_dec_ctl.scala 17:17] + io.out.fence_i <= _T_997 @[el2_dec_dec_ctl.scala 86:18] + node _T_998 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34] + node _T_999 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:34] + node _T_1000 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1001 = eq(_T_1000, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1002 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1003 = eq(_T_1002, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1004 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1005 = and(_T_998, _T_999) @[el2_dec_dec_ctl.scala 17:17] + node _T_1006 = and(_T_1005, _T_1001) @[el2_dec_dec_ctl.scala 17:17] + node _T_1007 = and(_T_1006, _T_1003) @[el2_dec_dec_ctl.scala 17:17] + node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 17:17] + node _T_1009 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1010 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1011 = and(_T_1009, _T_1010) @[el2_dec_dec_ctl.scala 17:17] + node _T_1012 = or(_T_1008, _T_1011) @[el2_dec_dec_ctl.scala 87:51] + node _T_1013 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1015 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1016 = eq(_T_1015, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1017 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1018 = and(_T_1014, _T_1016) @[el2_dec_dec_ctl.scala 17:17] + node _T_1019 = and(_T_1018, _T_1017) @[el2_dec_dec_ctl.scala 17:17] + node _T_1020 = or(_T_1012, _T_1019) @[el2_dec_dec_ctl.scala 87:72] + node _T_1021 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1022 = eq(_T_1021, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1023 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1024 = and(_T_1022, _T_1023) @[el2_dec_dec_ctl.scala 17:17] + node _T_1025 = or(_T_1020, _T_1024) @[el2_dec_dec_ctl.scala 88:29] + io.out.pm_alu <= _T_1025 @[el2_dec_dec_ctl.scala 87:17] + node _T_1026 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1028 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1029 = and(_T_1027, _T_1028) @[el2_dec_dec_ctl.scala 17:17] + node _T_1030 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1032 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_1033 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1034 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1035 = and(_T_1031, _T_1032) @[el2_dec_dec_ctl.scala 17:17] + node _T_1036 = and(_T_1035, _T_1033) @[el2_dec_dec_ctl.scala 17:17] + node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 17:17] + node _T_1038 = or(_T_1029, _T_1037) @[el2_dec_dec_ctl.scala 89:41] + node _T_1039 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1040 = eq(_T_1039, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1041 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_1042 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1043 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1044 = and(_T_1040, _T_1041) @[el2_dec_dec_ctl.scala 17:17] + node _T_1045 = and(_T_1044, _T_1042) @[el2_dec_dec_ctl.scala 17:17] + node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 17:17] + node _T_1047 = or(_T_1038, _T_1046) @[el2_dec_dec_ctl.scala 89:68] + node _T_1048 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1049 = eq(_T_1048, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1050 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_1051 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1052 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1053 = and(_T_1049, _T_1050) @[el2_dec_dec_ctl.scala 17:17] + node _T_1054 = and(_T_1053, _T_1051) @[el2_dec_dec_ctl.scala 17:17] + node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 17:17] + node _T_1056 = or(_T_1047, _T_1055) @[el2_dec_dec_ctl.scala 90:30] + node _T_1057 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1058 = eq(_T_1057, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1059 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_1060 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1061 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1062 = and(_T_1058, _T_1059) @[el2_dec_dec_ctl.scala 17:17] + node _T_1063 = and(_T_1062, _T_1060) @[el2_dec_dec_ctl.scala 17:17] + node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 17:17] + node _T_1065 = or(_T_1056, _T_1064) @[el2_dec_dec_ctl.scala 90:57] + node _T_1066 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1068 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_1069 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1070 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1071 = and(_T_1067, _T_1068) @[el2_dec_dec_ctl.scala 17:17] + node _T_1072 = and(_T_1071, _T_1069) @[el2_dec_dec_ctl.scala 17:17] + node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 17:17] + node _T_1074 = or(_T_1065, _T_1073) @[el2_dec_dec_ctl.scala 91:31] + node _T_1075 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1077 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1078 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1079 = and(_T_1075, _T_1076) @[el2_dec_dec_ctl.scala 17:17] + node _T_1080 = and(_T_1079, _T_1077) @[el2_dec_dec_ctl.scala 17:17] + node _T_1081 = and(_T_1080, _T_1078) @[el2_dec_dec_ctl.scala 17:17] + node _T_1082 = or(_T_1074, _T_1081) @[el2_dec_dec_ctl.scala 91:59] + node _T_1083 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_1084 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1085 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1086 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1087 = and(_T_1083, _T_1084) @[el2_dec_dec_ctl.scala 17:17] + node _T_1088 = and(_T_1087, _T_1085) @[el2_dec_dec_ctl.scala 17:17] + node _T_1089 = and(_T_1088, _T_1086) @[el2_dec_dec_ctl.scala 17:17] + node _T_1090 = or(_T_1082, _T_1089) @[el2_dec_dec_ctl.scala 92:30] + node _T_1091 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_1092 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1093 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1094 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1095 = and(_T_1091, _T_1092) @[el2_dec_dec_ctl.scala 17:17] + node _T_1096 = and(_T_1095, _T_1093) @[el2_dec_dec_ctl.scala 17:17] + node _T_1097 = and(_T_1096, _T_1094) @[el2_dec_dec_ctl.scala 17:17] + node _T_1098 = or(_T_1090, _T_1097) @[el2_dec_dec_ctl.scala 92:57] + node _T_1099 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_1100 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1101 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1102 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1103 = and(_T_1099, _T_1100) @[el2_dec_dec_ctl.scala 17:17] + node _T_1104 = and(_T_1103, _T_1101) @[el2_dec_dec_ctl.scala 17:17] + node _T_1105 = and(_T_1104, _T_1102) @[el2_dec_dec_ctl.scala 17:17] + node _T_1106 = or(_T_1098, _T_1105) @[el2_dec_dec_ctl.scala 93:30] + node _T_1107 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_1108 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1109 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1111 = and(_T_1107, _T_1108) @[el2_dec_dec_ctl.scala 17:17] + node _T_1112 = and(_T_1111, _T_1109) @[el2_dec_dec_ctl.scala 17:17] + node _T_1113 = and(_T_1112, _T_1110) @[el2_dec_dec_ctl.scala 17:17] + node _T_1114 = or(_T_1106, _T_1113) @[el2_dec_dec_ctl.scala 93:57] + io.out.presync <= _T_1114 @[el2_dec_dec_ctl.scala 89:18] + node _T_1115 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_1116 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1118 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1119 = and(_T_1115, _T_1117) @[el2_dec_dec_ctl.scala 17:17] + node _T_1120 = and(_T_1119, _T_1118) @[el2_dec_dec_ctl.scala 17:17] + node _T_1121 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1123 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1126 = eq(_T_1125, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1127 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1128 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1129 = and(_T_1122, _T_1124) @[el2_dec_dec_ctl.scala 17:17] + node _T_1130 = and(_T_1129, _T_1126) @[el2_dec_dec_ctl.scala 17:17] + node _T_1131 = and(_T_1130, _T_1127) @[el2_dec_dec_ctl.scala 17:17] + node _T_1132 = and(_T_1131, _T_1128) @[el2_dec_dec_ctl.scala 17:17] + node _T_1133 = or(_T_1120, _T_1132) @[el2_dec_dec_ctl.scala 95:45] + node _T_1134 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1135 = eq(_T_1134, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1136 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1139 = and(_T_1135, _T_1136) @[el2_dec_dec_ctl.scala 17:17] + node _T_1140 = and(_T_1139, _T_1137) @[el2_dec_dec_ctl.scala 17:17] + node _T_1141 = and(_T_1140, _T_1138) @[el2_dec_dec_ctl.scala 17:17] + node _T_1142 = or(_T_1133, _T_1141) @[el2_dec_dec_ctl.scala 95:78] + node _T_1143 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1145 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_1146 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1147 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1148 = and(_T_1144, _T_1145) @[el2_dec_dec_ctl.scala 17:17] + node _T_1149 = and(_T_1148, _T_1146) @[el2_dec_dec_ctl.scala 17:17] + node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 17:17] + node _T_1151 = or(_T_1142, _T_1150) @[el2_dec_dec_ctl.scala 96:30] + node _T_1152 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1153 = eq(_T_1152, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1154 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_1155 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1156 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1157 = and(_T_1153, _T_1154) @[el2_dec_dec_ctl.scala 17:17] + node _T_1158 = and(_T_1157, _T_1155) @[el2_dec_dec_ctl.scala 17:17] + node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 17:17] + node _T_1160 = or(_T_1151, _T_1159) @[el2_dec_dec_ctl.scala 96:57] + node _T_1161 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1162 = eq(_T_1161, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1163 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_1164 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1165 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1166 = and(_T_1162, _T_1163) @[el2_dec_dec_ctl.scala 17:17] + node _T_1167 = and(_T_1166, _T_1164) @[el2_dec_dec_ctl.scala 17:17] + node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 17:17] + node _T_1169 = or(_T_1160, _T_1168) @[el2_dec_dec_ctl.scala 97:30] + node _T_1170 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1172 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_1173 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1174 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1175 = and(_T_1171, _T_1172) @[el2_dec_dec_ctl.scala 17:17] + node _T_1176 = and(_T_1175, _T_1173) @[el2_dec_dec_ctl.scala 17:17] + node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 17:17] + node _T_1178 = or(_T_1169, _T_1177) @[el2_dec_dec_ctl.scala 97:58] + node _T_1179 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1181 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1182 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1183 = and(_T_1179, _T_1180) @[el2_dec_dec_ctl.scala 17:17] + node _T_1184 = and(_T_1183, _T_1181) @[el2_dec_dec_ctl.scala 17:17] + node _T_1185 = and(_T_1184, _T_1182) @[el2_dec_dec_ctl.scala 17:17] + node _T_1186 = or(_T_1178, _T_1185) @[el2_dec_dec_ctl.scala 98:31] + node _T_1187 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_1188 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1189 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1190 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1191 = and(_T_1187, _T_1188) @[el2_dec_dec_ctl.scala 17:17] + node _T_1192 = and(_T_1191, _T_1189) @[el2_dec_dec_ctl.scala 17:17] + node _T_1193 = and(_T_1192, _T_1190) @[el2_dec_dec_ctl.scala 17:17] + node _T_1194 = or(_T_1186, _T_1193) @[el2_dec_dec_ctl.scala 98:58] + node _T_1195 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_1196 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1197 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1198 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1199 = and(_T_1195, _T_1196) @[el2_dec_dec_ctl.scala 17:17] + node _T_1200 = and(_T_1199, _T_1197) @[el2_dec_dec_ctl.scala 17:17] + node _T_1201 = and(_T_1200, _T_1198) @[el2_dec_dec_ctl.scala 17:17] + node _T_1202 = or(_T_1194, _T_1201) @[el2_dec_dec_ctl.scala 99:30] + node _T_1203 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_1204 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1205 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1206 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1207 = and(_T_1203, _T_1204) @[el2_dec_dec_ctl.scala 17:17] + node _T_1208 = and(_T_1207, _T_1205) @[el2_dec_dec_ctl.scala 17:17] + node _T_1209 = and(_T_1208, _T_1206) @[el2_dec_dec_ctl.scala 17:17] + node _T_1210 = or(_T_1202, _T_1209) @[el2_dec_dec_ctl.scala 99:57] + node _T_1211 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_1212 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1213 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1215 = and(_T_1211, _T_1212) @[el2_dec_dec_ctl.scala 17:17] + node _T_1216 = and(_T_1215, _T_1213) @[el2_dec_dec_ctl.scala 17:17] + node _T_1217 = and(_T_1216, _T_1214) @[el2_dec_dec_ctl.scala 17:17] + node _T_1218 = or(_T_1210, _T_1217) @[el2_dec_dec_ctl.scala 100:30] + io.out.postsync <= _T_1218 @[el2_dec_dec_ctl.scala 95:19] + node _T_1219 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1220 = eq(_T_1219, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1221 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1222 = eq(_T_1221, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1223 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:34] + node _T_1224 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34] + node _T_1225 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1226 = eq(_T_1225, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1227 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1228 = eq(_T_1227, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1229 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1231 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1233 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1234 = eq(_T_1233, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1235 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1237 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:34] + node _T_1238 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53] + node _T_1239 = eq(_T_1238, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1240 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1242 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1243 = eq(_T_1242, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1244 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1245 = eq(_T_1244, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1246 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1247 = eq(_T_1246, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1248 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1250 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1252 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1254 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1256 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1258 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1260 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1262 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1263 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1264 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1265 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1266 = eq(_T_1265, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1267 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1269 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1270 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1271 = and(_T_1220, _T_1222) @[el2_dec_dec_ctl.scala 17:17] + node _T_1272 = and(_T_1271, _T_1223) @[el2_dec_dec_ctl.scala 17:17] + node _T_1273 = and(_T_1272, _T_1224) @[el2_dec_dec_ctl.scala 17:17] + node _T_1274 = and(_T_1273, _T_1226) @[el2_dec_dec_ctl.scala 17:17] + node _T_1275 = and(_T_1274, _T_1228) @[el2_dec_dec_ctl.scala 17:17] + node _T_1276 = and(_T_1275, _T_1230) @[el2_dec_dec_ctl.scala 17:17] + node _T_1277 = and(_T_1276, _T_1232) @[el2_dec_dec_ctl.scala 17:17] + node _T_1278 = and(_T_1277, _T_1234) @[el2_dec_dec_ctl.scala 17:17] + node _T_1279 = and(_T_1278, _T_1236) @[el2_dec_dec_ctl.scala 17:17] + node _T_1280 = and(_T_1279, _T_1237) @[el2_dec_dec_ctl.scala 17:17] + node _T_1281 = and(_T_1280, _T_1239) @[el2_dec_dec_ctl.scala 17:17] + node _T_1282 = and(_T_1281, _T_1241) @[el2_dec_dec_ctl.scala 17:17] + node _T_1283 = and(_T_1282, _T_1243) @[el2_dec_dec_ctl.scala 17:17] + node _T_1284 = and(_T_1283, _T_1245) @[el2_dec_dec_ctl.scala 17:17] + node _T_1285 = and(_T_1284, _T_1247) @[el2_dec_dec_ctl.scala 17:17] + node _T_1286 = and(_T_1285, _T_1249) @[el2_dec_dec_ctl.scala 17:17] + node _T_1287 = and(_T_1286, _T_1251) @[el2_dec_dec_ctl.scala 17:17] + node _T_1288 = and(_T_1287, _T_1253) @[el2_dec_dec_ctl.scala 17:17] + node _T_1289 = and(_T_1288, _T_1255) @[el2_dec_dec_ctl.scala 17:17] + node _T_1290 = and(_T_1289, _T_1257) @[el2_dec_dec_ctl.scala 17:17] + node _T_1291 = and(_T_1290, _T_1259) @[el2_dec_dec_ctl.scala 17:17] + node _T_1292 = and(_T_1291, _T_1261) @[el2_dec_dec_ctl.scala 17:17] + node _T_1293 = and(_T_1292, _T_1262) @[el2_dec_dec_ctl.scala 17:17] + node _T_1294 = and(_T_1293, _T_1263) @[el2_dec_dec_ctl.scala 17:17] + node _T_1295 = and(_T_1294, _T_1264) @[el2_dec_dec_ctl.scala 17:17] + node _T_1296 = and(_T_1295, _T_1266) @[el2_dec_dec_ctl.scala 17:17] + node _T_1297 = and(_T_1296, _T_1268) @[el2_dec_dec_ctl.scala 17:17] + node _T_1298 = and(_T_1297, _T_1269) @[el2_dec_dec_ctl.scala 17:17] + node _T_1299 = and(_T_1298, _T_1270) @[el2_dec_dec_ctl.scala 17:17] + node _T_1300 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1302 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1304 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1306 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34] + node _T_1307 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1309 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1310 = eq(_T_1309, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1311 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1313 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1315 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1317 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:34] + node _T_1318 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1320 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:34] + node _T_1321 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1322 = eq(_T_1321, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1323 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1324 = eq(_T_1323, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1325 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1326 = eq(_T_1325, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1327 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1329 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1331 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1332 = eq(_T_1331, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1333 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1334 = eq(_T_1333, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1335 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1336 = eq(_T_1335, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1337 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1338 = eq(_T_1337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1339 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1340 = eq(_T_1339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1341 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1342 = eq(_T_1341, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1343 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1344 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1345 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1346 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1348 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1350 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1351 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1352 = and(_T_1301, _T_1303) @[el2_dec_dec_ctl.scala 17:17] + node _T_1353 = and(_T_1352, _T_1305) @[el2_dec_dec_ctl.scala 17:17] + node _T_1354 = and(_T_1353, _T_1306) @[el2_dec_dec_ctl.scala 17:17] + node _T_1355 = and(_T_1354, _T_1308) @[el2_dec_dec_ctl.scala 17:17] + node _T_1356 = and(_T_1355, _T_1310) @[el2_dec_dec_ctl.scala 17:17] + node _T_1357 = and(_T_1356, _T_1312) @[el2_dec_dec_ctl.scala 17:17] + node _T_1358 = and(_T_1357, _T_1314) @[el2_dec_dec_ctl.scala 17:17] + node _T_1359 = and(_T_1358, _T_1316) @[el2_dec_dec_ctl.scala 17:17] + node _T_1360 = and(_T_1359, _T_1317) @[el2_dec_dec_ctl.scala 17:17] + node _T_1361 = and(_T_1360, _T_1319) @[el2_dec_dec_ctl.scala 17:17] + node _T_1362 = and(_T_1361, _T_1320) @[el2_dec_dec_ctl.scala 17:17] + node _T_1363 = and(_T_1362, _T_1322) @[el2_dec_dec_ctl.scala 17:17] + node _T_1364 = and(_T_1363, _T_1324) @[el2_dec_dec_ctl.scala 17:17] + node _T_1365 = and(_T_1364, _T_1326) @[el2_dec_dec_ctl.scala 17:17] + node _T_1366 = and(_T_1365, _T_1328) @[el2_dec_dec_ctl.scala 17:17] + node _T_1367 = and(_T_1366, _T_1330) @[el2_dec_dec_ctl.scala 17:17] + node _T_1368 = and(_T_1367, _T_1332) @[el2_dec_dec_ctl.scala 17:17] + node _T_1369 = and(_T_1368, _T_1334) @[el2_dec_dec_ctl.scala 17:17] + node _T_1370 = and(_T_1369, _T_1336) @[el2_dec_dec_ctl.scala 17:17] + node _T_1371 = and(_T_1370, _T_1338) @[el2_dec_dec_ctl.scala 17:17] + node _T_1372 = and(_T_1371, _T_1340) @[el2_dec_dec_ctl.scala 17:17] + node _T_1373 = and(_T_1372, _T_1342) @[el2_dec_dec_ctl.scala 17:17] + node _T_1374 = and(_T_1373, _T_1343) @[el2_dec_dec_ctl.scala 17:17] + node _T_1375 = and(_T_1374, _T_1344) @[el2_dec_dec_ctl.scala 17:17] + node _T_1376 = and(_T_1375, _T_1345) @[el2_dec_dec_ctl.scala 17:17] + node _T_1377 = and(_T_1376, _T_1347) @[el2_dec_dec_ctl.scala 17:17] + node _T_1378 = and(_T_1377, _T_1349) @[el2_dec_dec_ctl.scala 17:17] + node _T_1379 = and(_T_1378, _T_1350) @[el2_dec_dec_ctl.scala 17:17] + node _T_1380 = and(_T_1379, _T_1351) @[el2_dec_dec_ctl.scala 17:17] + node _T_1381 = or(_T_1299, _T_1380) @[el2_dec_dec_ctl.scala 101:136] + node _T_1382 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1383 = eq(_T_1382, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1384 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1385 = eq(_T_1384, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1386 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1388 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1390 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1391 = eq(_T_1390, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1392 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1393 = eq(_T_1392, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1394 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1396 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1398 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1400 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1402 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1404 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1406 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1408 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1410 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1412 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1414 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1416 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1418 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1420 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1422 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1424 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1426 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1427 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1428 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1430 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1432 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1433 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1434 = and(_T_1383, _T_1385) @[el2_dec_dec_ctl.scala 17:17] + node _T_1435 = and(_T_1434, _T_1387) @[el2_dec_dec_ctl.scala 17:17] + node _T_1436 = and(_T_1435, _T_1389) @[el2_dec_dec_ctl.scala 17:17] + node _T_1437 = and(_T_1436, _T_1391) @[el2_dec_dec_ctl.scala 17:17] + node _T_1438 = and(_T_1437, _T_1393) @[el2_dec_dec_ctl.scala 17:17] + node _T_1439 = and(_T_1438, _T_1395) @[el2_dec_dec_ctl.scala 17:17] + node _T_1440 = and(_T_1439, _T_1397) @[el2_dec_dec_ctl.scala 17:17] + node _T_1441 = and(_T_1440, _T_1399) @[el2_dec_dec_ctl.scala 17:17] + node _T_1442 = and(_T_1441, _T_1401) @[el2_dec_dec_ctl.scala 17:17] + node _T_1443 = and(_T_1442, _T_1403) @[el2_dec_dec_ctl.scala 17:17] + node _T_1444 = and(_T_1443, _T_1405) @[el2_dec_dec_ctl.scala 17:17] + node _T_1445 = and(_T_1444, _T_1407) @[el2_dec_dec_ctl.scala 17:17] + node _T_1446 = and(_T_1445, _T_1409) @[el2_dec_dec_ctl.scala 17:17] + node _T_1447 = and(_T_1446, _T_1411) @[el2_dec_dec_ctl.scala 17:17] + node _T_1448 = and(_T_1447, _T_1413) @[el2_dec_dec_ctl.scala 17:17] + node _T_1449 = and(_T_1448, _T_1415) @[el2_dec_dec_ctl.scala 17:17] + node _T_1450 = and(_T_1449, _T_1417) @[el2_dec_dec_ctl.scala 17:17] + node _T_1451 = and(_T_1450, _T_1419) @[el2_dec_dec_ctl.scala 17:17] + node _T_1452 = and(_T_1451, _T_1421) @[el2_dec_dec_ctl.scala 17:17] + node _T_1453 = and(_T_1452, _T_1423) @[el2_dec_dec_ctl.scala 17:17] + node _T_1454 = and(_T_1453, _T_1425) @[el2_dec_dec_ctl.scala 17:17] + node _T_1455 = and(_T_1454, _T_1426) @[el2_dec_dec_ctl.scala 17:17] + node _T_1456 = and(_T_1455, _T_1427) @[el2_dec_dec_ctl.scala 17:17] + node _T_1457 = and(_T_1456, _T_1429) @[el2_dec_dec_ctl.scala 17:17] + node _T_1458 = and(_T_1457, _T_1431) @[el2_dec_dec_ctl.scala 17:17] + node _T_1459 = and(_T_1458, _T_1432) @[el2_dec_dec_ctl.scala 17:17] + node _T_1460 = and(_T_1459, _T_1433) @[el2_dec_dec_ctl.scala 17:17] + node _T_1461 = or(_T_1381, _T_1460) @[el2_dec_dec_ctl.scala 102:122] + node _T_1462 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1463 = eq(_T_1462, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1464 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1465 = eq(_T_1464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1466 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1467 = eq(_T_1466, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1468 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1469 = eq(_T_1468, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1470 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1471 = eq(_T_1470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1472 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1473 = eq(_T_1472, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1474 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1475 = eq(_T_1474, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1476 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1478 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1479 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1481 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1482 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1483 = and(_T_1463, _T_1465) @[el2_dec_dec_ctl.scala 17:17] + node _T_1484 = and(_T_1483, _T_1467) @[el2_dec_dec_ctl.scala 17:17] + node _T_1485 = and(_T_1484, _T_1469) @[el2_dec_dec_ctl.scala 17:17] + node _T_1486 = and(_T_1485, _T_1471) @[el2_dec_dec_ctl.scala 17:17] + node _T_1487 = and(_T_1486, _T_1473) @[el2_dec_dec_ctl.scala 17:17] + node _T_1488 = and(_T_1487, _T_1475) @[el2_dec_dec_ctl.scala 17:17] + node _T_1489 = and(_T_1488, _T_1477) @[el2_dec_dec_ctl.scala 17:17] + node _T_1490 = and(_T_1489, _T_1478) @[el2_dec_dec_ctl.scala 17:17] + node _T_1491 = and(_T_1490, _T_1480) @[el2_dec_dec_ctl.scala 17:17] + node _T_1492 = and(_T_1491, _T_1481) @[el2_dec_dec_ctl.scala 17:17] + node _T_1493 = and(_T_1492, _T_1482) @[el2_dec_dec_ctl.scala 17:17] + node _T_1494 = or(_T_1461, _T_1493) @[el2_dec_dec_ctl.scala 103:119] + node _T_1495 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1497 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1499 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1500 = eq(_T_1499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1501 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1502 = eq(_T_1501, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1503 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1504 = eq(_T_1503, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1505 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1506 = eq(_T_1505, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1507 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1508 = eq(_T_1507, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1509 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1511 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1513 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1515 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1517 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1519 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1520 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1521 = and(_T_1496, _T_1498) @[el2_dec_dec_ctl.scala 17:17] + node _T_1522 = and(_T_1521, _T_1500) @[el2_dec_dec_ctl.scala 17:17] + node _T_1523 = and(_T_1522, _T_1502) @[el2_dec_dec_ctl.scala 17:17] + node _T_1524 = and(_T_1523, _T_1504) @[el2_dec_dec_ctl.scala 17:17] + node _T_1525 = and(_T_1524, _T_1506) @[el2_dec_dec_ctl.scala 17:17] + node _T_1526 = and(_T_1525, _T_1508) @[el2_dec_dec_ctl.scala 17:17] + node _T_1527 = and(_T_1526, _T_1510) @[el2_dec_dec_ctl.scala 17:17] + node _T_1528 = and(_T_1527, _T_1512) @[el2_dec_dec_ctl.scala 17:17] + node _T_1529 = and(_T_1528, _T_1514) @[el2_dec_dec_ctl.scala 17:17] + node _T_1530 = and(_T_1529, _T_1516) @[el2_dec_dec_ctl.scala 17:17] + node _T_1531 = and(_T_1530, _T_1518) @[el2_dec_dec_ctl.scala 17:17] + node _T_1532 = and(_T_1531, _T_1519) @[el2_dec_dec_ctl.scala 17:17] + node _T_1533 = and(_T_1532, _T_1520) @[el2_dec_dec_ctl.scala 17:17] + node _T_1534 = or(_T_1494, _T_1533) @[el2_dec_dec_ctl.scala 104:60] + node _T_1535 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1536 = eq(_T_1535, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1537 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1538 = eq(_T_1537, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1539 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1541 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1542 = eq(_T_1541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1543 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1544 = eq(_T_1543, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1545 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1547 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_1548 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1550 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_1551 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1552 = eq(_T_1551, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1553 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1554 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1556 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1557 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1558 = and(_T_1536, _T_1538) @[el2_dec_dec_ctl.scala 17:17] + node _T_1559 = and(_T_1558, _T_1540) @[el2_dec_dec_ctl.scala 17:17] + node _T_1560 = and(_T_1559, _T_1542) @[el2_dec_dec_ctl.scala 17:17] + node _T_1561 = and(_T_1560, _T_1544) @[el2_dec_dec_ctl.scala 17:17] + node _T_1562 = and(_T_1561, _T_1546) @[el2_dec_dec_ctl.scala 17:17] + node _T_1563 = and(_T_1562, _T_1547) @[el2_dec_dec_ctl.scala 17:17] + node _T_1564 = and(_T_1563, _T_1549) @[el2_dec_dec_ctl.scala 17:17] + node _T_1565 = and(_T_1564, _T_1550) @[el2_dec_dec_ctl.scala 17:17] + node _T_1566 = and(_T_1565, _T_1552) @[el2_dec_dec_ctl.scala 17:17] + node _T_1567 = and(_T_1566, _T_1553) @[el2_dec_dec_ctl.scala 17:17] + node _T_1568 = and(_T_1567, _T_1555) @[el2_dec_dec_ctl.scala 17:17] + node _T_1569 = and(_T_1568, _T_1556) @[el2_dec_dec_ctl.scala 17:17] + node _T_1570 = and(_T_1569, _T_1557) @[el2_dec_dec_ctl.scala 17:17] + node _T_1571 = or(_T_1534, _T_1570) @[el2_dec_dec_ctl.scala 105:69] + node _T_1572 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1574 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1575 = eq(_T_1574, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1576 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1577 = eq(_T_1576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1578 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1579 = eq(_T_1578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1580 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1581 = eq(_T_1580, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1582 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1584 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1586 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1587 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1588 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1590 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1591 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1592 = and(_T_1573, _T_1575) @[el2_dec_dec_ctl.scala 17:17] + node _T_1593 = and(_T_1592, _T_1577) @[el2_dec_dec_ctl.scala 17:17] + node _T_1594 = and(_T_1593, _T_1579) @[el2_dec_dec_ctl.scala 17:17] + node _T_1595 = and(_T_1594, _T_1581) @[el2_dec_dec_ctl.scala 17:17] + node _T_1596 = and(_T_1595, _T_1583) @[el2_dec_dec_ctl.scala 17:17] + node _T_1597 = and(_T_1596, _T_1585) @[el2_dec_dec_ctl.scala 17:17] + node _T_1598 = and(_T_1597, _T_1586) @[el2_dec_dec_ctl.scala 17:17] + node _T_1599 = and(_T_1598, _T_1587) @[el2_dec_dec_ctl.scala 17:17] + node _T_1600 = and(_T_1599, _T_1589) @[el2_dec_dec_ctl.scala 17:17] + node _T_1601 = and(_T_1600, _T_1590) @[el2_dec_dec_ctl.scala 17:17] + node _T_1602 = and(_T_1601, _T_1591) @[el2_dec_dec_ctl.scala 17:17] + node _T_1603 = or(_T_1571, _T_1602) @[el2_dec_dec_ctl.scala 106:66] + node _T_1604 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1606 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1607 = eq(_T_1606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1608 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1609 = eq(_T_1608, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1610 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1611 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1612 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1613 = eq(_T_1612, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1614 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1615 = eq(_T_1614, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1616 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1617 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1618 = and(_T_1605, _T_1607) @[el2_dec_dec_ctl.scala 17:17] + node _T_1619 = and(_T_1618, _T_1609) @[el2_dec_dec_ctl.scala 17:17] + node _T_1620 = and(_T_1619, _T_1610) @[el2_dec_dec_ctl.scala 17:17] + node _T_1621 = and(_T_1620, _T_1611) @[el2_dec_dec_ctl.scala 17:17] + node _T_1622 = and(_T_1621, _T_1613) @[el2_dec_dec_ctl.scala 17:17] + node _T_1623 = and(_T_1622, _T_1615) @[el2_dec_dec_ctl.scala 17:17] + node _T_1624 = and(_T_1623, _T_1616) @[el2_dec_dec_ctl.scala 17:17] + node _T_1625 = and(_T_1624, _T_1617) @[el2_dec_dec_ctl.scala 17:17] + node _T_1626 = or(_T_1603, _T_1625) @[el2_dec_dec_ctl.scala 107:58] + node _T_1627 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_1628 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1629 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1630 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1631 = eq(_T_1630, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1632 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1633 = eq(_T_1632, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1634 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1636 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1637 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1638 = and(_T_1627, _T_1628) @[el2_dec_dec_ctl.scala 17:17] + node _T_1639 = and(_T_1638, _T_1629) @[el2_dec_dec_ctl.scala 17:17] + node _T_1640 = and(_T_1639, _T_1631) @[el2_dec_dec_ctl.scala 17:17] + node _T_1641 = and(_T_1640, _T_1633) @[el2_dec_dec_ctl.scala 17:17] + node _T_1642 = and(_T_1641, _T_1635) @[el2_dec_dec_ctl.scala 17:17] + node _T_1643 = and(_T_1642, _T_1636) @[el2_dec_dec_ctl.scala 17:17] + node _T_1644 = and(_T_1643, _T_1637) @[el2_dec_dec_ctl.scala 17:17] + node _T_1645 = or(_T_1626, _T_1644) @[el2_dec_dec_ctl.scala 108:46] + node _T_1646 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1647 = eq(_T_1646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1648 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1650 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1652 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1653 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1654 = eq(_T_1653, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1655 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1656 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1657 = and(_T_1647, _T_1649) @[el2_dec_dec_ctl.scala 17:17] + node _T_1658 = and(_T_1657, _T_1651) @[el2_dec_dec_ctl.scala 17:17] + node _T_1659 = and(_T_1658, _T_1652) @[el2_dec_dec_ctl.scala 17:17] + node _T_1660 = and(_T_1659, _T_1654) @[el2_dec_dec_ctl.scala 17:17] + node _T_1661 = and(_T_1660, _T_1655) @[el2_dec_dec_ctl.scala 17:17] + node _T_1662 = and(_T_1661, _T_1656) @[el2_dec_dec_ctl.scala 17:17] + node _T_1663 = or(_T_1645, _T_1662) @[el2_dec_dec_ctl.scala 109:40] + node _T_1664 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1665 = eq(_T_1664, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1666 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1668 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1669 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1671 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1672 = eq(_T_1671, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1673 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1674 = eq(_T_1673, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1675 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1676 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1677 = and(_T_1665, _T_1667) @[el2_dec_dec_ctl.scala 17:17] + node _T_1678 = and(_T_1677, _T_1668) @[el2_dec_dec_ctl.scala 17:17] + node _T_1679 = and(_T_1678, _T_1670) @[el2_dec_dec_ctl.scala 17:17] + node _T_1680 = and(_T_1679, _T_1672) @[el2_dec_dec_ctl.scala 17:17] + node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 17:17] + node _T_1682 = and(_T_1681, _T_1675) @[el2_dec_dec_ctl.scala 17:17] + node _T_1683 = and(_T_1682, _T_1676) @[el2_dec_dec_ctl.scala 17:17] + node _T_1684 = or(_T_1663, _T_1683) @[el2_dec_dec_ctl.scala 110:39] + node _T_1685 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_1686 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1687 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1688 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1689 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1691 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1693 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1694 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1695 = and(_T_1685, _T_1686) @[el2_dec_dec_ctl.scala 17:17] + node _T_1696 = and(_T_1695, _T_1687) @[el2_dec_dec_ctl.scala 17:17] + node _T_1697 = and(_T_1696, _T_1688) @[el2_dec_dec_ctl.scala 17:17] + node _T_1698 = and(_T_1697, _T_1690) @[el2_dec_dec_ctl.scala 17:17] + node _T_1699 = and(_T_1698, _T_1692) @[el2_dec_dec_ctl.scala 17:17] + node _T_1700 = and(_T_1699, _T_1693) @[el2_dec_dec_ctl.scala 17:17] + node _T_1701 = and(_T_1700, _T_1694) @[el2_dec_dec_ctl.scala 17:17] + node _T_1702 = or(_T_1684, _T_1701) @[el2_dec_dec_ctl.scala 111:43] + node _T_1703 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1704 = eq(_T_1703, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1705 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1706 = eq(_T_1705, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1707 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1708 = eq(_T_1707, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1709 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1711 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1712 = eq(_T_1711, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1713 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1714 = eq(_T_1713, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1715 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1717 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1718 = eq(_T_1717, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1719 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1720 = eq(_T_1719, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1721 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1722 = eq(_T_1721, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1723 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_1724 = eq(_T_1723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1725 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53] + node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1727 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1729 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1731 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1733 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1735 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1737 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1739 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1741 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1743 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1745 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1747 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1749 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1753 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1755 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1757 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1758 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1759 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1760 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1761 = and(_T_1704, _T_1706) @[el2_dec_dec_ctl.scala 17:17] + node _T_1762 = and(_T_1761, _T_1708) @[el2_dec_dec_ctl.scala 17:17] + node _T_1763 = and(_T_1762, _T_1710) @[el2_dec_dec_ctl.scala 17:17] + node _T_1764 = and(_T_1763, _T_1712) @[el2_dec_dec_ctl.scala 17:17] + node _T_1765 = and(_T_1764, _T_1714) @[el2_dec_dec_ctl.scala 17:17] + node _T_1766 = and(_T_1765, _T_1716) @[el2_dec_dec_ctl.scala 17:17] + node _T_1767 = and(_T_1766, _T_1718) @[el2_dec_dec_ctl.scala 17:17] + node _T_1768 = and(_T_1767, _T_1720) @[el2_dec_dec_ctl.scala 17:17] + node _T_1769 = and(_T_1768, _T_1722) @[el2_dec_dec_ctl.scala 17:17] + node _T_1770 = and(_T_1769, _T_1724) @[el2_dec_dec_ctl.scala 17:17] + node _T_1771 = and(_T_1770, _T_1726) @[el2_dec_dec_ctl.scala 17:17] + node _T_1772 = and(_T_1771, _T_1728) @[el2_dec_dec_ctl.scala 17:17] + node _T_1773 = and(_T_1772, _T_1730) @[el2_dec_dec_ctl.scala 17:17] + node _T_1774 = and(_T_1773, _T_1732) @[el2_dec_dec_ctl.scala 17:17] + node _T_1775 = and(_T_1774, _T_1734) @[el2_dec_dec_ctl.scala 17:17] + node _T_1776 = and(_T_1775, _T_1736) @[el2_dec_dec_ctl.scala 17:17] + node _T_1777 = and(_T_1776, _T_1738) @[el2_dec_dec_ctl.scala 17:17] + node _T_1778 = and(_T_1777, _T_1740) @[el2_dec_dec_ctl.scala 17:17] + node _T_1779 = and(_T_1778, _T_1742) @[el2_dec_dec_ctl.scala 17:17] + node _T_1780 = and(_T_1779, _T_1744) @[el2_dec_dec_ctl.scala 17:17] + node _T_1781 = and(_T_1780, _T_1746) @[el2_dec_dec_ctl.scala 17:17] + node _T_1782 = and(_T_1781, _T_1748) @[el2_dec_dec_ctl.scala 17:17] + node _T_1783 = and(_T_1782, _T_1750) @[el2_dec_dec_ctl.scala 17:17] + node _T_1784 = and(_T_1783, _T_1752) @[el2_dec_dec_ctl.scala 17:17] + node _T_1785 = and(_T_1784, _T_1754) @[el2_dec_dec_ctl.scala 17:17] + node _T_1786 = and(_T_1785, _T_1756) @[el2_dec_dec_ctl.scala 17:17] + node _T_1787 = and(_T_1786, _T_1757) @[el2_dec_dec_ctl.scala 17:17] + node _T_1788 = and(_T_1787, _T_1758) @[el2_dec_dec_ctl.scala 17:17] + node _T_1789 = and(_T_1788, _T_1759) @[el2_dec_dec_ctl.scala 17:17] + node _T_1790 = and(_T_1789, _T_1760) @[el2_dec_dec_ctl.scala 17:17] + node _T_1791 = or(_T_1702, _T_1790) @[el2_dec_dec_ctl.scala 112:39] + node _T_1792 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1793 = eq(_T_1792, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1794 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1796 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1797 = eq(_T_1796, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1798 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1799 = eq(_T_1798, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1800 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1802 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1803 = eq(_T_1802, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1804 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1805 = eq(_T_1804, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1806 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1807 = eq(_T_1806, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1808 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1809 = eq(_T_1808, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1810 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1811 = eq(_T_1810, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1812 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1813 = eq(_T_1812, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1815 = eq(_T_1814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1816 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1817 = eq(_T_1816, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1818 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1820 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1822 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1824 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1826 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1828 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1830 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1832 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1833 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1834 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1835 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1836 = and(_T_1793, _T_1795) @[el2_dec_dec_ctl.scala 17:17] + node _T_1837 = and(_T_1836, _T_1797) @[el2_dec_dec_ctl.scala 17:17] + node _T_1838 = and(_T_1837, _T_1799) @[el2_dec_dec_ctl.scala 17:17] + node _T_1839 = and(_T_1838, _T_1801) @[el2_dec_dec_ctl.scala 17:17] + node _T_1840 = and(_T_1839, _T_1803) @[el2_dec_dec_ctl.scala 17:17] + node _T_1841 = and(_T_1840, _T_1805) @[el2_dec_dec_ctl.scala 17:17] + node _T_1842 = and(_T_1841, _T_1807) @[el2_dec_dec_ctl.scala 17:17] + node _T_1843 = and(_T_1842, _T_1809) @[el2_dec_dec_ctl.scala 17:17] + node _T_1844 = and(_T_1843, _T_1811) @[el2_dec_dec_ctl.scala 17:17] + node _T_1845 = and(_T_1844, _T_1813) @[el2_dec_dec_ctl.scala 17:17] + node _T_1846 = and(_T_1845, _T_1815) @[el2_dec_dec_ctl.scala 17:17] + node _T_1847 = and(_T_1846, _T_1817) @[el2_dec_dec_ctl.scala 17:17] + node _T_1848 = and(_T_1847, _T_1819) @[el2_dec_dec_ctl.scala 17:17] + node _T_1849 = and(_T_1848, _T_1821) @[el2_dec_dec_ctl.scala 17:17] + node _T_1850 = and(_T_1849, _T_1823) @[el2_dec_dec_ctl.scala 17:17] + node _T_1851 = and(_T_1850, _T_1825) @[el2_dec_dec_ctl.scala 17:17] + node _T_1852 = and(_T_1851, _T_1827) @[el2_dec_dec_ctl.scala 17:17] + node _T_1853 = and(_T_1852, _T_1829) @[el2_dec_dec_ctl.scala 17:17] + node _T_1854 = and(_T_1853, _T_1831) @[el2_dec_dec_ctl.scala 17:17] + node _T_1855 = and(_T_1854, _T_1832) @[el2_dec_dec_ctl.scala 17:17] + node _T_1856 = and(_T_1855, _T_1833) @[el2_dec_dec_ctl.scala 17:17] + node _T_1857 = and(_T_1856, _T_1834) @[el2_dec_dec_ctl.scala 17:17] + node _T_1858 = and(_T_1857, _T_1835) @[el2_dec_dec_ctl.scala 17:17] + node _T_1859 = or(_T_1791, _T_1858) @[el2_dec_dec_ctl.scala 113:130] + node _T_1860 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1861 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1862 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1864 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1866 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1867 = eq(_T_1866, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1868 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1869 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1870 = and(_T_1860, _T_1861) @[el2_dec_dec_ctl.scala 17:17] + node _T_1871 = and(_T_1870, _T_1862) @[el2_dec_dec_ctl.scala 17:17] + node _T_1872 = and(_T_1871, _T_1863) @[el2_dec_dec_ctl.scala 17:17] + node _T_1873 = and(_T_1872, _T_1865) @[el2_dec_dec_ctl.scala 17:17] + node _T_1874 = and(_T_1873, _T_1867) @[el2_dec_dec_ctl.scala 17:17] + node _T_1875 = and(_T_1874, _T_1868) @[el2_dec_dec_ctl.scala 17:17] + node _T_1876 = and(_T_1875, _T_1869) @[el2_dec_dec_ctl.scala 17:17] + node _T_1877 = or(_T_1859, _T_1876) @[el2_dec_dec_ctl.scala 114:102] + node _T_1878 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1879 = eq(_T_1878, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1880 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1881 = eq(_T_1880, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1882 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1883 = eq(_T_1882, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1884 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1885 = eq(_T_1884, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1886 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1887 = eq(_T_1886, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1888 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1889 = eq(_T_1888, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1890 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1891 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1892 = and(_T_1879, _T_1881) @[el2_dec_dec_ctl.scala 17:17] + node _T_1893 = and(_T_1892, _T_1883) @[el2_dec_dec_ctl.scala 17:17] + node _T_1894 = and(_T_1893, _T_1885) @[el2_dec_dec_ctl.scala 17:17] + node _T_1895 = and(_T_1894, _T_1887) @[el2_dec_dec_ctl.scala 17:17] + node _T_1896 = and(_T_1895, _T_1889) @[el2_dec_dec_ctl.scala 17:17] + node _T_1897 = and(_T_1896, _T_1890) @[el2_dec_dec_ctl.scala 17:17] + node _T_1898 = and(_T_1897, _T_1891) @[el2_dec_dec_ctl.scala 17:17] + node _T_1899 = or(_T_1877, _T_1898) @[el2_dec_dec_ctl.scala 115:39] + node _T_1900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1901 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1902 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1903 = eq(_T_1902, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1904 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1905 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1906 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1907 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1908 = and(_T_1900, _T_1901) @[el2_dec_dec_ctl.scala 17:17] + node _T_1909 = and(_T_1908, _T_1903) @[el2_dec_dec_ctl.scala 17:17] + node _T_1910 = and(_T_1909, _T_1904) @[el2_dec_dec_ctl.scala 17:17] + node _T_1911 = and(_T_1910, _T_1905) @[el2_dec_dec_ctl.scala 17:17] + node _T_1912 = and(_T_1911, _T_1906) @[el2_dec_dec_ctl.scala 17:17] + node _T_1913 = and(_T_1912, _T_1907) @[el2_dec_dec_ctl.scala 17:17] + node _T_1914 = or(_T_1899, _T_1913) @[el2_dec_dec_ctl.scala 116:43] + node _T_1915 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1916 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1917 = eq(_T_1916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1918 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1920 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1921 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1922 = eq(_T_1921, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1923 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1924 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1925 = and(_T_1915, _T_1917) @[el2_dec_dec_ctl.scala 17:17] + node _T_1926 = and(_T_1925, _T_1919) @[el2_dec_dec_ctl.scala 17:17] + node _T_1927 = and(_T_1926, _T_1920) @[el2_dec_dec_ctl.scala 17:17] + node _T_1928 = and(_T_1927, _T_1922) @[el2_dec_dec_ctl.scala 17:17] + node _T_1929 = and(_T_1928, _T_1923) @[el2_dec_dec_ctl.scala 17:17] + node _T_1930 = and(_T_1929, _T_1924) @[el2_dec_dec_ctl.scala 17:17] + node _T_1931 = or(_T_1914, _T_1930) @[el2_dec_dec_ctl.scala 117:35] + node _T_1932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1934 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1935 = eq(_T_1934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1936 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1937 = eq(_T_1936, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1938 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1939 = eq(_T_1938, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1940 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1942 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1943 = eq(_T_1942, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1944 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1945 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1946 = and(_T_1933, _T_1935) @[el2_dec_dec_ctl.scala 17:17] + node _T_1947 = and(_T_1946, _T_1937) @[el2_dec_dec_ctl.scala 17:17] + node _T_1948 = and(_T_1947, _T_1939) @[el2_dec_dec_ctl.scala 17:17] + node _T_1949 = and(_T_1948, _T_1941) @[el2_dec_dec_ctl.scala 17:17] + node _T_1950 = and(_T_1949, _T_1943) @[el2_dec_dec_ctl.scala 17:17] + node _T_1951 = and(_T_1950, _T_1944) @[el2_dec_dec_ctl.scala 17:17] + node _T_1952 = and(_T_1951, _T_1945) @[el2_dec_dec_ctl.scala 17:17] + node _T_1953 = or(_T_1931, _T_1952) @[el2_dec_dec_ctl.scala 118:38] + node _T_1954 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1957 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1959 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1960 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1961 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1962 = and(_T_1955, _T_1956) @[el2_dec_dec_ctl.scala 17:17] + node _T_1963 = and(_T_1962, _T_1958) @[el2_dec_dec_ctl.scala 17:17] + node _T_1964 = and(_T_1963, _T_1959) @[el2_dec_dec_ctl.scala 17:17] + node _T_1965 = and(_T_1964, _T_1960) @[el2_dec_dec_ctl.scala 17:17] + node _T_1966 = and(_T_1965, _T_1961) @[el2_dec_dec_ctl.scala 17:17] + node _T_1967 = or(_T_1953, _T_1966) @[el2_dec_dec_ctl.scala 119:44] + io.out.legal <= _T_1967 @[el2_dec_dec_ctl.scala 101:16] extmodule gated_latch_1 : output Q : Clock @@ -2591,7 +2576,7 @@ circuit el2_dec : module el2_dec_decode_ctl : input clock : Clock input reset : AsyncReset - output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[el2_dec_decode_ctl.scala 126:27] _T.bits.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] @@ -2642,11 +2627,11 @@ circuit el2_dec : wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] - wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 136:17] - wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 137:17] - wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 138:17] - wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 139:20] - wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 140:17] + wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] + wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] + wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] + wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] + wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] @@ -2656,14 +2641,14 @@ circuit el2_dec : i0_rs2_depth_d <= UInt<1>("h00") wire cam_wen : UInt<4> cam_wen <= UInt<1>("h00") - wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 147:17] + wire cam : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 147:17] wire cam_write : UInt<1> cam_write <= UInt<1>("h00") wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29] wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30] wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31] - wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 152:20] - wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 153:20] + wire cam_raw : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 152:20] + wire cam_in : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 153:20] wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18] wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22] wire i0_rs1bypass : UInt<3> @@ -2800,9 +2785,9 @@ circuit el2_dec : io.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 230:43] io.dec_i0_predict_p_d.bits.pja <= i0_pja @[el2_dec_decode_ctl.scala 231:43] io.dec_i0_predict_p_d.bits.pret <= i0_pret @[el2_dec_decode_ctl.scala 232:43] - io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[el2_dec_decode_ctl.scala 233:43] + io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.prett @[el2_dec_decode_ctl.scala 233:43] io.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 234:43] - io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[el2_dec_decode_ctl.scala 235:43] + io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.hist @[el2_dec_decode_ctl.scala 235:43] node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 236:55] io.dec_i0_predict_p_d.valid <= _T_19 @[el2_dec_decode_ctl.scala 236:38] node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 237:75] @@ -2810,34 +2795,34 @@ circuit el2_dec : node _T_22 = or(_T_21, i0_pret_raw) @[el2_dec_decode_ctl.scala 237:103] node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 237:56] node i0_notbr_error = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 237:54] - node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:72] + node _T_24 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:67] node _T_25 = and(i0_brp_valid, _T_24) @[el2_dec_decode_ctl.scala 240:47] - node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:106] - node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:76] - node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:126] - node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:124] - node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[el2_dec_decode_ctl.scala 241:47] - node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:74] - node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:72] - node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:62] - node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:79] - node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:101] + node _T_26 = neq(io.dec_i0_brp.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:96] + node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:71] + node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:116] + node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:114] + node _T_29 = and(i0_brp_valid, io.dec_i0_brp.ret) @[el2_dec_decode_ctl.scala 241:47] + node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:69] + node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:67] + node _T_31 = or(io.dec_i0_brp.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:57] + node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:74] + node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:96] node _T_33 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 243:72] node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 243:94] node _T_35 = and(_T_33, _T_34) @[el2_dec_decode_ctl.scala 243:92] io.dec_i0_predict_p_d.bits.br_error <= _T_35 @[el2_dec_decode_ctl.scala 243:56] - node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:94] - node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:116] - node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:114] + node _T_36 = and(io.dec_i0_brp.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:89] + node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:111] + node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:109] io.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[el2_dec_decode_ctl.scala 244:56] io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 245:32] io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 246:32] - node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[el2_dec_decode_ctl.scala 247:47] - node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:86] - node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:84] + node _T_39 = or(i0_br_error, io.dec_i0_brp.br_start_error) @[el2_dec_decode_ctl.scala 247:47] + node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:81] + node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:79] io.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 248:49] io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 249:32] - io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[el2_dec_decode_ctl.scala 250:56] + io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.way @[el2_dec_decode_ctl.scala 250:56] node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 256:36] i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 259:9] i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 259:9] @@ -3004,13 +2989,13 @@ circuit el2_dec : node _T_44 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 274:38] node _T_45 = or(_T_44, i0_pja) @[el2_dec_decode_ctl.scala 274:49] node i0_predict_br = or(_T_45, i0_pret) @[el2_dec_decode_ctl.scala 274:58] - node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:51] - node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:55] + node _T_46 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:46] + node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:50] node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 276:26] - node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:71] - node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:51] - node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:55] - node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:71] + node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:66] + node _T_49 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:46] + node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:50] + node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:66] node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 278:20] io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 280:26] io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 281:26] @@ -3074,34 +3059,34 @@ circuit el2_dec : cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25] node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54] node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63] - node _T_89 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:48] - node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] + node _T_89 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:43] + node nonblock_load_rd = mux(_T_89, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_90 : @[Reg.scala 28:19] nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 319:56] - node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 319:56] + node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 321:66] node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45] - node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87] + node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:82] cam_inv_reset_val[0] <= _T_93 @[el2_dec_decode_ctl.scala 321:26] - node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 322:67] node _T_95 = and(cam_data_reset, _T_94) @[el2_dec_decode_ctl.scala 322:45] - node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:88] + node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:83] cam_data_reset_val[0] <= _T_96 @[el2_dec_decode_ctl.scala 322:27] - wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] - _T_97.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_97.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_97.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_97 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_97.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_97.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[0].bits.rd <= _T_97.bits.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[0].bits.tag <= _T_97.bits.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[0].bits.wb <= _T_97.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].rd <= _T_97.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].tag <= _T_97.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].wb <= _T_97.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[0].valid <= _T_97.valid @[el2_dec_decode_ctl.scala 323:14] - cam[0].bits.rd <= cam_raw[0].bits.rd @[el2_dec_decode_ctl.scala 324:11] - cam[0].bits.tag <= cam_raw[0].bits.tag @[el2_dec_decode_ctl.scala 324:11] - cam[0].bits.wb <= cam_raw[0].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[0].rd <= cam_raw[0].rd @[el2_dec_decode_ctl.scala 324:11] + cam[0].tag <= cam_raw[0].tag @[el2_dec_decode_ctl.scala 324:11] + cam[0].wb <= cam_raw[0].wb @[el2_dec_decode_ctl.scala 324:11] cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 324:11] node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_98 : @[el2_dec_decode_ctl.scala 326:39] @@ -3111,75 +3096,75 @@ circuit el2_dec : node _T_100 = bits(_T_99, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_100 : @[el2_dec_decode_ctl.scala 329:28] cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[0].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] - cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] - cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + cam_in[0].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[0].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[0].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:116] node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_103 = eq(r_d_in.i0rd, cam[0].rd) @[el2_dec_decode_ctl.scala 334:80] node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64] - node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:105] + node _T_105 = bits(cam[0].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:95] node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44] - when _T_107 : @[el2_dec_decode_ctl.scala 334:131] + when _T_107 : @[el2_dec_decode_ctl.scala 334:116] cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:116] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[0].bits.wb <= cam[0].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].rd <= cam[0].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].tag <= cam[0].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].wb <= cam[0].wb @[el2_dec_decode_ctl.scala 337:22] cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 339:79] node _T_110 = and(_T_108, _T_109) @[el2_dec_decode_ctl.scala 339:44] - node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] - node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:100] - when _T_112 : @[el2_dec_decode_ctl.scala 339:122] - cam_in[0].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] - skip @[el2_dec_decode_ctl.scala 339:122] + node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:95] + when _T_112 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[0].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] - _T_113.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_113.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_113.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_113 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_113.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_113.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47] - _T_114.bits.rd <= cam_in[0].bits.rd @[el2_dec_decode_ctl.scala 347:47] - _T_114.bits.tag <= cam_in[0].bits.tag @[el2_dec_decode_ctl.scala 347:47] - _T_114.bits.wb <= cam_in[0].bits.wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_114 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47] + _T_114.rd <= cam_in[0].rd @[el2_dec_decode_ctl.scala 347:47] + _T_114.tag <= cam_in[0].tag @[el2_dec_decode_ctl.scala 347:47] + _T_114.wb <= cam_in[0].wb @[el2_dec_decode_ctl.scala 347:47] _T_114.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[0].bits.rd <= _T_114.bits.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[0].bits.tag <= _T_114.bits.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[0].bits.wb <= _T_114.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].rd <= _T_114.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].tag <= _T_114.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].wb <= _T_114.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[0].valid <= _T_114.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:71] + node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:66] nonblock_load_write[0] <= _T_116 @[el2_dec_decode_ctl.scala 348:28] - node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 321:66] node _T_118 = and(io.lsu_nonblock_load_inv_r, _T_117) @[el2_dec_decode_ctl.scala 321:45] - node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:87] + node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:82] cam_inv_reset_val[1] <= _T_119 @[el2_dec_decode_ctl.scala 321:26] - node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 322:67] node _T_121 = and(cam_data_reset, _T_120) @[el2_dec_decode_ctl.scala 322:45] - node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:88] + node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:83] cam_data_reset_val[1] <= _T_122 @[el2_dec_decode_ctl.scala 322:27] - wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] - _T_123.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_123.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_123.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_123 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_123.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_123.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[1].bits.rd <= _T_123.bits.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[1].bits.tag <= _T_123.bits.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[1].bits.wb <= _T_123.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].rd <= _T_123.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].tag <= _T_123.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].wb <= _T_123.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[1].valid <= _T_123.valid @[el2_dec_decode_ctl.scala 323:14] - cam[1].bits.rd <= cam_raw[1].bits.rd @[el2_dec_decode_ctl.scala 324:11] - cam[1].bits.tag <= cam_raw[1].bits.tag @[el2_dec_decode_ctl.scala 324:11] - cam[1].bits.wb <= cam_raw[1].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[1].rd <= cam_raw[1].rd @[el2_dec_decode_ctl.scala 324:11] + cam[1].tag <= cam_raw[1].tag @[el2_dec_decode_ctl.scala 324:11] + cam[1].wb <= cam_raw[1].wb @[el2_dec_decode_ctl.scala 324:11] cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 324:11] node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_124 : @[el2_dec_decode_ctl.scala 326:39] @@ -3189,75 +3174,75 @@ circuit el2_dec : node _T_126 = bits(_T_125, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_126 : @[el2_dec_decode_ctl.scala 329:28] cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[1].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] - cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] - cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + cam_in[1].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[1].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[1].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:116] node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_129 = eq(r_d_in.i0rd, cam[1].rd) @[el2_dec_decode_ctl.scala 334:80] node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64] - node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:105] + node _T_131 = bits(cam[1].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:95] node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44] - when _T_133 : @[el2_dec_decode_ctl.scala 334:131] + when _T_133 : @[el2_dec_decode_ctl.scala 334:116] cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:116] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[1].bits.wb <= cam[1].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].rd <= cam[1].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].tag <= cam[1].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].wb <= cam[1].wb @[el2_dec_decode_ctl.scala 337:22] cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 339:79] node _T_136 = and(_T_134, _T_135) @[el2_dec_decode_ctl.scala 339:44] - node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] - node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:100] - when _T_138 : @[el2_dec_decode_ctl.scala 339:122] - cam_in[1].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] - skip @[el2_dec_decode_ctl.scala 339:122] + node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:95] + when _T_138 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[1].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] - _T_139.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_139.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_139.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_139 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_139.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_139.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47] - _T_140.bits.rd <= cam_in[1].bits.rd @[el2_dec_decode_ctl.scala 347:47] - _T_140.bits.tag <= cam_in[1].bits.tag @[el2_dec_decode_ctl.scala 347:47] - _T_140.bits.wb <= cam_in[1].bits.wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_140 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47] + _T_140.rd <= cam_in[1].rd @[el2_dec_decode_ctl.scala 347:47] + _T_140.tag <= cam_in[1].tag @[el2_dec_decode_ctl.scala 347:47] + _T_140.wb <= cam_in[1].wb @[el2_dec_decode_ctl.scala 347:47] _T_140.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[1].bits.rd <= _T_140.bits.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[1].bits.tag <= _T_140.bits.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[1].bits.wb <= _T_140.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].rd <= _T_140.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].tag <= _T_140.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].wb <= _T_140.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[1].valid <= _T_140.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:71] + node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:66] nonblock_load_write[1] <= _T_142 @[el2_dec_decode_ctl.scala 348:28] - node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 321:66] node _T_144 = and(io.lsu_nonblock_load_inv_r, _T_143) @[el2_dec_decode_ctl.scala 321:45] - node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:87] + node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:82] cam_inv_reset_val[2] <= _T_145 @[el2_dec_decode_ctl.scala 321:26] - node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 322:67] node _T_147 = and(cam_data_reset, _T_146) @[el2_dec_decode_ctl.scala 322:45] - node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:88] + node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:83] cam_data_reset_val[2] <= _T_148 @[el2_dec_decode_ctl.scala 322:27] - wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] - _T_149.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_149.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_149.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_149 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_149.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_149.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[2].bits.rd <= _T_149.bits.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[2].bits.tag <= _T_149.bits.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[2].bits.wb <= _T_149.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].rd <= _T_149.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].tag <= _T_149.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].wb <= _T_149.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[2].valid <= _T_149.valid @[el2_dec_decode_ctl.scala 323:14] - cam[2].bits.rd <= cam_raw[2].bits.rd @[el2_dec_decode_ctl.scala 324:11] - cam[2].bits.tag <= cam_raw[2].bits.tag @[el2_dec_decode_ctl.scala 324:11] - cam[2].bits.wb <= cam_raw[2].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[2].rd <= cam_raw[2].rd @[el2_dec_decode_ctl.scala 324:11] + cam[2].tag <= cam_raw[2].tag @[el2_dec_decode_ctl.scala 324:11] + cam[2].wb <= cam_raw[2].wb @[el2_dec_decode_ctl.scala 324:11] cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 324:11] node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_150 : @[el2_dec_decode_ctl.scala 326:39] @@ -3267,75 +3252,75 @@ circuit el2_dec : node _T_152 = bits(_T_151, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_152 : @[el2_dec_decode_ctl.scala 329:28] cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[2].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] - cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] - cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + cam_in[2].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[2].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[2].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:116] node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_155 = eq(r_d_in.i0rd, cam[2].rd) @[el2_dec_decode_ctl.scala 334:80] node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64] - node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:105] + node _T_157 = bits(cam[2].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:95] node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44] - when _T_159 : @[el2_dec_decode_ctl.scala 334:131] + when _T_159 : @[el2_dec_decode_ctl.scala 334:116] cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:116] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[2].bits.wb <= cam[2].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].rd <= cam[2].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].tag <= cam[2].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].wb <= cam[2].wb @[el2_dec_decode_ctl.scala 337:22] cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 339:79] node _T_162 = and(_T_160, _T_161) @[el2_dec_decode_ctl.scala 339:44] - node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] - node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:100] - when _T_164 : @[el2_dec_decode_ctl.scala 339:122] - cam_in[2].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] - skip @[el2_dec_decode_ctl.scala 339:122] + node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:95] + when _T_164 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[2].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] - _T_165.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_165.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_165.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_165 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_165.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_165.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47] - _T_166.bits.rd <= cam_in[2].bits.rd @[el2_dec_decode_ctl.scala 347:47] - _T_166.bits.tag <= cam_in[2].bits.tag @[el2_dec_decode_ctl.scala 347:47] - _T_166.bits.wb <= cam_in[2].bits.wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_166 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47] + _T_166.rd <= cam_in[2].rd @[el2_dec_decode_ctl.scala 347:47] + _T_166.tag <= cam_in[2].tag @[el2_dec_decode_ctl.scala 347:47] + _T_166.wb <= cam_in[2].wb @[el2_dec_decode_ctl.scala 347:47] _T_166.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[2].bits.rd <= _T_166.bits.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[2].bits.tag <= _T_166.bits.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[2].bits.wb <= _T_166.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].rd <= _T_166.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].tag <= _T_166.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].wb <= _T_166.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[2].valid <= _T_166.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:71] + node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:66] nonblock_load_write[2] <= _T_168 @[el2_dec_decode_ctl.scala 348:28] - node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 321:66] node _T_170 = and(io.lsu_nonblock_load_inv_r, _T_169) @[el2_dec_decode_ctl.scala 321:45] - node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:87] + node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:82] cam_inv_reset_val[3] <= _T_171 @[el2_dec_decode_ctl.scala 321:26] - node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 322:67] node _T_173 = and(cam_data_reset, _T_172) @[el2_dec_decode_ctl.scala 322:45] - node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:88] + node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:83] cam_data_reset_val[3] <= _T_174 @[el2_dec_decode_ctl.scala 322:27] - wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] - _T_175.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_175.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_175.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_175 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_175.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_175.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[3].bits.rd <= _T_175.bits.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[3].bits.tag <= _T_175.bits.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[3].bits.wb <= _T_175.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].rd <= _T_175.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].tag <= _T_175.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].wb <= _T_175.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[3].valid <= _T_175.valid @[el2_dec_decode_ctl.scala 323:14] - cam[3].bits.rd <= cam_raw[3].bits.rd @[el2_dec_decode_ctl.scala 324:11] - cam[3].bits.tag <= cam_raw[3].bits.tag @[el2_dec_decode_ctl.scala 324:11] - cam[3].bits.wb <= cam_raw[3].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[3].rd <= cam_raw[3].rd @[el2_dec_decode_ctl.scala 324:11] + cam[3].tag <= cam_raw[3].tag @[el2_dec_decode_ctl.scala 324:11] + cam[3].wb <= cam_raw[3].wb @[el2_dec_decode_ctl.scala 324:11] cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 324:11] node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_176 : @[el2_dec_decode_ctl.scala 326:39] @@ -3345,58 +3330,58 @@ circuit el2_dec : node _T_178 = bits(_T_177, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_178 : @[el2_dec_decode_ctl.scala 329:28] cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[3].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] - cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] - cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + cam_in[3].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[3].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[3].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:116] node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_181 = eq(r_d_in.i0rd, cam[3].rd) @[el2_dec_decode_ctl.scala 334:80] node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64] - node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:105] + node _T_183 = bits(cam[3].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:95] node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44] - when _T_185 : @[el2_dec_decode_ctl.scala 334:131] + when _T_185 : @[el2_dec_decode_ctl.scala 334:116] cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:116] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[3].bits.wb <= cam[3].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].rd <= cam[3].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].tag <= cam[3].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].wb <= cam[3].wb @[el2_dec_decode_ctl.scala 337:22] cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 339:79] node _T_188 = and(_T_186, _T_187) @[el2_dec_decode_ctl.scala 339:44] - node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] - node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:100] - when _T_190 : @[el2_dec_decode_ctl.scala 339:122] - cam_in[3].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] - skip @[el2_dec_decode_ctl.scala 339:122] + node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:95] + when _T_190 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[3].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] - _T_191.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_191.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_191.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_191 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_191.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_191.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47] - _T_192.bits.rd <= cam_in[3].bits.rd @[el2_dec_decode_ctl.scala 347:47] - _T_192.bits.tag <= cam_in[3].bits.tag @[el2_dec_decode_ctl.scala 347:47] - _T_192.bits.wb <= cam_in[3].bits.wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_192 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47] + _T_192.rd <= cam_in[3].rd @[el2_dec_decode_ctl.scala 347:47] + _T_192.tag <= cam_in[3].tag @[el2_dec_decode_ctl.scala 347:47] + _T_192.wb <= cam_in[3].wb @[el2_dec_decode_ctl.scala 347:47] _T_192.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[3].bits.rd <= _T_192.bits.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[3].bits.tag <= _T_192.bits.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[3].bits.wb <= _T_192.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].rd <= _T_192.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].tag <= _T_192.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].wb <= _T_192.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[3].valid <= _T_192.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71] + node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:66] nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28] io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29] - node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:49] - node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:81] + node _T_195 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:44] + node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:76] node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95] node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95] node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95] @@ -3415,40 +3400,40 @@ circuit el2_dec : i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 357:26] node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_211 = and(_T_210, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:126] - node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] - node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:141] - node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:192] - node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] - node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:207] + node _T_211 = and(_T_210, cam[0].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_213 = eq(cam[0].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:136] + node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_216 = eq(cam[0].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:197] node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_220 = and(_T_219, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:126] - node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] - node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:141] - node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:192] - node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] - node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:207] + node _T_220 = and(_T_219, cam[1].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_222 = eq(cam[1].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:136] + node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_225 = eq(cam[1].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:197] node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_229 = and(_T_228, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:126] - node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] - node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:141] - node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:192] - node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] - node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:207] + node _T_229 = and(_T_228, cam[2].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_231 = eq(cam[2].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:136] + node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_234 = eq(cam[2].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:197] node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_238 = and(_T_237, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:126] - node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] - node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:141] - node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:192] - node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] - node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:207] + node _T_238 = and(_T_237, cam[3].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_240 = eq(cam[3].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:136] + node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_243 = eq(cam[3].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:197] node _T_245 = or(_T_211, _T_220) @[el2_dec_decode_ctl.scala 360:69] node _T_246 = or(_T_245, _T_229) @[el2_dec_decode_ctl.scala 360:69] node waddr = or(_T_246, _T_238) @[el2_dec_decode_ctl.scala 360:69] @@ -3701,18 +3686,18 @@ circuit el2_dec : io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24] node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30] io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24] - io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 467:23] - node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 471:39] - node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:53] - node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:51] + io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 467:23] + node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 471:34] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:50] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:48] io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20] - node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:50] - node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:85] - node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:64] - node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 474:100] - node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 474:118] - node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:132] - node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:130] + node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:45] + node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:75] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:59] + node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 474:90] + node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 474:103] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:119] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:117] io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27] reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52] csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52] @@ -3859,11 +3844,11 @@ circuit el2_dec : reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_429 <= write_csr_data_in @[el2_lib.scala 514:16] write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18] - node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:49] + node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:44] node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30] io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24] - node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:43] - node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:63] + node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 516:38] + node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 516:53] node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67] node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48] node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67] @@ -3983,8 +3968,8 @@ circuit el2_dec : io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29] node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46] io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29] - node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 564:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] + node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 564:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37] presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22] reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53] @@ -3993,7 +3978,7 @@ circuit el2_dec : node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56] node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54] node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39] - node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 570:88] + node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 570:88] node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69] ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15] node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50] @@ -4004,8 +3989,8 @@ circuit el2_dec : mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16] node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40] div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16] - node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:45] - node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 578:43] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:47] + node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 578:45] io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29] d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26] node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40] @@ -4142,7 +4127,7 @@ circuit el2_dec : r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10] r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10] r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10] - node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 607:61] + node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 607:56] wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48] _T_537[0] <= _T_536 @[el2_lib.scala 162:48] _T_537[1] <= _T_536 @[el2_lib.scala 162:48] @@ -4151,8 +4136,8 @@ circuit el2_dec : node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] - node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:82] - node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:105] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:72] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:95] r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33] r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33] node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35] @@ -4189,7 +4174,7 @@ circuit el2_dec : io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39] - node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 613:58] + node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 613:53] io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39] reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52] _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52] @@ -4509,22 +4494,22 @@ circuit el2_dec : io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27] node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27] - d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:34] - node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:50] - d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:34] - d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:27] - node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:50] - d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:34] - node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50] - d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:34] - node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:50] - d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:34] - node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:61] - d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:34] - node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:58] - d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:34] - node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:40] - d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:34] + d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:29] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:45] + d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:29] + d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:29] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:45] + d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:29] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:45] + d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:29] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:45] + d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:29] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:56] + d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:29] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:53] + d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:29] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:35] + d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:29] node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 518:23] rvclkhdr_7.clock <= clock @@ -4532,55 +4517,55 @@ circuit el2_dec : rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_730 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_730.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_730.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] - _T_731.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16] - _T_731.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16] - _T_731.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16] - _T_731.bits.i0v <= d_d.bits.i0v @[el2_lib.scala 524:16] - _T_731.bits.i0div <= d_d.bits.i0div @[el2_lib.scala 524:16] - _T_731.bits.i0store <= d_d.bits.i0store @[el2_lib.scala 524:16] - _T_731.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16] - _T_731.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16] - _T_731.valid <= d_d.valid @[el2_lib.scala 524:16] - x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 677:7] - x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 677:7] - wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 678:20] - x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 679:10] - x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 679:10] - node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:49] - node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:47] - node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:78] - node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:76] - x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:27] - node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:35] - node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 681:33] - node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:64] - node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:62] - x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 681:20] + wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] + _T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 524:16] + _T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 524:16] + _T_731.csrwen <= d_d.csrwen @[el2_lib.scala 524:16] + _T_731.i0valid <= d_d.i0valid @[el2_lib.scala 524:16] + _T_731.i0v <= d_d.i0v @[el2_lib.scala 524:16] + _T_731.i0div <= d_d.i0div @[el2_lib.scala 524:16] + _T_731.i0store <= d_d.i0store @[el2_lib.scala 524:16] + _T_731.i0load <= d_d.i0load @[el2_lib.scala 524:16] + _T_731.i0rd <= d_d.i0rd @[el2_lib.scala 524:16] + x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 677:7] + x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 677:7] + x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 677:7] + x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 677:7] + x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 677:7] + x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 677:7] + x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 677:7] + wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 678:20] + x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 679:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:39] + node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:37] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:68] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:66] + x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:22] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:39] + node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 681:37] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:68] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:66] + x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 681:22] node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 518:23] rvclkhdr_8.clock <= clock @@ -4588,57 +4573,57 @@ circuit el2_dec : rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_741 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_741.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_741.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] - _T_742.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_742.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_742.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_742.bits.i0v <= x_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_742.bits.i0div <= x_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_742.bits.i0store <= x_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_742.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_742.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_742.valid <= x_d_in.valid @[el2_lib.scala 524:16] - r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 683:7] - r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 683:7] - r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 684:10] - r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 685:22] - node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:51] - node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:49] - r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:27] - node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:37] - node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 688:35] - r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 688:20] - node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:51] - node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:49] - r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:27] - node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:51] - node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:49] - r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:27] + wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] + _T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 524:16] + _T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 524:16] + _T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 524:16] + _T_742.i0v <= x_d_in.i0v @[el2_lib.scala 524:16] + _T_742.i0div <= x_d_in.i0div @[el2_lib.scala 524:16] + _T_742.i0store <= x_d_in.i0store @[el2_lib.scala 524:16] + _T_742.i0load <= x_d_in.i0load @[el2_lib.scala 524:16] + _T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 524:16] + r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 683:7] + r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 683:7] + r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 683:7] + r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 683:7] + r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 683:7] + r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 683:7] + r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 683:7] + r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 685:17] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:41] + node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:39] + r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:22] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:41] + node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 688:39] + r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 688:22] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:41] + node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:39] + r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:22] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:41] + node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:39] + r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:22] node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 518:23] rvclkhdr_9.clock <= clock @@ -4646,43 +4631,43 @@ circuit el2_dec : rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_752 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_752.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_752.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] - _T_753.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_753.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_753.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_753.bits.i0v <= r_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_753.bits.i0div <= r_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_753.bits.i0store <= r_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_753.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_753.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_753.valid <= r_d_in.valid @[el2_lib.scala 524:16] - wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 692:7] - wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 692:7] - io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 694:27] - node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:47] - node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:45] + wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] + _T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 524:16] + _T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 524:16] + _T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 524:16] + _T_753.i0v <= r_d_in.i0v @[el2_lib.scala 524:16] + _T_753.i0div <= r_d_in.i0div @[el2_lib.scala 524:16] + _T_753.i0store <= r_d_in.i0store @[el2_lib.scala 524:16] + _T_753.i0load <= r_d_in.i0load @[el2_lib.scala 524:16] + _T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 524:16] + wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 692:7] + wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 692:7] + wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 692:7] + wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 692:7] + wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 692:7] + wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 692:7] + wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 692:7] + io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 694:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:42] + node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:40] i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25] - node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] + node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47] - node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:70] - node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:68] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:65] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:63] io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32] io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26] node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57] @@ -4694,13 +4679,13 @@ circuit el2_dec : rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] - node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 705:47] - node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:66] + node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 705:42] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:56] node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32] i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26] i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26] - node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 710:42] - node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:61] + node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 710:37] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:51] node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27] i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21] node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54] @@ -4769,25 +4754,25 @@ circuit el2_dec : reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_798 <= last_br_immed_d @[el2_lib.scala 514:16] last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19] - node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 719:45] - node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 719:76] - node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:58] - node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 721:48] - node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:77] - node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:60] - node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 722:21] - node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:33] - node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:94] - node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:21] - node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:33] - node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:60] - node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:62] + node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 719:40] + node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 719:68] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:55] + node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 721:43] + node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:69] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:57] + node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 722:16] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:30] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:86] + node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 723:16] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:30] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:57] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:59] node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51] node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26] node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24] - node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:56] + node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:51] node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39] - node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:77] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:72] node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65] node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53] io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29] @@ -4927,18 +4912,18 @@ circuit el2_dec : node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51] io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25] - node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 768:48] - node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:80] - node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:63] - node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 769:48] - node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:80] - node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:63] - node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 771:48] - node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:80] - node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:63] - node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48] - node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:80] - node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:63] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 768:48] + node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:70] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:58] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 769:48] + node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:70] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:58] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 771:48] + node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:70] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:58] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:70] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:58] node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44] node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81] wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109] @@ -5847,766 +5832,927 @@ circuit el2_dec : output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, rd0 : UInt<32>, rd1 : UInt<32>, flip scan_mode : UInt<1>} wire w0v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 10:30] - wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 11:30] - wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 12:30] - wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 13:22] - wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 14:22] - wire gpr_wr_en : UInt<32> @[el2_dec_gpr_ctl.scala 15:22] - w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 16:9] - w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:9] - w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 18:9] - gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 19:13] - gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:12] - io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 21:9] - io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 22:9] - node _T = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] - node _T_1 = cat(w0v[2], _T) @[Cat.scala 29:58] - node _T_2 = cat(w0v[3], _T_1) @[Cat.scala 29:58] - node _T_3 = cat(w0v[4], _T_2) @[Cat.scala 29:58] - node _T_4 = cat(w0v[5], _T_3) @[Cat.scala 29:58] - node _T_5 = cat(w0v[6], _T_4) @[Cat.scala 29:58] - node _T_6 = cat(w0v[7], _T_5) @[Cat.scala 29:58] - node _T_7 = cat(w0v[8], _T_6) @[Cat.scala 29:58] - node _T_8 = cat(w0v[9], _T_7) @[Cat.scala 29:58] - node _T_9 = cat(w0v[10], _T_8) @[Cat.scala 29:58] - node _T_10 = cat(w0v[11], _T_9) @[Cat.scala 29:58] - node _T_11 = cat(w0v[12], _T_10) @[Cat.scala 29:58] - node _T_12 = cat(w0v[13], _T_11) @[Cat.scala 29:58] - node _T_13 = cat(w0v[14], _T_12) @[Cat.scala 29:58] - node _T_14 = cat(w0v[15], _T_13) @[Cat.scala 29:58] - node _T_15 = cat(w0v[16], _T_14) @[Cat.scala 29:58] - node _T_16 = cat(w0v[17], _T_15) @[Cat.scala 29:58] - node _T_17 = cat(w0v[18], _T_16) @[Cat.scala 29:58] - node _T_18 = cat(w0v[19], _T_17) @[Cat.scala 29:58] - node _T_19 = cat(w0v[20], _T_18) @[Cat.scala 29:58] - node _T_20 = cat(w0v[21], _T_19) @[Cat.scala 29:58] - node _T_21 = cat(w0v[22], _T_20) @[Cat.scala 29:58] - node _T_22 = cat(w0v[23], _T_21) @[Cat.scala 29:58] - node _T_23 = cat(w0v[24], _T_22) @[Cat.scala 29:58] - node _T_24 = cat(w0v[25], _T_23) @[Cat.scala 29:58] - node _T_25 = cat(w0v[26], _T_24) @[Cat.scala 29:58] - node _T_26 = cat(w0v[27], _T_25) @[Cat.scala 29:58] - node _T_27 = cat(w0v[28], _T_26) @[Cat.scala 29:58] - node _T_28 = cat(w0v[29], _T_27) @[Cat.scala 29:58] - node _T_29 = cat(w0v[30], _T_28) @[Cat.scala 29:58] - node _T_30 = cat(w0v[31], _T_29) @[Cat.scala 29:58] - node _T_31 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] - node _T_32 = cat(w1v[2], _T_31) @[Cat.scala 29:58] - node _T_33 = cat(w1v[3], _T_32) @[Cat.scala 29:58] - node _T_34 = cat(w1v[4], _T_33) @[Cat.scala 29:58] - node _T_35 = cat(w1v[5], _T_34) @[Cat.scala 29:58] - node _T_36 = cat(w1v[6], _T_35) @[Cat.scala 29:58] - node _T_37 = cat(w1v[7], _T_36) @[Cat.scala 29:58] - node _T_38 = cat(w1v[8], _T_37) @[Cat.scala 29:58] - node _T_39 = cat(w1v[9], _T_38) @[Cat.scala 29:58] - node _T_40 = cat(w1v[10], _T_39) @[Cat.scala 29:58] - node _T_41 = cat(w1v[11], _T_40) @[Cat.scala 29:58] - node _T_42 = cat(w1v[12], _T_41) @[Cat.scala 29:58] - node _T_43 = cat(w1v[13], _T_42) @[Cat.scala 29:58] - node _T_44 = cat(w1v[14], _T_43) @[Cat.scala 29:58] - node _T_45 = cat(w1v[15], _T_44) @[Cat.scala 29:58] - node _T_46 = cat(w1v[16], _T_45) @[Cat.scala 29:58] - node _T_47 = cat(w1v[17], _T_46) @[Cat.scala 29:58] - node _T_48 = cat(w1v[18], _T_47) @[Cat.scala 29:58] - node _T_49 = cat(w1v[19], _T_48) @[Cat.scala 29:58] - node _T_50 = cat(w1v[20], _T_49) @[Cat.scala 29:58] - node _T_51 = cat(w1v[21], _T_50) @[Cat.scala 29:58] - node _T_52 = cat(w1v[22], _T_51) @[Cat.scala 29:58] - node _T_53 = cat(w1v[23], _T_52) @[Cat.scala 29:58] - node _T_54 = cat(w1v[24], _T_53) @[Cat.scala 29:58] - node _T_55 = cat(w1v[25], _T_54) @[Cat.scala 29:58] - node _T_56 = cat(w1v[26], _T_55) @[Cat.scala 29:58] - node _T_57 = cat(w1v[27], _T_56) @[Cat.scala 29:58] - node _T_58 = cat(w1v[28], _T_57) @[Cat.scala 29:58] - node _T_59 = cat(w1v[29], _T_58) @[Cat.scala 29:58] - node _T_60 = cat(w1v[30], _T_59) @[Cat.scala 29:58] - node _T_61 = cat(w1v[31], _T_60) @[Cat.scala 29:58] - node _T_62 = or(_T_30, _T_61) @[el2_dec_gpr_ctl.scala 23:51] - node _T_63 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] - node _T_64 = cat(w2v[2], _T_63) @[Cat.scala 29:58] - node _T_65 = cat(w2v[3], _T_64) @[Cat.scala 29:58] - node _T_66 = cat(w2v[4], _T_65) @[Cat.scala 29:58] - node _T_67 = cat(w2v[5], _T_66) @[Cat.scala 29:58] - node _T_68 = cat(w2v[6], _T_67) @[Cat.scala 29:58] - node _T_69 = cat(w2v[7], _T_68) @[Cat.scala 29:58] - node _T_70 = cat(w2v[8], _T_69) @[Cat.scala 29:58] - node _T_71 = cat(w2v[9], _T_70) @[Cat.scala 29:58] - node _T_72 = cat(w2v[10], _T_71) @[Cat.scala 29:58] - node _T_73 = cat(w2v[11], _T_72) @[Cat.scala 29:58] - node _T_74 = cat(w2v[12], _T_73) @[Cat.scala 29:58] - node _T_75 = cat(w2v[13], _T_74) @[Cat.scala 29:58] - node _T_76 = cat(w2v[14], _T_75) @[Cat.scala 29:58] - node _T_77 = cat(w2v[15], _T_76) @[Cat.scala 29:58] - node _T_78 = cat(w2v[16], _T_77) @[Cat.scala 29:58] - node _T_79 = cat(w2v[17], _T_78) @[Cat.scala 29:58] - node _T_80 = cat(w2v[18], _T_79) @[Cat.scala 29:58] - node _T_81 = cat(w2v[19], _T_80) @[Cat.scala 29:58] - node _T_82 = cat(w2v[20], _T_81) @[Cat.scala 29:58] - node _T_83 = cat(w2v[21], _T_82) @[Cat.scala 29:58] - node _T_84 = cat(w2v[22], _T_83) @[Cat.scala 29:58] - node _T_85 = cat(w2v[23], _T_84) @[Cat.scala 29:58] - node _T_86 = cat(w2v[24], _T_85) @[Cat.scala 29:58] - node _T_87 = cat(w2v[25], _T_86) @[Cat.scala 29:58] - node _T_88 = cat(w2v[26], _T_87) @[Cat.scala 29:58] - node _T_89 = cat(w2v[27], _T_88) @[Cat.scala 29:58] - node _T_90 = cat(w2v[28], _T_89) @[Cat.scala 29:58] - node _T_91 = cat(w2v[29], _T_90) @[Cat.scala 29:58] - node _T_92 = cat(w2v[30], _T_91) @[Cat.scala 29:58] - node _T_93 = cat(w2v[31], _T_92) @[Cat.scala 29:58] - node _T_94 = or(_T_62, _T_93) @[el2_dec_gpr_ctl.scala 23:89] - gpr_wr_en <= _T_94 @[el2_dec_gpr_ctl.scala 23:12] - node _T_95 = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_96 = and(io.wen0, _T_95) @[el2_dec_gpr_ctl.scala 26:28] - w0v[1] <= _T_96 @[el2_dec_gpr_ctl.scala 26:16] - node _T_97 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_98 = and(io.wen1, _T_97) @[el2_dec_gpr_ctl.scala 27:28] - w1v[1] <= _T_98 @[el2_dec_gpr_ctl.scala 27:16] - node _T_99 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_100 = and(io.wen2, _T_99) @[el2_dec_gpr_ctl.scala 28:28] - w2v[1] <= _T_100 @[el2_dec_gpr_ctl.scala 28:16] - node _T_101 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] - node _T_102 = mux(_T_101, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_103 = and(_T_102, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_104 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] - node _T_105 = mux(_T_104, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_106 = and(_T_105, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_107 = or(_T_103, _T_106) @[el2_dec_gpr_ctl.scala 29:47] - node _T_108 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 13:30] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 16:30] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 19:22] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 22:22] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + wire gpr_wr_en : UInt<32> + gpr_wr_en <= UInt<1>("h00") + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 26:9] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 27:9] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 28:9] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 29:13] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 30:12] + io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 31:9] + io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 32:9] + node _T = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_1 = and(io.wen0, _T) @[el2_dec_gpr_ctl.scala 35:28] + w0v[1] <= _T_1 @[el2_dec_gpr_ctl.scala 35:16] + node _T_2 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_3 = and(io.wen1, _T_2) @[el2_dec_gpr_ctl.scala 36:28] + w1v[1] <= _T_3 @[el2_dec_gpr_ctl.scala 36:16] + node _T_4 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_5 = and(io.wen2, _T_4) @[el2_dec_gpr_ctl.scala 37:28] + w2v[1] <= _T_5 @[el2_dec_gpr_ctl.scala 37:16] + node _T_6 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_7 = mux(_T_6, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_8 = and(_T_7, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_9 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_10 = mux(_T_9, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_11 = and(_T_10, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_12 = or(_T_8, _T_11) @[el2_dec_gpr_ctl.scala 38:47] + node _T_13 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_14 = mux(_T_13, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_15 = and(_T_14, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_16 = or(_T_12, _T_15) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[1] <= _T_16 @[el2_dec_gpr_ctl.scala 38:16] + node _T_17 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_18 = and(io.wen0, _T_17) @[el2_dec_gpr_ctl.scala 35:28] + w0v[2] <= _T_18 @[el2_dec_gpr_ctl.scala 35:16] + node _T_19 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_20 = and(io.wen1, _T_19) @[el2_dec_gpr_ctl.scala 36:28] + w1v[2] <= _T_20 @[el2_dec_gpr_ctl.scala 36:16] + node _T_21 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_22 = and(io.wen2, _T_21) @[el2_dec_gpr_ctl.scala 37:28] + w2v[2] <= _T_22 @[el2_dec_gpr_ctl.scala 37:16] + node _T_23 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_24 = mux(_T_23, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_25 = and(_T_24, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_26 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_27 = mux(_T_26, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_28 = and(_T_27, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_29 = or(_T_25, _T_28) @[el2_dec_gpr_ctl.scala 38:47] + node _T_30 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_31 = mux(_T_30, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_32 = and(_T_31, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_33 = or(_T_29, _T_32) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[2] <= _T_33 @[el2_dec_gpr_ctl.scala 38:16] + node _T_34 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_35 = and(io.wen0, _T_34) @[el2_dec_gpr_ctl.scala 35:28] + w0v[3] <= _T_35 @[el2_dec_gpr_ctl.scala 35:16] + node _T_36 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_37 = and(io.wen1, _T_36) @[el2_dec_gpr_ctl.scala 36:28] + w1v[3] <= _T_37 @[el2_dec_gpr_ctl.scala 36:16] + node _T_38 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_39 = and(io.wen2, _T_38) @[el2_dec_gpr_ctl.scala 37:28] + w2v[3] <= _T_39 @[el2_dec_gpr_ctl.scala 37:16] + node _T_40 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_41 = mux(_T_40, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_42 = and(_T_41, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_43 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_46 = or(_T_42, _T_45) @[el2_dec_gpr_ctl.scala 38:47] + node _T_47 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_48 = mux(_T_47, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_49 = and(_T_48, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_50 = or(_T_46, _T_49) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[3] <= _T_50 @[el2_dec_gpr_ctl.scala 38:16] + node _T_51 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_52 = and(io.wen0, _T_51) @[el2_dec_gpr_ctl.scala 35:28] + w0v[4] <= _T_52 @[el2_dec_gpr_ctl.scala 35:16] + node _T_53 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_54 = and(io.wen1, _T_53) @[el2_dec_gpr_ctl.scala 36:28] + w1v[4] <= _T_54 @[el2_dec_gpr_ctl.scala 36:16] + node _T_55 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_56 = and(io.wen2, _T_55) @[el2_dec_gpr_ctl.scala 37:28] + w2v[4] <= _T_56 @[el2_dec_gpr_ctl.scala 37:16] + node _T_57 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_59 = and(_T_58, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_60 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_61 = mux(_T_60, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_62 = and(_T_61, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_63 = or(_T_59, _T_62) @[el2_dec_gpr_ctl.scala 38:47] + node _T_64 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_65 = mux(_T_64, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_66 = and(_T_65, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_67 = or(_T_63, _T_66) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[4] <= _T_67 @[el2_dec_gpr_ctl.scala 38:16] + node _T_68 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_69 = and(io.wen0, _T_68) @[el2_dec_gpr_ctl.scala 35:28] + w0v[5] <= _T_69 @[el2_dec_gpr_ctl.scala 35:16] + node _T_70 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_71 = and(io.wen1, _T_70) @[el2_dec_gpr_ctl.scala 36:28] + w1v[5] <= _T_71 @[el2_dec_gpr_ctl.scala 36:16] + node _T_72 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_73 = and(io.wen2, _T_72) @[el2_dec_gpr_ctl.scala 37:28] + w2v[5] <= _T_73 @[el2_dec_gpr_ctl.scala 37:16] + node _T_74 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_75 = mux(_T_74, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_76 = and(_T_75, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_77 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_79 = and(_T_78, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_80 = or(_T_76, _T_79) @[el2_dec_gpr_ctl.scala 38:47] + node _T_81 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_82 = mux(_T_81, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_83 = and(_T_82, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_84 = or(_T_80, _T_83) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[5] <= _T_84 @[el2_dec_gpr_ctl.scala 38:16] + node _T_85 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_86 = and(io.wen0, _T_85) @[el2_dec_gpr_ctl.scala 35:28] + w0v[6] <= _T_86 @[el2_dec_gpr_ctl.scala 35:16] + node _T_87 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_88 = and(io.wen1, _T_87) @[el2_dec_gpr_ctl.scala 36:28] + w1v[6] <= _T_88 @[el2_dec_gpr_ctl.scala 36:16] + node _T_89 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_90 = and(io.wen2, _T_89) @[el2_dec_gpr_ctl.scala 37:28] + w2v[6] <= _T_90 @[el2_dec_gpr_ctl.scala 37:16] + node _T_91 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_93 = and(_T_92, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_94 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_96 = and(_T_95, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_97 = or(_T_93, _T_96) @[el2_dec_gpr_ctl.scala 38:47] + node _T_98 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_101 = or(_T_97, _T_100) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[6] <= _T_101 @[el2_dec_gpr_ctl.scala 38:16] + node _T_102 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_103 = and(io.wen0, _T_102) @[el2_dec_gpr_ctl.scala 35:28] + w0v[7] <= _T_103 @[el2_dec_gpr_ctl.scala 35:16] + node _T_104 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_105 = and(io.wen1, _T_104) @[el2_dec_gpr_ctl.scala 36:28] + w1v[7] <= _T_105 @[el2_dec_gpr_ctl.scala 36:16] + node _T_106 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_107 = and(io.wen2, _T_106) @[el2_dec_gpr_ctl.scala 37:28] + w2v[7] <= _T_107 @[el2_dec_gpr_ctl.scala 37:16] + node _T_108 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_110 = and(_T_109, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_111 = or(_T_107, _T_110) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[1] <= _T_111 @[el2_dec_gpr_ctl.scala 29:16] - node _T_112 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_113 = and(io.wen0, _T_112) @[el2_dec_gpr_ctl.scala 26:28] - w0v[2] <= _T_113 @[el2_dec_gpr_ctl.scala 26:16] - node _T_114 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_115 = and(io.wen1, _T_114) @[el2_dec_gpr_ctl.scala 27:28] - w1v[2] <= _T_115 @[el2_dec_gpr_ctl.scala 27:16] - node _T_116 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_117 = and(io.wen2, _T_116) @[el2_dec_gpr_ctl.scala 28:28] - w2v[2] <= _T_117 @[el2_dec_gpr_ctl.scala 28:16] - node _T_118 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] - node _T_119 = mux(_T_118, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_120 = and(_T_119, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_121 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] - node _T_122 = mux(_T_121, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_123 = and(_T_122, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_124 = or(_T_120, _T_123) @[el2_dec_gpr_ctl.scala 29:47] - node _T_125 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_110 = and(_T_109, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_111 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_113 = and(_T_112, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_114 = or(_T_110, _T_113) @[el2_dec_gpr_ctl.scala 38:47] + node _T_115 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_116 = mux(_T_115, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_117 = and(_T_116, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_118 = or(_T_114, _T_117) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[7] <= _T_118 @[el2_dec_gpr_ctl.scala 38:16] + node _T_119 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_120 = and(io.wen0, _T_119) @[el2_dec_gpr_ctl.scala 35:28] + w0v[8] <= _T_120 @[el2_dec_gpr_ctl.scala 35:16] + node _T_121 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_122 = and(io.wen1, _T_121) @[el2_dec_gpr_ctl.scala 36:28] + w1v[8] <= _T_122 @[el2_dec_gpr_ctl.scala 36:16] + node _T_123 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_124 = and(io.wen2, _T_123) @[el2_dec_gpr_ctl.scala 37:28] + w2v[8] <= _T_124 @[el2_dec_gpr_ctl.scala 37:16] + node _T_125 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_127 = and(_T_126, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_128 = or(_T_124, _T_127) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[2] <= _T_128 @[el2_dec_gpr_ctl.scala 29:16] - node _T_129 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_130 = and(io.wen0, _T_129) @[el2_dec_gpr_ctl.scala 26:28] - w0v[3] <= _T_130 @[el2_dec_gpr_ctl.scala 26:16] - node _T_131 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_132 = and(io.wen1, _T_131) @[el2_dec_gpr_ctl.scala 27:28] - w1v[3] <= _T_132 @[el2_dec_gpr_ctl.scala 27:16] - node _T_133 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_134 = and(io.wen2, _T_133) @[el2_dec_gpr_ctl.scala 28:28] - w2v[3] <= _T_134 @[el2_dec_gpr_ctl.scala 28:16] - node _T_135 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] - node _T_136 = mux(_T_135, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_137 = and(_T_136, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_138 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] - node _T_139 = mux(_T_138, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_140 = and(_T_139, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_141 = or(_T_137, _T_140) @[el2_dec_gpr_ctl.scala 29:47] - node _T_142 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_127 = and(_T_126, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_128 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_130 = and(_T_129, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_131 = or(_T_127, _T_130) @[el2_dec_gpr_ctl.scala 38:47] + node _T_132 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_133 = mux(_T_132, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_134 = and(_T_133, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_135 = or(_T_131, _T_134) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[8] <= _T_135 @[el2_dec_gpr_ctl.scala 38:16] + node _T_136 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_137 = and(io.wen0, _T_136) @[el2_dec_gpr_ctl.scala 35:28] + w0v[9] <= _T_137 @[el2_dec_gpr_ctl.scala 35:16] + node _T_138 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_139 = and(io.wen1, _T_138) @[el2_dec_gpr_ctl.scala 36:28] + w1v[9] <= _T_139 @[el2_dec_gpr_ctl.scala 36:16] + node _T_140 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_141 = and(io.wen2, _T_140) @[el2_dec_gpr_ctl.scala 37:28] + w2v[9] <= _T_141 @[el2_dec_gpr_ctl.scala 37:16] + node _T_142 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_144 = and(_T_143, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_145 = or(_T_141, _T_144) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[3] <= _T_145 @[el2_dec_gpr_ctl.scala 29:16] - node _T_146 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_147 = and(io.wen0, _T_146) @[el2_dec_gpr_ctl.scala 26:28] - w0v[4] <= _T_147 @[el2_dec_gpr_ctl.scala 26:16] - node _T_148 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_149 = and(io.wen1, _T_148) @[el2_dec_gpr_ctl.scala 27:28] - w1v[4] <= _T_149 @[el2_dec_gpr_ctl.scala 27:16] - node _T_150 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_151 = and(io.wen2, _T_150) @[el2_dec_gpr_ctl.scala 28:28] - w2v[4] <= _T_151 @[el2_dec_gpr_ctl.scala 28:16] - node _T_152 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] - node _T_153 = mux(_T_152, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_154 = and(_T_153, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_155 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] - node _T_156 = mux(_T_155, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_157 = and(_T_156, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_158 = or(_T_154, _T_157) @[el2_dec_gpr_ctl.scala 29:47] - node _T_159 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_144 = and(_T_143, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_145 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_146 = mux(_T_145, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_147 = and(_T_146, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_148 = or(_T_144, _T_147) @[el2_dec_gpr_ctl.scala 38:47] + node _T_149 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_150 = mux(_T_149, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_151 = and(_T_150, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_152 = or(_T_148, _T_151) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[9] <= _T_152 @[el2_dec_gpr_ctl.scala 38:16] + node _T_153 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_154 = and(io.wen0, _T_153) @[el2_dec_gpr_ctl.scala 35:28] + w0v[10] <= _T_154 @[el2_dec_gpr_ctl.scala 35:16] + node _T_155 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_156 = and(io.wen1, _T_155) @[el2_dec_gpr_ctl.scala 36:28] + w1v[10] <= _T_156 @[el2_dec_gpr_ctl.scala 36:16] + node _T_157 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_158 = and(io.wen2, _T_157) @[el2_dec_gpr_ctl.scala 37:28] + w2v[10] <= _T_158 @[el2_dec_gpr_ctl.scala 37:16] + node _T_159 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_161 = and(_T_160, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_162 = or(_T_158, _T_161) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[4] <= _T_162 @[el2_dec_gpr_ctl.scala 29:16] - node _T_163 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_164 = and(io.wen0, _T_163) @[el2_dec_gpr_ctl.scala 26:28] - w0v[5] <= _T_164 @[el2_dec_gpr_ctl.scala 26:16] - node _T_165 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_166 = and(io.wen1, _T_165) @[el2_dec_gpr_ctl.scala 27:28] - w1v[5] <= _T_166 @[el2_dec_gpr_ctl.scala 27:16] - node _T_167 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_168 = and(io.wen2, _T_167) @[el2_dec_gpr_ctl.scala 28:28] - w2v[5] <= _T_168 @[el2_dec_gpr_ctl.scala 28:16] - node _T_169 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] - node _T_170 = mux(_T_169, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_171 = and(_T_170, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_172 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(_T_173, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_175 = or(_T_171, _T_174) @[el2_dec_gpr_ctl.scala 29:47] - node _T_176 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_161 = and(_T_160, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_162 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_163 = mux(_T_162, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_164 = and(_T_163, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_165 = or(_T_161, _T_164) @[el2_dec_gpr_ctl.scala 38:47] + node _T_166 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_167 = mux(_T_166, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_168 = and(_T_167, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_169 = or(_T_165, _T_168) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[10] <= _T_169 @[el2_dec_gpr_ctl.scala 38:16] + node _T_170 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_171 = and(io.wen0, _T_170) @[el2_dec_gpr_ctl.scala 35:28] + w0v[11] <= _T_171 @[el2_dec_gpr_ctl.scala 35:16] + node _T_172 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_173 = and(io.wen1, _T_172) @[el2_dec_gpr_ctl.scala 36:28] + w1v[11] <= _T_173 @[el2_dec_gpr_ctl.scala 36:16] + node _T_174 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_175 = and(io.wen2, _T_174) @[el2_dec_gpr_ctl.scala 37:28] + w2v[11] <= _T_175 @[el2_dec_gpr_ctl.scala 37:16] + node _T_176 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_178 = and(_T_177, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_179 = or(_T_175, _T_178) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[5] <= _T_179 @[el2_dec_gpr_ctl.scala 29:16] - node _T_180 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_181 = and(io.wen0, _T_180) @[el2_dec_gpr_ctl.scala 26:28] - w0v[6] <= _T_181 @[el2_dec_gpr_ctl.scala 26:16] - node _T_182 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_183 = and(io.wen1, _T_182) @[el2_dec_gpr_ctl.scala 27:28] - w1v[6] <= _T_183 @[el2_dec_gpr_ctl.scala 27:16] - node _T_184 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_185 = and(io.wen2, _T_184) @[el2_dec_gpr_ctl.scala 28:28] - w2v[6] <= _T_185 @[el2_dec_gpr_ctl.scala 28:16] - node _T_186 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] - node _T_187 = mux(_T_186, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_188 = and(_T_187, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_189 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] - node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_191 = and(_T_190, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_192 = or(_T_188, _T_191) @[el2_dec_gpr_ctl.scala 29:47] - node _T_193 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_178 = and(_T_177, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_179 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_180 = mux(_T_179, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_181 = and(_T_180, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_182 = or(_T_178, _T_181) @[el2_dec_gpr_ctl.scala 38:47] + node _T_183 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(_T_184, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_186 = or(_T_182, _T_185) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[11] <= _T_186 @[el2_dec_gpr_ctl.scala 38:16] + node _T_187 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_188 = and(io.wen0, _T_187) @[el2_dec_gpr_ctl.scala 35:28] + w0v[12] <= _T_188 @[el2_dec_gpr_ctl.scala 35:16] + node _T_189 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_190 = and(io.wen1, _T_189) @[el2_dec_gpr_ctl.scala 36:28] + w1v[12] <= _T_190 @[el2_dec_gpr_ctl.scala 36:16] + node _T_191 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_192 = and(io.wen2, _T_191) @[el2_dec_gpr_ctl.scala 37:28] + w2v[12] <= _T_192 @[el2_dec_gpr_ctl.scala 37:16] + node _T_193 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_195 = and(_T_194, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_196 = or(_T_192, _T_195) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[6] <= _T_196 @[el2_dec_gpr_ctl.scala 29:16] - node _T_197 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_198 = and(io.wen0, _T_197) @[el2_dec_gpr_ctl.scala 26:28] - w0v[7] <= _T_198 @[el2_dec_gpr_ctl.scala 26:16] - node _T_199 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_200 = and(io.wen1, _T_199) @[el2_dec_gpr_ctl.scala 27:28] - w1v[7] <= _T_200 @[el2_dec_gpr_ctl.scala 27:16] - node _T_201 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_202 = and(io.wen2, _T_201) @[el2_dec_gpr_ctl.scala 28:28] - w2v[7] <= _T_202 @[el2_dec_gpr_ctl.scala 28:16] - node _T_203 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] - node _T_204 = mux(_T_203, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_205 = and(_T_204, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_206 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] - node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_208 = and(_T_207, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_209 = or(_T_205, _T_208) @[el2_dec_gpr_ctl.scala 29:47] - node _T_210 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_195 = and(_T_194, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_196 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_197 = mux(_T_196, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_198 = and(_T_197, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_199 = or(_T_195, _T_198) @[el2_dec_gpr_ctl.scala 38:47] + node _T_200 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_202 = and(_T_201, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_203 = or(_T_199, _T_202) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[12] <= _T_203 @[el2_dec_gpr_ctl.scala 38:16] + node _T_204 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_205 = and(io.wen0, _T_204) @[el2_dec_gpr_ctl.scala 35:28] + w0v[13] <= _T_205 @[el2_dec_gpr_ctl.scala 35:16] + node _T_206 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_207 = and(io.wen1, _T_206) @[el2_dec_gpr_ctl.scala 36:28] + w1v[13] <= _T_207 @[el2_dec_gpr_ctl.scala 36:16] + node _T_208 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_209 = and(io.wen2, _T_208) @[el2_dec_gpr_ctl.scala 37:28] + w2v[13] <= _T_209 @[el2_dec_gpr_ctl.scala 37:16] + node _T_210 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_212 = and(_T_211, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_213 = or(_T_209, _T_212) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[7] <= _T_213 @[el2_dec_gpr_ctl.scala 29:16] - node _T_214 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_215 = and(io.wen0, _T_214) @[el2_dec_gpr_ctl.scala 26:28] - w0v[8] <= _T_215 @[el2_dec_gpr_ctl.scala 26:16] - node _T_216 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_217 = and(io.wen1, _T_216) @[el2_dec_gpr_ctl.scala 27:28] - w1v[8] <= _T_217 @[el2_dec_gpr_ctl.scala 27:16] - node _T_218 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_219 = and(io.wen2, _T_218) @[el2_dec_gpr_ctl.scala 28:28] - w2v[8] <= _T_219 @[el2_dec_gpr_ctl.scala 28:16] - node _T_220 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] - node _T_221 = mux(_T_220, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_222 = and(_T_221, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_223 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] - node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_225 = and(_T_224, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_226 = or(_T_222, _T_225) @[el2_dec_gpr_ctl.scala 29:47] - node _T_227 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_212 = and(_T_211, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_213 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_214 = mux(_T_213, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_215 = and(_T_214, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_216 = or(_T_212, _T_215) @[el2_dec_gpr_ctl.scala 38:47] + node _T_217 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_218 = mux(_T_217, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_219 = and(_T_218, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_220 = or(_T_216, _T_219) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[13] <= _T_220 @[el2_dec_gpr_ctl.scala 38:16] + node _T_221 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_222 = and(io.wen0, _T_221) @[el2_dec_gpr_ctl.scala 35:28] + w0v[14] <= _T_222 @[el2_dec_gpr_ctl.scala 35:16] + node _T_223 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_224 = and(io.wen1, _T_223) @[el2_dec_gpr_ctl.scala 36:28] + w1v[14] <= _T_224 @[el2_dec_gpr_ctl.scala 36:16] + node _T_225 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_226 = and(io.wen2, _T_225) @[el2_dec_gpr_ctl.scala 37:28] + w2v[14] <= _T_226 @[el2_dec_gpr_ctl.scala 37:16] + node _T_227 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_229 = and(_T_228, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_230 = or(_T_226, _T_229) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[8] <= _T_230 @[el2_dec_gpr_ctl.scala 29:16] - node _T_231 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_232 = and(io.wen0, _T_231) @[el2_dec_gpr_ctl.scala 26:28] - w0v[9] <= _T_232 @[el2_dec_gpr_ctl.scala 26:16] - node _T_233 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_234 = and(io.wen1, _T_233) @[el2_dec_gpr_ctl.scala 27:28] - w1v[9] <= _T_234 @[el2_dec_gpr_ctl.scala 27:16] - node _T_235 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_236 = and(io.wen2, _T_235) @[el2_dec_gpr_ctl.scala 28:28] - w2v[9] <= _T_236 @[el2_dec_gpr_ctl.scala 28:16] - node _T_237 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] - node _T_238 = mux(_T_237, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_239 = and(_T_238, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_240 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] - node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_242 = and(_T_241, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_243 = or(_T_239, _T_242) @[el2_dec_gpr_ctl.scala 29:47] - node _T_244 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_229 = and(_T_228, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_230 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_232 = and(_T_231, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_233 = or(_T_229, _T_232) @[el2_dec_gpr_ctl.scala 38:47] + node _T_234 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = and(_T_235, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_237 = or(_T_233, _T_236) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[14] <= _T_237 @[el2_dec_gpr_ctl.scala 38:16] + node _T_238 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_239 = and(io.wen0, _T_238) @[el2_dec_gpr_ctl.scala 35:28] + w0v[15] <= _T_239 @[el2_dec_gpr_ctl.scala 35:16] + node _T_240 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_241 = and(io.wen1, _T_240) @[el2_dec_gpr_ctl.scala 36:28] + w1v[15] <= _T_241 @[el2_dec_gpr_ctl.scala 36:16] + node _T_242 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_243 = and(io.wen2, _T_242) @[el2_dec_gpr_ctl.scala 37:28] + w2v[15] <= _T_243 @[el2_dec_gpr_ctl.scala 37:16] + node _T_244 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_246 = and(_T_245, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_247 = or(_T_243, _T_246) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[9] <= _T_247 @[el2_dec_gpr_ctl.scala 29:16] - node _T_248 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_249 = and(io.wen0, _T_248) @[el2_dec_gpr_ctl.scala 26:28] - w0v[10] <= _T_249 @[el2_dec_gpr_ctl.scala 26:16] - node _T_250 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_251 = and(io.wen1, _T_250) @[el2_dec_gpr_ctl.scala 27:28] - w1v[10] <= _T_251 @[el2_dec_gpr_ctl.scala 27:16] - node _T_252 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_253 = and(io.wen2, _T_252) @[el2_dec_gpr_ctl.scala 28:28] - w2v[10] <= _T_253 @[el2_dec_gpr_ctl.scala 28:16] - node _T_254 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] - node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_256 = and(_T_255, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_257 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] - node _T_258 = mux(_T_257, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_259 = and(_T_258, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_260 = or(_T_256, _T_259) @[el2_dec_gpr_ctl.scala 29:47] - node _T_261 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_246 = and(_T_245, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_247 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_249 = and(_T_248, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_250 = or(_T_246, _T_249) @[el2_dec_gpr_ctl.scala 38:47] + node _T_251 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_253 = and(_T_252, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_254 = or(_T_250, _T_253) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[15] <= _T_254 @[el2_dec_gpr_ctl.scala 38:16] + node _T_255 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_256 = and(io.wen0, _T_255) @[el2_dec_gpr_ctl.scala 35:28] + w0v[16] <= _T_256 @[el2_dec_gpr_ctl.scala 35:16] + node _T_257 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_258 = and(io.wen1, _T_257) @[el2_dec_gpr_ctl.scala 36:28] + w1v[16] <= _T_258 @[el2_dec_gpr_ctl.scala 36:16] + node _T_259 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_260 = and(io.wen2, _T_259) @[el2_dec_gpr_ctl.scala 37:28] + w2v[16] <= _T_260 @[el2_dec_gpr_ctl.scala 37:16] + node _T_261 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_263 = and(_T_262, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_264 = or(_T_260, _T_263) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[10] <= _T_264 @[el2_dec_gpr_ctl.scala 29:16] - node _T_265 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_266 = and(io.wen0, _T_265) @[el2_dec_gpr_ctl.scala 26:28] - w0v[11] <= _T_266 @[el2_dec_gpr_ctl.scala 26:16] - node _T_267 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_268 = and(io.wen1, _T_267) @[el2_dec_gpr_ctl.scala 27:28] - w1v[11] <= _T_268 @[el2_dec_gpr_ctl.scala 27:16] - node _T_269 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_270 = and(io.wen2, _T_269) @[el2_dec_gpr_ctl.scala 28:28] - w2v[11] <= _T_270 @[el2_dec_gpr_ctl.scala 28:16] - node _T_271 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] - node _T_272 = mux(_T_271, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_273 = and(_T_272, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_274 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] - node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_276 = and(_T_275, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_277 = or(_T_273, _T_276) @[el2_dec_gpr_ctl.scala 29:47] - node _T_278 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_263 = and(_T_262, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_264 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_265 = mux(_T_264, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_266 = and(_T_265, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_267 = or(_T_263, _T_266) @[el2_dec_gpr_ctl.scala 38:47] + node _T_268 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_269 = mux(_T_268, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_270 = and(_T_269, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_271 = or(_T_267, _T_270) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[16] <= _T_271 @[el2_dec_gpr_ctl.scala 38:16] + node _T_272 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_273 = and(io.wen0, _T_272) @[el2_dec_gpr_ctl.scala 35:28] + w0v[17] <= _T_273 @[el2_dec_gpr_ctl.scala 35:16] + node _T_274 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_275 = and(io.wen1, _T_274) @[el2_dec_gpr_ctl.scala 36:28] + w1v[17] <= _T_275 @[el2_dec_gpr_ctl.scala 36:16] + node _T_276 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_277 = and(io.wen2, _T_276) @[el2_dec_gpr_ctl.scala 37:28] + w2v[17] <= _T_277 @[el2_dec_gpr_ctl.scala 37:16] + node _T_278 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_281 = or(_T_277, _T_280) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[11] <= _T_281 @[el2_dec_gpr_ctl.scala 29:16] - node _T_282 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_283 = and(io.wen0, _T_282) @[el2_dec_gpr_ctl.scala 26:28] - w0v[12] <= _T_283 @[el2_dec_gpr_ctl.scala 26:16] - node _T_284 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_285 = and(io.wen1, _T_284) @[el2_dec_gpr_ctl.scala 27:28] - w1v[12] <= _T_285 @[el2_dec_gpr_ctl.scala 27:16] - node _T_286 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_287 = and(io.wen2, _T_286) @[el2_dec_gpr_ctl.scala 28:28] - w2v[12] <= _T_287 @[el2_dec_gpr_ctl.scala 28:16] - node _T_288 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] - node _T_289 = mux(_T_288, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_290 = and(_T_289, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_291 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] - node _T_292 = mux(_T_291, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_293 = and(_T_292, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_294 = or(_T_290, _T_293) @[el2_dec_gpr_ctl.scala 29:47] - node _T_295 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_280 = and(_T_279, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_281 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_282 = mux(_T_281, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_283 = and(_T_282, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_284 = or(_T_280, _T_283) @[el2_dec_gpr_ctl.scala 38:47] + node _T_285 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_287 = and(_T_286, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_288 = or(_T_284, _T_287) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[17] <= _T_288 @[el2_dec_gpr_ctl.scala 38:16] + node _T_289 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_290 = and(io.wen0, _T_289) @[el2_dec_gpr_ctl.scala 35:28] + w0v[18] <= _T_290 @[el2_dec_gpr_ctl.scala 35:16] + node _T_291 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_292 = and(io.wen1, _T_291) @[el2_dec_gpr_ctl.scala 36:28] + w1v[18] <= _T_292 @[el2_dec_gpr_ctl.scala 36:16] + node _T_293 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_294 = and(io.wen2, _T_293) @[el2_dec_gpr_ctl.scala 37:28] + w2v[18] <= _T_294 @[el2_dec_gpr_ctl.scala 37:16] + node _T_295 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_297 = and(_T_296, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_298 = or(_T_294, _T_297) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[12] <= _T_298 @[el2_dec_gpr_ctl.scala 29:16] - node _T_299 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_300 = and(io.wen0, _T_299) @[el2_dec_gpr_ctl.scala 26:28] - w0v[13] <= _T_300 @[el2_dec_gpr_ctl.scala 26:16] - node _T_301 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_302 = and(io.wen1, _T_301) @[el2_dec_gpr_ctl.scala 27:28] - w1v[13] <= _T_302 @[el2_dec_gpr_ctl.scala 27:16] - node _T_303 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_304 = and(io.wen2, _T_303) @[el2_dec_gpr_ctl.scala 28:28] - w2v[13] <= _T_304 @[el2_dec_gpr_ctl.scala 28:16] - node _T_305 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] - node _T_306 = mux(_T_305, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_307 = and(_T_306, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_308 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] - node _T_309 = mux(_T_308, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_310 = and(_T_309, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_311 = or(_T_307, _T_310) @[el2_dec_gpr_ctl.scala 29:47] - node _T_312 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_297 = and(_T_296, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_298 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_300 = and(_T_299, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_301 = or(_T_297, _T_300) @[el2_dec_gpr_ctl.scala 38:47] + node _T_302 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_303 = mux(_T_302, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_304 = and(_T_303, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_305 = or(_T_301, _T_304) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[18] <= _T_305 @[el2_dec_gpr_ctl.scala 38:16] + node _T_306 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_307 = and(io.wen0, _T_306) @[el2_dec_gpr_ctl.scala 35:28] + w0v[19] <= _T_307 @[el2_dec_gpr_ctl.scala 35:16] + node _T_308 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_309 = and(io.wen1, _T_308) @[el2_dec_gpr_ctl.scala 36:28] + w1v[19] <= _T_309 @[el2_dec_gpr_ctl.scala 36:16] + node _T_310 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_311 = and(io.wen2, _T_310) @[el2_dec_gpr_ctl.scala 37:28] + w2v[19] <= _T_311 @[el2_dec_gpr_ctl.scala 37:16] + node _T_312 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_314 = and(_T_313, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_315 = or(_T_311, _T_314) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[13] <= _T_315 @[el2_dec_gpr_ctl.scala 29:16] - node _T_316 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_317 = and(io.wen0, _T_316) @[el2_dec_gpr_ctl.scala 26:28] - w0v[14] <= _T_317 @[el2_dec_gpr_ctl.scala 26:16] - node _T_318 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_319 = and(io.wen1, _T_318) @[el2_dec_gpr_ctl.scala 27:28] - w1v[14] <= _T_319 @[el2_dec_gpr_ctl.scala 27:16] - node _T_320 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_321 = and(io.wen2, _T_320) @[el2_dec_gpr_ctl.scala 28:28] - w2v[14] <= _T_321 @[el2_dec_gpr_ctl.scala 28:16] - node _T_322 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] - node _T_323 = mux(_T_322, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_324 = and(_T_323, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_325 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] - node _T_326 = mux(_T_325, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_327 = and(_T_326, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_328 = or(_T_324, _T_327) @[el2_dec_gpr_ctl.scala 29:47] - node _T_329 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_314 = and(_T_313, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_315 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_316 = mux(_T_315, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_317 = and(_T_316, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_318 = or(_T_314, _T_317) @[el2_dec_gpr_ctl.scala 38:47] + node _T_319 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_320 = mux(_T_319, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_321 = and(_T_320, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_322 = or(_T_318, _T_321) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[19] <= _T_322 @[el2_dec_gpr_ctl.scala 38:16] + node _T_323 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_324 = and(io.wen0, _T_323) @[el2_dec_gpr_ctl.scala 35:28] + w0v[20] <= _T_324 @[el2_dec_gpr_ctl.scala 35:16] + node _T_325 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_326 = and(io.wen1, _T_325) @[el2_dec_gpr_ctl.scala 36:28] + w1v[20] <= _T_326 @[el2_dec_gpr_ctl.scala 36:16] + node _T_327 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_328 = and(io.wen2, _T_327) @[el2_dec_gpr_ctl.scala 37:28] + w2v[20] <= _T_328 @[el2_dec_gpr_ctl.scala 37:16] + node _T_329 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_331 = and(_T_330, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_332 = or(_T_328, _T_331) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[14] <= _T_332 @[el2_dec_gpr_ctl.scala 29:16] - node _T_333 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_334 = and(io.wen0, _T_333) @[el2_dec_gpr_ctl.scala 26:28] - w0v[15] <= _T_334 @[el2_dec_gpr_ctl.scala 26:16] - node _T_335 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_336 = and(io.wen1, _T_335) @[el2_dec_gpr_ctl.scala 27:28] - w1v[15] <= _T_336 @[el2_dec_gpr_ctl.scala 27:16] - node _T_337 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_338 = and(io.wen2, _T_337) @[el2_dec_gpr_ctl.scala 28:28] - w2v[15] <= _T_338 @[el2_dec_gpr_ctl.scala 28:16] - node _T_339 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] - node _T_340 = mux(_T_339, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_341 = and(_T_340, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_342 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] - node _T_343 = mux(_T_342, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_344 = and(_T_343, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_345 = or(_T_341, _T_344) @[el2_dec_gpr_ctl.scala 29:47] - node _T_346 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_331 = and(_T_330, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_332 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_333 = mux(_T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_334 = and(_T_333, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_335 = or(_T_331, _T_334) @[el2_dec_gpr_ctl.scala 38:47] + node _T_336 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_337 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_338 = and(_T_337, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_339 = or(_T_335, _T_338) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[20] <= _T_339 @[el2_dec_gpr_ctl.scala 38:16] + node _T_340 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_341 = and(io.wen0, _T_340) @[el2_dec_gpr_ctl.scala 35:28] + w0v[21] <= _T_341 @[el2_dec_gpr_ctl.scala 35:16] + node _T_342 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_343 = and(io.wen1, _T_342) @[el2_dec_gpr_ctl.scala 36:28] + w1v[21] <= _T_343 @[el2_dec_gpr_ctl.scala 36:16] + node _T_344 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_345 = and(io.wen2, _T_344) @[el2_dec_gpr_ctl.scala 37:28] + w2v[21] <= _T_345 @[el2_dec_gpr_ctl.scala 37:16] + node _T_346 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_348 = and(_T_347, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_349 = or(_T_345, _T_348) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[15] <= _T_349 @[el2_dec_gpr_ctl.scala 29:16] - node _T_350 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_351 = and(io.wen0, _T_350) @[el2_dec_gpr_ctl.scala 26:28] - w0v[16] <= _T_351 @[el2_dec_gpr_ctl.scala 26:16] - node _T_352 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_353 = and(io.wen1, _T_352) @[el2_dec_gpr_ctl.scala 27:28] - w1v[16] <= _T_353 @[el2_dec_gpr_ctl.scala 27:16] - node _T_354 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_355 = and(io.wen2, _T_354) @[el2_dec_gpr_ctl.scala 28:28] - w2v[16] <= _T_355 @[el2_dec_gpr_ctl.scala 28:16] - node _T_356 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] - node _T_357 = mux(_T_356, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_358 = and(_T_357, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_359 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] - node _T_360 = mux(_T_359, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_361 = and(_T_360, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_362 = or(_T_358, _T_361) @[el2_dec_gpr_ctl.scala 29:47] - node _T_363 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_348 = and(_T_347, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_349 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_350 = mux(_T_349, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_351 = and(_T_350, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_352 = or(_T_348, _T_351) @[el2_dec_gpr_ctl.scala 38:47] + node _T_353 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_354 = mux(_T_353, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_355 = and(_T_354, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_356 = or(_T_352, _T_355) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[21] <= _T_356 @[el2_dec_gpr_ctl.scala 38:16] + node _T_357 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_358 = and(io.wen0, _T_357) @[el2_dec_gpr_ctl.scala 35:28] + w0v[22] <= _T_358 @[el2_dec_gpr_ctl.scala 35:16] + node _T_359 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_360 = and(io.wen1, _T_359) @[el2_dec_gpr_ctl.scala 36:28] + w1v[22] <= _T_360 @[el2_dec_gpr_ctl.scala 36:16] + node _T_361 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_362 = and(io.wen2, _T_361) @[el2_dec_gpr_ctl.scala 37:28] + w2v[22] <= _T_362 @[el2_dec_gpr_ctl.scala 37:16] + node _T_363 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_365 = and(_T_364, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_366 = or(_T_362, _T_365) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[16] <= _T_366 @[el2_dec_gpr_ctl.scala 29:16] - node _T_367 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_368 = and(io.wen0, _T_367) @[el2_dec_gpr_ctl.scala 26:28] - w0v[17] <= _T_368 @[el2_dec_gpr_ctl.scala 26:16] - node _T_369 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_370 = and(io.wen1, _T_369) @[el2_dec_gpr_ctl.scala 27:28] - w1v[17] <= _T_370 @[el2_dec_gpr_ctl.scala 27:16] - node _T_371 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_372 = and(io.wen2, _T_371) @[el2_dec_gpr_ctl.scala 28:28] - w2v[17] <= _T_372 @[el2_dec_gpr_ctl.scala 28:16] - node _T_373 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] - node _T_374 = mux(_T_373, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_375 = and(_T_374, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_376 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] - node _T_377 = mux(_T_376, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_378 = and(_T_377, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_379 = or(_T_375, _T_378) @[el2_dec_gpr_ctl.scala 29:47] - node _T_380 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_365 = and(_T_364, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_366 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_367 = mux(_T_366, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_368 = and(_T_367, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_369 = or(_T_365, _T_368) @[el2_dec_gpr_ctl.scala 38:47] + node _T_370 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_371 = mux(_T_370, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_372 = and(_T_371, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_373 = or(_T_369, _T_372) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[22] <= _T_373 @[el2_dec_gpr_ctl.scala 38:16] + node _T_374 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_375 = and(io.wen0, _T_374) @[el2_dec_gpr_ctl.scala 35:28] + w0v[23] <= _T_375 @[el2_dec_gpr_ctl.scala 35:16] + node _T_376 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_377 = and(io.wen1, _T_376) @[el2_dec_gpr_ctl.scala 36:28] + w1v[23] <= _T_377 @[el2_dec_gpr_ctl.scala 36:16] + node _T_378 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_379 = and(io.wen2, _T_378) @[el2_dec_gpr_ctl.scala 37:28] + w2v[23] <= _T_379 @[el2_dec_gpr_ctl.scala 37:16] + node _T_380 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_382 = and(_T_381, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_383 = or(_T_379, _T_382) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[17] <= _T_383 @[el2_dec_gpr_ctl.scala 29:16] - node _T_384 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_385 = and(io.wen0, _T_384) @[el2_dec_gpr_ctl.scala 26:28] - w0v[18] <= _T_385 @[el2_dec_gpr_ctl.scala 26:16] - node _T_386 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_387 = and(io.wen1, _T_386) @[el2_dec_gpr_ctl.scala 27:28] - w1v[18] <= _T_387 @[el2_dec_gpr_ctl.scala 27:16] - node _T_388 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_389 = and(io.wen2, _T_388) @[el2_dec_gpr_ctl.scala 28:28] - w2v[18] <= _T_389 @[el2_dec_gpr_ctl.scala 28:16] - node _T_390 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] - node _T_391 = mux(_T_390, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_392 = and(_T_391, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_393 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] - node _T_394 = mux(_T_393, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_395 = and(_T_394, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_396 = or(_T_392, _T_395) @[el2_dec_gpr_ctl.scala 29:47] - node _T_397 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_382 = and(_T_381, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_383 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_384 = mux(_T_383, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_385 = and(_T_384, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_386 = or(_T_382, _T_385) @[el2_dec_gpr_ctl.scala 38:47] + node _T_387 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_388 = mux(_T_387, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_389 = and(_T_388, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_390 = or(_T_386, _T_389) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[23] <= _T_390 @[el2_dec_gpr_ctl.scala 38:16] + node _T_391 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_392 = and(io.wen0, _T_391) @[el2_dec_gpr_ctl.scala 35:28] + w0v[24] <= _T_392 @[el2_dec_gpr_ctl.scala 35:16] + node _T_393 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_394 = and(io.wen1, _T_393) @[el2_dec_gpr_ctl.scala 36:28] + w1v[24] <= _T_394 @[el2_dec_gpr_ctl.scala 36:16] + node _T_395 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_396 = and(io.wen2, _T_395) @[el2_dec_gpr_ctl.scala 37:28] + w2v[24] <= _T_396 @[el2_dec_gpr_ctl.scala 37:16] + node _T_397 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_399 = and(_T_398, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_400 = or(_T_396, _T_399) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[18] <= _T_400 @[el2_dec_gpr_ctl.scala 29:16] - node _T_401 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_402 = and(io.wen0, _T_401) @[el2_dec_gpr_ctl.scala 26:28] - w0v[19] <= _T_402 @[el2_dec_gpr_ctl.scala 26:16] - node _T_403 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_404 = and(io.wen1, _T_403) @[el2_dec_gpr_ctl.scala 27:28] - w1v[19] <= _T_404 @[el2_dec_gpr_ctl.scala 27:16] - node _T_405 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_406 = and(io.wen2, _T_405) @[el2_dec_gpr_ctl.scala 28:28] - w2v[19] <= _T_406 @[el2_dec_gpr_ctl.scala 28:16] - node _T_407 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] - node _T_408 = mux(_T_407, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_409 = and(_T_408, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_410 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] - node _T_411 = mux(_T_410, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_412 = and(_T_411, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_413 = or(_T_409, _T_412) @[el2_dec_gpr_ctl.scala 29:47] - node _T_414 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_399 = and(_T_398, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_400 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_401 = mux(_T_400, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_402 = and(_T_401, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_403 = or(_T_399, _T_402) @[el2_dec_gpr_ctl.scala 38:47] + node _T_404 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_406 = and(_T_405, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_407 = or(_T_403, _T_406) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[24] <= _T_407 @[el2_dec_gpr_ctl.scala 38:16] + node _T_408 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_409 = and(io.wen0, _T_408) @[el2_dec_gpr_ctl.scala 35:28] + w0v[25] <= _T_409 @[el2_dec_gpr_ctl.scala 35:16] + node _T_410 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_411 = and(io.wen1, _T_410) @[el2_dec_gpr_ctl.scala 36:28] + w1v[25] <= _T_411 @[el2_dec_gpr_ctl.scala 36:16] + node _T_412 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_413 = and(io.wen2, _T_412) @[el2_dec_gpr_ctl.scala 37:28] + w2v[25] <= _T_413 @[el2_dec_gpr_ctl.scala 37:16] + node _T_414 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_416 = and(_T_415, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_417 = or(_T_413, _T_416) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[19] <= _T_417 @[el2_dec_gpr_ctl.scala 29:16] - node _T_418 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_419 = and(io.wen0, _T_418) @[el2_dec_gpr_ctl.scala 26:28] - w0v[20] <= _T_419 @[el2_dec_gpr_ctl.scala 26:16] - node _T_420 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_421 = and(io.wen1, _T_420) @[el2_dec_gpr_ctl.scala 27:28] - w1v[20] <= _T_421 @[el2_dec_gpr_ctl.scala 27:16] - node _T_422 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_423 = and(io.wen2, _T_422) @[el2_dec_gpr_ctl.scala 28:28] - w2v[20] <= _T_423 @[el2_dec_gpr_ctl.scala 28:16] - node _T_424 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] - node _T_425 = mux(_T_424, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_426 = and(_T_425, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_427 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] - node _T_428 = mux(_T_427, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_429 = and(_T_428, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_430 = or(_T_426, _T_429) @[el2_dec_gpr_ctl.scala 29:47] - node _T_431 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_416 = and(_T_415, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_417 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_418 = mux(_T_417, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_419 = and(_T_418, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_420 = or(_T_416, _T_419) @[el2_dec_gpr_ctl.scala 38:47] + node _T_421 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_422 = mux(_T_421, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_423 = and(_T_422, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_424 = or(_T_420, _T_423) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[25] <= _T_424 @[el2_dec_gpr_ctl.scala 38:16] + node _T_425 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_426 = and(io.wen0, _T_425) @[el2_dec_gpr_ctl.scala 35:28] + w0v[26] <= _T_426 @[el2_dec_gpr_ctl.scala 35:16] + node _T_427 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_428 = and(io.wen1, _T_427) @[el2_dec_gpr_ctl.scala 36:28] + w1v[26] <= _T_428 @[el2_dec_gpr_ctl.scala 36:16] + node _T_429 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_430 = and(io.wen2, _T_429) @[el2_dec_gpr_ctl.scala 37:28] + w2v[26] <= _T_430 @[el2_dec_gpr_ctl.scala 37:16] + node _T_431 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_433 = and(_T_432, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_434 = or(_T_430, _T_433) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[20] <= _T_434 @[el2_dec_gpr_ctl.scala 29:16] - node _T_435 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_436 = and(io.wen0, _T_435) @[el2_dec_gpr_ctl.scala 26:28] - w0v[21] <= _T_436 @[el2_dec_gpr_ctl.scala 26:16] - node _T_437 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_438 = and(io.wen1, _T_437) @[el2_dec_gpr_ctl.scala 27:28] - w1v[21] <= _T_438 @[el2_dec_gpr_ctl.scala 27:16] - node _T_439 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_440 = and(io.wen2, _T_439) @[el2_dec_gpr_ctl.scala 28:28] - w2v[21] <= _T_440 @[el2_dec_gpr_ctl.scala 28:16] - node _T_441 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] - node _T_442 = mux(_T_441, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_443 = and(_T_442, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_444 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] - node _T_445 = mux(_T_444, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_446 = and(_T_445, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_447 = or(_T_443, _T_446) @[el2_dec_gpr_ctl.scala 29:47] - node _T_448 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_433 = and(_T_432, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_434 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_436 = and(_T_435, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_437 = or(_T_433, _T_436) @[el2_dec_gpr_ctl.scala 38:47] + node _T_438 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_441 = or(_T_437, _T_440) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[26] <= _T_441 @[el2_dec_gpr_ctl.scala 38:16] + node _T_442 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_443 = and(io.wen0, _T_442) @[el2_dec_gpr_ctl.scala 35:28] + w0v[27] <= _T_443 @[el2_dec_gpr_ctl.scala 35:16] + node _T_444 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_445 = and(io.wen1, _T_444) @[el2_dec_gpr_ctl.scala 36:28] + w1v[27] <= _T_445 @[el2_dec_gpr_ctl.scala 36:16] + node _T_446 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_447 = and(io.wen2, _T_446) @[el2_dec_gpr_ctl.scala 37:28] + w2v[27] <= _T_447 @[el2_dec_gpr_ctl.scala 37:16] + node _T_448 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_450 = and(_T_449, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_451 = or(_T_447, _T_450) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[21] <= _T_451 @[el2_dec_gpr_ctl.scala 29:16] - node _T_452 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_453 = and(io.wen0, _T_452) @[el2_dec_gpr_ctl.scala 26:28] - w0v[22] <= _T_453 @[el2_dec_gpr_ctl.scala 26:16] - node _T_454 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_455 = and(io.wen1, _T_454) @[el2_dec_gpr_ctl.scala 27:28] - w1v[22] <= _T_455 @[el2_dec_gpr_ctl.scala 27:16] - node _T_456 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_457 = and(io.wen2, _T_456) @[el2_dec_gpr_ctl.scala 28:28] - w2v[22] <= _T_457 @[el2_dec_gpr_ctl.scala 28:16] - node _T_458 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] - node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_460 = and(_T_459, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_461 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] - node _T_462 = mux(_T_461, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_463 = and(_T_462, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_464 = or(_T_460, _T_463) @[el2_dec_gpr_ctl.scala 29:47] - node _T_465 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_450 = and(_T_449, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_451 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_452 = mux(_T_451, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_453 = and(_T_452, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_454 = or(_T_450, _T_453) @[el2_dec_gpr_ctl.scala 38:47] + node _T_455 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(_T_456, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_458 = or(_T_454, _T_457) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[27] <= _T_458 @[el2_dec_gpr_ctl.scala 38:16] + node _T_459 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_460 = and(io.wen0, _T_459) @[el2_dec_gpr_ctl.scala 35:28] + w0v[28] <= _T_460 @[el2_dec_gpr_ctl.scala 35:16] + node _T_461 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_462 = and(io.wen1, _T_461) @[el2_dec_gpr_ctl.scala 36:28] + w1v[28] <= _T_462 @[el2_dec_gpr_ctl.scala 36:16] + node _T_463 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_464 = and(io.wen2, _T_463) @[el2_dec_gpr_ctl.scala 37:28] + w2v[28] <= _T_464 @[el2_dec_gpr_ctl.scala 37:16] + node _T_465 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_467 = and(_T_466, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_468 = or(_T_464, _T_467) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[22] <= _T_468 @[el2_dec_gpr_ctl.scala 29:16] - node _T_469 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_470 = and(io.wen0, _T_469) @[el2_dec_gpr_ctl.scala 26:28] - w0v[23] <= _T_470 @[el2_dec_gpr_ctl.scala 26:16] - node _T_471 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_472 = and(io.wen1, _T_471) @[el2_dec_gpr_ctl.scala 27:28] - w1v[23] <= _T_472 @[el2_dec_gpr_ctl.scala 27:16] - node _T_473 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_474 = and(io.wen2, _T_473) @[el2_dec_gpr_ctl.scala 28:28] - w2v[23] <= _T_474 @[el2_dec_gpr_ctl.scala 28:16] - node _T_475 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(_T_476, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_478 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] - node _T_479 = mux(_T_478, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_480 = and(_T_479, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_481 = or(_T_477, _T_480) @[el2_dec_gpr_ctl.scala 29:47] - node _T_482 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_467 = and(_T_466, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_468 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_470 = and(_T_469, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_471 = or(_T_467, _T_470) @[el2_dec_gpr_ctl.scala 38:47] + node _T_472 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_473 = mux(_T_472, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_474 = and(_T_473, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_475 = or(_T_471, _T_474) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[28] <= _T_475 @[el2_dec_gpr_ctl.scala 38:16] + node _T_476 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_477 = and(io.wen0, _T_476) @[el2_dec_gpr_ctl.scala 35:28] + w0v[29] <= _T_477 @[el2_dec_gpr_ctl.scala 35:16] + node _T_478 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_479 = and(io.wen1, _T_478) @[el2_dec_gpr_ctl.scala 36:28] + w1v[29] <= _T_479 @[el2_dec_gpr_ctl.scala 36:16] + node _T_480 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_481 = and(io.wen2, _T_480) @[el2_dec_gpr_ctl.scala 37:28] + w2v[29] <= _T_481 @[el2_dec_gpr_ctl.scala 37:16] + node _T_482 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_484 = and(_T_483, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_485 = or(_T_481, _T_484) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[23] <= _T_485 @[el2_dec_gpr_ctl.scala 29:16] - node _T_486 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_487 = and(io.wen0, _T_486) @[el2_dec_gpr_ctl.scala 26:28] - w0v[24] <= _T_487 @[el2_dec_gpr_ctl.scala 26:16] - node _T_488 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_489 = and(io.wen1, _T_488) @[el2_dec_gpr_ctl.scala 27:28] - w1v[24] <= _T_489 @[el2_dec_gpr_ctl.scala 27:16] - node _T_490 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_491 = and(io.wen2, _T_490) @[el2_dec_gpr_ctl.scala 28:28] - w2v[24] <= _T_491 @[el2_dec_gpr_ctl.scala 28:16] - node _T_492 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] - node _T_493 = mux(_T_492, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_494 = and(_T_493, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_495 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] - node _T_496 = mux(_T_495, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_497 = and(_T_496, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_498 = or(_T_494, _T_497) @[el2_dec_gpr_ctl.scala 29:47] - node _T_499 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_484 = and(_T_483, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_485 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_486 = mux(_T_485, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_487 = and(_T_486, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_488 = or(_T_484, _T_487) @[el2_dec_gpr_ctl.scala 38:47] + node _T_489 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_490 = mux(_T_489, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_491 = and(_T_490, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_492 = or(_T_488, _T_491) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[29] <= _T_492 @[el2_dec_gpr_ctl.scala 38:16] + node _T_493 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_494 = and(io.wen0, _T_493) @[el2_dec_gpr_ctl.scala 35:28] + w0v[30] <= _T_494 @[el2_dec_gpr_ctl.scala 35:16] + node _T_495 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_496 = and(io.wen1, _T_495) @[el2_dec_gpr_ctl.scala 36:28] + w1v[30] <= _T_496 @[el2_dec_gpr_ctl.scala 36:16] + node _T_497 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_498 = and(io.wen2, _T_497) @[el2_dec_gpr_ctl.scala 37:28] + w2v[30] <= _T_498 @[el2_dec_gpr_ctl.scala 37:16] + node _T_499 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_501 = and(_T_500, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_502 = or(_T_498, _T_501) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[24] <= _T_502 @[el2_dec_gpr_ctl.scala 29:16] - node _T_503 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_504 = and(io.wen0, _T_503) @[el2_dec_gpr_ctl.scala 26:28] - w0v[25] <= _T_504 @[el2_dec_gpr_ctl.scala 26:16] - node _T_505 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_506 = and(io.wen1, _T_505) @[el2_dec_gpr_ctl.scala 27:28] - w1v[25] <= _T_506 @[el2_dec_gpr_ctl.scala 27:16] - node _T_507 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_508 = and(io.wen2, _T_507) @[el2_dec_gpr_ctl.scala 28:28] - w2v[25] <= _T_508 @[el2_dec_gpr_ctl.scala 28:16] - node _T_509 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] - node _T_510 = mux(_T_509, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_511 = and(_T_510, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_512 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] - node _T_513 = mux(_T_512, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_514 = and(_T_513, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_515 = or(_T_511, _T_514) @[el2_dec_gpr_ctl.scala 29:47] - node _T_516 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_501 = and(_T_500, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_502 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_503 = mux(_T_502, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_504 = and(_T_503, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_505 = or(_T_501, _T_504) @[el2_dec_gpr_ctl.scala 38:47] + node _T_506 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_508 = and(_T_507, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_509 = or(_T_505, _T_508) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[30] <= _T_509 @[el2_dec_gpr_ctl.scala 38:16] + node _T_510 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_511 = and(io.wen0, _T_510) @[el2_dec_gpr_ctl.scala 35:28] + w0v[31] <= _T_511 @[el2_dec_gpr_ctl.scala 35:16] + node _T_512 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_513 = and(io.wen1, _T_512) @[el2_dec_gpr_ctl.scala 36:28] + w1v[31] <= _T_513 @[el2_dec_gpr_ctl.scala 36:16] + node _T_514 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_515 = and(io.wen2, _T_514) @[el2_dec_gpr_ctl.scala 37:28] + w2v[31] <= _T_515 @[el2_dec_gpr_ctl.scala 37:16] + node _T_516 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_518 = and(_T_517, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_519 = or(_T_515, _T_518) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[25] <= _T_519 @[el2_dec_gpr_ctl.scala 29:16] - node _T_520 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_521 = and(io.wen0, _T_520) @[el2_dec_gpr_ctl.scala 26:28] - w0v[26] <= _T_521 @[el2_dec_gpr_ctl.scala 26:16] - node _T_522 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_523 = and(io.wen1, _T_522) @[el2_dec_gpr_ctl.scala 27:28] - w1v[26] <= _T_523 @[el2_dec_gpr_ctl.scala 27:16] - node _T_524 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_525 = and(io.wen2, _T_524) @[el2_dec_gpr_ctl.scala 28:28] - w2v[26] <= _T_525 @[el2_dec_gpr_ctl.scala 28:16] - node _T_526 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(_T_527, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_529 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] - node _T_530 = mux(_T_529, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_531 = and(_T_530, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_532 = or(_T_528, _T_531) @[el2_dec_gpr_ctl.scala 29:47] - node _T_533 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] - node _T_534 = mux(_T_533, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_535 = and(_T_534, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_536 = or(_T_532, _T_535) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[26] <= _T_536 @[el2_dec_gpr_ctl.scala 29:16] - node _T_537 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_538 = and(io.wen0, _T_537) @[el2_dec_gpr_ctl.scala 26:28] - w0v[27] <= _T_538 @[el2_dec_gpr_ctl.scala 26:16] - node _T_539 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_540 = and(io.wen1, _T_539) @[el2_dec_gpr_ctl.scala 27:28] - w1v[27] <= _T_540 @[el2_dec_gpr_ctl.scala 27:16] - node _T_541 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_542 = and(io.wen2, _T_541) @[el2_dec_gpr_ctl.scala 28:28] - w2v[27] <= _T_542 @[el2_dec_gpr_ctl.scala 28:16] - node _T_543 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] - node _T_544 = mux(_T_543, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_545 = and(_T_544, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_546 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] - node _T_547 = mux(_T_546, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_548 = and(_T_547, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_549 = or(_T_545, _T_548) @[el2_dec_gpr_ctl.scala 29:47] - node _T_550 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] - node _T_551 = mux(_T_550, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_552 = and(_T_551, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_553 = or(_T_549, _T_552) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[27] <= _T_553 @[el2_dec_gpr_ctl.scala 29:16] - node _T_554 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_555 = and(io.wen0, _T_554) @[el2_dec_gpr_ctl.scala 26:28] - w0v[28] <= _T_555 @[el2_dec_gpr_ctl.scala 26:16] - node _T_556 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_557 = and(io.wen1, _T_556) @[el2_dec_gpr_ctl.scala 27:28] - w1v[28] <= _T_557 @[el2_dec_gpr_ctl.scala 27:16] - node _T_558 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_559 = and(io.wen2, _T_558) @[el2_dec_gpr_ctl.scala 28:28] - w2v[28] <= _T_559 @[el2_dec_gpr_ctl.scala 28:16] - node _T_560 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] - node _T_561 = mux(_T_560, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_562 = and(_T_561, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_563 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] - node _T_564 = mux(_T_563, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_565 = and(_T_564, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_566 = or(_T_562, _T_565) @[el2_dec_gpr_ctl.scala 29:47] - node _T_567 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] - node _T_568 = mux(_T_567, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_569 = and(_T_568, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_570 = or(_T_566, _T_569) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[28] <= _T_570 @[el2_dec_gpr_ctl.scala 29:16] - node _T_571 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_572 = and(io.wen0, _T_571) @[el2_dec_gpr_ctl.scala 26:28] - w0v[29] <= _T_572 @[el2_dec_gpr_ctl.scala 26:16] - node _T_573 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_574 = and(io.wen1, _T_573) @[el2_dec_gpr_ctl.scala 27:28] - w1v[29] <= _T_574 @[el2_dec_gpr_ctl.scala 27:16] - node _T_575 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_576 = and(io.wen2, _T_575) @[el2_dec_gpr_ctl.scala 28:28] - w2v[29] <= _T_576 @[el2_dec_gpr_ctl.scala 28:16] - node _T_577 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] - node _T_578 = mux(_T_577, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_579 = and(_T_578, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_580 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] - node _T_581 = mux(_T_580, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_582 = and(_T_581, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_583 = or(_T_579, _T_582) @[el2_dec_gpr_ctl.scala 29:47] - node _T_584 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] - node _T_585 = mux(_T_584, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_586 = and(_T_585, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_587 = or(_T_583, _T_586) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[29] <= _T_587 @[el2_dec_gpr_ctl.scala 29:16] - node _T_588 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_589 = and(io.wen0, _T_588) @[el2_dec_gpr_ctl.scala 26:28] - w0v[30] <= _T_589 @[el2_dec_gpr_ctl.scala 26:16] - node _T_590 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_591 = and(io.wen1, _T_590) @[el2_dec_gpr_ctl.scala 27:28] - w1v[30] <= _T_591 @[el2_dec_gpr_ctl.scala 27:16] - node _T_592 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_593 = and(io.wen2, _T_592) @[el2_dec_gpr_ctl.scala 28:28] - w2v[30] <= _T_593 @[el2_dec_gpr_ctl.scala 28:16] - node _T_594 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] - node _T_595 = mux(_T_594, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_596 = and(_T_595, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_597 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_600 = or(_T_596, _T_599) @[el2_dec_gpr_ctl.scala 29:47] - node _T_601 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] - node _T_602 = mux(_T_601, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_603 = and(_T_602, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_604 = or(_T_600, _T_603) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[30] <= _T_604 @[el2_dec_gpr_ctl.scala 29:16] - node _T_605 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_606 = and(io.wen0, _T_605) @[el2_dec_gpr_ctl.scala 26:28] - w0v[31] <= _T_606 @[el2_dec_gpr_ctl.scala 26:16] - node _T_607 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_608 = and(io.wen1, _T_607) @[el2_dec_gpr_ctl.scala 27:28] - w1v[31] <= _T_608 @[el2_dec_gpr_ctl.scala 27:16] - node _T_609 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_610 = and(io.wen2, _T_609) @[el2_dec_gpr_ctl.scala 28:28] - w2v[31] <= _T_610 @[el2_dec_gpr_ctl.scala 28:16] - node _T_611 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] - node _T_612 = mux(_T_611, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_613 = and(_T_612, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_614 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] - node _T_615 = mux(_T_614, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_616 = and(_T_615, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_617 = or(_T_613, _T_616) @[el2_dec_gpr_ctl.scala 29:47] - node _T_618 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] - node _T_619 = mux(_T_618, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_620 = and(_T_619, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_621 = or(_T_617, _T_620) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[31] <= _T_621 @[el2_dec_gpr_ctl.scala 29:16] - node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 33:43] + node _T_518 = and(_T_517, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_519 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_520 = mux(_T_519, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_521 = and(_T_520, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_522 = or(_T_518, _T_521) @[el2_dec_gpr_ctl.scala 38:47] + node _T_523 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_524 = mux(_T_523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_525 = and(_T_524, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_526 = or(_T_522, _T_525) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[31] <= _T_526 @[el2_dec_gpr_ctl.scala 38:16] + node _T_527 = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] + node _T_528 = cat(w0v[2], _T_527) @[Cat.scala 29:58] + node _T_529 = cat(w0v[3], _T_528) @[Cat.scala 29:58] + node _T_530 = cat(w0v[4], _T_529) @[Cat.scala 29:58] + node _T_531 = cat(w0v[5], _T_530) @[Cat.scala 29:58] + node _T_532 = cat(w0v[6], _T_531) @[Cat.scala 29:58] + node _T_533 = cat(w0v[7], _T_532) @[Cat.scala 29:58] + node _T_534 = cat(w0v[8], _T_533) @[Cat.scala 29:58] + node _T_535 = cat(w0v[9], _T_534) @[Cat.scala 29:58] + node _T_536 = cat(w0v[10], _T_535) @[Cat.scala 29:58] + node _T_537 = cat(w0v[11], _T_536) @[Cat.scala 29:58] + node _T_538 = cat(w0v[12], _T_537) @[Cat.scala 29:58] + node _T_539 = cat(w0v[13], _T_538) @[Cat.scala 29:58] + node _T_540 = cat(w0v[14], _T_539) @[Cat.scala 29:58] + node _T_541 = cat(w0v[15], _T_540) @[Cat.scala 29:58] + node _T_542 = cat(w0v[16], _T_541) @[Cat.scala 29:58] + node _T_543 = cat(w0v[17], _T_542) @[Cat.scala 29:58] + node _T_544 = cat(w0v[18], _T_543) @[Cat.scala 29:58] + node _T_545 = cat(w0v[19], _T_544) @[Cat.scala 29:58] + node _T_546 = cat(w0v[20], _T_545) @[Cat.scala 29:58] + node _T_547 = cat(w0v[21], _T_546) @[Cat.scala 29:58] + node _T_548 = cat(w0v[22], _T_547) @[Cat.scala 29:58] + node _T_549 = cat(w0v[23], _T_548) @[Cat.scala 29:58] + node _T_550 = cat(w0v[24], _T_549) @[Cat.scala 29:58] + node _T_551 = cat(w0v[25], _T_550) @[Cat.scala 29:58] + node _T_552 = cat(w0v[26], _T_551) @[Cat.scala 29:58] + node _T_553 = cat(w0v[27], _T_552) @[Cat.scala 29:58] + node _T_554 = cat(w0v[28], _T_553) @[Cat.scala 29:58] + node _T_555 = cat(w0v[29], _T_554) @[Cat.scala 29:58] + node _T_556 = cat(w0v[30], _T_555) @[Cat.scala 29:58] + node _T_557 = cat(w0v[31], _T_556) @[Cat.scala 29:58] + node _T_558 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] + node _T_559 = cat(w1v[2], _T_558) @[Cat.scala 29:58] + node _T_560 = cat(w1v[3], _T_559) @[Cat.scala 29:58] + node _T_561 = cat(w1v[4], _T_560) @[Cat.scala 29:58] + node _T_562 = cat(w1v[5], _T_561) @[Cat.scala 29:58] + node _T_563 = cat(w1v[6], _T_562) @[Cat.scala 29:58] + node _T_564 = cat(w1v[7], _T_563) @[Cat.scala 29:58] + node _T_565 = cat(w1v[8], _T_564) @[Cat.scala 29:58] + node _T_566 = cat(w1v[9], _T_565) @[Cat.scala 29:58] + node _T_567 = cat(w1v[10], _T_566) @[Cat.scala 29:58] + node _T_568 = cat(w1v[11], _T_567) @[Cat.scala 29:58] + node _T_569 = cat(w1v[12], _T_568) @[Cat.scala 29:58] + node _T_570 = cat(w1v[13], _T_569) @[Cat.scala 29:58] + node _T_571 = cat(w1v[14], _T_570) @[Cat.scala 29:58] + node _T_572 = cat(w1v[15], _T_571) @[Cat.scala 29:58] + node _T_573 = cat(w1v[16], _T_572) @[Cat.scala 29:58] + node _T_574 = cat(w1v[17], _T_573) @[Cat.scala 29:58] + node _T_575 = cat(w1v[18], _T_574) @[Cat.scala 29:58] + node _T_576 = cat(w1v[19], _T_575) @[Cat.scala 29:58] + node _T_577 = cat(w1v[20], _T_576) @[Cat.scala 29:58] + node _T_578 = cat(w1v[21], _T_577) @[Cat.scala 29:58] + node _T_579 = cat(w1v[22], _T_578) @[Cat.scala 29:58] + node _T_580 = cat(w1v[23], _T_579) @[Cat.scala 29:58] + node _T_581 = cat(w1v[24], _T_580) @[Cat.scala 29:58] + node _T_582 = cat(w1v[25], _T_581) @[Cat.scala 29:58] + node _T_583 = cat(w1v[26], _T_582) @[Cat.scala 29:58] + node _T_584 = cat(w1v[27], _T_583) @[Cat.scala 29:58] + node _T_585 = cat(w1v[28], _T_584) @[Cat.scala 29:58] + node _T_586 = cat(w1v[29], _T_585) @[Cat.scala 29:58] + node _T_587 = cat(w1v[30], _T_586) @[Cat.scala 29:58] + node _T_588 = cat(w1v[31], _T_587) @[Cat.scala 29:58] + node _T_589 = or(_T_557, _T_588) @[el2_dec_gpr_ctl.scala 40:51] + node _T_590 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] + node _T_591 = cat(w2v[2], _T_590) @[Cat.scala 29:58] + node _T_592 = cat(w2v[3], _T_591) @[Cat.scala 29:58] + node _T_593 = cat(w2v[4], _T_592) @[Cat.scala 29:58] + node _T_594 = cat(w2v[5], _T_593) @[Cat.scala 29:58] + node _T_595 = cat(w2v[6], _T_594) @[Cat.scala 29:58] + node _T_596 = cat(w2v[7], _T_595) @[Cat.scala 29:58] + node _T_597 = cat(w2v[8], _T_596) @[Cat.scala 29:58] + node _T_598 = cat(w2v[9], _T_597) @[Cat.scala 29:58] + node _T_599 = cat(w2v[10], _T_598) @[Cat.scala 29:58] + node _T_600 = cat(w2v[11], _T_599) @[Cat.scala 29:58] + node _T_601 = cat(w2v[12], _T_600) @[Cat.scala 29:58] + node _T_602 = cat(w2v[13], _T_601) @[Cat.scala 29:58] + node _T_603 = cat(w2v[14], _T_602) @[Cat.scala 29:58] + node _T_604 = cat(w2v[15], _T_603) @[Cat.scala 29:58] + node _T_605 = cat(w2v[16], _T_604) @[Cat.scala 29:58] + node _T_606 = cat(w2v[17], _T_605) @[Cat.scala 29:58] + node _T_607 = cat(w2v[18], _T_606) @[Cat.scala 29:58] + node _T_608 = cat(w2v[19], _T_607) @[Cat.scala 29:58] + node _T_609 = cat(w2v[20], _T_608) @[Cat.scala 29:58] + node _T_610 = cat(w2v[21], _T_609) @[Cat.scala 29:58] + node _T_611 = cat(w2v[22], _T_610) @[Cat.scala 29:58] + node _T_612 = cat(w2v[23], _T_611) @[Cat.scala 29:58] + node _T_613 = cat(w2v[24], _T_612) @[Cat.scala 29:58] + node _T_614 = cat(w2v[25], _T_613) @[Cat.scala 29:58] + node _T_615 = cat(w2v[26], _T_614) @[Cat.scala 29:58] + node _T_616 = cat(w2v[27], _T_615) @[Cat.scala 29:58] + node _T_617 = cat(w2v[28], _T_616) @[Cat.scala 29:58] + node _T_618 = cat(w2v[29], _T_617) @[Cat.scala 29:58] + node _T_619 = cat(w2v[30], _T_618) @[Cat.scala 29:58] + node _T_620 = cat(w2v[31], _T_619) @[Cat.scala 29:58] + node _T_621 = or(_T_589, _T_620) @[el2_dec_gpr_ctl.scala 40:89] + gpr_wr_en <= _T_621 @[el2_dec_gpr_ctl.scala 40:12] + node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr of rvclkhdr_20 @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -6615,8 +6761,8 @@ circuit el2_dec : rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_623 <= gpr_in[1] @[el2_lib.scala 514:16] - gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 33:15] - node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 44:15] + node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_1 of rvclkhdr_21 @[el2_lib.scala 508:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -6625,8 +6771,8 @@ circuit el2_dec : rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_625 <= gpr_in[2] @[el2_lib.scala 514:16] - gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 33:15] - node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 44:15] + node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_2 of rvclkhdr_22 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -6635,8 +6781,8 @@ circuit el2_dec : rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_627 <= gpr_in[3] @[el2_lib.scala 514:16] - gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 33:15] - node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 44:15] + node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_3 of rvclkhdr_23 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -6645,8 +6791,8 @@ circuit el2_dec : rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_629 <= gpr_in[4] @[el2_lib.scala 514:16] - gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 33:15] - node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 44:15] + node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_4 of rvclkhdr_24 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -6655,8 +6801,8 @@ circuit el2_dec : rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_631 <= gpr_in[5] @[el2_lib.scala 514:16] - gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 33:15] - node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 44:15] + node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_5 of rvclkhdr_25 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -6665,8 +6811,8 @@ circuit el2_dec : rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_633 <= gpr_in[6] @[el2_lib.scala 514:16] - gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 33:15] - node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 44:15] + node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_6 of rvclkhdr_26 @[el2_lib.scala 508:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -6675,8 +6821,8 @@ circuit el2_dec : rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_635 <= gpr_in[7] @[el2_lib.scala 514:16] - gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 33:15] - node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 44:15] + node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_7 of rvclkhdr_27 @[el2_lib.scala 508:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -6685,8 +6831,8 @@ circuit el2_dec : rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_637 <= gpr_in[8] @[el2_lib.scala 514:16] - gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 33:15] - node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 44:15] + node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_8 of rvclkhdr_28 @[el2_lib.scala 508:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -6695,8 +6841,8 @@ circuit el2_dec : rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_639 <= gpr_in[9] @[el2_lib.scala 514:16] - gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 33:15] - node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 44:15] + node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_9 of rvclkhdr_29 @[el2_lib.scala 508:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -6705,8 +6851,8 @@ circuit el2_dec : rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_641 <= gpr_in[10] @[el2_lib.scala 514:16] - gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 33:15] - node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 44:15] + node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_10 of rvclkhdr_30 @[el2_lib.scala 508:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -6715,8 +6861,8 @@ circuit el2_dec : rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_643 <= gpr_in[11] @[el2_lib.scala 514:16] - gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 33:15] - node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 44:15] + node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_11 of rvclkhdr_31 @[el2_lib.scala 508:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset @@ -6725,8 +6871,8 @@ circuit el2_dec : rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_645 <= gpr_in[12] @[el2_lib.scala 514:16] - gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 33:15] - node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 44:15] + node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_12 of rvclkhdr_32 @[el2_lib.scala 508:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset @@ -6735,8 +6881,8 @@ circuit el2_dec : rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_647 <= gpr_in[13] @[el2_lib.scala 514:16] - gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 33:15] - node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 44:15] + node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_13 of rvclkhdr_33 @[el2_lib.scala 508:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset @@ -6745,8 +6891,8 @@ circuit el2_dec : rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_649 <= gpr_in[14] @[el2_lib.scala 514:16] - gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 33:15] - node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 44:15] + node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_14 of rvclkhdr_34 @[el2_lib.scala 508:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset @@ -6755,8 +6901,8 @@ circuit el2_dec : rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_651 <= gpr_in[15] @[el2_lib.scala 514:16] - gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 33:15] - node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 44:15] + node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_15 of rvclkhdr_35 @[el2_lib.scala 508:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset @@ -6765,8 +6911,8 @@ circuit el2_dec : rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_653 <= gpr_in[16] @[el2_lib.scala 514:16] - gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 33:15] - node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 44:15] + node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_16 of rvclkhdr_36 @[el2_lib.scala 508:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset @@ -6775,8 +6921,8 @@ circuit el2_dec : rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_655 <= gpr_in[17] @[el2_lib.scala 514:16] - gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 33:15] - node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 44:15] + node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_17 of rvclkhdr_37 @[el2_lib.scala 508:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset @@ -6785,8 +6931,8 @@ circuit el2_dec : rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_657 <= gpr_in[18] @[el2_lib.scala 514:16] - gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 33:15] - node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 44:15] + node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_18 of rvclkhdr_38 @[el2_lib.scala 508:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset @@ -6795,8 +6941,8 @@ circuit el2_dec : rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_659 <= gpr_in[19] @[el2_lib.scala 514:16] - gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 33:15] - node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 44:15] + node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_19 of rvclkhdr_39 @[el2_lib.scala 508:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset @@ -6805,8 +6951,8 @@ circuit el2_dec : rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_661 <= gpr_in[20] @[el2_lib.scala 514:16] - gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 33:15] - node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 44:15] + node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_20 of rvclkhdr_40 @[el2_lib.scala 508:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset @@ -6815,8 +6961,8 @@ circuit el2_dec : rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_663 <= gpr_in[21] @[el2_lib.scala 514:16] - gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 33:15] - node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 44:15] + node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_21 of rvclkhdr_41 @[el2_lib.scala 508:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset @@ -6825,8 +6971,8 @@ circuit el2_dec : rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_665 <= gpr_in[22] @[el2_lib.scala 514:16] - gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 33:15] - node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 44:15] + node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_22 of rvclkhdr_42 @[el2_lib.scala 508:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset @@ -6835,8 +6981,8 @@ circuit el2_dec : rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_667 <= gpr_in[23] @[el2_lib.scala 514:16] - gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 33:15] - node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 44:15] + node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_23 of rvclkhdr_43 @[el2_lib.scala 508:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset @@ -6845,8 +6991,8 @@ circuit el2_dec : rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_669 <= gpr_in[24] @[el2_lib.scala 514:16] - gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 33:15] - node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 44:15] + node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_24 of rvclkhdr_44 @[el2_lib.scala 508:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset @@ -6855,8 +7001,8 @@ circuit el2_dec : rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_671 <= gpr_in[25] @[el2_lib.scala 514:16] - gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 33:15] - node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 44:15] + node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_25 of rvclkhdr_45 @[el2_lib.scala 508:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset @@ -6865,8 +7011,8 @@ circuit el2_dec : rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_673 <= gpr_in[26] @[el2_lib.scala 514:16] - gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 33:15] - node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 44:15] + node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_26 of rvclkhdr_46 @[el2_lib.scala 508:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset @@ -6875,8 +7021,8 @@ circuit el2_dec : rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_675 <= gpr_in[27] @[el2_lib.scala 514:16] - gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 33:15] - node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 44:15] + node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_27 of rvclkhdr_47 @[el2_lib.scala 508:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset @@ -6885,8 +7031,8 @@ circuit el2_dec : rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_677 <= gpr_in[28] @[el2_lib.scala 514:16] - gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 33:15] - node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 44:15] + node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_28 of rvclkhdr_48 @[el2_lib.scala 508:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset @@ -6895,8 +7041,8 @@ circuit el2_dec : rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_679 <= gpr_in[29] @[el2_lib.scala 514:16] - gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 33:15] - node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 44:15] + node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_29 of rvclkhdr_49 @[el2_lib.scala 508:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset @@ -6905,8 +7051,8 @@ circuit el2_dec : rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_681 <= gpr_in[30] @[el2_lib.scala 514:16] - gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 33:15] - node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 44:15] + node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_30 of rvclkhdr_50 @[el2_lib.scala 508:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset @@ -6915,69 +7061,69 @@ circuit el2_dec : rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_683 <= gpr_in[31] @[el2_lib.scala 514:16] - gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 33:15] - node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 44:15] + node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] @@ -7041,69 +7187,69 @@ circuit el2_dec : node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72] wire _T_807 : UInt<32> @[Mux.scala 27:72] _T_807 <= _T_806 @[Mux.scala 27:72] - io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 36:9] - node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 47:9] + node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] @@ -7167,7 +7313,7 @@ circuit el2_dec : node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72] wire _T_931 : UInt<32> @[Mux.scala 27:72] _T_931 <= _T_930 @[Mux.scala 27:72] - io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 37:9] + io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 48:9] extmodule gated_latch_51 : output Q : Clock @@ -7267,15 +7413,21 @@ circuit el2_dec : module el2_dec_timer_ctl : input clock : Clock - input reset : Reset + input reset : AsyncReset output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>} - wire mitctl1 : UInt<4> @[el2_dec_tlu_ctl.scala 2745:19] - wire mitctl0 : UInt<3> @[el2_dec_tlu_ctl.scala 2746:19] - wire mitb1 : UInt<32> @[el2_dec_tlu_ctl.scala 2747:19] - wire mitb0 : UInt<32> @[el2_dec_tlu_ctl.scala 2748:19] - wire mitcnt1 : UInt<32> @[el2_dec_tlu_ctl.scala 2749:19] - wire mitcnt0 : UInt<32> @[el2_dec_tlu_ctl.scala 2750:19] + wire mitctl1 : UInt<4> + mitctl1 <= UInt<1>("h00") + wire mitctl0 : UInt<3> + mitctl0 <= UInt<1>("h00") + wire mitb1 : UInt<32> + mitb1 <= UInt<1>("h00") + wire mitb0 : UInt<32> + mitb0 <= UInt<1>("h00") + wire mitcnt1 : UInt<32> + mitcnt1 <= UInt<1>("h00") + wire mitcnt0 : UInt<32> + mitcnt0 <= UInt<1>("h00") node mit0_match_ns = geq(mitcnt0, mitb0) @[el2_dec_tlu_ctl.scala 2752:30] node mit1_match_ns = geq(mitcnt1, mitb1) @[el2_dec_tlu_ctl.scala 2753:30] io.dec_timer_t0_pulse <= mit0_match_ns @[el2_dec_tlu_ctl.scala 2755:25] @@ -7299,9 +7451,9 @@ circuit el2_dec : node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2767:68] node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[el2_dec_tlu_ctl.scala 2767:54] node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[el2_dec_tlu_ctl.scala 2767:23] - node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:60] - node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:77] - node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:94] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:59] + node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:76] + node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:93] inst rvclkhdr of rvclkhdr_51 @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -7363,7 +7515,7 @@ circuit el2_dec : mitb0 <= _T_46 @[el2_dec_tlu_ctl.scala 2791:11] node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[el2_dec_tlu_ctl.scala 2798:63] node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[el2_dec_tlu_ctl.scala 2798:41] - node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:24] + node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:23] node _T_49 = bits(wr_mitb1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2799:56] inst rvclkhdr_3 of rvclkhdr_54 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock @@ -8377,15 +8529,21 @@ circuit el2_dec : module csr_tlu : input clock : Clock - input reset : Reset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]} + input reset : AsyncReset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]} - wire miccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1454:41] - wire mice_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1455:41] - wire mdccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1456:41] - wire pc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 1457:41] - wire mpmc_b_ns : UInt<1> @[el2_dec_tlu_ctl.scala 1458:41] - wire mpmc_b : UInt<1> @[el2_dec_tlu_ctl.scala 1459:41] + wire miccme_ce_req : UInt<1> + miccme_ce_req <= UInt<1>("h00") + wire mice_ce_req : UInt<1> + mice_ce_req <= UInt<1>("h00") + wire mdccme_ce_req : UInt<1> + mdccme_ce_req <= UInt<1>("h00") + wire pc_r_d1 : UInt<31> + pc_r_d1 <= UInt<1>("h00") + wire mpmc_b_ns : UInt<1> + mpmc_b_ns <= UInt<1>("h00") + wire mpmc_b : UInt<1> + mpmc_b <= UInt<1>("h00") wire wr_mcycleh_r : UInt<1> wr_mcycleh_r <= UInt<1>("h00") wire mcycleh : UInt<32> @@ -9840,8 +9998,8 @@ circuit el2_dec : mtdata1_tsel_out <= _T_941 @[Mux.scala 27:72] node _T_942 = bits(io.mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[0].select <= _T_942 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[0].match_ <= _T_943 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[0].match_pkt <= _T_943 @[el2_dec_tlu_ctl.scala 2309:39] node _T_944 = bits(io.mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[0].store <= _T_944 @[el2_dec_tlu_ctl.scala 2310:36] node _T_945 = bits(io.mtdata1_t[0], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -9852,8 +10010,8 @@ circuit el2_dec : io.trigger_pkt_any[0].m <= _T_947 @[el2_dec_tlu_ctl.scala 2313:36] node _T_948 = bits(io.mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[1].select <= _T_948 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[1].match_ <= _T_949 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[1].match_pkt <= _T_949 @[el2_dec_tlu_ctl.scala 2309:39] node _T_950 = bits(io.mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[1].store <= _T_950 @[el2_dec_tlu_ctl.scala 2310:36] node _T_951 = bits(io.mtdata1_t[1], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -9864,8 +10022,8 @@ circuit el2_dec : io.trigger_pkt_any[1].m <= _T_953 @[el2_dec_tlu_ctl.scala 2313:36] node _T_954 = bits(io.mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[2].select <= _T_954 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[2].match_ <= _T_955 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[2].match_pkt <= _T_955 @[el2_dec_tlu_ctl.scala 2309:39] node _T_956 = bits(io.mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[2].store <= _T_956 @[el2_dec_tlu_ctl.scala 2310:36] node _T_957 = bits(io.mtdata1_t[2], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -9876,8 +10034,8 @@ circuit el2_dec : io.trigger_pkt_any[2].m <= _T_959 @[el2_dec_tlu_ctl.scala 2313:36] node _T_960 = bits(io.mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[3].select <= _T_960 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[3].match_ <= _T_961 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[3].match_pkt <= _T_961 @[el2_dec_tlu_ctl.scala 2309:39] node _T_962 = bits(io.mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[3].store <= _T_962 @[el2_dec_tlu_ctl.scala 2310:36] node _T_963 = bits(io.mtdata1_t[3], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -11758,7 +11916,7 @@ circuit el2_dec : module el2_dec_decode_csr_read : input clock : Clock - input reset : Reset + input reset : AsyncReset output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] @@ -13440,124 +13598,238 @@ circuit el2_dec : module el2_dec_tlu_ctl : input clock : Clock input reset : AsyncReset - output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>} + output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>} wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 236:59] - wire pause_expired_wb : UInt<1> @[el2_dec_tlu_ctl.scala 237:54] - wire take_nmi_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 238:62] - wire exc_or_int_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 239:54] - wire interrupt_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 240:54] - wire tlu_flush_lower_r : UInt<1> @[el2_dec_tlu_ctl.scala 241:54] - wire synchronous_flush_r : UInt<1> @[el2_dec_tlu_ctl.scala 242:62] - wire interrupt_valid_r : UInt<1> @[el2_dec_tlu_ctl.scala 243:54] - wire take_nmi : UInt<1> @[el2_dec_tlu_ctl.scala 244:62] - wire take_reset : UInt<1> @[el2_dec_tlu_ctl.scala 245:70] - wire take_int_timer1_int : UInt<1> @[el2_dec_tlu_ctl.scala 246:62] - wire take_int_timer0_int : UInt<1> @[el2_dec_tlu_ctl.scala 247:62] - wire take_timer_int : UInt<1> @[el2_dec_tlu_ctl.scala 248:62] - wire take_soft_int : UInt<1> @[el2_dec_tlu_ctl.scala 249:62] - wire take_ce_int : UInt<1> @[el2_dec_tlu_ctl.scala 250:70] - wire take_ext_int_start : UInt<1> @[el2_dec_tlu_ctl.scala 251:62] - wire ext_int_freeze : UInt<1> @[el2_dec_tlu_ctl.scala 252:62] - wire ext_int_freeze_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 253:62] - wire take_ext_int_start_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 254:54] - wire take_ext_int_start_d2 : UInt<1> @[el2_dec_tlu_ctl.scala 255:54] - wire take_ext_int_start_d3 : UInt<1> @[el2_dec_tlu_ctl.scala 256:54] - wire fast_int_meicpct : UInt<1> @[el2_dec_tlu_ctl.scala 257:54] - wire ignore_ext_int_due_to_lsu_stall : UInt<1> @[el2_dec_tlu_ctl.scala 258:44] - wire take_ext_int : UInt<1> @[el2_dec_tlu_ctl.scala 259:62] - wire internal_dbg_halt_timers : UInt<1> @[el2_dec_tlu_ctl.scala 260:46] - wire int_timer1_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 261:62] - wire int_timer0_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 262:62] - wire mhwakeup_ready : UInt<1> @[el2_dec_tlu_ctl.scala 263:62] - wire ext_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 264:54] - wire ce_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 265:54] - wire soft_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 266:54] - wire timer_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 267:54] - wire ebreak_to_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 268:54] - wire ebreak_to_debug_mode_r : UInt<1> @[el2_dec_tlu_ctl.scala 269:54] - wire inst_acc_r : UInt<1> @[el2_dec_tlu_ctl.scala 270:70] - wire inst_acc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 271:62] - wire iccm_sbecc_r : UInt<1> @[el2_dec_tlu_ctl.scala 272:62] - wire ic_perr_r : UInt<1> @[el2_dec_tlu_ctl.scala 273:62] - wire fence_i_r : UInt<1> @[el2_dec_tlu_ctl.scala 274:62] - wire ebreak_r : UInt<1> @[el2_dec_tlu_ctl.scala 275:62] - wire ecall_r : UInt<1> @[el2_dec_tlu_ctl.scala 276:62] - wire illegal_r : UInt<1> @[el2_dec_tlu_ctl.scala 277:62] - wire mret_r : UInt<1> @[el2_dec_tlu_ctl.scala 278:62] - wire iccm_repair_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 279:54] - wire rfpc_i0_r : UInt<1> @[el2_dec_tlu_ctl.scala 280:70] - wire tlu_i0_kill_writeb_r : UInt<1> @[el2_dec_tlu_ctl.scala 281:54] - wire lsu_exc_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 282:62] - wire lsu_i0_exc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 283:54] - wire mdseac_locked_f : UInt<1> @[el2_dec_tlu_ctl.scala 284:62] - wire i_cpu_run_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 285:54] - wire cpu_run_ack : UInt<1> @[el2_dec_tlu_ctl.scala 286:70] - wire cpu_halt_status : UInt<1> @[el2_dec_tlu_ctl.scala 287:62] - wire cpu_halt_ack : UInt<1> @[el2_dec_tlu_ctl.scala 288:62] - wire pmu_fw_tlu_halted : UInt<1> @[el2_dec_tlu_ctl.scala 289:54] - wire internal_pmu_fw_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 290:46] - wire pmu_fw_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 291:62] - wire pmu_fw_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 292:62] - wire pmu_fw_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 293:54] - wire int_timer0_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 294:54] - wire int_timer1_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 295:54] - wire trigger_hit_dmode_r : UInt<1> @[el2_dec_tlu_ctl.scala 296:54] - wire i0_trigger_hit_r : UInt<1> @[el2_dec_tlu_ctl.scala 297:54] - wire pause_expired_r : UInt<1> @[el2_dec_tlu_ctl.scala 298:62] - wire dec_tlu_pmu_fw_halted : UInt<1> @[el2_dec_tlu_ctl.scala 299:54] - wire dec_tlu_flush_noredir_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 300:54] - wire halt_taken_f : UInt<1> @[el2_dec_tlu_ctl.scala 301:62] - wire lsu_idle_any_f : UInt<1> @[el2_dec_tlu_ctl.scala 302:62] - wire ifu_miss_state_idle_f : UInt<1> @[el2_dec_tlu_ctl.scala 303:54] - wire dbg_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 304:54] - wire debug_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 305:54] - wire debug_resume_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 306:62] - wire trigger_hit_dmode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 307:54] - wire dcsr_single_step_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 308:54] - wire debug_halt_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 309:54] - wire request_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 310:54] - wire request_debug_mode_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 311:46] - wire dcsr_single_step_running_f : UInt<1> @[el2_dec_tlu_ctl.scala 312:54] - wire dec_tlu_flush_pause_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 313:46] - wire dbg_halt_req_held : UInt<1> @[el2_dec_tlu_ctl.scala 314:54] - wire debug_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 315:62] - wire internal_dbg_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 316:54] - wire core_empty : UInt<1> @[el2_dec_tlu_ctl.scala 317:70] - wire dbg_halt_req_final : UInt<1> @[el2_dec_tlu_ctl.scala 318:62] - wire debug_brkpt_status_ns : UInt<1> @[el2_dec_tlu_ctl.scala 319:54] - wire mpc_debug_halt_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 320:54] - wire mpc_debug_run_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 321:54] - wire mpc_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 322:62] - wire mpc_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 323:54] - wire dbg_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 324:62] - wire dbg_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 325:54] - wire dbg_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 326:54] - wire mpc_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 327:54] - wire nmi_int_detected : UInt<1> @[el2_dec_tlu_ctl.scala 328:54] - wire nmi_lsu_load_type : UInt<1> @[el2_dec_tlu_ctl.scala 329:62] - wire nmi_lsu_store_type : UInt<1> @[el2_dec_tlu_ctl.scala 330:62] - wire reset_delayed : UInt<1> @[el2_dec_tlu_ctl.scala 331:62] - wire debug_mode_status : UInt<1> @[el2_dec_tlu_ctl.scala 332:46] - wire e5_valid : UInt<1> @[el2_dec_tlu_ctl.scala 333:62] - wire ic_perr_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 334:62] - wire iccm_sbecc_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 335:62] - wire npc_r : UInt<31> @[el2_dec_tlu_ctl.scala 337:41] - wire npc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 338:41] - wire mie_ns : UInt<6> @[el2_dec_tlu_ctl.scala 339:41] - wire mepc : UInt<31> @[el2_dec_tlu_ctl.scala 340:41] - wire mdseac_locked_ns : UInt<1> @[el2_dec_tlu_ctl.scala 341:41] - wire force_halt : UInt<1> @[el2_dec_tlu_ctl.scala 342:57] - wire dpc : UInt<31> @[el2_dec_tlu_ctl.scala 343:41] - wire mstatus_mie_ns : UInt<1> @[el2_dec_tlu_ctl.scala 344:41] - wire dec_csr_wen_r_mod : UInt<1> @[el2_dec_tlu_ctl.scala 345:41] - wire fw_halt_req : UInt<1> @[el2_dec_tlu_ctl.scala 346:41] - wire mstatus : UInt<2> @[el2_dec_tlu_ctl.scala 347:41] - wire dcsr : UInt<16> @[el2_dec_tlu_ctl.scala 348:41] - wire mtvec : UInt<31> @[el2_dec_tlu_ctl.scala 349:41] - wire mip : UInt<6> @[el2_dec_tlu_ctl.scala 350:41] + wire pause_expired_wb : UInt<1> + pause_expired_wb <= UInt<1>("h00") + wire take_nmi_r_d1 : UInt<1> + take_nmi_r_d1 <= UInt<1>("h00") + wire exc_or_int_valid_r_d1 : UInt<1> + exc_or_int_valid_r_d1 <= UInt<1>("h00") + wire interrupt_valid_r_d1 : UInt<1> + interrupt_valid_r_d1 <= UInt<1>("h00") + wire tlu_flush_lower_r : UInt<1> + tlu_flush_lower_r <= UInt<1>("h00") + wire synchronous_flush_r : UInt<1> + synchronous_flush_r <= UInt<1>("h00") + wire interrupt_valid_r : UInt<1> + interrupt_valid_r <= UInt<1>("h00") + wire take_nmi : UInt<1> + take_nmi <= UInt<1>("h00") + wire take_reset : UInt<1> + take_reset <= UInt<1>("h00") + wire take_int_timer1_int : UInt<1> + take_int_timer1_int <= UInt<1>("h00") + wire take_int_timer0_int : UInt<1> + take_int_timer0_int <= UInt<1>("h00") + wire take_timer_int : UInt<1> + take_timer_int <= UInt<1>("h00") + wire take_soft_int : UInt<1> + take_soft_int <= UInt<1>("h00") + wire take_ce_int : UInt<1> + take_ce_int <= UInt<1>("h00") + wire take_ext_int_start : UInt<1> + take_ext_int_start <= UInt<1>("h00") + wire ext_int_freeze : UInt<1> + ext_int_freeze <= UInt<1>("h00") + wire ext_int_freeze_d1 : UInt<1> + ext_int_freeze_d1 <= UInt<1>("h00") + wire take_ext_int_start_d1 : UInt<1> + take_ext_int_start_d1 <= UInt<1>("h00") + wire take_ext_int_start_d2 : UInt<1> + take_ext_int_start_d2 <= UInt<1>("h00") + wire take_ext_int_start_d3 : UInt<1> + take_ext_int_start_d3 <= UInt<1>("h00") + wire fast_int_meicpct : UInt<1> + fast_int_meicpct <= UInt<1>("h00") + wire ignore_ext_int_due_to_lsu_stall : UInt<1> + ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00") + wire take_ext_int : UInt<1> + take_ext_int <= UInt<1>("h00") + wire internal_dbg_halt_timers : UInt<1> + internal_dbg_halt_timers <= UInt<1>("h00") + wire int_timer1_int_hold : UInt<1> + int_timer1_int_hold <= UInt<1>("h00") + wire int_timer0_int_hold : UInt<1> + int_timer0_int_hold <= UInt<1>("h00") + wire mhwakeup_ready : UInt<1> + mhwakeup_ready <= UInt<1>("h00") + wire ext_int_ready : UInt<1> + ext_int_ready <= UInt<1>("h00") + wire ce_int_ready : UInt<1> + ce_int_ready <= UInt<1>("h00") + wire soft_int_ready : UInt<1> + soft_int_ready <= UInt<1>("h00") + wire timer_int_ready : UInt<1> + timer_int_ready <= UInt<1>("h00") + wire ebreak_to_debug_mode_r_d1 : UInt<1> + ebreak_to_debug_mode_r_d1 <= UInt<1>("h00") + wire ebreak_to_debug_mode_r : UInt<1> + ebreak_to_debug_mode_r <= UInt<1>("h00") + wire inst_acc_r : UInt<1> + inst_acc_r <= UInt<1>("h00") + wire inst_acc_r_raw : UInt<1> + inst_acc_r_raw <= UInt<1>("h00") + wire iccm_sbecc_r : UInt<1> + iccm_sbecc_r <= UInt<1>("h00") + wire ic_perr_r : UInt<1> + ic_perr_r <= UInt<1>("h00") + wire fence_i_r : UInt<1> + fence_i_r <= UInt<1>("h00") + wire ebreak_r : UInt<1> + ebreak_r <= UInt<1>("h00") + wire ecall_r : UInt<1> + ecall_r <= UInt<1>("h00") + wire illegal_r : UInt<1> + illegal_r <= UInt<1>("h00") + wire mret_r : UInt<1> + mret_r <= UInt<1>("h00") + wire iccm_repair_state_ns : UInt<1> + iccm_repair_state_ns <= UInt<1>("h00") + wire rfpc_i0_r : UInt<1> + rfpc_i0_r <= UInt<1>("h00") + wire tlu_i0_kill_writeb_r : UInt<1> + tlu_i0_kill_writeb_r <= UInt<1>("h00") + wire lsu_exc_valid_r_d1 : UInt<1> + lsu_exc_valid_r_d1 <= UInt<1>("h00") + wire lsu_i0_exc_r_raw : UInt<1> + lsu_i0_exc_r_raw <= UInt<1>("h00") + wire mdseac_locked_f : UInt<1> + mdseac_locked_f <= UInt<1>("h00") + wire i_cpu_run_req_d1 : UInt<1> + i_cpu_run_req_d1 <= UInt<1>("h00") + wire cpu_run_ack : UInt<1> + cpu_run_ack <= UInt<1>("h00") + wire cpu_halt_status : UInt<1> + cpu_halt_status <= UInt<1>("h00") + wire cpu_halt_ack : UInt<1> + cpu_halt_ack <= UInt<1>("h00") + wire pmu_fw_tlu_halted : UInt<1> + pmu_fw_tlu_halted <= UInt<1>("h00") + wire internal_pmu_fw_halt_mode : UInt<1> + internal_pmu_fw_halt_mode <= UInt<1>("h00") + wire pmu_fw_halt_req_ns : UInt<1> + pmu_fw_halt_req_ns <= UInt<1>("h00") + wire pmu_fw_halt_req_f : UInt<1> + pmu_fw_halt_req_f <= UInt<1>("h00") + wire pmu_fw_tlu_halted_f : UInt<1> + pmu_fw_tlu_halted_f <= UInt<1>("h00") + wire int_timer0_int_hold_f : UInt<1> + int_timer0_int_hold_f <= UInt<1>("h00") + wire int_timer1_int_hold_f : UInt<1> + int_timer1_int_hold_f <= UInt<1>("h00") + wire trigger_hit_dmode_r : UInt<1> + trigger_hit_dmode_r <= UInt<1>("h00") + wire i0_trigger_hit_r : UInt<1> + i0_trigger_hit_r <= UInt<1>("h00") + wire pause_expired_r : UInt<1> + pause_expired_r <= UInt<1>("h00") + wire dec_tlu_pmu_fw_halted : UInt<1> + dec_tlu_pmu_fw_halted <= UInt<1>("h00") + wire dec_tlu_flush_noredir_r_d1 : UInt<1> + dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00") + wire halt_taken_f : UInt<1> + halt_taken_f <= UInt<1>("h00") + wire lsu_idle_any_f : UInt<1> + lsu_idle_any_f <= UInt<1>("h00") + wire ifu_miss_state_idle_f : UInt<1> + ifu_miss_state_idle_f <= UInt<1>("h00") + wire dbg_tlu_halted_f : UInt<1> + dbg_tlu_halted_f <= UInt<1>("h00") + wire debug_halt_req_f : UInt<1> + debug_halt_req_f <= UInt<1>("h00") + wire debug_resume_req_f : UInt<1> + debug_resume_req_f <= UInt<1>("h00") + wire trigger_hit_dmode_r_d1 : UInt<1> + trigger_hit_dmode_r_d1 <= UInt<1>("h00") + wire dcsr_single_step_done_f : UInt<1> + dcsr_single_step_done_f <= UInt<1>("h00") + wire debug_halt_req_d1 : UInt<1> + debug_halt_req_d1 <= UInt<1>("h00") + wire request_debug_mode_r_d1 : UInt<1> + request_debug_mode_r_d1 <= UInt<1>("h00") + wire request_debug_mode_done_f : UInt<1> + request_debug_mode_done_f <= UInt<1>("h00") + wire dcsr_single_step_running_f : UInt<1> + dcsr_single_step_running_f <= UInt<1>("h00") + wire dec_tlu_flush_pause_r_d1 : UInt<1> + dec_tlu_flush_pause_r_d1 <= UInt<1>("h00") + wire dbg_halt_req_held : UInt<1> + dbg_halt_req_held <= UInt<1>("h00") + wire debug_halt_req_ns : UInt<1> + debug_halt_req_ns <= UInt<1>("h00") + wire internal_dbg_halt_mode : UInt<1> + internal_dbg_halt_mode <= UInt<1>("h00") + wire core_empty : UInt<1> + core_empty <= UInt<1>("h00") + wire dbg_halt_req_final : UInt<1> + dbg_halt_req_final <= UInt<1>("h00") + wire debug_brkpt_status_ns : UInt<1> + debug_brkpt_status_ns <= UInt<1>("h00") + wire mpc_debug_halt_ack_ns : UInt<1> + mpc_debug_halt_ack_ns <= UInt<1>("h00") + wire mpc_debug_run_ack_ns : UInt<1> + mpc_debug_run_ack_ns <= UInt<1>("h00") + wire mpc_halt_state_ns : UInt<1> + mpc_halt_state_ns <= UInt<1>("h00") + wire mpc_run_state_ns : UInt<1> + mpc_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_ns : UInt<1> + dbg_halt_state_ns <= UInt<1>("h00") + wire dbg_run_state_ns : UInt<1> + dbg_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_f : UInt<1> + dbg_halt_state_f <= UInt<1>("h00") + wire mpc_halt_state_f : UInt<1> + mpc_halt_state_f <= UInt<1>("h00") + wire nmi_int_detected : UInt<1> + nmi_int_detected <= UInt<1>("h00") + wire nmi_lsu_load_type : UInt<1> + nmi_lsu_load_type <= UInt<1>("h00") + wire nmi_lsu_store_type : UInt<1> + nmi_lsu_store_type <= UInt<1>("h00") + wire reset_delayed : UInt<1> + reset_delayed <= UInt<1>("h00") + wire debug_mode_status : UInt<1> + debug_mode_status <= UInt<1>("h00") + wire e5_valid : UInt<1> + e5_valid <= UInt<1>("h00") + wire ic_perr_r_d1 : UInt<1> + ic_perr_r_d1 <= UInt<1>("h00") + wire iccm_sbecc_r_d1 : UInt<1> + iccm_sbecc_r_d1 <= UInt<1>("h00") + wire npc_r : UInt<31> + npc_r <= UInt<1>("h00") + wire npc_r_d1 : UInt<31> + npc_r_d1 <= UInt<1>("h00") + wire mie_ns : UInt<6> + mie_ns <= UInt<1>("h00") + wire mepc : UInt<31> + mepc <= UInt<1>("h00") + wire mdseac_locked_ns : UInt<1> + mdseac_locked_ns <= UInt<1>("h00") + wire force_halt : UInt<1> + force_halt <= UInt<1>("h00") + wire dpc : UInt<31> + dpc <= UInt<1>("h00") + wire mstatus_mie_ns : UInt<1> + mstatus_mie_ns <= UInt<1>("h00") + wire dec_csr_wen_r_mod : UInt<1> + dec_csr_wen_r_mod <= UInt<1>("h00") + wire fw_halt_req : UInt<1> + fw_halt_req <= UInt<1>("h00") + wire mstatus : UInt<2> + mstatus <= UInt<1>("h00") + wire dcsr : UInt<16> + dcsr <= UInt<1>("h00") + wire mtvec : UInt<31> + mtvec <= UInt<1>("h00") + wire mip : UInt<6> + mip <= UInt<1>("h00") wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[el2_dec_tlu_ctl.scala 351:41] - wire dec_tlu_mpc_halted_only_ns : UInt<1> @[el2_dec_tlu_ctl.scala 352:41] + wire dec_tlu_mpc_halted_only_ns : UInt<1> + dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") node _T = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 354:33] node _T_1 = and(_T, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 354:51] dec_tlu_mpc_halted_only_ns <= _T_1 @[el2_dec_tlu_ctl.scala 354:30] @@ -14221,7 +14493,7 @@ circuit el2_dec : lsu_exc_valid_r_d1 <= _T_407 @[el2_dec_tlu_ctl.scala 693:41] reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 694:73] lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 694:73] - node _T_408 = eq(io.lsu_error_pkt_r.bits.exc_type, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 695:39] + node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 695:39] node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[el2_dec_tlu_ctl.scala 695:37] node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 696:37] node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[el2_dec_tlu_ctl.scala 697:37] @@ -14289,12 +14561,12 @@ circuit el2_dec : node _T_461 = not(io.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 727:118] node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 727:116] node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 727:94] - io.dec_tlu_br0_r_pkt.bits.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:57] - io.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49] - io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:49] + io.dec_tlu_br0_r_pkt.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:49] + io.dec_tlu_br0_r_pkt.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49] + io.dec_tlu_br0_r_pkt.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:41] io.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 733:49] - io.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:57] - io.dec_tlu_br0_r_pkt.bits.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:57] + io.dec_tlu_br0_r_pkt.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:49] + io.dec_tlu_br0_r_pkt.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:49] node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 738:51] node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64] node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90] @@ -14867,28 +15139,28 @@ circuit el2_dec : io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[0].match_ <= csr.io.trigger_pkt_any[0].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[1].match_ <= csr.io.trigger_pkt_any[1].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[2].match_ <= csr.io.trigger_pkt_any[2].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[3].match_ <= csr.io.trigger_pkt_any[3].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[el2_dec_tlu_ctl.scala 962:40] io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[el2_dec_tlu_ctl.scala 963:40] io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[el2_dec_tlu_ctl.scala 964:40] @@ -15204,7 +15476,7 @@ circuit el2_dec : module el2_dec_trigger : input clock : Clock input reset : Reset - output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[el2_dec_trigger.scala 14:93] @@ -15488,7 +15760,7 @@ circuit el2_dec : dec_i0_match_data[2] <= _T_110 @[el2_dec_trigger.scala 14:46] dec_i0_match_data[3] <= _T_147 @[el2_dec_trigger.scala 14:46] node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[el2_dec_trigger.scala 15:83] - node _T_149 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_149 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_150 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] node _T_152 = not(_T_151) @[el2_lib.scala 241:39] @@ -15779,7 +16051,7 @@ circuit el2_dec : node _T_405 = cat(_T_404, _T_389) @[el2_lib.scala 245:14] node _T_406 = and(_T_148, _T_405) @[el2_dec_trigger.scala 15:109] node _T_407 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[el2_dec_trigger.scala 15:83] - node _T_408 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_408 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_409 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_410 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] node _T_411 = not(_T_410) @[el2_lib.scala 241:39] @@ -16070,7 +16342,7 @@ circuit el2_dec : node _T_664 = cat(_T_663, _T_648) @[el2_lib.scala 245:14] node _T_665 = and(_T_407, _T_664) @[el2_dec_trigger.scala 15:109] node _T_666 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[el2_dec_trigger.scala 15:83] - node _T_667 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_667 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_668 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_669 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] node _T_670 = not(_T_669) @[el2_lib.scala 241:39] @@ -16361,7 +16633,7 @@ circuit el2_dec : node _T_923 = cat(_T_922, _T_907) @[el2_lib.scala 245:14] node _T_924 = and(_T_666, _T_923) @[el2_dec_trigger.scala 15:109] node _T_925 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[el2_dec_trigger.scala 15:83] - node _T_926 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_926 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_927 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_928 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] node _T_929 = not(_T_928) @[el2_lib.scala 241:39] @@ -16659,7 +16931,7 @@ circuit el2_dec : module el2_dec : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} wire dec_i0_inst_wb1 : UInt<32> dec_i0_inst_wb1 <= UInt<1>("h00") @@ -16695,14 +16967,14 @@ circuit el2_dec : instbuff.io.dbg_cmd_write <= io.dbg_cmd_write @[el2_dec.scala 298:45] instbuff.io.dbg_cmd_type <= io.dbg_cmd_type @[el2_dec.scala 299:45] instbuff.io.dbg_cmd_addr <= io.dbg_cmd_addr @[el2_dec.scala 300:45] - instbuff.io.i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec.scala 301:55] + instbuff.io.i0_brp.ret <= io.i0_brp.ret @[el2_dec.scala 301:55] + instbuff.io.i0_brp.way <= io.i0_brp.way @[el2_dec.scala 301:55] + instbuff.io.i0_brp.prett <= io.i0_brp.prett @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bank <= io.i0_brp.bank @[el2_dec.scala 301:55] + instbuff.io.i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec.scala 301:55] + instbuff.io.i0_brp.br_error <= io.i0_brp.br_error @[el2_dec.scala 301:55] + instbuff.io.i0_brp.hist <= io.i0_brp.hist @[el2_dec.scala 301:55] + instbuff.io.i0_brp.toffset <= io.i0_brp.toffset @[el2_dec.scala 301:55] instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 301:55] instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 302:35] instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 303:35] @@ -16722,28 +16994,28 @@ circuit el2_dec : dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 321:34] - dec_trigger.io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 321:34] - dec_trigger.io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 321:34] - dec_trigger.io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 321:34] - dec_trigger.io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 321:34] decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 330:48] decode.io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 331:48] @@ -16769,14 +17041,14 @@ circuit el2_dec : decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 351:48] decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 352:48] decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 353:48] - decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.ret <= instbuff.io.dec_i0_brp.ret @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.way <= instbuff.io.dec_i0_brp.way @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.prett <= instbuff.io.dec_i0_brp.prett @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bank <= instbuff.io.dec_i0_brp.bank @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.br_start_error <= instbuff.io.dec_i0_brp.br_start_error @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.br_error <= instbuff.io.dec_i0_brp.br_error @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.hist <= instbuff.io.dec_i0_brp.hist @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.toffset <= instbuff.io.dec_i0_brp.toffset @[el2_dec.scala 354:48] decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 354:48] decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 355:48] decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 356:48] @@ -17029,28 +17301,28 @@ circuit el2_dec : io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 546:29] io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 546:29] io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 546:29] - io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[el2_dec.scala 546:29] io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 546:29] io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 546:29] io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 546:29] io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 546:29] io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 546:29] io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 546:29] - io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[el2_dec.scala 546:29] io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 546:29] io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 546:29] io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 546:29] io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 546:29] io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 546:29] io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 546:29] - io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[el2_dec.scala 546:29] io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 546:29] io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 546:29] io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 546:29] io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 546:29] io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 546:29] io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 546:29] - io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[el2_dec.scala 546:29] io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 546:29] io.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec.scala 547:29] io.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec.scala 547:29] @@ -17065,11 +17337,11 @@ circuit el2_dec : io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[el2_dec.scala 554:29] io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[el2_dec.scala 555:29] io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[el2_dec.scala 556:29] - io.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.dec_tlu_br0_r_pkt.bits.middle @[el2_dec.scala 557:42] - io.dec_tlu_br0_r_pkt.bits.way <= tlu.io.dec_tlu_br0_r_pkt.bits.way @[el2_dec.scala 557:42] - io.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_dec.scala 557:42] - io.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_dec.scala 557:42] - io.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.dec_tlu_br0_r_pkt.bits.hist @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.middle <= tlu.io.dec_tlu_br0_r_pkt.middle @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.way <= tlu.io.dec_tlu_br0_r_pkt.way @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.br_start_error @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.br_error <= tlu.io.dec_tlu_br0_r_pkt.br_error @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.hist <= tlu.io.dec_tlu_br0_r_pkt.hist @[el2_dec.scala 557:42] io.dec_tlu_br0_r_pkt.valid <= tlu.io.dec_tlu_br0_r_pkt.valid @[el2_dec.scala 557:42] io.dec_tlu_i0_commit_cmt <= tlu.io.dec_tlu_i0_commit_cmt @[el2_dec.scala 558:34] io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 559:34] diff --git a/el2_dec.v b/el2_dec.v index 5f66682d..0049f99a 100644 --- a/el2_dec.v +++ b/el2_dec.v @@ -4,13 +4,13 @@ module el2_dec_ib_ctl( input [1:0] io_dbg_cmd_type, input [31:0] io_dbg_cmd_addr, input io_i0_brp_valid, - input [11:0] io_i0_brp_bits_toffset, - input [1:0] io_i0_brp_bits_hist, - input io_i0_brp_bits_br_error, - input io_i0_brp_bits_br_start_error, - input [30:0] io_i0_brp_bits_prett, - input io_i0_brp_bits_way, - input io_i0_brp_bits_ret, + input [11:0] io_i0_brp_toffset, + input [1:0] io_i0_brp_hist, + input io_i0_brp_br_error, + input io_i0_brp_br_start_error, + input [30:0] io_i0_brp_prett, + input io_i0_brp_way, + input io_i0_brp_ret, input [7:0] io_ifu_i0_bp_index, input [7:0] io_ifu_i0_bp_fghr, input [4:0] io_ifu_i0_bp_btag, @@ -28,13 +28,13 @@ module el2_dec_ib_ctl( output [30:0] io_dec_i0_pc_d, output io_dec_i0_pc4_d, output io_dec_i0_brp_valid, - output [11:0] io_dec_i0_brp_bits_toffset, - output [1:0] io_dec_i0_brp_bits_hist, - output io_dec_i0_brp_bits_br_error, - output io_dec_i0_brp_bits_br_start_error, - output [30:0] io_dec_i0_brp_bits_prett, - output io_dec_i0_brp_bits_way, - output io_dec_i0_brp_bits_ret, + output [11:0] io_dec_i0_brp_toffset, + output [1:0] io_dec_i0_brp_hist, + output io_dec_i0_brp_br_error, + output io_dec_i0_brp_br_start_error, + output [30:0] io_dec_i0_brp_prett, + output io_dec_i0_brp_way, + output io_dec_i0_brp_ret, output [7:0] io_dec_i0_bp_index, output [7:0] io_dec_i0_bp_fghr, output [4:0] io_dec_i0_bp_btag, @@ -44,52 +44,55 @@ module el2_dec_ib_ctl( output io_dec_debug_wdata_rs1_d, output io_dec_debug_fence_d ); - wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 66:60] - wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 66:41] - wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 67:38] - wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 67:36] - wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 68:36] - wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 70:55] - wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 70:37] - wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 71:37] - wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 72:55] - wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 72:37] - wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 73:37] - wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 75:40] - wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 76:40] + wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 31:60] + wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 31:41] + wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 32:38] + wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 32:36] + wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 33:36] + wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 35:55] + wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 35:37] + wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 36:37] + wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 37:55] + wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 37:37] + wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 38:37] + wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 40:40] + wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 41:40] wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58] - wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58] - wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58] - wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58] + wire [13:0] _T_12 = {3'h6,dreg,6'h33}; // @[Cat.scala 29:58] + wire [25:0] _T_14 = {dcsr,14'h2073}; // @[Cat.scala 29:58] + wire [24:0] _T_16 = {dcsr,13'h1073}; // @[Cat.scala 29:58] wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] - wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] - wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72] - wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 89:51] - assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 91:22] - assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 48:31] - assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 92:22] - assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 46:31] - assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 47:31] - assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 50:31] - assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 51:31] - assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 52:31] - assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 45:31] - assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 43:31] - assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 44:31] - assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 86:28] - assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 89:24] + wire [13:0] _T_18 = debug_write_gpr ? _T_12 : 14'h0; // @[Mux.scala 27:72] + wire [25:0] _T_19 = debug_read_csr ? _T_14 : 26'h0; // @[Mux.scala 27:72] + wire [24:0] _T_20 = debug_write_csr ? _T_16 : 25'h0; // @[Mux.scala 27:72] + wire [31:0] _GEN_0 = {{18'd0}, _T_18}; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_17 | _GEN_0; // @[Mux.scala 27:72] + wire [31:0] _GEN_1 = {{6'd0}, _T_19}; // @[Mux.scala 27:72] + wire [31:0] _T_22 = _T_21 | _GEN_1; // @[Mux.scala 27:72] + wire [31:0] _GEN_2 = {{7'd0}, _T_20}; // @[Mux.scala 27:72] + wire [31:0] ib0_debug_in = _T_22 | _GEN_2; // @[Mux.scala 27:72] + wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 54:51] + assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 56:22] + assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 13:31] + assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 57:22] + assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31] + assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31] + assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31] + assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31] + assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31] + assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 10:31] + assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 8:31] + assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 9:31] + assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 51:28] + assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 54:24] endmodule module rvclkhdr( output io_l1clk, @@ -165,654 +168,661 @@ module el2_dec_dec_ctl( output io_out_pm_alu, output io_out_legal ); - wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 72:27] - wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 72:42] - wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:53] - wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 72:39] - wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 72:68] - wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:78] - wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 73:51] - wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 73:51] - wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 73:90] - wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 73:90] - wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 73:55] - wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 74:37] - wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 74:37] - wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 73:94] - wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 74:76] - wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 74:76] - wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 74:41] - wire _T_45 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_49 = _T_45 & io_ins[13]; // @[el2_dec_dec_ctl.scala 75:38] - wire _T_50 = _T_49 & _T_18; // @[el2_dec_dec_ctl.scala 75:38] - wire _T_51 = _T_43 | _T_50; // @[el2_dec_dec_ctl.scala 74:80] - wire _T_57 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 75:76] - wire _T_58 = _T_57 & _T_18; // @[el2_dec_dec_ctl.scala 75:76] - wire _T_59 = _T_51 | _T_58; // @[el2_dec_dec_ctl.scala 75:42] - wire _T_64 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 76:37] - wire _T_65 = _T_64 & _T_18; // @[el2_dec_dec_ctl.scala 76:37] - wire _T_66 = _T_59 | _T_65; // @[el2_dec_dec_ctl.scala 75:80] - wire _T_72 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 76:75] - wire _T_73 = _T_72 & _T_18; // @[el2_dec_dec_ctl.scala 76:75] - wire _T_74 = _T_66 | _T_73; // @[el2_dec_dec_ctl.scala 76:41] - wire _T_79 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 77:37] - wire _T_80 = _T_79 & _T_18; // @[el2_dec_dec_ctl.scala 77:37] - wire _T_81 = _T_74 | _T_80; // @[el2_dec_dec_ctl.scala 76:79] - wire _T_87 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 77:75] - wire _T_88 = _T_87 & _T_18; // @[el2_dec_dec_ctl.scala 77:75] - wire _T_89 = _T_81 | _T_88; // @[el2_dec_dec_ctl.scala 77:41] - wire _T_94 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 78:37] - wire _T_95 = _T_94 & _T_18; // @[el2_dec_dec_ctl.scala 78:37] - wire _T_96 = _T_89 | _T_95; // @[el2_dec_dec_ctl.scala 77:79] - wire _T_98 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_100 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_101 = _T_98 & _T_100; // @[el2_dec_dec_ctl.scala 78:71] - wire _T_102 = _T_96 | _T_101; // @[el2_dec_dec_ctl.scala 78:41] - wire _T_104 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_107 = _T_104 & _T_18; // @[el2_dec_dec_ctl.scala 78:106] - wire _T_114 = io_ins[5] & _T_98; // @[el2_dec_dec_ctl.scala 79:48] - wire _T_115 = _T_114 & _T_18; // @[el2_dec_dec_ctl.scala 79:48] - wire _T_121 = _T_104 & io_ins[5]; // @[el2_dec_dec_ctl.scala 79:85] - wire _T_122 = _T_121 & _T_18; // @[el2_dec_dec_ctl.scala 79:85] - wire _T_130 = _T_101 & io_ins[2]; // @[el2_dec_dec_ctl.scala 80:50] - wire _T_137 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 80:90] - wire _T_138 = _T_137 & io_ins[4]; // @[el2_dec_dec_ctl.scala 80:90] - wire _T_139 = _T_138 & _T_18; // @[el2_dec_dec_ctl.scala 80:90] - wire _T_140 = _T_130 | _T_139; // @[el2_dec_dec_ctl.scala 80:54] - wire _T_144 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_147 = _T_16 & _T_144; // @[el2_dec_dec_ctl.scala 81:40] - wire _T_148 = _T_147 & io_ins[6]; // @[el2_dec_dec_ctl.scala 81:40] - wire _T_149 = _T_148 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:40] - wire _T_150 = _T_140 | _T_149; // @[el2_dec_dec_ctl.scala 80:94] - wire _T_158 = _T_144 & _T_9; // @[el2_dec_dec_ctl.scala 81:81] - wire _T_159 = _T_158 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:81] - wire _T_160 = _T_159 & _T_18; // @[el2_dec_dec_ctl.scala 81:81] - wire _T_166 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 82:28] - wire _T_169 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 82:55] - wire _T_170 = _T_166 | _T_169; // @[el2_dec_dec_ctl.scala 82:42] - wire _T_181 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 83:58] - wire _T_182 = _T_181 & _T_9; // @[el2_dec_dec_ctl.scala 83:58] - wire _T_183 = _T_182 & io_ins[4]; // @[el2_dec_dec_ctl.scala 83:58] - wire _T_187 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 84:29] - wire _T_190 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 84:53] - wire _T_196 = _T_9 & _T_100; // @[el2_dec_dec_ctl.scala 85:28] - wire _T_198 = _T_196 & io_ins[2]; // @[el2_dec_dec_ctl.scala 85:41] - wire _T_209 = _T_9 & _T_98; // @[el2_dec_dec_ctl.scala 86:50] - wire _T_224 = _T_104 & _T_98; // @[el2_dec_dec_ctl.scala 88:49] - wire _T_236 = _T_19 & _T_144; // @[el2_dec_dec_ctl.scala 89:57] - wire _T_237 = _T_236 & _T_9; // @[el2_dec_dec_ctl.scala 89:57] - wire _T_238 = _T_237 & io_ins[4]; // @[el2_dec_dec_ctl.scala 89:57] - wire _T_246 = _T_238 | _T_198; // @[el2_dec_dec_ctl.scala 89:61] - wire _T_248 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_262 = _T_248 & _T_4; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_263 = _T_262 & _T_14; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_264 = _T_263 & _T_16; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_265 = _T_264 & _T_144; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_266 = _T_265 & _T_104; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_267 = _T_266 & io_ins[4]; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_268 = _T_267 & _T_18; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_279 = io_ins[30] & _T_144; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_280 = _T_279 & _T_104; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_281 = _T_280 & io_ins[5]; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_282 = _T_281 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_283 = _T_282 & _T_18; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_294 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_295 = _T_294 & io_ins[13]; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_296 = _T_295 & _T_104; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_297 = _T_296 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_298 = _T_297 & _T_18; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_299 = _T_283 | _T_298; // @[el2_dec_dec_ctl.scala 91:61] - wire _T_308 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_309 = _T_308 & _T_9; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_310 = _T_309 & io_ins[4]; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_311 = _T_310 & _T_18; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_312 = _T_299 | _T_311; // @[el2_dec_dec_ctl.scala 91:109] - wire _T_318 = io_ins[6] & _T_98; // @[el2_dec_dec_ctl.scala 92:80] - wire _T_319 = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 92:80] - wire _T_328 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_329 = _T_328 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_330 = _T_329 & _T_9; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_331 = _T_330 & _T_18; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_341 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_342 = _T_341 & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_343 = _T_342 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_344 = _T_343 & _T_104; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_345 = _T_344 & _T_18; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_350 = _T_104 & io_ins[3]; // @[el2_dec_dec_ctl.scala 94:45] - wire _T_363 = _T_342 & _T_144; // @[el2_dec_dec_ctl.scala 94:94] - wire _T_364 = _T_363 & _T_104; // @[el2_dec_dec_ctl.scala 94:94] - wire _T_365 = _T_364 & _T_18; // @[el2_dec_dec_ctl.scala 94:94] - wire _T_366 = _T_350 | _T_365; // @[el2_dec_dec_ctl.scala 94:49] - wire _T_370 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 95:34] - wire _T_371 = _T_370 & io_ins[2]; // @[el2_dec_dec_ctl.scala 95:34] - wire _T_372 = _T_366 | _T_371; // @[el2_dec_dec_ctl.scala 94:98] - wire _T_382 = _T_372 | _T_149; // @[el2_dec_dec_ctl.scala 95:38] - wire _T_392 = _T_328 & _T_144; // @[el2_dec_dec_ctl.scala 96:44] - wire _T_393 = _T_392 & _T_9; // @[el2_dec_dec_ctl.scala 96:44] - wire _T_394 = _T_393 & _T_18; // @[el2_dec_dec_ctl.scala 96:44] - wire _T_407 = _T_341 & _T_16; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_408 = _T_407 & _T_144; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_409 = _T_408 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_410 = _T_409 & _T_18; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_421 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_422 = _T_421 & _T_144; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_423 = _T_422 & _T_9; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_424 = _T_423 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_425 = _T_424 & _T_18; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_440 = _T_294 & _T_16; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_441 = _T_440 & io_ins[12]; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_442 = _T_441 & _T_104; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_443 = _T_442 & io_ins[4]; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_454 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_455 = _T_454 & io_ins[12]; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_456 = _T_455 & _T_104; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_457 = _T_456 & io_ins[4]; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_473 = _T_262 & io_ins[14]; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_474 = _T_473 & _T_16; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_475 = _T_474 & io_ins[12]; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_476 = _T_475 & _T_104; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_477 = _T_476 & io_ins[4]; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_492 = _T_295 & io_ins[12]; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_493 = _T_492 & _T_104; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_494 = _T_493 & io_ins[4]; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_495 = _T_494 & _T_18; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_518 = _T_308 & io_ins[12]; // @[el2_dec_dec_ctl.scala 102:59] - wire _T_519 = _T_518 & _T_9; // @[el2_dec_dec_ctl.scala 102:59] - wire _T_520 = _T_519 & _T_18; // @[el2_dec_dec_ctl.scala 102:59] - wire _T_527 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 102:99] - wire _T_528 = _T_527 & _T_98; // @[el2_dec_dec_ctl.scala 102:99] - wire _T_529 = _T_528 & _T_18; // @[el2_dec_dec_ctl.scala 102:99] - wire _T_530 = _T_520 | _T_529; // @[el2_dec_dec_ctl.scala 102:63] - wire _T_536 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 103:37] - wire _T_537 = _T_536 & _T_98; // @[el2_dec_dec_ctl.scala 103:37] - wire _T_538 = _T_530 | _T_537; // @[el2_dec_dec_ctl.scala 102:103] - wire _T_553 = _T_493 & _T_18; // @[el2_dec_dec_ctl.scala 103:86] - wire _T_554 = _T_538 | _T_553; // @[el2_dec_dec_ctl.scala 103:41] - wire _T_563 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_564 = _T_563 & io_ins[12]; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_565 = _T_564 & _T_104; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_566 = _T_565 & io_ins[5]; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_567 = _T_566 & _T_18; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_585 = _T_14 & _T_144; // @[el2_dec_dec_ctl.scala 106:56] - wire _T_586 = _T_585 & io_ins[6]; // @[el2_dec_dec_ctl.scala 106:56] - wire _T_587 = _T_586 & _T_98; // @[el2_dec_dec_ctl.scala 106:56] - wire _T_597 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 107:55] - wire _T_598 = _T_597 & io_ins[6]; // @[el2_dec_dec_ctl.scala 107:55] - wire _T_599 = _T_598 & _T_98; // @[el2_dec_dec_ctl.scala 107:55] - wire _T_608 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 108:54] - wire _T_609 = _T_608 & io_ins[5]; // @[el2_dec_dec_ctl.scala 108:54] - wire _T_610 = _T_609 & _T_98; // @[el2_dec_dec_ctl.scala 108:54] - wire _T_620 = io_ins[14] & _T_144; // @[el2_dec_dec_ctl.scala 109:55] - wire _T_621 = _T_620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 109:55] - wire _T_622 = _T_621 & _T_98; // @[el2_dec_dec_ctl.scala 109:55] - wire _T_638 = _T_147 & _T_104; // @[el2_dec_dec_ctl.scala 111:56] - wire _T_639 = _T_638 & _T_98; // @[el2_dec_dec_ctl.scala 111:56] - wire _T_648 = io_ins[12] & _T_104; // @[el2_dec_dec_ctl.scala 112:53] - wire _T_649 = _T_648 & _T_98; // @[el2_dec_dec_ctl.scala 112:53] - wire _T_656 = io_ins[13] & _T_104; // @[el2_dec_dec_ctl.scala 113:50] - wire _T_662 = _T_527 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:52] - wire _T_666 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 114:87] - wire _T_667 = _T_666 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:87] - wire _T_668 = _T_662 | _T_667; // @[el2_dec_dec_ctl.scala 114:56] - wire _T_672 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:34] - wire _T_673 = _T_672 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:34] - wire _T_674 = _T_668 | _T_673; // @[el2_dec_dec_ctl.scala 114:91] - wire _T_678 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:69] - wire _T_679 = _T_678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:69] - wire _T_680 = _T_674 | _T_679; // @[el2_dec_dec_ctl.scala 115:38] - wire _T_684 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:105] - wire _T_685 = _T_684 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:105] - wire _T_686 = _T_680 | _T_685; // @[el2_dec_dec_ctl.scala 115:73] - wire _T_690 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 116:35] - wire _T_691 = _T_690 & io_ins[4]; // @[el2_dec_dec_ctl.scala 116:35] - wire _T_699 = _T_94 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:57] - wire _T_700 = _T_699 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:57] - wire _T_701 = _T_700 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:57] - wire _T_708 = _T_79 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:99] - wire _T_709 = _T_708 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:99] - wire _T_710 = _T_709 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:99] - wire _T_711 = _T_701 | _T_710; // @[el2_dec_dec_ctl.scala 117:61] - wire _T_718 = _T_64 & io_ins[12]; // @[el2_dec_dec_ctl.scala 118:41] - wire _T_719 = _T_718 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:41] - wire _T_720 = _T_719 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:41] - wire _T_721 = _T_711 | _T_720; // @[el2_dec_dec_ctl.scala 117:103] - wire _T_727 = io_ins[18] & _T_144; // @[el2_dec_dec_ctl.scala 118:81] - wire _T_728 = _T_727 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:81] - wire _T_729 = _T_728 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:81] - wire _T_730 = _T_721 | _T_729; // @[el2_dec_dec_ctl.scala 118:45] - wire _T_736 = io_ins[19] & _T_144; // @[el2_dec_dec_ctl.scala 119:39] - wire _T_737 = _T_736 & io_ins[6]; // @[el2_dec_dec_ctl.scala 119:39] - wire _T_738 = _T_737 & io_ins[4]; // @[el2_dec_dec_ctl.scala 119:39] - wire _T_746 = _T_181 & io_ins[6]; // @[el2_dec_dec_ctl.scala 120:57] - wire _T_754 = _T_421 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:55] - wire _T_755 = _T_754 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:55] - wire _T_760 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 121:94] - wire _T_761 = _T_760 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:94] - wire _T_762 = _T_761 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:94] - wire _T_763 = _T_755 | _T_762; // @[el2_dec_dec_ctl.scala 121:59] - wire _T_768 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:38] - wire _T_769 = _T_768 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:38] - wire _T_770 = _T_769 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:38] - wire _T_771 = _T_763 | _T_770; // @[el2_dec_dec_ctl.scala 121:98] - wire _T_776 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:77] - wire _T_777 = _T_776 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:77] - wire _T_778 = _T_777 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:77] - wire _T_779 = _T_771 | _T_778; // @[el2_dec_dec_ctl.scala 122:42] - wire _T_784 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:38] - wire _T_785 = _T_784 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:38] - wire _T_786 = _T_785 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:38] - wire _T_787 = _T_779 | _T_786; // @[el2_dec_dec_ctl.scala 122:81] - wire _T_792 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:77] - wire _T_793 = _T_792 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:77] - wire _T_794 = _T_793 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:77] - wire _T_801 = io_ins[15] & _T_144; // @[el2_dec_dec_ctl.scala 124:55] - wire _T_802 = _T_801 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:55] - wire _T_803 = _T_802 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:55] - wire _T_809 = io_ins[16] & _T_144; // @[el2_dec_dec_ctl.scala 124:95] - wire _T_810 = _T_809 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:95] - wire _T_811 = _T_810 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:95] - wire _T_812 = _T_803 | _T_811; // @[el2_dec_dec_ctl.scala 124:59] - wire _T_818 = io_ins[17] & _T_144; // @[el2_dec_dec_ctl.scala 125:39] - wire _T_819 = _T_818 & io_ins[6]; // @[el2_dec_dec_ctl.scala 125:39] - wire _T_820 = _T_819 & io_ins[4]; // @[el2_dec_dec_ctl.scala 125:39] - wire _T_821 = _T_812 | _T_820; // @[el2_dec_dec_ctl.scala 124:99] - wire _T_830 = _T_821 | _T_729; // @[el2_dec_dec_ctl.scala 125:43] - wire _T_841 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_849 = _T_841 & io_ins[20]; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_850 = _T_849 & _T_16; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_851 = _T_850 & _T_144; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_852 = _T_851 & io_ins[6]; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_855 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_857 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_864 = _T_855 & _T_857; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_865 = _T_864 & _T_16; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_866 = _T_865 & _T_144; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_867 = _T_866 & io_ins[6]; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_876 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 129:56] - wire _T_877 = _T_876 & _T_144; // @[el2_dec_dec_ctl.scala 129:56] - wire _T_878 = _T_877 & io_ins[6]; // @[el2_dec_dec_ctl.scala 129:56] - wire _T_889 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_890 = _T_889 & _T_104; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_891 = _T_890 & io_ins[5]; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_892 = _T_891 & io_ins[4]; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_907 = _T_889 & io_ins[13]; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_908 = _T_907 & _T_144; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_909 = _T_908 & _T_104; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_910 = _T_909 & io_ins[5]; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_911 = _T_910 & io_ins[4]; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_912 = _T_911 & _T_18; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_925 = _T_889 & _T_16; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_926 = _T_925 & io_ins[12]; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_927 = _T_926 & _T_104; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_928 = _T_927 & io_ins[4]; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_929 = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_961 = _T_925 & _T_144; // @[el2_dec_dec_ctl.scala 134:62] - wire _T_962 = _T_961 & io_ins[5]; // @[el2_dec_dec_ctl.scala 134:62] - wire _T_963 = _T_962 & io_ins[4]; // @[el2_dec_dec_ctl.scala 134:62] - wire _T_973 = _T_563 & _T_104; // @[el2_dec_dec_ctl.scala 135:54] - wire _T_974 = _T_973 & io_ins[5]; // @[el2_dec_dec_ctl.scala 135:54] - wire _T_985 = _T_563 & io_ins[13]; // @[el2_dec_dec_ctl.scala 136:57] - wire _T_986 = _T_985 & _T_104; // @[el2_dec_dec_ctl.scala 136:57] - wire _T_987 = _T_986 & io_ins[5]; // @[el2_dec_dec_ctl.scala 136:57] - wire _T_992 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:47] - wire _T_997 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 138:52] - wire _T_998 = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:52] - wire _T_1006 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1007 = _T_1006 & _T_16; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1008 = _T_1007 & _T_144; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1009 = _T_1008 & io_ins[4]; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1013 = _T_1009 | _T_190; // @[el2_dec_dec_ctl.scala 139:63] - wire _T_1019 = _T_4 & _T_104; // @[el2_dec_dec_ctl.scala 140:37] - wire _T_1020 = _T_1019 & io_ins[4]; // @[el2_dec_dec_ctl.scala 140:37] - wire _T_1021 = _T_1013 | _T_1020; // @[el2_dec_dec_ctl.scala 139:96] - wire _T_1037 = _T_87 & io_ins[6]; // @[el2_dec_dec_ctl.scala 141:88] - wire _T_1038 = _T_1037 & io_ins[4]; // @[el2_dec_dec_ctl.scala 141:88] - wire _T_1039 = _T_992 | _T_1038; // @[el2_dec_dec_ctl.scala 141:53] - wire _T_1046 = _T_72 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:38] - wire _T_1047 = _T_1046 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:38] - wire _T_1048 = _T_1039 | _T_1047; // @[el2_dec_dec_ctl.scala 141:92] - wire _T_1055 = _T_57 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:77] - wire _T_1056 = _T_1055 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:77] - wire _T_1057 = _T_1048 | _T_1056; // @[el2_dec_dec_ctl.scala 142:42] - wire _T_1066 = _T_1057 | _T_1056; // @[el2_dec_dec_ctl.scala 142:81] - wire _T_1073 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 143:78] - wire _T_1074 = _T_1073 & io_ins[4]; // @[el2_dec_dec_ctl.scala 143:78] - wire _T_1075 = _T_1066 | _T_1074; // @[el2_dec_dec_ctl.scala 143:42] - wire _T_1082 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:39] - wire _T_1083 = _T_1082 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:39] - wire _T_1084 = _T_1075 | _T_1083; // @[el2_dec_dec_ctl.scala 143:82] - wire _T_1090 = _T_94 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:78] - wire _T_1091 = _T_1090 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:78] - wire _T_1092 = _T_1084 | _T_1091; // @[el2_dec_dec_ctl.scala 144:43] - wire _T_1098 = _T_79 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:38] - wire _T_1099 = _T_1098 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:38] - wire _T_1100 = _T_1092 | _T_1099; // @[el2_dec_dec_ctl.scala 144:82] - wire _T_1106 = _T_64 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:77] - wire _T_1107 = _T_1106 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:77] - wire _T_1108 = _T_1100 | _T_1107; // @[el2_dec_dec_ctl.scala 145:42] - wire _T_1113 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 146:38] - wire _T_1114 = _T_1113 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:38] - wire _T_1115 = _T_1114 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:38] - wire _T_1116 = _T_1108 | _T_1115; // @[el2_dec_dec_ctl.scala 145:81] - wire _T_1122 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:77] - wire _T_1123 = _T_1122 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:77] - wire _T_1139 = _T_841 & _T_16; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1140 = _T_1139 & _T_144; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1141 = _T_1140 & io_ins[6]; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1142 = _T_1141 & io_ins[4]; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1143 = _T_998 | _T_1142; // @[el2_dec_dec_ctl.scala 147:57] - wire _T_1152 = _T_1143 | _T_1038; // @[el2_dec_dec_ctl.scala 147:102] - wire _T_1161 = _T_1152 | _T_1047; // @[el2_dec_dec_ctl.scala 148:42] - wire _T_1170 = _T_1161 | _T_1056; // @[el2_dec_dec_ctl.scala 148:81] - wire _T_1179 = _T_1170 | _T_1074; // @[el2_dec_dec_ctl.scala 149:42] - wire _T_1188 = _T_1179 | _T_1083; // @[el2_dec_dec_ctl.scala 149:82] - wire _T_1196 = _T_1188 | _T_1091; // @[el2_dec_dec_ctl.scala 150:43] - wire _T_1204 = _T_1196 | _T_1099; // @[el2_dec_dec_ctl.scala 150:82] - wire _T_1212 = _T_1204 | _T_1107; // @[el2_dec_dec_ctl.scala 151:42] - wire _T_1220 = _T_1212 | _T_1115; // @[el2_dec_dec_ctl.scala 151:81] - wire _T_1230 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1236 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1238 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1242 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1244 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1251 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1255 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1257 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1259 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1263 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1265 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1267 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1269 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1271 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1281 = ~io_ins[0]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1282 = _T_1230 & _T_248; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1283 = _T_1282 & io_ins[29]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1284 = _T_1283 & io_ins[28]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1285 = _T_1284 & _T_1236; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1286 = _T_1285 & _T_1238; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1287 = _T_1286 & _T_4; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1288 = _T_1287 & _T_1242; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1289 = _T_1288 & _T_1244; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1290 = _T_1289 & _T_841; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1291 = _T_1290 & io_ins[21]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1292 = _T_1291 & _T_857; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1293 = _T_1292 & _T_1251; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1294 = _T_1293 & _T_45; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1295 = _T_1294 & _T_1255; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1296 = _T_1295 & _T_1257; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1297 = _T_1296 & _T_1259; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1298 = _T_1297 & _T_14; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1299 = _T_1298 & _T_1263; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1300 = _T_1299 & _T_1265; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1301 = _T_1300 & _T_1267; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1302 = _T_1301 & _T_1269; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1303 = _T_1302 & _T_1271; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1304 = _T_1303 & io_ins[6]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1305 = _T_1304 & io_ins[5]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1306 = _T_1305 & io_ins[4]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1307 = _T_1306 & _T_100; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1308 = _T_1307 & _T_18; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1309 = _T_1308 & io_ins[1]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1310 = _T_1309 & _T_1281; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1316 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1365 = _T_1282 & _T_1316; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1366 = _T_1365 & io_ins[28]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1367 = _T_1366 & _T_1236; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1368 = _T_1367 & _T_1238; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1369 = _T_1368 & _T_4; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1370 = _T_1369 & _T_1242; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1371 = _T_1370 & _T_1244; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1372 = _T_1371 & io_ins[22]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1373 = _T_1372 & _T_855; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1374 = _T_1373 & io_ins[20]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1375 = _T_1374 & _T_1251; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1376 = _T_1375 & _T_45; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1377 = _T_1376 & _T_1255; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1378 = _T_1377 & _T_1257; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1379 = _T_1378 & _T_1259; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1380 = _T_1379 & _T_14; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1381 = _T_1380 & _T_1263; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1382 = _T_1381 & _T_1265; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1383 = _T_1382 & _T_1267; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1384 = _T_1383 & _T_1269; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1385 = _T_1384 & _T_1271; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1386 = _T_1385 & io_ins[6]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1387 = _T_1386 & io_ins[5]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1388 = _T_1387 & io_ins[4]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1389 = _T_1388 & _T_100; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1390 = _T_1389 & _T_18; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1391 = _T_1390 & io_ins[1]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1392 = _T_1391 & _T_1281; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1393 = _T_1310 | _T_1392; // @[el2_dec_dec_ctl.scala 153:148] - wire _T_1401 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1449 = _T_1365 & _T_1401; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1450 = _T_1449 & _T_1236; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1451 = _T_1450 & _T_1238; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1452 = _T_1451 & _T_4; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1453 = _T_1452 & _T_1242; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1454 = _T_1453 & _T_1244; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1455 = _T_1454 & _T_841; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1456 = _T_1455 & _T_855; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1457 = _T_1456 & _T_1251; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1458 = _T_1457 & _T_45; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1459 = _T_1458 & _T_1255; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1460 = _T_1459 & _T_1257; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1461 = _T_1460 & _T_1259; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1462 = _T_1461 & _T_14; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1463 = _T_1462 & _T_1263; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1464 = _T_1463 & _T_1265; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1465 = _T_1464 & _T_1267; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1466 = _T_1465 & _T_1269; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1467 = _T_1466 & _T_1271; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1468 = _T_1467 & io_ins[5]; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1469 = _T_1468 & io_ins[4]; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1470 = _T_1469 & _T_100; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1471 = _T_1470 & _T_18; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1472 = _T_1471 & io_ins[1]; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1473 = _T_1472 & _T_1281; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1474 = _T_1393 | _T_1473; // @[el2_dec_dec_ctl.scala 154:134] - wire _T_1503 = _T_1452 & _T_104; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1504 = _T_1503 & io_ins[4]; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1505 = _T_1504 & _T_100; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1506 = _T_1505 & io_ins[1]; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1507 = _T_1506 & _T_1281; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1508 = _T_1474 | _T_1507; // @[el2_dec_dec_ctl.scala 155:131] - wire _T_1536 = _T_1230 & _T_1316; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1537 = _T_1536 & _T_1401; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1538 = _T_1537 & _T_1236; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1539 = _T_1538 & _T_1238; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1540 = _T_1539 & _T_4; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1541 = _T_1540 & _T_14; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1542 = _T_1541 & _T_16; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1543 = _T_1542 & _T_144; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1544 = _T_1543 & _T_104; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1545 = _T_1544 & _T_100; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1546 = _T_1545 & _T_18; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1547 = _T_1546 & io_ins[1]; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1548 = _T_1547 & _T_1281; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1549 = _T_1508 | _T_1548; // @[el2_dec_dec_ctl.scala 156:72] - wire _T_1579 = _T_1540 & io_ins[14]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1580 = _T_1579 & _T_16; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1581 = _T_1580 & io_ins[12]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1582 = _T_1581 & _T_104; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1583 = _T_1582 & io_ins[4]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1584 = _T_1583 & _T_100; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1585 = _T_1584 & io_ins[1]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1586 = _T_1585 & _T_1281; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1587 = _T_1549 | _T_1586; // @[el2_dec_dec_ctl.scala 157:81] - wire _T_1614 = _T_1451 & _T_104; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1615 = _T_1614 & io_ins[5]; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1616 = _T_1615 & io_ins[4]; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1617 = _T_1616 & _T_100; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1618 = _T_1617 & io_ins[1]; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1619 = _T_1618 & _T_1281; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1620 = _T_1587 | _T_1619; // @[el2_dec_dec_ctl.scala 158:78] - wire _T_1638 = _T_236 & io_ins[6]; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1640 = _T_1639 & _T_98; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1641 = _T_1640 & _T_100; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1642 = _T_1641 & io_ins[1]; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1643 = _T_1642 & _T_1281; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1644 = _T_1620 | _T_1643; // @[el2_dec_dec_ctl.scala 159:70] - wire _T_1657 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1658 = _T_1657 & io_ins[5]; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1659 = _T_1658 & _T_98; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1660 = _T_1659 & _T_100; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1661 = _T_1660 & _T_18; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1662 = _T_1661 & io_ins[1]; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1663 = _T_1662 & _T_1281; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1664 = _T_1644 | _T_1663; // @[el2_dec_dec_ctl.scala 160:58] - wire _T_1677 = _T_144 & _T_104; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1678 = _T_1677 & _T_9; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1679 = _T_1678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1680 = _T_1679 & _T_100; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1681 = _T_1680 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1682 = _T_1681 & _T_1281; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1683 = _T_1664 | _T_1682; // @[el2_dec_dec_ctl.scala 161:52] - wire _T_1699 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1700 = _T_1699 & _T_98; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1701 = _T_1700 & _T_100; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1702 = _T_1701 & _T_18; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1703 = _T_1702 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1704 = _T_1703 & _T_1281; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1705 = _T_1683 | _T_1704; // @[el2_dec_dec_ctl.scala 162:51] - wire _T_1717 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1718 = _T_1717 & io_ins[5]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1719 = _T_1718 & io_ins[4]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1720 = _T_1719 & _T_100; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1721 = _T_1720 & _T_18; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1722 = _T_1721 & io_ins[1]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1723 = _T_1722 & _T_1281; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1724 = _T_1705 | _T_1723; // @[el2_dec_dec_ctl.scala 162:103] - wire _T_1796 = _T_1456 & _T_857; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1797 = _T_1796 & _T_1251; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1798 = _T_1797 & _T_45; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1799 = _T_1798 & _T_1255; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1800 = _T_1799 & _T_1257; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1801 = _T_1800 & _T_1259; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1802 = _T_1801 & _T_14; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1803 = _T_1802 & _T_16; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1804 = _T_1803 & _T_144; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1805 = _T_1804 & _T_1263; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1806 = _T_1805 & _T_1265; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1807 = _T_1806 & _T_1267; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1808 = _T_1807 & _T_1269; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1809 = _T_1808 & _T_1271; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1810 = _T_1809 & _T_104; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1811 = _T_1810 & _T_9; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1812 = _T_1811 & _T_98; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1813 = _T_1812 & io_ins[3]; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1814 = _T_1813 & io_ins[2]; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1815 = _T_1814 & io_ins[1]; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1816 = _T_1815 & _T_1281; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1817 = _T_1724 | _T_1816; // @[el2_dec_dec_ctl.scala 163:51] - wire _T_1866 = _T_1449 & _T_1251; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1867 = _T_1866 & _T_45; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1868 = _T_1867 & _T_1255; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1869 = _T_1868 & _T_1257; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1870 = _T_1869 & _T_1259; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1871 = _T_1870 & _T_14; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1872 = _T_1871 & _T_16; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1873 = _T_1872 & _T_144; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1874 = _T_1873 & _T_1263; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1875 = _T_1874 & _T_1265; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1876 = _T_1875 & _T_1267; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1877 = _T_1876 & _T_1269; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1878 = _T_1877 & _T_1271; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1879 = _T_1878 & _T_104; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1880 = _T_1879 & _T_9; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1881 = _T_1880 & _T_98; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1882 = _T_1881 & io_ins[3]; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1883 = _T_1882 & io_ins[2]; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1884 = _T_1883 & io_ins[1]; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1885 = _T_1884 & _T_1281; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1886 = _T_1817 | _T_1885; // @[el2_dec_dec_ctl.scala 164:146] - wire _T_1902 = _T_16 & _T_104; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1903 = _T_1902 & _T_9; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1904 = _T_1903 & _T_98; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1905 = _T_1904 & _T_100; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1906 = _T_1905 & _T_18; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1907 = _T_1906 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1908 = _T_1907 & _T_1281; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1909 = _T_1886 | _T_1908; // @[el2_dec_dec_ctl.scala 165:114] - wire _T_1919 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1920 = _T_1919 & _T_98; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1921 = _T_1920 & io_ins[3]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1922 = _T_1921 & io_ins[2]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1923 = _T_1922 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1924 = _T_1923 & _T_1281; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1925 = _T_1909 | _T_1924; // @[el2_dec_dec_ctl.scala 166:55] - wire _T_1938 = _T_656 & _T_9; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1939 = _T_1938 & io_ins[4]; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1940 = _T_1939 & _T_100; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1941 = _T_1940 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1942 = _T_1941 & _T_1281; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1943 = _T_1925 | _T_1942; // @[el2_dec_dec_ctl.scala 166:99] - wire _T_1960 = _T_585 & _T_104; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1961 = _T_1960 & _T_98; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1962 = _T_1961 & _T_100; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1963 = _T_1962 & _T_18; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50] - wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43] - assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14] - assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14] - assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14] - assign io_out_imm12 = _T_150 | _T_160; // @[el2_dec_dec_ctl.scala 80:16] - assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13] - assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17] - assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16] - assign io_out_pc = _T_198 | _T_187; // @[el2_dec_dec_ctl.scala 85:13] - assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15] - assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16] - assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14] - assign io_out_add = _T_246 | _T_268; // @[el2_dec_dec_ctl.scala 89:14] - assign io_out_sub = _T_312 | _T_319; // @[el2_dec_dec_ctl.scala 91:14] - assign io_out_land = _T_331 | _T_345; // @[el2_dec_dec_ctl.scala 93:15] - assign io_out_lor = _T_382 | _T_394; // @[el2_dec_dec_ctl.scala 94:14] - assign io_out_lxor = _T_410 | _T_425; // @[el2_dec_dec_ctl.scala 97:15] - assign io_out_sll = _T_443 & _T_18; // @[el2_dec_dec_ctl.scala 98:14] - assign io_out_sra = _T_457 & _T_18; // @[el2_dec_dec_ctl.scala 99:14] - assign io_out_srl = _T_477 & _T_18; // @[el2_dec_dec_ctl.scala 100:14] - assign io_out_slt = _T_495 | _T_311; // @[el2_dec_dec_ctl.scala 101:14] - assign io_out_unsign = _T_554 | _T_567; // @[el2_dec_dec_ctl.scala 102:17] - assign io_out_condbr = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 105:17] - assign io_out_beq = _T_587 & _T_18; // @[el2_dec_dec_ctl.scala 106:14] - assign io_out_bne = _T_599 & _T_18; // @[el2_dec_dec_ctl.scala 107:14] - assign io_out_bge = _T_610 & _T_18; // @[el2_dec_dec_ctl.scala 108:14] - assign io_out_blt = _T_622 & _T_18; // @[el2_dec_dec_ctl.scala 109:14] - assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 110:14] - assign io_out_by = _T_639 & _T_18; // @[el2_dec_dec_ctl.scala 111:13] - assign io_out_half = _T_649 & _T_18; // @[el2_dec_dec_ctl.scala 112:15] - assign io_out_word = _T_656 & _T_98; // @[el2_dec_dec_ctl.scala 113:15] - assign io_out_csr_read = _T_686 | _T_691; // @[el2_dec_dec_ctl.scala 114:19] - assign io_out_csr_clr = _T_730 | _T_738; // @[el2_dec_dec_ctl.scala 117:18] - assign io_out_csr_set = _T_830 | _T_738; // @[el2_dec_dec_ctl.scala 124:18] - assign io_out_csr_write = _T_746 & io_ins[4]; // @[el2_dec_dec_ctl.scala 120:20] - assign io_out_csr_imm = _T_787 | _T_794; // @[el2_dec_dec_ctl.scala 121:18] - assign io_out_presync = _T_1116 | _T_1123; // @[el2_dec_dec_ctl.scala 141:18] - assign io_out_postsync = _T_1220 | _T_1123; // @[el2_dec_dec_ctl.scala 147:19] - assign io_out_ebreak = _T_852 & io_ins[4]; // @[el2_dec_dec_ctl.scala 127:17] - assign io_out_ecall = _T_867 & io_ins[4]; // @[el2_dec_dec_ctl.scala 128:16] - assign io_out_mret = _T_878 & io_ins[4]; // @[el2_dec_dec_ctl.scala 129:15] - assign io_out_mul = _T_892 & _T_18; // @[el2_dec_dec_ctl.scala 130:14] - assign io_out_rs1_sign = _T_912 | _T_929; // @[el2_dec_dec_ctl.scala 131:19] - assign io_out_rs2_sign = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 133:19] - assign io_out_low = _T_963 & _T_18; // @[el2_dec_dec_ctl.scala 134:14] - assign io_out_div = _T_974 & _T_18; // @[el2_dec_dec_ctl.scala 135:14] - assign io_out_rem = _T_987 & _T_18; // @[el2_dec_dec_ctl.scala 136:14] - assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16] - assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18] - assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17] - assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16] + wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 20:27] + wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 20:42] + wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:53] + wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 20:39] + wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 20:68] + wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:78] + wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 21:43] + wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 21:70] + wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 22:29] + wire _T_48 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_49 = _T_48 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_50 = _T_43 | _T_49; // @[el2_dec_dec_ctl.scala 22:56] + wire _T_56 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_57 = _T_56 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_58 = _T_50 | _T_57; // @[el2_dec_dec_ctl.scala 23:29] + wire _T_63 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_64 = _T_63 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_65 = _T_58 | _T_64; // @[el2_dec_dec_ctl.scala 23:55] + wire _T_71 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_72 = _T_71 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_73 = _T_65 | _T_72; // @[el2_dec_dec_ctl.scala 24:29] + wire _T_78 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_79 = _T_78 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_80 = _T_73 | _T_79; // @[el2_dec_dec_ctl.scala 24:55] + wire _T_86 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_87 = _T_86 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_88 = _T_80 | _T_87; // @[el2_dec_dec_ctl.scala 25:29] + wire _T_93 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_94 = _T_93 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_95 = _T_88 | _T_94; // @[el2_dec_dec_ctl.scala 25:55] + wire _T_97 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_99 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_100 = _T_97 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_101 = _T_95 | _T_100; // @[el2_dec_dec_ctl.scala 26:29] + wire _T_103 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_106 = _T_103 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_113 = io_ins[5] & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_114 = _T_113 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_120 = _T_103 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_121 = _T_120 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_129 = _T_100 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_136 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_137 = _T_136 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_138 = _T_137 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_139 = _T_129 | _T_138; // @[el2_dec_dec_ctl.scala 28:42] + wire _T_143 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_146 = _T_16 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_147 = _T_146 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_148 = _T_147 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_149 = _T_139 | _T_148; // @[el2_dec_dec_ctl.scala 28:70] + wire _T_157 = _T_143 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_158 = _T_157 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_159 = _T_158 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_165 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 30:28] + wire _T_168 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 30:55] + wire _T_169 = _T_165 | _T_168; // @[el2_dec_dec_ctl.scala 30:42] + wire _T_180 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_181 = _T_180 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_182 = _T_181 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_186 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 32:29] + wire _T_189 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 32:53] + wire _T_195 = _T_9 & _T_99; // @[el2_dec_dec_ctl.scala 33:28] + wire _T_197 = _T_195 & io_ins[2]; // @[el2_dec_dec_ctl.scala 33:41] + wire _T_208 = _T_9 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_223 = _T_103 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_235 = _T_19 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_236 = _T_235 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_237 = _T_236 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_245 = _T_237 | _T_197; // @[el2_dec_dec_ctl.scala 37:49] + wire _T_247 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_261 = _T_247 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_262 = _T_261 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_263 = _T_262 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_264 = _T_263 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_265 = _T_264 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_266 = _T_265 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_267 = _T_266 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_278 = io_ins[30] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_279 = _T_278 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_280 = _T_279 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_281 = _T_280 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_282 = _T_281 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_293 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_294 = _T_293 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_295 = _T_294 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_296 = _T_295 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_297 = _T_296 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_298 = _T_282 | _T_297; // @[el2_dec_dec_ctl.scala 39:49] + wire _T_307 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_308 = _T_307 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_309 = _T_308 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_310 = _T_309 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_311 = _T_298 | _T_310; // @[el2_dec_dec_ctl.scala 39:85] + wire _T_317 = io_ins[6] & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_318 = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_327 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_328 = _T_327 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_329 = _T_328 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_330 = _T_329 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_340 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_341 = _T_340 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_342 = _T_341 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_343 = _T_342 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_344 = _T_343 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_349 = _T_103 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_362 = _T_341 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_363 = _T_362 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_364 = _T_363 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_365 = _T_349 | _T_364; // @[el2_dec_dec_ctl.scala 42:37] + wire _T_369 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_370 = _T_369 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_371 = _T_365 | _T_370; // @[el2_dec_dec_ctl.scala 42:74] + wire _T_381 = _T_371 | _T_148; // @[el2_dec_dec_ctl.scala 43:26] + wire _T_391 = _T_327 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_392 = _T_391 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_393 = _T_392 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_406 = _T_340 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_407 = _T_406 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_408 = _T_407 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_409 = _T_408 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_420 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_421 = _T_420 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_422 = _T_421 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_423 = _T_422 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_424 = _T_423 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_439 = _T_293 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_440 = _T_439 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_441 = _T_440 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_442 = _T_441 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_453 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_454 = _T_453 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_455 = _T_454 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_456 = _T_455 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_472 = _T_261 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_473 = _T_472 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_474 = _T_473 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_475 = _T_474 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_476 = _T_475 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_515 = _T_307 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_516 = _T_515 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_517 = _T_516 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_524 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_525 = _T_524 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_526 = _T_525 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_527 = _T_517 | _T_526; // @[el2_dec_dec_ctl.scala 50:51] + wire _T_533 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_534 = _T_533 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_535 = _T_527 | _T_534; // @[el2_dec_dec_ctl.scala 50:79] + wire _T_548 = _T_294 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_549 = _T_548 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_550 = _T_549 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_551 = _T_535 | _T_550; // @[el2_dec_dec_ctl.scala 51:29] + wire _T_560 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_561 = _T_560 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_562 = _T_561 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_563 = _T_562 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_564 = _T_563 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_582 = _T_14 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_583 = _T_582 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_584 = _T_583 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_594 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_595 = _T_594 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_596 = _T_595 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_605 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_606 = _T_605 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_607 = _T_606 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_617 = io_ins[14] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_618 = _T_617 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_619 = _T_618 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_635 = _T_146 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_636 = _T_635 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_645 = io_ins[12] & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_646 = _T_645 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_653 = io_ins[13] & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_659 = _T_524 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_663 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_664 = _T_663 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_665 = _T_659 | _T_664; // @[el2_dec_dec_ctl.scala 62:44] + wire _T_669 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_670 = _T_669 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_671 = _T_665 | _T_670; // @[el2_dec_dec_ctl.scala 62:67] + wire _T_675 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_676 = _T_675 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_677 = _T_671 | _T_676; // @[el2_dec_dec_ctl.scala 63:26] + wire _T_681 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_682 = _T_681 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_683 = _T_677 | _T_682; // @[el2_dec_dec_ctl.scala 63:49] + wire _T_687 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_688 = _T_687 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_696 = _T_93 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_697 = _T_696 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_698 = _T_697 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_705 = _T_78 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_706 = _T_705 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_707 = _T_706 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_708 = _T_698 | _T_707; // @[el2_dec_dec_ctl.scala 65:49] + wire _T_715 = _T_63 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_716 = _T_715 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_717 = _T_716 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_718 = _T_708 | _T_717; // @[el2_dec_dec_ctl.scala 65:79] + wire _T_725 = _T_48 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_726 = _T_725 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_727 = _T_726 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_728 = _T_718 | _T_727; // @[el2_dec_dec_ctl.scala 66:33] + wire _T_735 = _T_33 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_736 = _T_735 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_737 = _T_736 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_745 = _T_180 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_753 = _T_420 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_754 = _T_753 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_759 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_760 = _T_759 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_761 = _T_760 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_762 = _T_754 | _T_761; // @[el2_dec_dec_ctl.scala 69:47] + wire _T_767 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_768 = _T_767 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_769 = _T_768 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_770 = _T_762 | _T_769; // @[el2_dec_dec_ctl.scala 69:74] + wire _T_775 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_776 = _T_775 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_777 = _T_776 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_778 = _T_770 | _T_777; // @[el2_dec_dec_ctl.scala 70:30] + wire _T_783 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_784 = _T_783 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_785 = _T_784 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_786 = _T_778 | _T_785; // @[el2_dec_dec_ctl.scala 70:57] + wire _T_791 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_792 = _T_791 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_793 = _T_792 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_800 = io_ins[15] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_801 = _T_800 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_802 = _T_801 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_808 = io_ins[16] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_809 = _T_808 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_810 = _T_809 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_811 = _T_802 | _T_810; // @[el2_dec_dec_ctl.scala 72:47] + wire _T_817 = io_ins[17] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_818 = _T_817 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_819 = _T_818 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_820 = _T_811 | _T_819; // @[el2_dec_dec_ctl.scala 72:75] + wire _T_826 = io_ins[18] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_827 = _T_826 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_828 = _T_827 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_829 = _T_820 | _T_828; // @[el2_dec_dec_ctl.scala 73:31] + wire _T_835 = io_ins[19] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_836 = _T_835 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_837 = _T_836 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_840 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_848 = _T_840 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_849 = _T_848 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_850 = _T_849 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_851 = _T_850 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_854 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_856 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_863 = _T_854 & _T_856; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_864 = _T_863 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_865 = _T_864 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_866 = _T_865 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_875 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_876 = _T_875 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_877 = _T_876 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_888 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_889 = _T_888 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_890 = _T_889 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_891 = _T_890 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_906 = _T_888 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_907 = _T_906 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_908 = _T_907 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_909 = _T_908 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_910 = _T_909 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_911 = _T_910 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_924 = _T_888 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_925 = _T_924 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_926 = _T_925 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_927 = _T_926 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_928 = _T_927 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_960 = _T_924 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_961 = _T_960 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_962 = _T_961 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_972 = _T_560 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_973 = _T_972 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_984 = _T_560 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_985 = _T_984 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_986 = _T_985 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_991 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_996 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_997 = _T_996 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1005 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1006 = _T_1005 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1007 = _T_1006 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1008 = _T_1007 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1012 = _T_1008 | _T_189; // @[el2_dec_dec_ctl.scala 87:51] + wire _T_1018 = _T_4 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1019 = _T_1018 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1020 = _T_1012 | _T_1019; // @[el2_dec_dec_ctl.scala 87:72] + wire _T_1036 = _T_86 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1037 = _T_1036 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1038 = _T_991 | _T_1037; // @[el2_dec_dec_ctl.scala 89:41] + wire _T_1045 = _T_71 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1046 = _T_1045 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1047 = _T_1038 | _T_1046; // @[el2_dec_dec_ctl.scala 89:68] + wire _T_1054 = _T_56 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1055 = _T_1054 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1056 = _T_1047 | _T_1055; // @[el2_dec_dec_ctl.scala 90:30] + wire _T_1063 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1064 = _T_1063 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1065 = _T_1056 | _T_1064; // @[el2_dec_dec_ctl.scala 90:57] + wire _T_1072 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1073 = _T_1072 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1074 = _T_1065 | _T_1073; // @[el2_dec_dec_ctl.scala 91:31] + wire _T_1080 = _T_93 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1081 = _T_1080 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1082 = _T_1074 | _T_1081; // @[el2_dec_dec_ctl.scala 91:59] + wire _T_1088 = _T_78 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1089 = _T_1088 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1090 = _T_1082 | _T_1089; // @[el2_dec_dec_ctl.scala 92:30] + wire _T_1096 = _T_63 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1097 = _T_1096 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1098 = _T_1090 | _T_1097; // @[el2_dec_dec_ctl.scala 92:57] + wire _T_1104 = _T_48 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1105 = _T_1104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1106 = _T_1098 | _T_1105; // @[el2_dec_dec_ctl.scala 93:30] + wire _T_1112 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1113 = _T_1112 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1129 = _T_840 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1130 = _T_1129 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1131 = _T_1130 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1132 = _T_1131 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1133 = _T_997 | _T_1132; // @[el2_dec_dec_ctl.scala 95:45] + wire _T_1142 = _T_1133 | _T_1037; // @[el2_dec_dec_ctl.scala 95:78] + wire _T_1151 = _T_1142 | _T_1046; // @[el2_dec_dec_ctl.scala 96:30] + wire _T_1160 = _T_1151 | _T_1055; // @[el2_dec_dec_ctl.scala 96:57] + wire _T_1169 = _T_1160 | _T_1064; // @[el2_dec_dec_ctl.scala 97:30] + wire _T_1178 = _T_1169 | _T_1073; // @[el2_dec_dec_ctl.scala 97:58] + wire _T_1186 = _T_1178 | _T_1081; // @[el2_dec_dec_ctl.scala 98:31] + wire _T_1194 = _T_1186 | _T_1089; // @[el2_dec_dec_ctl.scala 98:58] + wire _T_1202 = _T_1194 | _T_1097; // @[el2_dec_dec_ctl.scala 99:30] + wire _T_1210 = _T_1202 | _T_1105; // @[el2_dec_dec_ctl.scala 99:57] + wire _T_1220 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1226 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1228 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1232 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1234 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1241 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1243 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1245 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1247 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1249 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1253 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1255 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1257 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1259 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1261 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1271 = _T_1220 & _T_247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1272 = _T_1271 & io_ins[29]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1273 = _T_1272 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1274 = _T_1273 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1275 = _T_1274 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1276 = _T_1275 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1277 = _T_1276 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1278 = _T_1277 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1279 = _T_1278 & _T_840; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1280 = _T_1279 & io_ins[21]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1281 = _T_1280 & _T_856; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1282 = _T_1281 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1283 = _T_1282 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1284 = _T_1283 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1285 = _T_1284 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1286 = _T_1285 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1287 = _T_1286 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1288 = _T_1287 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1289 = _T_1288 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1290 = _T_1289 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1291 = _T_1290 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1292 = _T_1291 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1293 = _T_1292 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1294 = _T_1293 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1295 = _T_1294 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1296 = _T_1295 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1297 = _T_1296 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1298 = _T_1297 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1299 = _T_1298 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1305 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1353 = _T_1271 & _T_1305; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1354 = _T_1353 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1355 = _T_1354 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1356 = _T_1355 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1357 = _T_1356 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1358 = _T_1357 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1359 = _T_1358 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1360 = _T_1359 & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1361 = _T_1360 & _T_854; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1362 = _T_1361 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1363 = _T_1362 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1364 = _T_1363 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1365 = _T_1364 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1366 = _T_1365 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1367 = _T_1366 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1368 = _T_1367 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1369 = _T_1368 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1370 = _T_1369 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1371 = _T_1370 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1372 = _T_1371 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1373 = _T_1372 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1374 = _T_1373 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1375 = _T_1374 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1376 = _T_1375 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1377 = _T_1376 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1378 = _T_1377 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1379 = _T_1378 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1380 = _T_1379 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1381 = _T_1299 | _T_1380; // @[el2_dec_dec_ctl.scala 101:136] + wire _T_1389 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1436 = _T_1353 & _T_1389; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1437 = _T_1436 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1438 = _T_1437 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1439 = _T_1438 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1440 = _T_1439 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1441 = _T_1440 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1442 = _T_1441 & _T_840; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1443 = _T_1442 & _T_854; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1444 = _T_1443 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1445 = _T_1444 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1446 = _T_1445 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1447 = _T_1446 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1448 = _T_1447 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1449 = _T_1448 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1450 = _T_1449 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1451 = _T_1450 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1452 = _T_1451 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1453 = _T_1452 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1454 = _T_1453 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1455 = _T_1454 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1456 = _T_1455 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1457 = _T_1456 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1458 = _T_1457 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1459 = _T_1458 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1460 = _T_1459 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1461 = _T_1381 | _T_1460; // @[el2_dec_dec_ctl.scala 102:122] + wire _T_1489 = _T_1439 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1490 = _T_1489 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1491 = _T_1490 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1492 = _T_1491 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1493 = _T_1492 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1494 = _T_1461 | _T_1493; // @[el2_dec_dec_ctl.scala 103:119] + wire _T_1521 = _T_1220 & _T_1305; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1522 = _T_1521 & _T_1389; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1523 = _T_1522 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1524 = _T_1523 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1525 = _T_1524 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1526 = _T_1525 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1527 = _T_1526 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1528 = _T_1527 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1529 = _T_1528 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1530 = _T_1529 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1531 = _T_1530 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1532 = _T_1531 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1533 = _T_1532 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1534 = _T_1494 | _T_1533; // @[el2_dec_dec_ctl.scala 104:60] + wire _T_1563 = _T_1525 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1564 = _T_1563 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1565 = _T_1564 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1566 = _T_1565 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1567 = _T_1566 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1568 = _T_1567 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1569 = _T_1568 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1570 = _T_1569 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1571 = _T_1534 | _T_1570; // @[el2_dec_dec_ctl.scala 105:69] + wire _T_1597 = _T_1438 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1598 = _T_1597 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1599 = _T_1598 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1600 = _T_1599 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1601 = _T_1600 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1602 = _T_1601 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1603 = _T_1571 | _T_1602; // @[el2_dec_dec_ctl.scala 106:66] + wire _T_1620 = _T_235 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1621 = _T_1620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1622 = _T_1621 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1623 = _T_1622 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1624 = _T_1623 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1625 = _T_1624 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1626 = _T_1603 | _T_1625; // @[el2_dec_dec_ctl.scala 107:58] + wire _T_1638 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1640 = _T_1639 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1641 = _T_1640 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1642 = _T_1641 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1643 = _T_1642 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1644 = _T_1643 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1645 = _T_1626 | _T_1644; // @[el2_dec_dec_ctl.scala 108:46] + wire _T_1657 = _T_143 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1658 = _T_1657 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1659 = _T_1658 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1660 = _T_1659 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1661 = _T_1660 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1662 = _T_1661 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1663 = _T_1645 | _T_1662; // @[el2_dec_dec_ctl.scala 109:40] + wire _T_1678 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1679 = _T_1678 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1680 = _T_1679 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1681 = _T_1680 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1682 = _T_1681 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1683 = _T_1682 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1684 = _T_1663 | _T_1683; // @[el2_dec_dec_ctl.scala 110:39] + wire _T_1695 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1696 = _T_1695 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1697 = _T_1696 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1698 = _T_1697 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1699 = _T_1698 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1700 = _T_1699 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1701 = _T_1700 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1702 = _T_1684 | _T_1701; // @[el2_dec_dec_ctl.scala 111:43] + wire _T_1771 = _T_1443 & _T_856; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1772 = _T_1771 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1773 = _T_1772 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1774 = _T_1773 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1775 = _T_1774 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1776 = _T_1775 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1777 = _T_1776 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1778 = _T_1777 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1779 = _T_1778 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1780 = _T_1779 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1781 = _T_1780 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1782 = _T_1781 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1783 = _T_1782 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1784 = _T_1783 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1785 = _T_1784 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1786 = _T_1785 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1787 = _T_1786 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1788 = _T_1787 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1789 = _T_1788 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1790 = _T_1789 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1791 = _T_1702 | _T_1790; // @[el2_dec_dec_ctl.scala 112:39] + wire _T_1839 = _T_1436 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1840 = _T_1839 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1841 = _T_1840 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1842 = _T_1841 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1843 = _T_1842 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1844 = _T_1843 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1845 = _T_1844 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1846 = _T_1845 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1847 = _T_1846 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1848 = _T_1847 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1849 = _T_1848 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1850 = _T_1849 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1851 = _T_1850 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1852 = _T_1851 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1853 = _T_1852 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1854 = _T_1853 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1855 = _T_1854 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1856 = _T_1855 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1857 = _T_1856 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1858 = _T_1857 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1859 = _T_1791 | _T_1858; // @[el2_dec_dec_ctl.scala 113:130] + wire _T_1871 = _T_524 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1872 = _T_1871 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1873 = _T_1872 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1874 = _T_1873 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1875 = _T_1874 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1876 = _T_1875 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1877 = _T_1859 | _T_1876; // @[el2_dec_dec_ctl.scala 114:102] + wire _T_1892 = _T_16 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1893 = _T_1892 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1894 = _T_1893 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1895 = _T_1894 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1896 = _T_1895 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1897 = _T_1896 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1898 = _T_1897 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1899 = _T_1877 | _T_1898; // @[el2_dec_dec_ctl.scala 115:39] + wire _T_1908 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1909 = _T_1908 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1910 = _T_1909 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1911 = _T_1910 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1912 = _T_1911 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1913 = _T_1912 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1914 = _T_1899 | _T_1913; // @[el2_dec_dec_ctl.scala 116:43] + wire _T_1926 = _T_653 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1927 = _T_1926 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1928 = _T_1927 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1929 = _T_1928 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1930 = _T_1929 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1931 = _T_1914 | _T_1930; // @[el2_dec_dec_ctl.scala 117:35] + wire _T_1947 = _T_582 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1948 = _T_1947 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1949 = _T_1948 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1950 = _T_1949 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1951 = _T_1950 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1952 = _T_1951 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1953 = _T_1931 | _T_1952; // @[el2_dec_dec_ctl.scala 118:38] + wire _T_1962 = _T_103 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1963 = _T_1962 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1964 = _T_1963 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1965 = _T_1964 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1966 = _T_1965 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 20:14] + assign io_out_rs1 = _T_101 | _T_106; // @[el2_dec_dec_ctl.scala 21:14] + assign io_out_rs2 = _T_114 | _T_121; // @[el2_dec_dec_ctl.scala 27:14] + assign io_out_imm12 = _T_149 | _T_159; // @[el2_dec_dec_ctl.scala 28:16] + assign io_out_rd = _T_169 | io_ins[4]; // @[el2_dec_dec_ctl.scala 30:13] + assign io_out_shimm5 = _T_182 & _T_18; // @[el2_dec_dec_ctl.scala 31:17] + assign io_out_imm20 = _T_186 | _T_189; // @[el2_dec_dec_ctl.scala 32:16] + assign io_out_pc = _T_197 | _T_186; // @[el2_dec_dec_ctl.scala 33:13] + assign io_out_load = _T_208 & _T_18; // @[el2_dec_dec_ctl.scala 34:15] + assign io_out_store = _T_120 & _T_97; // @[el2_dec_dec_ctl.scala 35:16] + assign io_out_lsu = _T_223 & _T_18; // @[el2_dec_dec_ctl.scala 36:14] + assign io_out_add = _T_245 | _T_267; // @[el2_dec_dec_ctl.scala 37:14] + assign io_out_sub = _T_311 | _T_318; // @[el2_dec_dec_ctl.scala 39:14] + assign io_out_land = _T_330 | _T_344; // @[el2_dec_dec_ctl.scala 41:15] + assign io_out_lor = _T_381 | _T_393; // @[el2_dec_dec_ctl.scala 42:14] + assign io_out_lxor = _T_409 | _T_424; // @[el2_dec_dec_ctl.scala 45:15] + assign io_out_sll = _T_442 & _T_18; // @[el2_dec_dec_ctl.scala 46:14] + assign io_out_sra = _T_456 & _T_18; // @[el2_dec_dec_ctl.scala 47:14] + assign io_out_srl = _T_476 & _T_18; // @[el2_dec_dec_ctl.scala 48:14] + assign io_out_slt = _T_297 | _T_310; // @[el2_dec_dec_ctl.scala 49:14] + assign io_out_unsign = _T_551 | _T_564; // @[el2_dec_dec_ctl.scala 50:17] + assign io_out_condbr = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 53:17] + assign io_out_beq = _T_584 & _T_18; // @[el2_dec_dec_ctl.scala 54:14] + assign io_out_bne = _T_596 & _T_18; // @[el2_dec_dec_ctl.scala 55:14] + assign io_out_bge = _T_607 & _T_18; // @[el2_dec_dec_ctl.scala 56:14] + assign io_out_blt = _T_619 & _T_18; // @[el2_dec_dec_ctl.scala 57:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 58:14] + assign io_out_by = _T_636 & _T_18; // @[el2_dec_dec_ctl.scala 59:13] + assign io_out_half = _T_646 & _T_18; // @[el2_dec_dec_ctl.scala 60:15] + assign io_out_word = _T_653 & _T_97; // @[el2_dec_dec_ctl.scala 61:15] + assign io_out_csr_read = _T_683 | _T_688; // @[el2_dec_dec_ctl.scala 62:19] + assign io_out_csr_clr = _T_728 | _T_737; // @[el2_dec_dec_ctl.scala 65:18] + assign io_out_csr_set = _T_829 | _T_837; // @[el2_dec_dec_ctl.scala 72:18] + assign io_out_csr_write = _T_745 & io_ins[4]; // @[el2_dec_dec_ctl.scala 68:20] + assign io_out_csr_imm = _T_786 | _T_793; // @[el2_dec_dec_ctl.scala 69:18] + assign io_out_presync = _T_1106 | _T_1113; // @[el2_dec_dec_ctl.scala 89:18] + assign io_out_postsync = _T_1210 | _T_1113; // @[el2_dec_dec_ctl.scala 95:19] + assign io_out_ebreak = _T_851 & io_ins[4]; // @[el2_dec_dec_ctl.scala 75:17] + assign io_out_ecall = _T_866 & io_ins[4]; // @[el2_dec_dec_ctl.scala 76:16] + assign io_out_mret = _T_877 & io_ins[4]; // @[el2_dec_dec_ctl.scala 77:15] + assign io_out_mul = _T_891 & _T_18; // @[el2_dec_dec_ctl.scala 78:14] + assign io_out_rs1_sign = _T_911 | _T_928; // @[el2_dec_dec_ctl.scala 79:19] + assign io_out_rs2_sign = _T_927 & _T_18; // @[el2_dec_dec_ctl.scala 81:19] + assign io_out_low = _T_962 & _T_18; // @[el2_dec_dec_ctl.scala 82:14] + assign io_out_div = _T_973 & _T_18; // @[el2_dec_dec_ctl.scala 83:14] + assign io_out_rem = _T_986 & _T_18; // @[el2_dec_dec_ctl.scala 84:14] + assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 85:16] + assign io_out_fence_i = _T_996 & io_ins[3]; // @[el2_dec_dec_ctl.scala 86:18] + assign io_out_pm_alu = _T_1020 | _T_11; // @[el2_dec_dec_ctl.scala 87:17] + assign io_out_legal = _T_1953 | _T_1966; // @[el2_dec_dec_ctl.scala 101:16] endmodule module el2_dec_decode_ctl( input clock, @@ -845,13 +855,13 @@ module el2_dec_decode_ctl( input [1:0] io_dec_i0_icaf_type_d, input io_dec_i0_dbecc_d, input io_dec_i0_brp_valid, - input [11:0] io_dec_i0_brp_bits_toffset, - input [1:0] io_dec_i0_brp_bits_hist, - input io_dec_i0_brp_bits_br_error, - input io_dec_i0_brp_bits_br_start_error, - input [30:0] io_dec_i0_brp_bits_prett, - input io_dec_i0_brp_bits_way, - input io_dec_i0_brp_bits_ret, + input [11:0] io_dec_i0_brp_toffset, + input [1:0] io_dec_i0_brp_hist, + input io_dec_i0_brp_br_error, + input io_dec_i0_brp_br_start_error, + input [30:0] io_dec_i0_brp_prett, + input io_dec_i0_brp_way, + input io_dec_i0_brp_ret, input [7:0] io_dec_i0_bp_index, input [7:0] io_dec_i0_bp_fghr, input [4:0] io_dec_i0_bp_btag, @@ -1275,21 +1285,21 @@ module el2_dec_decode_ctl( wire _T_22 = _T_21 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 237:103] wire _T_23 = ~_T_22; // @[el2_dec_decode_ctl.scala 237:56] wire i0_notbr_error = i0_brp_valid & _T_23; // @[el2_dec_decode_ctl.scala 237:54] - wire _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:62] - wire _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[el2_dec_decode_ctl.scala 240:47] + wire _T_31 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:57] + wire _T_25 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 240:47] wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 415:41] wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 415:26] - wire _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:106] - wire _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:76] - wire _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:126] - wire i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:124] - wire _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:79] - wire _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[el2_dec_decode_ctl.scala 241:47] - wire i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:72] - wire i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:101] - wire _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[el2_dec_decode_ctl.scala 247:47] - wire i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:84] + wire _T_26 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:96] + wire _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:71] + wire _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:116] + wire i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:114] + wire _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:74] + wire _T_29 = i0_brp_valid & io_dec_i0_brp_ret; // @[el2_dec_decode_ctl.scala 241:47] + wire i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:67] + wire i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:96] + wire _T_39 = i0_br_error | io_dec_i0_brp_br_start_error; // @[el2_dec_decode_ctl.scala 247:47] + wire i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:79] wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 256:36] wire _T_41 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 260:25] wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] @@ -1318,8 +1328,8 @@ module el2_dec_decode_ctl( wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54] wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39] reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53] - reg x_d_valid; // @[el2_lib.scala 524:16] - wire _T_507 = postsync_stall & x_d_valid; // @[el2_dec_decode_ctl.scala 570:88] + reg x_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 570:88] wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69] wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] @@ -1334,7 +1344,7 @@ module el2_dec_decode_ctl( wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32] wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 644:46] wire _T_33 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 243:72] - wire _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:94] + wire _T_36 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:89] wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 260:50] wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] @@ -1411,42 +1421,42 @@ module el2_dec_decode_ctl( wire _T_45 = _T_44 | i0_pja; // @[el2_dec_decode_ctl.scala 274:49] wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 419:32] wire i0_predict_br = _T_45 | i0_pret; // @[el2_dec_decode_ctl.scala 274:58] - wire _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:55] + wire _T_47 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:50] wire _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26] wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20] wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63] - reg [2:0] cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] + reg [2:0] cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 347:47] wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 322:67] - wire _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_94 = _GEN_123 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_95 = cam_data_reset & _T_94; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:83] wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_51 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 303:78] - reg [2:0] cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + reg [2:0] cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_120 = _GEN_123 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_121 = cam_data_reset & _T_120; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:83] wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_54 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 303:78] wire _T_57 = cam_0_valid & _T_54; // @[el2_dec_decode_ctl.scala 303:126] wire [1:0] _T_59 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 303:158] - reg [2:0] cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + reg [2:0] cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_146 = _GEN_123 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_147 = cam_data_reset & _T_146; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:83] wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_60 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 303:78] wire _T_63 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 303:126] wire _T_66 = _T_63 & _T_60; // @[el2_dec_decode_ctl.scala 303:126] wire [2:0] _T_68 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 303:158] - reg [2:0] cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + reg [2:0] cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_172 = _GEN_123 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_173 = cam_data_reset & _T_172; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:83] wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_69 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 303:78] wire _T_75 = _T_63 & cam_2_valid; // @[el2_dec_decode_ctl.scala 303:126] @@ -1462,89 +1472,89 @@ module el2_dec_decode_ctl( wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72] wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72] wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] - reg x_d_bits_i0load; // @[el2_lib.scala 524:16] - reg [4:0] x_d_bits_i0rd; // @[el2_lib.scala 524:16] - wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] + reg x_d_i0load; // @[el2_lib.scala 524:16] + reg [4:0] x_d_i0rd; // @[el2_lib.scala 524:16] + wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49] wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] - reg r_d_bits_i0load; // @[el2_lib.scala 524:16] - wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 319:56] + reg r_d_i0load; // @[el2_lib.scala 524:16] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 319:56] wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66] - wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_91 = _GEN_130 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg r_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:51] - wire r_d_in_bits_i0v = r_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:49] - wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:47] - wire i0_wen_r = r_d_in_bits_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:45] - reg [4:0] r_d_bits_i0rd; // @[el2_lib.scala 524:16] - reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg r_d_i0v; // @[el2_lib.scala 524:16] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:41] + wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:39] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:42] + wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:40] + reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16] + reg [4:0] cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_103 = r_d_i0rd == cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + reg cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_106 = _T_104 & cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:95] wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:116] wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28] wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:100] - wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_117 = _GEN_130 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg [4:0] cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_129 = r_d_i0rd == cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + reg cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_132 = _T_130 & cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:95] wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:116] wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28] wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:100] - wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_143 = _GEN_130 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg [4:0] cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_155 = r_d_i0rd == cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + reg cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_158 = _T_156 & cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:95] wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:116] wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28] wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:100] - wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_169 = _GEN_130 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg [4:0] cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_181 = r_d_i0rd == cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + reg cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_184 = _T_182 & cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:95] wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:116] wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28] wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:100] - wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:49] - wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:81] + wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_195 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:44] + wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:76] wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95] wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95] wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95] @@ -1559,37 +1569,37 @@ module el2_dec_decode_ctl( wire _T_208 = _T_207 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 355:180] wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[el2_dec_decode_ctl.scala 355:118] wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:126] - wire _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] - wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:141] - wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:192] - wire _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] - wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_211 = _T_210 & cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_213 = cam_raw_0_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_216 = cam_raw_0_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:197] wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:126] - wire _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] - wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:141] - wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:192] - wire _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] - wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_220 = _T_219 & cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_222 = cam_raw_1_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_225 = cam_raw_1_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:197] wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:126] - wire _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] - wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:141] - wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:192] - wire _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] - wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_229 = _T_228 & cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_231 = cam_raw_2_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_234 = cam_raw_2_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:197] wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:126] - wire _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] - wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:141] - wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:192] - wire _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] - wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_238 = _T_237 & cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_240 = cam_raw_3_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_243 = cam_raw_3_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:197] wire [4:0] _T_245 = _T_211 | _T_220; // @[el2_dec_decode_ctl.scala 360:69] wire [4:0] _T_246 = _T_245 | _T_229; // @[el2_dec_decode_ctl.scala 360:69] wire _T_247 = _T_214 | _T_223; // @[el2_dec_decode_ctl.scala 360:102] @@ -1631,13 +1641,13 @@ module el2_dec_decode_ctl( reg _T_339; // @[el2_dec_decode_ctl.scala 432:58] wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40] wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43] - reg x_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_876 = io_dec_i0_rs1_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 768:48] - wire _T_877 = x_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:80] - wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:63] - wire _T_878 = io_dec_i0_rs1_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 769:48] - wire _T_879 = r_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:80] - wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:63] + reg x_d_i0v; // @[el2_lib.scala 524:16] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 768:48] + wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:70] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:58] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 769:48] + wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:70] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:58] wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63] wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24] wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58] @@ -1646,12 +1656,12 @@ module el2_dec_decode_ctl( wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61] wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24] wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78] - wire _T_880 = io_dec_i0_rs2_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 771:48] - wire _T_881 = x_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:80] - wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:63] - wire _T_882 = io_dec_i0_rs2_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 772:48] - wire _T_883 = r_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:80] - wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:63] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48] + wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:70] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:58] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:70] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:58] wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63] wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24] wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43] @@ -1659,16 +1669,16 @@ module el2_dec_decode_ctl( wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24] wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63] wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42] - reg r_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg r_d_valid; // @[el2_lib.scala 524:16] - wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[el2_dec_decode_ctl.scala 471:39] - reg [11:0] r_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:50] - wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:85] - wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:64] - wire _T_358 = _T_357 & r_d_bits_csrwen; // @[el2_dec_decode_ctl.scala 474:100] - wire _T_359 = _T_358 & r_d_valid; // @[el2_dec_decode_ctl.scala 474:118] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:132] + reg r_d_csrwen; // @[el2_lib.scala 524:16] + reg r_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 471:34] + reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:45] + wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:75] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:59] + wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 474:90] + wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:103] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:119] reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52] reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51] reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51] @@ -1698,14 +1708,14 @@ module el2_dec_decode_ctl( wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46] wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61] wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75] - reg r_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_764 = r_d_bits_i0v & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 710:42] + reg r_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 710:37] reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27] - reg x_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_432 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:43] - reg wbd_bits_csrwonly; // @[el2_lib.scala 524:16] - wire prior_csr_write = _T_432 | wbd_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:63] + reg x_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 516:38] + reg wbd_csrwonly; // @[el2_lib.scala 524:16] + wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 516:53] wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48] wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40] wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34] @@ -1722,8 +1732,8 @@ module el2_dec_decode_ctl( wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95] wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20] wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45] - wire prior_inflight = x_d_valid | r_d_valid; // @[el2_dec_decode_ctl.scala 564:41] - wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] + wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 564:41] + wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37] wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62] wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19] @@ -1779,13 +1789,13 @@ module el2_dec_decode_ctl( reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36] reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37] - reg r_d_bits_i0store; // @[el2_lib.scala 524:16] - wire _T_536 = r_d_bits_i0load | r_d_bits_i0store; // @[el2_dec_decode_ctl.scala 607:61] + reg r_d_i0store; // @[el2_lib.scala 524:16] + wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 607:56] wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] - wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:82] - wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:105] - reg r_d_bits_i0div; // @[el2_lib.scala 524:16] - wire _T_545 = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 613:58] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:72] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:95] + reg r_d_i0div; // @[el2_lib.scala 524:16] + wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 613:53] wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49] wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49] wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48] @@ -1821,34 +1831,34 @@ module el2_dec_decode_ctl( reg i0_r_c_alu; // @[Reg.scala 15:16] wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49] wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50] - reg x_d_bits_i0store; // @[el2_lib.scala 524:16] - reg x_d_bits_i0div; // @[el2_lib.scala 524:16] - reg x_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg [11:0] x_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_733 = x_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:47] - wire _T_737 = x_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 681:33] - wire _T_756 = ~r_d_bits_i0div; // @[el2_dec_decode_ctl.scala 696:49] + reg x_d_i0store; // @[el2_lib.scala 524:16] + reg x_d_i0div; // @[el2_lib.scala 524:16] + reg x_d_csrwen; // @[el2_lib.scala 524:16] + reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:37] + wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 681:37] + wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 696:49] wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47] - wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:70] - wire _T_761 = x_d_bits_i0v & x_d_bits_i0load; // @[el2_dec_decode_ctl.scala 705:47] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:65] + wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 705:42] wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52] wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] - wire _T_799 = x_d_bits_i0div & x_d_valid; // @[el2_dec_decode_ctl.scala 719:45] - wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:58] - wire _T_802 = x_d_bits_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:77] - wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:60] - wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:33] - wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:94] - wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:33] - wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:60] - wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:62] + wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 719:40] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:55] + wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:69] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:57] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:30] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:86] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:30] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:57] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:59] wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51] wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26] wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24] - wire _T_813 = r_d_bits_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:56] + wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:51] wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39] - wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:77] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:72] wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65] wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55] wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62] @@ -2147,7 +2157,7 @@ module el2_dec_decode_ctl( assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26] assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31] assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31] - assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[el2_dec_decode_ctl.scala 694:27] + assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 694:27] assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32] assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26] assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25] @@ -2179,10 +2189,10 @@ module el2_dec_decode_ctl( assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24] assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24] assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20] - assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] - assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] + assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] + assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27] - assign io_dec_tlu_i0_valid_r = r_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] + assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39] @@ -2191,22 +2201,22 @@ module el2_dec_decode_ctl( assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27] assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23] assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 764:25] assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 236:38] assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 234:43] - assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[el2_dec_decode_ctl.scala 235:43] + assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_hist; // @[el2_dec_decode_ctl.scala 235:43] assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 248:49] assign io_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[el2_dec_decode_ctl.scala 243:56] assign io_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[el2_dec_decode_ctl.scala 244:56] - assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[el2_dec_decode_ctl.scala 233:43] + assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_prett; // @[el2_dec_decode_ctl.scala 233:43] assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 230:43] assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 232:43] assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 231:43] - assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[el2_dec_decode_ctl.scala 250:56] + assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_way; // @[el2_dec_decode_ctl.scala 250:56] assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 249:32] assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 245:32] assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 246:32] @@ -2332,73 +2342,73 @@ initial begin _RAND_6 = {1{`RANDOM}}; postsync_stall = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - x_d_valid = _RAND_7[0:0]; + x_d_i0valid = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; flush_final_r = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; illegal_lockout = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; - cam_raw_0_bits_tag = _RAND_10[2:0]; + cam_raw_0_tag = _RAND_10[2:0]; _RAND_11 = {1{`RANDOM}}; cam_raw_0_valid = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - cam_raw_1_bits_tag = _RAND_12[2:0]; + cam_raw_1_tag = _RAND_12[2:0]; _RAND_13 = {1{`RANDOM}}; cam_raw_1_valid = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - cam_raw_2_bits_tag = _RAND_14[2:0]; + cam_raw_2_tag = _RAND_14[2:0]; _RAND_15 = {1{`RANDOM}}; cam_raw_2_valid = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - cam_raw_3_bits_tag = _RAND_16[2:0]; + cam_raw_3_tag = _RAND_16[2:0]; _RAND_17 = {1{`RANDOM}}; cam_raw_3_valid = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - x_d_bits_i0load = _RAND_18[0:0]; + x_d_i0load = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - x_d_bits_i0rd = _RAND_19[4:0]; + x_d_i0rd = _RAND_19[4:0]; _RAND_20 = {1{`RANDOM}}; _T_701 = _RAND_20[2:0]; _RAND_21 = {1{`RANDOM}}; nonblock_load_valid_m_delay = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - r_d_bits_i0load = _RAND_22[0:0]; + r_d_i0load = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - r_d_bits_i0v = _RAND_23[0:0]; + r_d_i0v = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - r_d_bits_i0rd = _RAND_24[4:0]; + r_d_i0rd = _RAND_24[4:0]; _RAND_25 = {1{`RANDOM}}; - cam_raw_0_bits_rd = _RAND_25[4:0]; + cam_raw_0_rd = _RAND_25[4:0]; _RAND_26 = {1{`RANDOM}}; - cam_raw_0_bits_wb = _RAND_26[0:0]; + cam_raw_0_wb = _RAND_26[0:0]; _RAND_27 = {1{`RANDOM}}; - cam_raw_1_bits_rd = _RAND_27[4:0]; + cam_raw_1_rd = _RAND_27[4:0]; _RAND_28 = {1{`RANDOM}}; - cam_raw_1_bits_wb = _RAND_28[0:0]; + cam_raw_1_wb = _RAND_28[0:0]; _RAND_29 = {1{`RANDOM}}; - cam_raw_2_bits_rd = _RAND_29[4:0]; + cam_raw_2_rd = _RAND_29[4:0]; _RAND_30 = {1{`RANDOM}}; - cam_raw_2_bits_wb = _RAND_30[0:0]; + cam_raw_2_wb = _RAND_30[0:0]; _RAND_31 = {1{`RANDOM}}; - cam_raw_3_bits_rd = _RAND_31[4:0]; + cam_raw_3_rd = _RAND_31[4:0]; _RAND_32 = {1{`RANDOM}}; - cam_raw_3_bits_wb = _RAND_32[0:0]; + cam_raw_3_wb = _RAND_32[0:0]; _RAND_33 = {1{`RANDOM}}; lsu_idle = _RAND_33[0:0]; _RAND_34 = {1{`RANDOM}}; _T_339 = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - x_d_bits_i0v = _RAND_35[0:0]; + x_d_i0v = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; i0_x_c_load = _RAND_36[0:0]; _RAND_37 = {1{`RANDOM}}; i0_r_c_load = _RAND_37[0:0]; _RAND_38 = {1{`RANDOM}}; - r_d_bits_csrwen = _RAND_38[0:0]; + r_d_csrwen = _RAND_38[0:0]; _RAND_39 = {1{`RANDOM}}; - r_d_valid = _RAND_39[0:0]; + r_d_i0valid = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - r_d_bits_csrwaddr = _RAND_40[11:0]; + r_d_csrwaddr = _RAND_40[11:0]; _RAND_41 = {1{`RANDOM}}; csr_read_x = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; @@ -2414,13 +2424,13 @@ initial begin _RAND_47 = {1{`RANDOM}}; csr_rddata_x = _RAND_47[31:0]; _RAND_48 = {1{`RANDOM}}; - r_d_bits_csrwonly = _RAND_48[0:0]; + r_d_csrwonly = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; i0_result_r_raw = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; - x_d_bits_csrwonly = _RAND_50[0:0]; + x_d_csrwonly = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - wbd_bits_csrwonly = _RAND_51[0:0]; + wbd_csrwonly = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; _T_465 = _RAND_52[31:0]; _RAND_53 = {1{`RANDOM}}; @@ -2460,9 +2470,9 @@ initial begin _RAND_70 = {1{`RANDOM}}; lsu_pmu_misaligned_r = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - r_d_bits_i0store = _RAND_71[0:0]; + r_d_i0store = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - r_d_bits_i0div = _RAND_72[0:0]; + r_d_i0div = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; i0_x_c_mul = _RAND_73[0:0]; _RAND_74 = {1{`RANDOM}}; @@ -2472,13 +2482,13 @@ initial begin _RAND_76 = {1{`RANDOM}}; i0_r_c_alu = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - x_d_bits_i0store = _RAND_77[0:0]; + x_d_i0store = _RAND_77[0:0]; _RAND_78 = {1{`RANDOM}}; - x_d_bits_i0div = _RAND_78[0:0]; + x_d_i0div = _RAND_78[0:0]; _RAND_79 = {1{`RANDOM}}; - x_d_bits_csrwen = _RAND_79[0:0]; + x_d_csrwen = _RAND_79[0:0]; _RAND_80 = {1{`RANDOM}}; - x_d_bits_csrwaddr = _RAND_80[11:0]; + x_d_csrwaddr = _RAND_80[11:0]; _RAND_81 = {1{`RANDOM}}; last_br_immed_x = _RAND_81[11:0]; _RAND_82 = {1{`RANDOM}}; @@ -2522,7 +2532,7 @@ initial begin postsync_stall = 1'h0; end if (reset) begin - x_d_valid = 1'h0; + x_d_i0valid = 1'h0; end if (reset) begin flush_final_r = 1'h0; @@ -2531,34 +2541,34 @@ initial begin illegal_lockout = 1'h0; end if (reset) begin - cam_raw_0_bits_tag = 3'h0; + cam_raw_0_tag = 3'h0; end if (reset) begin cam_raw_0_valid = 1'h0; end if (reset) begin - cam_raw_1_bits_tag = 3'h0; + cam_raw_1_tag = 3'h0; end if (reset) begin cam_raw_1_valid = 1'h0; end if (reset) begin - cam_raw_2_bits_tag = 3'h0; + cam_raw_2_tag = 3'h0; end if (reset) begin cam_raw_2_valid = 1'h0; end if (reset) begin - cam_raw_3_bits_tag = 3'h0; + cam_raw_3_tag = 3'h0; end if (reset) begin cam_raw_3_valid = 1'h0; end if (reset) begin - x_d_bits_i0load = 1'h0; + x_d_i0load = 1'h0; end if (reset) begin - x_d_bits_i0rd = 5'h0; + x_d_i0rd = 5'h0; end if (reset) begin _T_701 = 3'h0; @@ -2567,37 +2577,37 @@ initial begin nonblock_load_valid_m_delay = 1'h0; end if (reset) begin - r_d_bits_i0load = 1'h0; + r_d_i0load = 1'h0; end if (reset) begin - r_d_bits_i0v = 1'h0; + r_d_i0v = 1'h0; end if (reset) begin - r_d_bits_i0rd = 5'h0; + r_d_i0rd = 5'h0; end if (reset) begin - cam_raw_0_bits_rd = 5'h0; + cam_raw_0_rd = 5'h0; end if (reset) begin - cam_raw_0_bits_wb = 1'h0; + cam_raw_0_wb = 1'h0; end if (reset) begin - cam_raw_1_bits_rd = 5'h0; + cam_raw_1_rd = 5'h0; end if (reset) begin - cam_raw_1_bits_wb = 1'h0; + cam_raw_1_wb = 1'h0; end if (reset) begin - cam_raw_2_bits_rd = 5'h0; + cam_raw_2_rd = 5'h0; end if (reset) begin - cam_raw_2_bits_wb = 1'h0; + cam_raw_2_wb = 1'h0; end if (reset) begin - cam_raw_3_bits_rd = 5'h0; + cam_raw_3_rd = 5'h0; end if (reset) begin - cam_raw_3_bits_wb = 1'h0; + cam_raw_3_wb = 1'h0; end if (reset) begin lsu_idle = 1'h0; @@ -2606,16 +2616,16 @@ initial begin _T_339 = 1'h0; end if (reset) begin - x_d_bits_i0v = 1'h0; + x_d_i0v = 1'h0; end if (reset) begin - r_d_bits_csrwen = 1'h0; + r_d_csrwen = 1'h0; end if (reset) begin - r_d_valid = 1'h0; + r_d_i0valid = 1'h0; end if (reset) begin - r_d_bits_csrwaddr = 12'h0; + r_d_csrwaddr = 12'h0; end if (reset) begin csr_read_x = 1'h0; @@ -2639,16 +2649,16 @@ initial begin csr_rddata_x = 32'h0; end if (reset) begin - r_d_bits_csrwonly = 1'h0; + r_d_csrwonly = 1'h0; end if (reset) begin i0_result_r_raw = 32'h0; end if (reset) begin - x_d_bits_csrwonly = 1'h0; + x_d_csrwonly = 1'h0; end if (reset) begin - wbd_bits_csrwonly = 1'h0; + wbd_csrwonly = 1'h0; end if (reset) begin _T_465 = 32'h0; @@ -2708,22 +2718,22 @@ initial begin lsu_pmu_misaligned_r = 1'h0; end if (reset) begin - r_d_bits_i0store = 1'h0; + r_d_i0store = 1'h0; end if (reset) begin - r_d_bits_i0div = 1'h0; + r_d_i0div = 1'h0; end if (reset) begin - x_d_bits_i0store = 1'h0; + x_d_i0store = 1'h0; end if (reset) begin - x_d_bits_i0div = 1'h0; + x_d_i0div = 1'h0; end if (reset) begin - x_d_bits_csrwen = 1'h0; + x_d_csrwen = 1'h0; end if (reset) begin - x_d_bits_csrwaddr = 12'h0; + x_d_csrwaddr = 12'h0; end if (reset) begin last_br_immed_x = 12'h0; @@ -2836,9 +2846,9 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_valid <= 1'h0; + x_d_i0valid <= 1'h0; end else begin - x_d_valid <= io_dec_i0_decode_d; + x_d_i0valid <= io_dec_i0_decode_d; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -2857,11 +2867,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_bits_tag <= 3'h0; + cam_raw_0_tag <= 3'h0; end else if (cam_wen[0]) begin - cam_raw_0_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_0_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_107) begin - cam_raw_0_bits_tag <= 3'h0; + cam_raw_0_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -2875,11 +2885,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_bits_tag <= 3'h0; + cam_raw_1_tag <= 3'h0; end else if (cam_wen[1]) begin - cam_raw_1_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_1_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_133) begin - cam_raw_1_bits_tag <= 3'h0; + cam_raw_1_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -2893,11 +2903,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_bits_tag <= 3'h0; + cam_raw_2_tag <= 3'h0; end else if (cam_wen[2]) begin - cam_raw_2_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_2_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_159) begin - cam_raw_2_bits_tag <= 3'h0; + cam_raw_2_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -2911,11 +2921,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_bits_tag <= 3'h0; + cam_raw_3_tag <= 3'h0; end else if (cam_wen[3]) begin - cam_raw_3_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_3_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_185) begin - cam_raw_3_bits_tag <= 3'h0; + cam_raw_3_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -2929,16 +2939,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0load <= 1'h0; + x_d_i0load <= 1'h0; end else begin - x_d_bits_i0load <= i0_dp_load & i0_legal_decode_d; + x_d_i0load <= i0_dp_load & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0rd <= 5'h0; + x_d_i0rd <= 5'h0; end else begin - x_d_bits_i0rd <= io_dec_i0_instr_d[11:7]; + x_d_i0rd <= io_dec_i0_instr_d[11:7]; end end always @(posedge io_active_clk or posedge reset) begin @@ -2957,103 +2967,103 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0load <= 1'h0; + r_d_i0load <= 1'h0; end else begin - r_d_bits_i0load <= x_d_bits_i0load; + r_d_i0load <= x_d_i0load; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0v <= 1'h0; + r_d_i0v <= 1'h0; end else begin - r_d_bits_i0v <= _T_733 & _T_280; + r_d_i0v <= _T_733 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0rd <= 5'h0; + r_d_i0rd <= 5'h0; end else begin - r_d_bits_i0rd <= x_d_bits_i0rd; + r_d_i0rd <= x_d_i0rd; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_bits_rd <= 5'h0; + cam_raw_0_rd <= 5'h0; end else if (cam_wen[0]) begin - if (x_d_bits_i0load) begin - cam_raw_0_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_0_rd <= x_d_i0rd; end else begin - cam_raw_0_bits_rd <= 5'h0; + cam_raw_0_rd <= 5'h0; end end else if (_T_107) begin - cam_raw_0_bits_rd <= 5'h0; + cam_raw_0_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_bits_wb <= 1'h0; + cam_raw_0_wb <= 1'h0; end else begin - cam_raw_0_bits_wb <= _T_112 | _GEN_57; + cam_raw_0_wb <= _T_112 | _GEN_57; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_bits_rd <= 5'h0; + cam_raw_1_rd <= 5'h0; end else if (cam_wen[1]) begin - if (x_d_bits_i0load) begin - cam_raw_1_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_1_rd <= x_d_i0rd; end else begin - cam_raw_1_bits_rd <= 5'h0; + cam_raw_1_rd <= 5'h0; end end else if (_T_133) begin - cam_raw_1_bits_rd <= 5'h0; + cam_raw_1_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_bits_wb <= 1'h0; + cam_raw_1_wb <= 1'h0; end else begin - cam_raw_1_bits_wb <= _T_138 | _GEN_68; + cam_raw_1_wb <= _T_138 | _GEN_68; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_bits_rd <= 5'h0; + cam_raw_2_rd <= 5'h0; end else if (cam_wen[2]) begin - if (x_d_bits_i0load) begin - cam_raw_2_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_2_rd <= x_d_i0rd; end else begin - cam_raw_2_bits_rd <= 5'h0; + cam_raw_2_rd <= 5'h0; end end else if (_T_159) begin - cam_raw_2_bits_rd <= 5'h0; + cam_raw_2_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_bits_wb <= 1'h0; + cam_raw_2_wb <= 1'h0; end else begin - cam_raw_2_bits_wb <= _T_164 | _GEN_79; + cam_raw_2_wb <= _T_164 | _GEN_79; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_bits_rd <= 5'h0; + cam_raw_3_rd <= 5'h0; end else if (cam_wen[3]) begin - if (x_d_bits_i0load) begin - cam_raw_3_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_3_rd <= x_d_i0rd; end else begin - cam_raw_3_bits_rd <= 5'h0; + cam_raw_3_rd <= 5'h0; end end else if (_T_185) begin - cam_raw_3_bits_rd <= 5'h0; + cam_raw_3_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_bits_wb <= 1'h0; + cam_raw_3_wb <= 1'h0; end else begin - cam_raw_3_bits_wb <= _T_190 | _GEN_90; + cam_raw_3_wb <= _T_190 | _GEN_90; end end always @(posedge io_active_clk or posedge reset) begin @@ -3072,30 +3082,30 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0v <= 1'h0; + x_d_i0v <= 1'h0; end else begin - x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d; + x_d_i0v <= i0_rd_en_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwen <= 1'h0; + r_d_csrwen <= 1'h0; end else begin - r_d_bits_csrwen <= x_d_bits_csrwen; + r_d_csrwen <= x_d_csrwen; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_valid <= 1'h0; + r_d_i0valid <= 1'h0; end else begin - r_d_valid <= _T_737 & _T_280; + r_d_i0valid <= _T_737 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwaddr <= 12'h0; + r_d_csrwaddr <= 12'h0; end else begin - r_d_bits_csrwaddr <= x_d_bits_csrwaddr; + r_d_csrwaddr <= x_d_csrwaddr; end end always @(posedge io_active_clk or posedge reset) begin @@ -3151,9 +3161,9 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwonly <= 1'h0; + r_d_csrwonly <= 1'h0; end else begin - r_d_bits_csrwonly <= x_d_bits_csrwonly; + r_d_csrwonly <= x_d_csrwonly; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin @@ -3167,16 +3177,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwonly <= 1'h0; + x_d_csrwonly <= 1'h0; end else begin - x_d_bits_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; + x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin - wbd_bits_csrwonly <= 1'h0; + wbd_csrwonly <= 1'h0; end else begin - wbd_bits_csrwonly <= r_d_bits_csrwonly; + wbd_csrwonly <= r_d_csrwonly; end end always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin @@ -3316,44 +3326,44 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0store <= 1'h0; + r_d_i0store <= 1'h0; end else begin - r_d_bits_i0store <= x_d_bits_i0store; + r_d_i0store <= x_d_i0store; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0div <= 1'h0; + r_d_i0div <= 1'h0; end else begin - r_d_bits_i0div <= x_d_bits_i0div; + r_d_i0div <= x_d_i0div; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0store <= 1'h0; + x_d_i0store <= 1'h0; end else begin - x_d_bits_i0store <= i0_dp_store & i0_legal_decode_d; + x_d_i0store <= i0_dp_store & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0div <= 1'h0; + x_d_i0div <= 1'h0; end else begin - x_d_bits_i0div <= i0_dp_div & i0_legal_decode_d; + x_d_i0div <= i0_dp_div & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwen <= 1'h0; + x_d_csrwen <= 1'h0; end else begin - x_d_bits_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; + x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwaddr <= 12'h0; + x_d_csrwaddr <= 12'h0; end else begin - x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20]; + x_d_csrwaddr <= io_dec_i0_instr_d[31:20]; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -3608,423 +3618,423 @@ module el2_dec_gpr_ctl( wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23] wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23] - wire _T_95 = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_1 = io_wen0 & _T_95; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_112 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_2 = io_wen0 & _T_112; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_129 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_3 = io_wen0 & _T_129; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_146 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_4 = io_wen0 & _T_146; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_163 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_5 = io_wen0 & _T_163; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_180 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_6 = io_wen0 & _T_180; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_197 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_7 = io_wen0 & _T_197; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_214 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_8 = io_wen0 & _T_214; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_231 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_9 = io_wen0 & _T_231; // @[el2_dec_gpr_ctl.scala 26:28] - wire [9:0] _T_8 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] - wire _T_248 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_10 = io_wen0 & _T_248; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_265 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_11 = io_wen0 & _T_265; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_282 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_12 = io_wen0 & _T_282; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_299 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_13 = io_wen0 & _T_299; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_316 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_14 = io_wen0 & _T_316; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_333 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_15 = io_wen0 & _T_333; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_350 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_16 = io_wen0 & _T_350; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_367 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_17 = io_wen0 & _T_367; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_384 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_18 = io_wen0 & _T_384; // @[el2_dec_gpr_ctl.scala 26:28] - wire [18:0] _T_17 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_8}; // @[Cat.scala 29:58] - wire _T_401 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_19 = io_wen0 & _T_401; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_418 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_20 = io_wen0 & _T_418; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_435 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_21 = io_wen0 & _T_435; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_452 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_22 = io_wen0 & _T_452; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_469 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_23 = io_wen0 & _T_469; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_486 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_24 = io_wen0 & _T_486; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_503 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_25 = io_wen0 & _T_503; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_520 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_26 = io_wen0 & _T_520; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_537 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_27 = io_wen0 & _T_537; // @[el2_dec_gpr_ctl.scala 26:28] - wire [27:0] _T_26 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_17}; // @[Cat.scala 29:58] - wire _T_554 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_28 = io_wen0 & _T_554; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_571 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_29 = io_wen0 & _T_571; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_588 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_30 = io_wen0 & _T_588; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_605 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_31 = io_wen0 & _T_605; // @[el2_dec_gpr_ctl.scala 26:28] - wire [31:0] _T_30 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_26}; // @[Cat.scala 29:58] - wire _T_97 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_1 = io_wen1 & _T_97; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_114 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_2 = io_wen1 & _T_114; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_131 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_3 = io_wen1 & _T_131; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_148 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_4 = io_wen1 & _T_148; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_165 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_5 = io_wen1 & _T_165; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_182 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_6 = io_wen1 & _T_182; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_199 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_7 = io_wen1 & _T_199; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_216 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_8 = io_wen1 & _T_216; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_233 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_9 = io_wen1 & _T_233; // @[el2_dec_gpr_ctl.scala 27:28] - wire [9:0] _T_39 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] - wire _T_250 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_10 = io_wen1 & _T_250; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_267 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_11 = io_wen1 & _T_267; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_284 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_12 = io_wen1 & _T_284; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_301 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_13 = io_wen1 & _T_301; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_318 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_14 = io_wen1 & _T_318; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_335 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_15 = io_wen1 & _T_335; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_352 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_16 = io_wen1 & _T_352; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_369 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_17 = io_wen1 & _T_369; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_386 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_18 = io_wen1 & _T_386; // @[el2_dec_gpr_ctl.scala 27:28] - wire [18:0] _T_48 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_39}; // @[Cat.scala 29:58] - wire _T_403 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_19 = io_wen1 & _T_403; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_420 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_20 = io_wen1 & _T_420; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_437 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_21 = io_wen1 & _T_437; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_454 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_22 = io_wen1 & _T_454; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_471 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_23 = io_wen1 & _T_471; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_488 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_24 = io_wen1 & _T_488; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_505 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_25 = io_wen1 & _T_505; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_522 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_26 = io_wen1 & _T_522; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_539 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_27 = io_wen1 & _T_539; // @[el2_dec_gpr_ctl.scala 27:28] - wire [27:0] _T_57 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_48}; // @[Cat.scala 29:58] - wire _T_556 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_28 = io_wen1 & _T_556; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_573 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_29 = io_wen1 & _T_573; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_590 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_30 = io_wen1 & _T_590; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_607 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_31 = io_wen1 & _T_607; // @[el2_dec_gpr_ctl.scala 27:28] - wire [31:0] _T_61 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_57}; // @[Cat.scala 29:58] - wire [31:0] _T_62 = _T_30 | _T_61; // @[el2_dec_gpr_ctl.scala 23:51] - wire _T_99 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_1 = io_wen2 & _T_99; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_116 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_2 = io_wen2 & _T_116; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_133 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_3 = io_wen2 & _T_133; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_150 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_4 = io_wen2 & _T_150; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_167 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_5 = io_wen2 & _T_167; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_184 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_6 = io_wen2 & _T_184; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_201 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_7 = io_wen2 & _T_201; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_218 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_8 = io_wen2 & _T_218; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_235 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_9 = io_wen2 & _T_235; // @[el2_dec_gpr_ctl.scala 28:28] - wire [9:0] _T_71 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] - wire _T_252 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_10 = io_wen2 & _T_252; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_269 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_11 = io_wen2 & _T_269; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_286 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_12 = io_wen2 & _T_286; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_303 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_13 = io_wen2 & _T_303; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_320 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_14 = io_wen2 & _T_320; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_337 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_15 = io_wen2 & _T_337; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_354 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_16 = io_wen2 & _T_354; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_371 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_17 = io_wen2 & _T_371; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_388 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_18 = io_wen2 & _T_388; // @[el2_dec_gpr_ctl.scala 28:28] - wire [18:0] _T_80 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_71}; // @[Cat.scala 29:58] - wire _T_405 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_19 = io_wen2 & _T_405; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_422 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_20 = io_wen2 & _T_422; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_439 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_21 = io_wen2 & _T_439; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_456 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_22 = io_wen2 & _T_456; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_473 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_23 = io_wen2 & _T_473; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_490 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_24 = io_wen2 & _T_490; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_507 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_25 = io_wen2 & _T_507; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_524 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_26 = io_wen2 & _T_524; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_541 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_27 = io_wen2 & _T_541; // @[el2_dec_gpr_ctl.scala 28:28] - wire [27:0] _T_89 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_80}; // @[Cat.scala 29:58] - wire _T_558 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_28 = io_wen2 & _T_558; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_575 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_29 = io_wen2 & _T_575; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_592 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_30 = io_wen2 & _T_592; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_609 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_31 = io_wen2 & _T_609; // @[el2_dec_gpr_ctl.scala 28:28] - wire [31:0] _T_93 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_89}; // @[Cat.scala 29:58] - wire [31:0] gpr_wr_en = _T_62 | _T_93; // @[el2_dec_gpr_ctl.scala 23:89] - wire [31:0] _T_102 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_103 = _T_102 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_105 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_106 = _T_105 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_107 = _T_103 | _T_106; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_109 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_110 = _T_109 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_119 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_120 = _T_119 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_122 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_123 = _T_122 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_124 = _T_120 | _T_123; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_126 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_127 = _T_126 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_136 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_137 = _T_136 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_139 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_140 = _T_139 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_141 = _T_137 | _T_140; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_143 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_144 = _T_143 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_153 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_154 = _T_153 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_156 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_157 = _T_156 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_158 = _T_154 | _T_157; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_160 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_161 = _T_160 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_170 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_171 = _T_170 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_173 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_174 = _T_173 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_175 = _T_171 | _T_174; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_177 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_178 = _T_177 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_187 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_188 = _T_187 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_190 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_191 = _T_190 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_192 = _T_188 | _T_191; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_194 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_195 = _T_194 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_204 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_205 = _T_204 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_207 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_208 = _T_207 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_209 = _T_205 | _T_208; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_211 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_212 = _T_211 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_221 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_222 = _T_221 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_224 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_225 = _T_224 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_226 = _T_222 | _T_225; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_228 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_229 = _T_228 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_238 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_239 = _T_238 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_241 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_242 = _T_241 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_243 = _T_239 | _T_242; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_245 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_246 = _T_245 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_255 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_256 = _T_255 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_258 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_259 = _T_258 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_260 = _T_256 | _T_259; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_262 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_263 = _T_262 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_272 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_273 = _T_272 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_275 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_276 = _T_275 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_277 = _T_273 | _T_276; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_279 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_280 = _T_279 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_289 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_290 = _T_289 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_292 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_293 = _T_292 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_294 = _T_290 | _T_293; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_296 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_297 = _T_296 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_306 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_307 = _T_306 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_309 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_310 = _T_309 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_311 = _T_307 | _T_310; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_313 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_314 = _T_313 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_323 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_324 = _T_323 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_326 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_327 = _T_326 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_328 = _T_324 | _T_327; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_330 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_331 = _T_330 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_340 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_341 = _T_340 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_343 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_344 = _T_343 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_345 = _T_341 | _T_344; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_347 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_348 = _T_347 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_357 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_358 = _T_357 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_360 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_361 = _T_360 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_362 = _T_358 | _T_361; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_364 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_365 = _T_364 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_374 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_375 = _T_374 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_377 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_378 = _T_377 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_379 = _T_375 | _T_378; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_381 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_382 = _T_381 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_391 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_392 = _T_391 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_394 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_395 = _T_394 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_396 = _T_392 | _T_395; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_398 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_399 = _T_398 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_408 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_409 = _T_408 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_411 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_412 = _T_411 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_413 = _T_409 | _T_412; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_415 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_416 = _T_415 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_425 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_426 = _T_425 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_428 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_429 = _T_428 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_430 = _T_426 | _T_429; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_432 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_433 = _T_432 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_442 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_443 = _T_442 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_445 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_446 = _T_445 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_447 = _T_443 | _T_446; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_449 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_450 = _T_449 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_459 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_460 = _T_459 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_462 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_463 = _T_462 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_464 = _T_460 | _T_463; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_466 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_467 = _T_466 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_476 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_477 = _T_476 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_479 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_480 = _T_479 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_481 = _T_477 | _T_480; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_483 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_484 = _T_483 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_493 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_494 = _T_493 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_496 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_497 = _T_496 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_498 = _T_494 | _T_497; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_500 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_501 = _T_500 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_510 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_511 = _T_510 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_513 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_514 = _T_513 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_515 = _T_511 | _T_514; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_517 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_518 = _T_517 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_527 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_528 = _T_527 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_530 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_531 = _T_530 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_532 = _T_528 | _T_531; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_534 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_535 = _T_534 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_544 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_545 = _T_544 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_547 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_548 = _T_547 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_549 = _T_545 | _T_548; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_551 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_552 = _T_551 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_561 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_562 = _T_561 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_564 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_565 = _T_564 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_566 = _T_562 | _T_565; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_568 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_569 = _T_568 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_578 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_579 = _T_578 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_581 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_582 = _T_581 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_583 = _T_579 | _T_582; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_585 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_586 = _T_585 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_595 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_596 = _T_595 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_598 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_599 = _T_598 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_600 = _T_596 | _T_599; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_602 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_603 = _T_602 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_612 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_613 = _T_612 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_615 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_616 = _T_615 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_617 = _T_613 | _T_616; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_619 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_620 = _T_619 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire _T = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_1 = io_wen0 & _T; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_2 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_1 = io_wen1 & _T_2; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_4 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_1 = io_wen2 & _T_4; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_7 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_8 = _T_7 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_10 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_11 = _T_10 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_12 = _T_8 | _T_11; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_14 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_15 = _T_14 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_17 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_2 = io_wen0 & _T_17; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_19 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_2 = io_wen1 & _T_19; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_21 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_2 = io_wen2 & _T_21; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_24 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_25 = _T_24 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_27 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_28 = _T_27 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_29 = _T_25 | _T_28; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_31 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_32 = _T_31 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_34 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_3 = io_wen0 & _T_34; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_36 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_3 = io_wen1 & _T_36; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_38 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_3 = io_wen2 & _T_38; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_41 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_42 = _T_41 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_44 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_45 = _T_44 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_46 = _T_42 | _T_45; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_48 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_49 = _T_48 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_51 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_4 = io_wen0 & _T_51; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_53 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_4 = io_wen1 & _T_53; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_55 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_4 = io_wen2 & _T_55; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_58 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_59 = _T_58 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_61 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_62 = _T_61 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_63 = _T_59 | _T_62; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_65 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_66 = _T_65 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_68 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_5 = io_wen0 & _T_68; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_70 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_5 = io_wen1 & _T_70; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_72 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_5 = io_wen2 & _T_72; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_75 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_76 = _T_75 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_78 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_79 = _T_78 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_80 = _T_76 | _T_79; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_82 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_83 = _T_82 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_85 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_6 = io_wen0 & _T_85; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_87 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_6 = io_wen1 & _T_87; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_89 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_6 = io_wen2 & _T_89; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_92 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_93 = _T_92 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_95 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_96 = _T_95 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_97 = _T_93 | _T_96; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_99 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_100 = _T_99 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_102 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_7 = io_wen0 & _T_102; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_104 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_7 = io_wen1 & _T_104; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_106 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_7 = io_wen2 & _T_106; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_109 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_110 = _T_109 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_112 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_113 = _T_112 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_114 = _T_110 | _T_113; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_116 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_117 = _T_116 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_119 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_8 = io_wen0 & _T_119; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_121 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_8 = io_wen1 & _T_121; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_123 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_8 = io_wen2 & _T_123; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_126 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_127 = _T_126 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_129 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_130 = _T_129 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_131 = _T_127 | _T_130; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_133 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_134 = _T_133 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_136 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_9 = io_wen0 & _T_136; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_138 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_9 = io_wen1 & _T_138; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_140 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_9 = io_wen2 & _T_140; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_143 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_144 = _T_143 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_146 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_147 = _T_146 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_148 = _T_144 | _T_147; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_150 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_151 = _T_150 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_153 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_10 = io_wen0 & _T_153; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_155 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_10 = io_wen1 & _T_155; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_157 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_10 = io_wen2 & _T_157; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_160 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = _T_160 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_163 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_164 = _T_163 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_165 = _T_161 | _T_164; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_167 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_168 = _T_167 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_170 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_11 = io_wen0 & _T_170; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_172 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_11 = io_wen1 & _T_172; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_174 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_11 = io_wen2 & _T_174; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_177 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = _T_177 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_180 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_181 = _T_180 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_182 = _T_178 | _T_181; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_184 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_185 = _T_184 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_187 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_12 = io_wen0 & _T_187; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_189 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_12 = io_wen1 & _T_189; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_191 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_12 = io_wen2 & _T_191; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_194 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = _T_194 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_197 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_198 = _T_197 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_199 = _T_195 | _T_198; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_201 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_202 = _T_201 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_204 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_13 = io_wen0 & _T_204; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_206 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_13 = io_wen1 & _T_206; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_208 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_13 = io_wen2 & _T_208; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_211 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_211 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_214 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_215 = _T_214 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_216 = _T_212 | _T_215; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_218 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_219 = _T_218 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_221 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_14 = io_wen0 & _T_221; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_223 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_14 = io_wen1 & _T_223; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_225 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_14 = io_wen2 & _T_225; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_228 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = _T_228 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_231 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_232 = _T_231 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_233 = _T_229 | _T_232; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_235 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_236 = _T_235 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_238 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_15 = io_wen0 & _T_238; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_240 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_15 = io_wen1 & _T_240; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_242 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_15 = io_wen2 & _T_242; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_245 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_245 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_248 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_249 = _T_248 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_250 = _T_246 | _T_249; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_252 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_253 = _T_252 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_255 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_16 = io_wen0 & _T_255; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_257 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_16 = io_wen1 & _T_257; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_259 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_16 = io_wen2 & _T_259; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_262 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_263 = _T_262 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_265 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_266 = _T_265 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_267 = _T_263 | _T_266; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_269 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_270 = _T_269 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_272 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_17 = io_wen0 & _T_272; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_274 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_17 = io_wen1 & _T_274; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_276 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_17 = io_wen2 & _T_276; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_279 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = _T_279 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_282 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_283 = _T_282 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_284 = _T_280 | _T_283; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_286 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_287 = _T_286 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_289 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_18 = io_wen0 & _T_289; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_291 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_18 = io_wen1 & _T_291; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_293 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_18 = io_wen2 & _T_293; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_296 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_297 = _T_296 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_299 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_300 = _T_299 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_301 = _T_297 | _T_300; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_303 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_304 = _T_303 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_306 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_19 = io_wen0 & _T_306; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_308 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_19 = io_wen1 & _T_308; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_310 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_19 = io_wen2 & _T_310; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_313 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_314 = _T_313 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_316 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_317 = _T_316 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_318 = _T_314 | _T_317; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_320 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_321 = _T_320 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_323 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_20 = io_wen0 & _T_323; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_325 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_20 = io_wen1 & _T_325; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_327 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_20 = io_wen2 & _T_327; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_330 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_331 = _T_330 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_333 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_334 = _T_333 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_335 = _T_331 | _T_334; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_337 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_338 = _T_337 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_340 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_21 = io_wen0 & _T_340; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_342 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_21 = io_wen1 & _T_342; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_344 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_21 = io_wen2 & _T_344; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_347 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_348 = _T_347 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_350 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_351 = _T_350 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_352 = _T_348 | _T_351; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_354 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_355 = _T_354 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_357 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_22 = io_wen0 & _T_357; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_359 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_22 = io_wen1 & _T_359; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_361 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_22 = io_wen2 & _T_361; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_364 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_365 = _T_364 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_367 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_368 = _T_367 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_369 = _T_365 | _T_368; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_371 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_372 = _T_371 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_374 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_23 = io_wen0 & _T_374; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_376 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_23 = io_wen1 & _T_376; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_378 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_23 = io_wen2 & _T_378; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_381 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_382 = _T_381 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_384 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_385 = _T_384 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_386 = _T_382 | _T_385; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_388 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_389 = _T_388 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_391 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_24 = io_wen0 & _T_391; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_393 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_24 = io_wen1 & _T_393; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_395 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_24 = io_wen2 & _T_395; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_398 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_399 = _T_398 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_401 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_402 = _T_401 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_403 = _T_399 | _T_402; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_405 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_406 = _T_405 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_408 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_25 = io_wen0 & _T_408; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_410 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_25 = io_wen1 & _T_410; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_412 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_25 = io_wen2 & _T_412; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_415 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_418 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_419 = _T_418 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_420 = _T_416 | _T_419; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_422 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_423 = _T_422 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_425 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_26 = io_wen0 & _T_425; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_427 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_26 = io_wen1 & _T_427; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_429 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_26 = io_wen2 & _T_429; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_432 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_433 = _T_432 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_435 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_436 = _T_435 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_437 = _T_433 | _T_436; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_439 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_442 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_27 = io_wen0 & _T_442; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_444 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_27 = io_wen1 & _T_444; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_446 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_27 = io_wen2 & _T_446; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_449 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_452 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_453 = _T_452 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_454 = _T_450 | _T_453; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_456 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_457 = _T_456 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_459 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_28 = io_wen0 & _T_459; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_461 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_28 = io_wen1 & _T_461; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_463 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_28 = io_wen2 & _T_463; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_466 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_467 = _T_466 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_469 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_470 = _T_469 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_471 = _T_467 | _T_470; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_473 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_474 = _T_473 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_476 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_29 = io_wen0 & _T_476; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_478 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_29 = io_wen1 & _T_478; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_480 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_29 = io_wen2 & _T_480; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_483 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_484 = _T_483 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_486 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_487 = _T_486 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_488 = _T_484 | _T_487; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_490 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_491 = _T_490 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_493 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_30 = io_wen0 & _T_493; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_495 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_30 = io_wen1 & _T_495; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_497 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_30 = io_wen2 & _T_497; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_500 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_501 = _T_500 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_503 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_504 = _T_503 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_505 = _T_501 | _T_504; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_507 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_508 = _T_507 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_510 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_31 = io_wen0 & _T_510; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_512 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_31 = io_wen1 & _T_512; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_514 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_31 = io_wen2 & _T_514; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_517 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_518 = _T_517 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_520 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_521 = _T_520 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_522 = _T_518 | _T_521; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_524 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_525 = _T_524 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire [9:0] _T_535 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_544 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_535}; // @[Cat.scala 29:58] + wire [27:0] _T_553 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_544}; // @[Cat.scala 29:58] + wire [31:0] _T_557 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_553}; // @[Cat.scala 29:58] + wire [9:0] _T_566 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_575 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_566}; // @[Cat.scala 29:58] + wire [27:0] _T_584 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_575}; // @[Cat.scala 29:58] + wire [31:0] _T_588 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_584}; // @[Cat.scala 29:58] + wire [31:0] _T_589 = _T_557 | _T_588; // @[el2_dec_gpr_ctl.scala 40:51] + wire [9:0] _T_598 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_607 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_598}; // @[Cat.scala 29:58] + wire [27:0] _T_616 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_607}; // @[Cat.scala 29:58] + wire [31:0] _T_620 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_616}; // @[Cat.scala 29:58] + wire [31:0] gpr_wr_en = _T_589 | _T_620; // @[el2_dec_gpr_ctl.scala 40:89] reg [31:0] gpr_out_1; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_2; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_3; // @[el2_lib.scala 514:16] @@ -4056,37 +4066,37 @@ module el2_dec_gpr_ctl( reg [31:0] gpr_out_29; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_30; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_31; // @[el2_lib.scala 514:16] - wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 47:49] wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] @@ -4147,37 +4157,37 @@ module el2_dec_gpr_ctl( wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72] wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72] wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72] - wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 48:49] wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] @@ -4424,8 +4434,8 @@ module el2_dec_gpr_ctl( .io_en(rvclkhdr_30_io_en), .io_scan_mode(rvclkhdr_30_io_scan_mode) ); - assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 21:9 el2_dec_gpr_ctl.scala 36:9] - assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 22:9 el2_dec_gpr_ctl.scala 37:9] + assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 31:9 el2_dec_gpr_ctl.scala 47:9] + assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 32:9 el2_dec_gpr_ctl.scala 48:9] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_en = gpr_wr_en[1]; // @[el2_lib.scala 511:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] @@ -4720,217 +4730,217 @@ end // initial if (reset) begin gpr_out_1 <= 32'h0; end else begin - gpr_out_1 <= _T_107 | _T_110; + gpr_out_1 <= _T_12 | _T_15; end end always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin gpr_out_2 <= 32'h0; end else begin - gpr_out_2 <= _T_124 | _T_127; + gpr_out_2 <= _T_29 | _T_32; end end always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin gpr_out_3 <= 32'h0; end else begin - gpr_out_3 <= _T_141 | _T_144; + gpr_out_3 <= _T_46 | _T_49; end end always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin gpr_out_4 <= 32'h0; end else begin - gpr_out_4 <= _T_158 | _T_161; + gpr_out_4 <= _T_63 | _T_66; end end always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin if (reset) begin gpr_out_5 <= 32'h0; end else begin - gpr_out_5 <= _T_175 | _T_178; + gpr_out_5 <= _T_80 | _T_83; end end always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin gpr_out_6 <= 32'h0; end else begin - gpr_out_6 <= _T_192 | _T_195; + gpr_out_6 <= _T_97 | _T_100; end end always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin gpr_out_7 <= 32'h0; end else begin - gpr_out_7 <= _T_209 | _T_212; + gpr_out_7 <= _T_114 | _T_117; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin gpr_out_8 <= 32'h0; end else begin - gpr_out_8 <= _T_226 | _T_229; + gpr_out_8 <= _T_131 | _T_134; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin gpr_out_9 <= 32'h0; end else begin - gpr_out_9 <= _T_243 | _T_246; + gpr_out_9 <= _T_148 | _T_151; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin gpr_out_10 <= 32'h0; end else begin - gpr_out_10 <= _T_260 | _T_263; + gpr_out_10 <= _T_165 | _T_168; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin gpr_out_11 <= 32'h0; end else begin - gpr_out_11 <= _T_277 | _T_280; + gpr_out_11 <= _T_182 | _T_185; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin if (reset) begin gpr_out_12 <= 32'h0; end else begin - gpr_out_12 <= _T_294 | _T_297; + gpr_out_12 <= _T_199 | _T_202; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin gpr_out_13 <= 32'h0; end else begin - gpr_out_13 <= _T_311 | _T_314; + gpr_out_13 <= _T_216 | _T_219; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin gpr_out_14 <= 32'h0; end else begin - gpr_out_14 <= _T_328 | _T_331; + gpr_out_14 <= _T_233 | _T_236; end end always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin if (reset) begin gpr_out_15 <= 32'h0; end else begin - gpr_out_15 <= _T_345 | _T_348; + gpr_out_15 <= _T_250 | _T_253; end end always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin if (reset) begin gpr_out_16 <= 32'h0; end else begin - gpr_out_16 <= _T_362 | _T_365; + gpr_out_16 <= _T_267 | _T_270; end end always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin if (reset) begin gpr_out_17 <= 32'h0; end else begin - gpr_out_17 <= _T_379 | _T_382; + gpr_out_17 <= _T_284 | _T_287; end end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin gpr_out_18 <= 32'h0; end else begin - gpr_out_18 <= _T_396 | _T_399; + gpr_out_18 <= _T_301 | _T_304; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin gpr_out_19 <= 32'h0; end else begin - gpr_out_19 <= _T_413 | _T_416; + gpr_out_19 <= _T_318 | _T_321; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin gpr_out_20 <= 32'h0; end else begin - gpr_out_20 <= _T_430 | _T_433; + gpr_out_20 <= _T_335 | _T_338; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin if (reset) begin gpr_out_21 <= 32'h0; end else begin - gpr_out_21 <= _T_447 | _T_450; + gpr_out_21 <= _T_352 | _T_355; end end always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin if (reset) begin gpr_out_22 <= 32'h0; end else begin - gpr_out_22 <= _T_464 | _T_467; + gpr_out_22 <= _T_369 | _T_372; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin if (reset) begin gpr_out_23 <= 32'h0; end else begin - gpr_out_23 <= _T_481 | _T_484; + gpr_out_23 <= _T_386 | _T_389; end end always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin if (reset) begin gpr_out_24 <= 32'h0; end else begin - gpr_out_24 <= _T_498 | _T_501; + gpr_out_24 <= _T_403 | _T_406; end end always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin if (reset) begin gpr_out_25 <= 32'h0; end else begin - gpr_out_25 <= _T_515 | _T_518; + gpr_out_25 <= _T_420 | _T_423; end end always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin if (reset) begin gpr_out_26 <= 32'h0; end else begin - gpr_out_26 <= _T_532 | _T_535; + gpr_out_26 <= _T_437 | _T_440; end end always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin if (reset) begin gpr_out_27 <= 32'h0; end else begin - gpr_out_27 <= _T_549 | _T_552; + gpr_out_27 <= _T_454 | _T_457; end end always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin if (reset) begin gpr_out_28 <= 32'h0; end else begin - gpr_out_28 <= _T_566 | _T_569; + gpr_out_28 <= _T_471 | _T_474; end end always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin if (reset) begin gpr_out_29 <= 32'h0; end else begin - gpr_out_29 <= _T_583 | _T_586; + gpr_out_29 <= _T_488 | _T_491; end end always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin if (reset) begin gpr_out_30 <= 32'h0; end else begin - gpr_out_30 <= _T_600 | _T_603; + gpr_out_30 <= _T_505 | _T_508; end end always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin if (reset) begin gpr_out_31 <= 32'h0; end else begin - gpr_out_31 <= _T_617 | _T_620; + gpr_out_31 <= _T_522 | _T_525; end end endmodule @@ -5005,7 +5015,7 @@ module el2_dec_timer_ctl( wire _T_10 = ~io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 2765:167] wire mitcnt0_inc_ok = _T_9 & _T_10; // @[el2_dec_tlu_ctl.scala 2765:165] wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[el2_dec_tlu_ctl.scala 2766:29] - wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:60] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:59] wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[el2_dec_tlu_ctl.scala 2775:66] wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[el2_dec_tlu_ctl.scala 2775:43] reg [2:0] _T_66; // @[el2_dec_tlu_ctl.scala 2830:46] @@ -5250,28 +5260,28 @@ module csr_tlu( output io_dec_tlu_ic_diag_pkt_icache_wr_valid, input io_ifu_ic_debug_rd_data_valid, output io_trigger_pkt_any_0_select, - output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_match_pkt, output io_trigger_pkt_any_0_store, output io_trigger_pkt_any_0_load, output io_trigger_pkt_any_0_execute, output io_trigger_pkt_any_0_m, output [31:0] io_trigger_pkt_any_0_tdata2, output io_trigger_pkt_any_1_select, - output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_match_pkt, output io_trigger_pkt_any_1_store, output io_trigger_pkt_any_1_load, output io_trigger_pkt_any_1_execute, output io_trigger_pkt_any_1_m, output [31:0] io_trigger_pkt_any_1_tdata2, output io_trigger_pkt_any_2_select, - output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_match_pkt, output io_trigger_pkt_any_2_store, output io_trigger_pkt_any_2_load, output io_trigger_pkt_any_2_execute, output io_trigger_pkt_any_2_m, output [31:0] io_trigger_pkt_any_2_tdata2, output io_trigger_pkt_any_3_select, - output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_match_pkt, output io_trigger_pkt_any_3_store, output io_trigger_pkt_any_3_load, output io_trigger_pkt_any_3_execute, @@ -5350,7 +5360,7 @@ module csr_tlu( output io_dec_tlu_external_ldfwd_disable, output [2:0] io_dec_tlu_dma_qos_prty, input [31:0] io_dec_illegal_inst, - input io_lsu_error_pkt_r_bits_mscause, + input [3:0] io_lsu_error_pkt_r_bits_mscause, input io_mexintpend, input [30:0] io_exu_npc_r, input io_mpc_reset_run_req, @@ -5786,7 +5796,7 @@ module csr_tlu( wire [31:0] _T_533 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] wire [31:0] _GEN_12 = {{31'd0}, _T_531}; // @[el2_dec_tlu_ctl.scala 1946:61] wire [31:0] _T_534 = _GEN_12 & _T_533; // @[el2_dec_tlu_ctl.scala 1946:61] - wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1455:41 el2_dec_tlu_ctl.scala 1946:15] + wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1946:15] wire ce_int = _T_61 | mice_ce_req; // @[el2_dec_tlu_ctl.scala 1570:47] wire [2:0] _T_63 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_65 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] @@ -5916,14 +5926,14 @@ module csr_tlu( wire _T_237 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[el2_dec_tlu_ctl.scala 1741:57] wire [3:0] _T_238 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] wire [3:0] ifu_mscause = _T_237 ? 4'h9 : _T_238; // @[el2_dec_tlu_ctl.scala 1741:25] - wire _T_243 = io_lsu_i0_exc_r & io_lsu_error_pkt_r_bits_mscause; // @[Mux.scala 27:72] + wire [3:0] _T_243 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] wire [1:0] _T_245 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [3:0] _T_246 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] - wire _T_247 = _T_243 | io_i0_trigger_hit_r; // @[Mux.scala 27:72] - wire [1:0] _GEN_13 = {{1'd0}, _T_247}; // @[Mux.scala 27:72] - wire [1:0] _T_248 = _GEN_13 | _T_245; // @[Mux.scala 27:72] - wire [3:0] _GEN_14 = {{2'd0}, _T_248}; // @[Mux.scala 27:72] - wire [3:0] mscause_type = _GEN_14 | _T_246; // @[Mux.scala 27:72] + wire [3:0] _GEN_13 = {{3'd0}, io_i0_trigger_hit_r}; // @[Mux.scala 27:72] + wire [3:0] _T_247 = _T_243 | _GEN_13; // @[Mux.scala 27:72] + wire [3:0] _GEN_14 = {{2'd0}, _T_245}; // @[Mux.scala 27:72] + wire [3:0] _T_248 = _T_247 | _GEN_14; // @[Mux.scala 27:72] + wire [3:0] mscause_type = _T_248 | _T_246; // @[Mux.scala 27:72] wire _T_252 = wr_mscause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1752:19] wire _T_255 = ~wr_mscause_r; // @[el2_dec_tlu_ctl.scala 1753:6] wire _T_257 = _T_255 & _T_15; // @[el2_dec_tlu_ctl.scala 1753:20] @@ -7459,28 +7469,28 @@ module csr_tlu( assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2243:42] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2244:42] assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_0_match_ = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[el2_dec_tlu_ctl.scala 2312:36] assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 2313:36] assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[el2_dec_tlu_ctl.scala 2326:53] assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_1_match_ = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[el2_dec_tlu_ctl.scala 2312:36] assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 2313:36] assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[el2_dec_tlu_ctl.scala 2326:53] assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_2_match_ = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[el2_dec_tlu_ctl.scala 2312:36] assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 2313:36] assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[el2_dec_tlu_ctl.scala 2326:53] assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_3_match_ = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[el2_dec_tlu_ctl.scala 2312:36] @@ -9130,8 +9140,8 @@ module el2_dec_tlu_ctl( input io_lsu_error_pkt_r_bits_single_ecc_error, input io_lsu_error_pkt_r_bits_inst_type, input io_lsu_error_pkt_r_bits_exc_type, - input io_lsu_error_pkt_r_bits_mscause, - input io_lsu_error_pkt_r_bits_addr, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, input io_lsu_single_ecc_error_incr, input io_dec_pause_state, input io_lsu_imprecise_error_store_any, @@ -9184,28 +9194,28 @@ module el2_dec_tlu_ctl( input io_lsu_idle_any, input io_dec_div_active, output io_trigger_pkt_any_0_select, - output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_match_pkt, output io_trigger_pkt_any_0_store, output io_trigger_pkt_any_0_load, output io_trigger_pkt_any_0_execute, output io_trigger_pkt_any_0_m, output [31:0] io_trigger_pkt_any_0_tdata2, output io_trigger_pkt_any_1_select, - output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_match_pkt, output io_trigger_pkt_any_1_store, output io_trigger_pkt_any_1_load, output io_trigger_pkt_any_1_execute, output io_trigger_pkt_any_1_m, output [31:0] io_trigger_pkt_any_1_tdata2, output io_trigger_pkt_any_2_select, - output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_match_pkt, output io_trigger_pkt_any_2_store, output io_trigger_pkt_any_2_load, output io_trigger_pkt_any_2_execute, output io_trigger_pkt_any_2_m, output [31:0] io_trigger_pkt_any_2_tdata2, output io_trigger_pkt_any_3_select, - output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_match_pkt, output io_trigger_pkt_any_3_store, output io_trigger_pkt_any_3_load, output io_trigger_pkt_any_3_execute, @@ -9241,11 +9251,11 @@ module el2_dec_tlu_ctl( output [31:0] io_dec_csr_rddata_d, output io_dec_csr_legal_d, output io_dec_tlu_br0_r_pkt_valid, - output [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - output io_dec_tlu_br0_r_pkt_bits_br_error, - output io_dec_tlu_br0_r_pkt_bits_br_start_error, - output io_dec_tlu_br0_r_pkt_bits_way, - output io_dec_tlu_br0_r_pkt_bits_middle, + output [1:0] io_dec_tlu_br0_r_pkt_hist, + output io_dec_tlu_br0_r_pkt_br_error, + output io_dec_tlu_br0_r_pkt_br_start_error, + output io_dec_tlu_br0_r_pkt_way, + output io_dec_tlu_br0_r_pkt_middle, output io_dec_tlu_i0_kill_writeb_wb, output io_dec_tlu_flush_lower_wb, output io_dec_tlu_i0_commit_cmt, @@ -9413,28 +9423,28 @@ module el2_dec_tlu_ctl( wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 897:17] @@ -9513,7 +9523,7 @@ module el2_dec_tlu_ctl( wire csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 897:17] wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_mexintpend; // @[el2_dec_tlu_ctl.scala 897:17] wire [30:0] csr_io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 897:17] @@ -9749,7 +9759,7 @@ module el2_dec_tlu_ctl( wire i_cpu_run_req_sync = syncro_ff[2]; // @[el2_dec_tlu_ctl.scala 386:59] wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[el2_dec_tlu_ctl.scala 387:51] wire mpc_debug_run_req_sync = syncro_ff[0]; // @[el2_dec_tlu_ctl.scala 388:51] - wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 345:41 el2_dec_tlu_ctl.scala 1083:31] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 1083:31] reg lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 693:74] wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 392:61] reg e5_valid; // @[el2_dec_tlu_ctl.scala 404:89] @@ -9774,11 +9784,11 @@ module el2_dec_tlu_ctl( wire _T_44 = take_ext_int_start_d3 & _T_43; // @[el2_dec_tlu_ctl.scala 429:140] wire nmi_int_detected = _T_42 | _T_44; // @[el2_dec_tlu_ctl.scala 429:116] wire _T_631 = ~io_dec_csr_stall_int_ff; // @[el2_dec_tlu_ctl.scala 803:22] - wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 344:41 el2_dec_tlu_ctl.scala 1082:31] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 1082:31] wire _T_632 = _T_631 & mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 803:47] - wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 350:41 el2_dec_tlu_ctl.scala 1088:31] + wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 1088:31] wire _T_634 = _T_632 & mip[1]; // @[el2_dec_tlu_ctl.scala 803:64] - wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 339:41 el2_dec_tlu_ctl.scala 1077:31] + wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 1077:31] wire timer_int_ready = _T_634 & mie_ns[1]; // @[el2_dec_tlu_ctl.scala 803:82] wire _T_391 = nmi_int_detected | timer_int_ready; // @[el2_dec_tlu_ctl.scala 680:65] wire _T_628 = _T_632 & mip[0]; // @[el2_dec_tlu_ctl.scala 802:64] @@ -9834,7 +9844,7 @@ module el2_dec_tlu_ctl( reg ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 752:58] wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 503:126] reg debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 535:81] - wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 342:57 el2_dec_tlu_ctl.scala 1080:31] + wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 1080:31] reg lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 531:89] wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 497:47] wire _T_143 = _T_142 & io_ifu_miss_state_idle; // @[el2_dec_tlu_ctl.scala 497:64] @@ -9875,7 +9885,7 @@ module el2_dec_tlu_ctl( wire _T_167 = ~dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 514:67] wire _T_168 = debug_halt_req_f & _T_167; // @[el2_dec_tlu_ctl.scala 514:65] wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[el2_dec_tlu_ctl.scala 514:45] - wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 348:41 el2_dec_tlu_ctl.scala 1086:31] + wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 1086:31] wire _T_157 = ~dcsr[2]; // @[el2_dec_tlu_ctl.scala 506:100] wire _T_158 = debug_resume_req_f & _T_157; // @[el2_dec_tlu_ctl.scala 506:98] wire _T_159 = ~_T_158; // @[el2_dec_tlu_ctl.scala 506:77] @@ -9893,7 +9903,7 @@ module el2_dec_tlu_ctl( wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 649:54] wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[el2_dec_tlu_ctl.scala 649:79] wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[el2_dec_tlu_ctl.scala 665:49] - wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 346:41 el2_dec_tlu_ctl.scala 1084:31] + wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 1084:31] wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[el2_dec_tlu_ctl.scala 666:47] reg pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 658:73] wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 671:44] @@ -9952,7 +9962,7 @@ module el2_dec_tlu_ctl( wire [3:0] _T_290 = _T_287 & _T_289; // @[el2_dec_tlu_ctl.scala 593:65] wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[el2_dec_tlu_ctl.scala 593:34] wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:118] - wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 347:41 el2_dec_tlu_ctl.scala 1085:31] + wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 1085:31] wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:62] wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 587:86] wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:150] @@ -10344,7 +10354,7 @@ module el2_dec_tlu_ctl( wire _T_682 = _T_681 | take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 830:66] wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 832:45] - wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 349:41 el2_dec_tlu_ctl.scala 1087:31] + wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 1087:31] wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] wire [30:0] vectored_path = _T_769 + _T_771; // @[el2_dec_tlu_ctl.scala 860:50] @@ -10375,16 +10385,16 @@ module el2_dec_tlu_ctl( wire _T_833 = _T_529 & debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 875:16] wire _T_836 = _T_529 & sel_npc_resume; // @[el2_dec_tlu_ctl.scala 876:16] wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 337:41 el2_dec_tlu_ctl.scala 1075:31] + wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 1075:31] wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] - wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 340:41 el2_dec_tlu_ctl.scala 1078:31] + wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 1078:31] wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 343:41 el2_dec_tlu_ctl.scala 1081:31] + wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 1081:31] wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 338:41 el2_dec_tlu_ctl.scala 1076:31] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 1076:31] wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] @@ -10503,28 +10513,28 @@ module el2_dec_tlu_ctl( .io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid), .io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid), .io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(csr_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(csr_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute), .io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m), .io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(csr_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(csr_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute), .io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m), .io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(csr_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(csr_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute), .io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m), .io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(csr_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(csr_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute), @@ -10843,28 +10853,28 @@ module el2_dec_tlu_ctl( assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 557:27] assign io_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 956:44] assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_0_match_ = csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_1_match_ = csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_2_match_ = csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_3_match_ = csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 962:40] @@ -10886,11 +10896,11 @@ module el2_dec_tlu_ctl( assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40] assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22] assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49] - assign io_dec_tlu_br0_r_pkt_bits_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:57] - assign io_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49] - assign io_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:49] - assign io_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:57] - assign io_dec_tlu_br0_r_pkt_bits_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:57] + assign io_dec_tlu_br0_r_pkt_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:49] + assign io_dec_tlu_br0_r_pkt_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49] + assign io_dec_tlu_br0_r_pkt_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:41] + assign io_dec_tlu_br0_r_pkt_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:49] + assign io_dec_tlu_br0_r_pkt_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:49] assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33] assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33] assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28] @@ -11044,7 +11054,7 @@ module el2_dec_tlu_ctl( assign csr_io_inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 1021:39] assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[el2_dec_tlu_ctl.scala 1022:39] assign csr_io_take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 1023:39] - assign csr_io_lsu_error_pkt_addr_r = {{31'd0}, io_lsu_error_pkt_r_bits_addr}; // @[el2_dec_tlu_ctl.scala 1024:39] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[el2_dec_tlu_ctl.scala 1024:39] assign csr_io_exc_cause_r = _T_603 | _T_591; // @[el2_dec_tlu_ctl.scala 1025:39] assign csr_io_i0_valid_wb = i0_valid_wb; // @[el2_dec_tlu_ctl.scala 1026:39] assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1027:39] @@ -12096,22 +12106,22 @@ end // initial endmodule module el2_dec_trigger( input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_execute, input io_trigger_pkt_any_0_m, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_execute, input io_trigger_pkt_any_1_m, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_execute, input io_trigger_pkt_any_2_m, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_execute, input io_trigger_pkt_any_3_m, input [31:0] io_trigger_pkt_any_3_tdata2, @@ -12153,7 +12163,7 @@ module el2_dec_trigger( wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83] wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] wire _T_152 = ~_T_151; // @[el2_lib.scala 241:39] - wire _T_153 = io_trigger_pkt_any_0_match_ & _T_152; // @[el2_lib.scala 241:37] + wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[el2_lib.scala 241:37] wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 242:52] wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 242:41] wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] @@ -12289,7 +12299,7 @@ module el2_dec_trigger( wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83] wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] wire _T_411 = ~_T_410; // @[el2_lib.scala 241:39] - wire _T_412 = io_trigger_pkt_any_1_match_ & _T_411; // @[el2_lib.scala 241:37] + wire _T_412 = io_trigger_pkt_any_1_match_pkt & _T_411; // @[el2_lib.scala 241:37] wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 242:52] wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 242:41] wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] @@ -12425,7 +12435,7 @@ module el2_dec_trigger( wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83] wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] wire _T_670 = ~_T_669; // @[el2_lib.scala 241:39] - wire _T_671 = io_trigger_pkt_any_2_match_ & _T_670; // @[el2_lib.scala 241:37] + wire _T_671 = io_trigger_pkt_any_2_match_pkt & _T_670; // @[el2_lib.scala 241:37] wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 242:52] wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 242:41] wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] @@ -12561,7 +12571,7 @@ module el2_dec_trigger( wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83] wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] wire _T_929 = ~_T_928; // @[el2_lib.scala 241:39] - wire _T_930 = io_trigger_pkt_any_3_match_ & _T_929; // @[el2_lib.scala 241:37] + wire _T_930 = io_trigger_pkt_any_3_match_pkt & _T_929; // @[el2_lib.scala 241:37] wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 242:52] wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 242:41] wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] @@ -12767,14 +12777,14 @@ module el2_dec( input io_ifu_i0_dbecc, input io_lsu_idle_any, input io_i0_brp_valid, - input [11:0] io_i0_brp_bits_toffset, - input [1:0] io_i0_brp_bits_hist, - input io_i0_brp_bits_br_error, - input io_i0_brp_bits_br_start_error, - input io_i0_brp_bits_bank, - input [30:0] io_i0_brp_bits_prett, - input io_i0_brp_bits_way, - input io_i0_brp_bits_ret, + input [11:0] io_i0_brp_toffset, + input [1:0] io_i0_brp_hist, + input io_i0_brp_br_error, + input io_i0_brp_br_start_error, + input io_i0_brp_bank, + input [30:0] io_i0_brp_prett, + input io_i0_brp_way, + input io_i0_brp_ret, input [7:0] io_ifu_i0_bp_index, input [7:0] io_ifu_i0_bp_fghr, input [4:0] io_ifu_i0_bp_btag, @@ -12782,8 +12792,8 @@ module el2_dec( input io_lsu_error_pkt_r_bits_single_ecc_error, input io_lsu_error_pkt_r_bits_inst_type, input io_lsu_error_pkt_r_bits_exc_type, - input io_lsu_error_pkt_r_bits_mscause, - input io_lsu_error_pkt_r_bits_addr, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, input io_lsu_single_ecc_error_incr, input io_lsu_imprecise_error_load_any, input io_lsu_imprecise_error_store_any, @@ -12836,28 +12846,28 @@ module el2_dec( output io_dec_dbg_cmd_done, output io_dec_dbg_cmd_fail, output io_trigger_pkt_any_0_select, - output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_match_pkt, output io_trigger_pkt_any_0_store, output io_trigger_pkt_any_0_load, output io_trigger_pkt_any_0_execute, output io_trigger_pkt_any_0_m, output [31:0] io_trigger_pkt_any_0_tdata2, output io_trigger_pkt_any_1_select, - output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_match_pkt, output io_trigger_pkt_any_1_store, output io_trigger_pkt_any_1_load, output io_trigger_pkt_any_1_execute, output io_trigger_pkt_any_1_m, output [31:0] io_trigger_pkt_any_1_tdata2, output io_trigger_pkt_any_2_select, - output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_match_pkt, output io_trigger_pkt_any_2_store, output io_trigger_pkt_any_2_load, output io_trigger_pkt_any_2_execute, output io_trigger_pkt_any_2_m, output [31:0] io_trigger_pkt_any_2_tdata2, output io_trigger_pkt_any_3_select, - output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_match_pkt, output io_trigger_pkt_any_3_store, output io_trigger_pkt_any_3_load, output io_trigger_pkt_any_3_execute, @@ -12947,11 +12957,11 @@ module el2_dec( output io_dec_tlu_fence_i_r, output [30:0] io_pred_correct_npc_x, output io_dec_tlu_br0_r_pkt_valid, - output [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - output io_dec_tlu_br0_r_pkt_bits_br_error, - output io_dec_tlu_br0_r_pkt_bits_br_start_error, - output io_dec_tlu_br0_r_pkt_bits_way, - output io_dec_tlu_br0_r_pkt_bits_middle, + output [1:0] io_dec_tlu_br0_r_pkt_hist, + output io_dec_tlu_br0_r_pkt_br_error, + output io_dec_tlu_br0_r_pkt_br_start_error, + output io_dec_tlu_br0_r_pkt_way, + output io_dec_tlu_br0_r_pkt_middle, output io_dec_tlu_perfcnt0, output io_dec_tlu_perfcnt1, output io_dec_tlu_perfcnt2, @@ -13006,13 +13016,13 @@ module el2_dec( wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 285:24] wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 285:24] wire instbuff_io_i0_brp_valid; // @[el2_dec.scala 285:24] - wire [11:0] instbuff_io_i0_brp_bits_toffset; // @[el2_dec.scala 285:24] - wire [1:0] instbuff_io_i0_brp_bits_hist; // @[el2_dec.scala 285:24] - wire instbuff_io_i0_brp_bits_br_error; // @[el2_dec.scala 285:24] - wire instbuff_io_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24] - wire [30:0] instbuff_io_i0_brp_bits_prett; // @[el2_dec.scala 285:24] - wire instbuff_io_i0_brp_bits_way; // @[el2_dec.scala 285:24] - wire instbuff_io_i0_brp_bits_ret; // @[el2_dec.scala 285:24] + wire [11:0] instbuff_io_i0_brp_toffset; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_i0_brp_hist; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_br_error; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_br_start_error; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_i0_brp_prett; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_way; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_ret; // @[el2_dec.scala 285:24] wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 285:24] wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 285:24] wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 285:24] @@ -13030,13 +13040,13 @@ module el2_dec( wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 285:24] wire instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 285:24] wire instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 285:24] - wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 285:24] - wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 285:24] - wire instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 285:24] - wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24] - wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 285:24] - wire instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 285:24] - wire instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 285:24] + wire [11:0] instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 285:24] wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 285:24] wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 285:24] wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 285:24] @@ -13075,13 +13085,13 @@ module el2_dec( wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 286:22] wire decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 286:22] wire decode_io_dec_i0_brp_valid; // @[el2_dec.scala 286:22] - wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 286:22] - wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 286:22] - wire decode_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 286:22] - wire decode_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 286:22] - wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 286:22] - wire decode_io_dec_i0_brp_bits_way; // @[el2_dec.scala 286:22] - wire decode_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_i0_brp_toffset; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_brp_hist; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_br_error; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_i0_brp_prett; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_way; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_ret; // @[el2_dec.scala 286:22] wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 286:22] wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 286:22] wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 286:22] @@ -13276,8 +13286,8 @@ module el2_dec( wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 288:19] wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 288:19] wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 288:19] - wire tlu_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 288:19] - wire tlu_io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 288:19] wire tlu_io_lsu_single_ecc_error_incr; // @[el2_dec.scala 288:19] wire tlu_io_dec_pause_state; // @[el2_dec.scala 288:19] wire tlu_io_lsu_imprecise_error_store_any; // @[el2_dec.scala 288:19] @@ -13330,28 +13340,28 @@ module el2_dec( wire tlu_io_lsu_idle_any; // @[el2_dec.scala 288:19] wire tlu_io_dec_div_active; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 288:19] - wire tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 288:19] wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 288:19] - wire tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 288:19] wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 288:19] - wire tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 288:19] wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 288:19] - wire tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 288:19] @@ -13387,11 +13397,11 @@ module el2_dec( wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 288:19] wire tlu_io_dec_csr_legal_d; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 288:19] - wire [1:0] tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 288:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 288:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 288:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 288:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 288:19] @@ -13430,22 +13440,22 @@ module el2_dec( wire tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 288:19] wire dec_trigger_io_trigger_pkt_any_0_select; // @[el2_dec.scala 289:27] - wire dec_trigger_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_0_m; // @[el2_dec.scala 289:27] wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_1_select; // @[el2_dec.scala 289:27] - wire dec_trigger_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_1_m; // @[el2_dec.scala 289:27] wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_2_select; // @[el2_dec.scala 289:27] - wire dec_trigger_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_2_m; // @[el2_dec.scala 289:27] wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_3_select; // @[el2_dec.scala 289:27] - wire dec_trigger_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_3_m; // @[el2_dec.scala 289:27] wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 289:27] @@ -13458,13 +13468,13 @@ module el2_dec( .io_dbg_cmd_type(instbuff_io_dbg_cmd_type), .io_dbg_cmd_addr(instbuff_io_dbg_cmd_addr), .io_i0_brp_valid(instbuff_io_i0_brp_valid), - .io_i0_brp_bits_toffset(instbuff_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(instbuff_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(instbuff_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(instbuff_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_prett(instbuff_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(instbuff_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(instbuff_io_i0_brp_bits_ret), + .io_i0_brp_toffset(instbuff_io_i0_brp_toffset), + .io_i0_brp_hist(instbuff_io_i0_brp_hist), + .io_i0_brp_br_error(instbuff_io_i0_brp_br_error), + .io_i0_brp_br_start_error(instbuff_io_i0_brp_br_start_error), + .io_i0_brp_prett(instbuff_io_i0_brp_prett), + .io_i0_brp_way(instbuff_io_i0_brp_way), + .io_i0_brp_ret(instbuff_io_i0_brp_ret), .io_ifu_i0_bp_index(instbuff_io_ifu_i0_bp_index), .io_ifu_i0_bp_fghr(instbuff_io_ifu_i0_bp_fghr), .io_ifu_i0_bp_btag(instbuff_io_ifu_i0_bp_btag), @@ -13482,13 +13492,13 @@ module el2_dec( .io_dec_i0_pc_d(instbuff_io_dec_i0_pc_d), .io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d), .io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid), - .io_dec_i0_brp_bits_toffset(instbuff_io_dec_i0_brp_bits_toffset), - .io_dec_i0_brp_bits_hist(instbuff_io_dec_i0_brp_bits_hist), - .io_dec_i0_brp_bits_br_error(instbuff_io_dec_i0_brp_bits_br_error), - .io_dec_i0_brp_bits_br_start_error(instbuff_io_dec_i0_brp_bits_br_start_error), - .io_dec_i0_brp_bits_prett(instbuff_io_dec_i0_brp_bits_prett), - .io_dec_i0_brp_bits_way(instbuff_io_dec_i0_brp_bits_way), - .io_dec_i0_brp_bits_ret(instbuff_io_dec_i0_brp_bits_ret), + .io_dec_i0_brp_toffset(instbuff_io_dec_i0_brp_toffset), + .io_dec_i0_brp_hist(instbuff_io_dec_i0_brp_hist), + .io_dec_i0_brp_br_error(instbuff_io_dec_i0_brp_br_error), + .io_dec_i0_brp_br_start_error(instbuff_io_dec_i0_brp_br_start_error), + .io_dec_i0_brp_prett(instbuff_io_dec_i0_brp_prett), + .io_dec_i0_brp_way(instbuff_io_dec_i0_brp_way), + .io_dec_i0_brp_ret(instbuff_io_dec_i0_brp_ret), .io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index), .io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr), .io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag), @@ -13529,13 +13539,13 @@ module el2_dec( .io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d), .io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d), .io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid), - .io_dec_i0_brp_bits_toffset(decode_io_dec_i0_brp_bits_toffset), - .io_dec_i0_brp_bits_hist(decode_io_dec_i0_brp_bits_hist), - .io_dec_i0_brp_bits_br_error(decode_io_dec_i0_brp_bits_br_error), - .io_dec_i0_brp_bits_br_start_error(decode_io_dec_i0_brp_bits_br_start_error), - .io_dec_i0_brp_bits_prett(decode_io_dec_i0_brp_bits_prett), - .io_dec_i0_brp_bits_way(decode_io_dec_i0_brp_bits_way), - .io_dec_i0_brp_bits_ret(decode_io_dec_i0_brp_bits_ret), + .io_dec_i0_brp_toffset(decode_io_dec_i0_brp_toffset), + .io_dec_i0_brp_hist(decode_io_dec_i0_brp_hist), + .io_dec_i0_brp_br_error(decode_io_dec_i0_brp_br_error), + .io_dec_i0_brp_br_start_error(decode_io_dec_i0_brp_br_start_error), + .io_dec_i0_brp_prett(decode_io_dec_i0_brp_prett), + .io_dec_i0_brp_way(decode_io_dec_i0_brp_way), + .io_dec_i0_brp_ret(decode_io_dec_i0_brp_ret), .io_dec_i0_bp_index(decode_io_dec_i0_bp_index), .io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr), .io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag), @@ -13788,28 +13798,28 @@ module el2_dec( .io_lsu_idle_any(tlu_io_lsu_idle_any), .io_dec_div_active(tlu_io_dec_div_active), .io_trigger_pkt_any_0_select(tlu_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(tlu_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(tlu_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(tlu_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(tlu_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_execute(tlu_io_trigger_pkt_any_0_execute), .io_trigger_pkt_any_0_m(tlu_io_trigger_pkt_any_0_m), .io_trigger_pkt_any_0_tdata2(tlu_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(tlu_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(tlu_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(tlu_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(tlu_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(tlu_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_execute(tlu_io_trigger_pkt_any_1_execute), .io_trigger_pkt_any_1_m(tlu_io_trigger_pkt_any_1_m), .io_trigger_pkt_any_1_tdata2(tlu_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(tlu_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(tlu_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(tlu_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(tlu_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(tlu_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_execute(tlu_io_trigger_pkt_any_2_execute), .io_trigger_pkt_any_2_m(tlu_io_trigger_pkt_any_2_m), .io_trigger_pkt_any_2_tdata2(tlu_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(tlu_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(tlu_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(tlu_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(tlu_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(tlu_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_execute(tlu_io_trigger_pkt_any_3_execute), @@ -13845,11 +13855,11 @@ module el2_dec( .io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d), .io_dec_csr_legal_d(tlu_io_dec_csr_legal_d), .io_dec_tlu_br0_r_pkt_valid(tlu_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(tlu_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(tlu_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(tlu_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(tlu_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(tlu_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(tlu_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(tlu_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(tlu_io_dec_tlu_br0_r_pkt_middle), .io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb), .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb), .io_dec_tlu_i0_commit_cmt(tlu_io_dec_tlu_i0_commit_cmt), @@ -13890,22 +13900,22 @@ module el2_dec( ); el2_dec_trigger dec_trigger ( // @[el2_dec.scala 289:27] .io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(dec_trigger_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(dec_trigger_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute), .io_trigger_pkt_any_0_m(dec_trigger_io_trigger_pkt_any_0_m), .io_trigger_pkt_any_0_tdata2(dec_trigger_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(dec_trigger_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(dec_trigger_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(dec_trigger_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_execute(dec_trigger_io_trigger_pkt_any_1_execute), .io_trigger_pkt_any_1_m(dec_trigger_io_trigger_pkt_any_1_m), .io_trigger_pkt_any_1_tdata2(dec_trigger_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(dec_trigger_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(dec_trigger_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(dec_trigger_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_execute(dec_trigger_io_trigger_pkt_any_2_execute), .io_trigger_pkt_any_2_m(dec_trigger_io_trigger_pkt_any_2_m), .io_trigger_pkt_any_2_tdata2(dec_trigger_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(dec_trigger_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(dec_trigger_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(dec_trigger_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_execute(dec_trigger_io_trigger_pkt_any_3_execute), .io_trigger_pkt_any_3_m(dec_trigger_io_trigger_pkt_any_3_m), .io_trigger_pkt_any_3_tdata2(dec_trigger_io_trigger_pkt_any_3_tdata2), @@ -13941,28 +13951,28 @@ module el2_dec( assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 536:28] assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 537:28] assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 546:29] - assign io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 546:29] - assign io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 546:29] - assign io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 546:29] - assign io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 546:29] @@ -14045,11 +14055,11 @@ module el2_dec( assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 562:34] assign io_pred_correct_npc_x = decode_io_pred_correct_npc_x; // @[el2_dec.scala 411:40] assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_hist = tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_way = tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_middle = tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_hist = tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_br_error = tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_br_start_error = tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_way = tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_middle = tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 557:42] assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 565:29] assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 566:29] assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 567:29] @@ -14101,13 +14111,13 @@ module el2_dec( assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 299:45] assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 300:45] assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_hist = io_i0_brp_hist; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_prett = io_i0_brp_prett; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_way = io_i0_brp_way; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_ret = io_i0_brp_ret; // @[el2_dec.scala 301:55] assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec.scala 302:35] assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 303:35] assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 304:35] @@ -14146,13 +14156,13 @@ module el2_dec( assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 352:48] assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:48] assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_toffset = instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_hist = instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_br_error = instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_br_start_error = instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_prett = instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_way = instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_ret = instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 354:48] assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 355:48] assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 356:48] assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 357:48] @@ -14298,22 +14308,22 @@ module el2_dec( assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_dec.scala 533:45] assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec.scala 534:45] assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 321:34] - assign dec_trigger_io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 321:34] - assign dec_trigger_io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 321:34] - assign dec_trigger_io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 321:34] - assign dec_trigger_io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 321:34] diff --git a/el2_exu_alu_ctl.anno.json b/el2_exu_alu_ctl.anno.json index e88ea961..e9308935 100644 --- a/el2_exu_alu_ctl.anno.json +++ b/el2_exu_alu_ctl.anno.json @@ -1,16 +1,42 @@ [ { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_way", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_hist", "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_way" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_hist", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_prett", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pred_correct_out", "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub" ] }, { @@ -22,21 +48,38 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_br_start_error", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_final_out", "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_br_start_error" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_ataken", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_ataken", "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", @@ -47,30 +90,9 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pret", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_toffset", "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pc4", - "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pc4" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_toffset", - "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_toffset" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_br_error", - "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_br_error" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_toffset" ] }, { @@ -81,72 +103,15 @@ "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_boffset", - "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_boffset" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_hist", - "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_hist", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pcall", - "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_final_out", - "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", @@ -158,10 +123,10 @@ "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_path_out", "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pc_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_brimm_in", @@ -171,19 +136,40 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_misp", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pret", + "sources":[ + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pja", + "sources":[ + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pc4", + "sources":[ + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pc4" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_misp", "sources":[ "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pret", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pja", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", @@ -194,30 +180,44 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pred_correct_out", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_way", "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_way" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pja", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_pcall", "sources":[ - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_pcall" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_br_start_error", + "sources":[ + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_br_start_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_br_error", + "sources":[ + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_br_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_prett", + "sources":[ + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_prett" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_bits_boffset", + "sources":[ + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_bits_boffset" ] }, { diff --git a/el2_exu_alu_ctl.fir b/el2_exu_alu_ctl.fir index a8adeb2d..f28ff366 100644 --- a/el2_exu_alu_ctl.fir +++ b/el2_exu_alu_ctl.fir @@ -51,7 +51,7 @@ circuit el2_exu_alu_ctl : module el2_exu_alu_ctl : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} + output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}} node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60] inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] @@ -102,9 +102,9 @@ circuit el2_exu_alu_ctl : aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8] node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18] node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22] - node _T_26 = not(_T_25) @[el2_exu_alu_ctl.scala 45:14] + node _T_26 = eq(_T_25, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:14] node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32] - node _T_28 = not(_T_27) @[el2_exu_alu_ctl.scala 45:29] + node _T_28 = eq(_T_27, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:29] node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27] node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44] node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37] @@ -112,20 +112,20 @@ circuit el2_exu_alu_ctl : node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71] node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66] node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83] - node _T_36 = not(_T_35) @[el2_exu_alu_ctl.scala 45:78] + node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:78] node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76] node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50] node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50] node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38] node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29] node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34] - node _T_39 = not(io.ap.unsign) @[el2_exu_alu_ctl.scala 50:30] + node _T_39 = eq(io.ap.unsign, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:30] node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51] node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44] - node _T_42 = not(cout) @[el2_exu_alu_ctl.scala 50:78] + node _T_42 = eq(cout, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:78] node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76] node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58] - node ge = not(lt) @[el2_exu_alu_ctl.scala 51:29] + node ge = eq(lt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 51:29] node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19] node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50] node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16] @@ -190,12 +190,12 @@ circuit el2_exu_alu_ctl : shift_amount <= _T_97 @[Mux.scala 27:72] wire shift_mask : UInt<32> shift_mask <= UInt<1>("h00") - wire _T_98 : UInt<1>[5] @[el2_lib.scala 161:48] - _T_98[0] <= io.ap.sll @[el2_lib.scala 161:48] - _T_98[1] <= io.ap.sll @[el2_lib.scala 161:48] - _T_98[2] <= io.ap.sll @[el2_lib.scala 161:48] - _T_98[3] <= io.ap.sll @[el2_lib.scala 161:48] - _T_98[4] <= io.ap.sll @[el2_lib.scala 161:48] + wire _T_98 : UInt<1>[5] @[el2_lib.scala 162:48] + _T_98[0] <= io.ap.sll @[el2_lib.scala 162:48] + _T_98[1] <= io.ap.sll @[el2_lib.scala 162:48] + _T_98[2] <= io.ap.sll @[el2_lib.scala 162:48] + _T_98[3] <= io.ap.sll @[el2_lib.scala 162:48] + _T_98[4] <= io.ap.sll @[el2_lib.scala 162:48] node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58] node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58] node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58] @@ -206,38 +206,38 @@ circuit el2_exu_alu_ctl : shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14] wire shift_extend : UInt<63> shift_extend <= UInt<1>("h00") - wire _T_106 : UInt<1>[31] @[el2_lib.scala 161:48] - _T_106[0] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[1] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[2] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[3] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[4] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[5] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[6] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[7] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[8] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[9] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[10] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[11] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[12] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[13] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[14] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[15] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[16] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[17] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[18] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[19] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[20] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[21] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[22] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[23] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[24] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[25] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[26] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[27] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[28] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[29] <= io.ap.sra @[el2_lib.scala 161:48] - _T_106[30] <= io.ap.sra @[el2_lib.scala 161:48] + wire _T_106 : UInt<1>[31] @[el2_lib.scala 162:48] + _T_106[0] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[1] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[2] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[3] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[4] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[5] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[6] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[7] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[8] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[9] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[10] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[11] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[12] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[13] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[14] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[15] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[16] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[17] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[18] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[19] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[20] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[21] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[22] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[23] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[24] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[25] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[26] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[27] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[28] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[29] <= io.ap.sra @[el2_lib.scala 162:48] + _T_106[30] <= io.ap.sra @[el2_lib.scala 162:48] node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58] node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58] node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58] @@ -269,38 +269,38 @@ circuit el2_exu_alu_ctl : node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58] node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58] node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61] - wire _T_138 : UInt<1>[31] @[el2_lib.scala 161:48] - _T_138[0] <= _T_137 @[el2_lib.scala 161:48] - _T_138[1] <= _T_137 @[el2_lib.scala 161:48] - _T_138[2] <= _T_137 @[el2_lib.scala 161:48] - _T_138[3] <= _T_137 @[el2_lib.scala 161:48] - _T_138[4] <= _T_137 @[el2_lib.scala 161:48] - _T_138[5] <= _T_137 @[el2_lib.scala 161:48] - _T_138[6] <= _T_137 @[el2_lib.scala 161:48] - _T_138[7] <= _T_137 @[el2_lib.scala 161:48] - _T_138[8] <= _T_137 @[el2_lib.scala 161:48] - _T_138[9] <= _T_137 @[el2_lib.scala 161:48] - _T_138[10] <= _T_137 @[el2_lib.scala 161:48] - _T_138[11] <= _T_137 @[el2_lib.scala 161:48] - _T_138[12] <= _T_137 @[el2_lib.scala 161:48] - _T_138[13] <= _T_137 @[el2_lib.scala 161:48] - _T_138[14] <= _T_137 @[el2_lib.scala 161:48] - _T_138[15] <= _T_137 @[el2_lib.scala 161:48] - _T_138[16] <= _T_137 @[el2_lib.scala 161:48] - _T_138[17] <= _T_137 @[el2_lib.scala 161:48] - _T_138[18] <= _T_137 @[el2_lib.scala 161:48] - _T_138[19] <= _T_137 @[el2_lib.scala 161:48] - _T_138[20] <= _T_137 @[el2_lib.scala 161:48] - _T_138[21] <= _T_137 @[el2_lib.scala 161:48] - _T_138[22] <= _T_137 @[el2_lib.scala 161:48] - _T_138[23] <= _T_137 @[el2_lib.scala 161:48] - _T_138[24] <= _T_137 @[el2_lib.scala 161:48] - _T_138[25] <= _T_137 @[el2_lib.scala 161:48] - _T_138[26] <= _T_137 @[el2_lib.scala 161:48] - _T_138[27] <= _T_137 @[el2_lib.scala 161:48] - _T_138[28] <= _T_137 @[el2_lib.scala 161:48] - _T_138[29] <= _T_137 @[el2_lib.scala 161:48] - _T_138[30] <= _T_137 @[el2_lib.scala 161:48] + wire _T_138 : UInt<1>[31] @[el2_lib.scala 162:48] + _T_138[0] <= _T_137 @[el2_lib.scala 162:48] + _T_138[1] <= _T_137 @[el2_lib.scala 162:48] + _T_138[2] <= _T_137 @[el2_lib.scala 162:48] + _T_138[3] <= _T_137 @[el2_lib.scala 162:48] + _T_138[4] <= _T_137 @[el2_lib.scala 162:48] + _T_138[5] <= _T_137 @[el2_lib.scala 162:48] + _T_138[6] <= _T_137 @[el2_lib.scala 162:48] + _T_138[7] <= _T_137 @[el2_lib.scala 162:48] + _T_138[8] <= _T_137 @[el2_lib.scala 162:48] + _T_138[9] <= _T_137 @[el2_lib.scala 162:48] + _T_138[10] <= _T_137 @[el2_lib.scala 162:48] + _T_138[11] <= _T_137 @[el2_lib.scala 162:48] + _T_138[12] <= _T_137 @[el2_lib.scala 162:48] + _T_138[13] <= _T_137 @[el2_lib.scala 162:48] + _T_138[14] <= _T_137 @[el2_lib.scala 162:48] + _T_138[15] <= _T_137 @[el2_lib.scala 162:48] + _T_138[16] <= _T_137 @[el2_lib.scala 162:48] + _T_138[17] <= _T_137 @[el2_lib.scala 162:48] + _T_138[18] <= _T_137 @[el2_lib.scala 162:48] + _T_138[19] <= _T_137 @[el2_lib.scala 162:48] + _T_138[20] <= _T_137 @[el2_lib.scala 162:48] + _T_138[21] <= _T_137 @[el2_lib.scala 162:48] + _T_138[22] <= _T_137 @[el2_lib.scala 162:48] + _T_138[23] <= _T_137 @[el2_lib.scala 162:48] + _T_138[24] <= _T_137 @[el2_lib.scala 162:48] + _T_138[25] <= _T_137 @[el2_lib.scala 162:48] + _T_138[26] <= _T_137 @[el2_lib.scala 162:48] + _T_138[27] <= _T_137 @[el2_lib.scala 162:48] + _T_138[28] <= _T_137 @[el2_lib.scala 162:48] + _T_138[29] <= _T_137 @[el2_lib.scala 162:48] + _T_138[30] <= _T_137 @[el2_lib.scala 162:48] node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58] node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58] node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58] @@ -332,38 +332,38 @@ circuit el2_exu_alu_ctl : node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58] node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58] node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44] - wire _T_170 : UInt<1>[31] @[el2_lib.scala 161:48] - _T_170[0] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[1] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[2] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[3] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[4] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[5] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[6] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[7] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[8] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[9] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[10] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[11] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[12] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[13] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[14] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[15] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[16] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[17] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[18] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[19] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[20] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[21] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[22] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[23] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[24] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[25] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[26] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[27] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[28] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[29] <= io.ap.sll @[el2_lib.scala 161:48] - _T_170[30] <= io.ap.sll @[el2_lib.scala 161:48] + wire _T_170 : UInt<1>[31] @[el2_lib.scala 162:48] + _T_170[0] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[1] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[2] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[3] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[4] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[5] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[6] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[7] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[8] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[9] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[10] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[11] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[12] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[13] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[14] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[15] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[16] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[17] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[18] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[19] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[20] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[21] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[22] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[23] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[24] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[25] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[26] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[27] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[28] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[29] <= io.ap.sll @[el2_lib.scala 162:48] + _T_170[30] <= io.ap.sll @[el2_lib.scala 162:48] node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58] node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58] node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58] @@ -411,11 +411,11 @@ circuit el2_exu_alu_ctl : node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41] node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53] node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41] - node _T_212 = not(io.ap.slt) @[el2_exu_alu_ctl.scala 78:56] + node _T_212 = eq(io.ap.slt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 78:56] node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54] - node _T_213 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 79:41] - node _T_214 = or(_T_213, io.pp_in.pja) @[el2_exu_alu_ctl.scala 79:58] - node sel_pc = or(_T_214, io.pp_in.pret) @[el2_exu_alu_ctl.scala 79:73] + node _T_213 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 79:41] + node _T_214 = or(_T_213, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 79:63] + node sel_pc = or(_T_214, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 79:83] node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47] node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63] node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32] @@ -437,14 +437,14 @@ circuit el2_exu_alu_ctl : node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26] node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64] node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76] - node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:8] - node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:27] - node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:14] - node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:52] - node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:27] - node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:16] - node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:14] - node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:52] + node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:20] + node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:39] + node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:26] + node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:64] + node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:39] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:28] + node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:26] + node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:64] node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] @@ -452,7 +452,7 @@ circuit el2_exu_alu_ctl : node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72] wire _T_247 : UInt<19> @[Mux.scala 27:72] _T_247 <= _T_246 @[Mux.scala 27:72] - node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:82] + node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:94] node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58] node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24] @@ -476,9 +476,9 @@ circuit el2_exu_alu_ctl : _T_267 <= _T_266 @[Mux.scala 27:72] node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56] result <= _T_268 @[el2_exu_alu_ctl.scala 88:16] - node _T_269 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 96:45] - node _T_270 = or(_T_269, io.pp_in.pja) @[el2_exu_alu_ctl.scala 97:20] - node any_jal = or(_T_270, io.pp_in.pret) @[el2_exu_alu_ctl.scala 98:20] + node _T_269 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 96:45] + node _T_270 = or(_T_269, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 97:25] + node any_jal = or(_T_270, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 98:25] node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40] node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59] node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46] @@ -507,9 +507,9 @@ circuit el2_exu_alu_ctl : node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45] node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82] node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62] - node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:70] - node _T_296 = neq(io.pp_in.prett, _T_295) @[el2_exu_alu_ctl.scala 114:62] - node target_mispredict = and(io.pp_in.pret, _T_296) @[el2_exu_alu_ctl.scala 114:44] + node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:80] + node _T_296 = neq(io.pp_in.bits.prett, _T_295) @[el2_exu_alu_ctl.scala 114:72] + node target_mispredict = and(io.pp_in.bits.pret, _T_296) @[el2_exu_alu_ctl.scala 114:49] node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42] node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60] node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81] @@ -527,42 +527,42 @@ circuit el2_exu_alu_ctl : io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26] wire newhist : UInt<2> newhist <= UInt<1>("h00") - node _T_310 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:35] - node _T_311 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:55] - node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:39] - node _T_313 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:77] - node _T_314 = not(_T_313) @[el2_exu_alu_ctl.scala 122:63] - node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:81] - node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:60] - node _T_317 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:20] - node _T_318 = not(_T_317) @[el2_exu_alu_ctl.scala 123:6] - node _T_319 = not(actual_taken) @[el2_exu_alu_ctl.scala 123:26] - node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:24] - node _T_321 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:58] - node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:62] - node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:42] + node _T_310 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:40] + node _T_311 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:65] + node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:44] + node _T_313 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:92] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 122:73] + node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:96] + node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:70] + node _T_317 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:25] + node _T_318 = eq(_T_317, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:6] + node _T_319 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:31] + node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:29] + node _T_321 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:68] + node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:72] + node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:47] node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58] newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14] - io.predict_p_out.way <= io.pp_in.way @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.pja <= io.pp_in.pja @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.pret <= io.pp_in.pret @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.pcall <= io.pp_in.pcall @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.prett <= io.pp_in.prett @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.br_start_error <= io.pp_in.br_start_error @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.br_error <= io.pp_in.br_error @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.way <= io.pp_in.bits.way @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.pja <= io.pp_in.bits.pja @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.pret <= io.pp_in.bits.pret @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.pcall <= io.pp_in.bits.pcall @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.prett <= io.pp_in.bits.prett @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.br_start_error <= io.pp_in.bits.br_start_error @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.br_error <= io.pp_in.bits.br_error @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.toffset <= io.pp_in.bits.toffset @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.hist <= io.pp_in.bits.hist @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.pc4 <= io.pp_in.bits.pc4 @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.boffset <= io.pp_in.bits.boffset @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.ataken <= io.pp_in.bits.ataken @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.bits.misp <= io.pp_in.bits.misp @[el2_exu_alu_ctl.scala 125:30] io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.toffset <= io.pp_in.toffset @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.hist <= io.pp_in.hist @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.pc4 <= io.pp_in.pc4 @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.boffset <= io.pp_in.boffset @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.ataken <= io.pp_in.ataken @[el2_exu_alu_ctl.scala 125:30] - io.predict_p_out.misp <= io.pp_in.misp @[el2_exu_alu_ctl.scala 125:30] - node _T_325 = not(io.flush_upper_x) @[el2_exu_alu_ctl.scala 126:33] - node _T_326 = not(io.flush_lower_r) @[el2_exu_alu_ctl.scala 126:53] - node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:51] - node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:90] - node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:71] - io.predict_p_out.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:30] - io.predict_p_out.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:30] - io.predict_p_out.hist <= newhist @[el2_exu_alu_ctl.scala 128:30] + node _T_325 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:38] + node _T_326 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:58] + node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:56] + node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:95] + node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:76] + io.predict_p_out.bits.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:35] + io.predict_p_out.bits.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:35] + io.predict_p_out.bits.hist <= newhist @[el2_exu_alu_ctl.scala 128:35] diff --git a/el2_exu_alu_ctl.v b/el2_exu_alu_ctl.v index 8b3962b7..c0bfb30b 100644 --- a/el2_exu_alu_ctl.v +++ b/el2_exu_alu_ctl.v @@ -50,20 +50,20 @@ module el2_exu_alu_ctl( input [31:0] io_a_in, input [31:0] io_b_in, input [30:0] io_pc_in, - input io_pp_in_misp, - input io_pp_in_ataken, - input io_pp_in_boffset, - input io_pp_in_pc4, - input [1:0] io_pp_in_hist, - input [11:0] io_pp_in_toffset, input io_pp_in_valid, - input io_pp_in_br_error, - input io_pp_in_br_start_error, - input [30:0] io_pp_in_prett, - input io_pp_in_pcall, - input io_pp_in_pret, - input io_pp_in_pja, - input io_pp_in_way, + input io_pp_in_bits_misp, + input io_pp_in_bits_ataken, + input io_pp_in_bits_boffset, + input io_pp_in_bits_pc4, + input [1:0] io_pp_in_bits_hist, + input [11:0] io_pp_in_bits_toffset, + input io_pp_in_bits_br_error, + input io_pp_in_bits_br_start_error, + input [30:0] io_pp_in_bits_prett, + input io_pp_in_bits_pcall, + input io_pp_in_bits_pret, + input io_pp_in_bits_pja, + input io_pp_in_bits_way, input [11:0] io_brimm_in, output [31:0] io_result_ff, output io_flush_upper_out, @@ -71,20 +71,20 @@ module el2_exu_alu_ctl( output [30:0] io_flush_path_out, output [30:0] io_pc_ff, output io_pred_correct_out, - output io_predict_p_out_misp, - output io_predict_p_out_ataken, - output io_predict_p_out_boffset, - output io_predict_p_out_pc4, - output [1:0] io_predict_p_out_hist, - output [11:0] io_predict_p_out_toffset, output io_predict_p_out_valid, - output io_predict_p_out_br_error, - output io_predict_p_out_br_start_error, - output [30:0] io_predict_p_out_prett, - output io_predict_p_out_pcall, - output io_predict_p_out_pret, - output io_predict_p_out_pja, - output io_predict_p_out_way + output io_predict_p_out_bits_misp, + output io_predict_p_out_bits_ataken, + output io_predict_p_out_bits_boffset, + output io_predict_p_out_bits_pc4, + output [1:0] io_predict_p_out_bits_hist, + output [11:0] io_predict_p_out_bits_toffset, + output io_predict_p_out_bits_br_error, + output io_predict_p_out_bits_br_start_error, + output [30:0] io_predict_p_out_bits_prett, + output io_predict_p_out_bits_pcall, + output io_predict_p_out_bits_pret, + output io_predict_p_out_bits_pja, + output io_predict_p_out_bits_way ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -172,9 +172,9 @@ module el2_exu_alu_ctl( wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41] wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56] wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54] - wire _T_213 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 79:41] - wire _T_214 = _T_213 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 79:58] - wire sel_pc = _T_214 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 79:73] + wire _T_213 = io_ap_jal | io_pp_in_bits_pcall; // @[el2_exu_alu_ctl.scala 79:41] + wire _T_214 = _T_213 | io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 79:63] + wire sel_pc = _T_214 | io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 79:83] wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40] wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58] @@ -183,9 +183,9 @@ module el2_exu_alu_ctl( wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27] wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28] wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26] - wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:8] - wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:14] - wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:14] + wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:20] + wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:26] + wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:26] wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72] @@ -222,24 +222,24 @@ module el2_exu_alu_ctl( wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45] wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82] wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62] - wire _T_296 = io_pp_in_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:62] - wire target_mispredict = io_pp_in_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:44] + wire _T_296 = io_pp_in_bits_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:72] + wire target_mispredict = io_pp_in_bits_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:49] wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42] wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60] wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81] wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97] wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95] wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119] - wire _T_312 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:39] - wire _T_314 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:63] - wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:81] - wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:60] - wire _T_318 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 123:6] - wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:24] - wire _T_322 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:62] - wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:42] - wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:51] - wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:90] + wire _T_312 = io_pp_in_bits_hist[1] & io_pp_in_bits_hist[0]; // @[el2_exu_alu_ctl.scala 122:44] + wire _T_314 = ~io_pp_in_bits_hist[0]; // @[el2_exu_alu_ctl.scala 122:73] + wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:96] + wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:70] + wire _T_318 = ~io_pp_in_bits_hist[1]; // @[el2_exu_alu_ctl.scala 123:6] + wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:29] + wire _T_322 = io_pp_in_bits_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:72] + wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:47] + wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:56] + wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:95] rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -258,20 +258,20 @@ module el2_exu_alu_ctl( assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22] assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12] assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26] - assign io_predict_p_out_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:30] - assign io_predict_p_out_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:30] - assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 125:30] - assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 125:30] - assign io_predict_p_out_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:30] - assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30] - assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 125:30] - assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 125:30] - assign io_predict_p_out_prett = io_pp_in_prett; // @[el2_exu_alu_ctl.scala 125:30] - assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 125:30] - assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 125:30] - assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 125:30] - assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:35] + assign io_predict_p_out_bits_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:35] + assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:35] + assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_br_error = io_pp_in_bits_br_error; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_br_start_error = io_pp_in_bits_br_start_error; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_prett = io_pp_in_bits_prett; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_pcall = io_pp_in_bits_pcall; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[el2_exu_alu_ctl.scala 125:30] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] diff --git a/el2_exu_mul_ctl.fir b/el2_exu_mul_ctl.fir index 8e721b2f..3d16ce02 100644 --- a/el2_exu_mul_ctl.fir +++ b/el2_exu_mul_ctl.fir @@ -99,7 +99,7 @@ circuit el2_exu_mul_ctl : node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58] node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:71] rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14] - node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 36:52] + node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 29:52] inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -108,8 +108,8 @@ circuit el2_exu_mul_ctl : rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_9 <= io.mul_p.bits.low @[el2_lib.scala 514:16] - low_x <= _T_9 @[el2_exu_mul_ctl.scala 36:9] - node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 37:44] + low_x <= _T_9 @[el2_exu_mul_ctl.scala 29:9] + node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 30:44] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 528:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -118,8 +118,8 @@ circuit el2_exu_mul_ctl : rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] _T_11 <= rs1_ext_in @[el2_lib.scala 534:16] - rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 37:9] - node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 38:45] + rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 30:9] + node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 31:45] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 528:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -128,18 +128,18 @@ circuit el2_exu_mul_ctl : rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] _T_13 <= rs2_ext_in @[el2_lib.scala 534:16] - rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 38:9] - node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 40:20] - prod_x <= _T_14 @[el2_exu_mul_ctl.scala 40:10] - node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:36] - node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 41:29] - node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 41:52] - node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:67] - node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 41:83] + rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 31:9] + node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 33:20] + prod_x <= _T_14 @[el2_exu_mul_ctl.scala 33:10] + node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 34:36] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 34:29] + node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 34:52] + node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 34:67] + node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 34:83] node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72] node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72] node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72] wire _T_23 : UInt<32> @[Mux.scala 27:72] _T_23 <= _T_22 @[Mux.scala 27:72] - io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 41:15] + io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 34:15] diff --git a/el2_exu_mul_ctl.v b/el2_exu_mul_ctl.v index 6976e228..f9175386 100644 --- a/el2_exu_mul_ctl.v +++ b/el2_exu_mul_ctl.v @@ -68,8 +68,8 @@ module el2_exu_mul_ctl( reg low_x; // @[el2_lib.scala 514:16] reg [32:0] rs1_x; // @[el2_lib.scala 534:16] reg [32:0] rs2_x; // @[el2_lib.scala 534:16] - wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 40:20] - wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 41:29] + wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 33:20] + wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 34:29] wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] @@ -90,7 +90,7 @@ module el2_exu_mul_ctl( .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 41:15] + assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 34:15] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 511:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] diff --git a/el2_ifu.anno.json b/el2_ifu.anno.json index c879cc05..9d6b4228 100644 --- a/el2_ifu.anno.json +++ b/el2_ifu.anno.json @@ -1,88 +1,28 @@ [ { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error", + "sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall", "sources":[ - "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", - "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", + "~el2_ifu|el2_ifu>io_ic_rd_data", + "~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_ic_rd_hit", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_ic_rd_en", + "sink":"~el2_ifu|el2_ifu>io_iccm_wren", "sources":[ - "~el2_ifu|el2_ifu>io_exu_flush_final", - "~el2_ifu|el2_ifu>io_dec_tlu_force_halt", - "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_exu_flush_path_final", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff", - "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", - "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", - "~el2_ifu|el2_ifu>io_ic_rd_data", - "~el2_ifu|el2_ifu>io_dec_i0_decode_d" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_iccm_rden", - "sources":[ - "~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_dma_mem_write", - "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", - "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", - "~el2_ifu|el2_ifu>io_exu_flush_final", - "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_exu_flush_path_final", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", - "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", - "~el2_ifu|el2_ifu>io_ic_rd_data", - "~el2_ifu|el2_ifu>io_dec_i0_decode_d" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_ic_premux_data", - "sources":[ - "~el2_ifu|el2_ifu>io_iccm_rd_data", - "~el2_ifu|el2_ifu>io_exu_flush_final", - "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_ifu_axi_rid", - "~el2_ifu|el2_ifu>io_ifu_axi_rvalid", - "~el2_ifu|el2_ifu>io_ifu_bus_clk_en", - "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", - "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_iccm_ready", - "sources":[ + "~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", @@ -92,8 +32,8 @@ "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", @@ -122,58 +62,6 @@ "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_rd_valid" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error", - "sources":[ - "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", - "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", - "~el2_ifu|el2_ifu>io_exu_flush_final", - "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", - "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start", - "sources":[ - "~el2_ifu|el2_ifu>io_ic_eccerr", - "~el2_ifu|el2_ifu>io_ic_tag_perr", - "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_exu_flush_final", - "~el2_ifu|el2_ifu>io_ifu_axi_rid", - "~el2_ifu|el2_ifu>io_ifu_axi_rvalid", - "~el2_ifu|el2_ifu>io_ifu_bus_clk_en", - "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", - "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data", - "sources":[ - "~el2_ifu|el2_ifu>io_exu_flush_final", - "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_ifu_axi_rid", - "~el2_ifu|el2_ifu>io_ifu_axi_rvalid", - "~el2_ifu|el2_ifu>io_ifu_bus_clk_en", - "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", - "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_iccm_wr_data", @@ -189,8 +77,8 @@ "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", "~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", @@ -215,50 +103,61 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr", + "sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start", "sources":[ - "~el2_ifu|el2_ifu>io_dma_mem_addr", - "~el2_ifu|el2_ifu>io_dma_iccm_req", - "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", - "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", - "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_ic_eccerr", + "~el2_ifu|el2_ifu>io_ic_tag_perr", "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_exu_flush_path_final", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", + "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_ifu_axi_rid", + "~el2_ifu|el2_ifu>io_ifu_axi_rvalid", + "~el2_ifu|el2_ifu>io_ifu_bus_clk_en", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", - "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", - "~el2_ifu|el2_ifu>io_dec_i0_decode_d", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", - "~el2_ifu|el2_ifu>io_ic_rd_data" + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", + "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_iccm_wren", + "sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error", "sources":[ - "~el2_ifu|el2_ifu>io_dma_mem_write", - "~el2_ifu|el2_ifu>io_dma_iccm_req", "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", - "~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", + "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu|el2_ifu>io_iccm_rden", + "sources":[ + "~el2_ifu|el2_ifu>io_dma_iccm_req", + "~el2_ifu|el2_ifu>io_dma_mem_write", + "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", + "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", + "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_ic_rd_hit", + "~el2_ifu|el2_ifu>io_exu_flush_path_final", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", - "~el2_ifu|el2_ifu>io_dec_i0_decode_d", "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", - "~el2_ifu|el2_ifu>io_ic_rd_data" + "~el2_ifu|el2_ifu>io_ic_rd_data", + "~el2_ifu|el2_ifu>io_dec_i0_decode_d" ] }, { @@ -268,6 +167,62 @@ "~el2_ifu|el2_ifu>io_dec_i0_decode_d" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error", + "sources":[ + "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", + "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", + "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_ic_rd_hit", + "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", + "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array", + "sources":[ + "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu|el2_ifu>io_ic_premux_data", + "sources":[ + "~el2_ifu|el2_ifu>io_iccm_rd_data", + "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_ic_rd_hit", + "~el2_ifu|el2_ifu>io_ifu_axi_rid", + "~el2_ifu|el2_ifu>io_ifu_axi_rvalid", + "~el2_ifu|el2_ifu>io_ifu_bus_clk_en", + "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", + "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu|el2_ifu>io_ic_rw_addr", + "sources":[ + "~el2_ifu|el2_ifu>io_exu_flush_path_final", + "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", + "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", + "~el2_ifu|el2_ifu>io_ic_rd_hit", + "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err", @@ -279,33 +234,8 @@ "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", - "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array", - "sources":[ - "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall", - "sources":[ - "~el2_ifu|el2_ifu>io_exu_flush_final", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", - "~el2_ifu|el2_ifu>io_ic_rd_data", - "~el2_ifu|el2_ifu>io_dec_i0_decode_d", - "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" ] }, @@ -318,17 +248,48 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu|el2_ifu>io_ic_rw_addr", + "sink":"~el2_ifu|el2_ifu>io_ic_rd_en", "sources":[ - "~el2_ifu|el2_ifu>io_exu_flush_path_final", "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_dec_tlu_force_halt", + "~el2_ifu|el2_ifu>io_ic_rd_hit", + "~el2_ifu|el2_ifu>io_exu_flush_path_final", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff", + "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error", - "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", + "~el2_ifu|el2_ifu>io_ic_rd_data", + "~el2_ifu|el2_ifu>io_dec_i0_decode_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr", + "sources":[ + "~el2_ifu|el2_ifu>io_dma_mem_addr", + "~el2_ifu|el2_ifu>io_dma_iccm_req", + "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", + "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", + "~el2_ifu|el2_ifu>io_exu_flush_final", "~el2_ifu|el2_ifu>io_ic_rd_hit", - "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable" + "~el2_ifu|el2_ifu>io_exu_flush_path_final", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", + "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", + "~el2_ifu|el2_ifu>io_dec_i0_decode_d", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", + "~el2_ifu|el2_ifu>io_ic_rd_data" ] }, { @@ -338,6 +299,45 @@ "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu|el2_ifu>io_iccm_ready", + "sources":[ + "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable", + "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc", + "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_ic_rd_hit", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb", + "~el2_ifu|el2_ifu>io_exu_flush_path_final", + "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", + "~el2_ifu|el2_ifu>io_exu_i0_br_index_r", + "~el2_ifu|el2_ifu>io_dec_i0_decode_d", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt", + "~el2_ifu|el2_ifu>io_ic_rd_data" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data", + "sources":[ + "~el2_ifu|el2_ifu>io_exu_flush_final", + "~el2_ifu|el2_ifu>io_ic_rd_hit", + "~el2_ifu|el2_ifu>io_ifu_axi_rid", + "~el2_ifu|el2_ifu>io_ifu_axi_rvalid", + "~el2_ifu|el2_ifu>io_ifu_bus_clk_en", + "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error", + "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error", + "~el2_ifu|el2_ifu>io_exu_i0_br_index_r" + ] + }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" diff --git a/el2_ifu.fir b/el2_ifu.fir index 3217e507..b37a29ee 100644 --- a/el2_ifu.fir +++ b/el2_ifu.fir @@ -28977,7 +28977,7 @@ circuit el2_ifu : module el2_ifu_bp_ctl : input clock : Clock input reset : AsyncReset - output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt} + output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt} wire leak_one_f : UInt<1> leak_one_f <= UInt<1>("h00") @@ -29004,10 +29004,10 @@ circuit el2_ifu : dec_tlu_way_wb <= UInt<1>("h00") node _T = eq(leak_one_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 72:51] node exu_mp_valid = and(io.exu_mp_pkt.bits.misp, _T) @[el2_ifu_bp_ctl.scala 72:49] - node _T_1 = or(io.dec_tlu_br0_r_pkt.bits.br_start_error, io.dec_tlu_br0_r_pkt.bits.br_error) @[el2_ifu_bp_ctl.scala 94:50] + node _T_1 = or(io.dec_tlu_br0_r_pkt.br_start_error, io.dec_tlu_br0_r_pkt.br_error) @[el2_ifu_bp_ctl.scala 94:50] dec_tlu_error_wb <= _T_1 @[el2_ifu_bp_ctl.scala 94:20] btb_error_addr_wb <= io.exu_i0_br_index_r @[el2_ifu_bp_ctl.scala 95:21] - dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu_bp_ctl.scala 96:18] + dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.way @[el2_ifu_bp_ctl.scala 96:18] node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 191:13] node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 191:51] node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 191:47] @@ -29814,8 +29814,8 @@ circuit el2_ifu : node bht_wr_en0 = and(_T_556, _T_558) @[el2_ifu_bp_ctl.scala 408:84] node _T_559 = bits(io.dec_tlu_br0_r_pkt.valid, 0, 0) @[Bitwise.scala 72:15] node _T_560 = mux(_T_559, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_561 = not(io.dec_tlu_br0_r_pkt.bits.middle) @[el2_ifu_bp_ctl.scala 409:75] - node _T_562 = cat(io.dec_tlu_br0_r_pkt.bits.middle, _T_561) @[Cat.scala 29:58] + node _T_561 = not(io.dec_tlu_br0_r_pkt.middle) @[el2_ifu_bp_ctl.scala 409:75] + node _T_562 = cat(io.dec_tlu_br0_r_pkt.middle, _T_561) @[Cat.scala 29:58] node bht_wr_en2 = and(_T_560, _T_562) @[el2_ifu_bp_ctl.scala 409:46] node _T_563 = cat(io.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58] node _T_564 = bits(_T_563, 9, 2) @[el2_lib.scala 196:16] @@ -40155,7 +40155,7 @@ circuit el2_ifu : node _T_6565 = and(_T_6562, _T_6564) @[el2_ifu_bp_ctl.scala 447:81] node _T_6566 = or(_T_6565, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6567 = bits(_T_6566, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6568 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6569 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6570 = eq(_T_6569, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40165,7 +40165,7 @@ circuit el2_ifu : node _T_6574 = and(_T_6571, _T_6573) @[el2_ifu_bp_ctl.scala 447:81] node _T_6575 = or(_T_6574, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6576 = bits(_T_6575, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6577 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6578 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6579 = eq(_T_6578, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40175,7 +40175,7 @@ circuit el2_ifu : node _T_6583 = and(_T_6580, _T_6582) @[el2_ifu_bp_ctl.scala 447:81] node _T_6584 = or(_T_6583, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6585 = bits(_T_6584, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6586 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6587 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6588 = eq(_T_6587, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40185,7 +40185,7 @@ circuit el2_ifu : node _T_6592 = and(_T_6589, _T_6591) @[el2_ifu_bp_ctl.scala 447:81] node _T_6593 = or(_T_6592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6594 = bits(_T_6593, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6595 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6596 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6597 = eq(_T_6596, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40195,7 +40195,7 @@ circuit el2_ifu : node _T_6601 = and(_T_6598, _T_6600) @[el2_ifu_bp_ctl.scala 447:81] node _T_6602 = or(_T_6601, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6603 = bits(_T_6602, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6604 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6605 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6606 = eq(_T_6605, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40205,7 +40205,7 @@ circuit el2_ifu : node _T_6610 = and(_T_6607, _T_6609) @[el2_ifu_bp_ctl.scala 447:81] node _T_6611 = or(_T_6610, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6612 = bits(_T_6611, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6613 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6614 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6615 = eq(_T_6614, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40215,7 +40215,7 @@ circuit el2_ifu : node _T_6619 = and(_T_6616, _T_6618) @[el2_ifu_bp_ctl.scala 447:81] node _T_6620 = or(_T_6619, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6621 = bits(_T_6620, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6622 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6623 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6624 = eq(_T_6623, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40225,7 +40225,7 @@ circuit el2_ifu : node _T_6628 = and(_T_6625, _T_6627) @[el2_ifu_bp_ctl.scala 447:81] node _T_6629 = or(_T_6628, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6630 = bits(_T_6629, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6631 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6632 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6633 = eq(_T_6632, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40235,7 +40235,7 @@ circuit el2_ifu : node _T_6637 = and(_T_6634, _T_6636) @[el2_ifu_bp_ctl.scala 447:81] node _T_6638 = or(_T_6637, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6639 = bits(_T_6638, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6640 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6641 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6642 = eq(_T_6641, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40245,7 +40245,7 @@ circuit el2_ifu : node _T_6646 = and(_T_6643, _T_6645) @[el2_ifu_bp_ctl.scala 447:81] node _T_6647 = or(_T_6646, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6648 = bits(_T_6647, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6649 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6650 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6651 = eq(_T_6650, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40255,7 +40255,7 @@ circuit el2_ifu : node _T_6655 = and(_T_6652, _T_6654) @[el2_ifu_bp_ctl.scala 447:81] node _T_6656 = or(_T_6655, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6657 = bits(_T_6656, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6658 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6659 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6660 = eq(_T_6659, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40265,7 +40265,7 @@ circuit el2_ifu : node _T_6664 = and(_T_6661, _T_6663) @[el2_ifu_bp_ctl.scala 447:81] node _T_6665 = or(_T_6664, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6666 = bits(_T_6665, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6667 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6668 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6669 = eq(_T_6668, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40275,7 +40275,7 @@ circuit el2_ifu : node _T_6673 = and(_T_6670, _T_6672) @[el2_ifu_bp_ctl.scala 447:81] node _T_6674 = or(_T_6673, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6675 = bits(_T_6674, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6676 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6677 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6678 = eq(_T_6677, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40285,7 +40285,7 @@ circuit el2_ifu : node _T_6682 = and(_T_6679, _T_6681) @[el2_ifu_bp_ctl.scala 447:81] node _T_6683 = or(_T_6682, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6684 = bits(_T_6683, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6685 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6686 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6687 = eq(_T_6686, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40295,7 +40295,7 @@ circuit el2_ifu : node _T_6691 = and(_T_6688, _T_6690) @[el2_ifu_bp_ctl.scala 447:81] node _T_6692 = or(_T_6691, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6693 = bits(_T_6692, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6694 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6695 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6696 = eq(_T_6695, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40305,7 +40305,7 @@ circuit el2_ifu : node _T_6700 = and(_T_6697, _T_6699) @[el2_ifu_bp_ctl.scala 447:81] node _T_6701 = or(_T_6700, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6702 = bits(_T_6701, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6703 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6704 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6705 = eq(_T_6704, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40315,7 +40315,7 @@ circuit el2_ifu : node _T_6709 = and(_T_6706, _T_6708) @[el2_ifu_bp_ctl.scala 447:81] node _T_6710 = or(_T_6709, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6711 = bits(_T_6710, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6712 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6713 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6714 = eq(_T_6713, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40325,7 +40325,7 @@ circuit el2_ifu : node _T_6718 = and(_T_6715, _T_6717) @[el2_ifu_bp_ctl.scala 447:81] node _T_6719 = or(_T_6718, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6720 = bits(_T_6719, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6721 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6722 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6723 = eq(_T_6722, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40335,7 +40335,7 @@ circuit el2_ifu : node _T_6727 = and(_T_6724, _T_6726) @[el2_ifu_bp_ctl.scala 447:81] node _T_6728 = or(_T_6727, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6729 = bits(_T_6728, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6730 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6731 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6732 = eq(_T_6731, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40345,7 +40345,7 @@ circuit el2_ifu : node _T_6736 = and(_T_6733, _T_6735) @[el2_ifu_bp_ctl.scala 447:81] node _T_6737 = or(_T_6736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6738 = bits(_T_6737, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6739 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6740 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6741 = eq(_T_6740, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40355,7 +40355,7 @@ circuit el2_ifu : node _T_6745 = and(_T_6742, _T_6744) @[el2_ifu_bp_ctl.scala 447:81] node _T_6746 = or(_T_6745, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6747 = bits(_T_6746, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6748 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6749 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6750 = eq(_T_6749, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40365,7 +40365,7 @@ circuit el2_ifu : node _T_6754 = and(_T_6751, _T_6753) @[el2_ifu_bp_ctl.scala 447:81] node _T_6755 = or(_T_6754, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6756 = bits(_T_6755, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6757 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6758 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6759 = eq(_T_6758, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40375,7 +40375,7 @@ circuit el2_ifu : node _T_6763 = and(_T_6760, _T_6762) @[el2_ifu_bp_ctl.scala 447:81] node _T_6764 = or(_T_6763, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6765 = bits(_T_6764, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6766 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6767 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6768 = eq(_T_6767, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40385,7 +40385,7 @@ circuit el2_ifu : node _T_6772 = and(_T_6769, _T_6771) @[el2_ifu_bp_ctl.scala 447:81] node _T_6773 = or(_T_6772, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6774 = bits(_T_6773, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6775 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6776 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6777 = eq(_T_6776, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40395,7 +40395,7 @@ circuit el2_ifu : node _T_6781 = and(_T_6778, _T_6780) @[el2_ifu_bp_ctl.scala 447:81] node _T_6782 = or(_T_6781, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6783 = bits(_T_6782, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6784 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6785 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6786 = eq(_T_6785, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40405,7 +40405,7 @@ circuit el2_ifu : node _T_6790 = and(_T_6787, _T_6789) @[el2_ifu_bp_ctl.scala 447:81] node _T_6791 = or(_T_6790, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6792 = bits(_T_6791, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6793 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6794 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6795 = eq(_T_6794, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40415,7 +40415,7 @@ circuit el2_ifu : node _T_6799 = and(_T_6796, _T_6798) @[el2_ifu_bp_ctl.scala 447:81] node _T_6800 = or(_T_6799, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6801 = bits(_T_6800, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6802 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6803 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6804 = eq(_T_6803, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40425,7 +40425,7 @@ circuit el2_ifu : node _T_6808 = and(_T_6805, _T_6807) @[el2_ifu_bp_ctl.scala 447:81] node _T_6809 = or(_T_6808, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6810 = bits(_T_6809, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6811 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6812 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6813 = eq(_T_6812, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40435,7 +40435,7 @@ circuit el2_ifu : node _T_6817 = and(_T_6814, _T_6816) @[el2_ifu_bp_ctl.scala 447:81] node _T_6818 = or(_T_6817, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6819 = bits(_T_6818, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6820 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6821 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6822 = eq(_T_6821, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40445,7 +40445,7 @@ circuit el2_ifu : node _T_6826 = and(_T_6823, _T_6825) @[el2_ifu_bp_ctl.scala 447:81] node _T_6827 = or(_T_6826, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6828 = bits(_T_6827, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6829 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6830 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6831 = eq(_T_6830, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40455,7 +40455,7 @@ circuit el2_ifu : node _T_6835 = and(_T_6832, _T_6834) @[el2_ifu_bp_ctl.scala 447:81] node _T_6836 = or(_T_6835, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6837 = bits(_T_6836, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6838 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6839 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6840 = eq(_T_6839, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40465,7 +40465,7 @@ circuit el2_ifu : node _T_6844 = and(_T_6841, _T_6843) @[el2_ifu_bp_ctl.scala 447:81] node _T_6845 = or(_T_6844, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6846 = bits(_T_6845, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6847 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6848 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6849 = eq(_T_6848, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40475,7 +40475,7 @@ circuit el2_ifu : node _T_6853 = and(_T_6850, _T_6852) @[el2_ifu_bp_ctl.scala 447:81] node _T_6854 = or(_T_6853, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6855 = bits(_T_6854, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6856 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6857 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6858 = eq(_T_6857, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40485,7 +40485,7 @@ circuit el2_ifu : node _T_6862 = and(_T_6859, _T_6861) @[el2_ifu_bp_ctl.scala 447:81] node _T_6863 = or(_T_6862, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6864 = bits(_T_6863, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6865 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6866 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6867 = eq(_T_6866, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40495,7 +40495,7 @@ circuit el2_ifu : node _T_6871 = and(_T_6868, _T_6870) @[el2_ifu_bp_ctl.scala 447:81] node _T_6872 = or(_T_6871, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6873 = bits(_T_6872, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6874 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6875 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6876 = eq(_T_6875, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40505,7 +40505,7 @@ circuit el2_ifu : node _T_6880 = and(_T_6877, _T_6879) @[el2_ifu_bp_ctl.scala 447:81] node _T_6881 = or(_T_6880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6882 = bits(_T_6881, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6883 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6884 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6885 = eq(_T_6884, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40515,7 +40515,7 @@ circuit el2_ifu : node _T_6889 = and(_T_6886, _T_6888) @[el2_ifu_bp_ctl.scala 447:81] node _T_6890 = or(_T_6889, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6891 = bits(_T_6890, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6892 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6893 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6894 = eq(_T_6893, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40525,7 +40525,7 @@ circuit el2_ifu : node _T_6898 = and(_T_6895, _T_6897) @[el2_ifu_bp_ctl.scala 447:81] node _T_6899 = or(_T_6898, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6900 = bits(_T_6899, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6901 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6902 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6903 = eq(_T_6902, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40535,7 +40535,7 @@ circuit el2_ifu : node _T_6907 = and(_T_6904, _T_6906) @[el2_ifu_bp_ctl.scala 447:81] node _T_6908 = or(_T_6907, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6909 = bits(_T_6908, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6910 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6911 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6912 = eq(_T_6911, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40545,7 +40545,7 @@ circuit el2_ifu : node _T_6916 = and(_T_6913, _T_6915) @[el2_ifu_bp_ctl.scala 447:81] node _T_6917 = or(_T_6916, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6918 = bits(_T_6917, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6919 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6920 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6921 = eq(_T_6920, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40555,7 +40555,7 @@ circuit el2_ifu : node _T_6925 = and(_T_6922, _T_6924) @[el2_ifu_bp_ctl.scala 447:81] node _T_6926 = or(_T_6925, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6927 = bits(_T_6926, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6928 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6929 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6930 = eq(_T_6929, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40565,7 +40565,7 @@ circuit el2_ifu : node _T_6934 = and(_T_6931, _T_6933) @[el2_ifu_bp_ctl.scala 447:81] node _T_6935 = or(_T_6934, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6936 = bits(_T_6935, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6937 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6938 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6939 = eq(_T_6938, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40575,7 +40575,7 @@ circuit el2_ifu : node _T_6943 = and(_T_6940, _T_6942) @[el2_ifu_bp_ctl.scala 447:81] node _T_6944 = or(_T_6943, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6945 = bits(_T_6944, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6946 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6947 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6948 = eq(_T_6947, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40585,7 +40585,7 @@ circuit el2_ifu : node _T_6952 = and(_T_6949, _T_6951) @[el2_ifu_bp_ctl.scala 447:81] node _T_6953 = or(_T_6952, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6954 = bits(_T_6953, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6955 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6956 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6957 = eq(_T_6956, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40595,7 +40595,7 @@ circuit el2_ifu : node _T_6961 = and(_T_6958, _T_6960) @[el2_ifu_bp_ctl.scala 447:81] node _T_6962 = or(_T_6961, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6963 = bits(_T_6962, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6964 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6965 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6966 = eq(_T_6965, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40605,7 +40605,7 @@ circuit el2_ifu : node _T_6970 = and(_T_6967, _T_6969) @[el2_ifu_bp_ctl.scala 447:81] node _T_6971 = or(_T_6970, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6972 = bits(_T_6971, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6973 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6974 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6975 = eq(_T_6974, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40615,7 +40615,7 @@ circuit el2_ifu : node _T_6979 = and(_T_6976, _T_6978) @[el2_ifu_bp_ctl.scala 447:81] node _T_6980 = or(_T_6979, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6981 = bits(_T_6980, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6982 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6983 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6984 = eq(_T_6983, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40625,7 +40625,7 @@ circuit el2_ifu : node _T_6988 = and(_T_6985, _T_6987) @[el2_ifu_bp_ctl.scala 447:81] node _T_6989 = or(_T_6988, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6990 = bits(_T_6989, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6991 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6992 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6993 = eq(_T_6992, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40635,7 +40635,7 @@ circuit el2_ifu : node _T_6997 = and(_T_6994, _T_6996) @[el2_ifu_bp_ctl.scala 447:81] node _T_6998 = or(_T_6997, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6999 = bits(_T_6998, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7000 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7001 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7002 = eq(_T_7001, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40645,7 +40645,7 @@ circuit el2_ifu : node _T_7006 = and(_T_7003, _T_7005) @[el2_ifu_bp_ctl.scala 447:81] node _T_7007 = or(_T_7006, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7008 = bits(_T_7007, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7009 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7010 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7011 = eq(_T_7010, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40655,7 +40655,7 @@ circuit el2_ifu : node _T_7015 = and(_T_7012, _T_7014) @[el2_ifu_bp_ctl.scala 447:81] node _T_7016 = or(_T_7015, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7017 = bits(_T_7016, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7018 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7019 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7020 = eq(_T_7019, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40665,7 +40665,7 @@ circuit el2_ifu : node _T_7024 = and(_T_7021, _T_7023) @[el2_ifu_bp_ctl.scala 447:81] node _T_7025 = or(_T_7024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7026 = bits(_T_7025, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7027 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7028 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7029 = eq(_T_7028, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40675,7 +40675,7 @@ circuit el2_ifu : node _T_7033 = and(_T_7030, _T_7032) @[el2_ifu_bp_ctl.scala 447:81] node _T_7034 = or(_T_7033, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7035 = bits(_T_7034, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7036 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7037 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7038 = eq(_T_7037, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40685,7 +40685,7 @@ circuit el2_ifu : node _T_7042 = and(_T_7039, _T_7041) @[el2_ifu_bp_ctl.scala 447:81] node _T_7043 = or(_T_7042, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7044 = bits(_T_7043, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7045 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7046 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7047 = eq(_T_7046, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40695,7 +40695,7 @@ circuit el2_ifu : node _T_7051 = and(_T_7048, _T_7050) @[el2_ifu_bp_ctl.scala 447:81] node _T_7052 = or(_T_7051, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7053 = bits(_T_7052, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7054 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7055 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7056 = eq(_T_7055, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40705,7 +40705,7 @@ circuit el2_ifu : node _T_7060 = and(_T_7057, _T_7059) @[el2_ifu_bp_ctl.scala 447:81] node _T_7061 = or(_T_7060, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7062 = bits(_T_7061, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7063 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7064 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7065 = eq(_T_7064, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40715,7 +40715,7 @@ circuit el2_ifu : node _T_7069 = and(_T_7066, _T_7068) @[el2_ifu_bp_ctl.scala 447:81] node _T_7070 = or(_T_7069, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7071 = bits(_T_7070, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7072 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7073 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7074 = eq(_T_7073, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40725,7 +40725,7 @@ circuit el2_ifu : node _T_7078 = and(_T_7075, _T_7077) @[el2_ifu_bp_ctl.scala 447:81] node _T_7079 = or(_T_7078, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7080 = bits(_T_7079, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7081 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7082 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7083 = eq(_T_7082, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40735,7 +40735,7 @@ circuit el2_ifu : node _T_7087 = and(_T_7084, _T_7086) @[el2_ifu_bp_ctl.scala 447:81] node _T_7088 = or(_T_7087, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7089 = bits(_T_7088, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7090 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7091 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7092 = eq(_T_7091, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40745,7 +40745,7 @@ circuit el2_ifu : node _T_7096 = and(_T_7093, _T_7095) @[el2_ifu_bp_ctl.scala 447:81] node _T_7097 = or(_T_7096, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7098 = bits(_T_7097, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7099 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7100 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7101 = eq(_T_7100, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40755,7 +40755,7 @@ circuit el2_ifu : node _T_7105 = and(_T_7102, _T_7104) @[el2_ifu_bp_ctl.scala 447:81] node _T_7106 = or(_T_7105, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7107 = bits(_T_7106, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7108 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7109 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7110 = eq(_T_7109, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40765,7 +40765,7 @@ circuit el2_ifu : node _T_7114 = and(_T_7111, _T_7113) @[el2_ifu_bp_ctl.scala 447:81] node _T_7115 = or(_T_7114, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7116 = bits(_T_7115, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7117 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7118 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7119 = eq(_T_7118, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40775,7 +40775,7 @@ circuit el2_ifu : node _T_7123 = and(_T_7120, _T_7122) @[el2_ifu_bp_ctl.scala 447:81] node _T_7124 = or(_T_7123, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7125 = bits(_T_7124, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7126 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7127 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7128 = eq(_T_7127, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40785,7 +40785,7 @@ circuit el2_ifu : node _T_7132 = and(_T_7129, _T_7131) @[el2_ifu_bp_ctl.scala 447:81] node _T_7133 = or(_T_7132, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7134 = bits(_T_7133, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7135 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7136 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7137 = eq(_T_7136, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40795,7 +40795,7 @@ circuit el2_ifu : node _T_7141 = and(_T_7138, _T_7140) @[el2_ifu_bp_ctl.scala 447:81] node _T_7142 = or(_T_7141, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7143 = bits(_T_7142, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7144 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7145 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7146 = eq(_T_7145, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40805,7 +40805,7 @@ circuit el2_ifu : node _T_7150 = and(_T_7147, _T_7149) @[el2_ifu_bp_ctl.scala 447:81] node _T_7151 = or(_T_7150, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7152 = bits(_T_7151, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7153 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7154 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7155 = eq(_T_7154, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40815,7 +40815,7 @@ circuit el2_ifu : node _T_7159 = and(_T_7156, _T_7158) @[el2_ifu_bp_ctl.scala 447:81] node _T_7160 = or(_T_7159, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7161 = bits(_T_7160, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7162 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7163 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7164 = eq(_T_7163, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40825,7 +40825,7 @@ circuit el2_ifu : node _T_7168 = and(_T_7165, _T_7167) @[el2_ifu_bp_ctl.scala 447:81] node _T_7169 = or(_T_7168, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7170 = bits(_T_7169, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7171 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7172 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7173 = eq(_T_7172, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40835,7 +40835,7 @@ circuit el2_ifu : node _T_7177 = and(_T_7174, _T_7176) @[el2_ifu_bp_ctl.scala 447:81] node _T_7178 = or(_T_7177, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7179 = bits(_T_7178, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7180 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7181 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7182 = eq(_T_7181, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40845,7 +40845,7 @@ circuit el2_ifu : node _T_7186 = and(_T_7183, _T_7185) @[el2_ifu_bp_ctl.scala 447:81] node _T_7187 = or(_T_7186, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7188 = bits(_T_7187, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7189 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7190 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7191 = eq(_T_7190, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40855,7 +40855,7 @@ circuit el2_ifu : node _T_7195 = and(_T_7192, _T_7194) @[el2_ifu_bp_ctl.scala 447:81] node _T_7196 = or(_T_7195, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7197 = bits(_T_7196, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7198 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7199 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7200 = eq(_T_7199, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40865,7 +40865,7 @@ circuit el2_ifu : node _T_7204 = and(_T_7201, _T_7203) @[el2_ifu_bp_ctl.scala 447:81] node _T_7205 = or(_T_7204, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7206 = bits(_T_7205, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7207 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7208 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7209 = eq(_T_7208, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40875,7 +40875,7 @@ circuit el2_ifu : node _T_7213 = and(_T_7210, _T_7212) @[el2_ifu_bp_ctl.scala 447:81] node _T_7214 = or(_T_7213, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7215 = bits(_T_7214, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7216 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7217 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7218 = eq(_T_7217, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40885,7 +40885,7 @@ circuit el2_ifu : node _T_7222 = and(_T_7219, _T_7221) @[el2_ifu_bp_ctl.scala 447:81] node _T_7223 = or(_T_7222, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7224 = bits(_T_7223, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7225 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7226 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7227 = eq(_T_7226, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40895,7 +40895,7 @@ circuit el2_ifu : node _T_7231 = and(_T_7228, _T_7230) @[el2_ifu_bp_ctl.scala 447:81] node _T_7232 = or(_T_7231, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7233 = bits(_T_7232, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7234 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7235 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7236 = eq(_T_7235, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40905,7 +40905,7 @@ circuit el2_ifu : node _T_7240 = and(_T_7237, _T_7239) @[el2_ifu_bp_ctl.scala 447:81] node _T_7241 = or(_T_7240, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7242 = bits(_T_7241, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7243 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7244 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7245 = eq(_T_7244, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40915,7 +40915,7 @@ circuit el2_ifu : node _T_7249 = and(_T_7246, _T_7248) @[el2_ifu_bp_ctl.scala 447:81] node _T_7250 = or(_T_7249, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7251 = bits(_T_7250, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7252 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7253 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7254 = eq(_T_7253, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40925,7 +40925,7 @@ circuit el2_ifu : node _T_7258 = and(_T_7255, _T_7257) @[el2_ifu_bp_ctl.scala 447:81] node _T_7259 = or(_T_7258, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7260 = bits(_T_7259, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7261 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7262 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7263 = eq(_T_7262, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40935,7 +40935,7 @@ circuit el2_ifu : node _T_7267 = and(_T_7264, _T_7266) @[el2_ifu_bp_ctl.scala 447:81] node _T_7268 = or(_T_7267, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7269 = bits(_T_7268, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7270 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7271 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7272 = eq(_T_7271, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40945,7 +40945,7 @@ circuit el2_ifu : node _T_7276 = and(_T_7273, _T_7275) @[el2_ifu_bp_ctl.scala 447:81] node _T_7277 = or(_T_7276, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7278 = bits(_T_7277, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7279 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7280 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7281 = eq(_T_7280, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40955,7 +40955,7 @@ circuit el2_ifu : node _T_7285 = and(_T_7282, _T_7284) @[el2_ifu_bp_ctl.scala 447:81] node _T_7286 = or(_T_7285, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7287 = bits(_T_7286, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7288 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7289 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7290 = eq(_T_7289, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40965,7 +40965,7 @@ circuit el2_ifu : node _T_7294 = and(_T_7291, _T_7293) @[el2_ifu_bp_ctl.scala 447:81] node _T_7295 = or(_T_7294, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7296 = bits(_T_7295, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7297 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7298 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7299 = eq(_T_7298, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40975,7 +40975,7 @@ circuit el2_ifu : node _T_7303 = and(_T_7300, _T_7302) @[el2_ifu_bp_ctl.scala 447:81] node _T_7304 = or(_T_7303, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7305 = bits(_T_7304, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7306 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7307 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7308 = eq(_T_7307, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40985,7 +40985,7 @@ circuit el2_ifu : node _T_7312 = and(_T_7309, _T_7311) @[el2_ifu_bp_ctl.scala 447:81] node _T_7313 = or(_T_7312, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7314 = bits(_T_7313, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7315 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7316 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7317 = eq(_T_7316, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40995,7 +40995,7 @@ circuit el2_ifu : node _T_7321 = and(_T_7318, _T_7320) @[el2_ifu_bp_ctl.scala 447:81] node _T_7322 = or(_T_7321, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7323 = bits(_T_7322, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7324 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7325 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7326 = eq(_T_7325, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41005,7 +41005,7 @@ circuit el2_ifu : node _T_7330 = and(_T_7327, _T_7329) @[el2_ifu_bp_ctl.scala 447:81] node _T_7331 = or(_T_7330, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7332 = bits(_T_7331, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7333 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7334 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7335 = eq(_T_7334, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41015,7 +41015,7 @@ circuit el2_ifu : node _T_7339 = and(_T_7336, _T_7338) @[el2_ifu_bp_ctl.scala 447:81] node _T_7340 = or(_T_7339, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7341 = bits(_T_7340, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7342 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7343 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7344 = eq(_T_7343, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41025,7 +41025,7 @@ circuit el2_ifu : node _T_7348 = and(_T_7345, _T_7347) @[el2_ifu_bp_ctl.scala 447:81] node _T_7349 = or(_T_7348, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7350 = bits(_T_7349, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7351 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7352 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7353 = eq(_T_7352, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41035,7 +41035,7 @@ circuit el2_ifu : node _T_7357 = and(_T_7354, _T_7356) @[el2_ifu_bp_ctl.scala 447:81] node _T_7358 = or(_T_7357, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7359 = bits(_T_7358, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7360 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7361 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7362 = eq(_T_7361, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41045,7 +41045,7 @@ circuit el2_ifu : node _T_7366 = and(_T_7363, _T_7365) @[el2_ifu_bp_ctl.scala 447:81] node _T_7367 = or(_T_7366, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7368 = bits(_T_7367, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7369 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7370 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7371 = eq(_T_7370, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41055,7 +41055,7 @@ circuit el2_ifu : node _T_7375 = and(_T_7372, _T_7374) @[el2_ifu_bp_ctl.scala 447:81] node _T_7376 = or(_T_7375, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7377 = bits(_T_7376, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7378 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7379 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7380 = eq(_T_7379, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41065,7 +41065,7 @@ circuit el2_ifu : node _T_7384 = and(_T_7381, _T_7383) @[el2_ifu_bp_ctl.scala 447:81] node _T_7385 = or(_T_7384, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7386 = bits(_T_7385, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7387 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7388 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7389 = eq(_T_7388, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41075,7 +41075,7 @@ circuit el2_ifu : node _T_7393 = and(_T_7390, _T_7392) @[el2_ifu_bp_ctl.scala 447:81] node _T_7394 = or(_T_7393, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7395 = bits(_T_7394, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7396 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7397 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7398 = eq(_T_7397, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41085,7 +41085,7 @@ circuit el2_ifu : node _T_7402 = and(_T_7399, _T_7401) @[el2_ifu_bp_ctl.scala 447:81] node _T_7403 = or(_T_7402, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7404 = bits(_T_7403, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7405 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7406 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7407 = eq(_T_7406, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41095,7 +41095,7 @@ circuit el2_ifu : node _T_7411 = and(_T_7408, _T_7410) @[el2_ifu_bp_ctl.scala 447:81] node _T_7412 = or(_T_7411, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7413 = bits(_T_7412, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7414 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7415 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7416 = eq(_T_7415, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41105,7 +41105,7 @@ circuit el2_ifu : node _T_7420 = and(_T_7417, _T_7419) @[el2_ifu_bp_ctl.scala 447:81] node _T_7421 = or(_T_7420, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7422 = bits(_T_7421, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7423 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7424 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7425 = eq(_T_7424, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41115,7 +41115,7 @@ circuit el2_ifu : node _T_7429 = and(_T_7426, _T_7428) @[el2_ifu_bp_ctl.scala 447:81] node _T_7430 = or(_T_7429, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7431 = bits(_T_7430, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7432 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7433 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7434 = eq(_T_7433, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41125,7 +41125,7 @@ circuit el2_ifu : node _T_7438 = and(_T_7435, _T_7437) @[el2_ifu_bp_ctl.scala 447:81] node _T_7439 = or(_T_7438, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7440 = bits(_T_7439, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7441 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7442 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7443 = eq(_T_7442, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41135,7 +41135,7 @@ circuit el2_ifu : node _T_7447 = and(_T_7444, _T_7446) @[el2_ifu_bp_ctl.scala 447:81] node _T_7448 = or(_T_7447, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7449 = bits(_T_7448, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7450 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7451 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7452 = eq(_T_7451, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41145,7 +41145,7 @@ circuit el2_ifu : node _T_7456 = and(_T_7453, _T_7455) @[el2_ifu_bp_ctl.scala 447:81] node _T_7457 = or(_T_7456, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7458 = bits(_T_7457, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7459 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7460 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7461 = eq(_T_7460, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41155,7 +41155,7 @@ circuit el2_ifu : node _T_7465 = and(_T_7462, _T_7464) @[el2_ifu_bp_ctl.scala 447:81] node _T_7466 = or(_T_7465, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7467 = bits(_T_7466, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7468 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7469 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7470 = eq(_T_7469, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41165,7 +41165,7 @@ circuit el2_ifu : node _T_7474 = and(_T_7471, _T_7473) @[el2_ifu_bp_ctl.scala 447:81] node _T_7475 = or(_T_7474, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7476 = bits(_T_7475, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7477 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7478 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7479 = eq(_T_7478, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41175,7 +41175,7 @@ circuit el2_ifu : node _T_7483 = and(_T_7480, _T_7482) @[el2_ifu_bp_ctl.scala 447:81] node _T_7484 = or(_T_7483, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7485 = bits(_T_7484, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7486 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7487 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7488 = eq(_T_7487, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41185,7 +41185,7 @@ circuit el2_ifu : node _T_7492 = and(_T_7489, _T_7491) @[el2_ifu_bp_ctl.scala 447:81] node _T_7493 = or(_T_7492, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7494 = bits(_T_7493, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7495 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7496 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7497 = eq(_T_7496, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41195,7 +41195,7 @@ circuit el2_ifu : node _T_7501 = and(_T_7498, _T_7500) @[el2_ifu_bp_ctl.scala 447:81] node _T_7502 = or(_T_7501, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7503 = bits(_T_7502, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7504 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7505 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7506 = eq(_T_7505, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41205,7 +41205,7 @@ circuit el2_ifu : node _T_7510 = and(_T_7507, _T_7509) @[el2_ifu_bp_ctl.scala 447:81] node _T_7511 = or(_T_7510, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7512 = bits(_T_7511, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7513 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7514 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7515 = eq(_T_7514, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41215,7 +41215,7 @@ circuit el2_ifu : node _T_7519 = and(_T_7516, _T_7518) @[el2_ifu_bp_ctl.scala 447:81] node _T_7520 = or(_T_7519, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7521 = bits(_T_7520, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7522 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7523 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7524 = eq(_T_7523, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41225,7 +41225,7 @@ circuit el2_ifu : node _T_7528 = and(_T_7525, _T_7527) @[el2_ifu_bp_ctl.scala 447:81] node _T_7529 = or(_T_7528, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7530 = bits(_T_7529, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7531 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7532 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7533 = eq(_T_7532, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41235,7 +41235,7 @@ circuit el2_ifu : node _T_7537 = and(_T_7534, _T_7536) @[el2_ifu_bp_ctl.scala 447:81] node _T_7538 = or(_T_7537, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7539 = bits(_T_7538, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7540 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7541 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7542 = eq(_T_7541, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41245,7 +41245,7 @@ circuit el2_ifu : node _T_7546 = and(_T_7543, _T_7545) @[el2_ifu_bp_ctl.scala 447:81] node _T_7547 = or(_T_7546, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7548 = bits(_T_7547, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7549 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7550 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7551 = eq(_T_7550, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41255,7 +41255,7 @@ circuit el2_ifu : node _T_7555 = and(_T_7552, _T_7554) @[el2_ifu_bp_ctl.scala 447:81] node _T_7556 = or(_T_7555, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7557 = bits(_T_7556, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7558 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7559 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7560 = eq(_T_7559, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41265,7 +41265,7 @@ circuit el2_ifu : node _T_7564 = and(_T_7561, _T_7563) @[el2_ifu_bp_ctl.scala 447:81] node _T_7565 = or(_T_7564, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7566 = bits(_T_7565, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7567 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7568 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7569 = eq(_T_7568, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41275,7 +41275,7 @@ circuit el2_ifu : node _T_7573 = and(_T_7570, _T_7572) @[el2_ifu_bp_ctl.scala 447:81] node _T_7574 = or(_T_7573, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7575 = bits(_T_7574, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7576 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7577 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7578 = eq(_T_7577, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41285,7 +41285,7 @@ circuit el2_ifu : node _T_7582 = and(_T_7579, _T_7581) @[el2_ifu_bp_ctl.scala 447:81] node _T_7583 = or(_T_7582, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7584 = bits(_T_7583, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7585 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7586 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7587 = eq(_T_7586, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41295,7 +41295,7 @@ circuit el2_ifu : node _T_7591 = and(_T_7588, _T_7590) @[el2_ifu_bp_ctl.scala 447:81] node _T_7592 = or(_T_7591, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7593 = bits(_T_7592, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7594 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7595 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7596 = eq(_T_7595, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41305,7 +41305,7 @@ circuit el2_ifu : node _T_7600 = and(_T_7597, _T_7599) @[el2_ifu_bp_ctl.scala 447:81] node _T_7601 = or(_T_7600, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7602 = bits(_T_7601, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7603 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7604 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7605 = eq(_T_7604, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41315,7 +41315,7 @@ circuit el2_ifu : node _T_7609 = and(_T_7606, _T_7608) @[el2_ifu_bp_ctl.scala 447:81] node _T_7610 = or(_T_7609, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7611 = bits(_T_7610, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7612 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7613 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7614 = eq(_T_7613, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41325,7 +41325,7 @@ circuit el2_ifu : node _T_7618 = and(_T_7615, _T_7617) @[el2_ifu_bp_ctl.scala 447:81] node _T_7619 = or(_T_7618, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7620 = bits(_T_7619, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7621 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7622 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7623 = eq(_T_7622, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41335,7 +41335,7 @@ circuit el2_ifu : node _T_7627 = and(_T_7624, _T_7626) @[el2_ifu_bp_ctl.scala 447:81] node _T_7628 = or(_T_7627, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7629 = bits(_T_7628, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7630 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7631 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7632 = eq(_T_7631, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41345,7 +41345,7 @@ circuit el2_ifu : node _T_7636 = and(_T_7633, _T_7635) @[el2_ifu_bp_ctl.scala 447:81] node _T_7637 = or(_T_7636, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7638 = bits(_T_7637, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7639 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7640 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7641 = eq(_T_7640, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41355,7 +41355,7 @@ circuit el2_ifu : node _T_7645 = and(_T_7642, _T_7644) @[el2_ifu_bp_ctl.scala 447:81] node _T_7646 = or(_T_7645, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7647 = bits(_T_7646, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7648 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7649 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7650 = eq(_T_7649, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41365,7 +41365,7 @@ circuit el2_ifu : node _T_7654 = and(_T_7651, _T_7653) @[el2_ifu_bp_ctl.scala 447:81] node _T_7655 = or(_T_7654, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7656 = bits(_T_7655, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7657 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7658 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7659 = eq(_T_7658, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41375,7 +41375,7 @@ circuit el2_ifu : node _T_7663 = and(_T_7660, _T_7662) @[el2_ifu_bp_ctl.scala 447:81] node _T_7664 = or(_T_7663, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7665 = bits(_T_7664, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7666 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7667 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7668 = eq(_T_7667, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41385,7 +41385,7 @@ circuit el2_ifu : node _T_7672 = and(_T_7669, _T_7671) @[el2_ifu_bp_ctl.scala 447:81] node _T_7673 = or(_T_7672, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7674 = bits(_T_7673, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7675 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7676 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7677 = eq(_T_7676, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41395,7 +41395,7 @@ circuit el2_ifu : node _T_7681 = and(_T_7678, _T_7680) @[el2_ifu_bp_ctl.scala 447:81] node _T_7682 = or(_T_7681, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7683 = bits(_T_7682, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7684 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7685 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7686 = eq(_T_7685, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41405,7 +41405,7 @@ circuit el2_ifu : node _T_7690 = and(_T_7687, _T_7689) @[el2_ifu_bp_ctl.scala 447:81] node _T_7691 = or(_T_7690, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7692 = bits(_T_7691, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7693 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7694 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7695 = eq(_T_7694, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41415,7 +41415,7 @@ circuit el2_ifu : node _T_7699 = and(_T_7696, _T_7698) @[el2_ifu_bp_ctl.scala 447:81] node _T_7700 = or(_T_7699, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7701 = bits(_T_7700, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7702 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7703 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7704 = eq(_T_7703, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41425,7 +41425,7 @@ circuit el2_ifu : node _T_7708 = and(_T_7705, _T_7707) @[el2_ifu_bp_ctl.scala 447:81] node _T_7709 = or(_T_7708, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7710 = bits(_T_7709, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7711 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7712 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7713 = eq(_T_7712, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41435,7 +41435,7 @@ circuit el2_ifu : node _T_7717 = and(_T_7714, _T_7716) @[el2_ifu_bp_ctl.scala 447:81] node _T_7718 = or(_T_7717, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7719 = bits(_T_7718, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7720 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7721 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7722 = eq(_T_7721, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41445,7 +41445,7 @@ circuit el2_ifu : node _T_7726 = and(_T_7723, _T_7725) @[el2_ifu_bp_ctl.scala 447:81] node _T_7727 = or(_T_7726, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7728 = bits(_T_7727, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7729 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7730 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7731 = eq(_T_7730, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41455,7 +41455,7 @@ circuit el2_ifu : node _T_7735 = and(_T_7732, _T_7734) @[el2_ifu_bp_ctl.scala 447:81] node _T_7736 = or(_T_7735, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7737 = bits(_T_7736, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7738 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7739 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7740 = eq(_T_7739, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41465,7 +41465,7 @@ circuit el2_ifu : node _T_7744 = and(_T_7741, _T_7743) @[el2_ifu_bp_ctl.scala 447:81] node _T_7745 = or(_T_7744, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7746 = bits(_T_7745, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7747 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7748 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7749 = eq(_T_7748, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41475,7 +41475,7 @@ circuit el2_ifu : node _T_7753 = and(_T_7750, _T_7752) @[el2_ifu_bp_ctl.scala 447:81] node _T_7754 = or(_T_7753, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7755 = bits(_T_7754, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7756 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7757 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7758 = eq(_T_7757, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41485,7 +41485,7 @@ circuit el2_ifu : node _T_7762 = and(_T_7759, _T_7761) @[el2_ifu_bp_ctl.scala 447:81] node _T_7763 = or(_T_7762, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7764 = bits(_T_7763, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7765 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7766 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7767 = eq(_T_7766, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41495,7 +41495,7 @@ circuit el2_ifu : node _T_7771 = and(_T_7768, _T_7770) @[el2_ifu_bp_ctl.scala 447:81] node _T_7772 = or(_T_7771, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7773 = bits(_T_7772, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7774 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7775 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7776 = eq(_T_7775, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41505,7 +41505,7 @@ circuit el2_ifu : node _T_7780 = and(_T_7777, _T_7779) @[el2_ifu_bp_ctl.scala 447:81] node _T_7781 = or(_T_7780, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7782 = bits(_T_7781, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7783 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7784 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7785 = eq(_T_7784, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41515,7 +41515,7 @@ circuit el2_ifu : node _T_7789 = and(_T_7786, _T_7788) @[el2_ifu_bp_ctl.scala 447:81] node _T_7790 = or(_T_7789, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7791 = bits(_T_7790, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7792 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7793 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7794 = eq(_T_7793, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41525,7 +41525,7 @@ circuit el2_ifu : node _T_7798 = and(_T_7795, _T_7797) @[el2_ifu_bp_ctl.scala 447:81] node _T_7799 = or(_T_7798, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7800 = bits(_T_7799, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7801 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7802 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7803 = eq(_T_7802, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41535,7 +41535,7 @@ circuit el2_ifu : node _T_7807 = and(_T_7804, _T_7806) @[el2_ifu_bp_ctl.scala 447:81] node _T_7808 = or(_T_7807, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7809 = bits(_T_7808, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7810 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7811 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7812 = eq(_T_7811, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41545,7 +41545,7 @@ circuit el2_ifu : node _T_7816 = and(_T_7813, _T_7815) @[el2_ifu_bp_ctl.scala 447:81] node _T_7817 = or(_T_7816, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7818 = bits(_T_7817, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7819 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7820 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7821 = eq(_T_7820, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41555,7 +41555,7 @@ circuit el2_ifu : node _T_7825 = and(_T_7822, _T_7824) @[el2_ifu_bp_ctl.scala 447:81] node _T_7826 = or(_T_7825, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7827 = bits(_T_7826, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7828 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7829 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7830 = eq(_T_7829, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41565,7 +41565,7 @@ circuit el2_ifu : node _T_7834 = and(_T_7831, _T_7833) @[el2_ifu_bp_ctl.scala 447:81] node _T_7835 = or(_T_7834, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7836 = bits(_T_7835, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7837 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7838 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7839 = eq(_T_7838, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41575,7 +41575,7 @@ circuit el2_ifu : node _T_7843 = and(_T_7840, _T_7842) @[el2_ifu_bp_ctl.scala 447:81] node _T_7844 = or(_T_7843, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7845 = bits(_T_7844, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7846 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7847 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7848 = eq(_T_7847, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41585,7 +41585,7 @@ circuit el2_ifu : node _T_7852 = and(_T_7849, _T_7851) @[el2_ifu_bp_ctl.scala 447:81] node _T_7853 = or(_T_7852, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7854 = bits(_T_7853, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7855 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7856 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7857 = eq(_T_7856, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41595,7 +41595,7 @@ circuit el2_ifu : node _T_7861 = and(_T_7858, _T_7860) @[el2_ifu_bp_ctl.scala 447:81] node _T_7862 = or(_T_7861, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7863 = bits(_T_7862, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7864 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7865 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7866 = eq(_T_7865, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41605,7 +41605,7 @@ circuit el2_ifu : node _T_7870 = and(_T_7867, _T_7869) @[el2_ifu_bp_ctl.scala 447:81] node _T_7871 = or(_T_7870, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7872 = bits(_T_7871, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7873 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7874 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7875 = eq(_T_7874, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41615,7 +41615,7 @@ circuit el2_ifu : node _T_7879 = and(_T_7876, _T_7878) @[el2_ifu_bp_ctl.scala 447:81] node _T_7880 = or(_T_7879, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7881 = bits(_T_7880, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7882 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7883 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7884 = eq(_T_7883, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41625,7 +41625,7 @@ circuit el2_ifu : node _T_7888 = and(_T_7885, _T_7887) @[el2_ifu_bp_ctl.scala 447:81] node _T_7889 = or(_T_7888, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7890 = bits(_T_7889, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7891 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7892 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7893 = eq(_T_7892, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41635,7 +41635,7 @@ circuit el2_ifu : node _T_7897 = and(_T_7894, _T_7896) @[el2_ifu_bp_ctl.scala 447:81] node _T_7898 = or(_T_7897, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7899 = bits(_T_7898, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7900 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7901 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7902 = eq(_T_7901, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41645,7 +41645,7 @@ circuit el2_ifu : node _T_7906 = and(_T_7903, _T_7905) @[el2_ifu_bp_ctl.scala 447:81] node _T_7907 = or(_T_7906, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7908 = bits(_T_7907, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7909 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7910 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7911 = eq(_T_7910, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41655,7 +41655,7 @@ circuit el2_ifu : node _T_7915 = and(_T_7912, _T_7914) @[el2_ifu_bp_ctl.scala 447:81] node _T_7916 = or(_T_7915, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7917 = bits(_T_7916, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7918 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7919 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7920 = eq(_T_7919, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41665,7 +41665,7 @@ circuit el2_ifu : node _T_7924 = and(_T_7921, _T_7923) @[el2_ifu_bp_ctl.scala 447:81] node _T_7925 = or(_T_7924, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7926 = bits(_T_7925, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7927 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7928 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7929 = eq(_T_7928, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41675,7 +41675,7 @@ circuit el2_ifu : node _T_7933 = and(_T_7930, _T_7932) @[el2_ifu_bp_ctl.scala 447:81] node _T_7934 = or(_T_7933, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7935 = bits(_T_7934, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7936 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7937 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7938 = eq(_T_7937, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41685,7 +41685,7 @@ circuit el2_ifu : node _T_7942 = and(_T_7939, _T_7941) @[el2_ifu_bp_ctl.scala 447:81] node _T_7943 = or(_T_7942, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7944 = bits(_T_7943, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7945 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7946 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7947 = eq(_T_7946, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41695,7 +41695,7 @@ circuit el2_ifu : node _T_7951 = and(_T_7948, _T_7950) @[el2_ifu_bp_ctl.scala 447:81] node _T_7952 = or(_T_7951, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7953 = bits(_T_7952, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7954 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7955 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7956 = eq(_T_7955, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41705,7 +41705,7 @@ circuit el2_ifu : node _T_7960 = and(_T_7957, _T_7959) @[el2_ifu_bp_ctl.scala 447:81] node _T_7961 = or(_T_7960, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7962 = bits(_T_7961, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7963 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7964 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7965 = eq(_T_7964, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41715,7 +41715,7 @@ circuit el2_ifu : node _T_7969 = and(_T_7966, _T_7968) @[el2_ifu_bp_ctl.scala 447:81] node _T_7970 = or(_T_7969, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7971 = bits(_T_7970, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7972 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7973 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7974 = eq(_T_7973, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41725,7 +41725,7 @@ circuit el2_ifu : node _T_7978 = and(_T_7975, _T_7977) @[el2_ifu_bp_ctl.scala 447:81] node _T_7979 = or(_T_7978, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7980 = bits(_T_7979, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7981 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7982 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7983 = eq(_T_7982, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41735,7 +41735,7 @@ circuit el2_ifu : node _T_7987 = and(_T_7984, _T_7986) @[el2_ifu_bp_ctl.scala 447:81] node _T_7988 = or(_T_7987, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7989 = bits(_T_7988, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7990 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7991 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7992 = eq(_T_7991, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41745,7 +41745,7 @@ circuit el2_ifu : node _T_7996 = and(_T_7993, _T_7995) @[el2_ifu_bp_ctl.scala 447:81] node _T_7997 = or(_T_7996, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7998 = bits(_T_7997, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7999 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8000 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8001 = eq(_T_8000, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41755,7 +41755,7 @@ circuit el2_ifu : node _T_8005 = and(_T_8002, _T_8004) @[el2_ifu_bp_ctl.scala 447:81] node _T_8006 = or(_T_8005, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8007 = bits(_T_8006, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8008 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8009 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8010 = eq(_T_8009, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41765,7 +41765,7 @@ circuit el2_ifu : node _T_8014 = and(_T_8011, _T_8013) @[el2_ifu_bp_ctl.scala 447:81] node _T_8015 = or(_T_8014, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8016 = bits(_T_8015, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8017 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8018 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8019 = eq(_T_8018, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41775,7 +41775,7 @@ circuit el2_ifu : node _T_8023 = and(_T_8020, _T_8022) @[el2_ifu_bp_ctl.scala 447:81] node _T_8024 = or(_T_8023, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8025 = bits(_T_8024, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8026 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8027 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8028 = eq(_T_8027, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41785,7 +41785,7 @@ circuit el2_ifu : node _T_8032 = and(_T_8029, _T_8031) @[el2_ifu_bp_ctl.scala 447:81] node _T_8033 = or(_T_8032, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8034 = bits(_T_8033, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8035 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8036 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8037 = eq(_T_8036, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41795,7 +41795,7 @@ circuit el2_ifu : node _T_8041 = and(_T_8038, _T_8040) @[el2_ifu_bp_ctl.scala 447:81] node _T_8042 = or(_T_8041, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8043 = bits(_T_8042, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8044 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8045 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8046 = eq(_T_8045, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41805,7 +41805,7 @@ circuit el2_ifu : node _T_8050 = and(_T_8047, _T_8049) @[el2_ifu_bp_ctl.scala 447:81] node _T_8051 = or(_T_8050, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8052 = bits(_T_8051, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8053 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8054 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8055 = eq(_T_8054, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41815,7 +41815,7 @@ circuit el2_ifu : node _T_8059 = and(_T_8056, _T_8058) @[el2_ifu_bp_ctl.scala 447:81] node _T_8060 = or(_T_8059, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8061 = bits(_T_8060, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8062 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8063 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8064 = eq(_T_8063, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41825,7 +41825,7 @@ circuit el2_ifu : node _T_8068 = and(_T_8065, _T_8067) @[el2_ifu_bp_ctl.scala 447:81] node _T_8069 = or(_T_8068, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8070 = bits(_T_8069, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8071 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8072 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8073 = eq(_T_8072, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41835,7 +41835,7 @@ circuit el2_ifu : node _T_8077 = and(_T_8074, _T_8076) @[el2_ifu_bp_ctl.scala 447:81] node _T_8078 = or(_T_8077, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8079 = bits(_T_8078, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8080 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8081 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8082 = eq(_T_8081, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41845,7 +41845,7 @@ circuit el2_ifu : node _T_8086 = and(_T_8083, _T_8085) @[el2_ifu_bp_ctl.scala 447:81] node _T_8087 = or(_T_8086, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8088 = bits(_T_8087, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8089 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8090 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8091 = eq(_T_8090, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41855,7 +41855,7 @@ circuit el2_ifu : node _T_8095 = and(_T_8092, _T_8094) @[el2_ifu_bp_ctl.scala 447:81] node _T_8096 = or(_T_8095, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8097 = bits(_T_8096, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8098 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8099 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8100 = eq(_T_8099, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41865,7 +41865,7 @@ circuit el2_ifu : node _T_8104 = and(_T_8101, _T_8103) @[el2_ifu_bp_ctl.scala 447:81] node _T_8105 = or(_T_8104, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8106 = bits(_T_8105, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8107 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8108 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8109 = eq(_T_8108, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41875,7 +41875,7 @@ circuit el2_ifu : node _T_8113 = and(_T_8110, _T_8112) @[el2_ifu_bp_ctl.scala 447:81] node _T_8114 = or(_T_8113, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8115 = bits(_T_8114, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8116 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8117 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8118 = eq(_T_8117, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41885,7 +41885,7 @@ circuit el2_ifu : node _T_8122 = and(_T_8119, _T_8121) @[el2_ifu_bp_ctl.scala 447:81] node _T_8123 = or(_T_8122, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8124 = bits(_T_8123, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8125 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8126 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8127 = eq(_T_8126, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41895,7 +41895,7 @@ circuit el2_ifu : node _T_8131 = and(_T_8128, _T_8130) @[el2_ifu_bp_ctl.scala 447:81] node _T_8132 = or(_T_8131, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8133 = bits(_T_8132, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8134 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8135 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8136 = eq(_T_8135, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41905,7 +41905,7 @@ circuit el2_ifu : node _T_8140 = and(_T_8137, _T_8139) @[el2_ifu_bp_ctl.scala 447:81] node _T_8141 = or(_T_8140, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8142 = bits(_T_8141, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8143 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8144 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8145 = eq(_T_8144, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41915,7 +41915,7 @@ circuit el2_ifu : node _T_8149 = and(_T_8146, _T_8148) @[el2_ifu_bp_ctl.scala 447:81] node _T_8150 = or(_T_8149, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8151 = bits(_T_8150, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8152 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8153 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8154 = eq(_T_8153, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41925,7 +41925,7 @@ circuit el2_ifu : node _T_8158 = and(_T_8155, _T_8157) @[el2_ifu_bp_ctl.scala 447:81] node _T_8159 = or(_T_8158, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8160 = bits(_T_8159, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8161 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8162 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8163 = eq(_T_8162, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41935,7 +41935,7 @@ circuit el2_ifu : node _T_8167 = and(_T_8164, _T_8166) @[el2_ifu_bp_ctl.scala 447:81] node _T_8168 = or(_T_8167, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8169 = bits(_T_8168, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8170 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8171 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8172 = eq(_T_8171, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41945,7 +41945,7 @@ circuit el2_ifu : node _T_8176 = and(_T_8173, _T_8175) @[el2_ifu_bp_ctl.scala 447:81] node _T_8177 = or(_T_8176, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8178 = bits(_T_8177, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8179 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8180 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8181 = eq(_T_8180, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41955,7 +41955,7 @@ circuit el2_ifu : node _T_8185 = and(_T_8182, _T_8184) @[el2_ifu_bp_ctl.scala 447:81] node _T_8186 = or(_T_8185, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8187 = bits(_T_8186, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8188 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8189 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8190 = eq(_T_8189, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41965,7 +41965,7 @@ circuit el2_ifu : node _T_8194 = and(_T_8191, _T_8193) @[el2_ifu_bp_ctl.scala 447:81] node _T_8195 = or(_T_8194, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8196 = bits(_T_8195, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8197 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8198 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8199 = eq(_T_8198, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41975,7 +41975,7 @@ circuit el2_ifu : node _T_8203 = and(_T_8200, _T_8202) @[el2_ifu_bp_ctl.scala 447:81] node _T_8204 = or(_T_8203, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8205 = bits(_T_8204, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8206 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8207 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8208 = eq(_T_8207, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41985,7 +41985,7 @@ circuit el2_ifu : node _T_8212 = and(_T_8209, _T_8211) @[el2_ifu_bp_ctl.scala 447:81] node _T_8213 = or(_T_8212, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8214 = bits(_T_8213, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8215 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8216 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8217 = eq(_T_8216, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41995,7 +41995,7 @@ circuit el2_ifu : node _T_8221 = and(_T_8218, _T_8220) @[el2_ifu_bp_ctl.scala 447:81] node _T_8222 = or(_T_8221, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8223 = bits(_T_8222, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8224 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8225 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8226 = eq(_T_8225, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42005,7 +42005,7 @@ circuit el2_ifu : node _T_8230 = and(_T_8227, _T_8229) @[el2_ifu_bp_ctl.scala 447:81] node _T_8231 = or(_T_8230, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8232 = bits(_T_8231, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8233 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8234 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8235 = eq(_T_8234, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42015,7 +42015,7 @@ circuit el2_ifu : node _T_8239 = and(_T_8236, _T_8238) @[el2_ifu_bp_ctl.scala 447:81] node _T_8240 = or(_T_8239, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8241 = bits(_T_8240, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8242 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8243 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8244 = eq(_T_8243, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42025,7 +42025,7 @@ circuit el2_ifu : node _T_8248 = and(_T_8245, _T_8247) @[el2_ifu_bp_ctl.scala 447:81] node _T_8249 = or(_T_8248, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8250 = bits(_T_8249, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8251 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8252 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8253 = eq(_T_8252, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42035,7 +42035,7 @@ circuit el2_ifu : node _T_8257 = and(_T_8254, _T_8256) @[el2_ifu_bp_ctl.scala 447:81] node _T_8258 = or(_T_8257, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8259 = bits(_T_8258, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8260 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8261 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8262 = eq(_T_8261, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42045,7 +42045,7 @@ circuit el2_ifu : node _T_8266 = and(_T_8263, _T_8265) @[el2_ifu_bp_ctl.scala 447:81] node _T_8267 = or(_T_8266, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8268 = bits(_T_8267, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8269 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8270 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8271 = eq(_T_8270, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42055,7 +42055,7 @@ circuit el2_ifu : node _T_8275 = and(_T_8272, _T_8274) @[el2_ifu_bp_ctl.scala 447:81] node _T_8276 = or(_T_8275, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8277 = bits(_T_8276, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8278 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8279 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8280 = eq(_T_8279, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42065,7 +42065,7 @@ circuit el2_ifu : node _T_8284 = and(_T_8281, _T_8283) @[el2_ifu_bp_ctl.scala 447:81] node _T_8285 = or(_T_8284, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8286 = bits(_T_8285, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8287 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8288 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8289 = eq(_T_8288, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42075,7 +42075,7 @@ circuit el2_ifu : node _T_8293 = and(_T_8290, _T_8292) @[el2_ifu_bp_ctl.scala 447:81] node _T_8294 = or(_T_8293, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8295 = bits(_T_8294, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8296 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8297 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8298 = eq(_T_8297, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42085,7 +42085,7 @@ circuit el2_ifu : node _T_8302 = and(_T_8299, _T_8301) @[el2_ifu_bp_ctl.scala 447:81] node _T_8303 = or(_T_8302, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8304 = bits(_T_8303, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8305 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8306 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8307 = eq(_T_8306, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42095,7 +42095,7 @@ circuit el2_ifu : node _T_8311 = and(_T_8308, _T_8310) @[el2_ifu_bp_ctl.scala 447:81] node _T_8312 = or(_T_8311, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8313 = bits(_T_8312, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8314 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8315 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8316 = eq(_T_8315, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42105,7 +42105,7 @@ circuit el2_ifu : node _T_8320 = and(_T_8317, _T_8319) @[el2_ifu_bp_ctl.scala 447:81] node _T_8321 = or(_T_8320, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8322 = bits(_T_8321, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8323 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8324 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8325 = eq(_T_8324, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42115,7 +42115,7 @@ circuit el2_ifu : node _T_8329 = and(_T_8326, _T_8328) @[el2_ifu_bp_ctl.scala 447:81] node _T_8330 = or(_T_8329, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8331 = bits(_T_8330, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8332 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8333 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8334 = eq(_T_8333, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42125,7 +42125,7 @@ circuit el2_ifu : node _T_8338 = and(_T_8335, _T_8337) @[el2_ifu_bp_ctl.scala 447:81] node _T_8339 = or(_T_8338, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8340 = bits(_T_8339, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8341 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8342 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8343 = eq(_T_8342, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42135,7 +42135,7 @@ circuit el2_ifu : node _T_8347 = and(_T_8344, _T_8346) @[el2_ifu_bp_ctl.scala 447:81] node _T_8348 = or(_T_8347, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8349 = bits(_T_8348, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8350 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8351 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8352 = eq(_T_8351, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42145,7 +42145,7 @@ circuit el2_ifu : node _T_8356 = and(_T_8353, _T_8355) @[el2_ifu_bp_ctl.scala 447:81] node _T_8357 = or(_T_8356, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8358 = bits(_T_8357, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8359 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8360 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8361 = eq(_T_8360, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42155,7 +42155,7 @@ circuit el2_ifu : node _T_8365 = and(_T_8362, _T_8364) @[el2_ifu_bp_ctl.scala 447:81] node _T_8366 = or(_T_8365, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8367 = bits(_T_8366, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8368 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8369 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8370 = eq(_T_8369, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42165,7 +42165,7 @@ circuit el2_ifu : node _T_8374 = and(_T_8371, _T_8373) @[el2_ifu_bp_ctl.scala 447:81] node _T_8375 = or(_T_8374, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8376 = bits(_T_8375, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8377 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8378 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8379 = eq(_T_8378, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42175,7 +42175,7 @@ circuit el2_ifu : node _T_8383 = and(_T_8380, _T_8382) @[el2_ifu_bp_ctl.scala 447:81] node _T_8384 = or(_T_8383, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8385 = bits(_T_8384, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8386 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8387 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8388 = eq(_T_8387, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42185,7 +42185,7 @@ circuit el2_ifu : node _T_8392 = and(_T_8389, _T_8391) @[el2_ifu_bp_ctl.scala 447:81] node _T_8393 = or(_T_8392, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8394 = bits(_T_8393, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8395 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8396 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8397 = eq(_T_8396, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42195,7 +42195,7 @@ circuit el2_ifu : node _T_8401 = and(_T_8398, _T_8400) @[el2_ifu_bp_ctl.scala 447:81] node _T_8402 = or(_T_8401, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8403 = bits(_T_8402, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8404 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8405 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8406 = eq(_T_8405, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42205,7 +42205,7 @@ circuit el2_ifu : node _T_8410 = and(_T_8407, _T_8409) @[el2_ifu_bp_ctl.scala 447:81] node _T_8411 = or(_T_8410, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8412 = bits(_T_8411, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8413 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8414 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8415 = eq(_T_8414, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42215,7 +42215,7 @@ circuit el2_ifu : node _T_8419 = and(_T_8416, _T_8418) @[el2_ifu_bp_ctl.scala 447:81] node _T_8420 = or(_T_8419, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8421 = bits(_T_8420, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8422 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8423 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8424 = eq(_T_8423, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42225,7 +42225,7 @@ circuit el2_ifu : node _T_8428 = and(_T_8425, _T_8427) @[el2_ifu_bp_ctl.scala 447:81] node _T_8429 = or(_T_8428, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8430 = bits(_T_8429, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8431 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8432 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8433 = eq(_T_8432, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42235,7 +42235,7 @@ circuit el2_ifu : node _T_8437 = and(_T_8434, _T_8436) @[el2_ifu_bp_ctl.scala 447:81] node _T_8438 = or(_T_8437, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8439 = bits(_T_8438, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8440 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8441 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8442 = eq(_T_8441, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42245,7 +42245,7 @@ circuit el2_ifu : node _T_8446 = and(_T_8443, _T_8445) @[el2_ifu_bp_ctl.scala 447:81] node _T_8447 = or(_T_8446, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8448 = bits(_T_8447, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8449 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8450 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8451 = eq(_T_8450, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42255,7 +42255,7 @@ circuit el2_ifu : node _T_8455 = and(_T_8452, _T_8454) @[el2_ifu_bp_ctl.scala 447:81] node _T_8456 = or(_T_8455, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8457 = bits(_T_8456, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8458 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8459 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8460 = eq(_T_8459, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42265,7 +42265,7 @@ circuit el2_ifu : node _T_8464 = and(_T_8461, _T_8463) @[el2_ifu_bp_ctl.scala 447:81] node _T_8465 = or(_T_8464, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8466 = bits(_T_8465, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8467 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8468 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8469 = eq(_T_8468, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42275,7 +42275,7 @@ circuit el2_ifu : node _T_8473 = and(_T_8470, _T_8472) @[el2_ifu_bp_ctl.scala 447:81] node _T_8474 = or(_T_8473, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8475 = bits(_T_8474, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8476 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8477 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8478 = eq(_T_8477, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42285,7 +42285,7 @@ circuit el2_ifu : node _T_8482 = and(_T_8479, _T_8481) @[el2_ifu_bp_ctl.scala 447:81] node _T_8483 = or(_T_8482, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8484 = bits(_T_8483, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8485 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8486 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8487 = eq(_T_8486, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42295,7 +42295,7 @@ circuit el2_ifu : node _T_8491 = and(_T_8488, _T_8490) @[el2_ifu_bp_ctl.scala 447:81] node _T_8492 = or(_T_8491, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8493 = bits(_T_8492, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8494 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8495 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8496 = eq(_T_8495, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42305,7 +42305,7 @@ circuit el2_ifu : node _T_8500 = and(_T_8497, _T_8499) @[el2_ifu_bp_ctl.scala 447:81] node _T_8501 = or(_T_8500, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8502 = bits(_T_8501, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8503 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8504 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8505 = eq(_T_8504, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42315,7 +42315,7 @@ circuit el2_ifu : node _T_8509 = and(_T_8506, _T_8508) @[el2_ifu_bp_ctl.scala 447:81] node _T_8510 = or(_T_8509, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8511 = bits(_T_8510, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8512 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8513 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8514 = eq(_T_8513, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42325,7 +42325,7 @@ circuit el2_ifu : node _T_8518 = and(_T_8515, _T_8517) @[el2_ifu_bp_ctl.scala 447:81] node _T_8519 = or(_T_8518, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8520 = bits(_T_8519, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8521 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8522 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8523 = eq(_T_8522, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42335,7 +42335,7 @@ circuit el2_ifu : node _T_8527 = and(_T_8524, _T_8526) @[el2_ifu_bp_ctl.scala 447:81] node _T_8528 = or(_T_8527, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8529 = bits(_T_8528, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8530 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8531 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8532 = eq(_T_8531, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42345,7 +42345,7 @@ circuit el2_ifu : node _T_8536 = and(_T_8533, _T_8535) @[el2_ifu_bp_ctl.scala 447:81] node _T_8537 = or(_T_8536, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8538 = bits(_T_8537, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8539 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8540 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8541 = eq(_T_8540, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42355,7 +42355,7 @@ circuit el2_ifu : node _T_8545 = and(_T_8542, _T_8544) @[el2_ifu_bp_ctl.scala 447:81] node _T_8546 = or(_T_8545, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8547 = bits(_T_8546, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8548 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8549 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8550 = eq(_T_8549, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42365,7 +42365,7 @@ circuit el2_ifu : node _T_8554 = and(_T_8551, _T_8553) @[el2_ifu_bp_ctl.scala 447:81] node _T_8555 = or(_T_8554, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8556 = bits(_T_8555, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8557 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8558 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8559 = eq(_T_8558, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42375,7 +42375,7 @@ circuit el2_ifu : node _T_8563 = and(_T_8560, _T_8562) @[el2_ifu_bp_ctl.scala 447:81] node _T_8564 = or(_T_8563, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8565 = bits(_T_8564, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8566 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8567 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8568 = eq(_T_8567, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42385,7 +42385,7 @@ circuit el2_ifu : node _T_8572 = and(_T_8569, _T_8571) @[el2_ifu_bp_ctl.scala 447:81] node _T_8573 = or(_T_8572, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8574 = bits(_T_8573, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8575 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8576 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8577 = eq(_T_8576, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42395,7 +42395,7 @@ circuit el2_ifu : node _T_8581 = and(_T_8578, _T_8580) @[el2_ifu_bp_ctl.scala 447:81] node _T_8582 = or(_T_8581, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8583 = bits(_T_8582, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8584 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8585 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8586 = eq(_T_8585, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42405,7 +42405,7 @@ circuit el2_ifu : node _T_8590 = and(_T_8587, _T_8589) @[el2_ifu_bp_ctl.scala 447:81] node _T_8591 = or(_T_8590, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8592 = bits(_T_8591, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8593 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8594 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8595 = eq(_T_8594, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42415,7 +42415,7 @@ circuit el2_ifu : node _T_8599 = and(_T_8596, _T_8598) @[el2_ifu_bp_ctl.scala 447:81] node _T_8600 = or(_T_8599, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8601 = bits(_T_8600, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8602 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8603 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8604 = eq(_T_8603, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42425,7 +42425,7 @@ circuit el2_ifu : node _T_8608 = and(_T_8605, _T_8607) @[el2_ifu_bp_ctl.scala 447:81] node _T_8609 = or(_T_8608, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8610 = bits(_T_8609, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8611 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8612 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8613 = eq(_T_8612, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42435,7 +42435,7 @@ circuit el2_ifu : node _T_8617 = and(_T_8614, _T_8616) @[el2_ifu_bp_ctl.scala 447:81] node _T_8618 = or(_T_8617, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8619 = bits(_T_8618, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8620 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8621 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8622 = eq(_T_8621, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42445,7 +42445,7 @@ circuit el2_ifu : node _T_8626 = and(_T_8623, _T_8625) @[el2_ifu_bp_ctl.scala 447:81] node _T_8627 = or(_T_8626, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8628 = bits(_T_8627, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8629 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8630 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8631 = eq(_T_8630, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42455,7 +42455,7 @@ circuit el2_ifu : node _T_8635 = and(_T_8632, _T_8634) @[el2_ifu_bp_ctl.scala 447:81] node _T_8636 = or(_T_8635, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8637 = bits(_T_8636, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8638 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8639 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8640 = eq(_T_8639, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42465,7 +42465,7 @@ circuit el2_ifu : node _T_8644 = and(_T_8641, _T_8643) @[el2_ifu_bp_ctl.scala 447:81] node _T_8645 = or(_T_8644, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8646 = bits(_T_8645, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8647 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8648 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8649 = eq(_T_8648, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42475,7 +42475,7 @@ circuit el2_ifu : node _T_8653 = and(_T_8650, _T_8652) @[el2_ifu_bp_ctl.scala 447:81] node _T_8654 = or(_T_8653, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8655 = bits(_T_8654, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8656 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8657 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8658 = eq(_T_8657, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42485,7 +42485,7 @@ circuit el2_ifu : node _T_8662 = and(_T_8659, _T_8661) @[el2_ifu_bp_ctl.scala 447:81] node _T_8663 = or(_T_8662, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8664 = bits(_T_8663, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8665 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8666 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8667 = eq(_T_8666, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42495,7 +42495,7 @@ circuit el2_ifu : node _T_8671 = and(_T_8668, _T_8670) @[el2_ifu_bp_ctl.scala 447:81] node _T_8672 = or(_T_8671, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8673 = bits(_T_8672, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8674 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8675 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8676 = eq(_T_8675, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42505,7 +42505,7 @@ circuit el2_ifu : node _T_8680 = and(_T_8677, _T_8679) @[el2_ifu_bp_ctl.scala 447:81] node _T_8681 = or(_T_8680, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8682 = bits(_T_8681, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8683 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8684 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8685 = eq(_T_8684, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42515,7 +42515,7 @@ circuit el2_ifu : node _T_8689 = and(_T_8686, _T_8688) @[el2_ifu_bp_ctl.scala 447:81] node _T_8690 = or(_T_8689, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8691 = bits(_T_8690, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8692 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8693 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8694 = eq(_T_8693, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42525,7 +42525,7 @@ circuit el2_ifu : node _T_8698 = and(_T_8695, _T_8697) @[el2_ifu_bp_ctl.scala 447:81] node _T_8699 = or(_T_8698, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8700 = bits(_T_8699, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8701 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8702 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8703 = eq(_T_8702, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42535,7 +42535,7 @@ circuit el2_ifu : node _T_8707 = and(_T_8704, _T_8706) @[el2_ifu_bp_ctl.scala 447:81] node _T_8708 = or(_T_8707, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8709 = bits(_T_8708, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8710 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8711 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8712 = eq(_T_8711, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42545,7 +42545,7 @@ circuit el2_ifu : node _T_8716 = and(_T_8713, _T_8715) @[el2_ifu_bp_ctl.scala 447:81] node _T_8717 = or(_T_8716, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8718 = bits(_T_8717, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8719 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8720 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8721 = eq(_T_8720, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42555,7 +42555,7 @@ circuit el2_ifu : node _T_8725 = and(_T_8722, _T_8724) @[el2_ifu_bp_ctl.scala 447:81] node _T_8726 = or(_T_8725, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8727 = bits(_T_8726, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8728 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8729 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8730 = eq(_T_8729, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42565,7 +42565,7 @@ circuit el2_ifu : node _T_8734 = and(_T_8731, _T_8733) @[el2_ifu_bp_ctl.scala 447:81] node _T_8735 = or(_T_8734, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8736 = bits(_T_8735, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8737 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8738 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8739 = eq(_T_8738, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42575,7 +42575,7 @@ circuit el2_ifu : node _T_8743 = and(_T_8740, _T_8742) @[el2_ifu_bp_ctl.scala 447:81] node _T_8744 = or(_T_8743, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8745 = bits(_T_8744, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8746 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8747 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8748 = eq(_T_8747, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42585,7 +42585,7 @@ circuit el2_ifu : node _T_8752 = and(_T_8749, _T_8751) @[el2_ifu_bp_ctl.scala 447:81] node _T_8753 = or(_T_8752, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8754 = bits(_T_8753, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8755 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8756 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8757 = eq(_T_8756, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42595,7 +42595,7 @@ circuit el2_ifu : node _T_8761 = and(_T_8758, _T_8760) @[el2_ifu_bp_ctl.scala 447:81] node _T_8762 = or(_T_8761, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8763 = bits(_T_8762, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8764 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8765 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8766 = eq(_T_8765, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42605,7 +42605,7 @@ circuit el2_ifu : node _T_8770 = and(_T_8767, _T_8769) @[el2_ifu_bp_ctl.scala 447:81] node _T_8771 = or(_T_8770, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8772 = bits(_T_8771, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8773 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8774 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8775 = eq(_T_8774, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42615,7 +42615,7 @@ circuit el2_ifu : node _T_8779 = and(_T_8776, _T_8778) @[el2_ifu_bp_ctl.scala 447:81] node _T_8780 = or(_T_8779, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8781 = bits(_T_8780, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8782 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8783 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8784 = eq(_T_8783, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42625,7 +42625,7 @@ circuit el2_ifu : node _T_8788 = and(_T_8785, _T_8787) @[el2_ifu_bp_ctl.scala 447:81] node _T_8789 = or(_T_8788, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8790 = bits(_T_8789, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8791 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8792 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8793 = eq(_T_8792, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42635,7 +42635,7 @@ circuit el2_ifu : node _T_8797 = and(_T_8794, _T_8796) @[el2_ifu_bp_ctl.scala 447:81] node _T_8798 = or(_T_8797, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8799 = bits(_T_8798, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8800 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8801 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8802 = eq(_T_8801, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42645,7 +42645,7 @@ circuit el2_ifu : node _T_8806 = and(_T_8803, _T_8805) @[el2_ifu_bp_ctl.scala 447:81] node _T_8807 = or(_T_8806, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8808 = bits(_T_8807, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8809 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8810 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8811 = eq(_T_8810, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42655,7 +42655,7 @@ circuit el2_ifu : node _T_8815 = and(_T_8812, _T_8814) @[el2_ifu_bp_ctl.scala 447:81] node _T_8816 = or(_T_8815, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8817 = bits(_T_8816, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8818 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8819 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8820 = eq(_T_8819, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42665,7 +42665,7 @@ circuit el2_ifu : node _T_8824 = and(_T_8821, _T_8823) @[el2_ifu_bp_ctl.scala 447:81] node _T_8825 = or(_T_8824, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8826 = bits(_T_8825, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8827 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8828 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8829 = eq(_T_8828, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42675,7 +42675,7 @@ circuit el2_ifu : node _T_8833 = and(_T_8830, _T_8832) @[el2_ifu_bp_ctl.scala 447:81] node _T_8834 = or(_T_8833, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8835 = bits(_T_8834, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8836 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8837 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8838 = eq(_T_8837, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42685,7 +42685,7 @@ circuit el2_ifu : node _T_8842 = and(_T_8839, _T_8841) @[el2_ifu_bp_ctl.scala 447:81] node _T_8843 = or(_T_8842, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8844 = bits(_T_8843, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8845 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8846 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8847 = eq(_T_8846, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42695,7 +42695,7 @@ circuit el2_ifu : node _T_8851 = and(_T_8848, _T_8850) @[el2_ifu_bp_ctl.scala 447:81] node _T_8852 = or(_T_8851, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8853 = bits(_T_8852, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8854 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8855 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8856 = eq(_T_8855, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42705,7 +42705,7 @@ circuit el2_ifu : node _T_8860 = and(_T_8857, _T_8859) @[el2_ifu_bp_ctl.scala 447:81] node _T_8861 = or(_T_8860, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8862 = bits(_T_8861, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8863 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8864 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8865 = eq(_T_8864, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42715,7 +42715,7 @@ circuit el2_ifu : node _T_8869 = and(_T_8866, _T_8868) @[el2_ifu_bp_ctl.scala 447:81] node _T_8870 = or(_T_8869, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8871 = bits(_T_8870, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8872 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8873 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8874 = eq(_T_8873, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42725,7 +42725,7 @@ circuit el2_ifu : node _T_8878 = and(_T_8875, _T_8877) @[el2_ifu_bp_ctl.scala 447:81] node _T_8879 = or(_T_8878, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8880 = bits(_T_8879, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8881 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8882 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8883 = eq(_T_8882, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42735,7 +42735,7 @@ circuit el2_ifu : node _T_8887 = and(_T_8884, _T_8886) @[el2_ifu_bp_ctl.scala 447:81] node _T_8888 = or(_T_8887, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8889 = bits(_T_8888, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8890 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8891 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8892 = eq(_T_8891, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42745,7 +42745,7 @@ circuit el2_ifu : node _T_8896 = and(_T_8893, _T_8895) @[el2_ifu_bp_ctl.scala 447:81] node _T_8897 = or(_T_8896, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8898 = bits(_T_8897, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8899 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8900 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8901 = eq(_T_8900, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42755,7 +42755,7 @@ circuit el2_ifu : node _T_8905 = and(_T_8902, _T_8904) @[el2_ifu_bp_ctl.scala 447:81] node _T_8906 = or(_T_8905, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8907 = bits(_T_8906, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8908 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8909 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8910 = eq(_T_8909, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42765,7 +42765,7 @@ circuit el2_ifu : node _T_8914 = and(_T_8911, _T_8913) @[el2_ifu_bp_ctl.scala 447:81] node _T_8915 = or(_T_8914, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8916 = bits(_T_8915, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8917 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8918 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8919 = eq(_T_8918, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42775,7 +42775,7 @@ circuit el2_ifu : node _T_8923 = and(_T_8920, _T_8922) @[el2_ifu_bp_ctl.scala 447:81] node _T_8924 = or(_T_8923, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8925 = bits(_T_8924, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8926 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8927 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8928 = eq(_T_8927, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42785,7 +42785,7 @@ circuit el2_ifu : node _T_8932 = and(_T_8929, _T_8931) @[el2_ifu_bp_ctl.scala 447:81] node _T_8933 = or(_T_8932, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8934 = bits(_T_8933, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8935 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8936 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8937 = eq(_T_8936, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42795,7 +42795,7 @@ circuit el2_ifu : node _T_8941 = and(_T_8938, _T_8940) @[el2_ifu_bp_ctl.scala 447:81] node _T_8942 = or(_T_8941, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8943 = bits(_T_8942, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8944 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8945 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8946 = eq(_T_8945, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42805,7 +42805,7 @@ circuit el2_ifu : node _T_8950 = and(_T_8947, _T_8949) @[el2_ifu_bp_ctl.scala 447:81] node _T_8951 = or(_T_8950, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8952 = bits(_T_8951, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8953 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8954 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8955 = eq(_T_8954, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42815,7 +42815,7 @@ circuit el2_ifu : node _T_8959 = and(_T_8956, _T_8958) @[el2_ifu_bp_ctl.scala 447:81] node _T_8960 = or(_T_8959, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8961 = bits(_T_8960, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8962 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8963 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8964 = eq(_T_8963, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42825,7 +42825,7 @@ circuit el2_ifu : node _T_8968 = and(_T_8965, _T_8967) @[el2_ifu_bp_ctl.scala 447:81] node _T_8969 = or(_T_8968, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8970 = bits(_T_8969, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8971 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8972 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8973 = eq(_T_8972, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42835,7 +42835,7 @@ circuit el2_ifu : node _T_8977 = and(_T_8974, _T_8976) @[el2_ifu_bp_ctl.scala 447:81] node _T_8978 = or(_T_8977, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8979 = bits(_T_8978, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8980 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8981 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8982 = eq(_T_8981, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42845,7 +42845,7 @@ circuit el2_ifu : node _T_8986 = and(_T_8983, _T_8985) @[el2_ifu_bp_ctl.scala 447:81] node _T_8987 = or(_T_8986, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8988 = bits(_T_8987, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8989 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8990 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8991 = eq(_T_8990, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42855,7 +42855,7 @@ circuit el2_ifu : node _T_8995 = and(_T_8992, _T_8994) @[el2_ifu_bp_ctl.scala 447:81] node _T_8996 = or(_T_8995, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8997 = bits(_T_8996, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8998 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8999 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9000 = eq(_T_8999, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42865,7 +42865,7 @@ circuit el2_ifu : node _T_9004 = and(_T_9001, _T_9003) @[el2_ifu_bp_ctl.scala 447:81] node _T_9005 = or(_T_9004, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9006 = bits(_T_9005, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9007 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9008 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9009 = eq(_T_9008, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42875,7 +42875,7 @@ circuit el2_ifu : node _T_9013 = and(_T_9010, _T_9012) @[el2_ifu_bp_ctl.scala 447:81] node _T_9014 = or(_T_9013, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9015 = bits(_T_9014, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9016 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9017 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9018 = eq(_T_9017, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42885,7 +42885,7 @@ circuit el2_ifu : node _T_9022 = and(_T_9019, _T_9021) @[el2_ifu_bp_ctl.scala 447:81] node _T_9023 = or(_T_9022, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9024 = bits(_T_9023, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9025 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9026 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9027 = eq(_T_9026, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42895,7 +42895,7 @@ circuit el2_ifu : node _T_9031 = and(_T_9028, _T_9030) @[el2_ifu_bp_ctl.scala 447:81] node _T_9032 = or(_T_9031, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9033 = bits(_T_9032, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9034 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9035 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9036 = eq(_T_9035, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42905,7 +42905,7 @@ circuit el2_ifu : node _T_9040 = and(_T_9037, _T_9039) @[el2_ifu_bp_ctl.scala 447:81] node _T_9041 = or(_T_9040, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9042 = bits(_T_9041, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9043 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9044 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9045 = eq(_T_9044, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42915,7 +42915,7 @@ circuit el2_ifu : node _T_9049 = and(_T_9046, _T_9048) @[el2_ifu_bp_ctl.scala 447:81] node _T_9050 = or(_T_9049, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9051 = bits(_T_9050, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9052 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9053 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9054 = eq(_T_9053, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42925,7 +42925,7 @@ circuit el2_ifu : node _T_9058 = and(_T_9055, _T_9057) @[el2_ifu_bp_ctl.scala 447:81] node _T_9059 = or(_T_9058, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9060 = bits(_T_9059, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9061 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9062 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9063 = eq(_T_9062, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42935,7 +42935,7 @@ circuit el2_ifu : node _T_9067 = and(_T_9064, _T_9066) @[el2_ifu_bp_ctl.scala 447:81] node _T_9068 = or(_T_9067, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9069 = bits(_T_9068, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9070 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9071 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9072 = eq(_T_9071, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42945,7 +42945,7 @@ circuit el2_ifu : node _T_9076 = and(_T_9073, _T_9075) @[el2_ifu_bp_ctl.scala 447:81] node _T_9077 = or(_T_9076, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9078 = bits(_T_9077, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9079 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9080 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9081 = eq(_T_9080, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42955,7 +42955,7 @@ circuit el2_ifu : node _T_9085 = and(_T_9082, _T_9084) @[el2_ifu_bp_ctl.scala 447:81] node _T_9086 = or(_T_9085, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9087 = bits(_T_9086, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9088 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9089 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9090 = eq(_T_9089, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42965,7 +42965,7 @@ circuit el2_ifu : node _T_9094 = and(_T_9091, _T_9093) @[el2_ifu_bp_ctl.scala 447:81] node _T_9095 = or(_T_9094, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9096 = bits(_T_9095, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9097 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9098 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9099 = eq(_T_9098, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42975,7 +42975,7 @@ circuit el2_ifu : node _T_9103 = and(_T_9100, _T_9102) @[el2_ifu_bp_ctl.scala 447:81] node _T_9104 = or(_T_9103, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9105 = bits(_T_9104, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9106 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9107 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9108 = eq(_T_9107, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42985,7 +42985,7 @@ circuit el2_ifu : node _T_9112 = and(_T_9109, _T_9111) @[el2_ifu_bp_ctl.scala 447:81] node _T_9113 = or(_T_9112, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9114 = bits(_T_9113, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9115 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9116 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9117 = eq(_T_9116, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42995,7 +42995,7 @@ circuit el2_ifu : node _T_9121 = and(_T_9118, _T_9120) @[el2_ifu_bp_ctl.scala 447:81] node _T_9122 = or(_T_9121, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9123 = bits(_T_9122, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9124 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9125 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9126 = eq(_T_9125, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43005,7 +43005,7 @@ circuit el2_ifu : node _T_9130 = and(_T_9127, _T_9129) @[el2_ifu_bp_ctl.scala 447:81] node _T_9131 = or(_T_9130, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9132 = bits(_T_9131, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9133 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9134 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9135 = eq(_T_9134, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43015,7 +43015,7 @@ circuit el2_ifu : node _T_9139 = and(_T_9136, _T_9138) @[el2_ifu_bp_ctl.scala 447:81] node _T_9140 = or(_T_9139, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9141 = bits(_T_9140, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9142 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9143 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9144 = eq(_T_9143, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43025,7 +43025,7 @@ circuit el2_ifu : node _T_9148 = and(_T_9145, _T_9147) @[el2_ifu_bp_ctl.scala 447:81] node _T_9149 = or(_T_9148, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9150 = bits(_T_9149, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9151 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9152 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9153 = eq(_T_9152, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43035,7 +43035,7 @@ circuit el2_ifu : node _T_9157 = and(_T_9154, _T_9156) @[el2_ifu_bp_ctl.scala 447:81] node _T_9158 = or(_T_9157, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9159 = bits(_T_9158, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9160 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9161 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9162 = eq(_T_9161, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43045,7 +43045,7 @@ circuit el2_ifu : node _T_9166 = and(_T_9163, _T_9165) @[el2_ifu_bp_ctl.scala 447:81] node _T_9167 = or(_T_9166, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9168 = bits(_T_9167, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9169 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9170 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9171 = eq(_T_9170, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43055,7 +43055,7 @@ circuit el2_ifu : node _T_9175 = and(_T_9172, _T_9174) @[el2_ifu_bp_ctl.scala 447:81] node _T_9176 = or(_T_9175, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9177 = bits(_T_9176, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9178 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9179 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9180 = eq(_T_9179, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43065,7 +43065,7 @@ circuit el2_ifu : node _T_9184 = and(_T_9181, _T_9183) @[el2_ifu_bp_ctl.scala 447:81] node _T_9185 = or(_T_9184, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9186 = bits(_T_9185, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9187 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9188 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9189 = eq(_T_9188, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43075,7 +43075,7 @@ circuit el2_ifu : node _T_9193 = and(_T_9190, _T_9192) @[el2_ifu_bp_ctl.scala 447:81] node _T_9194 = or(_T_9193, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9195 = bits(_T_9194, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9196 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9197 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9198 = eq(_T_9197, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43085,7 +43085,7 @@ circuit el2_ifu : node _T_9202 = and(_T_9199, _T_9201) @[el2_ifu_bp_ctl.scala 447:81] node _T_9203 = or(_T_9202, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9204 = bits(_T_9203, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9205 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9206 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9207 = eq(_T_9206, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43095,7 +43095,7 @@ circuit el2_ifu : node _T_9211 = and(_T_9208, _T_9210) @[el2_ifu_bp_ctl.scala 447:81] node _T_9212 = or(_T_9211, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9213 = bits(_T_9212, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9214 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9215 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9216 = eq(_T_9215, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43105,7 +43105,7 @@ circuit el2_ifu : node _T_9220 = and(_T_9217, _T_9219) @[el2_ifu_bp_ctl.scala 447:81] node _T_9221 = or(_T_9220, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9222 = bits(_T_9221, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9223 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9224 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9225 = eq(_T_9224, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43115,7 +43115,7 @@ circuit el2_ifu : node _T_9229 = and(_T_9226, _T_9228) @[el2_ifu_bp_ctl.scala 447:81] node _T_9230 = or(_T_9229, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9231 = bits(_T_9230, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9232 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9233 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9234 = eq(_T_9233, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43125,7 +43125,7 @@ circuit el2_ifu : node _T_9238 = and(_T_9235, _T_9237) @[el2_ifu_bp_ctl.scala 447:81] node _T_9239 = or(_T_9238, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9240 = bits(_T_9239, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9241 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9242 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9243 = eq(_T_9242, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43135,7 +43135,7 @@ circuit el2_ifu : node _T_9247 = and(_T_9244, _T_9246) @[el2_ifu_bp_ctl.scala 447:81] node _T_9248 = or(_T_9247, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9249 = bits(_T_9248, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9250 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9251 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9252 = eq(_T_9251, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43145,7 +43145,7 @@ circuit el2_ifu : node _T_9256 = and(_T_9253, _T_9255) @[el2_ifu_bp_ctl.scala 447:81] node _T_9257 = or(_T_9256, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9258 = bits(_T_9257, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9259 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9260 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9261 = eq(_T_9260, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43155,7 +43155,7 @@ circuit el2_ifu : node _T_9265 = and(_T_9262, _T_9264) @[el2_ifu_bp_ctl.scala 447:81] node _T_9266 = or(_T_9265, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9267 = bits(_T_9266, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9268 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9269 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9270 = eq(_T_9269, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43165,7 +43165,7 @@ circuit el2_ifu : node _T_9274 = and(_T_9271, _T_9273) @[el2_ifu_bp_ctl.scala 447:81] node _T_9275 = or(_T_9274, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9276 = bits(_T_9275, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9277 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9278 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9279 = eq(_T_9278, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43175,7 +43175,7 @@ circuit el2_ifu : node _T_9283 = and(_T_9280, _T_9282) @[el2_ifu_bp_ctl.scala 447:81] node _T_9284 = or(_T_9283, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9285 = bits(_T_9284, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9286 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9287 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9288 = eq(_T_9287, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43185,7 +43185,7 @@ circuit el2_ifu : node _T_9292 = and(_T_9289, _T_9291) @[el2_ifu_bp_ctl.scala 447:81] node _T_9293 = or(_T_9292, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9294 = bits(_T_9293, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9295 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9296 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9297 = eq(_T_9296, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43195,7 +43195,7 @@ circuit el2_ifu : node _T_9301 = and(_T_9298, _T_9300) @[el2_ifu_bp_ctl.scala 447:81] node _T_9302 = or(_T_9301, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9303 = bits(_T_9302, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9304 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9305 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9306 = eq(_T_9305, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43205,7 +43205,7 @@ circuit el2_ifu : node _T_9310 = and(_T_9307, _T_9309) @[el2_ifu_bp_ctl.scala 447:81] node _T_9311 = or(_T_9310, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9312 = bits(_T_9311, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9313 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9314 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9315 = eq(_T_9314, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43215,7 +43215,7 @@ circuit el2_ifu : node _T_9319 = and(_T_9316, _T_9318) @[el2_ifu_bp_ctl.scala 447:81] node _T_9320 = or(_T_9319, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9321 = bits(_T_9320, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9322 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9323 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9324 = eq(_T_9323, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43225,7 +43225,7 @@ circuit el2_ifu : node _T_9328 = and(_T_9325, _T_9327) @[el2_ifu_bp_ctl.scala 447:81] node _T_9329 = or(_T_9328, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9330 = bits(_T_9329, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9331 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9332 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9333 = eq(_T_9332, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43235,7 +43235,7 @@ circuit el2_ifu : node _T_9337 = and(_T_9334, _T_9336) @[el2_ifu_bp_ctl.scala 447:81] node _T_9338 = or(_T_9337, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9339 = bits(_T_9338, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9340 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9341 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9342 = eq(_T_9341, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43245,7 +43245,7 @@ circuit el2_ifu : node _T_9346 = and(_T_9343, _T_9345) @[el2_ifu_bp_ctl.scala 447:81] node _T_9347 = or(_T_9346, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9348 = bits(_T_9347, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9349 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9350 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9351 = eq(_T_9350, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43255,7 +43255,7 @@ circuit el2_ifu : node _T_9355 = and(_T_9352, _T_9354) @[el2_ifu_bp_ctl.scala 447:81] node _T_9356 = or(_T_9355, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9357 = bits(_T_9356, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9358 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9359 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9360 = eq(_T_9359, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43265,7 +43265,7 @@ circuit el2_ifu : node _T_9364 = and(_T_9361, _T_9363) @[el2_ifu_bp_ctl.scala 447:81] node _T_9365 = or(_T_9364, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9366 = bits(_T_9365, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9367 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9368 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9369 = eq(_T_9368, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43275,7 +43275,7 @@ circuit el2_ifu : node _T_9373 = and(_T_9370, _T_9372) @[el2_ifu_bp_ctl.scala 447:81] node _T_9374 = or(_T_9373, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9375 = bits(_T_9374, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9376 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9377 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9378 = eq(_T_9377, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43285,7 +43285,7 @@ circuit el2_ifu : node _T_9382 = and(_T_9379, _T_9381) @[el2_ifu_bp_ctl.scala 447:81] node _T_9383 = or(_T_9382, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9384 = bits(_T_9383, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9385 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9386 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9387 = eq(_T_9386, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43295,7 +43295,7 @@ circuit el2_ifu : node _T_9391 = and(_T_9388, _T_9390) @[el2_ifu_bp_ctl.scala 447:81] node _T_9392 = or(_T_9391, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9393 = bits(_T_9392, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9394 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9395 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9396 = eq(_T_9395, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43305,7 +43305,7 @@ circuit el2_ifu : node _T_9400 = and(_T_9397, _T_9399) @[el2_ifu_bp_ctl.scala 447:81] node _T_9401 = or(_T_9400, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9402 = bits(_T_9401, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9403 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9404 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9405 = eq(_T_9404, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43315,7 +43315,7 @@ circuit el2_ifu : node _T_9409 = and(_T_9406, _T_9408) @[el2_ifu_bp_ctl.scala 447:81] node _T_9410 = or(_T_9409, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9411 = bits(_T_9410, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9412 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9413 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9414 = eq(_T_9413, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43325,7 +43325,7 @@ circuit el2_ifu : node _T_9418 = and(_T_9415, _T_9417) @[el2_ifu_bp_ctl.scala 447:81] node _T_9419 = or(_T_9418, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9420 = bits(_T_9419, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9421 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9422 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9423 = eq(_T_9422, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43335,7 +43335,7 @@ circuit el2_ifu : node _T_9427 = and(_T_9424, _T_9426) @[el2_ifu_bp_ctl.scala 447:81] node _T_9428 = or(_T_9427, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9429 = bits(_T_9428, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9430 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9431 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9432 = eq(_T_9431, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43345,7 +43345,7 @@ circuit el2_ifu : node _T_9436 = and(_T_9433, _T_9435) @[el2_ifu_bp_ctl.scala 447:81] node _T_9437 = or(_T_9436, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9438 = bits(_T_9437, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9439 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9440 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9441 = eq(_T_9440, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43355,7 +43355,7 @@ circuit el2_ifu : node _T_9445 = and(_T_9442, _T_9444) @[el2_ifu_bp_ctl.scala 447:81] node _T_9446 = or(_T_9445, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9447 = bits(_T_9446, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9448 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9449 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9450 = eq(_T_9449, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43365,7 +43365,7 @@ circuit el2_ifu : node _T_9454 = and(_T_9451, _T_9453) @[el2_ifu_bp_ctl.scala 447:81] node _T_9455 = or(_T_9454, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9456 = bits(_T_9455, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9457 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9458 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9459 = eq(_T_9458, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43375,7 +43375,7 @@ circuit el2_ifu : node _T_9463 = and(_T_9460, _T_9462) @[el2_ifu_bp_ctl.scala 447:81] node _T_9464 = or(_T_9463, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9465 = bits(_T_9464, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9466 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9467 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9468 = eq(_T_9467, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43385,7 +43385,7 @@ circuit el2_ifu : node _T_9472 = and(_T_9469, _T_9471) @[el2_ifu_bp_ctl.scala 447:81] node _T_9473 = or(_T_9472, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9474 = bits(_T_9473, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9475 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9476 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9477 = eq(_T_9476, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43395,7 +43395,7 @@ circuit el2_ifu : node _T_9481 = and(_T_9478, _T_9480) @[el2_ifu_bp_ctl.scala 447:81] node _T_9482 = or(_T_9481, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9483 = bits(_T_9482, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9484 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9485 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9486 = eq(_T_9485, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43405,7 +43405,7 @@ circuit el2_ifu : node _T_9490 = and(_T_9487, _T_9489) @[el2_ifu_bp_ctl.scala 447:81] node _T_9491 = or(_T_9490, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9492 = bits(_T_9491, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9493 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9494 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9495 = eq(_T_9494, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43415,7 +43415,7 @@ circuit el2_ifu : node _T_9499 = and(_T_9496, _T_9498) @[el2_ifu_bp_ctl.scala 447:81] node _T_9500 = or(_T_9499, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9501 = bits(_T_9500, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9502 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9503 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9504 = eq(_T_9503, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43425,7 +43425,7 @@ circuit el2_ifu : node _T_9508 = and(_T_9505, _T_9507) @[el2_ifu_bp_ctl.scala 447:81] node _T_9509 = or(_T_9508, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9510 = bits(_T_9509, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9511 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9512 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9513 = eq(_T_9512, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43435,7 +43435,7 @@ circuit el2_ifu : node _T_9517 = and(_T_9514, _T_9516) @[el2_ifu_bp_ctl.scala 447:81] node _T_9518 = or(_T_9517, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9519 = bits(_T_9518, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9520 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9521 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9522 = eq(_T_9521, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43445,7 +43445,7 @@ circuit el2_ifu : node _T_9526 = and(_T_9523, _T_9525) @[el2_ifu_bp_ctl.scala 447:81] node _T_9527 = or(_T_9526, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9528 = bits(_T_9527, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9529 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9530 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9531 = eq(_T_9530, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43455,7 +43455,7 @@ circuit el2_ifu : node _T_9535 = and(_T_9532, _T_9534) @[el2_ifu_bp_ctl.scala 447:81] node _T_9536 = or(_T_9535, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9537 = bits(_T_9536, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9538 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9539 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9540 = eq(_T_9539, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43465,7 +43465,7 @@ circuit el2_ifu : node _T_9544 = and(_T_9541, _T_9543) @[el2_ifu_bp_ctl.scala 447:81] node _T_9545 = or(_T_9544, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9546 = bits(_T_9545, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9547 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9548 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9549 = eq(_T_9548, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43475,7 +43475,7 @@ circuit el2_ifu : node _T_9553 = and(_T_9550, _T_9552) @[el2_ifu_bp_ctl.scala 447:81] node _T_9554 = or(_T_9553, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9555 = bits(_T_9554, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9556 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9557 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9558 = eq(_T_9557, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43485,7 +43485,7 @@ circuit el2_ifu : node _T_9562 = and(_T_9559, _T_9561) @[el2_ifu_bp_ctl.scala 447:81] node _T_9563 = or(_T_9562, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9564 = bits(_T_9563, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9565 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9566 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9567 = eq(_T_9566, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43495,7 +43495,7 @@ circuit el2_ifu : node _T_9571 = and(_T_9568, _T_9570) @[el2_ifu_bp_ctl.scala 447:81] node _T_9572 = or(_T_9571, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9573 = bits(_T_9572, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9574 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9575 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9576 = eq(_T_9575, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43505,7 +43505,7 @@ circuit el2_ifu : node _T_9580 = and(_T_9577, _T_9579) @[el2_ifu_bp_ctl.scala 447:81] node _T_9581 = or(_T_9580, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9582 = bits(_T_9581, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9583 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9584 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9585 = eq(_T_9584, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43515,7 +43515,7 @@ circuit el2_ifu : node _T_9589 = and(_T_9586, _T_9588) @[el2_ifu_bp_ctl.scala 447:81] node _T_9590 = or(_T_9589, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9591 = bits(_T_9590, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9592 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9593 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9594 = eq(_T_9593, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43525,7 +43525,7 @@ circuit el2_ifu : node _T_9598 = and(_T_9595, _T_9597) @[el2_ifu_bp_ctl.scala 447:81] node _T_9599 = or(_T_9598, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9600 = bits(_T_9599, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9601 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9602 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9603 = eq(_T_9602, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43535,7 +43535,7 @@ circuit el2_ifu : node _T_9607 = and(_T_9604, _T_9606) @[el2_ifu_bp_ctl.scala 447:81] node _T_9608 = or(_T_9607, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9609 = bits(_T_9608, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9610 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9611 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9612 = eq(_T_9611, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43545,7 +43545,7 @@ circuit el2_ifu : node _T_9616 = and(_T_9613, _T_9615) @[el2_ifu_bp_ctl.scala 447:81] node _T_9617 = or(_T_9616, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9618 = bits(_T_9617, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9619 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9620 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9621 = eq(_T_9620, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43555,7 +43555,7 @@ circuit el2_ifu : node _T_9625 = and(_T_9622, _T_9624) @[el2_ifu_bp_ctl.scala 447:81] node _T_9626 = or(_T_9625, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9627 = bits(_T_9626, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9628 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9629 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9630 = eq(_T_9629, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43565,7 +43565,7 @@ circuit el2_ifu : node _T_9634 = and(_T_9631, _T_9633) @[el2_ifu_bp_ctl.scala 447:81] node _T_9635 = or(_T_9634, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9636 = bits(_T_9635, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9637 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9638 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9639 = eq(_T_9638, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43575,7 +43575,7 @@ circuit el2_ifu : node _T_9643 = and(_T_9640, _T_9642) @[el2_ifu_bp_ctl.scala 447:81] node _T_9644 = or(_T_9643, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9645 = bits(_T_9644, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9646 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9647 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9648 = eq(_T_9647, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43585,7 +43585,7 @@ circuit el2_ifu : node _T_9652 = and(_T_9649, _T_9651) @[el2_ifu_bp_ctl.scala 447:81] node _T_9653 = or(_T_9652, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9654 = bits(_T_9653, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9655 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9656 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9657 = eq(_T_9656, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43595,7 +43595,7 @@ circuit el2_ifu : node _T_9661 = and(_T_9658, _T_9660) @[el2_ifu_bp_ctl.scala 447:81] node _T_9662 = or(_T_9661, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9663 = bits(_T_9662, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9664 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9665 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9666 = eq(_T_9665, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43605,7 +43605,7 @@ circuit el2_ifu : node _T_9670 = and(_T_9667, _T_9669) @[el2_ifu_bp_ctl.scala 447:81] node _T_9671 = or(_T_9670, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9672 = bits(_T_9671, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9673 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9674 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9675 = eq(_T_9674, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43615,7 +43615,7 @@ circuit el2_ifu : node _T_9679 = and(_T_9676, _T_9678) @[el2_ifu_bp_ctl.scala 447:81] node _T_9680 = or(_T_9679, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9681 = bits(_T_9680, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9682 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9683 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9684 = eq(_T_9683, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43625,7 +43625,7 @@ circuit el2_ifu : node _T_9688 = and(_T_9685, _T_9687) @[el2_ifu_bp_ctl.scala 447:81] node _T_9689 = or(_T_9688, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9690 = bits(_T_9689, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9691 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9692 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9693 = eq(_T_9692, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43635,7 +43635,7 @@ circuit el2_ifu : node _T_9697 = and(_T_9694, _T_9696) @[el2_ifu_bp_ctl.scala 447:81] node _T_9698 = or(_T_9697, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9699 = bits(_T_9698, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9700 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9701 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9702 = eq(_T_9701, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43645,7 +43645,7 @@ circuit el2_ifu : node _T_9706 = and(_T_9703, _T_9705) @[el2_ifu_bp_ctl.scala 447:81] node _T_9707 = or(_T_9706, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9708 = bits(_T_9707, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9709 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9710 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9711 = eq(_T_9710, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43655,7 +43655,7 @@ circuit el2_ifu : node _T_9715 = and(_T_9712, _T_9714) @[el2_ifu_bp_ctl.scala 447:81] node _T_9716 = or(_T_9715, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9717 = bits(_T_9716, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9718 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9719 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9720 = eq(_T_9719, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43665,7 +43665,7 @@ circuit el2_ifu : node _T_9724 = and(_T_9721, _T_9723) @[el2_ifu_bp_ctl.scala 447:81] node _T_9725 = or(_T_9724, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9726 = bits(_T_9725, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9727 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9728 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9729 = eq(_T_9728, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43675,7 +43675,7 @@ circuit el2_ifu : node _T_9733 = and(_T_9730, _T_9732) @[el2_ifu_bp_ctl.scala 447:81] node _T_9734 = or(_T_9733, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9735 = bits(_T_9734, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9736 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9737 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9738 = eq(_T_9737, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43685,7 +43685,7 @@ circuit el2_ifu : node _T_9742 = and(_T_9739, _T_9741) @[el2_ifu_bp_ctl.scala 447:81] node _T_9743 = or(_T_9742, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9744 = bits(_T_9743, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9745 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9746 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9747 = eq(_T_9746, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43695,7 +43695,7 @@ circuit el2_ifu : node _T_9751 = and(_T_9748, _T_9750) @[el2_ifu_bp_ctl.scala 447:81] node _T_9752 = or(_T_9751, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9753 = bits(_T_9752, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9754 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9755 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9756 = eq(_T_9755, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43705,7 +43705,7 @@ circuit el2_ifu : node _T_9760 = and(_T_9757, _T_9759) @[el2_ifu_bp_ctl.scala 447:81] node _T_9761 = or(_T_9760, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9762 = bits(_T_9761, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9763 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9764 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9765 = eq(_T_9764, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43715,7 +43715,7 @@ circuit el2_ifu : node _T_9769 = and(_T_9766, _T_9768) @[el2_ifu_bp_ctl.scala 447:81] node _T_9770 = or(_T_9769, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9771 = bits(_T_9770, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9772 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9773 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9774 = eq(_T_9773, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43725,7 +43725,7 @@ circuit el2_ifu : node _T_9778 = and(_T_9775, _T_9777) @[el2_ifu_bp_ctl.scala 447:81] node _T_9779 = or(_T_9778, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9780 = bits(_T_9779, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9781 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9782 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9783 = eq(_T_9782, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43735,7 +43735,7 @@ circuit el2_ifu : node _T_9787 = and(_T_9784, _T_9786) @[el2_ifu_bp_ctl.scala 447:81] node _T_9788 = or(_T_9787, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9789 = bits(_T_9788, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9790 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9791 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9792 = eq(_T_9791, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43745,7 +43745,7 @@ circuit el2_ifu : node _T_9796 = and(_T_9793, _T_9795) @[el2_ifu_bp_ctl.scala 447:81] node _T_9797 = or(_T_9796, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9798 = bits(_T_9797, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9799 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9800 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9801 = eq(_T_9800, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43755,7 +43755,7 @@ circuit el2_ifu : node _T_9805 = and(_T_9802, _T_9804) @[el2_ifu_bp_ctl.scala 447:81] node _T_9806 = or(_T_9805, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9807 = bits(_T_9806, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9808 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9809 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9810 = eq(_T_9809, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43765,7 +43765,7 @@ circuit el2_ifu : node _T_9814 = and(_T_9811, _T_9813) @[el2_ifu_bp_ctl.scala 447:81] node _T_9815 = or(_T_9814, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9816 = bits(_T_9815, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9817 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9818 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9819 = eq(_T_9818, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43775,7 +43775,7 @@ circuit el2_ifu : node _T_9823 = and(_T_9820, _T_9822) @[el2_ifu_bp_ctl.scala 447:81] node _T_9824 = or(_T_9823, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9825 = bits(_T_9824, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9826 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9827 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9828 = eq(_T_9827, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43785,7 +43785,7 @@ circuit el2_ifu : node _T_9832 = and(_T_9829, _T_9831) @[el2_ifu_bp_ctl.scala 447:81] node _T_9833 = or(_T_9832, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9834 = bits(_T_9833, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9835 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9836 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9837 = eq(_T_9836, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43795,7 +43795,7 @@ circuit el2_ifu : node _T_9841 = and(_T_9838, _T_9840) @[el2_ifu_bp_ctl.scala 447:81] node _T_9842 = or(_T_9841, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9843 = bits(_T_9842, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9844 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9845 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9846 = eq(_T_9845, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43805,7 +43805,7 @@ circuit el2_ifu : node _T_9850 = and(_T_9847, _T_9849) @[el2_ifu_bp_ctl.scala 447:81] node _T_9851 = or(_T_9850, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9852 = bits(_T_9851, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9853 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9854 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9855 = eq(_T_9854, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43815,7 +43815,7 @@ circuit el2_ifu : node _T_9859 = and(_T_9856, _T_9858) @[el2_ifu_bp_ctl.scala 447:81] node _T_9860 = or(_T_9859, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9861 = bits(_T_9860, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9862 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9863 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9864 = eq(_T_9863, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43825,7 +43825,7 @@ circuit el2_ifu : node _T_9868 = and(_T_9865, _T_9867) @[el2_ifu_bp_ctl.scala 447:81] node _T_9869 = or(_T_9868, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9870 = bits(_T_9869, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9871 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9872 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9873 = eq(_T_9872, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43835,7 +43835,7 @@ circuit el2_ifu : node _T_9877 = and(_T_9874, _T_9876) @[el2_ifu_bp_ctl.scala 447:81] node _T_9878 = or(_T_9877, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9879 = bits(_T_9878, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9880 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9881 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9882 = eq(_T_9881, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43845,7 +43845,7 @@ circuit el2_ifu : node _T_9886 = and(_T_9883, _T_9885) @[el2_ifu_bp_ctl.scala 447:81] node _T_9887 = or(_T_9886, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9888 = bits(_T_9887, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9889 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9890 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9891 = eq(_T_9890, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43855,7 +43855,7 @@ circuit el2_ifu : node _T_9895 = and(_T_9892, _T_9894) @[el2_ifu_bp_ctl.scala 447:81] node _T_9896 = or(_T_9895, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9897 = bits(_T_9896, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9898 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9899 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9900 = eq(_T_9899, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43865,7 +43865,7 @@ circuit el2_ifu : node _T_9904 = and(_T_9901, _T_9903) @[el2_ifu_bp_ctl.scala 447:81] node _T_9905 = or(_T_9904, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9906 = bits(_T_9905, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9907 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9908 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9909 = eq(_T_9908, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43875,7 +43875,7 @@ circuit el2_ifu : node _T_9913 = and(_T_9910, _T_9912) @[el2_ifu_bp_ctl.scala 447:81] node _T_9914 = or(_T_9913, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9915 = bits(_T_9914, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9916 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9917 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9918 = eq(_T_9917, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43885,7 +43885,7 @@ circuit el2_ifu : node _T_9922 = and(_T_9919, _T_9921) @[el2_ifu_bp_ctl.scala 447:81] node _T_9923 = or(_T_9922, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9924 = bits(_T_9923, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9925 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9926 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9927 = eq(_T_9926, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43895,7 +43895,7 @@ circuit el2_ifu : node _T_9931 = and(_T_9928, _T_9930) @[el2_ifu_bp_ctl.scala 447:81] node _T_9932 = or(_T_9931, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9933 = bits(_T_9932, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9934 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9935 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9936 = eq(_T_9935, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43905,7 +43905,7 @@ circuit el2_ifu : node _T_9940 = and(_T_9937, _T_9939) @[el2_ifu_bp_ctl.scala 447:81] node _T_9941 = or(_T_9940, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9942 = bits(_T_9941, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9943 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9944 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9945 = eq(_T_9944, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43915,7 +43915,7 @@ circuit el2_ifu : node _T_9949 = and(_T_9946, _T_9948) @[el2_ifu_bp_ctl.scala 447:81] node _T_9950 = or(_T_9949, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9951 = bits(_T_9950, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9952 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9953 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9954 = eq(_T_9953, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43925,7 +43925,7 @@ circuit el2_ifu : node _T_9958 = and(_T_9955, _T_9957) @[el2_ifu_bp_ctl.scala 447:81] node _T_9959 = or(_T_9958, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9960 = bits(_T_9959, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9961 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9962 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9963 = eq(_T_9962, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43935,7 +43935,7 @@ circuit el2_ifu : node _T_9967 = and(_T_9964, _T_9966) @[el2_ifu_bp_ctl.scala 447:81] node _T_9968 = or(_T_9967, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9969 = bits(_T_9968, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9970 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9971 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9972 = eq(_T_9971, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43945,7 +43945,7 @@ circuit el2_ifu : node _T_9976 = and(_T_9973, _T_9975) @[el2_ifu_bp_ctl.scala 447:81] node _T_9977 = or(_T_9976, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9978 = bits(_T_9977, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9979 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9980 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9981 = eq(_T_9980, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43955,7 +43955,7 @@ circuit el2_ifu : node _T_9985 = and(_T_9982, _T_9984) @[el2_ifu_bp_ctl.scala 447:81] node _T_9986 = or(_T_9985, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9987 = bits(_T_9986, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9988 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9989 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9990 = eq(_T_9989, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43965,7 +43965,7 @@ circuit el2_ifu : node _T_9994 = and(_T_9991, _T_9993) @[el2_ifu_bp_ctl.scala 447:81] node _T_9995 = or(_T_9994, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9996 = bits(_T_9995, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9997 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9998 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9999 = eq(_T_9998, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43975,7 +43975,7 @@ circuit el2_ifu : node _T_10003 = and(_T_10000, _T_10002) @[el2_ifu_bp_ctl.scala 447:81] node _T_10004 = or(_T_10003, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10005 = bits(_T_10004, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10006 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10007 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10008 = eq(_T_10007, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43985,7 +43985,7 @@ circuit el2_ifu : node _T_10012 = and(_T_10009, _T_10011) @[el2_ifu_bp_ctl.scala 447:81] node _T_10013 = or(_T_10012, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10014 = bits(_T_10013, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10015 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10016 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10017 = eq(_T_10016, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43995,7 +43995,7 @@ circuit el2_ifu : node _T_10021 = and(_T_10018, _T_10020) @[el2_ifu_bp_ctl.scala 447:81] node _T_10022 = or(_T_10021, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10023 = bits(_T_10022, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10024 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10025 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10026 = eq(_T_10025, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44005,7 +44005,7 @@ circuit el2_ifu : node _T_10030 = and(_T_10027, _T_10029) @[el2_ifu_bp_ctl.scala 447:81] node _T_10031 = or(_T_10030, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10032 = bits(_T_10031, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10033 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10034 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10035 = eq(_T_10034, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44015,7 +44015,7 @@ circuit el2_ifu : node _T_10039 = and(_T_10036, _T_10038) @[el2_ifu_bp_ctl.scala 447:81] node _T_10040 = or(_T_10039, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10041 = bits(_T_10040, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10042 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10043 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10044 = eq(_T_10043, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44025,7 +44025,7 @@ circuit el2_ifu : node _T_10048 = and(_T_10045, _T_10047) @[el2_ifu_bp_ctl.scala 447:81] node _T_10049 = or(_T_10048, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10050 = bits(_T_10049, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10051 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10052 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10053 = eq(_T_10052, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44035,7 +44035,7 @@ circuit el2_ifu : node _T_10057 = and(_T_10054, _T_10056) @[el2_ifu_bp_ctl.scala 447:81] node _T_10058 = or(_T_10057, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10059 = bits(_T_10058, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10060 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10061 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10062 = eq(_T_10061, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44045,7 +44045,7 @@ circuit el2_ifu : node _T_10066 = and(_T_10063, _T_10065) @[el2_ifu_bp_ctl.scala 447:81] node _T_10067 = or(_T_10066, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10068 = bits(_T_10067, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10069 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10070 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10071 = eq(_T_10070, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44055,7 +44055,7 @@ circuit el2_ifu : node _T_10075 = and(_T_10072, _T_10074) @[el2_ifu_bp_ctl.scala 447:81] node _T_10076 = or(_T_10075, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10077 = bits(_T_10076, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10078 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10079 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10080 = eq(_T_10079, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44065,7 +44065,7 @@ circuit el2_ifu : node _T_10084 = and(_T_10081, _T_10083) @[el2_ifu_bp_ctl.scala 447:81] node _T_10085 = or(_T_10084, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10086 = bits(_T_10085, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10087 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10088 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10089 = eq(_T_10088, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44075,7 +44075,7 @@ circuit el2_ifu : node _T_10093 = and(_T_10090, _T_10092) @[el2_ifu_bp_ctl.scala 447:81] node _T_10094 = or(_T_10093, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10095 = bits(_T_10094, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10096 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10097 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10098 = eq(_T_10097, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44085,7 +44085,7 @@ circuit el2_ifu : node _T_10102 = and(_T_10099, _T_10101) @[el2_ifu_bp_ctl.scala 447:81] node _T_10103 = or(_T_10102, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10104 = bits(_T_10103, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10105 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10106 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10107 = eq(_T_10106, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44095,7 +44095,7 @@ circuit el2_ifu : node _T_10111 = and(_T_10108, _T_10110) @[el2_ifu_bp_ctl.scala 447:81] node _T_10112 = or(_T_10111, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10113 = bits(_T_10112, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10114 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10115 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10116 = eq(_T_10115, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44105,7 +44105,7 @@ circuit el2_ifu : node _T_10120 = and(_T_10117, _T_10119) @[el2_ifu_bp_ctl.scala 447:81] node _T_10121 = or(_T_10120, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10122 = bits(_T_10121, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10123 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10124 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10125 = eq(_T_10124, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44115,7 +44115,7 @@ circuit el2_ifu : node _T_10129 = and(_T_10126, _T_10128) @[el2_ifu_bp_ctl.scala 447:81] node _T_10130 = or(_T_10129, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10131 = bits(_T_10130, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10132 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10133 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10134 = eq(_T_10133, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44125,7 +44125,7 @@ circuit el2_ifu : node _T_10138 = and(_T_10135, _T_10137) @[el2_ifu_bp_ctl.scala 447:81] node _T_10139 = or(_T_10138, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10140 = bits(_T_10139, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10141 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10142 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10143 = eq(_T_10142, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44135,7 +44135,7 @@ circuit el2_ifu : node _T_10147 = and(_T_10144, _T_10146) @[el2_ifu_bp_ctl.scala 447:81] node _T_10148 = or(_T_10147, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10149 = bits(_T_10148, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10150 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10151 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10152 = eq(_T_10151, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44145,7 +44145,7 @@ circuit el2_ifu : node _T_10156 = and(_T_10153, _T_10155) @[el2_ifu_bp_ctl.scala 447:81] node _T_10157 = or(_T_10156, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10158 = bits(_T_10157, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10159 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10160 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10161 = eq(_T_10160, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44155,7 +44155,7 @@ circuit el2_ifu : node _T_10165 = and(_T_10162, _T_10164) @[el2_ifu_bp_ctl.scala 447:81] node _T_10166 = or(_T_10165, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10167 = bits(_T_10166, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10168 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10169 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10170 = eq(_T_10169, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44165,7 +44165,7 @@ circuit el2_ifu : node _T_10174 = and(_T_10171, _T_10173) @[el2_ifu_bp_ctl.scala 447:81] node _T_10175 = or(_T_10174, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10176 = bits(_T_10175, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10177 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10178 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10179 = eq(_T_10178, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44175,7 +44175,7 @@ circuit el2_ifu : node _T_10183 = and(_T_10180, _T_10182) @[el2_ifu_bp_ctl.scala 447:81] node _T_10184 = or(_T_10183, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10185 = bits(_T_10184, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10186 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10187 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10188 = eq(_T_10187, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44185,7 +44185,7 @@ circuit el2_ifu : node _T_10192 = and(_T_10189, _T_10191) @[el2_ifu_bp_ctl.scala 447:81] node _T_10193 = or(_T_10192, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10194 = bits(_T_10193, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10195 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10196 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10197 = eq(_T_10196, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44195,7 +44195,7 @@ circuit el2_ifu : node _T_10201 = and(_T_10198, _T_10200) @[el2_ifu_bp_ctl.scala 447:81] node _T_10202 = or(_T_10201, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10203 = bits(_T_10202, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10204 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10205 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10206 = eq(_T_10205, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44205,7 +44205,7 @@ circuit el2_ifu : node _T_10210 = and(_T_10207, _T_10209) @[el2_ifu_bp_ctl.scala 447:81] node _T_10211 = or(_T_10210, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10212 = bits(_T_10211, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10213 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10214 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10215 = eq(_T_10214, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44215,7 +44215,7 @@ circuit el2_ifu : node _T_10219 = and(_T_10216, _T_10218) @[el2_ifu_bp_ctl.scala 447:81] node _T_10220 = or(_T_10219, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10221 = bits(_T_10220, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10222 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10223 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10224 = eq(_T_10223, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44225,7 +44225,7 @@ circuit el2_ifu : node _T_10228 = and(_T_10225, _T_10227) @[el2_ifu_bp_ctl.scala 447:81] node _T_10229 = or(_T_10228, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10230 = bits(_T_10229, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10231 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10232 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10233 = eq(_T_10232, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44235,7 +44235,7 @@ circuit el2_ifu : node _T_10237 = and(_T_10234, _T_10236) @[el2_ifu_bp_ctl.scala 447:81] node _T_10238 = or(_T_10237, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10239 = bits(_T_10238, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10240 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10241 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10242 = eq(_T_10241, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44245,7 +44245,7 @@ circuit el2_ifu : node _T_10246 = and(_T_10243, _T_10245) @[el2_ifu_bp_ctl.scala 447:81] node _T_10247 = or(_T_10246, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10248 = bits(_T_10247, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10249 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10250 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10251 = eq(_T_10250, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44255,7 +44255,7 @@ circuit el2_ifu : node _T_10255 = and(_T_10252, _T_10254) @[el2_ifu_bp_ctl.scala 447:81] node _T_10256 = or(_T_10255, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10257 = bits(_T_10256, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10258 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10259 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10260 = eq(_T_10259, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44265,7 +44265,7 @@ circuit el2_ifu : node _T_10264 = and(_T_10261, _T_10263) @[el2_ifu_bp_ctl.scala 447:81] node _T_10265 = or(_T_10264, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10266 = bits(_T_10265, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10267 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10268 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10269 = eq(_T_10268, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44275,7 +44275,7 @@ circuit el2_ifu : node _T_10273 = and(_T_10270, _T_10272) @[el2_ifu_bp_ctl.scala 447:81] node _T_10274 = or(_T_10273, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10275 = bits(_T_10274, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10276 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10277 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10278 = eq(_T_10277, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44285,7 +44285,7 @@ circuit el2_ifu : node _T_10282 = and(_T_10279, _T_10281) @[el2_ifu_bp_ctl.scala 447:81] node _T_10283 = or(_T_10282, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10284 = bits(_T_10283, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10285 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10286 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10287 = eq(_T_10286, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44295,7 +44295,7 @@ circuit el2_ifu : node _T_10291 = and(_T_10288, _T_10290) @[el2_ifu_bp_ctl.scala 447:81] node _T_10292 = or(_T_10291, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10293 = bits(_T_10292, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10294 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10295 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10296 = eq(_T_10295, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44305,7 +44305,7 @@ circuit el2_ifu : node _T_10300 = and(_T_10297, _T_10299) @[el2_ifu_bp_ctl.scala 447:81] node _T_10301 = or(_T_10300, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10302 = bits(_T_10301, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10303 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10304 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10305 = eq(_T_10304, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44315,7 +44315,7 @@ circuit el2_ifu : node _T_10309 = and(_T_10306, _T_10308) @[el2_ifu_bp_ctl.scala 447:81] node _T_10310 = or(_T_10309, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10311 = bits(_T_10310, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10312 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10313 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10314 = eq(_T_10313, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44325,7 +44325,7 @@ circuit el2_ifu : node _T_10318 = and(_T_10315, _T_10317) @[el2_ifu_bp_ctl.scala 447:81] node _T_10319 = or(_T_10318, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10320 = bits(_T_10319, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10321 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10322 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10323 = eq(_T_10322, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44335,7 +44335,7 @@ circuit el2_ifu : node _T_10327 = and(_T_10324, _T_10326) @[el2_ifu_bp_ctl.scala 447:81] node _T_10328 = or(_T_10327, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10329 = bits(_T_10328, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10330 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10331 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10332 = eq(_T_10331, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44345,7 +44345,7 @@ circuit el2_ifu : node _T_10336 = and(_T_10333, _T_10335) @[el2_ifu_bp_ctl.scala 447:81] node _T_10337 = or(_T_10336, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10338 = bits(_T_10337, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10339 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10340 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10341 = eq(_T_10340, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44355,7 +44355,7 @@ circuit el2_ifu : node _T_10345 = and(_T_10342, _T_10344) @[el2_ifu_bp_ctl.scala 447:81] node _T_10346 = or(_T_10345, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10347 = bits(_T_10346, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10348 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10349 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10350 = eq(_T_10349, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44365,7 +44365,7 @@ circuit el2_ifu : node _T_10354 = and(_T_10351, _T_10353) @[el2_ifu_bp_ctl.scala 447:81] node _T_10355 = or(_T_10354, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10356 = bits(_T_10355, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10357 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10358 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10359 = eq(_T_10358, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44375,7 +44375,7 @@ circuit el2_ifu : node _T_10363 = and(_T_10360, _T_10362) @[el2_ifu_bp_ctl.scala 447:81] node _T_10364 = or(_T_10363, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10365 = bits(_T_10364, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10366 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10367 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10368 = eq(_T_10367, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44385,7 +44385,7 @@ circuit el2_ifu : node _T_10372 = and(_T_10369, _T_10371) @[el2_ifu_bp_ctl.scala 447:81] node _T_10373 = or(_T_10372, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10374 = bits(_T_10373, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10375 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10376 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10377 = eq(_T_10376, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44395,7 +44395,7 @@ circuit el2_ifu : node _T_10381 = and(_T_10378, _T_10380) @[el2_ifu_bp_ctl.scala 447:81] node _T_10382 = or(_T_10381, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10383 = bits(_T_10382, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10384 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10385 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10386 = eq(_T_10385, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44405,7 +44405,7 @@ circuit el2_ifu : node _T_10390 = and(_T_10387, _T_10389) @[el2_ifu_bp_ctl.scala 447:81] node _T_10391 = or(_T_10390, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10392 = bits(_T_10391, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10393 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10394 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10395 = eq(_T_10394, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44415,7 +44415,7 @@ circuit el2_ifu : node _T_10399 = and(_T_10396, _T_10398) @[el2_ifu_bp_ctl.scala 447:81] node _T_10400 = or(_T_10399, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10401 = bits(_T_10400, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10402 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10403 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10404 = eq(_T_10403, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44425,7 +44425,7 @@ circuit el2_ifu : node _T_10408 = and(_T_10405, _T_10407) @[el2_ifu_bp_ctl.scala 447:81] node _T_10409 = or(_T_10408, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10410 = bits(_T_10409, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10411 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10412 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10413 = eq(_T_10412, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44435,7 +44435,7 @@ circuit el2_ifu : node _T_10417 = and(_T_10414, _T_10416) @[el2_ifu_bp_ctl.scala 447:81] node _T_10418 = or(_T_10417, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10419 = bits(_T_10418, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10420 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10421 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10422 = eq(_T_10421, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44445,7 +44445,7 @@ circuit el2_ifu : node _T_10426 = and(_T_10423, _T_10425) @[el2_ifu_bp_ctl.scala 447:81] node _T_10427 = or(_T_10426, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10428 = bits(_T_10427, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10429 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10430 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10431 = eq(_T_10430, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44455,7 +44455,7 @@ circuit el2_ifu : node _T_10435 = and(_T_10432, _T_10434) @[el2_ifu_bp_ctl.scala 447:81] node _T_10436 = or(_T_10435, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10437 = bits(_T_10436, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10438 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10439 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10440 = eq(_T_10439, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44465,7 +44465,7 @@ circuit el2_ifu : node _T_10444 = and(_T_10441, _T_10443) @[el2_ifu_bp_ctl.scala 447:81] node _T_10445 = or(_T_10444, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10446 = bits(_T_10445, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10447 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10448 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10449 = eq(_T_10448, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44475,7 +44475,7 @@ circuit el2_ifu : node _T_10453 = and(_T_10450, _T_10452) @[el2_ifu_bp_ctl.scala 447:81] node _T_10454 = or(_T_10453, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10455 = bits(_T_10454, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10456 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10457 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10458 = eq(_T_10457, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44485,7 +44485,7 @@ circuit el2_ifu : node _T_10462 = and(_T_10459, _T_10461) @[el2_ifu_bp_ctl.scala 447:81] node _T_10463 = or(_T_10462, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10464 = bits(_T_10463, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10465 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10466 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10467 = eq(_T_10466, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44495,7 +44495,7 @@ circuit el2_ifu : node _T_10471 = and(_T_10468, _T_10470) @[el2_ifu_bp_ctl.scala 447:81] node _T_10472 = or(_T_10471, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10473 = bits(_T_10472, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10474 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10475 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10476 = eq(_T_10475, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44505,7 +44505,7 @@ circuit el2_ifu : node _T_10480 = and(_T_10477, _T_10479) @[el2_ifu_bp_ctl.scala 447:81] node _T_10481 = or(_T_10480, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10482 = bits(_T_10481, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10483 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10484 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10485 = eq(_T_10484, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44515,7 +44515,7 @@ circuit el2_ifu : node _T_10489 = and(_T_10486, _T_10488) @[el2_ifu_bp_ctl.scala 447:81] node _T_10490 = or(_T_10489, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10491 = bits(_T_10490, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10492 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10493 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10494 = eq(_T_10493, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44525,7 +44525,7 @@ circuit el2_ifu : node _T_10498 = and(_T_10495, _T_10497) @[el2_ifu_bp_ctl.scala 447:81] node _T_10499 = or(_T_10498, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10500 = bits(_T_10499, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10501 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10502 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10503 = eq(_T_10502, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44535,7 +44535,7 @@ circuit el2_ifu : node _T_10507 = and(_T_10504, _T_10506) @[el2_ifu_bp_ctl.scala 447:81] node _T_10508 = or(_T_10507, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10509 = bits(_T_10508, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10510 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10511 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10512 = eq(_T_10511, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44545,7 +44545,7 @@ circuit el2_ifu : node _T_10516 = and(_T_10513, _T_10515) @[el2_ifu_bp_ctl.scala 447:81] node _T_10517 = or(_T_10516, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10518 = bits(_T_10517, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10519 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10520 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10521 = eq(_T_10520, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44555,7 +44555,7 @@ circuit el2_ifu : node _T_10525 = and(_T_10522, _T_10524) @[el2_ifu_bp_ctl.scala 447:81] node _T_10526 = or(_T_10525, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10527 = bits(_T_10526, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10528 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10529 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10530 = eq(_T_10529, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44565,7 +44565,7 @@ circuit el2_ifu : node _T_10534 = and(_T_10531, _T_10533) @[el2_ifu_bp_ctl.scala 447:81] node _T_10535 = or(_T_10534, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10536 = bits(_T_10535, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10537 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10538 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10539 = eq(_T_10538, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44575,7 +44575,7 @@ circuit el2_ifu : node _T_10543 = and(_T_10540, _T_10542) @[el2_ifu_bp_ctl.scala 447:81] node _T_10544 = or(_T_10543, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10545 = bits(_T_10544, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10546 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10547 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10548 = eq(_T_10547, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44585,7 +44585,7 @@ circuit el2_ifu : node _T_10552 = and(_T_10549, _T_10551) @[el2_ifu_bp_ctl.scala 447:81] node _T_10553 = or(_T_10552, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10554 = bits(_T_10553, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10555 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10556 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10557 = eq(_T_10556, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44595,7 +44595,7 @@ circuit el2_ifu : node _T_10561 = and(_T_10558, _T_10560) @[el2_ifu_bp_ctl.scala 447:81] node _T_10562 = or(_T_10561, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10563 = bits(_T_10562, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10564 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10565 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10566 = eq(_T_10565, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44605,7 +44605,7 @@ circuit el2_ifu : node _T_10570 = and(_T_10567, _T_10569) @[el2_ifu_bp_ctl.scala 447:81] node _T_10571 = or(_T_10570, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10572 = bits(_T_10571, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10573 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10574 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10575 = eq(_T_10574, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44615,7 +44615,7 @@ circuit el2_ifu : node _T_10579 = and(_T_10576, _T_10578) @[el2_ifu_bp_ctl.scala 447:81] node _T_10580 = or(_T_10579, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10581 = bits(_T_10580, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10582 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10583 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10584 = eq(_T_10583, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44625,7 +44625,7 @@ circuit el2_ifu : node _T_10588 = and(_T_10585, _T_10587) @[el2_ifu_bp_ctl.scala 447:81] node _T_10589 = or(_T_10588, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10590 = bits(_T_10589, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10591 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10592 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10593 = eq(_T_10592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44635,7 +44635,7 @@ circuit el2_ifu : node _T_10597 = and(_T_10594, _T_10596) @[el2_ifu_bp_ctl.scala 447:81] node _T_10598 = or(_T_10597, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10599 = bits(_T_10598, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10600 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10601 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10602 = eq(_T_10601, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44645,7 +44645,7 @@ circuit el2_ifu : node _T_10606 = and(_T_10603, _T_10605) @[el2_ifu_bp_ctl.scala 447:81] node _T_10607 = or(_T_10606, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10608 = bits(_T_10607, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10609 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10610 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10611 = eq(_T_10610, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44655,7 +44655,7 @@ circuit el2_ifu : node _T_10615 = and(_T_10612, _T_10614) @[el2_ifu_bp_ctl.scala 447:81] node _T_10616 = or(_T_10615, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10617 = bits(_T_10616, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10618 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10619 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10620 = eq(_T_10619, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44665,7 +44665,7 @@ circuit el2_ifu : node _T_10624 = and(_T_10621, _T_10623) @[el2_ifu_bp_ctl.scala 447:81] node _T_10625 = or(_T_10624, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10626 = bits(_T_10625, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10627 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10628 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10629 = eq(_T_10628, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44675,7 +44675,7 @@ circuit el2_ifu : node _T_10633 = and(_T_10630, _T_10632) @[el2_ifu_bp_ctl.scala 447:81] node _T_10634 = or(_T_10633, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10635 = bits(_T_10634, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10636 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10637 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10638 = eq(_T_10637, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44685,7 +44685,7 @@ circuit el2_ifu : node _T_10642 = and(_T_10639, _T_10641) @[el2_ifu_bp_ctl.scala 447:81] node _T_10643 = or(_T_10642, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10644 = bits(_T_10643, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10645 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10646 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10647 = eq(_T_10646, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44695,7 +44695,7 @@ circuit el2_ifu : node _T_10651 = and(_T_10648, _T_10650) @[el2_ifu_bp_ctl.scala 447:81] node _T_10652 = or(_T_10651, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10653 = bits(_T_10652, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10654 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10655 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10656 = eq(_T_10655, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44705,7 +44705,7 @@ circuit el2_ifu : node _T_10660 = and(_T_10657, _T_10659) @[el2_ifu_bp_ctl.scala 447:81] node _T_10661 = or(_T_10660, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10662 = bits(_T_10661, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10663 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10664 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10665 = eq(_T_10664, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44715,7 +44715,7 @@ circuit el2_ifu : node _T_10669 = and(_T_10666, _T_10668) @[el2_ifu_bp_ctl.scala 447:81] node _T_10670 = or(_T_10669, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10671 = bits(_T_10670, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10672 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10673 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10674 = eq(_T_10673, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44725,7 +44725,7 @@ circuit el2_ifu : node _T_10678 = and(_T_10675, _T_10677) @[el2_ifu_bp_ctl.scala 447:81] node _T_10679 = or(_T_10678, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10680 = bits(_T_10679, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10681 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10682 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10683 = eq(_T_10682, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44735,7 +44735,7 @@ circuit el2_ifu : node _T_10687 = and(_T_10684, _T_10686) @[el2_ifu_bp_ctl.scala 447:81] node _T_10688 = or(_T_10687, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10689 = bits(_T_10688, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10690 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10691 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10692 = eq(_T_10691, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44745,7 +44745,7 @@ circuit el2_ifu : node _T_10696 = and(_T_10693, _T_10695) @[el2_ifu_bp_ctl.scala 447:81] node _T_10697 = or(_T_10696, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10698 = bits(_T_10697, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10699 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10700 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10701 = eq(_T_10700, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44755,7 +44755,7 @@ circuit el2_ifu : node _T_10705 = and(_T_10702, _T_10704) @[el2_ifu_bp_ctl.scala 447:81] node _T_10706 = or(_T_10705, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10707 = bits(_T_10706, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10708 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10709 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10710 = eq(_T_10709, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44765,7 +44765,7 @@ circuit el2_ifu : node _T_10714 = and(_T_10711, _T_10713) @[el2_ifu_bp_ctl.scala 447:81] node _T_10715 = or(_T_10714, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10716 = bits(_T_10715, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10717 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10718 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10719 = eq(_T_10718, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44775,7 +44775,7 @@ circuit el2_ifu : node _T_10723 = and(_T_10720, _T_10722) @[el2_ifu_bp_ctl.scala 447:81] node _T_10724 = or(_T_10723, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10725 = bits(_T_10724, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10726 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10727 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10728 = eq(_T_10727, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44785,7 +44785,7 @@ circuit el2_ifu : node _T_10732 = and(_T_10729, _T_10731) @[el2_ifu_bp_ctl.scala 447:81] node _T_10733 = or(_T_10732, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10734 = bits(_T_10733, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10735 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10736 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10737 = eq(_T_10736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44795,7 +44795,7 @@ circuit el2_ifu : node _T_10741 = and(_T_10738, _T_10740) @[el2_ifu_bp_ctl.scala 447:81] node _T_10742 = or(_T_10741, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10743 = bits(_T_10742, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10744 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10745 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10746 = eq(_T_10745, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44805,7 +44805,7 @@ circuit el2_ifu : node _T_10750 = and(_T_10747, _T_10749) @[el2_ifu_bp_ctl.scala 447:81] node _T_10751 = or(_T_10750, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10752 = bits(_T_10751, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10753 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10754 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10755 = eq(_T_10754, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44815,7 +44815,7 @@ circuit el2_ifu : node _T_10759 = and(_T_10756, _T_10758) @[el2_ifu_bp_ctl.scala 447:81] node _T_10760 = or(_T_10759, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10761 = bits(_T_10760, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10762 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10763 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10764 = eq(_T_10763, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44825,7 +44825,7 @@ circuit el2_ifu : node _T_10768 = and(_T_10765, _T_10767) @[el2_ifu_bp_ctl.scala 447:81] node _T_10769 = or(_T_10768, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10770 = bits(_T_10769, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10771 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10772 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10773 = eq(_T_10772, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44835,7 +44835,7 @@ circuit el2_ifu : node _T_10777 = and(_T_10774, _T_10776) @[el2_ifu_bp_ctl.scala 447:81] node _T_10778 = or(_T_10777, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10779 = bits(_T_10778, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10780 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10781 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10782 = eq(_T_10781, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44845,7 +44845,7 @@ circuit el2_ifu : node _T_10786 = and(_T_10783, _T_10785) @[el2_ifu_bp_ctl.scala 447:81] node _T_10787 = or(_T_10786, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10788 = bits(_T_10787, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10789 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10790 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10791 = eq(_T_10790, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44855,7 +44855,7 @@ circuit el2_ifu : node _T_10795 = and(_T_10792, _T_10794) @[el2_ifu_bp_ctl.scala 447:81] node _T_10796 = or(_T_10795, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10797 = bits(_T_10796, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10798 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10799 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10800 = eq(_T_10799, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44865,7 +44865,7 @@ circuit el2_ifu : node _T_10804 = and(_T_10801, _T_10803) @[el2_ifu_bp_ctl.scala 447:81] node _T_10805 = or(_T_10804, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10806 = bits(_T_10805, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10807 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10808 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10809 = eq(_T_10808, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44875,7 +44875,7 @@ circuit el2_ifu : node _T_10813 = and(_T_10810, _T_10812) @[el2_ifu_bp_ctl.scala 447:81] node _T_10814 = or(_T_10813, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10815 = bits(_T_10814, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10816 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10817 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10818 = eq(_T_10817, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44885,7 +44885,7 @@ circuit el2_ifu : node _T_10822 = and(_T_10819, _T_10821) @[el2_ifu_bp_ctl.scala 447:81] node _T_10823 = or(_T_10822, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10824 = bits(_T_10823, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10825 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10826 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10827 = eq(_T_10826, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44895,7 +44895,7 @@ circuit el2_ifu : node _T_10831 = and(_T_10828, _T_10830) @[el2_ifu_bp_ctl.scala 447:81] node _T_10832 = or(_T_10831, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10833 = bits(_T_10832, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10834 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10835 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10836 = eq(_T_10835, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44905,7 +44905,7 @@ circuit el2_ifu : node _T_10840 = and(_T_10837, _T_10839) @[el2_ifu_bp_ctl.scala 447:81] node _T_10841 = or(_T_10840, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10842 = bits(_T_10841, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10843 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10844 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10845 = eq(_T_10844, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44915,7 +44915,7 @@ circuit el2_ifu : node _T_10849 = and(_T_10846, _T_10848) @[el2_ifu_bp_ctl.scala 447:81] node _T_10850 = or(_T_10849, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10851 = bits(_T_10850, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10852 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10853 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10854 = eq(_T_10853, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44925,7 +44925,7 @@ circuit el2_ifu : node _T_10858 = and(_T_10855, _T_10857) @[el2_ifu_bp_ctl.scala 447:81] node _T_10859 = or(_T_10858, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10860 = bits(_T_10859, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10861 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10862 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10863 = eq(_T_10862, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44935,7 +44935,7 @@ circuit el2_ifu : node _T_10867 = and(_T_10864, _T_10866) @[el2_ifu_bp_ctl.scala 447:81] node _T_10868 = or(_T_10867, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10869 = bits(_T_10868, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10870 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10871 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10872 = eq(_T_10871, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44945,7 +44945,7 @@ circuit el2_ifu : node _T_10876 = and(_T_10873, _T_10875) @[el2_ifu_bp_ctl.scala 447:81] node _T_10877 = or(_T_10876, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10878 = bits(_T_10877, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10879 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10880 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10881 = eq(_T_10880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44955,7 +44955,7 @@ circuit el2_ifu : node _T_10885 = and(_T_10882, _T_10884) @[el2_ifu_bp_ctl.scala 447:81] node _T_10886 = or(_T_10885, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10887 = bits(_T_10886, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10888 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10889 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10890 = eq(_T_10889, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44965,7 +44965,7 @@ circuit el2_ifu : node _T_10894 = and(_T_10891, _T_10893) @[el2_ifu_bp_ctl.scala 447:81] node _T_10895 = or(_T_10894, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10896 = bits(_T_10895, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10897 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10898 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10899 = eq(_T_10898, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44975,7 +44975,7 @@ circuit el2_ifu : node _T_10903 = and(_T_10900, _T_10902) @[el2_ifu_bp_ctl.scala 447:81] node _T_10904 = or(_T_10903, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10905 = bits(_T_10904, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10906 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10907 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10908 = eq(_T_10907, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44985,7 +44985,7 @@ circuit el2_ifu : node _T_10912 = and(_T_10909, _T_10911) @[el2_ifu_bp_ctl.scala 447:81] node _T_10913 = or(_T_10912, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10914 = bits(_T_10913, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10915 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10916 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10917 = eq(_T_10916, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44995,7 +44995,7 @@ circuit el2_ifu : node _T_10921 = and(_T_10918, _T_10920) @[el2_ifu_bp_ctl.scala 447:81] node _T_10922 = or(_T_10921, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10923 = bits(_T_10922, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10924 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10925 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10926 = eq(_T_10925, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45005,7 +45005,7 @@ circuit el2_ifu : node _T_10930 = and(_T_10927, _T_10929) @[el2_ifu_bp_ctl.scala 447:81] node _T_10931 = or(_T_10930, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10932 = bits(_T_10931, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10933 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10934 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10935 = eq(_T_10934, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45015,7 +45015,7 @@ circuit el2_ifu : node _T_10939 = and(_T_10936, _T_10938) @[el2_ifu_bp_ctl.scala 447:81] node _T_10940 = or(_T_10939, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10941 = bits(_T_10940, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10942 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10943 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10944 = eq(_T_10943, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45025,7 +45025,7 @@ circuit el2_ifu : node _T_10948 = and(_T_10945, _T_10947) @[el2_ifu_bp_ctl.scala 447:81] node _T_10949 = or(_T_10948, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10950 = bits(_T_10949, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10951 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10952 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10953 = eq(_T_10952, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45035,7 +45035,7 @@ circuit el2_ifu : node _T_10957 = and(_T_10954, _T_10956) @[el2_ifu_bp_ctl.scala 447:81] node _T_10958 = or(_T_10957, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10959 = bits(_T_10958, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10960 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10961 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10962 = eq(_T_10961, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45045,7 +45045,7 @@ circuit el2_ifu : node _T_10966 = and(_T_10963, _T_10965) @[el2_ifu_bp_ctl.scala 447:81] node _T_10967 = or(_T_10966, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10968 = bits(_T_10967, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10969 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10970 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10971 = eq(_T_10970, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45055,7 +45055,7 @@ circuit el2_ifu : node _T_10975 = and(_T_10972, _T_10974) @[el2_ifu_bp_ctl.scala 447:81] node _T_10976 = or(_T_10975, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10977 = bits(_T_10976, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10978 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10979 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10980 = eq(_T_10979, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45065,7 +45065,7 @@ circuit el2_ifu : node _T_10984 = and(_T_10981, _T_10983) @[el2_ifu_bp_ctl.scala 447:81] node _T_10985 = or(_T_10984, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10986 = bits(_T_10985, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10987 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10988 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10989 = eq(_T_10988, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45075,7 +45075,7 @@ circuit el2_ifu : node _T_10993 = and(_T_10990, _T_10992) @[el2_ifu_bp_ctl.scala 447:81] node _T_10994 = or(_T_10993, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10995 = bits(_T_10994, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10996 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10997 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10998 = eq(_T_10997, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45085,7 +45085,7 @@ circuit el2_ifu : node _T_11002 = and(_T_10999, _T_11001) @[el2_ifu_bp_ctl.scala 447:81] node _T_11003 = or(_T_11002, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11004 = bits(_T_11003, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11005 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11006 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11007 = eq(_T_11006, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45095,7 +45095,7 @@ circuit el2_ifu : node _T_11011 = and(_T_11008, _T_11010) @[el2_ifu_bp_ctl.scala 447:81] node _T_11012 = or(_T_11011, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11013 = bits(_T_11012, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11014 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11015 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11016 = eq(_T_11015, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45105,7 +45105,7 @@ circuit el2_ifu : node _T_11020 = and(_T_11017, _T_11019) @[el2_ifu_bp_ctl.scala 447:81] node _T_11021 = or(_T_11020, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11022 = bits(_T_11021, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11023 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11024 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11025 = eq(_T_11024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45115,7 +45115,7 @@ circuit el2_ifu : node _T_11029 = and(_T_11026, _T_11028) @[el2_ifu_bp_ctl.scala 447:81] node _T_11030 = or(_T_11029, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11031 = bits(_T_11030, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11032 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11033 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11034 = eq(_T_11033, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45125,7 +45125,7 @@ circuit el2_ifu : node _T_11038 = and(_T_11035, _T_11037) @[el2_ifu_bp_ctl.scala 447:81] node _T_11039 = or(_T_11038, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11040 = bits(_T_11039, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11041 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11042 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11043 = eq(_T_11042, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45135,7 +45135,7 @@ circuit el2_ifu : node _T_11047 = and(_T_11044, _T_11046) @[el2_ifu_bp_ctl.scala 447:81] node _T_11048 = or(_T_11047, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11049 = bits(_T_11048, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11050 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11051 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11052 = eq(_T_11051, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45145,7 +45145,7 @@ circuit el2_ifu : node _T_11056 = and(_T_11053, _T_11055) @[el2_ifu_bp_ctl.scala 447:81] node _T_11057 = or(_T_11056, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11058 = bits(_T_11057, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11059 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11060 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11061 = eq(_T_11060, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45155,7 +45155,7 @@ circuit el2_ifu : node _T_11065 = and(_T_11062, _T_11064) @[el2_ifu_bp_ctl.scala 447:81] node _T_11066 = or(_T_11065, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11067 = bits(_T_11066, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11068 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11069 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11070 = eq(_T_11069, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45165,7 +45165,7 @@ circuit el2_ifu : node _T_11074 = and(_T_11071, _T_11073) @[el2_ifu_bp_ctl.scala 447:81] node _T_11075 = or(_T_11074, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11076 = bits(_T_11075, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11077 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11078 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11079 = eq(_T_11078, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45175,7 +45175,7 @@ circuit el2_ifu : node _T_11083 = and(_T_11080, _T_11082) @[el2_ifu_bp_ctl.scala 447:81] node _T_11084 = or(_T_11083, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11085 = bits(_T_11084, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11086 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11087 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11088 = eq(_T_11087, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45185,7 +45185,7 @@ circuit el2_ifu : node _T_11092 = and(_T_11089, _T_11091) @[el2_ifu_bp_ctl.scala 447:81] node _T_11093 = or(_T_11092, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11094 = bits(_T_11093, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11095 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11096 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11097 = eq(_T_11096, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45195,7 +45195,7 @@ circuit el2_ifu : node _T_11101 = and(_T_11098, _T_11100) @[el2_ifu_bp_ctl.scala 447:81] node _T_11102 = or(_T_11101, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11103 = bits(_T_11102, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11104 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11105 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11106 = eq(_T_11105, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45205,7 +45205,7 @@ circuit el2_ifu : node _T_11110 = and(_T_11107, _T_11109) @[el2_ifu_bp_ctl.scala 447:81] node _T_11111 = or(_T_11110, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11112 = bits(_T_11111, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11113 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11114 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11115 = eq(_T_11114, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45215,7 +45215,7 @@ circuit el2_ifu : node _T_11119 = and(_T_11116, _T_11118) @[el2_ifu_bp_ctl.scala 447:81] node _T_11120 = or(_T_11119, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11121 = bits(_T_11120, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11122 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11123 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11124 = eq(_T_11123, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45225,7 +45225,7 @@ circuit el2_ifu : node _T_11128 = and(_T_11125, _T_11127) @[el2_ifu_bp_ctl.scala 447:81] node _T_11129 = or(_T_11128, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11130 = bits(_T_11129, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11131 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11132 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11133 = eq(_T_11132, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45235,7 +45235,7 @@ circuit el2_ifu : node _T_11137 = and(_T_11134, _T_11136) @[el2_ifu_bp_ctl.scala 447:81] node _T_11138 = or(_T_11137, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11139 = bits(_T_11138, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11140 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11141 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11142 = eq(_T_11141, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45245,7 +45245,7 @@ circuit el2_ifu : node _T_11146 = and(_T_11143, _T_11145) @[el2_ifu_bp_ctl.scala 447:81] node _T_11147 = or(_T_11146, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11148 = bits(_T_11147, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11149 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11150 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11151 = eq(_T_11150, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45255,7 +45255,7 @@ circuit el2_ifu : node _T_11155 = and(_T_11152, _T_11154) @[el2_ifu_bp_ctl.scala 447:81] node _T_11156 = or(_T_11155, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11157 = bits(_T_11156, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11158 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11159 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11160 = eq(_T_11159, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45265,7 +45265,7 @@ circuit el2_ifu : node _T_11164 = and(_T_11161, _T_11163) @[el2_ifu_bp_ctl.scala 447:81] node _T_11165 = or(_T_11164, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11166 = bits(_T_11165, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] wire bht_bank_sel : UInt<1>[16][16][2] @[el2_ifu_bp_ctl.scala 449:26] node _T_11167 = bits(bht_wr_en0, 0, 0) @[el2_ifu_bp_ctl.scala 455:41] node _T_11168 = bits(mp_hashed, 3, 0) @[el2_ifu_bp_ctl.scala 455:60] @@ -62407,7 +62407,7 @@ circuit el2_ifu : module el2_ifu_aln_ctl : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}} + output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}} io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19] io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18] @@ -63516,62 +63516,62 @@ circuit el2_ifu : node _T_726 = and(_T_724, _T_725) @[el2_ifu_aln_ctl.scala 378:100] node _T_727 = or(_T_722, _T_726) @[el2_ifu_aln_ctl.scala 378:75] io.i0_brp.valid <= _T_727 @[el2_ifu_aln_ctl.scala 378:19] - node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:44] - node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:34] - node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:70] - node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:60] - node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:49] - io.i0_brp.bits.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:22] + node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:39] + node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:29] + node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:65] + node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:55] + node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:44] + io.i0_brp.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:17] node _T_733 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 382:39] node _T_734 = and(first2B, _T_733) @[el2_ifu_aln_ctl.scala 382:29] node _T_735 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 382:65] node _T_736 = and(first4B, _T_735) @[el2_ifu_aln_ctl.scala 382:55] node i0_brp_pc4 = or(_T_734, _T_736) @[el2_ifu_aln_ctl.scala 382:44] - node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:50] - node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:38] - node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:55] - node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:71] - node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:85] - node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:28] - io.i0_brp.bits.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:22] - node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:51] - node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:39] - node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:79] - node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:67] - node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:56] + node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:45] + node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:33] + node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:50] + node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:66] + node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:80] + node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:23] + io.i0_brp.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:17] + node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:46] + node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:34] + node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:74] + node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:62] + node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:51] node _T_748 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 387:26] node _T_749 = and(first2B, _T_748) @[el2_ifu_aln_ctl.scala 387:14] node _T_750 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 387:54] node _T_751 = and(first4B, _T_750) @[el2_ifu_aln_ctl.scala 387:42] node _T_752 = or(_T_749, _T_751) @[el2_ifu_aln_ctl.scala 387:31] node _T_753 = cat(_T_747, _T_752) @[Cat.scala 29:58] - io.i0_brp.bits.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:23] + io.i0_brp.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:18] node i0_ends_f1 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 389:28] - node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:44] - node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:32] - io.i0_brp.bits.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:26] - node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:42] - node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:30] - io.i0_brp.bits.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:24] - node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:56] - node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:46] - node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:72] - node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:60] - io.i0_brp.bits.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:34] - node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:62] - node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:50] - node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:67] - node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:82] - node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:95] - node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:40] - io.i0_brp.bits.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:34] - node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:47] - node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:61] - node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:94] - node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:92] - node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:106] - node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:73] - io.i0_brp.bits.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:27] + node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:39] + node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:27] + io.i0_brp.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:21] + node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:37] + node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:25] + io.i0_brp.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:19] + node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:51] + node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:41] + node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:67] + node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:55] + io.i0_brp.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:29] + node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:57] + node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:45] + node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:62] + node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:77] + node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:90] + node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:35] + io.i0_brp.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:29] + node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:42] + node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:56] + node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:89] + node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:87] + node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:101] + node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:68] + io.i0_brp.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:22] node _T_774 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 400:50] node _T_775 = or(first2B, _T_774) @[el2_ifu_aln_ctl.scala 400:38] node _T_776 = bits(_T_775, 0, 0) @[el2_ifu_aln_ctl.scala 400:55] @@ -63910,7 +63910,7 @@ circuit el2_ifu : module el2_ifu : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>} inst mem_ctl_ch of el2_ifu_mem_ctl @[el2_ifu.scala 146:26] mem_ctl_ch.clock <= clock @@ -63965,11 +63965,11 @@ circuit el2_ifu : bp_ctl_ch.io.ic_hit_f <= mem_ctl_ch.io.ic_hit_f @[el2_ifu.scala 195:25] bp_ctl_ch.io.ifc_fetch_addr_f <= ifc_ctl_ch.io.ifc_fetch_addr_f @[el2_ifu.scala 196:33] bp_ctl_ch.io.ifc_fetch_req_f <= ifc_ctl_ch.io.ifc_fetch_req_f @[el2_ifu.scala 197:32] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.middle <= io.dec_tlu_br0_r_pkt.bits.middle @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.way <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_start_error <= io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_error <= io.dec_tlu_br0_r_pkt.bits.br_error @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.hist <= io.dec_tlu_br0_r_pkt.bits.hist @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.middle <= io.dec_tlu_br0_r_pkt.middle @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.way <= io.dec_tlu_br0_r_pkt.way @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_start_error <= io.dec_tlu_br0_r_pkt.br_start_error @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_error <= io.dec_tlu_br0_r_pkt.br_error @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.hist <= io.dec_tlu_br0_r_pkt.hist @[el2_ifu.scala 198:34] bp_ctl_ch.io.dec_tlu_br0_r_pkt.valid <= io.dec_tlu_br0_r_pkt.valid @[el2_ifu.scala 198:34] bp_ctl_ch.io.exu_i0_br_fghr_r <= io.exu_i0_br_fghr_r @[el2_ifu.scala 199:33] bp_ctl_ch.io.exu_i0_br_index_r <= io.exu_i0_br_index_r @[el2_ifu.scala 200:34] @@ -64111,14 +64111,14 @@ circuit el2_ifu : io.ifu_i0_pc <= aln_ctl_ch.io.ifu_i0_pc @[el2_ifu.scala 327:16] io.ifu_i0_pc4 <= aln_ctl_ch.io.ifu_i0_pc4 @[el2_ifu.scala 328:17] io.ifu_miss_state_idle <= mem_ctl_ch.io.ifu_miss_state_idle @[el2_ifu.scala 329:26] - io.i0_brp.bits.ret <= aln_ctl_ch.io.i0_brp.bits.ret @[el2_ifu.scala 331:13] - io.i0_brp.bits.way <= aln_ctl_ch.io.i0_brp.bits.way @[el2_ifu.scala 331:13] - io.i0_brp.bits.prett <= aln_ctl_ch.io.i0_brp.bits.prett @[el2_ifu.scala 331:13] - io.i0_brp.bits.bank <= aln_ctl_ch.io.i0_brp.bits.bank @[el2_ifu.scala 331:13] - io.i0_brp.bits.br_start_error <= aln_ctl_ch.io.i0_brp.bits.br_start_error @[el2_ifu.scala 331:13] - io.i0_brp.bits.br_error <= aln_ctl_ch.io.i0_brp.bits.br_error @[el2_ifu.scala 331:13] - io.i0_brp.bits.hist <= aln_ctl_ch.io.i0_brp.bits.hist @[el2_ifu.scala 331:13] - io.i0_brp.bits.toffset <= aln_ctl_ch.io.i0_brp.bits.toffset @[el2_ifu.scala 331:13] + io.i0_brp.ret <= aln_ctl_ch.io.i0_brp.ret @[el2_ifu.scala 331:13] + io.i0_brp.way <= aln_ctl_ch.io.i0_brp.way @[el2_ifu.scala 331:13] + io.i0_brp.prett <= aln_ctl_ch.io.i0_brp.prett @[el2_ifu.scala 331:13] + io.i0_brp.bank <= aln_ctl_ch.io.i0_brp.bank @[el2_ifu.scala 331:13] + io.i0_brp.br_start_error <= aln_ctl_ch.io.i0_brp.br_start_error @[el2_ifu.scala 331:13] + io.i0_brp.br_error <= aln_ctl_ch.io.i0_brp.br_error @[el2_ifu.scala 331:13] + io.i0_brp.hist <= aln_ctl_ch.io.i0_brp.hist @[el2_ifu.scala 331:13] + io.i0_brp.toffset <= aln_ctl_ch.io.i0_brp.toffset @[el2_ifu.scala 331:13] io.i0_brp.valid <= aln_ctl_ch.io.i0_brp.valid @[el2_ifu.scala 331:13] io.ifu_i0_bp_index <= aln_ctl_ch.io.ifu_i0_bp_index @[el2_ifu.scala 332:22] io.ifu_i0_bp_fghr <= aln_ctl_ch.io.ifu_i0_bp_fghr @[el2_ifu.scala 333:21] diff --git a/el2_ifu.v b/el2_ifu.v index 21edbc0a..d149b538 100644 --- a/el2_ifu.v +++ b/el2_ifu.v @@ -11814,11 +11814,11 @@ module el2_ifu_bp_ctl( input [30:0] io_ifc_fetch_addr_f, input io_ifc_fetch_req_f, input io_dec_tlu_br0_r_pkt_valid, - input [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - input io_dec_tlu_br0_r_pkt_bits_br_error, - input io_dec_tlu_br0_r_pkt_bits_br_start_error, - input io_dec_tlu_br0_r_pkt_bits_way, - input io_dec_tlu_br0_r_pkt_bits_middle, + input [1:0] io_dec_tlu_br0_r_pkt_hist, + input io_dec_tlu_br0_r_pkt_br_error, + input io_dec_tlu_br0_r_pkt_br_start_error, + input io_dec_tlu_br0_r_pkt_way, + input io_dec_tlu_br0_r_pkt_middle, input [7:0] io_exu_i0_br_fghr_r, input [7:0] io_exu_i0_br_index_r, input io_dec_tlu_flush_lower_wb, @@ -15115,7 +15115,7 @@ module el2_ifu_bp_ctl( wire leak_one_f = _T_40 | _T_41; // @[el2_ifu_bp_ctl.scala 135:76] wire _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 72:51] wire exu_mp_valid = io_exu_mp_pkt_bits_misp & _T; // @[el2_ifu_bp_ctl.scala 72:49] - wire dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_bits_br_start_error | io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu_bp_ctl.scala 94:50] + wire dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_br_start_error | io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu_bp_ctl.scala 94:50] wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 191:47] wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 191:85] wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_bp_ctl.scala 102:51] @@ -21046,12 +21046,12 @@ module el2_ifu_bp_ctl( wire exu_mp_valid_write = exu_mp_valid & io_exu_mp_pkt_bits_ataken; // @[el2_ifu_bp_ctl.scala 397:41] wire _T_539 = _T_175 & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 400:39] wire _T_541 = _T_539 & _T_530; // @[el2_ifu_bp_ctl.scala 400:60] - wire _T_542 = ~io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu_bp_ctl.scala 400:87] + wire _T_542 = ~io_dec_tlu_br0_r_pkt_way; // @[el2_ifu_bp_ctl.scala 400:87] wire _T_543 = _T_542 & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 400:104] wire btb_wr_en_way0 = _T_541 | _T_543; // @[el2_ifu_bp_ctl.scala 400:83] wire _T_544 = io_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 401:36] wire _T_546 = _T_544 & _T_530; // @[el2_ifu_bp_ctl.scala 401:57] - wire _T_547 = io_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98] + wire _T_547 = io_dec_tlu_br0_r_pkt_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98] wire btb_wr_en_way1 = _T_546 | _T_547; // @[el2_ifu_bp_ctl.scala 401:80] wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_i0_br_index_r : io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 404:24] wire middle_of_bank = io_exu_mp_pkt_bits_pc4 ^ io_exu_mp_pkt_bits_boffset; // @[el2_ifu_bp_ctl.scala 405:35] @@ -21066,8 +21066,8 @@ module el2_ifu_bp_ctl( wire [1:0] _T_558 = {middle_of_bank,_T_557}; // @[Cat.scala 29:58] wire [1:0] bht_wr_en0 = _T_556 & _T_558; // @[el2_ifu_bp_ctl.scala 408:84] wire [1:0] _T_560 = io_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_561 = ~io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu_bp_ctl.scala 409:75] - wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_bits_middle,_T_561}; // @[Cat.scala 29:58] + wire _T_561 = ~io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu_bp_ctl.scala 409:75] + wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_middle,_T_561}; // @[Cat.scala 29:58] wire [1:0] bht_wr_en2 = _T_560 & _T_562; // @[el2_ifu_bp_ctl.scala 409:46] wire [9:0] _T_563 = {io_exu_mp_index,2'h0}; // @[Cat.scala 29:58] wire [7:0] mp_hashed = _T_563[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 196:35] @@ -35094,7 +35094,7 @@ end // initial if (reset) begin dec_tlu_way_wb_f <= 1'h0; end else begin - dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_bits_way; + dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_way; end end always @(posedge rvclkhdr_266_io_l1clk or posedge reset) begin @@ -36901,7 +36901,7 @@ end // initial bht_bank_rd_data_out_1_0 <= 2'h0; end else if (bht_bank_sel_1_0_0) begin if (_T_8869) begin - bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_0 <= io_exu_mp_pkt_bits_hist; end @@ -36912,7 +36912,7 @@ end // initial bht_bank_rd_data_out_1_1 <= 2'h0; end else if (bht_bank_sel_1_0_1) begin if (_T_8878) begin - bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_1 <= io_exu_mp_pkt_bits_hist; end @@ -36923,7 +36923,7 @@ end // initial bht_bank_rd_data_out_1_2 <= 2'h0; end else if (bht_bank_sel_1_0_2) begin if (_T_8887) begin - bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_2 <= io_exu_mp_pkt_bits_hist; end @@ -36934,7 +36934,7 @@ end // initial bht_bank_rd_data_out_1_3 <= 2'h0; end else if (bht_bank_sel_1_0_3) begin if (_T_8896) begin - bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_3 <= io_exu_mp_pkt_bits_hist; end @@ -36945,7 +36945,7 @@ end // initial bht_bank_rd_data_out_1_4 <= 2'h0; end else if (bht_bank_sel_1_0_4) begin if (_T_8905) begin - bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_4 <= io_exu_mp_pkt_bits_hist; end @@ -36956,7 +36956,7 @@ end // initial bht_bank_rd_data_out_1_5 <= 2'h0; end else if (bht_bank_sel_1_0_5) begin if (_T_8914) begin - bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_5 <= io_exu_mp_pkt_bits_hist; end @@ -36967,7 +36967,7 @@ end // initial bht_bank_rd_data_out_1_6 <= 2'h0; end else if (bht_bank_sel_1_0_6) begin if (_T_8923) begin - bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_6 <= io_exu_mp_pkt_bits_hist; end @@ -36978,7 +36978,7 @@ end // initial bht_bank_rd_data_out_1_7 <= 2'h0; end else if (bht_bank_sel_1_0_7) begin if (_T_8932) begin - bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_7 <= io_exu_mp_pkt_bits_hist; end @@ -36989,7 +36989,7 @@ end // initial bht_bank_rd_data_out_1_8 <= 2'h0; end else if (bht_bank_sel_1_0_8) begin if (_T_8941) begin - bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_8 <= io_exu_mp_pkt_bits_hist; end @@ -37000,7 +37000,7 @@ end // initial bht_bank_rd_data_out_1_9 <= 2'h0; end else if (bht_bank_sel_1_0_9) begin if (_T_8950) begin - bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_9 <= io_exu_mp_pkt_bits_hist; end @@ -37011,7 +37011,7 @@ end // initial bht_bank_rd_data_out_1_10 <= 2'h0; end else if (bht_bank_sel_1_0_10) begin if (_T_8959) begin - bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_10 <= io_exu_mp_pkt_bits_hist; end @@ -37022,7 +37022,7 @@ end // initial bht_bank_rd_data_out_1_11 <= 2'h0; end else if (bht_bank_sel_1_0_11) begin if (_T_8968) begin - bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_11 <= io_exu_mp_pkt_bits_hist; end @@ -37033,7 +37033,7 @@ end // initial bht_bank_rd_data_out_1_12 <= 2'h0; end else if (bht_bank_sel_1_0_12) begin if (_T_8977) begin - bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_12 <= io_exu_mp_pkt_bits_hist; end @@ -37044,7 +37044,7 @@ end // initial bht_bank_rd_data_out_1_13 <= 2'h0; end else if (bht_bank_sel_1_0_13) begin if (_T_8986) begin - bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_13 <= io_exu_mp_pkt_bits_hist; end @@ -37055,7 +37055,7 @@ end // initial bht_bank_rd_data_out_1_14 <= 2'h0; end else if (bht_bank_sel_1_0_14) begin if (_T_8995) begin - bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_14 <= io_exu_mp_pkt_bits_hist; end @@ -37066,7 +37066,7 @@ end // initial bht_bank_rd_data_out_1_15 <= 2'h0; end else if (bht_bank_sel_1_0_15) begin if (_T_9004) begin - bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_15 <= io_exu_mp_pkt_bits_hist; end @@ -37077,7 +37077,7 @@ end // initial bht_bank_rd_data_out_1_16 <= 2'h0; end else if (bht_bank_sel_1_1_0) begin if (_T_9013) begin - bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_16 <= io_exu_mp_pkt_bits_hist; end @@ -37088,7 +37088,7 @@ end // initial bht_bank_rd_data_out_1_17 <= 2'h0; end else if (bht_bank_sel_1_1_1) begin if (_T_9022) begin - bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_17 <= io_exu_mp_pkt_bits_hist; end @@ -37099,7 +37099,7 @@ end // initial bht_bank_rd_data_out_1_18 <= 2'h0; end else if (bht_bank_sel_1_1_2) begin if (_T_9031) begin - bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_18 <= io_exu_mp_pkt_bits_hist; end @@ -37110,7 +37110,7 @@ end // initial bht_bank_rd_data_out_1_19 <= 2'h0; end else if (bht_bank_sel_1_1_3) begin if (_T_9040) begin - bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_19 <= io_exu_mp_pkt_bits_hist; end @@ -37121,7 +37121,7 @@ end // initial bht_bank_rd_data_out_1_20 <= 2'h0; end else if (bht_bank_sel_1_1_4) begin if (_T_9049) begin - bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_20 <= io_exu_mp_pkt_bits_hist; end @@ -37132,7 +37132,7 @@ end // initial bht_bank_rd_data_out_1_21 <= 2'h0; end else if (bht_bank_sel_1_1_5) begin if (_T_9058) begin - bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_21 <= io_exu_mp_pkt_bits_hist; end @@ -37143,7 +37143,7 @@ end // initial bht_bank_rd_data_out_1_22 <= 2'h0; end else if (bht_bank_sel_1_1_6) begin if (_T_9067) begin - bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_22 <= io_exu_mp_pkt_bits_hist; end @@ -37154,7 +37154,7 @@ end // initial bht_bank_rd_data_out_1_23 <= 2'h0; end else if (bht_bank_sel_1_1_7) begin if (_T_9076) begin - bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_23 <= io_exu_mp_pkt_bits_hist; end @@ -37165,7 +37165,7 @@ end // initial bht_bank_rd_data_out_1_24 <= 2'h0; end else if (bht_bank_sel_1_1_8) begin if (_T_9085) begin - bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_24 <= io_exu_mp_pkt_bits_hist; end @@ -37176,7 +37176,7 @@ end // initial bht_bank_rd_data_out_1_25 <= 2'h0; end else if (bht_bank_sel_1_1_9) begin if (_T_9094) begin - bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_25 <= io_exu_mp_pkt_bits_hist; end @@ -37187,7 +37187,7 @@ end // initial bht_bank_rd_data_out_1_26 <= 2'h0; end else if (bht_bank_sel_1_1_10) begin if (_T_9103) begin - bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_26 <= io_exu_mp_pkt_bits_hist; end @@ -37198,7 +37198,7 @@ end // initial bht_bank_rd_data_out_1_27 <= 2'h0; end else if (bht_bank_sel_1_1_11) begin if (_T_9112) begin - bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_27 <= io_exu_mp_pkt_bits_hist; end @@ -37209,7 +37209,7 @@ end // initial bht_bank_rd_data_out_1_28 <= 2'h0; end else if (bht_bank_sel_1_1_12) begin if (_T_9121) begin - bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_28 <= io_exu_mp_pkt_bits_hist; end @@ -37220,7 +37220,7 @@ end // initial bht_bank_rd_data_out_1_29 <= 2'h0; end else if (bht_bank_sel_1_1_13) begin if (_T_9130) begin - bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_29 <= io_exu_mp_pkt_bits_hist; end @@ -37231,7 +37231,7 @@ end // initial bht_bank_rd_data_out_1_30 <= 2'h0; end else if (bht_bank_sel_1_1_14) begin if (_T_9139) begin - bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_30 <= io_exu_mp_pkt_bits_hist; end @@ -37242,7 +37242,7 @@ end // initial bht_bank_rd_data_out_1_31 <= 2'h0; end else if (bht_bank_sel_1_1_15) begin if (_T_9148) begin - bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_31 <= io_exu_mp_pkt_bits_hist; end @@ -37253,7 +37253,7 @@ end // initial bht_bank_rd_data_out_1_32 <= 2'h0; end else if (bht_bank_sel_1_2_0) begin if (_T_9157) begin - bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_32 <= io_exu_mp_pkt_bits_hist; end @@ -37264,7 +37264,7 @@ end // initial bht_bank_rd_data_out_1_33 <= 2'h0; end else if (bht_bank_sel_1_2_1) begin if (_T_9166) begin - bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_33 <= io_exu_mp_pkt_bits_hist; end @@ -37275,7 +37275,7 @@ end // initial bht_bank_rd_data_out_1_34 <= 2'h0; end else if (bht_bank_sel_1_2_2) begin if (_T_9175) begin - bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_34 <= io_exu_mp_pkt_bits_hist; end @@ -37286,7 +37286,7 @@ end // initial bht_bank_rd_data_out_1_35 <= 2'h0; end else if (bht_bank_sel_1_2_3) begin if (_T_9184) begin - bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_35 <= io_exu_mp_pkt_bits_hist; end @@ -37297,7 +37297,7 @@ end // initial bht_bank_rd_data_out_1_36 <= 2'h0; end else if (bht_bank_sel_1_2_4) begin if (_T_9193) begin - bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_36 <= io_exu_mp_pkt_bits_hist; end @@ -37308,7 +37308,7 @@ end // initial bht_bank_rd_data_out_1_37 <= 2'h0; end else if (bht_bank_sel_1_2_5) begin if (_T_9202) begin - bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_37 <= io_exu_mp_pkt_bits_hist; end @@ -37319,7 +37319,7 @@ end // initial bht_bank_rd_data_out_1_38 <= 2'h0; end else if (bht_bank_sel_1_2_6) begin if (_T_9211) begin - bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_38 <= io_exu_mp_pkt_bits_hist; end @@ -37330,7 +37330,7 @@ end // initial bht_bank_rd_data_out_1_39 <= 2'h0; end else if (bht_bank_sel_1_2_7) begin if (_T_9220) begin - bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_39 <= io_exu_mp_pkt_bits_hist; end @@ -37341,7 +37341,7 @@ end // initial bht_bank_rd_data_out_1_40 <= 2'h0; end else if (bht_bank_sel_1_2_8) begin if (_T_9229) begin - bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_40 <= io_exu_mp_pkt_bits_hist; end @@ -37352,7 +37352,7 @@ end // initial bht_bank_rd_data_out_1_41 <= 2'h0; end else if (bht_bank_sel_1_2_9) begin if (_T_9238) begin - bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_41 <= io_exu_mp_pkt_bits_hist; end @@ -37363,7 +37363,7 @@ end // initial bht_bank_rd_data_out_1_42 <= 2'h0; end else if (bht_bank_sel_1_2_10) begin if (_T_9247) begin - bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_42 <= io_exu_mp_pkt_bits_hist; end @@ -37374,7 +37374,7 @@ end // initial bht_bank_rd_data_out_1_43 <= 2'h0; end else if (bht_bank_sel_1_2_11) begin if (_T_9256) begin - bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_43 <= io_exu_mp_pkt_bits_hist; end @@ -37385,7 +37385,7 @@ end // initial bht_bank_rd_data_out_1_44 <= 2'h0; end else if (bht_bank_sel_1_2_12) begin if (_T_9265) begin - bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_44 <= io_exu_mp_pkt_bits_hist; end @@ -37396,7 +37396,7 @@ end // initial bht_bank_rd_data_out_1_45 <= 2'h0; end else if (bht_bank_sel_1_2_13) begin if (_T_9274) begin - bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_45 <= io_exu_mp_pkt_bits_hist; end @@ -37407,7 +37407,7 @@ end // initial bht_bank_rd_data_out_1_46 <= 2'h0; end else if (bht_bank_sel_1_2_14) begin if (_T_9283) begin - bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_46 <= io_exu_mp_pkt_bits_hist; end @@ -37418,7 +37418,7 @@ end // initial bht_bank_rd_data_out_1_47 <= 2'h0; end else if (bht_bank_sel_1_2_15) begin if (_T_9292) begin - bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_47 <= io_exu_mp_pkt_bits_hist; end @@ -37429,7 +37429,7 @@ end // initial bht_bank_rd_data_out_1_48 <= 2'h0; end else if (bht_bank_sel_1_3_0) begin if (_T_9301) begin - bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_48 <= io_exu_mp_pkt_bits_hist; end @@ -37440,7 +37440,7 @@ end // initial bht_bank_rd_data_out_1_49 <= 2'h0; end else if (bht_bank_sel_1_3_1) begin if (_T_9310) begin - bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_49 <= io_exu_mp_pkt_bits_hist; end @@ -37451,7 +37451,7 @@ end // initial bht_bank_rd_data_out_1_50 <= 2'h0; end else if (bht_bank_sel_1_3_2) begin if (_T_9319) begin - bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_50 <= io_exu_mp_pkt_bits_hist; end @@ -37462,7 +37462,7 @@ end // initial bht_bank_rd_data_out_1_51 <= 2'h0; end else if (bht_bank_sel_1_3_3) begin if (_T_9328) begin - bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_51 <= io_exu_mp_pkt_bits_hist; end @@ -37473,7 +37473,7 @@ end // initial bht_bank_rd_data_out_1_52 <= 2'h0; end else if (bht_bank_sel_1_3_4) begin if (_T_9337) begin - bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_52 <= io_exu_mp_pkt_bits_hist; end @@ -37484,7 +37484,7 @@ end // initial bht_bank_rd_data_out_1_53 <= 2'h0; end else if (bht_bank_sel_1_3_5) begin if (_T_9346) begin - bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_53 <= io_exu_mp_pkt_bits_hist; end @@ -37495,7 +37495,7 @@ end // initial bht_bank_rd_data_out_1_54 <= 2'h0; end else if (bht_bank_sel_1_3_6) begin if (_T_9355) begin - bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_54 <= io_exu_mp_pkt_bits_hist; end @@ -37506,7 +37506,7 @@ end // initial bht_bank_rd_data_out_1_55 <= 2'h0; end else if (bht_bank_sel_1_3_7) begin if (_T_9364) begin - bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_55 <= io_exu_mp_pkt_bits_hist; end @@ -37517,7 +37517,7 @@ end // initial bht_bank_rd_data_out_1_56 <= 2'h0; end else if (bht_bank_sel_1_3_8) begin if (_T_9373) begin - bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_56 <= io_exu_mp_pkt_bits_hist; end @@ -37528,7 +37528,7 @@ end // initial bht_bank_rd_data_out_1_57 <= 2'h0; end else if (bht_bank_sel_1_3_9) begin if (_T_9382) begin - bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_57 <= io_exu_mp_pkt_bits_hist; end @@ -37539,7 +37539,7 @@ end // initial bht_bank_rd_data_out_1_58 <= 2'h0; end else if (bht_bank_sel_1_3_10) begin if (_T_9391) begin - bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_58 <= io_exu_mp_pkt_bits_hist; end @@ -37550,7 +37550,7 @@ end // initial bht_bank_rd_data_out_1_59 <= 2'h0; end else if (bht_bank_sel_1_3_11) begin if (_T_9400) begin - bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_59 <= io_exu_mp_pkt_bits_hist; end @@ -37561,7 +37561,7 @@ end // initial bht_bank_rd_data_out_1_60 <= 2'h0; end else if (bht_bank_sel_1_3_12) begin if (_T_9409) begin - bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_60 <= io_exu_mp_pkt_bits_hist; end @@ -37572,7 +37572,7 @@ end // initial bht_bank_rd_data_out_1_61 <= 2'h0; end else if (bht_bank_sel_1_3_13) begin if (_T_9418) begin - bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_61 <= io_exu_mp_pkt_bits_hist; end @@ -37583,7 +37583,7 @@ end // initial bht_bank_rd_data_out_1_62 <= 2'h0; end else if (bht_bank_sel_1_3_14) begin if (_T_9427) begin - bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_62 <= io_exu_mp_pkt_bits_hist; end @@ -37594,7 +37594,7 @@ end // initial bht_bank_rd_data_out_1_63 <= 2'h0; end else if (bht_bank_sel_1_3_15) begin if (_T_9436) begin - bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_63 <= io_exu_mp_pkt_bits_hist; end @@ -37605,7 +37605,7 @@ end // initial bht_bank_rd_data_out_1_64 <= 2'h0; end else if (bht_bank_sel_1_4_0) begin if (_T_9445) begin - bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_64 <= io_exu_mp_pkt_bits_hist; end @@ -37616,7 +37616,7 @@ end // initial bht_bank_rd_data_out_1_65 <= 2'h0; end else if (bht_bank_sel_1_4_1) begin if (_T_9454) begin - bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_65 <= io_exu_mp_pkt_bits_hist; end @@ -37627,7 +37627,7 @@ end // initial bht_bank_rd_data_out_1_66 <= 2'h0; end else if (bht_bank_sel_1_4_2) begin if (_T_9463) begin - bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_66 <= io_exu_mp_pkt_bits_hist; end @@ -37638,7 +37638,7 @@ end // initial bht_bank_rd_data_out_1_67 <= 2'h0; end else if (bht_bank_sel_1_4_3) begin if (_T_9472) begin - bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_67 <= io_exu_mp_pkt_bits_hist; end @@ -37649,7 +37649,7 @@ end // initial bht_bank_rd_data_out_1_68 <= 2'h0; end else if (bht_bank_sel_1_4_4) begin if (_T_9481) begin - bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_68 <= io_exu_mp_pkt_bits_hist; end @@ -37660,7 +37660,7 @@ end // initial bht_bank_rd_data_out_1_69 <= 2'h0; end else if (bht_bank_sel_1_4_5) begin if (_T_9490) begin - bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_69 <= io_exu_mp_pkt_bits_hist; end @@ -37671,7 +37671,7 @@ end // initial bht_bank_rd_data_out_1_70 <= 2'h0; end else if (bht_bank_sel_1_4_6) begin if (_T_9499) begin - bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_70 <= io_exu_mp_pkt_bits_hist; end @@ -37682,7 +37682,7 @@ end // initial bht_bank_rd_data_out_1_71 <= 2'h0; end else if (bht_bank_sel_1_4_7) begin if (_T_9508) begin - bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_71 <= io_exu_mp_pkt_bits_hist; end @@ -37693,7 +37693,7 @@ end // initial bht_bank_rd_data_out_1_72 <= 2'h0; end else if (bht_bank_sel_1_4_8) begin if (_T_9517) begin - bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_72 <= io_exu_mp_pkt_bits_hist; end @@ -37704,7 +37704,7 @@ end // initial bht_bank_rd_data_out_1_73 <= 2'h0; end else if (bht_bank_sel_1_4_9) begin if (_T_9526) begin - bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_73 <= io_exu_mp_pkt_bits_hist; end @@ -37715,7 +37715,7 @@ end // initial bht_bank_rd_data_out_1_74 <= 2'h0; end else if (bht_bank_sel_1_4_10) begin if (_T_9535) begin - bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_74 <= io_exu_mp_pkt_bits_hist; end @@ -37726,7 +37726,7 @@ end // initial bht_bank_rd_data_out_1_75 <= 2'h0; end else if (bht_bank_sel_1_4_11) begin if (_T_9544) begin - bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_75 <= io_exu_mp_pkt_bits_hist; end @@ -37737,7 +37737,7 @@ end // initial bht_bank_rd_data_out_1_76 <= 2'h0; end else if (bht_bank_sel_1_4_12) begin if (_T_9553) begin - bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_76 <= io_exu_mp_pkt_bits_hist; end @@ -37748,7 +37748,7 @@ end // initial bht_bank_rd_data_out_1_77 <= 2'h0; end else if (bht_bank_sel_1_4_13) begin if (_T_9562) begin - bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_77 <= io_exu_mp_pkt_bits_hist; end @@ -37759,7 +37759,7 @@ end // initial bht_bank_rd_data_out_1_78 <= 2'h0; end else if (bht_bank_sel_1_4_14) begin if (_T_9571) begin - bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_78 <= io_exu_mp_pkt_bits_hist; end @@ -37770,7 +37770,7 @@ end // initial bht_bank_rd_data_out_1_79 <= 2'h0; end else if (bht_bank_sel_1_4_15) begin if (_T_9580) begin - bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_79 <= io_exu_mp_pkt_bits_hist; end @@ -37781,7 +37781,7 @@ end // initial bht_bank_rd_data_out_1_80 <= 2'h0; end else if (bht_bank_sel_1_5_0) begin if (_T_9589) begin - bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_80 <= io_exu_mp_pkt_bits_hist; end @@ -37792,7 +37792,7 @@ end // initial bht_bank_rd_data_out_1_81 <= 2'h0; end else if (bht_bank_sel_1_5_1) begin if (_T_9598) begin - bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_81 <= io_exu_mp_pkt_bits_hist; end @@ -37803,7 +37803,7 @@ end // initial bht_bank_rd_data_out_1_82 <= 2'h0; end else if (bht_bank_sel_1_5_2) begin if (_T_9607) begin - bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_82 <= io_exu_mp_pkt_bits_hist; end @@ -37814,7 +37814,7 @@ end // initial bht_bank_rd_data_out_1_83 <= 2'h0; end else if (bht_bank_sel_1_5_3) begin if (_T_9616) begin - bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_83 <= io_exu_mp_pkt_bits_hist; end @@ -37825,7 +37825,7 @@ end // initial bht_bank_rd_data_out_1_84 <= 2'h0; end else if (bht_bank_sel_1_5_4) begin if (_T_9625) begin - bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_84 <= io_exu_mp_pkt_bits_hist; end @@ -37836,7 +37836,7 @@ end // initial bht_bank_rd_data_out_1_85 <= 2'h0; end else if (bht_bank_sel_1_5_5) begin if (_T_9634) begin - bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_85 <= io_exu_mp_pkt_bits_hist; end @@ -37847,7 +37847,7 @@ end // initial bht_bank_rd_data_out_1_86 <= 2'h0; end else if (bht_bank_sel_1_5_6) begin if (_T_9643) begin - bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_86 <= io_exu_mp_pkt_bits_hist; end @@ -37858,7 +37858,7 @@ end // initial bht_bank_rd_data_out_1_87 <= 2'h0; end else if (bht_bank_sel_1_5_7) begin if (_T_9652) begin - bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_87 <= io_exu_mp_pkt_bits_hist; end @@ -37869,7 +37869,7 @@ end // initial bht_bank_rd_data_out_1_88 <= 2'h0; end else if (bht_bank_sel_1_5_8) begin if (_T_9661) begin - bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_88 <= io_exu_mp_pkt_bits_hist; end @@ -37880,7 +37880,7 @@ end // initial bht_bank_rd_data_out_1_89 <= 2'h0; end else if (bht_bank_sel_1_5_9) begin if (_T_9670) begin - bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_89 <= io_exu_mp_pkt_bits_hist; end @@ -37891,7 +37891,7 @@ end // initial bht_bank_rd_data_out_1_90 <= 2'h0; end else if (bht_bank_sel_1_5_10) begin if (_T_9679) begin - bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_90 <= io_exu_mp_pkt_bits_hist; end @@ -37902,7 +37902,7 @@ end // initial bht_bank_rd_data_out_1_91 <= 2'h0; end else if (bht_bank_sel_1_5_11) begin if (_T_9688) begin - bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_91 <= io_exu_mp_pkt_bits_hist; end @@ -37913,7 +37913,7 @@ end // initial bht_bank_rd_data_out_1_92 <= 2'h0; end else if (bht_bank_sel_1_5_12) begin if (_T_9697) begin - bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_92 <= io_exu_mp_pkt_bits_hist; end @@ -37924,7 +37924,7 @@ end // initial bht_bank_rd_data_out_1_93 <= 2'h0; end else if (bht_bank_sel_1_5_13) begin if (_T_9706) begin - bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_93 <= io_exu_mp_pkt_bits_hist; end @@ -37935,7 +37935,7 @@ end // initial bht_bank_rd_data_out_1_94 <= 2'h0; end else if (bht_bank_sel_1_5_14) begin if (_T_9715) begin - bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_94 <= io_exu_mp_pkt_bits_hist; end @@ -37946,7 +37946,7 @@ end // initial bht_bank_rd_data_out_1_95 <= 2'h0; end else if (bht_bank_sel_1_5_15) begin if (_T_9724) begin - bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_95 <= io_exu_mp_pkt_bits_hist; end @@ -37957,7 +37957,7 @@ end // initial bht_bank_rd_data_out_1_96 <= 2'h0; end else if (bht_bank_sel_1_6_0) begin if (_T_9733) begin - bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_96 <= io_exu_mp_pkt_bits_hist; end @@ -37968,7 +37968,7 @@ end // initial bht_bank_rd_data_out_1_97 <= 2'h0; end else if (bht_bank_sel_1_6_1) begin if (_T_9742) begin - bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_97 <= io_exu_mp_pkt_bits_hist; end @@ -37979,7 +37979,7 @@ end // initial bht_bank_rd_data_out_1_98 <= 2'h0; end else if (bht_bank_sel_1_6_2) begin if (_T_9751) begin - bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_98 <= io_exu_mp_pkt_bits_hist; end @@ -37990,7 +37990,7 @@ end // initial bht_bank_rd_data_out_1_99 <= 2'h0; end else if (bht_bank_sel_1_6_3) begin if (_T_9760) begin - bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_99 <= io_exu_mp_pkt_bits_hist; end @@ -38001,7 +38001,7 @@ end // initial bht_bank_rd_data_out_1_100 <= 2'h0; end else if (bht_bank_sel_1_6_4) begin if (_T_9769) begin - bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_100 <= io_exu_mp_pkt_bits_hist; end @@ -38012,7 +38012,7 @@ end // initial bht_bank_rd_data_out_1_101 <= 2'h0; end else if (bht_bank_sel_1_6_5) begin if (_T_9778) begin - bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_101 <= io_exu_mp_pkt_bits_hist; end @@ -38023,7 +38023,7 @@ end // initial bht_bank_rd_data_out_1_102 <= 2'h0; end else if (bht_bank_sel_1_6_6) begin if (_T_9787) begin - bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_102 <= io_exu_mp_pkt_bits_hist; end @@ -38034,7 +38034,7 @@ end // initial bht_bank_rd_data_out_1_103 <= 2'h0; end else if (bht_bank_sel_1_6_7) begin if (_T_9796) begin - bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_103 <= io_exu_mp_pkt_bits_hist; end @@ -38045,7 +38045,7 @@ end // initial bht_bank_rd_data_out_1_104 <= 2'h0; end else if (bht_bank_sel_1_6_8) begin if (_T_9805) begin - bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_104 <= io_exu_mp_pkt_bits_hist; end @@ -38056,7 +38056,7 @@ end // initial bht_bank_rd_data_out_1_105 <= 2'h0; end else if (bht_bank_sel_1_6_9) begin if (_T_9814) begin - bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_105 <= io_exu_mp_pkt_bits_hist; end @@ -38067,7 +38067,7 @@ end // initial bht_bank_rd_data_out_1_106 <= 2'h0; end else if (bht_bank_sel_1_6_10) begin if (_T_9823) begin - bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_106 <= io_exu_mp_pkt_bits_hist; end @@ -38078,7 +38078,7 @@ end // initial bht_bank_rd_data_out_1_107 <= 2'h0; end else if (bht_bank_sel_1_6_11) begin if (_T_9832) begin - bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_107 <= io_exu_mp_pkt_bits_hist; end @@ -38089,7 +38089,7 @@ end // initial bht_bank_rd_data_out_1_108 <= 2'h0; end else if (bht_bank_sel_1_6_12) begin if (_T_9841) begin - bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_108 <= io_exu_mp_pkt_bits_hist; end @@ -38100,7 +38100,7 @@ end // initial bht_bank_rd_data_out_1_109 <= 2'h0; end else if (bht_bank_sel_1_6_13) begin if (_T_9850) begin - bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_109 <= io_exu_mp_pkt_bits_hist; end @@ -38111,7 +38111,7 @@ end // initial bht_bank_rd_data_out_1_110 <= 2'h0; end else if (bht_bank_sel_1_6_14) begin if (_T_9859) begin - bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_110 <= io_exu_mp_pkt_bits_hist; end @@ -38122,7 +38122,7 @@ end // initial bht_bank_rd_data_out_1_111 <= 2'h0; end else if (bht_bank_sel_1_6_15) begin if (_T_9868) begin - bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_111 <= io_exu_mp_pkt_bits_hist; end @@ -38133,7 +38133,7 @@ end // initial bht_bank_rd_data_out_1_112 <= 2'h0; end else if (bht_bank_sel_1_7_0) begin if (_T_9877) begin - bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_112 <= io_exu_mp_pkt_bits_hist; end @@ -38144,7 +38144,7 @@ end // initial bht_bank_rd_data_out_1_113 <= 2'h0; end else if (bht_bank_sel_1_7_1) begin if (_T_9886) begin - bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_113 <= io_exu_mp_pkt_bits_hist; end @@ -38155,7 +38155,7 @@ end // initial bht_bank_rd_data_out_1_114 <= 2'h0; end else if (bht_bank_sel_1_7_2) begin if (_T_9895) begin - bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_114 <= io_exu_mp_pkt_bits_hist; end @@ -38166,7 +38166,7 @@ end // initial bht_bank_rd_data_out_1_115 <= 2'h0; end else if (bht_bank_sel_1_7_3) begin if (_T_9904) begin - bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_115 <= io_exu_mp_pkt_bits_hist; end @@ -38177,7 +38177,7 @@ end // initial bht_bank_rd_data_out_1_116 <= 2'h0; end else if (bht_bank_sel_1_7_4) begin if (_T_9913) begin - bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_116 <= io_exu_mp_pkt_bits_hist; end @@ -38188,7 +38188,7 @@ end // initial bht_bank_rd_data_out_1_117 <= 2'h0; end else if (bht_bank_sel_1_7_5) begin if (_T_9922) begin - bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_117 <= io_exu_mp_pkt_bits_hist; end @@ -38199,7 +38199,7 @@ end // initial bht_bank_rd_data_out_1_118 <= 2'h0; end else if (bht_bank_sel_1_7_6) begin if (_T_9931) begin - bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_118 <= io_exu_mp_pkt_bits_hist; end @@ -38210,7 +38210,7 @@ end // initial bht_bank_rd_data_out_1_119 <= 2'h0; end else if (bht_bank_sel_1_7_7) begin if (_T_9940) begin - bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_119 <= io_exu_mp_pkt_bits_hist; end @@ -38221,7 +38221,7 @@ end // initial bht_bank_rd_data_out_1_120 <= 2'h0; end else if (bht_bank_sel_1_7_8) begin if (_T_9949) begin - bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_120 <= io_exu_mp_pkt_bits_hist; end @@ -38232,7 +38232,7 @@ end // initial bht_bank_rd_data_out_1_121 <= 2'h0; end else if (bht_bank_sel_1_7_9) begin if (_T_9958) begin - bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_121 <= io_exu_mp_pkt_bits_hist; end @@ -38243,7 +38243,7 @@ end // initial bht_bank_rd_data_out_1_122 <= 2'h0; end else if (bht_bank_sel_1_7_10) begin if (_T_9967) begin - bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_122 <= io_exu_mp_pkt_bits_hist; end @@ -38254,7 +38254,7 @@ end // initial bht_bank_rd_data_out_1_123 <= 2'h0; end else if (bht_bank_sel_1_7_11) begin if (_T_9976) begin - bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_123 <= io_exu_mp_pkt_bits_hist; end @@ -38265,7 +38265,7 @@ end // initial bht_bank_rd_data_out_1_124 <= 2'h0; end else if (bht_bank_sel_1_7_12) begin if (_T_9985) begin - bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_124 <= io_exu_mp_pkt_bits_hist; end @@ -38276,7 +38276,7 @@ end // initial bht_bank_rd_data_out_1_125 <= 2'h0; end else if (bht_bank_sel_1_7_13) begin if (_T_9994) begin - bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_125 <= io_exu_mp_pkt_bits_hist; end @@ -38287,7 +38287,7 @@ end // initial bht_bank_rd_data_out_1_126 <= 2'h0; end else if (bht_bank_sel_1_7_14) begin if (_T_10003) begin - bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_126 <= io_exu_mp_pkt_bits_hist; end @@ -38298,7 +38298,7 @@ end // initial bht_bank_rd_data_out_1_127 <= 2'h0; end else if (bht_bank_sel_1_7_15) begin if (_T_10012) begin - bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_127 <= io_exu_mp_pkt_bits_hist; end @@ -38309,7 +38309,7 @@ end // initial bht_bank_rd_data_out_1_128 <= 2'h0; end else if (bht_bank_sel_1_8_0) begin if (_T_10021) begin - bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_128 <= io_exu_mp_pkt_bits_hist; end @@ -38320,7 +38320,7 @@ end // initial bht_bank_rd_data_out_1_129 <= 2'h0; end else if (bht_bank_sel_1_8_1) begin if (_T_10030) begin - bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_129 <= io_exu_mp_pkt_bits_hist; end @@ -38331,7 +38331,7 @@ end // initial bht_bank_rd_data_out_1_130 <= 2'h0; end else if (bht_bank_sel_1_8_2) begin if (_T_10039) begin - bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_130 <= io_exu_mp_pkt_bits_hist; end @@ -38342,7 +38342,7 @@ end // initial bht_bank_rd_data_out_1_131 <= 2'h0; end else if (bht_bank_sel_1_8_3) begin if (_T_10048) begin - bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_131 <= io_exu_mp_pkt_bits_hist; end @@ -38353,7 +38353,7 @@ end // initial bht_bank_rd_data_out_1_132 <= 2'h0; end else if (bht_bank_sel_1_8_4) begin if (_T_10057) begin - bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_132 <= io_exu_mp_pkt_bits_hist; end @@ -38364,7 +38364,7 @@ end // initial bht_bank_rd_data_out_1_133 <= 2'h0; end else if (bht_bank_sel_1_8_5) begin if (_T_10066) begin - bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_133 <= io_exu_mp_pkt_bits_hist; end @@ -38375,7 +38375,7 @@ end // initial bht_bank_rd_data_out_1_134 <= 2'h0; end else if (bht_bank_sel_1_8_6) begin if (_T_10075) begin - bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_134 <= io_exu_mp_pkt_bits_hist; end @@ -38386,7 +38386,7 @@ end // initial bht_bank_rd_data_out_1_135 <= 2'h0; end else if (bht_bank_sel_1_8_7) begin if (_T_10084) begin - bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_135 <= io_exu_mp_pkt_bits_hist; end @@ -38397,7 +38397,7 @@ end // initial bht_bank_rd_data_out_1_136 <= 2'h0; end else if (bht_bank_sel_1_8_8) begin if (_T_10093) begin - bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_136 <= io_exu_mp_pkt_bits_hist; end @@ -38408,7 +38408,7 @@ end // initial bht_bank_rd_data_out_1_137 <= 2'h0; end else if (bht_bank_sel_1_8_9) begin if (_T_10102) begin - bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_137 <= io_exu_mp_pkt_bits_hist; end @@ -38419,7 +38419,7 @@ end // initial bht_bank_rd_data_out_1_138 <= 2'h0; end else if (bht_bank_sel_1_8_10) begin if (_T_10111) begin - bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_138 <= io_exu_mp_pkt_bits_hist; end @@ -38430,7 +38430,7 @@ end // initial bht_bank_rd_data_out_1_139 <= 2'h0; end else if (bht_bank_sel_1_8_11) begin if (_T_10120) begin - bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_139 <= io_exu_mp_pkt_bits_hist; end @@ -38441,7 +38441,7 @@ end // initial bht_bank_rd_data_out_1_140 <= 2'h0; end else if (bht_bank_sel_1_8_12) begin if (_T_10129) begin - bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_140 <= io_exu_mp_pkt_bits_hist; end @@ -38452,7 +38452,7 @@ end // initial bht_bank_rd_data_out_1_141 <= 2'h0; end else if (bht_bank_sel_1_8_13) begin if (_T_10138) begin - bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_141 <= io_exu_mp_pkt_bits_hist; end @@ -38463,7 +38463,7 @@ end // initial bht_bank_rd_data_out_1_142 <= 2'h0; end else if (bht_bank_sel_1_8_14) begin if (_T_10147) begin - bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_142 <= io_exu_mp_pkt_bits_hist; end @@ -38474,7 +38474,7 @@ end // initial bht_bank_rd_data_out_1_143 <= 2'h0; end else if (bht_bank_sel_1_8_15) begin if (_T_10156) begin - bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_143 <= io_exu_mp_pkt_bits_hist; end @@ -38485,7 +38485,7 @@ end // initial bht_bank_rd_data_out_1_144 <= 2'h0; end else if (bht_bank_sel_1_9_0) begin if (_T_10165) begin - bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_144 <= io_exu_mp_pkt_bits_hist; end @@ -38496,7 +38496,7 @@ end // initial bht_bank_rd_data_out_1_145 <= 2'h0; end else if (bht_bank_sel_1_9_1) begin if (_T_10174) begin - bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_145 <= io_exu_mp_pkt_bits_hist; end @@ -38507,7 +38507,7 @@ end // initial bht_bank_rd_data_out_1_146 <= 2'h0; end else if (bht_bank_sel_1_9_2) begin if (_T_10183) begin - bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_146 <= io_exu_mp_pkt_bits_hist; end @@ -38518,7 +38518,7 @@ end // initial bht_bank_rd_data_out_1_147 <= 2'h0; end else if (bht_bank_sel_1_9_3) begin if (_T_10192) begin - bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_147 <= io_exu_mp_pkt_bits_hist; end @@ -38529,7 +38529,7 @@ end // initial bht_bank_rd_data_out_1_148 <= 2'h0; end else if (bht_bank_sel_1_9_4) begin if (_T_10201) begin - bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_148 <= io_exu_mp_pkt_bits_hist; end @@ -38540,7 +38540,7 @@ end // initial bht_bank_rd_data_out_1_149 <= 2'h0; end else if (bht_bank_sel_1_9_5) begin if (_T_10210) begin - bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_149 <= io_exu_mp_pkt_bits_hist; end @@ -38551,7 +38551,7 @@ end // initial bht_bank_rd_data_out_1_150 <= 2'h0; end else if (bht_bank_sel_1_9_6) begin if (_T_10219) begin - bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_150 <= io_exu_mp_pkt_bits_hist; end @@ -38562,7 +38562,7 @@ end // initial bht_bank_rd_data_out_1_151 <= 2'h0; end else if (bht_bank_sel_1_9_7) begin if (_T_10228) begin - bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_151 <= io_exu_mp_pkt_bits_hist; end @@ -38573,7 +38573,7 @@ end // initial bht_bank_rd_data_out_1_152 <= 2'h0; end else if (bht_bank_sel_1_9_8) begin if (_T_10237) begin - bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_152 <= io_exu_mp_pkt_bits_hist; end @@ -38584,7 +38584,7 @@ end // initial bht_bank_rd_data_out_1_153 <= 2'h0; end else if (bht_bank_sel_1_9_9) begin if (_T_10246) begin - bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_153 <= io_exu_mp_pkt_bits_hist; end @@ -38595,7 +38595,7 @@ end // initial bht_bank_rd_data_out_1_154 <= 2'h0; end else if (bht_bank_sel_1_9_10) begin if (_T_10255) begin - bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_154 <= io_exu_mp_pkt_bits_hist; end @@ -38606,7 +38606,7 @@ end // initial bht_bank_rd_data_out_1_155 <= 2'h0; end else if (bht_bank_sel_1_9_11) begin if (_T_10264) begin - bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_155 <= io_exu_mp_pkt_bits_hist; end @@ -38617,7 +38617,7 @@ end // initial bht_bank_rd_data_out_1_156 <= 2'h0; end else if (bht_bank_sel_1_9_12) begin if (_T_10273) begin - bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_156 <= io_exu_mp_pkt_bits_hist; end @@ -38628,7 +38628,7 @@ end // initial bht_bank_rd_data_out_1_157 <= 2'h0; end else if (bht_bank_sel_1_9_13) begin if (_T_10282) begin - bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_157 <= io_exu_mp_pkt_bits_hist; end @@ -38639,7 +38639,7 @@ end // initial bht_bank_rd_data_out_1_158 <= 2'h0; end else if (bht_bank_sel_1_9_14) begin if (_T_10291) begin - bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_158 <= io_exu_mp_pkt_bits_hist; end @@ -38650,7 +38650,7 @@ end // initial bht_bank_rd_data_out_1_159 <= 2'h0; end else if (bht_bank_sel_1_9_15) begin if (_T_10300) begin - bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_159 <= io_exu_mp_pkt_bits_hist; end @@ -38661,7 +38661,7 @@ end // initial bht_bank_rd_data_out_1_160 <= 2'h0; end else if (bht_bank_sel_1_10_0) begin if (_T_10309) begin - bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_160 <= io_exu_mp_pkt_bits_hist; end @@ -38672,7 +38672,7 @@ end // initial bht_bank_rd_data_out_1_161 <= 2'h0; end else if (bht_bank_sel_1_10_1) begin if (_T_10318) begin - bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_161 <= io_exu_mp_pkt_bits_hist; end @@ -38683,7 +38683,7 @@ end // initial bht_bank_rd_data_out_1_162 <= 2'h0; end else if (bht_bank_sel_1_10_2) begin if (_T_10327) begin - bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_162 <= io_exu_mp_pkt_bits_hist; end @@ -38694,7 +38694,7 @@ end // initial bht_bank_rd_data_out_1_163 <= 2'h0; end else if (bht_bank_sel_1_10_3) begin if (_T_10336) begin - bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_163 <= io_exu_mp_pkt_bits_hist; end @@ -38705,7 +38705,7 @@ end // initial bht_bank_rd_data_out_1_164 <= 2'h0; end else if (bht_bank_sel_1_10_4) begin if (_T_10345) begin - bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_164 <= io_exu_mp_pkt_bits_hist; end @@ -38716,7 +38716,7 @@ end // initial bht_bank_rd_data_out_1_165 <= 2'h0; end else if (bht_bank_sel_1_10_5) begin if (_T_10354) begin - bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_165 <= io_exu_mp_pkt_bits_hist; end @@ -38727,7 +38727,7 @@ end // initial bht_bank_rd_data_out_1_166 <= 2'h0; end else if (bht_bank_sel_1_10_6) begin if (_T_10363) begin - bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_166 <= io_exu_mp_pkt_bits_hist; end @@ -38738,7 +38738,7 @@ end // initial bht_bank_rd_data_out_1_167 <= 2'h0; end else if (bht_bank_sel_1_10_7) begin if (_T_10372) begin - bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_167 <= io_exu_mp_pkt_bits_hist; end @@ -38749,7 +38749,7 @@ end // initial bht_bank_rd_data_out_1_168 <= 2'h0; end else if (bht_bank_sel_1_10_8) begin if (_T_10381) begin - bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_168 <= io_exu_mp_pkt_bits_hist; end @@ -38760,7 +38760,7 @@ end // initial bht_bank_rd_data_out_1_169 <= 2'h0; end else if (bht_bank_sel_1_10_9) begin if (_T_10390) begin - bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_169 <= io_exu_mp_pkt_bits_hist; end @@ -38771,7 +38771,7 @@ end // initial bht_bank_rd_data_out_1_170 <= 2'h0; end else if (bht_bank_sel_1_10_10) begin if (_T_10399) begin - bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_170 <= io_exu_mp_pkt_bits_hist; end @@ -38782,7 +38782,7 @@ end // initial bht_bank_rd_data_out_1_171 <= 2'h0; end else if (bht_bank_sel_1_10_11) begin if (_T_10408) begin - bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_171 <= io_exu_mp_pkt_bits_hist; end @@ -38793,7 +38793,7 @@ end // initial bht_bank_rd_data_out_1_172 <= 2'h0; end else if (bht_bank_sel_1_10_12) begin if (_T_10417) begin - bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_172 <= io_exu_mp_pkt_bits_hist; end @@ -38804,7 +38804,7 @@ end // initial bht_bank_rd_data_out_1_173 <= 2'h0; end else if (bht_bank_sel_1_10_13) begin if (_T_10426) begin - bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_173 <= io_exu_mp_pkt_bits_hist; end @@ -38815,7 +38815,7 @@ end // initial bht_bank_rd_data_out_1_174 <= 2'h0; end else if (bht_bank_sel_1_10_14) begin if (_T_10435) begin - bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_174 <= io_exu_mp_pkt_bits_hist; end @@ -38826,7 +38826,7 @@ end // initial bht_bank_rd_data_out_1_175 <= 2'h0; end else if (bht_bank_sel_1_10_15) begin if (_T_10444) begin - bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_175 <= io_exu_mp_pkt_bits_hist; end @@ -38837,7 +38837,7 @@ end // initial bht_bank_rd_data_out_1_176 <= 2'h0; end else if (bht_bank_sel_1_11_0) begin if (_T_10453) begin - bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_176 <= io_exu_mp_pkt_bits_hist; end @@ -38848,7 +38848,7 @@ end // initial bht_bank_rd_data_out_1_177 <= 2'h0; end else if (bht_bank_sel_1_11_1) begin if (_T_10462) begin - bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_177 <= io_exu_mp_pkt_bits_hist; end @@ -38859,7 +38859,7 @@ end // initial bht_bank_rd_data_out_1_178 <= 2'h0; end else if (bht_bank_sel_1_11_2) begin if (_T_10471) begin - bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_178 <= io_exu_mp_pkt_bits_hist; end @@ -38870,7 +38870,7 @@ end // initial bht_bank_rd_data_out_1_179 <= 2'h0; end else if (bht_bank_sel_1_11_3) begin if (_T_10480) begin - bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_179 <= io_exu_mp_pkt_bits_hist; end @@ -38881,7 +38881,7 @@ end // initial bht_bank_rd_data_out_1_180 <= 2'h0; end else if (bht_bank_sel_1_11_4) begin if (_T_10489) begin - bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_180 <= io_exu_mp_pkt_bits_hist; end @@ -38892,7 +38892,7 @@ end // initial bht_bank_rd_data_out_1_181 <= 2'h0; end else if (bht_bank_sel_1_11_5) begin if (_T_10498) begin - bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_181 <= io_exu_mp_pkt_bits_hist; end @@ -38903,7 +38903,7 @@ end // initial bht_bank_rd_data_out_1_182 <= 2'h0; end else if (bht_bank_sel_1_11_6) begin if (_T_10507) begin - bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_182 <= io_exu_mp_pkt_bits_hist; end @@ -38914,7 +38914,7 @@ end // initial bht_bank_rd_data_out_1_183 <= 2'h0; end else if (bht_bank_sel_1_11_7) begin if (_T_10516) begin - bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_183 <= io_exu_mp_pkt_bits_hist; end @@ -38925,7 +38925,7 @@ end // initial bht_bank_rd_data_out_1_184 <= 2'h0; end else if (bht_bank_sel_1_11_8) begin if (_T_10525) begin - bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_184 <= io_exu_mp_pkt_bits_hist; end @@ -38936,7 +38936,7 @@ end // initial bht_bank_rd_data_out_1_185 <= 2'h0; end else if (bht_bank_sel_1_11_9) begin if (_T_10534) begin - bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_185 <= io_exu_mp_pkt_bits_hist; end @@ -38947,7 +38947,7 @@ end // initial bht_bank_rd_data_out_1_186 <= 2'h0; end else if (bht_bank_sel_1_11_10) begin if (_T_10543) begin - bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_186 <= io_exu_mp_pkt_bits_hist; end @@ -38958,7 +38958,7 @@ end // initial bht_bank_rd_data_out_1_187 <= 2'h0; end else if (bht_bank_sel_1_11_11) begin if (_T_10552) begin - bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_187 <= io_exu_mp_pkt_bits_hist; end @@ -38969,7 +38969,7 @@ end // initial bht_bank_rd_data_out_1_188 <= 2'h0; end else if (bht_bank_sel_1_11_12) begin if (_T_10561) begin - bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_188 <= io_exu_mp_pkt_bits_hist; end @@ -38980,7 +38980,7 @@ end // initial bht_bank_rd_data_out_1_189 <= 2'h0; end else if (bht_bank_sel_1_11_13) begin if (_T_10570) begin - bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_189 <= io_exu_mp_pkt_bits_hist; end @@ -38991,7 +38991,7 @@ end // initial bht_bank_rd_data_out_1_190 <= 2'h0; end else if (bht_bank_sel_1_11_14) begin if (_T_10579) begin - bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_190 <= io_exu_mp_pkt_bits_hist; end @@ -39002,7 +39002,7 @@ end // initial bht_bank_rd_data_out_1_191 <= 2'h0; end else if (bht_bank_sel_1_11_15) begin if (_T_10588) begin - bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_191 <= io_exu_mp_pkt_bits_hist; end @@ -39013,7 +39013,7 @@ end // initial bht_bank_rd_data_out_1_192 <= 2'h0; end else if (bht_bank_sel_1_12_0) begin if (_T_10597) begin - bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_192 <= io_exu_mp_pkt_bits_hist; end @@ -39024,7 +39024,7 @@ end // initial bht_bank_rd_data_out_1_193 <= 2'h0; end else if (bht_bank_sel_1_12_1) begin if (_T_10606) begin - bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_193 <= io_exu_mp_pkt_bits_hist; end @@ -39035,7 +39035,7 @@ end // initial bht_bank_rd_data_out_1_194 <= 2'h0; end else if (bht_bank_sel_1_12_2) begin if (_T_10615) begin - bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_194 <= io_exu_mp_pkt_bits_hist; end @@ -39046,7 +39046,7 @@ end // initial bht_bank_rd_data_out_1_195 <= 2'h0; end else if (bht_bank_sel_1_12_3) begin if (_T_10624) begin - bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_195 <= io_exu_mp_pkt_bits_hist; end @@ -39057,7 +39057,7 @@ end // initial bht_bank_rd_data_out_1_196 <= 2'h0; end else if (bht_bank_sel_1_12_4) begin if (_T_10633) begin - bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_196 <= io_exu_mp_pkt_bits_hist; end @@ -39068,7 +39068,7 @@ end // initial bht_bank_rd_data_out_1_197 <= 2'h0; end else if (bht_bank_sel_1_12_5) begin if (_T_10642) begin - bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_197 <= io_exu_mp_pkt_bits_hist; end @@ -39079,7 +39079,7 @@ end // initial bht_bank_rd_data_out_1_198 <= 2'h0; end else if (bht_bank_sel_1_12_6) begin if (_T_10651) begin - bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_198 <= io_exu_mp_pkt_bits_hist; end @@ -39090,7 +39090,7 @@ end // initial bht_bank_rd_data_out_1_199 <= 2'h0; end else if (bht_bank_sel_1_12_7) begin if (_T_10660) begin - bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_199 <= io_exu_mp_pkt_bits_hist; end @@ -39101,7 +39101,7 @@ end // initial bht_bank_rd_data_out_1_200 <= 2'h0; end else if (bht_bank_sel_1_12_8) begin if (_T_10669) begin - bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_200 <= io_exu_mp_pkt_bits_hist; end @@ -39112,7 +39112,7 @@ end // initial bht_bank_rd_data_out_1_201 <= 2'h0; end else if (bht_bank_sel_1_12_9) begin if (_T_10678) begin - bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_201 <= io_exu_mp_pkt_bits_hist; end @@ -39123,7 +39123,7 @@ end // initial bht_bank_rd_data_out_1_202 <= 2'h0; end else if (bht_bank_sel_1_12_10) begin if (_T_10687) begin - bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_202 <= io_exu_mp_pkt_bits_hist; end @@ -39134,7 +39134,7 @@ end // initial bht_bank_rd_data_out_1_203 <= 2'h0; end else if (bht_bank_sel_1_12_11) begin if (_T_10696) begin - bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_203 <= io_exu_mp_pkt_bits_hist; end @@ -39145,7 +39145,7 @@ end // initial bht_bank_rd_data_out_1_204 <= 2'h0; end else if (bht_bank_sel_1_12_12) begin if (_T_10705) begin - bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_204 <= io_exu_mp_pkt_bits_hist; end @@ -39156,7 +39156,7 @@ end // initial bht_bank_rd_data_out_1_205 <= 2'h0; end else if (bht_bank_sel_1_12_13) begin if (_T_10714) begin - bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_205 <= io_exu_mp_pkt_bits_hist; end @@ -39167,7 +39167,7 @@ end // initial bht_bank_rd_data_out_1_206 <= 2'h0; end else if (bht_bank_sel_1_12_14) begin if (_T_10723) begin - bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_206 <= io_exu_mp_pkt_bits_hist; end @@ -39178,7 +39178,7 @@ end // initial bht_bank_rd_data_out_1_207 <= 2'h0; end else if (bht_bank_sel_1_12_15) begin if (_T_10732) begin - bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_207 <= io_exu_mp_pkt_bits_hist; end @@ -39189,7 +39189,7 @@ end // initial bht_bank_rd_data_out_1_208 <= 2'h0; end else if (bht_bank_sel_1_13_0) begin if (_T_10741) begin - bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_208 <= io_exu_mp_pkt_bits_hist; end @@ -39200,7 +39200,7 @@ end // initial bht_bank_rd_data_out_1_209 <= 2'h0; end else if (bht_bank_sel_1_13_1) begin if (_T_10750) begin - bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_209 <= io_exu_mp_pkt_bits_hist; end @@ -39211,7 +39211,7 @@ end // initial bht_bank_rd_data_out_1_210 <= 2'h0; end else if (bht_bank_sel_1_13_2) begin if (_T_10759) begin - bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_210 <= io_exu_mp_pkt_bits_hist; end @@ -39222,7 +39222,7 @@ end // initial bht_bank_rd_data_out_1_211 <= 2'h0; end else if (bht_bank_sel_1_13_3) begin if (_T_10768) begin - bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_211 <= io_exu_mp_pkt_bits_hist; end @@ -39233,7 +39233,7 @@ end // initial bht_bank_rd_data_out_1_212 <= 2'h0; end else if (bht_bank_sel_1_13_4) begin if (_T_10777) begin - bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_212 <= io_exu_mp_pkt_bits_hist; end @@ -39244,7 +39244,7 @@ end // initial bht_bank_rd_data_out_1_213 <= 2'h0; end else if (bht_bank_sel_1_13_5) begin if (_T_10786) begin - bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_213 <= io_exu_mp_pkt_bits_hist; end @@ -39255,7 +39255,7 @@ end // initial bht_bank_rd_data_out_1_214 <= 2'h0; end else if (bht_bank_sel_1_13_6) begin if (_T_10795) begin - bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_214 <= io_exu_mp_pkt_bits_hist; end @@ -39266,7 +39266,7 @@ end // initial bht_bank_rd_data_out_1_215 <= 2'h0; end else if (bht_bank_sel_1_13_7) begin if (_T_10804) begin - bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_215 <= io_exu_mp_pkt_bits_hist; end @@ -39277,7 +39277,7 @@ end // initial bht_bank_rd_data_out_1_216 <= 2'h0; end else if (bht_bank_sel_1_13_8) begin if (_T_10813) begin - bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_216 <= io_exu_mp_pkt_bits_hist; end @@ -39288,7 +39288,7 @@ end // initial bht_bank_rd_data_out_1_217 <= 2'h0; end else if (bht_bank_sel_1_13_9) begin if (_T_10822) begin - bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_217 <= io_exu_mp_pkt_bits_hist; end @@ -39299,7 +39299,7 @@ end // initial bht_bank_rd_data_out_1_218 <= 2'h0; end else if (bht_bank_sel_1_13_10) begin if (_T_10831) begin - bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_218 <= io_exu_mp_pkt_bits_hist; end @@ -39310,7 +39310,7 @@ end // initial bht_bank_rd_data_out_1_219 <= 2'h0; end else if (bht_bank_sel_1_13_11) begin if (_T_10840) begin - bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_219 <= io_exu_mp_pkt_bits_hist; end @@ -39321,7 +39321,7 @@ end // initial bht_bank_rd_data_out_1_220 <= 2'h0; end else if (bht_bank_sel_1_13_12) begin if (_T_10849) begin - bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_220 <= io_exu_mp_pkt_bits_hist; end @@ -39332,7 +39332,7 @@ end // initial bht_bank_rd_data_out_1_221 <= 2'h0; end else if (bht_bank_sel_1_13_13) begin if (_T_10858) begin - bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_221 <= io_exu_mp_pkt_bits_hist; end @@ -39343,7 +39343,7 @@ end // initial bht_bank_rd_data_out_1_222 <= 2'h0; end else if (bht_bank_sel_1_13_14) begin if (_T_10867) begin - bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_222 <= io_exu_mp_pkt_bits_hist; end @@ -39354,7 +39354,7 @@ end // initial bht_bank_rd_data_out_1_223 <= 2'h0; end else if (bht_bank_sel_1_13_15) begin if (_T_10876) begin - bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_223 <= io_exu_mp_pkt_bits_hist; end @@ -39365,7 +39365,7 @@ end // initial bht_bank_rd_data_out_1_224 <= 2'h0; end else if (bht_bank_sel_1_14_0) begin if (_T_10885) begin - bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_224 <= io_exu_mp_pkt_bits_hist; end @@ -39376,7 +39376,7 @@ end // initial bht_bank_rd_data_out_1_225 <= 2'h0; end else if (bht_bank_sel_1_14_1) begin if (_T_10894) begin - bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_225 <= io_exu_mp_pkt_bits_hist; end @@ -39387,7 +39387,7 @@ end // initial bht_bank_rd_data_out_1_226 <= 2'h0; end else if (bht_bank_sel_1_14_2) begin if (_T_10903) begin - bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_226 <= io_exu_mp_pkt_bits_hist; end @@ -39398,7 +39398,7 @@ end // initial bht_bank_rd_data_out_1_227 <= 2'h0; end else if (bht_bank_sel_1_14_3) begin if (_T_10912) begin - bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_227 <= io_exu_mp_pkt_bits_hist; end @@ -39409,7 +39409,7 @@ end // initial bht_bank_rd_data_out_1_228 <= 2'h0; end else if (bht_bank_sel_1_14_4) begin if (_T_10921) begin - bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_228 <= io_exu_mp_pkt_bits_hist; end @@ -39420,7 +39420,7 @@ end // initial bht_bank_rd_data_out_1_229 <= 2'h0; end else if (bht_bank_sel_1_14_5) begin if (_T_10930) begin - bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_229 <= io_exu_mp_pkt_bits_hist; end @@ -39431,7 +39431,7 @@ end // initial bht_bank_rd_data_out_1_230 <= 2'h0; end else if (bht_bank_sel_1_14_6) begin if (_T_10939) begin - bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_230 <= io_exu_mp_pkt_bits_hist; end @@ -39442,7 +39442,7 @@ end // initial bht_bank_rd_data_out_1_231 <= 2'h0; end else if (bht_bank_sel_1_14_7) begin if (_T_10948) begin - bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_231 <= io_exu_mp_pkt_bits_hist; end @@ -39453,7 +39453,7 @@ end // initial bht_bank_rd_data_out_1_232 <= 2'h0; end else if (bht_bank_sel_1_14_8) begin if (_T_10957) begin - bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_232 <= io_exu_mp_pkt_bits_hist; end @@ -39464,7 +39464,7 @@ end // initial bht_bank_rd_data_out_1_233 <= 2'h0; end else if (bht_bank_sel_1_14_9) begin if (_T_10966) begin - bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_233 <= io_exu_mp_pkt_bits_hist; end @@ -39475,7 +39475,7 @@ end // initial bht_bank_rd_data_out_1_234 <= 2'h0; end else if (bht_bank_sel_1_14_10) begin if (_T_10975) begin - bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_234 <= io_exu_mp_pkt_bits_hist; end @@ -39486,7 +39486,7 @@ end // initial bht_bank_rd_data_out_1_235 <= 2'h0; end else if (bht_bank_sel_1_14_11) begin if (_T_10984) begin - bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_235 <= io_exu_mp_pkt_bits_hist; end @@ -39497,7 +39497,7 @@ end // initial bht_bank_rd_data_out_1_236 <= 2'h0; end else if (bht_bank_sel_1_14_12) begin if (_T_10993) begin - bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_236 <= io_exu_mp_pkt_bits_hist; end @@ -39508,7 +39508,7 @@ end // initial bht_bank_rd_data_out_1_237 <= 2'h0; end else if (bht_bank_sel_1_14_13) begin if (_T_11002) begin - bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_237 <= io_exu_mp_pkt_bits_hist; end @@ -39519,7 +39519,7 @@ end // initial bht_bank_rd_data_out_1_238 <= 2'h0; end else if (bht_bank_sel_1_14_14) begin if (_T_11011) begin - bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_238 <= io_exu_mp_pkt_bits_hist; end @@ -39530,7 +39530,7 @@ end // initial bht_bank_rd_data_out_1_239 <= 2'h0; end else if (bht_bank_sel_1_14_15) begin if (_T_11020) begin - bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_239 <= io_exu_mp_pkt_bits_hist; end @@ -39541,7 +39541,7 @@ end // initial bht_bank_rd_data_out_1_240 <= 2'h0; end else if (bht_bank_sel_1_15_0) begin if (_T_11029) begin - bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_240 <= io_exu_mp_pkt_bits_hist; end @@ -39552,7 +39552,7 @@ end // initial bht_bank_rd_data_out_1_241 <= 2'h0; end else if (bht_bank_sel_1_15_1) begin if (_T_11038) begin - bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_241 <= io_exu_mp_pkt_bits_hist; end @@ -39563,7 +39563,7 @@ end // initial bht_bank_rd_data_out_1_242 <= 2'h0; end else if (bht_bank_sel_1_15_2) begin if (_T_11047) begin - bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_242 <= io_exu_mp_pkt_bits_hist; end @@ -39574,7 +39574,7 @@ end // initial bht_bank_rd_data_out_1_243 <= 2'h0; end else if (bht_bank_sel_1_15_3) begin if (_T_11056) begin - bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_243 <= io_exu_mp_pkt_bits_hist; end @@ -39585,7 +39585,7 @@ end // initial bht_bank_rd_data_out_1_244 <= 2'h0; end else if (bht_bank_sel_1_15_4) begin if (_T_11065) begin - bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_244 <= io_exu_mp_pkt_bits_hist; end @@ -39596,7 +39596,7 @@ end // initial bht_bank_rd_data_out_1_245 <= 2'h0; end else if (bht_bank_sel_1_15_5) begin if (_T_11074) begin - bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_245 <= io_exu_mp_pkt_bits_hist; end @@ -39607,7 +39607,7 @@ end // initial bht_bank_rd_data_out_1_246 <= 2'h0; end else if (bht_bank_sel_1_15_6) begin if (_T_11083) begin - bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_246 <= io_exu_mp_pkt_bits_hist; end @@ -39618,7 +39618,7 @@ end // initial bht_bank_rd_data_out_1_247 <= 2'h0; end else if (bht_bank_sel_1_15_7) begin if (_T_11092) begin - bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_247 <= io_exu_mp_pkt_bits_hist; end @@ -39629,7 +39629,7 @@ end // initial bht_bank_rd_data_out_1_248 <= 2'h0; end else if (bht_bank_sel_1_15_8) begin if (_T_11101) begin - bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_248 <= io_exu_mp_pkt_bits_hist; end @@ -39640,7 +39640,7 @@ end // initial bht_bank_rd_data_out_1_249 <= 2'h0; end else if (bht_bank_sel_1_15_9) begin if (_T_11110) begin - bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_249 <= io_exu_mp_pkt_bits_hist; end @@ -39651,7 +39651,7 @@ end // initial bht_bank_rd_data_out_1_250 <= 2'h0; end else if (bht_bank_sel_1_15_10) begin if (_T_11119) begin - bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_250 <= io_exu_mp_pkt_bits_hist; end @@ -39662,7 +39662,7 @@ end // initial bht_bank_rd_data_out_1_251 <= 2'h0; end else if (bht_bank_sel_1_15_11) begin if (_T_11128) begin - bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_251 <= io_exu_mp_pkt_bits_hist; end @@ -39673,7 +39673,7 @@ end // initial bht_bank_rd_data_out_1_252 <= 2'h0; end else if (bht_bank_sel_1_15_12) begin if (_T_11137) begin - bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_252 <= io_exu_mp_pkt_bits_hist; end @@ -39684,7 +39684,7 @@ end // initial bht_bank_rd_data_out_1_253 <= 2'h0; end else if (bht_bank_sel_1_15_13) begin if (_T_11146) begin - bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_253 <= io_exu_mp_pkt_bits_hist; end @@ -39695,7 +39695,7 @@ end // initial bht_bank_rd_data_out_1_254 <= 2'h0; end else if (bht_bank_sel_1_15_14) begin if (_T_11155) begin - bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_254 <= io_exu_mp_pkt_bits_hist; end @@ -39706,7 +39706,7 @@ end // initial bht_bank_rd_data_out_1_255 <= 2'h0; end else if (bht_bank_sel_1_15_15) begin if (_T_11164) begin - bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_255 <= io_exu_mp_pkt_bits_hist; end @@ -39717,7 +39717,7 @@ end // initial bht_bank_rd_data_out_0_0 <= 2'h0; end else if (bht_bank_sel_0_0_0) begin if (_T_6565) begin - bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_0 <= io_exu_mp_pkt_bits_hist; end @@ -39728,7 +39728,7 @@ end // initial bht_bank_rd_data_out_0_1 <= 2'h0; end else if (bht_bank_sel_0_0_1) begin if (_T_6574) begin - bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_1 <= io_exu_mp_pkt_bits_hist; end @@ -39739,7 +39739,7 @@ end // initial bht_bank_rd_data_out_0_2 <= 2'h0; end else if (bht_bank_sel_0_0_2) begin if (_T_6583) begin - bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_2 <= io_exu_mp_pkt_bits_hist; end @@ -39750,7 +39750,7 @@ end // initial bht_bank_rd_data_out_0_3 <= 2'h0; end else if (bht_bank_sel_0_0_3) begin if (_T_6592) begin - bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_3 <= io_exu_mp_pkt_bits_hist; end @@ -39761,7 +39761,7 @@ end // initial bht_bank_rd_data_out_0_4 <= 2'h0; end else if (bht_bank_sel_0_0_4) begin if (_T_6601) begin - bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_4 <= io_exu_mp_pkt_bits_hist; end @@ -39772,7 +39772,7 @@ end // initial bht_bank_rd_data_out_0_5 <= 2'h0; end else if (bht_bank_sel_0_0_5) begin if (_T_6610) begin - bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_5 <= io_exu_mp_pkt_bits_hist; end @@ -39783,7 +39783,7 @@ end // initial bht_bank_rd_data_out_0_6 <= 2'h0; end else if (bht_bank_sel_0_0_6) begin if (_T_6619) begin - bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_6 <= io_exu_mp_pkt_bits_hist; end @@ -39794,7 +39794,7 @@ end // initial bht_bank_rd_data_out_0_7 <= 2'h0; end else if (bht_bank_sel_0_0_7) begin if (_T_6628) begin - bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_7 <= io_exu_mp_pkt_bits_hist; end @@ -39805,7 +39805,7 @@ end // initial bht_bank_rd_data_out_0_8 <= 2'h0; end else if (bht_bank_sel_0_0_8) begin if (_T_6637) begin - bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_8 <= io_exu_mp_pkt_bits_hist; end @@ -39816,7 +39816,7 @@ end // initial bht_bank_rd_data_out_0_9 <= 2'h0; end else if (bht_bank_sel_0_0_9) begin if (_T_6646) begin - bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_9 <= io_exu_mp_pkt_bits_hist; end @@ -39827,7 +39827,7 @@ end // initial bht_bank_rd_data_out_0_10 <= 2'h0; end else if (bht_bank_sel_0_0_10) begin if (_T_6655) begin - bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_10 <= io_exu_mp_pkt_bits_hist; end @@ -39838,7 +39838,7 @@ end // initial bht_bank_rd_data_out_0_11 <= 2'h0; end else if (bht_bank_sel_0_0_11) begin if (_T_6664) begin - bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_11 <= io_exu_mp_pkt_bits_hist; end @@ -39849,7 +39849,7 @@ end // initial bht_bank_rd_data_out_0_12 <= 2'h0; end else if (bht_bank_sel_0_0_12) begin if (_T_6673) begin - bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_12 <= io_exu_mp_pkt_bits_hist; end @@ -39860,7 +39860,7 @@ end // initial bht_bank_rd_data_out_0_13 <= 2'h0; end else if (bht_bank_sel_0_0_13) begin if (_T_6682) begin - bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_13 <= io_exu_mp_pkt_bits_hist; end @@ -39871,7 +39871,7 @@ end // initial bht_bank_rd_data_out_0_14 <= 2'h0; end else if (bht_bank_sel_0_0_14) begin if (_T_6691) begin - bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_14 <= io_exu_mp_pkt_bits_hist; end @@ -39882,7 +39882,7 @@ end // initial bht_bank_rd_data_out_0_15 <= 2'h0; end else if (bht_bank_sel_0_0_15) begin if (_T_6700) begin - bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_15 <= io_exu_mp_pkt_bits_hist; end @@ -39893,7 +39893,7 @@ end // initial bht_bank_rd_data_out_0_16 <= 2'h0; end else if (bht_bank_sel_0_1_0) begin if (_T_6709) begin - bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_16 <= io_exu_mp_pkt_bits_hist; end @@ -39904,7 +39904,7 @@ end // initial bht_bank_rd_data_out_0_17 <= 2'h0; end else if (bht_bank_sel_0_1_1) begin if (_T_6718) begin - bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_17 <= io_exu_mp_pkt_bits_hist; end @@ -39915,7 +39915,7 @@ end // initial bht_bank_rd_data_out_0_18 <= 2'h0; end else if (bht_bank_sel_0_1_2) begin if (_T_6727) begin - bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_18 <= io_exu_mp_pkt_bits_hist; end @@ -39926,7 +39926,7 @@ end // initial bht_bank_rd_data_out_0_19 <= 2'h0; end else if (bht_bank_sel_0_1_3) begin if (_T_6736) begin - bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_19 <= io_exu_mp_pkt_bits_hist; end @@ -39937,7 +39937,7 @@ end // initial bht_bank_rd_data_out_0_20 <= 2'h0; end else if (bht_bank_sel_0_1_4) begin if (_T_6745) begin - bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_20 <= io_exu_mp_pkt_bits_hist; end @@ -39948,7 +39948,7 @@ end // initial bht_bank_rd_data_out_0_21 <= 2'h0; end else if (bht_bank_sel_0_1_5) begin if (_T_6754) begin - bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_21 <= io_exu_mp_pkt_bits_hist; end @@ -39959,7 +39959,7 @@ end // initial bht_bank_rd_data_out_0_22 <= 2'h0; end else if (bht_bank_sel_0_1_6) begin if (_T_6763) begin - bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_22 <= io_exu_mp_pkt_bits_hist; end @@ -39970,7 +39970,7 @@ end // initial bht_bank_rd_data_out_0_23 <= 2'h0; end else if (bht_bank_sel_0_1_7) begin if (_T_6772) begin - bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_23 <= io_exu_mp_pkt_bits_hist; end @@ -39981,7 +39981,7 @@ end // initial bht_bank_rd_data_out_0_24 <= 2'h0; end else if (bht_bank_sel_0_1_8) begin if (_T_6781) begin - bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_24 <= io_exu_mp_pkt_bits_hist; end @@ -39992,7 +39992,7 @@ end // initial bht_bank_rd_data_out_0_25 <= 2'h0; end else if (bht_bank_sel_0_1_9) begin if (_T_6790) begin - bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_25 <= io_exu_mp_pkt_bits_hist; end @@ -40003,7 +40003,7 @@ end // initial bht_bank_rd_data_out_0_26 <= 2'h0; end else if (bht_bank_sel_0_1_10) begin if (_T_6799) begin - bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_26 <= io_exu_mp_pkt_bits_hist; end @@ -40014,7 +40014,7 @@ end // initial bht_bank_rd_data_out_0_27 <= 2'h0; end else if (bht_bank_sel_0_1_11) begin if (_T_6808) begin - bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_27 <= io_exu_mp_pkt_bits_hist; end @@ -40025,7 +40025,7 @@ end // initial bht_bank_rd_data_out_0_28 <= 2'h0; end else if (bht_bank_sel_0_1_12) begin if (_T_6817) begin - bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_28 <= io_exu_mp_pkt_bits_hist; end @@ -40036,7 +40036,7 @@ end // initial bht_bank_rd_data_out_0_29 <= 2'h0; end else if (bht_bank_sel_0_1_13) begin if (_T_6826) begin - bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_29 <= io_exu_mp_pkt_bits_hist; end @@ -40047,7 +40047,7 @@ end // initial bht_bank_rd_data_out_0_30 <= 2'h0; end else if (bht_bank_sel_0_1_14) begin if (_T_6835) begin - bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_30 <= io_exu_mp_pkt_bits_hist; end @@ -40058,7 +40058,7 @@ end // initial bht_bank_rd_data_out_0_31 <= 2'h0; end else if (bht_bank_sel_0_1_15) begin if (_T_6844) begin - bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_31 <= io_exu_mp_pkt_bits_hist; end @@ -40069,7 +40069,7 @@ end // initial bht_bank_rd_data_out_0_32 <= 2'h0; end else if (bht_bank_sel_0_2_0) begin if (_T_6853) begin - bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_32 <= io_exu_mp_pkt_bits_hist; end @@ -40080,7 +40080,7 @@ end // initial bht_bank_rd_data_out_0_33 <= 2'h0; end else if (bht_bank_sel_0_2_1) begin if (_T_6862) begin - bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_33 <= io_exu_mp_pkt_bits_hist; end @@ -40091,7 +40091,7 @@ end // initial bht_bank_rd_data_out_0_34 <= 2'h0; end else if (bht_bank_sel_0_2_2) begin if (_T_6871) begin - bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_34 <= io_exu_mp_pkt_bits_hist; end @@ -40102,7 +40102,7 @@ end // initial bht_bank_rd_data_out_0_35 <= 2'h0; end else if (bht_bank_sel_0_2_3) begin if (_T_6880) begin - bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_35 <= io_exu_mp_pkt_bits_hist; end @@ -40113,7 +40113,7 @@ end // initial bht_bank_rd_data_out_0_36 <= 2'h0; end else if (bht_bank_sel_0_2_4) begin if (_T_6889) begin - bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_36 <= io_exu_mp_pkt_bits_hist; end @@ -40124,7 +40124,7 @@ end // initial bht_bank_rd_data_out_0_37 <= 2'h0; end else if (bht_bank_sel_0_2_5) begin if (_T_6898) begin - bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_37 <= io_exu_mp_pkt_bits_hist; end @@ -40135,7 +40135,7 @@ end // initial bht_bank_rd_data_out_0_38 <= 2'h0; end else if (bht_bank_sel_0_2_6) begin if (_T_6907) begin - bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_38 <= io_exu_mp_pkt_bits_hist; end @@ -40146,7 +40146,7 @@ end // initial bht_bank_rd_data_out_0_39 <= 2'h0; end else if (bht_bank_sel_0_2_7) begin if (_T_6916) begin - bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_39 <= io_exu_mp_pkt_bits_hist; end @@ -40157,7 +40157,7 @@ end // initial bht_bank_rd_data_out_0_40 <= 2'h0; end else if (bht_bank_sel_0_2_8) begin if (_T_6925) begin - bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_40 <= io_exu_mp_pkt_bits_hist; end @@ -40168,7 +40168,7 @@ end // initial bht_bank_rd_data_out_0_41 <= 2'h0; end else if (bht_bank_sel_0_2_9) begin if (_T_6934) begin - bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_41 <= io_exu_mp_pkt_bits_hist; end @@ -40179,7 +40179,7 @@ end // initial bht_bank_rd_data_out_0_42 <= 2'h0; end else if (bht_bank_sel_0_2_10) begin if (_T_6943) begin - bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_42 <= io_exu_mp_pkt_bits_hist; end @@ -40190,7 +40190,7 @@ end // initial bht_bank_rd_data_out_0_43 <= 2'h0; end else if (bht_bank_sel_0_2_11) begin if (_T_6952) begin - bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_43 <= io_exu_mp_pkt_bits_hist; end @@ -40201,7 +40201,7 @@ end // initial bht_bank_rd_data_out_0_44 <= 2'h0; end else if (bht_bank_sel_0_2_12) begin if (_T_6961) begin - bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_44 <= io_exu_mp_pkt_bits_hist; end @@ -40212,7 +40212,7 @@ end // initial bht_bank_rd_data_out_0_45 <= 2'h0; end else if (bht_bank_sel_0_2_13) begin if (_T_6970) begin - bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_45 <= io_exu_mp_pkt_bits_hist; end @@ -40223,7 +40223,7 @@ end // initial bht_bank_rd_data_out_0_46 <= 2'h0; end else if (bht_bank_sel_0_2_14) begin if (_T_6979) begin - bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_46 <= io_exu_mp_pkt_bits_hist; end @@ -40234,7 +40234,7 @@ end // initial bht_bank_rd_data_out_0_47 <= 2'h0; end else if (bht_bank_sel_0_2_15) begin if (_T_6988) begin - bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_47 <= io_exu_mp_pkt_bits_hist; end @@ -40245,7 +40245,7 @@ end // initial bht_bank_rd_data_out_0_48 <= 2'h0; end else if (bht_bank_sel_0_3_0) begin if (_T_6997) begin - bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_48 <= io_exu_mp_pkt_bits_hist; end @@ -40256,7 +40256,7 @@ end // initial bht_bank_rd_data_out_0_49 <= 2'h0; end else if (bht_bank_sel_0_3_1) begin if (_T_7006) begin - bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_49 <= io_exu_mp_pkt_bits_hist; end @@ -40267,7 +40267,7 @@ end // initial bht_bank_rd_data_out_0_50 <= 2'h0; end else if (bht_bank_sel_0_3_2) begin if (_T_7015) begin - bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_50 <= io_exu_mp_pkt_bits_hist; end @@ -40278,7 +40278,7 @@ end // initial bht_bank_rd_data_out_0_51 <= 2'h0; end else if (bht_bank_sel_0_3_3) begin if (_T_7024) begin - bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_51 <= io_exu_mp_pkt_bits_hist; end @@ -40289,7 +40289,7 @@ end // initial bht_bank_rd_data_out_0_52 <= 2'h0; end else if (bht_bank_sel_0_3_4) begin if (_T_7033) begin - bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_52 <= io_exu_mp_pkt_bits_hist; end @@ -40300,7 +40300,7 @@ end // initial bht_bank_rd_data_out_0_53 <= 2'h0; end else if (bht_bank_sel_0_3_5) begin if (_T_7042) begin - bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_53 <= io_exu_mp_pkt_bits_hist; end @@ -40311,7 +40311,7 @@ end // initial bht_bank_rd_data_out_0_54 <= 2'h0; end else if (bht_bank_sel_0_3_6) begin if (_T_7051) begin - bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_54 <= io_exu_mp_pkt_bits_hist; end @@ -40322,7 +40322,7 @@ end // initial bht_bank_rd_data_out_0_55 <= 2'h0; end else if (bht_bank_sel_0_3_7) begin if (_T_7060) begin - bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_55 <= io_exu_mp_pkt_bits_hist; end @@ -40333,7 +40333,7 @@ end // initial bht_bank_rd_data_out_0_56 <= 2'h0; end else if (bht_bank_sel_0_3_8) begin if (_T_7069) begin - bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_56 <= io_exu_mp_pkt_bits_hist; end @@ -40344,7 +40344,7 @@ end // initial bht_bank_rd_data_out_0_57 <= 2'h0; end else if (bht_bank_sel_0_3_9) begin if (_T_7078) begin - bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_57 <= io_exu_mp_pkt_bits_hist; end @@ -40355,7 +40355,7 @@ end // initial bht_bank_rd_data_out_0_58 <= 2'h0; end else if (bht_bank_sel_0_3_10) begin if (_T_7087) begin - bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_58 <= io_exu_mp_pkt_bits_hist; end @@ -40366,7 +40366,7 @@ end // initial bht_bank_rd_data_out_0_59 <= 2'h0; end else if (bht_bank_sel_0_3_11) begin if (_T_7096) begin - bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_59 <= io_exu_mp_pkt_bits_hist; end @@ -40377,7 +40377,7 @@ end // initial bht_bank_rd_data_out_0_60 <= 2'h0; end else if (bht_bank_sel_0_3_12) begin if (_T_7105) begin - bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_60 <= io_exu_mp_pkt_bits_hist; end @@ -40388,7 +40388,7 @@ end // initial bht_bank_rd_data_out_0_61 <= 2'h0; end else if (bht_bank_sel_0_3_13) begin if (_T_7114) begin - bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_61 <= io_exu_mp_pkt_bits_hist; end @@ -40399,7 +40399,7 @@ end // initial bht_bank_rd_data_out_0_62 <= 2'h0; end else if (bht_bank_sel_0_3_14) begin if (_T_7123) begin - bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_62 <= io_exu_mp_pkt_bits_hist; end @@ -40410,7 +40410,7 @@ end // initial bht_bank_rd_data_out_0_63 <= 2'h0; end else if (bht_bank_sel_0_3_15) begin if (_T_7132) begin - bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_63 <= io_exu_mp_pkt_bits_hist; end @@ -40421,7 +40421,7 @@ end // initial bht_bank_rd_data_out_0_64 <= 2'h0; end else if (bht_bank_sel_0_4_0) begin if (_T_7141) begin - bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_64 <= io_exu_mp_pkt_bits_hist; end @@ -40432,7 +40432,7 @@ end // initial bht_bank_rd_data_out_0_65 <= 2'h0; end else if (bht_bank_sel_0_4_1) begin if (_T_7150) begin - bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_65 <= io_exu_mp_pkt_bits_hist; end @@ -40443,7 +40443,7 @@ end // initial bht_bank_rd_data_out_0_66 <= 2'h0; end else if (bht_bank_sel_0_4_2) begin if (_T_7159) begin - bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_66 <= io_exu_mp_pkt_bits_hist; end @@ -40454,7 +40454,7 @@ end // initial bht_bank_rd_data_out_0_67 <= 2'h0; end else if (bht_bank_sel_0_4_3) begin if (_T_7168) begin - bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_67 <= io_exu_mp_pkt_bits_hist; end @@ -40465,7 +40465,7 @@ end // initial bht_bank_rd_data_out_0_68 <= 2'h0; end else if (bht_bank_sel_0_4_4) begin if (_T_7177) begin - bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_68 <= io_exu_mp_pkt_bits_hist; end @@ -40476,7 +40476,7 @@ end // initial bht_bank_rd_data_out_0_69 <= 2'h0; end else if (bht_bank_sel_0_4_5) begin if (_T_7186) begin - bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_69 <= io_exu_mp_pkt_bits_hist; end @@ -40487,7 +40487,7 @@ end // initial bht_bank_rd_data_out_0_70 <= 2'h0; end else if (bht_bank_sel_0_4_6) begin if (_T_7195) begin - bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_70 <= io_exu_mp_pkt_bits_hist; end @@ -40498,7 +40498,7 @@ end // initial bht_bank_rd_data_out_0_71 <= 2'h0; end else if (bht_bank_sel_0_4_7) begin if (_T_7204) begin - bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_71 <= io_exu_mp_pkt_bits_hist; end @@ -40509,7 +40509,7 @@ end // initial bht_bank_rd_data_out_0_72 <= 2'h0; end else if (bht_bank_sel_0_4_8) begin if (_T_7213) begin - bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_72 <= io_exu_mp_pkt_bits_hist; end @@ -40520,7 +40520,7 @@ end // initial bht_bank_rd_data_out_0_73 <= 2'h0; end else if (bht_bank_sel_0_4_9) begin if (_T_7222) begin - bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_73 <= io_exu_mp_pkt_bits_hist; end @@ -40531,7 +40531,7 @@ end // initial bht_bank_rd_data_out_0_74 <= 2'h0; end else if (bht_bank_sel_0_4_10) begin if (_T_7231) begin - bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_74 <= io_exu_mp_pkt_bits_hist; end @@ -40542,7 +40542,7 @@ end // initial bht_bank_rd_data_out_0_75 <= 2'h0; end else if (bht_bank_sel_0_4_11) begin if (_T_7240) begin - bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_75 <= io_exu_mp_pkt_bits_hist; end @@ -40553,7 +40553,7 @@ end // initial bht_bank_rd_data_out_0_76 <= 2'h0; end else if (bht_bank_sel_0_4_12) begin if (_T_7249) begin - bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_76 <= io_exu_mp_pkt_bits_hist; end @@ -40564,7 +40564,7 @@ end // initial bht_bank_rd_data_out_0_77 <= 2'h0; end else if (bht_bank_sel_0_4_13) begin if (_T_7258) begin - bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_77 <= io_exu_mp_pkt_bits_hist; end @@ -40575,7 +40575,7 @@ end // initial bht_bank_rd_data_out_0_78 <= 2'h0; end else if (bht_bank_sel_0_4_14) begin if (_T_7267) begin - bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_78 <= io_exu_mp_pkt_bits_hist; end @@ -40586,7 +40586,7 @@ end // initial bht_bank_rd_data_out_0_79 <= 2'h0; end else if (bht_bank_sel_0_4_15) begin if (_T_7276) begin - bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_79 <= io_exu_mp_pkt_bits_hist; end @@ -40597,7 +40597,7 @@ end // initial bht_bank_rd_data_out_0_80 <= 2'h0; end else if (bht_bank_sel_0_5_0) begin if (_T_7285) begin - bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_80 <= io_exu_mp_pkt_bits_hist; end @@ -40608,7 +40608,7 @@ end // initial bht_bank_rd_data_out_0_81 <= 2'h0; end else if (bht_bank_sel_0_5_1) begin if (_T_7294) begin - bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_81 <= io_exu_mp_pkt_bits_hist; end @@ -40619,7 +40619,7 @@ end // initial bht_bank_rd_data_out_0_82 <= 2'h0; end else if (bht_bank_sel_0_5_2) begin if (_T_7303) begin - bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_82 <= io_exu_mp_pkt_bits_hist; end @@ -40630,7 +40630,7 @@ end // initial bht_bank_rd_data_out_0_83 <= 2'h0; end else if (bht_bank_sel_0_5_3) begin if (_T_7312) begin - bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_83 <= io_exu_mp_pkt_bits_hist; end @@ -40641,7 +40641,7 @@ end // initial bht_bank_rd_data_out_0_84 <= 2'h0; end else if (bht_bank_sel_0_5_4) begin if (_T_7321) begin - bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_84 <= io_exu_mp_pkt_bits_hist; end @@ -40652,7 +40652,7 @@ end // initial bht_bank_rd_data_out_0_85 <= 2'h0; end else if (bht_bank_sel_0_5_5) begin if (_T_7330) begin - bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_85 <= io_exu_mp_pkt_bits_hist; end @@ -40663,7 +40663,7 @@ end // initial bht_bank_rd_data_out_0_86 <= 2'h0; end else if (bht_bank_sel_0_5_6) begin if (_T_7339) begin - bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_86 <= io_exu_mp_pkt_bits_hist; end @@ -40674,7 +40674,7 @@ end // initial bht_bank_rd_data_out_0_87 <= 2'h0; end else if (bht_bank_sel_0_5_7) begin if (_T_7348) begin - bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_87 <= io_exu_mp_pkt_bits_hist; end @@ -40685,7 +40685,7 @@ end // initial bht_bank_rd_data_out_0_88 <= 2'h0; end else if (bht_bank_sel_0_5_8) begin if (_T_7357) begin - bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_88 <= io_exu_mp_pkt_bits_hist; end @@ -40696,7 +40696,7 @@ end // initial bht_bank_rd_data_out_0_89 <= 2'h0; end else if (bht_bank_sel_0_5_9) begin if (_T_7366) begin - bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_89 <= io_exu_mp_pkt_bits_hist; end @@ -40707,7 +40707,7 @@ end // initial bht_bank_rd_data_out_0_90 <= 2'h0; end else if (bht_bank_sel_0_5_10) begin if (_T_7375) begin - bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_90 <= io_exu_mp_pkt_bits_hist; end @@ -40718,7 +40718,7 @@ end // initial bht_bank_rd_data_out_0_91 <= 2'h0; end else if (bht_bank_sel_0_5_11) begin if (_T_7384) begin - bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_91 <= io_exu_mp_pkt_bits_hist; end @@ -40729,7 +40729,7 @@ end // initial bht_bank_rd_data_out_0_92 <= 2'h0; end else if (bht_bank_sel_0_5_12) begin if (_T_7393) begin - bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_92 <= io_exu_mp_pkt_bits_hist; end @@ -40740,7 +40740,7 @@ end // initial bht_bank_rd_data_out_0_93 <= 2'h0; end else if (bht_bank_sel_0_5_13) begin if (_T_7402) begin - bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_93 <= io_exu_mp_pkt_bits_hist; end @@ -40751,7 +40751,7 @@ end // initial bht_bank_rd_data_out_0_94 <= 2'h0; end else if (bht_bank_sel_0_5_14) begin if (_T_7411) begin - bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_94 <= io_exu_mp_pkt_bits_hist; end @@ -40762,7 +40762,7 @@ end // initial bht_bank_rd_data_out_0_95 <= 2'h0; end else if (bht_bank_sel_0_5_15) begin if (_T_7420) begin - bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_95 <= io_exu_mp_pkt_bits_hist; end @@ -40773,7 +40773,7 @@ end // initial bht_bank_rd_data_out_0_96 <= 2'h0; end else if (bht_bank_sel_0_6_0) begin if (_T_7429) begin - bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_96 <= io_exu_mp_pkt_bits_hist; end @@ -40784,7 +40784,7 @@ end // initial bht_bank_rd_data_out_0_97 <= 2'h0; end else if (bht_bank_sel_0_6_1) begin if (_T_7438) begin - bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_97 <= io_exu_mp_pkt_bits_hist; end @@ -40795,7 +40795,7 @@ end // initial bht_bank_rd_data_out_0_98 <= 2'h0; end else if (bht_bank_sel_0_6_2) begin if (_T_7447) begin - bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_98 <= io_exu_mp_pkt_bits_hist; end @@ -40806,7 +40806,7 @@ end // initial bht_bank_rd_data_out_0_99 <= 2'h0; end else if (bht_bank_sel_0_6_3) begin if (_T_7456) begin - bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_99 <= io_exu_mp_pkt_bits_hist; end @@ -40817,7 +40817,7 @@ end // initial bht_bank_rd_data_out_0_100 <= 2'h0; end else if (bht_bank_sel_0_6_4) begin if (_T_7465) begin - bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_100 <= io_exu_mp_pkt_bits_hist; end @@ -40828,7 +40828,7 @@ end // initial bht_bank_rd_data_out_0_101 <= 2'h0; end else if (bht_bank_sel_0_6_5) begin if (_T_7474) begin - bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_101 <= io_exu_mp_pkt_bits_hist; end @@ -40839,7 +40839,7 @@ end // initial bht_bank_rd_data_out_0_102 <= 2'h0; end else if (bht_bank_sel_0_6_6) begin if (_T_7483) begin - bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_102 <= io_exu_mp_pkt_bits_hist; end @@ -40850,7 +40850,7 @@ end // initial bht_bank_rd_data_out_0_103 <= 2'h0; end else if (bht_bank_sel_0_6_7) begin if (_T_7492) begin - bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_103 <= io_exu_mp_pkt_bits_hist; end @@ -40861,7 +40861,7 @@ end // initial bht_bank_rd_data_out_0_104 <= 2'h0; end else if (bht_bank_sel_0_6_8) begin if (_T_7501) begin - bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_104 <= io_exu_mp_pkt_bits_hist; end @@ -40872,7 +40872,7 @@ end // initial bht_bank_rd_data_out_0_105 <= 2'h0; end else if (bht_bank_sel_0_6_9) begin if (_T_7510) begin - bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_105 <= io_exu_mp_pkt_bits_hist; end @@ -40883,7 +40883,7 @@ end // initial bht_bank_rd_data_out_0_106 <= 2'h0; end else if (bht_bank_sel_0_6_10) begin if (_T_7519) begin - bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_106 <= io_exu_mp_pkt_bits_hist; end @@ -40894,7 +40894,7 @@ end // initial bht_bank_rd_data_out_0_107 <= 2'h0; end else if (bht_bank_sel_0_6_11) begin if (_T_7528) begin - bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_107 <= io_exu_mp_pkt_bits_hist; end @@ -40905,7 +40905,7 @@ end // initial bht_bank_rd_data_out_0_108 <= 2'h0; end else if (bht_bank_sel_0_6_12) begin if (_T_7537) begin - bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_108 <= io_exu_mp_pkt_bits_hist; end @@ -40916,7 +40916,7 @@ end // initial bht_bank_rd_data_out_0_109 <= 2'h0; end else if (bht_bank_sel_0_6_13) begin if (_T_7546) begin - bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_109 <= io_exu_mp_pkt_bits_hist; end @@ -40927,7 +40927,7 @@ end // initial bht_bank_rd_data_out_0_110 <= 2'h0; end else if (bht_bank_sel_0_6_14) begin if (_T_7555) begin - bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_110 <= io_exu_mp_pkt_bits_hist; end @@ -40938,7 +40938,7 @@ end // initial bht_bank_rd_data_out_0_111 <= 2'h0; end else if (bht_bank_sel_0_6_15) begin if (_T_7564) begin - bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_111 <= io_exu_mp_pkt_bits_hist; end @@ -40949,7 +40949,7 @@ end // initial bht_bank_rd_data_out_0_112 <= 2'h0; end else if (bht_bank_sel_0_7_0) begin if (_T_7573) begin - bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_112 <= io_exu_mp_pkt_bits_hist; end @@ -40960,7 +40960,7 @@ end // initial bht_bank_rd_data_out_0_113 <= 2'h0; end else if (bht_bank_sel_0_7_1) begin if (_T_7582) begin - bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_113 <= io_exu_mp_pkt_bits_hist; end @@ -40971,7 +40971,7 @@ end // initial bht_bank_rd_data_out_0_114 <= 2'h0; end else if (bht_bank_sel_0_7_2) begin if (_T_7591) begin - bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_114 <= io_exu_mp_pkt_bits_hist; end @@ -40982,7 +40982,7 @@ end // initial bht_bank_rd_data_out_0_115 <= 2'h0; end else if (bht_bank_sel_0_7_3) begin if (_T_7600) begin - bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_115 <= io_exu_mp_pkt_bits_hist; end @@ -40993,7 +40993,7 @@ end // initial bht_bank_rd_data_out_0_116 <= 2'h0; end else if (bht_bank_sel_0_7_4) begin if (_T_7609) begin - bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_116 <= io_exu_mp_pkt_bits_hist; end @@ -41004,7 +41004,7 @@ end // initial bht_bank_rd_data_out_0_117 <= 2'h0; end else if (bht_bank_sel_0_7_5) begin if (_T_7618) begin - bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_117 <= io_exu_mp_pkt_bits_hist; end @@ -41015,7 +41015,7 @@ end // initial bht_bank_rd_data_out_0_118 <= 2'h0; end else if (bht_bank_sel_0_7_6) begin if (_T_7627) begin - bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_118 <= io_exu_mp_pkt_bits_hist; end @@ -41026,7 +41026,7 @@ end // initial bht_bank_rd_data_out_0_119 <= 2'h0; end else if (bht_bank_sel_0_7_7) begin if (_T_7636) begin - bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_119 <= io_exu_mp_pkt_bits_hist; end @@ -41037,7 +41037,7 @@ end // initial bht_bank_rd_data_out_0_120 <= 2'h0; end else if (bht_bank_sel_0_7_8) begin if (_T_7645) begin - bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_120 <= io_exu_mp_pkt_bits_hist; end @@ -41048,7 +41048,7 @@ end // initial bht_bank_rd_data_out_0_121 <= 2'h0; end else if (bht_bank_sel_0_7_9) begin if (_T_7654) begin - bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_121 <= io_exu_mp_pkt_bits_hist; end @@ -41059,7 +41059,7 @@ end // initial bht_bank_rd_data_out_0_122 <= 2'h0; end else if (bht_bank_sel_0_7_10) begin if (_T_7663) begin - bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_122 <= io_exu_mp_pkt_bits_hist; end @@ -41070,7 +41070,7 @@ end // initial bht_bank_rd_data_out_0_123 <= 2'h0; end else if (bht_bank_sel_0_7_11) begin if (_T_7672) begin - bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_123 <= io_exu_mp_pkt_bits_hist; end @@ -41081,7 +41081,7 @@ end // initial bht_bank_rd_data_out_0_124 <= 2'h0; end else if (bht_bank_sel_0_7_12) begin if (_T_7681) begin - bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_124 <= io_exu_mp_pkt_bits_hist; end @@ -41092,7 +41092,7 @@ end // initial bht_bank_rd_data_out_0_125 <= 2'h0; end else if (bht_bank_sel_0_7_13) begin if (_T_7690) begin - bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_125 <= io_exu_mp_pkt_bits_hist; end @@ -41103,7 +41103,7 @@ end // initial bht_bank_rd_data_out_0_126 <= 2'h0; end else if (bht_bank_sel_0_7_14) begin if (_T_7699) begin - bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_126 <= io_exu_mp_pkt_bits_hist; end @@ -41114,7 +41114,7 @@ end // initial bht_bank_rd_data_out_0_127 <= 2'h0; end else if (bht_bank_sel_0_7_15) begin if (_T_7708) begin - bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_127 <= io_exu_mp_pkt_bits_hist; end @@ -41125,7 +41125,7 @@ end // initial bht_bank_rd_data_out_0_128 <= 2'h0; end else if (bht_bank_sel_0_8_0) begin if (_T_7717) begin - bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_128 <= io_exu_mp_pkt_bits_hist; end @@ -41136,7 +41136,7 @@ end // initial bht_bank_rd_data_out_0_129 <= 2'h0; end else if (bht_bank_sel_0_8_1) begin if (_T_7726) begin - bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_129 <= io_exu_mp_pkt_bits_hist; end @@ -41147,7 +41147,7 @@ end // initial bht_bank_rd_data_out_0_130 <= 2'h0; end else if (bht_bank_sel_0_8_2) begin if (_T_7735) begin - bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_130 <= io_exu_mp_pkt_bits_hist; end @@ -41158,7 +41158,7 @@ end // initial bht_bank_rd_data_out_0_131 <= 2'h0; end else if (bht_bank_sel_0_8_3) begin if (_T_7744) begin - bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_131 <= io_exu_mp_pkt_bits_hist; end @@ -41169,7 +41169,7 @@ end // initial bht_bank_rd_data_out_0_132 <= 2'h0; end else if (bht_bank_sel_0_8_4) begin if (_T_7753) begin - bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_132 <= io_exu_mp_pkt_bits_hist; end @@ -41180,7 +41180,7 @@ end // initial bht_bank_rd_data_out_0_133 <= 2'h0; end else if (bht_bank_sel_0_8_5) begin if (_T_7762) begin - bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_133 <= io_exu_mp_pkt_bits_hist; end @@ -41191,7 +41191,7 @@ end // initial bht_bank_rd_data_out_0_134 <= 2'h0; end else if (bht_bank_sel_0_8_6) begin if (_T_7771) begin - bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_134 <= io_exu_mp_pkt_bits_hist; end @@ -41202,7 +41202,7 @@ end // initial bht_bank_rd_data_out_0_135 <= 2'h0; end else if (bht_bank_sel_0_8_7) begin if (_T_7780) begin - bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_135 <= io_exu_mp_pkt_bits_hist; end @@ -41213,7 +41213,7 @@ end // initial bht_bank_rd_data_out_0_136 <= 2'h0; end else if (bht_bank_sel_0_8_8) begin if (_T_7789) begin - bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_136 <= io_exu_mp_pkt_bits_hist; end @@ -41224,7 +41224,7 @@ end // initial bht_bank_rd_data_out_0_137 <= 2'h0; end else if (bht_bank_sel_0_8_9) begin if (_T_7798) begin - bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_137 <= io_exu_mp_pkt_bits_hist; end @@ -41235,7 +41235,7 @@ end // initial bht_bank_rd_data_out_0_138 <= 2'h0; end else if (bht_bank_sel_0_8_10) begin if (_T_7807) begin - bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_138 <= io_exu_mp_pkt_bits_hist; end @@ -41246,7 +41246,7 @@ end // initial bht_bank_rd_data_out_0_139 <= 2'h0; end else if (bht_bank_sel_0_8_11) begin if (_T_7816) begin - bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_139 <= io_exu_mp_pkt_bits_hist; end @@ -41257,7 +41257,7 @@ end // initial bht_bank_rd_data_out_0_140 <= 2'h0; end else if (bht_bank_sel_0_8_12) begin if (_T_7825) begin - bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_140 <= io_exu_mp_pkt_bits_hist; end @@ -41268,7 +41268,7 @@ end // initial bht_bank_rd_data_out_0_141 <= 2'h0; end else if (bht_bank_sel_0_8_13) begin if (_T_7834) begin - bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_141 <= io_exu_mp_pkt_bits_hist; end @@ -41279,7 +41279,7 @@ end // initial bht_bank_rd_data_out_0_142 <= 2'h0; end else if (bht_bank_sel_0_8_14) begin if (_T_7843) begin - bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_142 <= io_exu_mp_pkt_bits_hist; end @@ -41290,7 +41290,7 @@ end // initial bht_bank_rd_data_out_0_143 <= 2'h0; end else if (bht_bank_sel_0_8_15) begin if (_T_7852) begin - bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_143 <= io_exu_mp_pkt_bits_hist; end @@ -41301,7 +41301,7 @@ end // initial bht_bank_rd_data_out_0_144 <= 2'h0; end else if (bht_bank_sel_0_9_0) begin if (_T_7861) begin - bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_144 <= io_exu_mp_pkt_bits_hist; end @@ -41312,7 +41312,7 @@ end // initial bht_bank_rd_data_out_0_145 <= 2'h0; end else if (bht_bank_sel_0_9_1) begin if (_T_7870) begin - bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_145 <= io_exu_mp_pkt_bits_hist; end @@ -41323,7 +41323,7 @@ end // initial bht_bank_rd_data_out_0_146 <= 2'h0; end else if (bht_bank_sel_0_9_2) begin if (_T_7879) begin - bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_146 <= io_exu_mp_pkt_bits_hist; end @@ -41334,7 +41334,7 @@ end // initial bht_bank_rd_data_out_0_147 <= 2'h0; end else if (bht_bank_sel_0_9_3) begin if (_T_7888) begin - bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_147 <= io_exu_mp_pkt_bits_hist; end @@ -41345,7 +41345,7 @@ end // initial bht_bank_rd_data_out_0_148 <= 2'h0; end else if (bht_bank_sel_0_9_4) begin if (_T_7897) begin - bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_148 <= io_exu_mp_pkt_bits_hist; end @@ -41356,7 +41356,7 @@ end // initial bht_bank_rd_data_out_0_149 <= 2'h0; end else if (bht_bank_sel_0_9_5) begin if (_T_7906) begin - bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_149 <= io_exu_mp_pkt_bits_hist; end @@ -41367,7 +41367,7 @@ end // initial bht_bank_rd_data_out_0_150 <= 2'h0; end else if (bht_bank_sel_0_9_6) begin if (_T_7915) begin - bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_150 <= io_exu_mp_pkt_bits_hist; end @@ -41378,7 +41378,7 @@ end // initial bht_bank_rd_data_out_0_151 <= 2'h0; end else if (bht_bank_sel_0_9_7) begin if (_T_7924) begin - bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_151 <= io_exu_mp_pkt_bits_hist; end @@ -41389,7 +41389,7 @@ end // initial bht_bank_rd_data_out_0_152 <= 2'h0; end else if (bht_bank_sel_0_9_8) begin if (_T_7933) begin - bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_152 <= io_exu_mp_pkt_bits_hist; end @@ -41400,7 +41400,7 @@ end // initial bht_bank_rd_data_out_0_153 <= 2'h0; end else if (bht_bank_sel_0_9_9) begin if (_T_7942) begin - bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_153 <= io_exu_mp_pkt_bits_hist; end @@ -41411,7 +41411,7 @@ end // initial bht_bank_rd_data_out_0_154 <= 2'h0; end else if (bht_bank_sel_0_9_10) begin if (_T_7951) begin - bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_154 <= io_exu_mp_pkt_bits_hist; end @@ -41422,7 +41422,7 @@ end // initial bht_bank_rd_data_out_0_155 <= 2'h0; end else if (bht_bank_sel_0_9_11) begin if (_T_7960) begin - bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_155 <= io_exu_mp_pkt_bits_hist; end @@ -41433,7 +41433,7 @@ end // initial bht_bank_rd_data_out_0_156 <= 2'h0; end else if (bht_bank_sel_0_9_12) begin if (_T_7969) begin - bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_156 <= io_exu_mp_pkt_bits_hist; end @@ -41444,7 +41444,7 @@ end // initial bht_bank_rd_data_out_0_157 <= 2'h0; end else if (bht_bank_sel_0_9_13) begin if (_T_7978) begin - bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_157 <= io_exu_mp_pkt_bits_hist; end @@ -41455,7 +41455,7 @@ end // initial bht_bank_rd_data_out_0_158 <= 2'h0; end else if (bht_bank_sel_0_9_14) begin if (_T_7987) begin - bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_158 <= io_exu_mp_pkt_bits_hist; end @@ -41466,7 +41466,7 @@ end // initial bht_bank_rd_data_out_0_159 <= 2'h0; end else if (bht_bank_sel_0_9_15) begin if (_T_7996) begin - bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_159 <= io_exu_mp_pkt_bits_hist; end @@ -41477,7 +41477,7 @@ end // initial bht_bank_rd_data_out_0_160 <= 2'h0; end else if (bht_bank_sel_0_10_0) begin if (_T_8005) begin - bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_160 <= io_exu_mp_pkt_bits_hist; end @@ -41488,7 +41488,7 @@ end // initial bht_bank_rd_data_out_0_161 <= 2'h0; end else if (bht_bank_sel_0_10_1) begin if (_T_8014) begin - bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_161 <= io_exu_mp_pkt_bits_hist; end @@ -41499,7 +41499,7 @@ end // initial bht_bank_rd_data_out_0_162 <= 2'h0; end else if (bht_bank_sel_0_10_2) begin if (_T_8023) begin - bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_162 <= io_exu_mp_pkt_bits_hist; end @@ -41510,7 +41510,7 @@ end // initial bht_bank_rd_data_out_0_163 <= 2'h0; end else if (bht_bank_sel_0_10_3) begin if (_T_8032) begin - bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_163 <= io_exu_mp_pkt_bits_hist; end @@ -41521,7 +41521,7 @@ end // initial bht_bank_rd_data_out_0_164 <= 2'h0; end else if (bht_bank_sel_0_10_4) begin if (_T_8041) begin - bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_164 <= io_exu_mp_pkt_bits_hist; end @@ -41532,7 +41532,7 @@ end // initial bht_bank_rd_data_out_0_165 <= 2'h0; end else if (bht_bank_sel_0_10_5) begin if (_T_8050) begin - bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_165 <= io_exu_mp_pkt_bits_hist; end @@ -41543,7 +41543,7 @@ end // initial bht_bank_rd_data_out_0_166 <= 2'h0; end else if (bht_bank_sel_0_10_6) begin if (_T_8059) begin - bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_166 <= io_exu_mp_pkt_bits_hist; end @@ -41554,7 +41554,7 @@ end // initial bht_bank_rd_data_out_0_167 <= 2'h0; end else if (bht_bank_sel_0_10_7) begin if (_T_8068) begin - bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_167 <= io_exu_mp_pkt_bits_hist; end @@ -41565,7 +41565,7 @@ end // initial bht_bank_rd_data_out_0_168 <= 2'h0; end else if (bht_bank_sel_0_10_8) begin if (_T_8077) begin - bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_168 <= io_exu_mp_pkt_bits_hist; end @@ -41576,7 +41576,7 @@ end // initial bht_bank_rd_data_out_0_169 <= 2'h0; end else if (bht_bank_sel_0_10_9) begin if (_T_8086) begin - bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_169 <= io_exu_mp_pkt_bits_hist; end @@ -41587,7 +41587,7 @@ end // initial bht_bank_rd_data_out_0_170 <= 2'h0; end else if (bht_bank_sel_0_10_10) begin if (_T_8095) begin - bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_170 <= io_exu_mp_pkt_bits_hist; end @@ -41598,7 +41598,7 @@ end // initial bht_bank_rd_data_out_0_171 <= 2'h0; end else if (bht_bank_sel_0_10_11) begin if (_T_8104) begin - bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_171 <= io_exu_mp_pkt_bits_hist; end @@ -41609,7 +41609,7 @@ end // initial bht_bank_rd_data_out_0_172 <= 2'h0; end else if (bht_bank_sel_0_10_12) begin if (_T_8113) begin - bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_172 <= io_exu_mp_pkt_bits_hist; end @@ -41620,7 +41620,7 @@ end // initial bht_bank_rd_data_out_0_173 <= 2'h0; end else if (bht_bank_sel_0_10_13) begin if (_T_8122) begin - bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_173 <= io_exu_mp_pkt_bits_hist; end @@ -41631,7 +41631,7 @@ end // initial bht_bank_rd_data_out_0_174 <= 2'h0; end else if (bht_bank_sel_0_10_14) begin if (_T_8131) begin - bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_174 <= io_exu_mp_pkt_bits_hist; end @@ -41642,7 +41642,7 @@ end // initial bht_bank_rd_data_out_0_175 <= 2'h0; end else if (bht_bank_sel_0_10_15) begin if (_T_8140) begin - bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_175 <= io_exu_mp_pkt_bits_hist; end @@ -41653,7 +41653,7 @@ end // initial bht_bank_rd_data_out_0_176 <= 2'h0; end else if (bht_bank_sel_0_11_0) begin if (_T_8149) begin - bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_176 <= io_exu_mp_pkt_bits_hist; end @@ -41664,7 +41664,7 @@ end // initial bht_bank_rd_data_out_0_177 <= 2'h0; end else if (bht_bank_sel_0_11_1) begin if (_T_8158) begin - bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_177 <= io_exu_mp_pkt_bits_hist; end @@ -41675,7 +41675,7 @@ end // initial bht_bank_rd_data_out_0_178 <= 2'h0; end else if (bht_bank_sel_0_11_2) begin if (_T_8167) begin - bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_178 <= io_exu_mp_pkt_bits_hist; end @@ -41686,7 +41686,7 @@ end // initial bht_bank_rd_data_out_0_179 <= 2'h0; end else if (bht_bank_sel_0_11_3) begin if (_T_8176) begin - bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_179 <= io_exu_mp_pkt_bits_hist; end @@ -41697,7 +41697,7 @@ end // initial bht_bank_rd_data_out_0_180 <= 2'h0; end else if (bht_bank_sel_0_11_4) begin if (_T_8185) begin - bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_180 <= io_exu_mp_pkt_bits_hist; end @@ -41708,7 +41708,7 @@ end // initial bht_bank_rd_data_out_0_181 <= 2'h0; end else if (bht_bank_sel_0_11_5) begin if (_T_8194) begin - bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_181 <= io_exu_mp_pkt_bits_hist; end @@ -41719,7 +41719,7 @@ end // initial bht_bank_rd_data_out_0_182 <= 2'h0; end else if (bht_bank_sel_0_11_6) begin if (_T_8203) begin - bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_182 <= io_exu_mp_pkt_bits_hist; end @@ -41730,7 +41730,7 @@ end // initial bht_bank_rd_data_out_0_183 <= 2'h0; end else if (bht_bank_sel_0_11_7) begin if (_T_8212) begin - bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_183 <= io_exu_mp_pkt_bits_hist; end @@ -41741,7 +41741,7 @@ end // initial bht_bank_rd_data_out_0_184 <= 2'h0; end else if (bht_bank_sel_0_11_8) begin if (_T_8221) begin - bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_184 <= io_exu_mp_pkt_bits_hist; end @@ -41752,7 +41752,7 @@ end // initial bht_bank_rd_data_out_0_185 <= 2'h0; end else if (bht_bank_sel_0_11_9) begin if (_T_8230) begin - bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_185 <= io_exu_mp_pkt_bits_hist; end @@ -41763,7 +41763,7 @@ end // initial bht_bank_rd_data_out_0_186 <= 2'h0; end else if (bht_bank_sel_0_11_10) begin if (_T_8239) begin - bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_186 <= io_exu_mp_pkt_bits_hist; end @@ -41774,7 +41774,7 @@ end // initial bht_bank_rd_data_out_0_187 <= 2'h0; end else if (bht_bank_sel_0_11_11) begin if (_T_8248) begin - bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_187 <= io_exu_mp_pkt_bits_hist; end @@ -41785,7 +41785,7 @@ end // initial bht_bank_rd_data_out_0_188 <= 2'h0; end else if (bht_bank_sel_0_11_12) begin if (_T_8257) begin - bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_188 <= io_exu_mp_pkt_bits_hist; end @@ -41796,7 +41796,7 @@ end // initial bht_bank_rd_data_out_0_189 <= 2'h0; end else if (bht_bank_sel_0_11_13) begin if (_T_8266) begin - bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_189 <= io_exu_mp_pkt_bits_hist; end @@ -41807,7 +41807,7 @@ end // initial bht_bank_rd_data_out_0_190 <= 2'h0; end else if (bht_bank_sel_0_11_14) begin if (_T_8275) begin - bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_190 <= io_exu_mp_pkt_bits_hist; end @@ -41818,7 +41818,7 @@ end // initial bht_bank_rd_data_out_0_191 <= 2'h0; end else if (bht_bank_sel_0_11_15) begin if (_T_8284) begin - bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_191 <= io_exu_mp_pkt_bits_hist; end @@ -41829,7 +41829,7 @@ end // initial bht_bank_rd_data_out_0_192 <= 2'h0; end else if (bht_bank_sel_0_12_0) begin if (_T_8293) begin - bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_192 <= io_exu_mp_pkt_bits_hist; end @@ -41840,7 +41840,7 @@ end // initial bht_bank_rd_data_out_0_193 <= 2'h0; end else if (bht_bank_sel_0_12_1) begin if (_T_8302) begin - bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_193 <= io_exu_mp_pkt_bits_hist; end @@ -41851,7 +41851,7 @@ end // initial bht_bank_rd_data_out_0_194 <= 2'h0; end else if (bht_bank_sel_0_12_2) begin if (_T_8311) begin - bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_194 <= io_exu_mp_pkt_bits_hist; end @@ -41862,7 +41862,7 @@ end // initial bht_bank_rd_data_out_0_195 <= 2'h0; end else if (bht_bank_sel_0_12_3) begin if (_T_8320) begin - bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_195 <= io_exu_mp_pkt_bits_hist; end @@ -41873,7 +41873,7 @@ end // initial bht_bank_rd_data_out_0_196 <= 2'h0; end else if (bht_bank_sel_0_12_4) begin if (_T_8329) begin - bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_196 <= io_exu_mp_pkt_bits_hist; end @@ -41884,7 +41884,7 @@ end // initial bht_bank_rd_data_out_0_197 <= 2'h0; end else if (bht_bank_sel_0_12_5) begin if (_T_8338) begin - bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_197 <= io_exu_mp_pkt_bits_hist; end @@ -41895,7 +41895,7 @@ end // initial bht_bank_rd_data_out_0_198 <= 2'h0; end else if (bht_bank_sel_0_12_6) begin if (_T_8347) begin - bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_198 <= io_exu_mp_pkt_bits_hist; end @@ -41906,7 +41906,7 @@ end // initial bht_bank_rd_data_out_0_199 <= 2'h0; end else if (bht_bank_sel_0_12_7) begin if (_T_8356) begin - bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_199 <= io_exu_mp_pkt_bits_hist; end @@ -41917,7 +41917,7 @@ end // initial bht_bank_rd_data_out_0_200 <= 2'h0; end else if (bht_bank_sel_0_12_8) begin if (_T_8365) begin - bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_200 <= io_exu_mp_pkt_bits_hist; end @@ -41928,7 +41928,7 @@ end // initial bht_bank_rd_data_out_0_201 <= 2'h0; end else if (bht_bank_sel_0_12_9) begin if (_T_8374) begin - bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_201 <= io_exu_mp_pkt_bits_hist; end @@ -41939,7 +41939,7 @@ end // initial bht_bank_rd_data_out_0_202 <= 2'h0; end else if (bht_bank_sel_0_12_10) begin if (_T_8383) begin - bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_202 <= io_exu_mp_pkt_bits_hist; end @@ -41950,7 +41950,7 @@ end // initial bht_bank_rd_data_out_0_203 <= 2'h0; end else if (bht_bank_sel_0_12_11) begin if (_T_8392) begin - bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_203 <= io_exu_mp_pkt_bits_hist; end @@ -41961,7 +41961,7 @@ end // initial bht_bank_rd_data_out_0_204 <= 2'h0; end else if (bht_bank_sel_0_12_12) begin if (_T_8401) begin - bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_204 <= io_exu_mp_pkt_bits_hist; end @@ -41972,7 +41972,7 @@ end // initial bht_bank_rd_data_out_0_205 <= 2'h0; end else if (bht_bank_sel_0_12_13) begin if (_T_8410) begin - bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_205 <= io_exu_mp_pkt_bits_hist; end @@ -41983,7 +41983,7 @@ end // initial bht_bank_rd_data_out_0_206 <= 2'h0; end else if (bht_bank_sel_0_12_14) begin if (_T_8419) begin - bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_206 <= io_exu_mp_pkt_bits_hist; end @@ -41994,7 +41994,7 @@ end // initial bht_bank_rd_data_out_0_207 <= 2'h0; end else if (bht_bank_sel_0_12_15) begin if (_T_8428) begin - bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_207 <= io_exu_mp_pkt_bits_hist; end @@ -42005,7 +42005,7 @@ end // initial bht_bank_rd_data_out_0_208 <= 2'h0; end else if (bht_bank_sel_0_13_0) begin if (_T_8437) begin - bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_208 <= io_exu_mp_pkt_bits_hist; end @@ -42016,7 +42016,7 @@ end // initial bht_bank_rd_data_out_0_209 <= 2'h0; end else if (bht_bank_sel_0_13_1) begin if (_T_8446) begin - bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_209 <= io_exu_mp_pkt_bits_hist; end @@ -42027,7 +42027,7 @@ end // initial bht_bank_rd_data_out_0_210 <= 2'h0; end else if (bht_bank_sel_0_13_2) begin if (_T_8455) begin - bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_210 <= io_exu_mp_pkt_bits_hist; end @@ -42038,7 +42038,7 @@ end // initial bht_bank_rd_data_out_0_211 <= 2'h0; end else if (bht_bank_sel_0_13_3) begin if (_T_8464) begin - bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_211 <= io_exu_mp_pkt_bits_hist; end @@ -42049,7 +42049,7 @@ end // initial bht_bank_rd_data_out_0_212 <= 2'h0; end else if (bht_bank_sel_0_13_4) begin if (_T_8473) begin - bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_212 <= io_exu_mp_pkt_bits_hist; end @@ -42060,7 +42060,7 @@ end // initial bht_bank_rd_data_out_0_213 <= 2'h0; end else if (bht_bank_sel_0_13_5) begin if (_T_8482) begin - bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_213 <= io_exu_mp_pkt_bits_hist; end @@ -42071,7 +42071,7 @@ end // initial bht_bank_rd_data_out_0_214 <= 2'h0; end else if (bht_bank_sel_0_13_6) begin if (_T_8491) begin - bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_214 <= io_exu_mp_pkt_bits_hist; end @@ -42082,7 +42082,7 @@ end // initial bht_bank_rd_data_out_0_215 <= 2'h0; end else if (bht_bank_sel_0_13_7) begin if (_T_8500) begin - bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_215 <= io_exu_mp_pkt_bits_hist; end @@ -42093,7 +42093,7 @@ end // initial bht_bank_rd_data_out_0_216 <= 2'h0; end else if (bht_bank_sel_0_13_8) begin if (_T_8509) begin - bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_216 <= io_exu_mp_pkt_bits_hist; end @@ -42104,7 +42104,7 @@ end // initial bht_bank_rd_data_out_0_217 <= 2'h0; end else if (bht_bank_sel_0_13_9) begin if (_T_8518) begin - bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_217 <= io_exu_mp_pkt_bits_hist; end @@ -42115,7 +42115,7 @@ end // initial bht_bank_rd_data_out_0_218 <= 2'h0; end else if (bht_bank_sel_0_13_10) begin if (_T_8527) begin - bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_218 <= io_exu_mp_pkt_bits_hist; end @@ -42126,7 +42126,7 @@ end // initial bht_bank_rd_data_out_0_219 <= 2'h0; end else if (bht_bank_sel_0_13_11) begin if (_T_8536) begin - bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_219 <= io_exu_mp_pkt_bits_hist; end @@ -42137,7 +42137,7 @@ end // initial bht_bank_rd_data_out_0_220 <= 2'h0; end else if (bht_bank_sel_0_13_12) begin if (_T_8545) begin - bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_220 <= io_exu_mp_pkt_bits_hist; end @@ -42148,7 +42148,7 @@ end // initial bht_bank_rd_data_out_0_221 <= 2'h0; end else if (bht_bank_sel_0_13_13) begin if (_T_8554) begin - bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_221 <= io_exu_mp_pkt_bits_hist; end @@ -42159,7 +42159,7 @@ end // initial bht_bank_rd_data_out_0_222 <= 2'h0; end else if (bht_bank_sel_0_13_14) begin if (_T_8563) begin - bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_222 <= io_exu_mp_pkt_bits_hist; end @@ -42170,7 +42170,7 @@ end // initial bht_bank_rd_data_out_0_223 <= 2'h0; end else if (bht_bank_sel_0_13_15) begin if (_T_8572) begin - bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_223 <= io_exu_mp_pkt_bits_hist; end @@ -42181,7 +42181,7 @@ end // initial bht_bank_rd_data_out_0_224 <= 2'h0; end else if (bht_bank_sel_0_14_0) begin if (_T_8581) begin - bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_224 <= io_exu_mp_pkt_bits_hist; end @@ -42192,7 +42192,7 @@ end // initial bht_bank_rd_data_out_0_225 <= 2'h0; end else if (bht_bank_sel_0_14_1) begin if (_T_8590) begin - bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_225 <= io_exu_mp_pkt_bits_hist; end @@ -42203,7 +42203,7 @@ end // initial bht_bank_rd_data_out_0_226 <= 2'h0; end else if (bht_bank_sel_0_14_2) begin if (_T_8599) begin - bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_226 <= io_exu_mp_pkt_bits_hist; end @@ -42214,7 +42214,7 @@ end // initial bht_bank_rd_data_out_0_227 <= 2'h0; end else if (bht_bank_sel_0_14_3) begin if (_T_8608) begin - bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_227 <= io_exu_mp_pkt_bits_hist; end @@ -42225,7 +42225,7 @@ end // initial bht_bank_rd_data_out_0_228 <= 2'h0; end else if (bht_bank_sel_0_14_4) begin if (_T_8617) begin - bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_228 <= io_exu_mp_pkt_bits_hist; end @@ -42236,7 +42236,7 @@ end // initial bht_bank_rd_data_out_0_229 <= 2'h0; end else if (bht_bank_sel_0_14_5) begin if (_T_8626) begin - bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_229 <= io_exu_mp_pkt_bits_hist; end @@ -42247,7 +42247,7 @@ end // initial bht_bank_rd_data_out_0_230 <= 2'h0; end else if (bht_bank_sel_0_14_6) begin if (_T_8635) begin - bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_230 <= io_exu_mp_pkt_bits_hist; end @@ -42258,7 +42258,7 @@ end // initial bht_bank_rd_data_out_0_231 <= 2'h0; end else if (bht_bank_sel_0_14_7) begin if (_T_8644) begin - bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_231 <= io_exu_mp_pkt_bits_hist; end @@ -42269,7 +42269,7 @@ end // initial bht_bank_rd_data_out_0_232 <= 2'h0; end else if (bht_bank_sel_0_14_8) begin if (_T_8653) begin - bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_232 <= io_exu_mp_pkt_bits_hist; end @@ -42280,7 +42280,7 @@ end // initial bht_bank_rd_data_out_0_233 <= 2'h0; end else if (bht_bank_sel_0_14_9) begin if (_T_8662) begin - bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_233 <= io_exu_mp_pkt_bits_hist; end @@ -42291,7 +42291,7 @@ end // initial bht_bank_rd_data_out_0_234 <= 2'h0; end else if (bht_bank_sel_0_14_10) begin if (_T_8671) begin - bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_234 <= io_exu_mp_pkt_bits_hist; end @@ -42302,7 +42302,7 @@ end // initial bht_bank_rd_data_out_0_235 <= 2'h0; end else if (bht_bank_sel_0_14_11) begin if (_T_8680) begin - bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_235 <= io_exu_mp_pkt_bits_hist; end @@ -42313,7 +42313,7 @@ end // initial bht_bank_rd_data_out_0_236 <= 2'h0; end else if (bht_bank_sel_0_14_12) begin if (_T_8689) begin - bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_236 <= io_exu_mp_pkt_bits_hist; end @@ -42324,7 +42324,7 @@ end // initial bht_bank_rd_data_out_0_237 <= 2'h0; end else if (bht_bank_sel_0_14_13) begin if (_T_8698) begin - bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_237 <= io_exu_mp_pkt_bits_hist; end @@ -42335,7 +42335,7 @@ end // initial bht_bank_rd_data_out_0_238 <= 2'h0; end else if (bht_bank_sel_0_14_14) begin if (_T_8707) begin - bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_238 <= io_exu_mp_pkt_bits_hist; end @@ -42346,7 +42346,7 @@ end // initial bht_bank_rd_data_out_0_239 <= 2'h0; end else if (bht_bank_sel_0_14_15) begin if (_T_8716) begin - bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_239 <= io_exu_mp_pkt_bits_hist; end @@ -42357,7 +42357,7 @@ end // initial bht_bank_rd_data_out_0_240 <= 2'h0; end else if (bht_bank_sel_0_15_0) begin if (_T_8725) begin - bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_240 <= io_exu_mp_pkt_bits_hist; end @@ -42368,7 +42368,7 @@ end // initial bht_bank_rd_data_out_0_241 <= 2'h0; end else if (bht_bank_sel_0_15_1) begin if (_T_8734) begin - bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_241 <= io_exu_mp_pkt_bits_hist; end @@ -42379,7 +42379,7 @@ end // initial bht_bank_rd_data_out_0_242 <= 2'h0; end else if (bht_bank_sel_0_15_2) begin if (_T_8743) begin - bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_242 <= io_exu_mp_pkt_bits_hist; end @@ -42390,7 +42390,7 @@ end // initial bht_bank_rd_data_out_0_243 <= 2'h0; end else if (bht_bank_sel_0_15_3) begin if (_T_8752) begin - bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_243 <= io_exu_mp_pkt_bits_hist; end @@ -42401,7 +42401,7 @@ end // initial bht_bank_rd_data_out_0_244 <= 2'h0; end else if (bht_bank_sel_0_15_4) begin if (_T_8761) begin - bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_244 <= io_exu_mp_pkt_bits_hist; end @@ -42412,7 +42412,7 @@ end // initial bht_bank_rd_data_out_0_245 <= 2'h0; end else if (bht_bank_sel_0_15_5) begin if (_T_8770) begin - bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_245 <= io_exu_mp_pkt_bits_hist; end @@ -42423,7 +42423,7 @@ end // initial bht_bank_rd_data_out_0_246 <= 2'h0; end else if (bht_bank_sel_0_15_6) begin if (_T_8779) begin - bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_246 <= io_exu_mp_pkt_bits_hist; end @@ -42434,7 +42434,7 @@ end // initial bht_bank_rd_data_out_0_247 <= 2'h0; end else if (bht_bank_sel_0_15_7) begin if (_T_8788) begin - bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_247 <= io_exu_mp_pkt_bits_hist; end @@ -42445,7 +42445,7 @@ end // initial bht_bank_rd_data_out_0_248 <= 2'h0; end else if (bht_bank_sel_0_15_8) begin if (_T_8797) begin - bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_248 <= io_exu_mp_pkt_bits_hist; end @@ -42456,7 +42456,7 @@ end // initial bht_bank_rd_data_out_0_249 <= 2'h0; end else if (bht_bank_sel_0_15_9) begin if (_T_8806) begin - bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_249 <= io_exu_mp_pkt_bits_hist; end @@ -42467,7 +42467,7 @@ end // initial bht_bank_rd_data_out_0_250 <= 2'h0; end else if (bht_bank_sel_0_15_10) begin if (_T_8815) begin - bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_250 <= io_exu_mp_pkt_bits_hist; end @@ -42478,7 +42478,7 @@ end // initial bht_bank_rd_data_out_0_251 <= 2'h0; end else if (bht_bank_sel_0_15_11) begin if (_T_8824) begin - bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_251 <= io_exu_mp_pkt_bits_hist; end @@ -42489,7 +42489,7 @@ end // initial bht_bank_rd_data_out_0_252 <= 2'h0; end else if (bht_bank_sel_0_15_12) begin if (_T_8833) begin - bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_252 <= io_exu_mp_pkt_bits_hist; end @@ -42500,7 +42500,7 @@ end // initial bht_bank_rd_data_out_0_253 <= 2'h0; end else if (bht_bank_sel_0_15_13) begin if (_T_8842) begin - bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_253 <= io_exu_mp_pkt_bits_hist; end @@ -42511,7 +42511,7 @@ end // initial bht_bank_rd_data_out_0_254 <= 2'h0; end else if (bht_bank_sel_0_15_14) begin if (_T_8851) begin - bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_254 <= io_exu_mp_pkt_bits_hist; end @@ -42522,7 +42522,7 @@ end // initial bht_bank_rd_data_out_0_255 <= 2'h0; end else if (bht_bank_sel_0_15_15) begin if (_T_8860) begin - bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_255 <= io_exu_mp_pkt_bits_hist; end @@ -43161,14 +43161,14 @@ module el2_ifu_aln_ctl( output io_ifu_pmu_instr_aligned, output [15:0] io_ifu_i0_cinst, output io_i0_brp_valid, - output [11:0] io_i0_brp_bits_toffset, - output [1:0] io_i0_brp_bits_hist, - output io_i0_brp_bits_br_error, - output io_i0_brp_bits_br_start_error, - output io_i0_brp_bits_bank, - output [30:0] io_i0_brp_bits_prett, - output io_i0_brp_bits_way, - output io_i0_brp_bits_ret + output [11:0] io_i0_brp_toffset, + output [1:0] io_i0_brp_hist, + output io_i0_brp_br_error, + output io_i0_brp_br_start_error, + output io_i0_brp_bank, + output [30:0] io_i0_brp_prett, + output io_i0_brp_way, + output io_i0_brp_ret ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -43607,24 +43607,24 @@ module el2_ifu_aln_ctl( wire _T_721 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 378:58] wire _T_722 = _T_719 | _T_721; // @[el2_ifu_aln_ctl.scala 378:47] wire _T_726 = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:100] - wire _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:34] - wire _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:60] + wire _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:29] + wire _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:55] wire _T_734 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 382:29] wire _T_736 = first4B & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 382:55] wire i0_brp_pc4 = _T_734 | _T_736; // @[el2_ifu_aln_ctl.scala 382:44] - wire _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:38] - wire _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:39] - wire _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:67] - wire _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:56] + wire _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:33] + wire _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:34] + wire _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:62] + wire _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:51] wire _T_749 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 387:14] wire _T_751 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42] wire _T_752 = _T_749 | _T_751; // @[el2_ifu_aln_ctl.scala 387:31] wire i0_ends_f1 = first4B & _T_515; // @[el2_ifu_aln_ctl.scala 389:28] - wire _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:47] - wire _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:61] - wire _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:94] - wire _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:92] - wire _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:106] + wire _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42] + wire _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:56] + wire _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89] + wire _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:87] + wire _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:101] rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -43717,14 +43717,14 @@ module el2_ifu_aln_ctl( assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_785; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28] assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 61:19 el2_ifu_aln_ctl.scala 346:19] assign io_i0_brp_valid = _T_722 | _T_726; // @[el2_ifu_aln_ctl.scala 378:19] - assign io_i0_brp_bits_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:26] - assign io_i0_brp_bits_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:23] - assign io_i0_brp_bits_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:27] - assign io_i0_brp_bits_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:34] - assign io_i0_brp_bits_bank = _T_738 ? f0pc[0] : secondpc[0]; // @[el2_ifu_aln_ctl.scala 396:34] - assign io_i0_brp_bits_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:24] - assign io_i0_brp_bits_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:22] - assign io_i0_brp_bits_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:22] + assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:21] + assign io_i0_brp_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:18] + assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22] + assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29] + assign io_i0_brp_bank = _T_738 ? f0pc[0] : secondpc[0]; // @[el2_ifu_aln_ctl.scala 396:29] + assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19] + assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17] + assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_en = _T_354 | _T_358; // @[el2_lib.scala 511:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] @@ -44475,14 +44475,14 @@ module el2_ifu( output io_ifu_i0_pc4, output io_ifu_miss_state_idle, output io_i0_brp_valid, - output [11:0] io_i0_brp_bits_toffset, - output [1:0] io_i0_brp_bits_hist, - output io_i0_brp_bits_br_error, - output io_i0_brp_bits_br_start_error, - output io_i0_brp_bits_bank, - output [30:0] io_i0_brp_bits_prett, - output io_i0_brp_bits_way, - output io_i0_brp_bits_ret, + output [11:0] io_i0_brp_toffset, + output [1:0] io_i0_brp_hist, + output io_i0_brp_br_error, + output io_i0_brp_br_start_error, + output io_i0_brp_bank, + output [30:0] io_i0_brp_prett, + output io_i0_brp_way, + output io_i0_brp_ret, output [7:0] io_ifu_i0_bp_index, output [7:0] io_ifu_i0_bp_fghr, output [4:0] io_ifu_i0_bp_btag, @@ -44505,11 +44505,11 @@ module el2_ifu( input [7:0] io_exu_mp_index, input [4:0] io_exu_mp_btag, input io_dec_tlu_br0_r_pkt_valid, - input [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - input io_dec_tlu_br0_r_pkt_bits_br_error, - input io_dec_tlu_br0_r_pkt_bits_br_start_error, - input io_dec_tlu_br0_r_pkt_bits_way, - input io_dec_tlu_br0_r_pkt_bits_middle, + input [1:0] io_dec_tlu_br0_r_pkt_hist, + input io_dec_tlu_br0_r_pkt_br_error, + input io_dec_tlu_br0_r_pkt_br_start_error, + input io_dec_tlu_br0_r_pkt_way, + input io_dec_tlu_br0_r_pkt_middle, input [7:0] io_exu_i0_br_fghr_r, input [7:0] io_exu_i0_br_index_r, input io_dec_tlu_flush_lower_wb, @@ -44628,11 +44628,11 @@ module el2_ifu( wire [30:0] bp_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 147:25] - wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 147:25] + wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 147:25] wire [7:0] bp_ctl_ch_io_exu_i0_br_fghr_r; // @[el2_ifu.scala 147:25] wire [7:0] bp_ctl_ch_io_exu_i0_br_index_r; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 147:25] @@ -44703,14 +44703,14 @@ module el2_ifu( wire aln_ctl_ch_io_ifu_pmu_instr_aligned; // @[el2_ifu.scala 148:26] wire [15:0] aln_ctl_ch_io_ifu_i0_cinst; // @[el2_ifu.scala 148:26] wire aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 148:26] - wire [11:0] aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 148:26] - wire [1:0] aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_bank; // @[el2_ifu.scala 148:26] - wire [30:0] aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 148:26] + wire [11:0] aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 148:26] + wire [1:0] aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_bank; // @[el2_ifu.scala 148:26] + wire [30:0] aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 148:26] wire ifc_ctl_ch_clock; // @[el2_ifu.scala 149:26] wire ifc_ctl_ch_reset; // @[el2_ifu.scala 149:26] wire ifc_ctl_ch_io_free_clk; // @[el2_ifu.scala 149:26] @@ -44847,11 +44847,11 @@ module el2_ifu( .io_ifc_fetch_addr_f(bp_ctl_ch_io_ifc_fetch_addr_f), .io_ifc_fetch_req_f(bp_ctl_ch_io_ifc_fetch_req_f), .io_dec_tlu_br0_r_pkt_valid(bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle), .io_exu_i0_br_fghr_r(bp_ctl_ch_io_exu_i0_br_fghr_r), .io_exu_i0_br_index_r(bp_ctl_ch_io_exu_i0_br_index_r), .io_dec_tlu_flush_lower_wb(bp_ctl_ch_io_dec_tlu_flush_lower_wb), @@ -44924,14 +44924,14 @@ module el2_ifu( .io_ifu_pmu_instr_aligned(aln_ctl_ch_io_ifu_pmu_instr_aligned), .io_ifu_i0_cinst(aln_ctl_ch_io_ifu_i0_cinst), .io_i0_brp_valid(aln_ctl_ch_io_i0_brp_valid), - .io_i0_brp_bits_toffset(aln_ctl_ch_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(aln_ctl_ch_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(aln_ctl_ch_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(aln_ctl_ch_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_bank(aln_ctl_ch_io_i0_brp_bits_bank), - .io_i0_brp_bits_prett(aln_ctl_ch_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(aln_ctl_ch_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(aln_ctl_ch_io_i0_brp_bits_ret) + .io_i0_brp_toffset(aln_ctl_ch_io_i0_brp_toffset), + .io_i0_brp_hist(aln_ctl_ch_io_i0_brp_hist), + .io_i0_brp_br_error(aln_ctl_ch_io_i0_brp_br_error), + .io_i0_brp_br_start_error(aln_ctl_ch_io_i0_brp_br_start_error), + .io_i0_brp_bank(aln_ctl_ch_io_i0_brp_bank), + .io_i0_brp_prett(aln_ctl_ch_io_i0_brp_prett), + .io_i0_brp_way(aln_ctl_ch_io_i0_brp_way), + .io_i0_brp_ret(aln_ctl_ch_io_i0_brp_ret) ); el2_ifu_ifc_ctl ifc_ctl_ch ( // @[el2_ifu.scala 149:26] .clock(ifc_ctl_ch_clock), @@ -45036,14 +45036,14 @@ module el2_ifu( assign io_ifu_i0_pc4 = aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 328:17] assign io_ifu_miss_state_idle = mem_ctl_ch_io_ifu_miss_state_idle; // @[el2_ifu.scala 329:26] assign io_i0_brp_valid = aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_toffset = aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_hist = aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_br_error = aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_br_start_error = aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_bank = aln_ctl_ch_io_i0_brp_bits_bank; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_prett = aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_way = aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_ret = aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 331:13] + assign io_i0_brp_toffset = aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 331:13] + assign io_i0_brp_hist = aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 331:13] + assign io_i0_brp_br_error = aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 331:13] + assign io_i0_brp_br_start_error = aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 331:13] + assign io_i0_brp_bank = aln_ctl_ch_io_i0_brp_bank; // @[el2_ifu.scala 331:13] + assign io_i0_brp_prett = aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 331:13] + assign io_i0_brp_way = aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 331:13] + assign io_i0_brp_ret = aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 331:13] assign io_ifu_i0_bp_index = aln_ctl_ch_io_ifu_i0_bp_index; // @[el2_ifu.scala 332:22] assign io_ifu_i0_bp_fghr = aln_ctl_ch_io_ifu_i0_bp_fghr; // @[el2_ifu.scala 333:21] assign io_ifu_i0_bp_btag = aln_ctl_ch_io_ifu_i0_bp_btag; // @[el2_ifu.scala 334:21] @@ -45104,11 +45104,11 @@ module el2_ifu( assign bp_ctl_ch_io_ifc_fetch_addr_f = ifc_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 196:33] assign bp_ctl_ch_io_ifc_fetch_req_f = ifc_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 197:32] assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid = io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist = io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error = io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error = io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way = io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle = io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist = io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error = io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error = io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_way = io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle = io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 198:34] assign bp_ctl_ch_io_exu_i0_br_fghr_r = io_exu_i0_br_fghr_r; // @[el2_ifu.scala 199:33] assign bp_ctl_ch_io_exu_i0_br_index_r = io_exu_i0_br_index_r; // @[el2_ifu.scala 200:34] assign bp_ctl_ch_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 201:39] diff --git a/el2_lsu.anno.json b/el2_lsu.anno.json index 429982ac..50caba14 100644 --- a/el2_lsu.anno.json +++ b/el2_lsu.anno.json @@ -132,37 +132,6 @@ "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m", - "sources":[ - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_", - "~el2_lsu|el2_lsu>io_picm_rd_data", - "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", - "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", - "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", - "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu|el2_lsu>io_dccm_ready", @@ -374,6 +343,37 @@ "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m", + "sources":[ + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_pkt", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_pkt", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_pkt", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_pkt", + "~el2_lsu|el2_lsu>io_picm_rd_data", + "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", + "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", + "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned", diff --git a/el2_lsu.fir b/el2_lsu.fir index bc727512..27c949d2 100644 --- a/el2_lsu.fir +++ b/el2_lsu.fir @@ -253,12 +253,12 @@ circuit el2_lsu : module el2_lsu_lsc_ctl : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} + output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 96:29] wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 97:29] wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 98:29] - wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 99:29] + wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 99:29] node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 101:52] node lsu_rs1_d = mux(_T, io.exu_lsu_rs1_d, io.dma_mem_addr) @[el2_lsu_lsc_ctl.scala 101:28] node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 102:44] @@ -432,14 +432,14 @@ circuit el2_lsu : node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[el2_lsu_lsc_ctl.scala 185:92] node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[el2_lsu_lsc_ctl.scala 185:44] lsu_fir_error_m <= _T_103 @[el2_lsu_lsc_ctl.scala 185:38] - wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 186:104] - _T_104.bits.addr <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] - _T_104.bits.mscause <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.bits.addr <= UInt<32>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.bits.mscause <= UInt<4>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.exc_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.inst_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.single_ecc_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] - reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75] + reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.addr <= lsu_error_pkt_m.bits.addr @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.mscause <= lsu_error_pkt_m.bits.mscause @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[el2_lsu_lsc_ctl.scala 186:75] @@ -6362,7 +6362,7 @@ circuit el2_lsu : module el2_lsu_trigger : input clock : Clock input reset : AsyncReset - output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_1 = mux(_T, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] @@ -6420,7 +6420,7 @@ circuit el2_lsu : node _T_44 = and(_T_42, _T_43) @[el2_lsu_trigger.scala 19:58] node _T_45 = or(_T_41, _T_44) @[el2_lsu_trigger.scala 18:152] node _T_46 = and(_T_40, _T_45) @[el2_lsu_trigger.scala 18:94] - node _T_47 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_47 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_48 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_49 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] node _T_50 = not(_T_49) @[el2_lib.scala 241:39] @@ -6430,254 +6430,254 @@ circuit el2_lsu : node _T_54 = eq(_T_52, _T_53) @[el2_lib.scala 242:52] node _T_55 = or(_T_51, _T_54) @[el2_lib.scala 242:41] _T_48[0] <= _T_55 @[el2_lib.scala 242:18] - node _T_56 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 244:30] - node _T_57 = andr(_T_56) @[el2_lib.scala 244:38] - node _T_58 = and(_T_57, _T_51) @[el2_lib.scala 244:43] - node _T_59 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 244:76] - node _T_60 = bits(lsu_match_data_0, 1, 1) @[el2_lib.scala 244:88] - node _T_61 = eq(_T_59, _T_60) @[el2_lib.scala 244:80] - node _T_62 = mux(_T_58, UInt<1>("h01"), _T_61) @[el2_lib.scala 244:25] - _T_48[1] <= _T_62 @[el2_lib.scala 244:19] - node _T_63 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 244:30] - node _T_64 = andr(_T_63) @[el2_lib.scala 244:38] - node _T_65 = and(_T_64, _T_51) @[el2_lib.scala 244:43] - node _T_66 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 244:76] - node _T_67 = bits(lsu_match_data_0, 2, 2) @[el2_lib.scala 244:88] - node _T_68 = eq(_T_66, _T_67) @[el2_lib.scala 244:80] - node _T_69 = mux(_T_65, UInt<1>("h01"), _T_68) @[el2_lib.scala 244:25] - _T_48[2] <= _T_69 @[el2_lib.scala 244:19] - node _T_70 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 244:30] - node _T_71 = andr(_T_70) @[el2_lib.scala 244:38] - node _T_72 = and(_T_71, _T_51) @[el2_lib.scala 244:43] - node _T_73 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 244:76] - node _T_74 = bits(lsu_match_data_0, 3, 3) @[el2_lib.scala 244:88] - node _T_75 = eq(_T_73, _T_74) @[el2_lib.scala 244:80] - node _T_76 = mux(_T_72, UInt<1>("h01"), _T_75) @[el2_lib.scala 244:25] - _T_48[3] <= _T_76 @[el2_lib.scala 244:19] - node _T_77 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 244:30] - node _T_78 = andr(_T_77) @[el2_lib.scala 244:38] - node _T_79 = and(_T_78, _T_51) @[el2_lib.scala 244:43] - node _T_80 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 244:76] - node _T_81 = bits(lsu_match_data_0, 4, 4) @[el2_lib.scala 244:88] - node _T_82 = eq(_T_80, _T_81) @[el2_lib.scala 244:80] - node _T_83 = mux(_T_79, UInt<1>("h01"), _T_82) @[el2_lib.scala 244:25] - _T_48[4] <= _T_83 @[el2_lib.scala 244:19] - node _T_84 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 244:30] - node _T_85 = andr(_T_84) @[el2_lib.scala 244:38] - node _T_86 = and(_T_85, _T_51) @[el2_lib.scala 244:43] - node _T_87 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 244:76] - node _T_88 = bits(lsu_match_data_0, 5, 5) @[el2_lib.scala 244:88] - node _T_89 = eq(_T_87, _T_88) @[el2_lib.scala 244:80] - node _T_90 = mux(_T_86, UInt<1>("h01"), _T_89) @[el2_lib.scala 244:25] - _T_48[5] <= _T_90 @[el2_lib.scala 244:19] - node _T_91 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 244:30] - node _T_92 = andr(_T_91) @[el2_lib.scala 244:38] - node _T_93 = and(_T_92, _T_51) @[el2_lib.scala 244:43] - node _T_94 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 244:76] - node _T_95 = bits(lsu_match_data_0, 6, 6) @[el2_lib.scala 244:88] - node _T_96 = eq(_T_94, _T_95) @[el2_lib.scala 244:80] - node _T_97 = mux(_T_93, UInt<1>("h01"), _T_96) @[el2_lib.scala 244:25] - _T_48[6] <= _T_97 @[el2_lib.scala 244:19] - node _T_98 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 244:30] - node _T_99 = andr(_T_98) @[el2_lib.scala 244:38] - node _T_100 = and(_T_99, _T_51) @[el2_lib.scala 244:43] - node _T_101 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 244:76] - node _T_102 = bits(lsu_match_data_0, 7, 7) @[el2_lib.scala 244:88] - node _T_103 = eq(_T_101, _T_102) @[el2_lib.scala 244:80] - node _T_104 = mux(_T_100, UInt<1>("h01"), _T_103) @[el2_lib.scala 244:25] - _T_48[7] <= _T_104 @[el2_lib.scala 244:19] - node _T_105 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 244:30] - node _T_106 = andr(_T_105) @[el2_lib.scala 244:38] - node _T_107 = and(_T_106, _T_51) @[el2_lib.scala 244:43] - node _T_108 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 244:76] - node _T_109 = bits(lsu_match_data_0, 8, 8) @[el2_lib.scala 244:88] - node _T_110 = eq(_T_108, _T_109) @[el2_lib.scala 244:80] - node _T_111 = mux(_T_107, UInt<1>("h01"), _T_110) @[el2_lib.scala 244:25] - _T_48[8] <= _T_111 @[el2_lib.scala 244:19] - node _T_112 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 244:30] - node _T_113 = andr(_T_112) @[el2_lib.scala 244:38] - node _T_114 = and(_T_113, _T_51) @[el2_lib.scala 244:43] - node _T_115 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 244:76] - node _T_116 = bits(lsu_match_data_0, 9, 9) @[el2_lib.scala 244:88] - node _T_117 = eq(_T_115, _T_116) @[el2_lib.scala 244:80] - node _T_118 = mux(_T_114, UInt<1>("h01"), _T_117) @[el2_lib.scala 244:25] - _T_48[9] <= _T_118 @[el2_lib.scala 244:19] - node _T_119 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 244:30] - node _T_120 = andr(_T_119) @[el2_lib.scala 244:38] - node _T_121 = and(_T_120, _T_51) @[el2_lib.scala 244:43] - node _T_122 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 244:76] - node _T_123 = bits(lsu_match_data_0, 10, 10) @[el2_lib.scala 244:88] - node _T_124 = eq(_T_122, _T_123) @[el2_lib.scala 244:80] - node _T_125 = mux(_T_121, UInt<1>("h01"), _T_124) @[el2_lib.scala 244:25] - _T_48[10] <= _T_125 @[el2_lib.scala 244:19] - node _T_126 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 244:30] - node _T_127 = andr(_T_126) @[el2_lib.scala 244:38] - node _T_128 = and(_T_127, _T_51) @[el2_lib.scala 244:43] - node _T_129 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 244:76] - node _T_130 = bits(lsu_match_data_0, 11, 11) @[el2_lib.scala 244:88] - node _T_131 = eq(_T_129, _T_130) @[el2_lib.scala 244:80] - node _T_132 = mux(_T_128, UInt<1>("h01"), _T_131) @[el2_lib.scala 244:25] - _T_48[11] <= _T_132 @[el2_lib.scala 244:19] - node _T_133 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 244:30] - node _T_134 = andr(_T_133) @[el2_lib.scala 244:38] - node _T_135 = and(_T_134, _T_51) @[el2_lib.scala 244:43] - node _T_136 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 244:76] - node _T_137 = bits(lsu_match_data_0, 12, 12) @[el2_lib.scala 244:88] - node _T_138 = eq(_T_136, _T_137) @[el2_lib.scala 244:80] - node _T_139 = mux(_T_135, UInt<1>("h01"), _T_138) @[el2_lib.scala 244:25] - _T_48[12] <= _T_139 @[el2_lib.scala 244:19] - node _T_140 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 244:30] - node _T_141 = andr(_T_140) @[el2_lib.scala 244:38] - node _T_142 = and(_T_141, _T_51) @[el2_lib.scala 244:43] - node _T_143 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 244:76] - node _T_144 = bits(lsu_match_data_0, 13, 13) @[el2_lib.scala 244:88] - node _T_145 = eq(_T_143, _T_144) @[el2_lib.scala 244:80] - node _T_146 = mux(_T_142, UInt<1>("h01"), _T_145) @[el2_lib.scala 244:25] - _T_48[13] <= _T_146 @[el2_lib.scala 244:19] - node _T_147 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 244:30] - node _T_148 = andr(_T_147) @[el2_lib.scala 244:38] - node _T_149 = and(_T_148, _T_51) @[el2_lib.scala 244:43] - node _T_150 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 244:76] - node _T_151 = bits(lsu_match_data_0, 14, 14) @[el2_lib.scala 244:88] - node _T_152 = eq(_T_150, _T_151) @[el2_lib.scala 244:80] - node _T_153 = mux(_T_149, UInt<1>("h01"), _T_152) @[el2_lib.scala 244:25] - _T_48[14] <= _T_153 @[el2_lib.scala 244:19] - node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 244:30] - node _T_155 = andr(_T_154) @[el2_lib.scala 244:38] - node _T_156 = and(_T_155, _T_51) @[el2_lib.scala 244:43] - node _T_157 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 244:76] - node _T_158 = bits(lsu_match_data_0, 15, 15) @[el2_lib.scala 244:88] - node _T_159 = eq(_T_157, _T_158) @[el2_lib.scala 244:80] - node _T_160 = mux(_T_156, UInt<1>("h01"), _T_159) @[el2_lib.scala 244:25] - _T_48[15] <= _T_160 @[el2_lib.scala 244:19] - node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 244:30] - node _T_162 = andr(_T_161) @[el2_lib.scala 244:38] - node _T_163 = and(_T_162, _T_51) @[el2_lib.scala 244:43] - node _T_164 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 244:76] - node _T_165 = bits(lsu_match_data_0, 16, 16) @[el2_lib.scala 244:88] - node _T_166 = eq(_T_164, _T_165) @[el2_lib.scala 244:80] - node _T_167 = mux(_T_163, UInt<1>("h01"), _T_166) @[el2_lib.scala 244:25] - _T_48[16] <= _T_167 @[el2_lib.scala 244:19] - node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 244:30] - node _T_169 = andr(_T_168) @[el2_lib.scala 244:38] - node _T_170 = and(_T_169, _T_51) @[el2_lib.scala 244:43] - node _T_171 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 244:76] - node _T_172 = bits(lsu_match_data_0, 17, 17) @[el2_lib.scala 244:88] - node _T_173 = eq(_T_171, _T_172) @[el2_lib.scala 244:80] - node _T_174 = mux(_T_170, UInt<1>("h01"), _T_173) @[el2_lib.scala 244:25] - _T_48[17] <= _T_174 @[el2_lib.scala 244:19] - node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 244:30] - node _T_176 = andr(_T_175) @[el2_lib.scala 244:38] - node _T_177 = and(_T_176, _T_51) @[el2_lib.scala 244:43] - node _T_178 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 244:76] - node _T_179 = bits(lsu_match_data_0, 18, 18) @[el2_lib.scala 244:88] - node _T_180 = eq(_T_178, _T_179) @[el2_lib.scala 244:80] - node _T_181 = mux(_T_177, UInt<1>("h01"), _T_180) @[el2_lib.scala 244:25] - _T_48[18] <= _T_181 @[el2_lib.scala 244:19] - node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 244:30] - node _T_183 = andr(_T_182) @[el2_lib.scala 244:38] - node _T_184 = and(_T_183, _T_51) @[el2_lib.scala 244:43] - node _T_185 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 244:76] - node _T_186 = bits(lsu_match_data_0, 19, 19) @[el2_lib.scala 244:88] - node _T_187 = eq(_T_185, _T_186) @[el2_lib.scala 244:80] - node _T_188 = mux(_T_184, UInt<1>("h01"), _T_187) @[el2_lib.scala 244:25] - _T_48[19] <= _T_188 @[el2_lib.scala 244:19] - node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 244:30] - node _T_190 = andr(_T_189) @[el2_lib.scala 244:38] - node _T_191 = and(_T_190, _T_51) @[el2_lib.scala 244:43] - node _T_192 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 244:76] - node _T_193 = bits(lsu_match_data_0, 20, 20) @[el2_lib.scala 244:88] - node _T_194 = eq(_T_192, _T_193) @[el2_lib.scala 244:80] - node _T_195 = mux(_T_191, UInt<1>("h01"), _T_194) @[el2_lib.scala 244:25] - _T_48[20] <= _T_195 @[el2_lib.scala 244:19] - node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 244:30] - node _T_197 = andr(_T_196) @[el2_lib.scala 244:38] - node _T_198 = and(_T_197, _T_51) @[el2_lib.scala 244:43] - node _T_199 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 244:76] - node _T_200 = bits(lsu_match_data_0, 21, 21) @[el2_lib.scala 244:88] - node _T_201 = eq(_T_199, _T_200) @[el2_lib.scala 244:80] - node _T_202 = mux(_T_198, UInt<1>("h01"), _T_201) @[el2_lib.scala 244:25] - _T_48[21] <= _T_202 @[el2_lib.scala 244:19] - node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 244:30] - node _T_204 = andr(_T_203) @[el2_lib.scala 244:38] - node _T_205 = and(_T_204, _T_51) @[el2_lib.scala 244:43] - node _T_206 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 244:76] - node _T_207 = bits(lsu_match_data_0, 22, 22) @[el2_lib.scala 244:88] - node _T_208 = eq(_T_206, _T_207) @[el2_lib.scala 244:80] - node _T_209 = mux(_T_205, UInt<1>("h01"), _T_208) @[el2_lib.scala 244:25] - _T_48[22] <= _T_209 @[el2_lib.scala 244:19] - node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 244:30] - node _T_211 = andr(_T_210) @[el2_lib.scala 244:38] - node _T_212 = and(_T_211, _T_51) @[el2_lib.scala 244:43] - node _T_213 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 244:76] - node _T_214 = bits(lsu_match_data_0, 23, 23) @[el2_lib.scala 244:88] - node _T_215 = eq(_T_213, _T_214) @[el2_lib.scala 244:80] - node _T_216 = mux(_T_212, UInt<1>("h01"), _T_215) @[el2_lib.scala 244:25] - _T_48[23] <= _T_216 @[el2_lib.scala 244:19] - node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 244:30] - node _T_218 = andr(_T_217) @[el2_lib.scala 244:38] - node _T_219 = and(_T_218, _T_51) @[el2_lib.scala 244:43] - node _T_220 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 244:76] - node _T_221 = bits(lsu_match_data_0, 24, 24) @[el2_lib.scala 244:88] - node _T_222 = eq(_T_220, _T_221) @[el2_lib.scala 244:80] - node _T_223 = mux(_T_219, UInt<1>("h01"), _T_222) @[el2_lib.scala 244:25] - _T_48[24] <= _T_223 @[el2_lib.scala 244:19] - node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 244:30] - node _T_225 = andr(_T_224) @[el2_lib.scala 244:38] - node _T_226 = and(_T_225, _T_51) @[el2_lib.scala 244:43] - node _T_227 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 244:76] - node _T_228 = bits(lsu_match_data_0, 25, 25) @[el2_lib.scala 244:88] - node _T_229 = eq(_T_227, _T_228) @[el2_lib.scala 244:80] - node _T_230 = mux(_T_226, UInt<1>("h01"), _T_229) @[el2_lib.scala 244:25] - _T_48[25] <= _T_230 @[el2_lib.scala 244:19] - node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 244:30] - node _T_232 = andr(_T_231) @[el2_lib.scala 244:38] - node _T_233 = and(_T_232, _T_51) @[el2_lib.scala 244:43] - node _T_234 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 244:76] - node _T_235 = bits(lsu_match_data_0, 26, 26) @[el2_lib.scala 244:88] - node _T_236 = eq(_T_234, _T_235) @[el2_lib.scala 244:80] - node _T_237 = mux(_T_233, UInt<1>("h01"), _T_236) @[el2_lib.scala 244:25] - _T_48[26] <= _T_237 @[el2_lib.scala 244:19] - node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 244:30] - node _T_239 = andr(_T_238) @[el2_lib.scala 244:38] - node _T_240 = and(_T_239, _T_51) @[el2_lib.scala 244:43] - node _T_241 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 244:76] - node _T_242 = bits(lsu_match_data_0, 27, 27) @[el2_lib.scala 244:88] - node _T_243 = eq(_T_241, _T_242) @[el2_lib.scala 244:80] - node _T_244 = mux(_T_240, UInt<1>("h01"), _T_243) @[el2_lib.scala 244:25] - _T_48[27] <= _T_244 @[el2_lib.scala 244:19] - node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 244:30] - node _T_246 = andr(_T_245) @[el2_lib.scala 244:38] - node _T_247 = and(_T_246, _T_51) @[el2_lib.scala 244:43] - node _T_248 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 244:76] - node _T_249 = bits(lsu_match_data_0, 28, 28) @[el2_lib.scala 244:88] - node _T_250 = eq(_T_248, _T_249) @[el2_lib.scala 244:80] - node _T_251 = mux(_T_247, UInt<1>("h01"), _T_250) @[el2_lib.scala 244:25] - _T_48[28] <= _T_251 @[el2_lib.scala 244:19] - node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 244:30] - node _T_253 = andr(_T_252) @[el2_lib.scala 244:38] - node _T_254 = and(_T_253, _T_51) @[el2_lib.scala 244:43] - node _T_255 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 244:76] - node _T_256 = bits(lsu_match_data_0, 29, 29) @[el2_lib.scala 244:88] - node _T_257 = eq(_T_255, _T_256) @[el2_lib.scala 244:80] - node _T_258 = mux(_T_254, UInt<1>("h01"), _T_257) @[el2_lib.scala 244:25] - _T_48[29] <= _T_258 @[el2_lib.scala 244:19] - node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 244:30] - node _T_260 = andr(_T_259) @[el2_lib.scala 244:38] - node _T_261 = and(_T_260, _T_51) @[el2_lib.scala 244:43] - node _T_262 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 244:76] - node _T_263 = bits(lsu_match_data_0, 30, 30) @[el2_lib.scala 244:88] - node _T_264 = eq(_T_262, _T_263) @[el2_lib.scala 244:80] - node _T_265 = mux(_T_261, UInt<1>("h01"), _T_264) @[el2_lib.scala 244:25] - _T_48[30] <= _T_265 @[el2_lib.scala 244:19] - node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 244:30] - node _T_267 = andr(_T_266) @[el2_lib.scala 244:38] - node _T_268 = and(_T_267, _T_51) @[el2_lib.scala 244:43] - node _T_269 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 244:76] - node _T_270 = bits(lsu_match_data_0, 31, 31) @[el2_lib.scala 244:88] - node _T_271 = eq(_T_269, _T_270) @[el2_lib.scala 244:80] - node _T_272 = mux(_T_268, UInt<1>("h01"), _T_271) @[el2_lib.scala 244:25] - _T_48[31] <= _T_272 @[el2_lib.scala 244:19] + node _T_56 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_57 = andr(_T_56) @[el2_lib.scala 244:36] + node _T_58 = and(_T_57, _T_51) @[el2_lib.scala 244:41] + node _T_59 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_60 = bits(lsu_match_data_0, 1, 1) @[el2_lib.scala 244:86] + node _T_61 = eq(_T_59, _T_60) @[el2_lib.scala 244:78] + node _T_62 = mux(_T_58, UInt<1>("h01"), _T_61) @[el2_lib.scala 244:23] + _T_48[1] <= _T_62 @[el2_lib.scala 244:17] + node _T_63 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_64 = andr(_T_63) @[el2_lib.scala 244:36] + node _T_65 = and(_T_64, _T_51) @[el2_lib.scala 244:41] + node _T_66 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_67 = bits(lsu_match_data_0, 2, 2) @[el2_lib.scala 244:86] + node _T_68 = eq(_T_66, _T_67) @[el2_lib.scala 244:78] + node _T_69 = mux(_T_65, UInt<1>("h01"), _T_68) @[el2_lib.scala 244:23] + _T_48[2] <= _T_69 @[el2_lib.scala 244:17] + node _T_70 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_71 = andr(_T_70) @[el2_lib.scala 244:36] + node _T_72 = and(_T_71, _T_51) @[el2_lib.scala 244:41] + node _T_73 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_74 = bits(lsu_match_data_0, 3, 3) @[el2_lib.scala 244:86] + node _T_75 = eq(_T_73, _T_74) @[el2_lib.scala 244:78] + node _T_76 = mux(_T_72, UInt<1>("h01"), _T_75) @[el2_lib.scala 244:23] + _T_48[3] <= _T_76 @[el2_lib.scala 244:17] + node _T_77 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_78 = andr(_T_77) @[el2_lib.scala 244:36] + node _T_79 = and(_T_78, _T_51) @[el2_lib.scala 244:41] + node _T_80 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_81 = bits(lsu_match_data_0, 4, 4) @[el2_lib.scala 244:86] + node _T_82 = eq(_T_80, _T_81) @[el2_lib.scala 244:78] + node _T_83 = mux(_T_79, UInt<1>("h01"), _T_82) @[el2_lib.scala 244:23] + _T_48[4] <= _T_83 @[el2_lib.scala 244:17] + node _T_84 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_85 = andr(_T_84) @[el2_lib.scala 244:36] + node _T_86 = and(_T_85, _T_51) @[el2_lib.scala 244:41] + node _T_87 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_88 = bits(lsu_match_data_0, 5, 5) @[el2_lib.scala 244:86] + node _T_89 = eq(_T_87, _T_88) @[el2_lib.scala 244:78] + node _T_90 = mux(_T_86, UInt<1>("h01"), _T_89) @[el2_lib.scala 244:23] + _T_48[5] <= _T_90 @[el2_lib.scala 244:17] + node _T_91 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_92 = andr(_T_91) @[el2_lib.scala 244:36] + node _T_93 = and(_T_92, _T_51) @[el2_lib.scala 244:41] + node _T_94 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_95 = bits(lsu_match_data_0, 6, 6) @[el2_lib.scala 244:86] + node _T_96 = eq(_T_94, _T_95) @[el2_lib.scala 244:78] + node _T_97 = mux(_T_93, UInt<1>("h01"), _T_96) @[el2_lib.scala 244:23] + _T_48[6] <= _T_97 @[el2_lib.scala 244:17] + node _T_98 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_99 = andr(_T_98) @[el2_lib.scala 244:36] + node _T_100 = and(_T_99, _T_51) @[el2_lib.scala 244:41] + node _T_101 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_102 = bits(lsu_match_data_0, 7, 7) @[el2_lib.scala 244:86] + node _T_103 = eq(_T_101, _T_102) @[el2_lib.scala 244:78] + node _T_104 = mux(_T_100, UInt<1>("h01"), _T_103) @[el2_lib.scala 244:23] + _T_48[7] <= _T_104 @[el2_lib.scala 244:17] + node _T_105 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_106 = andr(_T_105) @[el2_lib.scala 244:36] + node _T_107 = and(_T_106, _T_51) @[el2_lib.scala 244:41] + node _T_108 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_109 = bits(lsu_match_data_0, 8, 8) @[el2_lib.scala 244:86] + node _T_110 = eq(_T_108, _T_109) @[el2_lib.scala 244:78] + node _T_111 = mux(_T_107, UInt<1>("h01"), _T_110) @[el2_lib.scala 244:23] + _T_48[8] <= _T_111 @[el2_lib.scala 244:17] + node _T_112 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_113 = andr(_T_112) @[el2_lib.scala 244:36] + node _T_114 = and(_T_113, _T_51) @[el2_lib.scala 244:41] + node _T_115 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_116 = bits(lsu_match_data_0, 9, 9) @[el2_lib.scala 244:86] + node _T_117 = eq(_T_115, _T_116) @[el2_lib.scala 244:78] + node _T_118 = mux(_T_114, UInt<1>("h01"), _T_117) @[el2_lib.scala 244:23] + _T_48[9] <= _T_118 @[el2_lib.scala 244:17] + node _T_119 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_120 = andr(_T_119) @[el2_lib.scala 244:36] + node _T_121 = and(_T_120, _T_51) @[el2_lib.scala 244:41] + node _T_122 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_123 = bits(lsu_match_data_0, 10, 10) @[el2_lib.scala 244:86] + node _T_124 = eq(_T_122, _T_123) @[el2_lib.scala 244:78] + node _T_125 = mux(_T_121, UInt<1>("h01"), _T_124) @[el2_lib.scala 244:23] + _T_48[10] <= _T_125 @[el2_lib.scala 244:17] + node _T_126 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_127 = andr(_T_126) @[el2_lib.scala 244:36] + node _T_128 = and(_T_127, _T_51) @[el2_lib.scala 244:41] + node _T_129 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_130 = bits(lsu_match_data_0, 11, 11) @[el2_lib.scala 244:86] + node _T_131 = eq(_T_129, _T_130) @[el2_lib.scala 244:78] + node _T_132 = mux(_T_128, UInt<1>("h01"), _T_131) @[el2_lib.scala 244:23] + _T_48[11] <= _T_132 @[el2_lib.scala 244:17] + node _T_133 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_134 = andr(_T_133) @[el2_lib.scala 244:36] + node _T_135 = and(_T_134, _T_51) @[el2_lib.scala 244:41] + node _T_136 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_137 = bits(lsu_match_data_0, 12, 12) @[el2_lib.scala 244:86] + node _T_138 = eq(_T_136, _T_137) @[el2_lib.scala 244:78] + node _T_139 = mux(_T_135, UInt<1>("h01"), _T_138) @[el2_lib.scala 244:23] + _T_48[12] <= _T_139 @[el2_lib.scala 244:17] + node _T_140 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_141 = andr(_T_140) @[el2_lib.scala 244:36] + node _T_142 = and(_T_141, _T_51) @[el2_lib.scala 244:41] + node _T_143 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_144 = bits(lsu_match_data_0, 13, 13) @[el2_lib.scala 244:86] + node _T_145 = eq(_T_143, _T_144) @[el2_lib.scala 244:78] + node _T_146 = mux(_T_142, UInt<1>("h01"), _T_145) @[el2_lib.scala 244:23] + _T_48[13] <= _T_146 @[el2_lib.scala 244:17] + node _T_147 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_148 = andr(_T_147) @[el2_lib.scala 244:36] + node _T_149 = and(_T_148, _T_51) @[el2_lib.scala 244:41] + node _T_150 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_151 = bits(lsu_match_data_0, 14, 14) @[el2_lib.scala 244:86] + node _T_152 = eq(_T_150, _T_151) @[el2_lib.scala 244:78] + node _T_153 = mux(_T_149, UInt<1>("h01"), _T_152) @[el2_lib.scala 244:23] + _T_48[14] <= _T_153 @[el2_lib.scala 244:17] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_155 = andr(_T_154) @[el2_lib.scala 244:36] + node _T_156 = and(_T_155, _T_51) @[el2_lib.scala 244:41] + node _T_157 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_158 = bits(lsu_match_data_0, 15, 15) @[el2_lib.scala 244:86] + node _T_159 = eq(_T_157, _T_158) @[el2_lib.scala 244:78] + node _T_160 = mux(_T_156, UInt<1>("h01"), _T_159) @[el2_lib.scala 244:23] + _T_48[15] <= _T_160 @[el2_lib.scala 244:17] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_162 = andr(_T_161) @[el2_lib.scala 244:36] + node _T_163 = and(_T_162, _T_51) @[el2_lib.scala 244:41] + node _T_164 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_165 = bits(lsu_match_data_0, 16, 16) @[el2_lib.scala 244:86] + node _T_166 = eq(_T_164, _T_165) @[el2_lib.scala 244:78] + node _T_167 = mux(_T_163, UInt<1>("h01"), _T_166) @[el2_lib.scala 244:23] + _T_48[16] <= _T_167 @[el2_lib.scala 244:17] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_169 = andr(_T_168) @[el2_lib.scala 244:36] + node _T_170 = and(_T_169, _T_51) @[el2_lib.scala 244:41] + node _T_171 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_172 = bits(lsu_match_data_0, 17, 17) @[el2_lib.scala 244:86] + node _T_173 = eq(_T_171, _T_172) @[el2_lib.scala 244:78] + node _T_174 = mux(_T_170, UInt<1>("h01"), _T_173) @[el2_lib.scala 244:23] + _T_48[17] <= _T_174 @[el2_lib.scala 244:17] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_176 = andr(_T_175) @[el2_lib.scala 244:36] + node _T_177 = and(_T_176, _T_51) @[el2_lib.scala 244:41] + node _T_178 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_179 = bits(lsu_match_data_0, 18, 18) @[el2_lib.scala 244:86] + node _T_180 = eq(_T_178, _T_179) @[el2_lib.scala 244:78] + node _T_181 = mux(_T_177, UInt<1>("h01"), _T_180) @[el2_lib.scala 244:23] + _T_48[18] <= _T_181 @[el2_lib.scala 244:17] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_183 = andr(_T_182) @[el2_lib.scala 244:36] + node _T_184 = and(_T_183, _T_51) @[el2_lib.scala 244:41] + node _T_185 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_186 = bits(lsu_match_data_0, 19, 19) @[el2_lib.scala 244:86] + node _T_187 = eq(_T_185, _T_186) @[el2_lib.scala 244:78] + node _T_188 = mux(_T_184, UInt<1>("h01"), _T_187) @[el2_lib.scala 244:23] + _T_48[19] <= _T_188 @[el2_lib.scala 244:17] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_190 = andr(_T_189) @[el2_lib.scala 244:36] + node _T_191 = and(_T_190, _T_51) @[el2_lib.scala 244:41] + node _T_192 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_193 = bits(lsu_match_data_0, 20, 20) @[el2_lib.scala 244:86] + node _T_194 = eq(_T_192, _T_193) @[el2_lib.scala 244:78] + node _T_195 = mux(_T_191, UInt<1>("h01"), _T_194) @[el2_lib.scala 244:23] + _T_48[20] <= _T_195 @[el2_lib.scala 244:17] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_197 = andr(_T_196) @[el2_lib.scala 244:36] + node _T_198 = and(_T_197, _T_51) @[el2_lib.scala 244:41] + node _T_199 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_200 = bits(lsu_match_data_0, 21, 21) @[el2_lib.scala 244:86] + node _T_201 = eq(_T_199, _T_200) @[el2_lib.scala 244:78] + node _T_202 = mux(_T_198, UInt<1>("h01"), _T_201) @[el2_lib.scala 244:23] + _T_48[21] <= _T_202 @[el2_lib.scala 244:17] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_204 = andr(_T_203) @[el2_lib.scala 244:36] + node _T_205 = and(_T_204, _T_51) @[el2_lib.scala 244:41] + node _T_206 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_207 = bits(lsu_match_data_0, 22, 22) @[el2_lib.scala 244:86] + node _T_208 = eq(_T_206, _T_207) @[el2_lib.scala 244:78] + node _T_209 = mux(_T_205, UInt<1>("h01"), _T_208) @[el2_lib.scala 244:23] + _T_48[22] <= _T_209 @[el2_lib.scala 244:17] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_211 = andr(_T_210) @[el2_lib.scala 244:36] + node _T_212 = and(_T_211, _T_51) @[el2_lib.scala 244:41] + node _T_213 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_214 = bits(lsu_match_data_0, 23, 23) @[el2_lib.scala 244:86] + node _T_215 = eq(_T_213, _T_214) @[el2_lib.scala 244:78] + node _T_216 = mux(_T_212, UInt<1>("h01"), _T_215) @[el2_lib.scala 244:23] + _T_48[23] <= _T_216 @[el2_lib.scala 244:17] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_218 = andr(_T_217) @[el2_lib.scala 244:36] + node _T_219 = and(_T_218, _T_51) @[el2_lib.scala 244:41] + node _T_220 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_221 = bits(lsu_match_data_0, 24, 24) @[el2_lib.scala 244:86] + node _T_222 = eq(_T_220, _T_221) @[el2_lib.scala 244:78] + node _T_223 = mux(_T_219, UInt<1>("h01"), _T_222) @[el2_lib.scala 244:23] + _T_48[24] <= _T_223 @[el2_lib.scala 244:17] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_225 = andr(_T_224) @[el2_lib.scala 244:36] + node _T_226 = and(_T_225, _T_51) @[el2_lib.scala 244:41] + node _T_227 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_228 = bits(lsu_match_data_0, 25, 25) @[el2_lib.scala 244:86] + node _T_229 = eq(_T_227, _T_228) @[el2_lib.scala 244:78] + node _T_230 = mux(_T_226, UInt<1>("h01"), _T_229) @[el2_lib.scala 244:23] + _T_48[25] <= _T_230 @[el2_lib.scala 244:17] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_232 = andr(_T_231) @[el2_lib.scala 244:36] + node _T_233 = and(_T_232, _T_51) @[el2_lib.scala 244:41] + node _T_234 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_235 = bits(lsu_match_data_0, 26, 26) @[el2_lib.scala 244:86] + node _T_236 = eq(_T_234, _T_235) @[el2_lib.scala 244:78] + node _T_237 = mux(_T_233, UInt<1>("h01"), _T_236) @[el2_lib.scala 244:23] + _T_48[26] <= _T_237 @[el2_lib.scala 244:17] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_239 = andr(_T_238) @[el2_lib.scala 244:36] + node _T_240 = and(_T_239, _T_51) @[el2_lib.scala 244:41] + node _T_241 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_242 = bits(lsu_match_data_0, 27, 27) @[el2_lib.scala 244:86] + node _T_243 = eq(_T_241, _T_242) @[el2_lib.scala 244:78] + node _T_244 = mux(_T_240, UInt<1>("h01"), _T_243) @[el2_lib.scala 244:23] + _T_48[27] <= _T_244 @[el2_lib.scala 244:17] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_246 = andr(_T_245) @[el2_lib.scala 244:36] + node _T_247 = and(_T_246, _T_51) @[el2_lib.scala 244:41] + node _T_248 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_249 = bits(lsu_match_data_0, 28, 28) @[el2_lib.scala 244:86] + node _T_250 = eq(_T_248, _T_249) @[el2_lib.scala 244:78] + node _T_251 = mux(_T_247, UInt<1>("h01"), _T_250) @[el2_lib.scala 244:23] + _T_48[28] <= _T_251 @[el2_lib.scala 244:17] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_253 = andr(_T_252) @[el2_lib.scala 244:36] + node _T_254 = and(_T_253, _T_51) @[el2_lib.scala 244:41] + node _T_255 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_256 = bits(lsu_match_data_0, 29, 29) @[el2_lib.scala 244:86] + node _T_257 = eq(_T_255, _T_256) @[el2_lib.scala 244:78] + node _T_258 = mux(_T_254, UInt<1>("h01"), _T_257) @[el2_lib.scala 244:23] + _T_48[29] <= _T_258 @[el2_lib.scala 244:17] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_260 = andr(_T_259) @[el2_lib.scala 244:36] + node _T_261 = and(_T_260, _T_51) @[el2_lib.scala 244:41] + node _T_262 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_263 = bits(lsu_match_data_0, 30, 30) @[el2_lib.scala 244:86] + node _T_264 = eq(_T_262, _T_263) @[el2_lib.scala 244:78] + node _T_265 = mux(_T_261, UInt<1>("h01"), _T_264) @[el2_lib.scala 244:23] + _T_48[30] <= _T_265 @[el2_lib.scala 244:17] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_267 = andr(_T_266) @[el2_lib.scala 244:36] + node _T_268 = and(_T_267, _T_51) @[el2_lib.scala 244:41] + node _T_269 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_270 = bits(lsu_match_data_0, 31, 31) @[el2_lib.scala 244:86] + node _T_271 = eq(_T_269, _T_270) @[el2_lib.scala 244:78] + node _T_272 = mux(_T_268, UInt<1>("h01"), _T_271) @[el2_lib.scala 244:23] + _T_48[31] <= _T_272 @[el2_lib.scala 244:17] node _T_273 = cat(_T_48[1], _T_48[0]) @[el2_lib.scala 245:14] node _T_274 = cat(_T_48[3], _T_48[2]) @[el2_lib.scala 245:14] node _T_275 = cat(_T_274, _T_273) @[el2_lib.scala 245:14] @@ -6718,7 +6718,7 @@ circuit el2_lsu : node _T_310 = and(_T_308, _T_309) @[el2_lsu_trigger.scala 19:58] node _T_311 = or(_T_307, _T_310) @[el2_lsu_trigger.scala 18:152] node _T_312 = and(_T_306, _T_311) @[el2_lsu_trigger.scala 18:94] - node _T_313 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_313 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_314 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_315 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] node _T_316 = not(_T_315) @[el2_lib.scala 241:39] @@ -6728,254 +6728,254 @@ circuit el2_lsu : node _T_320 = eq(_T_318, _T_319) @[el2_lib.scala 242:52] node _T_321 = or(_T_317, _T_320) @[el2_lib.scala 242:41] _T_314[0] <= _T_321 @[el2_lib.scala 242:18] - node _T_322 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 244:30] - node _T_323 = andr(_T_322) @[el2_lib.scala 244:38] - node _T_324 = and(_T_323, _T_317) @[el2_lib.scala 244:43] - node _T_325 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 244:76] - node _T_326 = bits(lsu_match_data_1, 1, 1) @[el2_lib.scala 244:88] - node _T_327 = eq(_T_325, _T_326) @[el2_lib.scala 244:80] - node _T_328 = mux(_T_324, UInt<1>("h01"), _T_327) @[el2_lib.scala 244:25] - _T_314[1] <= _T_328 @[el2_lib.scala 244:19] - node _T_329 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 244:30] - node _T_330 = andr(_T_329) @[el2_lib.scala 244:38] - node _T_331 = and(_T_330, _T_317) @[el2_lib.scala 244:43] - node _T_332 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 244:76] - node _T_333 = bits(lsu_match_data_1, 2, 2) @[el2_lib.scala 244:88] - node _T_334 = eq(_T_332, _T_333) @[el2_lib.scala 244:80] - node _T_335 = mux(_T_331, UInt<1>("h01"), _T_334) @[el2_lib.scala 244:25] - _T_314[2] <= _T_335 @[el2_lib.scala 244:19] - node _T_336 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 244:30] - node _T_337 = andr(_T_336) @[el2_lib.scala 244:38] - node _T_338 = and(_T_337, _T_317) @[el2_lib.scala 244:43] - node _T_339 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 244:76] - node _T_340 = bits(lsu_match_data_1, 3, 3) @[el2_lib.scala 244:88] - node _T_341 = eq(_T_339, _T_340) @[el2_lib.scala 244:80] - node _T_342 = mux(_T_338, UInt<1>("h01"), _T_341) @[el2_lib.scala 244:25] - _T_314[3] <= _T_342 @[el2_lib.scala 244:19] - node _T_343 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 244:30] - node _T_344 = andr(_T_343) @[el2_lib.scala 244:38] - node _T_345 = and(_T_344, _T_317) @[el2_lib.scala 244:43] - node _T_346 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 244:76] - node _T_347 = bits(lsu_match_data_1, 4, 4) @[el2_lib.scala 244:88] - node _T_348 = eq(_T_346, _T_347) @[el2_lib.scala 244:80] - node _T_349 = mux(_T_345, UInt<1>("h01"), _T_348) @[el2_lib.scala 244:25] - _T_314[4] <= _T_349 @[el2_lib.scala 244:19] - node _T_350 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 244:30] - node _T_351 = andr(_T_350) @[el2_lib.scala 244:38] - node _T_352 = and(_T_351, _T_317) @[el2_lib.scala 244:43] - node _T_353 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 244:76] - node _T_354 = bits(lsu_match_data_1, 5, 5) @[el2_lib.scala 244:88] - node _T_355 = eq(_T_353, _T_354) @[el2_lib.scala 244:80] - node _T_356 = mux(_T_352, UInt<1>("h01"), _T_355) @[el2_lib.scala 244:25] - _T_314[5] <= _T_356 @[el2_lib.scala 244:19] - node _T_357 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 244:30] - node _T_358 = andr(_T_357) @[el2_lib.scala 244:38] - node _T_359 = and(_T_358, _T_317) @[el2_lib.scala 244:43] - node _T_360 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 244:76] - node _T_361 = bits(lsu_match_data_1, 6, 6) @[el2_lib.scala 244:88] - node _T_362 = eq(_T_360, _T_361) @[el2_lib.scala 244:80] - node _T_363 = mux(_T_359, UInt<1>("h01"), _T_362) @[el2_lib.scala 244:25] - _T_314[6] <= _T_363 @[el2_lib.scala 244:19] - node _T_364 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 244:30] - node _T_365 = andr(_T_364) @[el2_lib.scala 244:38] - node _T_366 = and(_T_365, _T_317) @[el2_lib.scala 244:43] - node _T_367 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 244:76] - node _T_368 = bits(lsu_match_data_1, 7, 7) @[el2_lib.scala 244:88] - node _T_369 = eq(_T_367, _T_368) @[el2_lib.scala 244:80] - node _T_370 = mux(_T_366, UInt<1>("h01"), _T_369) @[el2_lib.scala 244:25] - _T_314[7] <= _T_370 @[el2_lib.scala 244:19] - node _T_371 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 244:30] - node _T_372 = andr(_T_371) @[el2_lib.scala 244:38] - node _T_373 = and(_T_372, _T_317) @[el2_lib.scala 244:43] - node _T_374 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 244:76] - node _T_375 = bits(lsu_match_data_1, 8, 8) @[el2_lib.scala 244:88] - node _T_376 = eq(_T_374, _T_375) @[el2_lib.scala 244:80] - node _T_377 = mux(_T_373, UInt<1>("h01"), _T_376) @[el2_lib.scala 244:25] - _T_314[8] <= _T_377 @[el2_lib.scala 244:19] - node _T_378 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 244:30] - node _T_379 = andr(_T_378) @[el2_lib.scala 244:38] - node _T_380 = and(_T_379, _T_317) @[el2_lib.scala 244:43] - node _T_381 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 244:76] - node _T_382 = bits(lsu_match_data_1, 9, 9) @[el2_lib.scala 244:88] - node _T_383 = eq(_T_381, _T_382) @[el2_lib.scala 244:80] - node _T_384 = mux(_T_380, UInt<1>("h01"), _T_383) @[el2_lib.scala 244:25] - _T_314[9] <= _T_384 @[el2_lib.scala 244:19] - node _T_385 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 244:30] - node _T_386 = andr(_T_385) @[el2_lib.scala 244:38] - node _T_387 = and(_T_386, _T_317) @[el2_lib.scala 244:43] - node _T_388 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 244:76] - node _T_389 = bits(lsu_match_data_1, 10, 10) @[el2_lib.scala 244:88] - node _T_390 = eq(_T_388, _T_389) @[el2_lib.scala 244:80] - node _T_391 = mux(_T_387, UInt<1>("h01"), _T_390) @[el2_lib.scala 244:25] - _T_314[10] <= _T_391 @[el2_lib.scala 244:19] - node _T_392 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 244:30] - node _T_393 = andr(_T_392) @[el2_lib.scala 244:38] - node _T_394 = and(_T_393, _T_317) @[el2_lib.scala 244:43] - node _T_395 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 244:76] - node _T_396 = bits(lsu_match_data_1, 11, 11) @[el2_lib.scala 244:88] - node _T_397 = eq(_T_395, _T_396) @[el2_lib.scala 244:80] - node _T_398 = mux(_T_394, UInt<1>("h01"), _T_397) @[el2_lib.scala 244:25] - _T_314[11] <= _T_398 @[el2_lib.scala 244:19] - node _T_399 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 244:30] - node _T_400 = andr(_T_399) @[el2_lib.scala 244:38] - node _T_401 = and(_T_400, _T_317) @[el2_lib.scala 244:43] - node _T_402 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 244:76] - node _T_403 = bits(lsu_match_data_1, 12, 12) @[el2_lib.scala 244:88] - node _T_404 = eq(_T_402, _T_403) @[el2_lib.scala 244:80] - node _T_405 = mux(_T_401, UInt<1>("h01"), _T_404) @[el2_lib.scala 244:25] - _T_314[12] <= _T_405 @[el2_lib.scala 244:19] - node _T_406 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 244:30] - node _T_407 = andr(_T_406) @[el2_lib.scala 244:38] - node _T_408 = and(_T_407, _T_317) @[el2_lib.scala 244:43] - node _T_409 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 244:76] - node _T_410 = bits(lsu_match_data_1, 13, 13) @[el2_lib.scala 244:88] - node _T_411 = eq(_T_409, _T_410) @[el2_lib.scala 244:80] - node _T_412 = mux(_T_408, UInt<1>("h01"), _T_411) @[el2_lib.scala 244:25] - _T_314[13] <= _T_412 @[el2_lib.scala 244:19] - node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 244:30] - node _T_414 = andr(_T_413) @[el2_lib.scala 244:38] - node _T_415 = and(_T_414, _T_317) @[el2_lib.scala 244:43] - node _T_416 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 244:76] - node _T_417 = bits(lsu_match_data_1, 14, 14) @[el2_lib.scala 244:88] - node _T_418 = eq(_T_416, _T_417) @[el2_lib.scala 244:80] - node _T_419 = mux(_T_415, UInt<1>("h01"), _T_418) @[el2_lib.scala 244:25] - _T_314[14] <= _T_419 @[el2_lib.scala 244:19] - node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 244:30] - node _T_421 = andr(_T_420) @[el2_lib.scala 244:38] - node _T_422 = and(_T_421, _T_317) @[el2_lib.scala 244:43] - node _T_423 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 244:76] - node _T_424 = bits(lsu_match_data_1, 15, 15) @[el2_lib.scala 244:88] - node _T_425 = eq(_T_423, _T_424) @[el2_lib.scala 244:80] - node _T_426 = mux(_T_422, UInt<1>("h01"), _T_425) @[el2_lib.scala 244:25] - _T_314[15] <= _T_426 @[el2_lib.scala 244:19] - node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 244:30] - node _T_428 = andr(_T_427) @[el2_lib.scala 244:38] - node _T_429 = and(_T_428, _T_317) @[el2_lib.scala 244:43] - node _T_430 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 244:76] - node _T_431 = bits(lsu_match_data_1, 16, 16) @[el2_lib.scala 244:88] - node _T_432 = eq(_T_430, _T_431) @[el2_lib.scala 244:80] - node _T_433 = mux(_T_429, UInt<1>("h01"), _T_432) @[el2_lib.scala 244:25] - _T_314[16] <= _T_433 @[el2_lib.scala 244:19] - node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 244:30] - node _T_435 = andr(_T_434) @[el2_lib.scala 244:38] - node _T_436 = and(_T_435, _T_317) @[el2_lib.scala 244:43] - node _T_437 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 244:76] - node _T_438 = bits(lsu_match_data_1, 17, 17) @[el2_lib.scala 244:88] - node _T_439 = eq(_T_437, _T_438) @[el2_lib.scala 244:80] - node _T_440 = mux(_T_436, UInt<1>("h01"), _T_439) @[el2_lib.scala 244:25] - _T_314[17] <= _T_440 @[el2_lib.scala 244:19] - node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 244:30] - node _T_442 = andr(_T_441) @[el2_lib.scala 244:38] - node _T_443 = and(_T_442, _T_317) @[el2_lib.scala 244:43] - node _T_444 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 244:76] - node _T_445 = bits(lsu_match_data_1, 18, 18) @[el2_lib.scala 244:88] - node _T_446 = eq(_T_444, _T_445) @[el2_lib.scala 244:80] - node _T_447 = mux(_T_443, UInt<1>("h01"), _T_446) @[el2_lib.scala 244:25] - _T_314[18] <= _T_447 @[el2_lib.scala 244:19] - node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 244:30] - node _T_449 = andr(_T_448) @[el2_lib.scala 244:38] - node _T_450 = and(_T_449, _T_317) @[el2_lib.scala 244:43] - node _T_451 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 244:76] - node _T_452 = bits(lsu_match_data_1, 19, 19) @[el2_lib.scala 244:88] - node _T_453 = eq(_T_451, _T_452) @[el2_lib.scala 244:80] - node _T_454 = mux(_T_450, UInt<1>("h01"), _T_453) @[el2_lib.scala 244:25] - _T_314[19] <= _T_454 @[el2_lib.scala 244:19] - node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 244:30] - node _T_456 = andr(_T_455) @[el2_lib.scala 244:38] - node _T_457 = and(_T_456, _T_317) @[el2_lib.scala 244:43] - node _T_458 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 244:76] - node _T_459 = bits(lsu_match_data_1, 20, 20) @[el2_lib.scala 244:88] - node _T_460 = eq(_T_458, _T_459) @[el2_lib.scala 244:80] - node _T_461 = mux(_T_457, UInt<1>("h01"), _T_460) @[el2_lib.scala 244:25] - _T_314[20] <= _T_461 @[el2_lib.scala 244:19] - node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 244:30] - node _T_463 = andr(_T_462) @[el2_lib.scala 244:38] - node _T_464 = and(_T_463, _T_317) @[el2_lib.scala 244:43] - node _T_465 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 244:76] - node _T_466 = bits(lsu_match_data_1, 21, 21) @[el2_lib.scala 244:88] - node _T_467 = eq(_T_465, _T_466) @[el2_lib.scala 244:80] - node _T_468 = mux(_T_464, UInt<1>("h01"), _T_467) @[el2_lib.scala 244:25] - _T_314[21] <= _T_468 @[el2_lib.scala 244:19] - node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 244:30] - node _T_470 = andr(_T_469) @[el2_lib.scala 244:38] - node _T_471 = and(_T_470, _T_317) @[el2_lib.scala 244:43] - node _T_472 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 244:76] - node _T_473 = bits(lsu_match_data_1, 22, 22) @[el2_lib.scala 244:88] - node _T_474 = eq(_T_472, _T_473) @[el2_lib.scala 244:80] - node _T_475 = mux(_T_471, UInt<1>("h01"), _T_474) @[el2_lib.scala 244:25] - _T_314[22] <= _T_475 @[el2_lib.scala 244:19] - node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 244:30] - node _T_477 = andr(_T_476) @[el2_lib.scala 244:38] - node _T_478 = and(_T_477, _T_317) @[el2_lib.scala 244:43] - node _T_479 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 244:76] - node _T_480 = bits(lsu_match_data_1, 23, 23) @[el2_lib.scala 244:88] - node _T_481 = eq(_T_479, _T_480) @[el2_lib.scala 244:80] - node _T_482 = mux(_T_478, UInt<1>("h01"), _T_481) @[el2_lib.scala 244:25] - _T_314[23] <= _T_482 @[el2_lib.scala 244:19] - node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 244:30] - node _T_484 = andr(_T_483) @[el2_lib.scala 244:38] - node _T_485 = and(_T_484, _T_317) @[el2_lib.scala 244:43] - node _T_486 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 244:76] - node _T_487 = bits(lsu_match_data_1, 24, 24) @[el2_lib.scala 244:88] - node _T_488 = eq(_T_486, _T_487) @[el2_lib.scala 244:80] - node _T_489 = mux(_T_485, UInt<1>("h01"), _T_488) @[el2_lib.scala 244:25] - _T_314[24] <= _T_489 @[el2_lib.scala 244:19] - node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 244:30] - node _T_491 = andr(_T_490) @[el2_lib.scala 244:38] - node _T_492 = and(_T_491, _T_317) @[el2_lib.scala 244:43] - node _T_493 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 244:76] - node _T_494 = bits(lsu_match_data_1, 25, 25) @[el2_lib.scala 244:88] - node _T_495 = eq(_T_493, _T_494) @[el2_lib.scala 244:80] - node _T_496 = mux(_T_492, UInt<1>("h01"), _T_495) @[el2_lib.scala 244:25] - _T_314[25] <= _T_496 @[el2_lib.scala 244:19] - node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 244:30] - node _T_498 = andr(_T_497) @[el2_lib.scala 244:38] - node _T_499 = and(_T_498, _T_317) @[el2_lib.scala 244:43] - node _T_500 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 244:76] - node _T_501 = bits(lsu_match_data_1, 26, 26) @[el2_lib.scala 244:88] - node _T_502 = eq(_T_500, _T_501) @[el2_lib.scala 244:80] - node _T_503 = mux(_T_499, UInt<1>("h01"), _T_502) @[el2_lib.scala 244:25] - _T_314[26] <= _T_503 @[el2_lib.scala 244:19] - node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 244:30] - node _T_505 = andr(_T_504) @[el2_lib.scala 244:38] - node _T_506 = and(_T_505, _T_317) @[el2_lib.scala 244:43] - node _T_507 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 244:76] - node _T_508 = bits(lsu_match_data_1, 27, 27) @[el2_lib.scala 244:88] - node _T_509 = eq(_T_507, _T_508) @[el2_lib.scala 244:80] - node _T_510 = mux(_T_506, UInt<1>("h01"), _T_509) @[el2_lib.scala 244:25] - _T_314[27] <= _T_510 @[el2_lib.scala 244:19] - node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 244:30] - node _T_512 = andr(_T_511) @[el2_lib.scala 244:38] - node _T_513 = and(_T_512, _T_317) @[el2_lib.scala 244:43] - node _T_514 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 244:76] - node _T_515 = bits(lsu_match_data_1, 28, 28) @[el2_lib.scala 244:88] - node _T_516 = eq(_T_514, _T_515) @[el2_lib.scala 244:80] - node _T_517 = mux(_T_513, UInt<1>("h01"), _T_516) @[el2_lib.scala 244:25] - _T_314[28] <= _T_517 @[el2_lib.scala 244:19] - node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 244:30] - node _T_519 = andr(_T_518) @[el2_lib.scala 244:38] - node _T_520 = and(_T_519, _T_317) @[el2_lib.scala 244:43] - node _T_521 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 244:76] - node _T_522 = bits(lsu_match_data_1, 29, 29) @[el2_lib.scala 244:88] - node _T_523 = eq(_T_521, _T_522) @[el2_lib.scala 244:80] - node _T_524 = mux(_T_520, UInt<1>("h01"), _T_523) @[el2_lib.scala 244:25] - _T_314[29] <= _T_524 @[el2_lib.scala 244:19] - node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 244:30] - node _T_526 = andr(_T_525) @[el2_lib.scala 244:38] - node _T_527 = and(_T_526, _T_317) @[el2_lib.scala 244:43] - node _T_528 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 244:76] - node _T_529 = bits(lsu_match_data_1, 30, 30) @[el2_lib.scala 244:88] - node _T_530 = eq(_T_528, _T_529) @[el2_lib.scala 244:80] - node _T_531 = mux(_T_527, UInt<1>("h01"), _T_530) @[el2_lib.scala 244:25] - _T_314[30] <= _T_531 @[el2_lib.scala 244:19] - node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 244:30] - node _T_533 = andr(_T_532) @[el2_lib.scala 244:38] - node _T_534 = and(_T_533, _T_317) @[el2_lib.scala 244:43] - node _T_535 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 244:76] - node _T_536 = bits(lsu_match_data_1, 31, 31) @[el2_lib.scala 244:88] - node _T_537 = eq(_T_535, _T_536) @[el2_lib.scala 244:80] - node _T_538 = mux(_T_534, UInt<1>("h01"), _T_537) @[el2_lib.scala 244:25] - _T_314[31] <= _T_538 @[el2_lib.scala 244:19] + node _T_322 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_323 = andr(_T_322) @[el2_lib.scala 244:36] + node _T_324 = and(_T_323, _T_317) @[el2_lib.scala 244:41] + node _T_325 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_326 = bits(lsu_match_data_1, 1, 1) @[el2_lib.scala 244:86] + node _T_327 = eq(_T_325, _T_326) @[el2_lib.scala 244:78] + node _T_328 = mux(_T_324, UInt<1>("h01"), _T_327) @[el2_lib.scala 244:23] + _T_314[1] <= _T_328 @[el2_lib.scala 244:17] + node _T_329 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_330 = andr(_T_329) @[el2_lib.scala 244:36] + node _T_331 = and(_T_330, _T_317) @[el2_lib.scala 244:41] + node _T_332 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_333 = bits(lsu_match_data_1, 2, 2) @[el2_lib.scala 244:86] + node _T_334 = eq(_T_332, _T_333) @[el2_lib.scala 244:78] + node _T_335 = mux(_T_331, UInt<1>("h01"), _T_334) @[el2_lib.scala 244:23] + _T_314[2] <= _T_335 @[el2_lib.scala 244:17] + node _T_336 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_337 = andr(_T_336) @[el2_lib.scala 244:36] + node _T_338 = and(_T_337, _T_317) @[el2_lib.scala 244:41] + node _T_339 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_340 = bits(lsu_match_data_1, 3, 3) @[el2_lib.scala 244:86] + node _T_341 = eq(_T_339, _T_340) @[el2_lib.scala 244:78] + node _T_342 = mux(_T_338, UInt<1>("h01"), _T_341) @[el2_lib.scala 244:23] + _T_314[3] <= _T_342 @[el2_lib.scala 244:17] + node _T_343 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_344 = andr(_T_343) @[el2_lib.scala 244:36] + node _T_345 = and(_T_344, _T_317) @[el2_lib.scala 244:41] + node _T_346 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_347 = bits(lsu_match_data_1, 4, 4) @[el2_lib.scala 244:86] + node _T_348 = eq(_T_346, _T_347) @[el2_lib.scala 244:78] + node _T_349 = mux(_T_345, UInt<1>("h01"), _T_348) @[el2_lib.scala 244:23] + _T_314[4] <= _T_349 @[el2_lib.scala 244:17] + node _T_350 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_351 = andr(_T_350) @[el2_lib.scala 244:36] + node _T_352 = and(_T_351, _T_317) @[el2_lib.scala 244:41] + node _T_353 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_354 = bits(lsu_match_data_1, 5, 5) @[el2_lib.scala 244:86] + node _T_355 = eq(_T_353, _T_354) @[el2_lib.scala 244:78] + node _T_356 = mux(_T_352, UInt<1>("h01"), _T_355) @[el2_lib.scala 244:23] + _T_314[5] <= _T_356 @[el2_lib.scala 244:17] + node _T_357 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_358 = andr(_T_357) @[el2_lib.scala 244:36] + node _T_359 = and(_T_358, _T_317) @[el2_lib.scala 244:41] + node _T_360 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_361 = bits(lsu_match_data_1, 6, 6) @[el2_lib.scala 244:86] + node _T_362 = eq(_T_360, _T_361) @[el2_lib.scala 244:78] + node _T_363 = mux(_T_359, UInt<1>("h01"), _T_362) @[el2_lib.scala 244:23] + _T_314[6] <= _T_363 @[el2_lib.scala 244:17] + node _T_364 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_365 = andr(_T_364) @[el2_lib.scala 244:36] + node _T_366 = and(_T_365, _T_317) @[el2_lib.scala 244:41] + node _T_367 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_368 = bits(lsu_match_data_1, 7, 7) @[el2_lib.scala 244:86] + node _T_369 = eq(_T_367, _T_368) @[el2_lib.scala 244:78] + node _T_370 = mux(_T_366, UInt<1>("h01"), _T_369) @[el2_lib.scala 244:23] + _T_314[7] <= _T_370 @[el2_lib.scala 244:17] + node _T_371 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_372 = andr(_T_371) @[el2_lib.scala 244:36] + node _T_373 = and(_T_372, _T_317) @[el2_lib.scala 244:41] + node _T_374 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_375 = bits(lsu_match_data_1, 8, 8) @[el2_lib.scala 244:86] + node _T_376 = eq(_T_374, _T_375) @[el2_lib.scala 244:78] + node _T_377 = mux(_T_373, UInt<1>("h01"), _T_376) @[el2_lib.scala 244:23] + _T_314[8] <= _T_377 @[el2_lib.scala 244:17] + node _T_378 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_379 = andr(_T_378) @[el2_lib.scala 244:36] + node _T_380 = and(_T_379, _T_317) @[el2_lib.scala 244:41] + node _T_381 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_382 = bits(lsu_match_data_1, 9, 9) @[el2_lib.scala 244:86] + node _T_383 = eq(_T_381, _T_382) @[el2_lib.scala 244:78] + node _T_384 = mux(_T_380, UInt<1>("h01"), _T_383) @[el2_lib.scala 244:23] + _T_314[9] <= _T_384 @[el2_lib.scala 244:17] + node _T_385 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_386 = andr(_T_385) @[el2_lib.scala 244:36] + node _T_387 = and(_T_386, _T_317) @[el2_lib.scala 244:41] + node _T_388 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_389 = bits(lsu_match_data_1, 10, 10) @[el2_lib.scala 244:86] + node _T_390 = eq(_T_388, _T_389) @[el2_lib.scala 244:78] + node _T_391 = mux(_T_387, UInt<1>("h01"), _T_390) @[el2_lib.scala 244:23] + _T_314[10] <= _T_391 @[el2_lib.scala 244:17] + node _T_392 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_393 = andr(_T_392) @[el2_lib.scala 244:36] + node _T_394 = and(_T_393, _T_317) @[el2_lib.scala 244:41] + node _T_395 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_396 = bits(lsu_match_data_1, 11, 11) @[el2_lib.scala 244:86] + node _T_397 = eq(_T_395, _T_396) @[el2_lib.scala 244:78] + node _T_398 = mux(_T_394, UInt<1>("h01"), _T_397) @[el2_lib.scala 244:23] + _T_314[11] <= _T_398 @[el2_lib.scala 244:17] + node _T_399 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_400 = andr(_T_399) @[el2_lib.scala 244:36] + node _T_401 = and(_T_400, _T_317) @[el2_lib.scala 244:41] + node _T_402 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_403 = bits(lsu_match_data_1, 12, 12) @[el2_lib.scala 244:86] + node _T_404 = eq(_T_402, _T_403) @[el2_lib.scala 244:78] + node _T_405 = mux(_T_401, UInt<1>("h01"), _T_404) @[el2_lib.scala 244:23] + _T_314[12] <= _T_405 @[el2_lib.scala 244:17] + node _T_406 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_407 = andr(_T_406) @[el2_lib.scala 244:36] + node _T_408 = and(_T_407, _T_317) @[el2_lib.scala 244:41] + node _T_409 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_410 = bits(lsu_match_data_1, 13, 13) @[el2_lib.scala 244:86] + node _T_411 = eq(_T_409, _T_410) @[el2_lib.scala 244:78] + node _T_412 = mux(_T_408, UInt<1>("h01"), _T_411) @[el2_lib.scala 244:23] + _T_314[13] <= _T_412 @[el2_lib.scala 244:17] + node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_414 = andr(_T_413) @[el2_lib.scala 244:36] + node _T_415 = and(_T_414, _T_317) @[el2_lib.scala 244:41] + node _T_416 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_417 = bits(lsu_match_data_1, 14, 14) @[el2_lib.scala 244:86] + node _T_418 = eq(_T_416, _T_417) @[el2_lib.scala 244:78] + node _T_419 = mux(_T_415, UInt<1>("h01"), _T_418) @[el2_lib.scala 244:23] + _T_314[14] <= _T_419 @[el2_lib.scala 244:17] + node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_421 = andr(_T_420) @[el2_lib.scala 244:36] + node _T_422 = and(_T_421, _T_317) @[el2_lib.scala 244:41] + node _T_423 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_424 = bits(lsu_match_data_1, 15, 15) @[el2_lib.scala 244:86] + node _T_425 = eq(_T_423, _T_424) @[el2_lib.scala 244:78] + node _T_426 = mux(_T_422, UInt<1>("h01"), _T_425) @[el2_lib.scala 244:23] + _T_314[15] <= _T_426 @[el2_lib.scala 244:17] + node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_428 = andr(_T_427) @[el2_lib.scala 244:36] + node _T_429 = and(_T_428, _T_317) @[el2_lib.scala 244:41] + node _T_430 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_431 = bits(lsu_match_data_1, 16, 16) @[el2_lib.scala 244:86] + node _T_432 = eq(_T_430, _T_431) @[el2_lib.scala 244:78] + node _T_433 = mux(_T_429, UInt<1>("h01"), _T_432) @[el2_lib.scala 244:23] + _T_314[16] <= _T_433 @[el2_lib.scala 244:17] + node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_435 = andr(_T_434) @[el2_lib.scala 244:36] + node _T_436 = and(_T_435, _T_317) @[el2_lib.scala 244:41] + node _T_437 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_438 = bits(lsu_match_data_1, 17, 17) @[el2_lib.scala 244:86] + node _T_439 = eq(_T_437, _T_438) @[el2_lib.scala 244:78] + node _T_440 = mux(_T_436, UInt<1>("h01"), _T_439) @[el2_lib.scala 244:23] + _T_314[17] <= _T_440 @[el2_lib.scala 244:17] + node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_442 = andr(_T_441) @[el2_lib.scala 244:36] + node _T_443 = and(_T_442, _T_317) @[el2_lib.scala 244:41] + node _T_444 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_445 = bits(lsu_match_data_1, 18, 18) @[el2_lib.scala 244:86] + node _T_446 = eq(_T_444, _T_445) @[el2_lib.scala 244:78] + node _T_447 = mux(_T_443, UInt<1>("h01"), _T_446) @[el2_lib.scala 244:23] + _T_314[18] <= _T_447 @[el2_lib.scala 244:17] + node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_449 = andr(_T_448) @[el2_lib.scala 244:36] + node _T_450 = and(_T_449, _T_317) @[el2_lib.scala 244:41] + node _T_451 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_452 = bits(lsu_match_data_1, 19, 19) @[el2_lib.scala 244:86] + node _T_453 = eq(_T_451, _T_452) @[el2_lib.scala 244:78] + node _T_454 = mux(_T_450, UInt<1>("h01"), _T_453) @[el2_lib.scala 244:23] + _T_314[19] <= _T_454 @[el2_lib.scala 244:17] + node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_456 = andr(_T_455) @[el2_lib.scala 244:36] + node _T_457 = and(_T_456, _T_317) @[el2_lib.scala 244:41] + node _T_458 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_459 = bits(lsu_match_data_1, 20, 20) @[el2_lib.scala 244:86] + node _T_460 = eq(_T_458, _T_459) @[el2_lib.scala 244:78] + node _T_461 = mux(_T_457, UInt<1>("h01"), _T_460) @[el2_lib.scala 244:23] + _T_314[20] <= _T_461 @[el2_lib.scala 244:17] + node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_463 = andr(_T_462) @[el2_lib.scala 244:36] + node _T_464 = and(_T_463, _T_317) @[el2_lib.scala 244:41] + node _T_465 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_466 = bits(lsu_match_data_1, 21, 21) @[el2_lib.scala 244:86] + node _T_467 = eq(_T_465, _T_466) @[el2_lib.scala 244:78] + node _T_468 = mux(_T_464, UInt<1>("h01"), _T_467) @[el2_lib.scala 244:23] + _T_314[21] <= _T_468 @[el2_lib.scala 244:17] + node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_470 = andr(_T_469) @[el2_lib.scala 244:36] + node _T_471 = and(_T_470, _T_317) @[el2_lib.scala 244:41] + node _T_472 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_473 = bits(lsu_match_data_1, 22, 22) @[el2_lib.scala 244:86] + node _T_474 = eq(_T_472, _T_473) @[el2_lib.scala 244:78] + node _T_475 = mux(_T_471, UInt<1>("h01"), _T_474) @[el2_lib.scala 244:23] + _T_314[22] <= _T_475 @[el2_lib.scala 244:17] + node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_477 = andr(_T_476) @[el2_lib.scala 244:36] + node _T_478 = and(_T_477, _T_317) @[el2_lib.scala 244:41] + node _T_479 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_480 = bits(lsu_match_data_1, 23, 23) @[el2_lib.scala 244:86] + node _T_481 = eq(_T_479, _T_480) @[el2_lib.scala 244:78] + node _T_482 = mux(_T_478, UInt<1>("h01"), _T_481) @[el2_lib.scala 244:23] + _T_314[23] <= _T_482 @[el2_lib.scala 244:17] + node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_484 = andr(_T_483) @[el2_lib.scala 244:36] + node _T_485 = and(_T_484, _T_317) @[el2_lib.scala 244:41] + node _T_486 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_487 = bits(lsu_match_data_1, 24, 24) @[el2_lib.scala 244:86] + node _T_488 = eq(_T_486, _T_487) @[el2_lib.scala 244:78] + node _T_489 = mux(_T_485, UInt<1>("h01"), _T_488) @[el2_lib.scala 244:23] + _T_314[24] <= _T_489 @[el2_lib.scala 244:17] + node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_491 = andr(_T_490) @[el2_lib.scala 244:36] + node _T_492 = and(_T_491, _T_317) @[el2_lib.scala 244:41] + node _T_493 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_494 = bits(lsu_match_data_1, 25, 25) @[el2_lib.scala 244:86] + node _T_495 = eq(_T_493, _T_494) @[el2_lib.scala 244:78] + node _T_496 = mux(_T_492, UInt<1>("h01"), _T_495) @[el2_lib.scala 244:23] + _T_314[25] <= _T_496 @[el2_lib.scala 244:17] + node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_498 = andr(_T_497) @[el2_lib.scala 244:36] + node _T_499 = and(_T_498, _T_317) @[el2_lib.scala 244:41] + node _T_500 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_501 = bits(lsu_match_data_1, 26, 26) @[el2_lib.scala 244:86] + node _T_502 = eq(_T_500, _T_501) @[el2_lib.scala 244:78] + node _T_503 = mux(_T_499, UInt<1>("h01"), _T_502) @[el2_lib.scala 244:23] + _T_314[26] <= _T_503 @[el2_lib.scala 244:17] + node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_505 = andr(_T_504) @[el2_lib.scala 244:36] + node _T_506 = and(_T_505, _T_317) @[el2_lib.scala 244:41] + node _T_507 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_508 = bits(lsu_match_data_1, 27, 27) @[el2_lib.scala 244:86] + node _T_509 = eq(_T_507, _T_508) @[el2_lib.scala 244:78] + node _T_510 = mux(_T_506, UInt<1>("h01"), _T_509) @[el2_lib.scala 244:23] + _T_314[27] <= _T_510 @[el2_lib.scala 244:17] + node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_512 = andr(_T_511) @[el2_lib.scala 244:36] + node _T_513 = and(_T_512, _T_317) @[el2_lib.scala 244:41] + node _T_514 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_515 = bits(lsu_match_data_1, 28, 28) @[el2_lib.scala 244:86] + node _T_516 = eq(_T_514, _T_515) @[el2_lib.scala 244:78] + node _T_517 = mux(_T_513, UInt<1>("h01"), _T_516) @[el2_lib.scala 244:23] + _T_314[28] <= _T_517 @[el2_lib.scala 244:17] + node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_519 = andr(_T_518) @[el2_lib.scala 244:36] + node _T_520 = and(_T_519, _T_317) @[el2_lib.scala 244:41] + node _T_521 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_522 = bits(lsu_match_data_1, 29, 29) @[el2_lib.scala 244:86] + node _T_523 = eq(_T_521, _T_522) @[el2_lib.scala 244:78] + node _T_524 = mux(_T_520, UInt<1>("h01"), _T_523) @[el2_lib.scala 244:23] + _T_314[29] <= _T_524 @[el2_lib.scala 244:17] + node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_526 = andr(_T_525) @[el2_lib.scala 244:36] + node _T_527 = and(_T_526, _T_317) @[el2_lib.scala 244:41] + node _T_528 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_529 = bits(lsu_match_data_1, 30, 30) @[el2_lib.scala 244:86] + node _T_530 = eq(_T_528, _T_529) @[el2_lib.scala 244:78] + node _T_531 = mux(_T_527, UInt<1>("h01"), _T_530) @[el2_lib.scala 244:23] + _T_314[30] <= _T_531 @[el2_lib.scala 244:17] + node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_533 = andr(_T_532) @[el2_lib.scala 244:36] + node _T_534 = and(_T_533, _T_317) @[el2_lib.scala 244:41] + node _T_535 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_536 = bits(lsu_match_data_1, 31, 31) @[el2_lib.scala 244:86] + node _T_537 = eq(_T_535, _T_536) @[el2_lib.scala 244:78] + node _T_538 = mux(_T_534, UInt<1>("h01"), _T_537) @[el2_lib.scala 244:23] + _T_314[31] <= _T_538 @[el2_lib.scala 244:17] node _T_539 = cat(_T_314[1], _T_314[0]) @[el2_lib.scala 245:14] node _T_540 = cat(_T_314[3], _T_314[2]) @[el2_lib.scala 245:14] node _T_541 = cat(_T_540, _T_539) @[el2_lib.scala 245:14] @@ -7016,7 +7016,7 @@ circuit el2_lsu : node _T_576 = and(_T_574, _T_575) @[el2_lsu_trigger.scala 19:58] node _T_577 = or(_T_573, _T_576) @[el2_lsu_trigger.scala 18:152] node _T_578 = and(_T_572, _T_577) @[el2_lsu_trigger.scala 18:94] - node _T_579 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_579 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_580 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_581 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] node _T_582 = not(_T_581) @[el2_lib.scala 241:39] @@ -7026,254 +7026,254 @@ circuit el2_lsu : node _T_586 = eq(_T_584, _T_585) @[el2_lib.scala 242:52] node _T_587 = or(_T_583, _T_586) @[el2_lib.scala 242:41] _T_580[0] <= _T_587 @[el2_lib.scala 242:18] - node _T_588 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 244:30] - node _T_589 = andr(_T_588) @[el2_lib.scala 244:38] - node _T_590 = and(_T_589, _T_583) @[el2_lib.scala 244:43] - node _T_591 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 244:76] - node _T_592 = bits(lsu_match_data_2, 1, 1) @[el2_lib.scala 244:88] - node _T_593 = eq(_T_591, _T_592) @[el2_lib.scala 244:80] - node _T_594 = mux(_T_590, UInt<1>("h01"), _T_593) @[el2_lib.scala 244:25] - _T_580[1] <= _T_594 @[el2_lib.scala 244:19] - node _T_595 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 244:30] - node _T_596 = andr(_T_595) @[el2_lib.scala 244:38] - node _T_597 = and(_T_596, _T_583) @[el2_lib.scala 244:43] - node _T_598 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 244:76] - node _T_599 = bits(lsu_match_data_2, 2, 2) @[el2_lib.scala 244:88] - node _T_600 = eq(_T_598, _T_599) @[el2_lib.scala 244:80] - node _T_601 = mux(_T_597, UInt<1>("h01"), _T_600) @[el2_lib.scala 244:25] - _T_580[2] <= _T_601 @[el2_lib.scala 244:19] - node _T_602 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 244:30] - node _T_603 = andr(_T_602) @[el2_lib.scala 244:38] - node _T_604 = and(_T_603, _T_583) @[el2_lib.scala 244:43] - node _T_605 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 244:76] - node _T_606 = bits(lsu_match_data_2, 3, 3) @[el2_lib.scala 244:88] - node _T_607 = eq(_T_605, _T_606) @[el2_lib.scala 244:80] - node _T_608 = mux(_T_604, UInt<1>("h01"), _T_607) @[el2_lib.scala 244:25] - _T_580[3] <= _T_608 @[el2_lib.scala 244:19] - node _T_609 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 244:30] - node _T_610 = andr(_T_609) @[el2_lib.scala 244:38] - node _T_611 = and(_T_610, _T_583) @[el2_lib.scala 244:43] - node _T_612 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 244:76] - node _T_613 = bits(lsu_match_data_2, 4, 4) @[el2_lib.scala 244:88] - node _T_614 = eq(_T_612, _T_613) @[el2_lib.scala 244:80] - node _T_615 = mux(_T_611, UInt<1>("h01"), _T_614) @[el2_lib.scala 244:25] - _T_580[4] <= _T_615 @[el2_lib.scala 244:19] - node _T_616 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 244:30] - node _T_617 = andr(_T_616) @[el2_lib.scala 244:38] - node _T_618 = and(_T_617, _T_583) @[el2_lib.scala 244:43] - node _T_619 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 244:76] - node _T_620 = bits(lsu_match_data_2, 5, 5) @[el2_lib.scala 244:88] - node _T_621 = eq(_T_619, _T_620) @[el2_lib.scala 244:80] - node _T_622 = mux(_T_618, UInt<1>("h01"), _T_621) @[el2_lib.scala 244:25] - _T_580[5] <= _T_622 @[el2_lib.scala 244:19] - node _T_623 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 244:30] - node _T_624 = andr(_T_623) @[el2_lib.scala 244:38] - node _T_625 = and(_T_624, _T_583) @[el2_lib.scala 244:43] - node _T_626 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 244:76] - node _T_627 = bits(lsu_match_data_2, 6, 6) @[el2_lib.scala 244:88] - node _T_628 = eq(_T_626, _T_627) @[el2_lib.scala 244:80] - node _T_629 = mux(_T_625, UInt<1>("h01"), _T_628) @[el2_lib.scala 244:25] - _T_580[6] <= _T_629 @[el2_lib.scala 244:19] - node _T_630 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 244:30] - node _T_631 = andr(_T_630) @[el2_lib.scala 244:38] - node _T_632 = and(_T_631, _T_583) @[el2_lib.scala 244:43] - node _T_633 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 244:76] - node _T_634 = bits(lsu_match_data_2, 7, 7) @[el2_lib.scala 244:88] - node _T_635 = eq(_T_633, _T_634) @[el2_lib.scala 244:80] - node _T_636 = mux(_T_632, UInt<1>("h01"), _T_635) @[el2_lib.scala 244:25] - _T_580[7] <= _T_636 @[el2_lib.scala 244:19] - node _T_637 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 244:30] - node _T_638 = andr(_T_637) @[el2_lib.scala 244:38] - node _T_639 = and(_T_638, _T_583) @[el2_lib.scala 244:43] - node _T_640 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 244:76] - node _T_641 = bits(lsu_match_data_2, 8, 8) @[el2_lib.scala 244:88] - node _T_642 = eq(_T_640, _T_641) @[el2_lib.scala 244:80] - node _T_643 = mux(_T_639, UInt<1>("h01"), _T_642) @[el2_lib.scala 244:25] - _T_580[8] <= _T_643 @[el2_lib.scala 244:19] - node _T_644 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 244:30] - node _T_645 = andr(_T_644) @[el2_lib.scala 244:38] - node _T_646 = and(_T_645, _T_583) @[el2_lib.scala 244:43] - node _T_647 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 244:76] - node _T_648 = bits(lsu_match_data_2, 9, 9) @[el2_lib.scala 244:88] - node _T_649 = eq(_T_647, _T_648) @[el2_lib.scala 244:80] - node _T_650 = mux(_T_646, UInt<1>("h01"), _T_649) @[el2_lib.scala 244:25] - _T_580[9] <= _T_650 @[el2_lib.scala 244:19] - node _T_651 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 244:30] - node _T_652 = andr(_T_651) @[el2_lib.scala 244:38] - node _T_653 = and(_T_652, _T_583) @[el2_lib.scala 244:43] - node _T_654 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 244:76] - node _T_655 = bits(lsu_match_data_2, 10, 10) @[el2_lib.scala 244:88] - node _T_656 = eq(_T_654, _T_655) @[el2_lib.scala 244:80] - node _T_657 = mux(_T_653, UInt<1>("h01"), _T_656) @[el2_lib.scala 244:25] - _T_580[10] <= _T_657 @[el2_lib.scala 244:19] - node _T_658 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 244:30] - node _T_659 = andr(_T_658) @[el2_lib.scala 244:38] - node _T_660 = and(_T_659, _T_583) @[el2_lib.scala 244:43] - node _T_661 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 244:76] - node _T_662 = bits(lsu_match_data_2, 11, 11) @[el2_lib.scala 244:88] - node _T_663 = eq(_T_661, _T_662) @[el2_lib.scala 244:80] - node _T_664 = mux(_T_660, UInt<1>("h01"), _T_663) @[el2_lib.scala 244:25] - _T_580[11] <= _T_664 @[el2_lib.scala 244:19] - node _T_665 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 244:30] - node _T_666 = andr(_T_665) @[el2_lib.scala 244:38] - node _T_667 = and(_T_666, _T_583) @[el2_lib.scala 244:43] - node _T_668 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 244:76] - node _T_669 = bits(lsu_match_data_2, 12, 12) @[el2_lib.scala 244:88] - node _T_670 = eq(_T_668, _T_669) @[el2_lib.scala 244:80] - node _T_671 = mux(_T_667, UInt<1>("h01"), _T_670) @[el2_lib.scala 244:25] - _T_580[12] <= _T_671 @[el2_lib.scala 244:19] - node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 244:30] - node _T_673 = andr(_T_672) @[el2_lib.scala 244:38] - node _T_674 = and(_T_673, _T_583) @[el2_lib.scala 244:43] - node _T_675 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 244:76] - node _T_676 = bits(lsu_match_data_2, 13, 13) @[el2_lib.scala 244:88] - node _T_677 = eq(_T_675, _T_676) @[el2_lib.scala 244:80] - node _T_678 = mux(_T_674, UInt<1>("h01"), _T_677) @[el2_lib.scala 244:25] - _T_580[13] <= _T_678 @[el2_lib.scala 244:19] - node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 244:30] - node _T_680 = andr(_T_679) @[el2_lib.scala 244:38] - node _T_681 = and(_T_680, _T_583) @[el2_lib.scala 244:43] - node _T_682 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 244:76] - node _T_683 = bits(lsu_match_data_2, 14, 14) @[el2_lib.scala 244:88] - node _T_684 = eq(_T_682, _T_683) @[el2_lib.scala 244:80] - node _T_685 = mux(_T_681, UInt<1>("h01"), _T_684) @[el2_lib.scala 244:25] - _T_580[14] <= _T_685 @[el2_lib.scala 244:19] - node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 244:30] - node _T_687 = andr(_T_686) @[el2_lib.scala 244:38] - node _T_688 = and(_T_687, _T_583) @[el2_lib.scala 244:43] - node _T_689 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 244:76] - node _T_690 = bits(lsu_match_data_2, 15, 15) @[el2_lib.scala 244:88] - node _T_691 = eq(_T_689, _T_690) @[el2_lib.scala 244:80] - node _T_692 = mux(_T_688, UInt<1>("h01"), _T_691) @[el2_lib.scala 244:25] - _T_580[15] <= _T_692 @[el2_lib.scala 244:19] - node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 244:30] - node _T_694 = andr(_T_693) @[el2_lib.scala 244:38] - node _T_695 = and(_T_694, _T_583) @[el2_lib.scala 244:43] - node _T_696 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 244:76] - node _T_697 = bits(lsu_match_data_2, 16, 16) @[el2_lib.scala 244:88] - node _T_698 = eq(_T_696, _T_697) @[el2_lib.scala 244:80] - node _T_699 = mux(_T_695, UInt<1>("h01"), _T_698) @[el2_lib.scala 244:25] - _T_580[16] <= _T_699 @[el2_lib.scala 244:19] - node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 244:30] - node _T_701 = andr(_T_700) @[el2_lib.scala 244:38] - node _T_702 = and(_T_701, _T_583) @[el2_lib.scala 244:43] - node _T_703 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 244:76] - node _T_704 = bits(lsu_match_data_2, 17, 17) @[el2_lib.scala 244:88] - node _T_705 = eq(_T_703, _T_704) @[el2_lib.scala 244:80] - node _T_706 = mux(_T_702, UInt<1>("h01"), _T_705) @[el2_lib.scala 244:25] - _T_580[17] <= _T_706 @[el2_lib.scala 244:19] - node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 244:30] - node _T_708 = andr(_T_707) @[el2_lib.scala 244:38] - node _T_709 = and(_T_708, _T_583) @[el2_lib.scala 244:43] - node _T_710 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 244:76] - node _T_711 = bits(lsu_match_data_2, 18, 18) @[el2_lib.scala 244:88] - node _T_712 = eq(_T_710, _T_711) @[el2_lib.scala 244:80] - node _T_713 = mux(_T_709, UInt<1>("h01"), _T_712) @[el2_lib.scala 244:25] - _T_580[18] <= _T_713 @[el2_lib.scala 244:19] - node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 244:30] - node _T_715 = andr(_T_714) @[el2_lib.scala 244:38] - node _T_716 = and(_T_715, _T_583) @[el2_lib.scala 244:43] - node _T_717 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 244:76] - node _T_718 = bits(lsu_match_data_2, 19, 19) @[el2_lib.scala 244:88] - node _T_719 = eq(_T_717, _T_718) @[el2_lib.scala 244:80] - node _T_720 = mux(_T_716, UInt<1>("h01"), _T_719) @[el2_lib.scala 244:25] - _T_580[19] <= _T_720 @[el2_lib.scala 244:19] - node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 244:30] - node _T_722 = andr(_T_721) @[el2_lib.scala 244:38] - node _T_723 = and(_T_722, _T_583) @[el2_lib.scala 244:43] - node _T_724 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 244:76] - node _T_725 = bits(lsu_match_data_2, 20, 20) @[el2_lib.scala 244:88] - node _T_726 = eq(_T_724, _T_725) @[el2_lib.scala 244:80] - node _T_727 = mux(_T_723, UInt<1>("h01"), _T_726) @[el2_lib.scala 244:25] - _T_580[20] <= _T_727 @[el2_lib.scala 244:19] - node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 244:30] - node _T_729 = andr(_T_728) @[el2_lib.scala 244:38] - node _T_730 = and(_T_729, _T_583) @[el2_lib.scala 244:43] - node _T_731 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 244:76] - node _T_732 = bits(lsu_match_data_2, 21, 21) @[el2_lib.scala 244:88] - node _T_733 = eq(_T_731, _T_732) @[el2_lib.scala 244:80] - node _T_734 = mux(_T_730, UInt<1>("h01"), _T_733) @[el2_lib.scala 244:25] - _T_580[21] <= _T_734 @[el2_lib.scala 244:19] - node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 244:30] - node _T_736 = andr(_T_735) @[el2_lib.scala 244:38] - node _T_737 = and(_T_736, _T_583) @[el2_lib.scala 244:43] - node _T_738 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 244:76] - node _T_739 = bits(lsu_match_data_2, 22, 22) @[el2_lib.scala 244:88] - node _T_740 = eq(_T_738, _T_739) @[el2_lib.scala 244:80] - node _T_741 = mux(_T_737, UInt<1>("h01"), _T_740) @[el2_lib.scala 244:25] - _T_580[22] <= _T_741 @[el2_lib.scala 244:19] - node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 244:30] - node _T_743 = andr(_T_742) @[el2_lib.scala 244:38] - node _T_744 = and(_T_743, _T_583) @[el2_lib.scala 244:43] - node _T_745 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 244:76] - node _T_746 = bits(lsu_match_data_2, 23, 23) @[el2_lib.scala 244:88] - node _T_747 = eq(_T_745, _T_746) @[el2_lib.scala 244:80] - node _T_748 = mux(_T_744, UInt<1>("h01"), _T_747) @[el2_lib.scala 244:25] - _T_580[23] <= _T_748 @[el2_lib.scala 244:19] - node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 244:30] - node _T_750 = andr(_T_749) @[el2_lib.scala 244:38] - node _T_751 = and(_T_750, _T_583) @[el2_lib.scala 244:43] - node _T_752 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 244:76] - node _T_753 = bits(lsu_match_data_2, 24, 24) @[el2_lib.scala 244:88] - node _T_754 = eq(_T_752, _T_753) @[el2_lib.scala 244:80] - node _T_755 = mux(_T_751, UInt<1>("h01"), _T_754) @[el2_lib.scala 244:25] - _T_580[24] <= _T_755 @[el2_lib.scala 244:19] - node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 244:30] - node _T_757 = andr(_T_756) @[el2_lib.scala 244:38] - node _T_758 = and(_T_757, _T_583) @[el2_lib.scala 244:43] - node _T_759 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 244:76] - node _T_760 = bits(lsu_match_data_2, 25, 25) @[el2_lib.scala 244:88] - node _T_761 = eq(_T_759, _T_760) @[el2_lib.scala 244:80] - node _T_762 = mux(_T_758, UInt<1>("h01"), _T_761) @[el2_lib.scala 244:25] - _T_580[25] <= _T_762 @[el2_lib.scala 244:19] - node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 244:30] - node _T_764 = andr(_T_763) @[el2_lib.scala 244:38] - node _T_765 = and(_T_764, _T_583) @[el2_lib.scala 244:43] - node _T_766 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 244:76] - node _T_767 = bits(lsu_match_data_2, 26, 26) @[el2_lib.scala 244:88] - node _T_768 = eq(_T_766, _T_767) @[el2_lib.scala 244:80] - node _T_769 = mux(_T_765, UInt<1>("h01"), _T_768) @[el2_lib.scala 244:25] - _T_580[26] <= _T_769 @[el2_lib.scala 244:19] - node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 244:30] - node _T_771 = andr(_T_770) @[el2_lib.scala 244:38] - node _T_772 = and(_T_771, _T_583) @[el2_lib.scala 244:43] - node _T_773 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 244:76] - node _T_774 = bits(lsu_match_data_2, 27, 27) @[el2_lib.scala 244:88] - node _T_775 = eq(_T_773, _T_774) @[el2_lib.scala 244:80] - node _T_776 = mux(_T_772, UInt<1>("h01"), _T_775) @[el2_lib.scala 244:25] - _T_580[27] <= _T_776 @[el2_lib.scala 244:19] - node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 244:30] - node _T_778 = andr(_T_777) @[el2_lib.scala 244:38] - node _T_779 = and(_T_778, _T_583) @[el2_lib.scala 244:43] - node _T_780 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 244:76] - node _T_781 = bits(lsu_match_data_2, 28, 28) @[el2_lib.scala 244:88] - node _T_782 = eq(_T_780, _T_781) @[el2_lib.scala 244:80] - node _T_783 = mux(_T_779, UInt<1>("h01"), _T_782) @[el2_lib.scala 244:25] - _T_580[28] <= _T_783 @[el2_lib.scala 244:19] - node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 244:30] - node _T_785 = andr(_T_784) @[el2_lib.scala 244:38] - node _T_786 = and(_T_785, _T_583) @[el2_lib.scala 244:43] - node _T_787 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 244:76] - node _T_788 = bits(lsu_match_data_2, 29, 29) @[el2_lib.scala 244:88] - node _T_789 = eq(_T_787, _T_788) @[el2_lib.scala 244:80] - node _T_790 = mux(_T_786, UInt<1>("h01"), _T_789) @[el2_lib.scala 244:25] - _T_580[29] <= _T_790 @[el2_lib.scala 244:19] - node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 244:30] - node _T_792 = andr(_T_791) @[el2_lib.scala 244:38] - node _T_793 = and(_T_792, _T_583) @[el2_lib.scala 244:43] - node _T_794 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 244:76] - node _T_795 = bits(lsu_match_data_2, 30, 30) @[el2_lib.scala 244:88] - node _T_796 = eq(_T_794, _T_795) @[el2_lib.scala 244:80] - node _T_797 = mux(_T_793, UInt<1>("h01"), _T_796) @[el2_lib.scala 244:25] - _T_580[30] <= _T_797 @[el2_lib.scala 244:19] - node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 244:30] - node _T_799 = andr(_T_798) @[el2_lib.scala 244:38] - node _T_800 = and(_T_799, _T_583) @[el2_lib.scala 244:43] - node _T_801 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 244:76] - node _T_802 = bits(lsu_match_data_2, 31, 31) @[el2_lib.scala 244:88] - node _T_803 = eq(_T_801, _T_802) @[el2_lib.scala 244:80] - node _T_804 = mux(_T_800, UInt<1>("h01"), _T_803) @[el2_lib.scala 244:25] - _T_580[31] <= _T_804 @[el2_lib.scala 244:19] + node _T_588 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_589 = andr(_T_588) @[el2_lib.scala 244:36] + node _T_590 = and(_T_589, _T_583) @[el2_lib.scala 244:41] + node _T_591 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_592 = bits(lsu_match_data_2, 1, 1) @[el2_lib.scala 244:86] + node _T_593 = eq(_T_591, _T_592) @[el2_lib.scala 244:78] + node _T_594 = mux(_T_590, UInt<1>("h01"), _T_593) @[el2_lib.scala 244:23] + _T_580[1] <= _T_594 @[el2_lib.scala 244:17] + node _T_595 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_596 = andr(_T_595) @[el2_lib.scala 244:36] + node _T_597 = and(_T_596, _T_583) @[el2_lib.scala 244:41] + node _T_598 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_599 = bits(lsu_match_data_2, 2, 2) @[el2_lib.scala 244:86] + node _T_600 = eq(_T_598, _T_599) @[el2_lib.scala 244:78] + node _T_601 = mux(_T_597, UInt<1>("h01"), _T_600) @[el2_lib.scala 244:23] + _T_580[2] <= _T_601 @[el2_lib.scala 244:17] + node _T_602 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_603 = andr(_T_602) @[el2_lib.scala 244:36] + node _T_604 = and(_T_603, _T_583) @[el2_lib.scala 244:41] + node _T_605 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_606 = bits(lsu_match_data_2, 3, 3) @[el2_lib.scala 244:86] + node _T_607 = eq(_T_605, _T_606) @[el2_lib.scala 244:78] + node _T_608 = mux(_T_604, UInt<1>("h01"), _T_607) @[el2_lib.scala 244:23] + _T_580[3] <= _T_608 @[el2_lib.scala 244:17] + node _T_609 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_610 = andr(_T_609) @[el2_lib.scala 244:36] + node _T_611 = and(_T_610, _T_583) @[el2_lib.scala 244:41] + node _T_612 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_613 = bits(lsu_match_data_2, 4, 4) @[el2_lib.scala 244:86] + node _T_614 = eq(_T_612, _T_613) @[el2_lib.scala 244:78] + node _T_615 = mux(_T_611, UInt<1>("h01"), _T_614) @[el2_lib.scala 244:23] + _T_580[4] <= _T_615 @[el2_lib.scala 244:17] + node _T_616 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_617 = andr(_T_616) @[el2_lib.scala 244:36] + node _T_618 = and(_T_617, _T_583) @[el2_lib.scala 244:41] + node _T_619 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_620 = bits(lsu_match_data_2, 5, 5) @[el2_lib.scala 244:86] + node _T_621 = eq(_T_619, _T_620) @[el2_lib.scala 244:78] + node _T_622 = mux(_T_618, UInt<1>("h01"), _T_621) @[el2_lib.scala 244:23] + _T_580[5] <= _T_622 @[el2_lib.scala 244:17] + node _T_623 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_624 = andr(_T_623) @[el2_lib.scala 244:36] + node _T_625 = and(_T_624, _T_583) @[el2_lib.scala 244:41] + node _T_626 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_627 = bits(lsu_match_data_2, 6, 6) @[el2_lib.scala 244:86] + node _T_628 = eq(_T_626, _T_627) @[el2_lib.scala 244:78] + node _T_629 = mux(_T_625, UInt<1>("h01"), _T_628) @[el2_lib.scala 244:23] + _T_580[6] <= _T_629 @[el2_lib.scala 244:17] + node _T_630 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_631 = andr(_T_630) @[el2_lib.scala 244:36] + node _T_632 = and(_T_631, _T_583) @[el2_lib.scala 244:41] + node _T_633 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_634 = bits(lsu_match_data_2, 7, 7) @[el2_lib.scala 244:86] + node _T_635 = eq(_T_633, _T_634) @[el2_lib.scala 244:78] + node _T_636 = mux(_T_632, UInt<1>("h01"), _T_635) @[el2_lib.scala 244:23] + _T_580[7] <= _T_636 @[el2_lib.scala 244:17] + node _T_637 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_638 = andr(_T_637) @[el2_lib.scala 244:36] + node _T_639 = and(_T_638, _T_583) @[el2_lib.scala 244:41] + node _T_640 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_641 = bits(lsu_match_data_2, 8, 8) @[el2_lib.scala 244:86] + node _T_642 = eq(_T_640, _T_641) @[el2_lib.scala 244:78] + node _T_643 = mux(_T_639, UInt<1>("h01"), _T_642) @[el2_lib.scala 244:23] + _T_580[8] <= _T_643 @[el2_lib.scala 244:17] + node _T_644 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_645 = andr(_T_644) @[el2_lib.scala 244:36] + node _T_646 = and(_T_645, _T_583) @[el2_lib.scala 244:41] + node _T_647 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_648 = bits(lsu_match_data_2, 9, 9) @[el2_lib.scala 244:86] + node _T_649 = eq(_T_647, _T_648) @[el2_lib.scala 244:78] + node _T_650 = mux(_T_646, UInt<1>("h01"), _T_649) @[el2_lib.scala 244:23] + _T_580[9] <= _T_650 @[el2_lib.scala 244:17] + node _T_651 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_652 = andr(_T_651) @[el2_lib.scala 244:36] + node _T_653 = and(_T_652, _T_583) @[el2_lib.scala 244:41] + node _T_654 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_655 = bits(lsu_match_data_2, 10, 10) @[el2_lib.scala 244:86] + node _T_656 = eq(_T_654, _T_655) @[el2_lib.scala 244:78] + node _T_657 = mux(_T_653, UInt<1>("h01"), _T_656) @[el2_lib.scala 244:23] + _T_580[10] <= _T_657 @[el2_lib.scala 244:17] + node _T_658 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_659 = andr(_T_658) @[el2_lib.scala 244:36] + node _T_660 = and(_T_659, _T_583) @[el2_lib.scala 244:41] + node _T_661 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_662 = bits(lsu_match_data_2, 11, 11) @[el2_lib.scala 244:86] + node _T_663 = eq(_T_661, _T_662) @[el2_lib.scala 244:78] + node _T_664 = mux(_T_660, UInt<1>("h01"), _T_663) @[el2_lib.scala 244:23] + _T_580[11] <= _T_664 @[el2_lib.scala 244:17] + node _T_665 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_666 = andr(_T_665) @[el2_lib.scala 244:36] + node _T_667 = and(_T_666, _T_583) @[el2_lib.scala 244:41] + node _T_668 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_669 = bits(lsu_match_data_2, 12, 12) @[el2_lib.scala 244:86] + node _T_670 = eq(_T_668, _T_669) @[el2_lib.scala 244:78] + node _T_671 = mux(_T_667, UInt<1>("h01"), _T_670) @[el2_lib.scala 244:23] + _T_580[12] <= _T_671 @[el2_lib.scala 244:17] + node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_673 = andr(_T_672) @[el2_lib.scala 244:36] + node _T_674 = and(_T_673, _T_583) @[el2_lib.scala 244:41] + node _T_675 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_676 = bits(lsu_match_data_2, 13, 13) @[el2_lib.scala 244:86] + node _T_677 = eq(_T_675, _T_676) @[el2_lib.scala 244:78] + node _T_678 = mux(_T_674, UInt<1>("h01"), _T_677) @[el2_lib.scala 244:23] + _T_580[13] <= _T_678 @[el2_lib.scala 244:17] + node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_680 = andr(_T_679) @[el2_lib.scala 244:36] + node _T_681 = and(_T_680, _T_583) @[el2_lib.scala 244:41] + node _T_682 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_683 = bits(lsu_match_data_2, 14, 14) @[el2_lib.scala 244:86] + node _T_684 = eq(_T_682, _T_683) @[el2_lib.scala 244:78] + node _T_685 = mux(_T_681, UInt<1>("h01"), _T_684) @[el2_lib.scala 244:23] + _T_580[14] <= _T_685 @[el2_lib.scala 244:17] + node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_687 = andr(_T_686) @[el2_lib.scala 244:36] + node _T_688 = and(_T_687, _T_583) @[el2_lib.scala 244:41] + node _T_689 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_690 = bits(lsu_match_data_2, 15, 15) @[el2_lib.scala 244:86] + node _T_691 = eq(_T_689, _T_690) @[el2_lib.scala 244:78] + node _T_692 = mux(_T_688, UInt<1>("h01"), _T_691) @[el2_lib.scala 244:23] + _T_580[15] <= _T_692 @[el2_lib.scala 244:17] + node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_694 = andr(_T_693) @[el2_lib.scala 244:36] + node _T_695 = and(_T_694, _T_583) @[el2_lib.scala 244:41] + node _T_696 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_697 = bits(lsu_match_data_2, 16, 16) @[el2_lib.scala 244:86] + node _T_698 = eq(_T_696, _T_697) @[el2_lib.scala 244:78] + node _T_699 = mux(_T_695, UInt<1>("h01"), _T_698) @[el2_lib.scala 244:23] + _T_580[16] <= _T_699 @[el2_lib.scala 244:17] + node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_701 = andr(_T_700) @[el2_lib.scala 244:36] + node _T_702 = and(_T_701, _T_583) @[el2_lib.scala 244:41] + node _T_703 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_704 = bits(lsu_match_data_2, 17, 17) @[el2_lib.scala 244:86] + node _T_705 = eq(_T_703, _T_704) @[el2_lib.scala 244:78] + node _T_706 = mux(_T_702, UInt<1>("h01"), _T_705) @[el2_lib.scala 244:23] + _T_580[17] <= _T_706 @[el2_lib.scala 244:17] + node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_708 = andr(_T_707) @[el2_lib.scala 244:36] + node _T_709 = and(_T_708, _T_583) @[el2_lib.scala 244:41] + node _T_710 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_711 = bits(lsu_match_data_2, 18, 18) @[el2_lib.scala 244:86] + node _T_712 = eq(_T_710, _T_711) @[el2_lib.scala 244:78] + node _T_713 = mux(_T_709, UInt<1>("h01"), _T_712) @[el2_lib.scala 244:23] + _T_580[18] <= _T_713 @[el2_lib.scala 244:17] + node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_715 = andr(_T_714) @[el2_lib.scala 244:36] + node _T_716 = and(_T_715, _T_583) @[el2_lib.scala 244:41] + node _T_717 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_718 = bits(lsu_match_data_2, 19, 19) @[el2_lib.scala 244:86] + node _T_719 = eq(_T_717, _T_718) @[el2_lib.scala 244:78] + node _T_720 = mux(_T_716, UInt<1>("h01"), _T_719) @[el2_lib.scala 244:23] + _T_580[19] <= _T_720 @[el2_lib.scala 244:17] + node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_722 = andr(_T_721) @[el2_lib.scala 244:36] + node _T_723 = and(_T_722, _T_583) @[el2_lib.scala 244:41] + node _T_724 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_725 = bits(lsu_match_data_2, 20, 20) @[el2_lib.scala 244:86] + node _T_726 = eq(_T_724, _T_725) @[el2_lib.scala 244:78] + node _T_727 = mux(_T_723, UInt<1>("h01"), _T_726) @[el2_lib.scala 244:23] + _T_580[20] <= _T_727 @[el2_lib.scala 244:17] + node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_729 = andr(_T_728) @[el2_lib.scala 244:36] + node _T_730 = and(_T_729, _T_583) @[el2_lib.scala 244:41] + node _T_731 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_732 = bits(lsu_match_data_2, 21, 21) @[el2_lib.scala 244:86] + node _T_733 = eq(_T_731, _T_732) @[el2_lib.scala 244:78] + node _T_734 = mux(_T_730, UInt<1>("h01"), _T_733) @[el2_lib.scala 244:23] + _T_580[21] <= _T_734 @[el2_lib.scala 244:17] + node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_736 = andr(_T_735) @[el2_lib.scala 244:36] + node _T_737 = and(_T_736, _T_583) @[el2_lib.scala 244:41] + node _T_738 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_739 = bits(lsu_match_data_2, 22, 22) @[el2_lib.scala 244:86] + node _T_740 = eq(_T_738, _T_739) @[el2_lib.scala 244:78] + node _T_741 = mux(_T_737, UInt<1>("h01"), _T_740) @[el2_lib.scala 244:23] + _T_580[22] <= _T_741 @[el2_lib.scala 244:17] + node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_743 = andr(_T_742) @[el2_lib.scala 244:36] + node _T_744 = and(_T_743, _T_583) @[el2_lib.scala 244:41] + node _T_745 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_746 = bits(lsu_match_data_2, 23, 23) @[el2_lib.scala 244:86] + node _T_747 = eq(_T_745, _T_746) @[el2_lib.scala 244:78] + node _T_748 = mux(_T_744, UInt<1>("h01"), _T_747) @[el2_lib.scala 244:23] + _T_580[23] <= _T_748 @[el2_lib.scala 244:17] + node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_750 = andr(_T_749) @[el2_lib.scala 244:36] + node _T_751 = and(_T_750, _T_583) @[el2_lib.scala 244:41] + node _T_752 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_753 = bits(lsu_match_data_2, 24, 24) @[el2_lib.scala 244:86] + node _T_754 = eq(_T_752, _T_753) @[el2_lib.scala 244:78] + node _T_755 = mux(_T_751, UInt<1>("h01"), _T_754) @[el2_lib.scala 244:23] + _T_580[24] <= _T_755 @[el2_lib.scala 244:17] + node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_757 = andr(_T_756) @[el2_lib.scala 244:36] + node _T_758 = and(_T_757, _T_583) @[el2_lib.scala 244:41] + node _T_759 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_760 = bits(lsu_match_data_2, 25, 25) @[el2_lib.scala 244:86] + node _T_761 = eq(_T_759, _T_760) @[el2_lib.scala 244:78] + node _T_762 = mux(_T_758, UInt<1>("h01"), _T_761) @[el2_lib.scala 244:23] + _T_580[25] <= _T_762 @[el2_lib.scala 244:17] + node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_764 = andr(_T_763) @[el2_lib.scala 244:36] + node _T_765 = and(_T_764, _T_583) @[el2_lib.scala 244:41] + node _T_766 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_767 = bits(lsu_match_data_2, 26, 26) @[el2_lib.scala 244:86] + node _T_768 = eq(_T_766, _T_767) @[el2_lib.scala 244:78] + node _T_769 = mux(_T_765, UInt<1>("h01"), _T_768) @[el2_lib.scala 244:23] + _T_580[26] <= _T_769 @[el2_lib.scala 244:17] + node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_771 = andr(_T_770) @[el2_lib.scala 244:36] + node _T_772 = and(_T_771, _T_583) @[el2_lib.scala 244:41] + node _T_773 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_774 = bits(lsu_match_data_2, 27, 27) @[el2_lib.scala 244:86] + node _T_775 = eq(_T_773, _T_774) @[el2_lib.scala 244:78] + node _T_776 = mux(_T_772, UInt<1>("h01"), _T_775) @[el2_lib.scala 244:23] + _T_580[27] <= _T_776 @[el2_lib.scala 244:17] + node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_778 = andr(_T_777) @[el2_lib.scala 244:36] + node _T_779 = and(_T_778, _T_583) @[el2_lib.scala 244:41] + node _T_780 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_781 = bits(lsu_match_data_2, 28, 28) @[el2_lib.scala 244:86] + node _T_782 = eq(_T_780, _T_781) @[el2_lib.scala 244:78] + node _T_783 = mux(_T_779, UInt<1>("h01"), _T_782) @[el2_lib.scala 244:23] + _T_580[28] <= _T_783 @[el2_lib.scala 244:17] + node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_785 = andr(_T_784) @[el2_lib.scala 244:36] + node _T_786 = and(_T_785, _T_583) @[el2_lib.scala 244:41] + node _T_787 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_788 = bits(lsu_match_data_2, 29, 29) @[el2_lib.scala 244:86] + node _T_789 = eq(_T_787, _T_788) @[el2_lib.scala 244:78] + node _T_790 = mux(_T_786, UInt<1>("h01"), _T_789) @[el2_lib.scala 244:23] + _T_580[29] <= _T_790 @[el2_lib.scala 244:17] + node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_792 = andr(_T_791) @[el2_lib.scala 244:36] + node _T_793 = and(_T_792, _T_583) @[el2_lib.scala 244:41] + node _T_794 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_795 = bits(lsu_match_data_2, 30, 30) @[el2_lib.scala 244:86] + node _T_796 = eq(_T_794, _T_795) @[el2_lib.scala 244:78] + node _T_797 = mux(_T_793, UInt<1>("h01"), _T_796) @[el2_lib.scala 244:23] + _T_580[30] <= _T_797 @[el2_lib.scala 244:17] + node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_799 = andr(_T_798) @[el2_lib.scala 244:36] + node _T_800 = and(_T_799, _T_583) @[el2_lib.scala 244:41] + node _T_801 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_802 = bits(lsu_match_data_2, 31, 31) @[el2_lib.scala 244:86] + node _T_803 = eq(_T_801, _T_802) @[el2_lib.scala 244:78] + node _T_804 = mux(_T_800, UInt<1>("h01"), _T_803) @[el2_lib.scala 244:23] + _T_580[31] <= _T_804 @[el2_lib.scala 244:17] node _T_805 = cat(_T_580[1], _T_580[0]) @[el2_lib.scala 245:14] node _T_806 = cat(_T_580[3], _T_580[2]) @[el2_lib.scala 245:14] node _T_807 = cat(_T_806, _T_805) @[el2_lib.scala 245:14] @@ -7314,7 +7314,7 @@ circuit el2_lsu : node _T_842 = and(_T_840, _T_841) @[el2_lsu_trigger.scala 19:58] node _T_843 = or(_T_839, _T_842) @[el2_lsu_trigger.scala 18:152] node _T_844 = and(_T_838, _T_843) @[el2_lsu_trigger.scala 18:94] - node _T_845 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_845 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_846 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_847 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] node _T_848 = not(_T_847) @[el2_lib.scala 241:39] @@ -7324,254 +7324,254 @@ circuit el2_lsu : node _T_852 = eq(_T_850, _T_851) @[el2_lib.scala 242:52] node _T_853 = or(_T_849, _T_852) @[el2_lib.scala 242:41] _T_846[0] <= _T_853 @[el2_lib.scala 242:18] - node _T_854 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 244:30] - node _T_855 = andr(_T_854) @[el2_lib.scala 244:38] - node _T_856 = and(_T_855, _T_849) @[el2_lib.scala 244:43] - node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 244:76] - node _T_858 = bits(lsu_match_data_3, 1, 1) @[el2_lib.scala 244:88] - node _T_859 = eq(_T_857, _T_858) @[el2_lib.scala 244:80] - node _T_860 = mux(_T_856, UInt<1>("h01"), _T_859) @[el2_lib.scala 244:25] - _T_846[1] <= _T_860 @[el2_lib.scala 244:19] - node _T_861 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 244:30] - node _T_862 = andr(_T_861) @[el2_lib.scala 244:38] - node _T_863 = and(_T_862, _T_849) @[el2_lib.scala 244:43] - node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 244:76] - node _T_865 = bits(lsu_match_data_3, 2, 2) @[el2_lib.scala 244:88] - node _T_866 = eq(_T_864, _T_865) @[el2_lib.scala 244:80] - node _T_867 = mux(_T_863, UInt<1>("h01"), _T_866) @[el2_lib.scala 244:25] - _T_846[2] <= _T_867 @[el2_lib.scala 244:19] - node _T_868 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 244:30] - node _T_869 = andr(_T_868) @[el2_lib.scala 244:38] - node _T_870 = and(_T_869, _T_849) @[el2_lib.scala 244:43] - node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 244:76] - node _T_872 = bits(lsu_match_data_3, 3, 3) @[el2_lib.scala 244:88] - node _T_873 = eq(_T_871, _T_872) @[el2_lib.scala 244:80] - node _T_874 = mux(_T_870, UInt<1>("h01"), _T_873) @[el2_lib.scala 244:25] - _T_846[3] <= _T_874 @[el2_lib.scala 244:19] - node _T_875 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 244:30] - node _T_876 = andr(_T_875) @[el2_lib.scala 244:38] - node _T_877 = and(_T_876, _T_849) @[el2_lib.scala 244:43] - node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 244:76] - node _T_879 = bits(lsu_match_data_3, 4, 4) @[el2_lib.scala 244:88] - node _T_880 = eq(_T_878, _T_879) @[el2_lib.scala 244:80] - node _T_881 = mux(_T_877, UInt<1>("h01"), _T_880) @[el2_lib.scala 244:25] - _T_846[4] <= _T_881 @[el2_lib.scala 244:19] - node _T_882 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 244:30] - node _T_883 = andr(_T_882) @[el2_lib.scala 244:38] - node _T_884 = and(_T_883, _T_849) @[el2_lib.scala 244:43] - node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 244:76] - node _T_886 = bits(lsu_match_data_3, 5, 5) @[el2_lib.scala 244:88] - node _T_887 = eq(_T_885, _T_886) @[el2_lib.scala 244:80] - node _T_888 = mux(_T_884, UInt<1>("h01"), _T_887) @[el2_lib.scala 244:25] - _T_846[5] <= _T_888 @[el2_lib.scala 244:19] - node _T_889 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 244:30] - node _T_890 = andr(_T_889) @[el2_lib.scala 244:38] - node _T_891 = and(_T_890, _T_849) @[el2_lib.scala 244:43] - node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 244:76] - node _T_893 = bits(lsu_match_data_3, 6, 6) @[el2_lib.scala 244:88] - node _T_894 = eq(_T_892, _T_893) @[el2_lib.scala 244:80] - node _T_895 = mux(_T_891, UInt<1>("h01"), _T_894) @[el2_lib.scala 244:25] - _T_846[6] <= _T_895 @[el2_lib.scala 244:19] - node _T_896 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 244:30] - node _T_897 = andr(_T_896) @[el2_lib.scala 244:38] - node _T_898 = and(_T_897, _T_849) @[el2_lib.scala 244:43] - node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 244:76] - node _T_900 = bits(lsu_match_data_3, 7, 7) @[el2_lib.scala 244:88] - node _T_901 = eq(_T_899, _T_900) @[el2_lib.scala 244:80] - node _T_902 = mux(_T_898, UInt<1>("h01"), _T_901) @[el2_lib.scala 244:25] - _T_846[7] <= _T_902 @[el2_lib.scala 244:19] - node _T_903 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 244:30] - node _T_904 = andr(_T_903) @[el2_lib.scala 244:38] - node _T_905 = and(_T_904, _T_849) @[el2_lib.scala 244:43] - node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 244:76] - node _T_907 = bits(lsu_match_data_3, 8, 8) @[el2_lib.scala 244:88] - node _T_908 = eq(_T_906, _T_907) @[el2_lib.scala 244:80] - node _T_909 = mux(_T_905, UInt<1>("h01"), _T_908) @[el2_lib.scala 244:25] - _T_846[8] <= _T_909 @[el2_lib.scala 244:19] - node _T_910 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 244:30] - node _T_911 = andr(_T_910) @[el2_lib.scala 244:38] - node _T_912 = and(_T_911, _T_849) @[el2_lib.scala 244:43] - node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 244:76] - node _T_914 = bits(lsu_match_data_3, 9, 9) @[el2_lib.scala 244:88] - node _T_915 = eq(_T_913, _T_914) @[el2_lib.scala 244:80] - node _T_916 = mux(_T_912, UInt<1>("h01"), _T_915) @[el2_lib.scala 244:25] - _T_846[9] <= _T_916 @[el2_lib.scala 244:19] - node _T_917 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 244:30] - node _T_918 = andr(_T_917) @[el2_lib.scala 244:38] - node _T_919 = and(_T_918, _T_849) @[el2_lib.scala 244:43] - node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 244:76] - node _T_921 = bits(lsu_match_data_3, 10, 10) @[el2_lib.scala 244:88] - node _T_922 = eq(_T_920, _T_921) @[el2_lib.scala 244:80] - node _T_923 = mux(_T_919, UInt<1>("h01"), _T_922) @[el2_lib.scala 244:25] - _T_846[10] <= _T_923 @[el2_lib.scala 244:19] - node _T_924 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 244:30] - node _T_925 = andr(_T_924) @[el2_lib.scala 244:38] - node _T_926 = and(_T_925, _T_849) @[el2_lib.scala 244:43] - node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 244:76] - node _T_928 = bits(lsu_match_data_3, 11, 11) @[el2_lib.scala 244:88] - node _T_929 = eq(_T_927, _T_928) @[el2_lib.scala 244:80] - node _T_930 = mux(_T_926, UInt<1>("h01"), _T_929) @[el2_lib.scala 244:25] - _T_846[11] <= _T_930 @[el2_lib.scala 244:19] - node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 244:30] - node _T_932 = andr(_T_931) @[el2_lib.scala 244:38] - node _T_933 = and(_T_932, _T_849) @[el2_lib.scala 244:43] - node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 244:76] - node _T_935 = bits(lsu_match_data_3, 12, 12) @[el2_lib.scala 244:88] - node _T_936 = eq(_T_934, _T_935) @[el2_lib.scala 244:80] - node _T_937 = mux(_T_933, UInt<1>("h01"), _T_936) @[el2_lib.scala 244:25] - _T_846[12] <= _T_937 @[el2_lib.scala 244:19] - node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 244:30] - node _T_939 = andr(_T_938) @[el2_lib.scala 244:38] - node _T_940 = and(_T_939, _T_849) @[el2_lib.scala 244:43] - node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 244:76] - node _T_942 = bits(lsu_match_data_3, 13, 13) @[el2_lib.scala 244:88] - node _T_943 = eq(_T_941, _T_942) @[el2_lib.scala 244:80] - node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[el2_lib.scala 244:25] - _T_846[13] <= _T_944 @[el2_lib.scala 244:19] - node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 244:30] - node _T_946 = andr(_T_945) @[el2_lib.scala 244:38] - node _T_947 = and(_T_946, _T_849) @[el2_lib.scala 244:43] - node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 244:76] - node _T_949 = bits(lsu_match_data_3, 14, 14) @[el2_lib.scala 244:88] - node _T_950 = eq(_T_948, _T_949) @[el2_lib.scala 244:80] - node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[el2_lib.scala 244:25] - _T_846[14] <= _T_951 @[el2_lib.scala 244:19] - node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 244:30] - node _T_953 = andr(_T_952) @[el2_lib.scala 244:38] - node _T_954 = and(_T_953, _T_849) @[el2_lib.scala 244:43] - node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 244:76] - node _T_956 = bits(lsu_match_data_3, 15, 15) @[el2_lib.scala 244:88] - node _T_957 = eq(_T_955, _T_956) @[el2_lib.scala 244:80] - node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[el2_lib.scala 244:25] - _T_846[15] <= _T_958 @[el2_lib.scala 244:19] - node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 244:30] - node _T_960 = andr(_T_959) @[el2_lib.scala 244:38] - node _T_961 = and(_T_960, _T_849) @[el2_lib.scala 244:43] - node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 244:76] - node _T_963 = bits(lsu_match_data_3, 16, 16) @[el2_lib.scala 244:88] - node _T_964 = eq(_T_962, _T_963) @[el2_lib.scala 244:80] - node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[el2_lib.scala 244:25] - _T_846[16] <= _T_965 @[el2_lib.scala 244:19] - node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 244:30] - node _T_967 = andr(_T_966) @[el2_lib.scala 244:38] - node _T_968 = and(_T_967, _T_849) @[el2_lib.scala 244:43] - node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 244:76] - node _T_970 = bits(lsu_match_data_3, 17, 17) @[el2_lib.scala 244:88] - node _T_971 = eq(_T_969, _T_970) @[el2_lib.scala 244:80] - node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[el2_lib.scala 244:25] - _T_846[17] <= _T_972 @[el2_lib.scala 244:19] - node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 244:30] - node _T_974 = andr(_T_973) @[el2_lib.scala 244:38] - node _T_975 = and(_T_974, _T_849) @[el2_lib.scala 244:43] - node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 244:76] - node _T_977 = bits(lsu_match_data_3, 18, 18) @[el2_lib.scala 244:88] - node _T_978 = eq(_T_976, _T_977) @[el2_lib.scala 244:80] - node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[el2_lib.scala 244:25] - _T_846[18] <= _T_979 @[el2_lib.scala 244:19] - node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 244:30] - node _T_981 = andr(_T_980) @[el2_lib.scala 244:38] - node _T_982 = and(_T_981, _T_849) @[el2_lib.scala 244:43] - node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 244:76] - node _T_984 = bits(lsu_match_data_3, 19, 19) @[el2_lib.scala 244:88] - node _T_985 = eq(_T_983, _T_984) @[el2_lib.scala 244:80] - node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[el2_lib.scala 244:25] - _T_846[19] <= _T_986 @[el2_lib.scala 244:19] - node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 244:30] - node _T_988 = andr(_T_987) @[el2_lib.scala 244:38] - node _T_989 = and(_T_988, _T_849) @[el2_lib.scala 244:43] - node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 244:76] - node _T_991 = bits(lsu_match_data_3, 20, 20) @[el2_lib.scala 244:88] - node _T_992 = eq(_T_990, _T_991) @[el2_lib.scala 244:80] - node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[el2_lib.scala 244:25] - _T_846[20] <= _T_993 @[el2_lib.scala 244:19] - node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 244:30] - node _T_995 = andr(_T_994) @[el2_lib.scala 244:38] - node _T_996 = and(_T_995, _T_849) @[el2_lib.scala 244:43] - node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 244:76] - node _T_998 = bits(lsu_match_data_3, 21, 21) @[el2_lib.scala 244:88] - node _T_999 = eq(_T_997, _T_998) @[el2_lib.scala 244:80] - node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[el2_lib.scala 244:25] - _T_846[21] <= _T_1000 @[el2_lib.scala 244:19] - node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 244:30] - node _T_1002 = andr(_T_1001) @[el2_lib.scala 244:38] - node _T_1003 = and(_T_1002, _T_849) @[el2_lib.scala 244:43] - node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 244:76] - node _T_1005 = bits(lsu_match_data_3, 22, 22) @[el2_lib.scala 244:88] - node _T_1006 = eq(_T_1004, _T_1005) @[el2_lib.scala 244:80] - node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[el2_lib.scala 244:25] - _T_846[22] <= _T_1007 @[el2_lib.scala 244:19] - node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 244:30] - node _T_1009 = andr(_T_1008) @[el2_lib.scala 244:38] - node _T_1010 = and(_T_1009, _T_849) @[el2_lib.scala 244:43] - node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 244:76] - node _T_1012 = bits(lsu_match_data_3, 23, 23) @[el2_lib.scala 244:88] - node _T_1013 = eq(_T_1011, _T_1012) @[el2_lib.scala 244:80] - node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[el2_lib.scala 244:25] - _T_846[23] <= _T_1014 @[el2_lib.scala 244:19] - node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 244:30] - node _T_1016 = andr(_T_1015) @[el2_lib.scala 244:38] - node _T_1017 = and(_T_1016, _T_849) @[el2_lib.scala 244:43] - node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 244:76] - node _T_1019 = bits(lsu_match_data_3, 24, 24) @[el2_lib.scala 244:88] - node _T_1020 = eq(_T_1018, _T_1019) @[el2_lib.scala 244:80] - node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[el2_lib.scala 244:25] - _T_846[24] <= _T_1021 @[el2_lib.scala 244:19] - node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 244:30] - node _T_1023 = andr(_T_1022) @[el2_lib.scala 244:38] - node _T_1024 = and(_T_1023, _T_849) @[el2_lib.scala 244:43] - node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 244:76] - node _T_1026 = bits(lsu_match_data_3, 25, 25) @[el2_lib.scala 244:88] - node _T_1027 = eq(_T_1025, _T_1026) @[el2_lib.scala 244:80] - node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[el2_lib.scala 244:25] - _T_846[25] <= _T_1028 @[el2_lib.scala 244:19] - node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 244:30] - node _T_1030 = andr(_T_1029) @[el2_lib.scala 244:38] - node _T_1031 = and(_T_1030, _T_849) @[el2_lib.scala 244:43] - node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 244:76] - node _T_1033 = bits(lsu_match_data_3, 26, 26) @[el2_lib.scala 244:88] - node _T_1034 = eq(_T_1032, _T_1033) @[el2_lib.scala 244:80] - node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[el2_lib.scala 244:25] - _T_846[26] <= _T_1035 @[el2_lib.scala 244:19] - node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 244:30] - node _T_1037 = andr(_T_1036) @[el2_lib.scala 244:38] - node _T_1038 = and(_T_1037, _T_849) @[el2_lib.scala 244:43] - node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 244:76] - node _T_1040 = bits(lsu_match_data_3, 27, 27) @[el2_lib.scala 244:88] - node _T_1041 = eq(_T_1039, _T_1040) @[el2_lib.scala 244:80] - node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[el2_lib.scala 244:25] - _T_846[27] <= _T_1042 @[el2_lib.scala 244:19] - node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 244:30] - node _T_1044 = andr(_T_1043) @[el2_lib.scala 244:38] - node _T_1045 = and(_T_1044, _T_849) @[el2_lib.scala 244:43] - node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 244:76] - node _T_1047 = bits(lsu_match_data_3, 28, 28) @[el2_lib.scala 244:88] - node _T_1048 = eq(_T_1046, _T_1047) @[el2_lib.scala 244:80] - node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[el2_lib.scala 244:25] - _T_846[28] <= _T_1049 @[el2_lib.scala 244:19] - node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 244:30] - node _T_1051 = andr(_T_1050) @[el2_lib.scala 244:38] - node _T_1052 = and(_T_1051, _T_849) @[el2_lib.scala 244:43] - node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 244:76] - node _T_1054 = bits(lsu_match_data_3, 29, 29) @[el2_lib.scala 244:88] - node _T_1055 = eq(_T_1053, _T_1054) @[el2_lib.scala 244:80] - node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[el2_lib.scala 244:25] - _T_846[29] <= _T_1056 @[el2_lib.scala 244:19] - node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 244:30] - node _T_1058 = andr(_T_1057) @[el2_lib.scala 244:38] - node _T_1059 = and(_T_1058, _T_849) @[el2_lib.scala 244:43] - node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 244:76] - node _T_1061 = bits(lsu_match_data_3, 30, 30) @[el2_lib.scala 244:88] - node _T_1062 = eq(_T_1060, _T_1061) @[el2_lib.scala 244:80] - node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[el2_lib.scala 244:25] - _T_846[30] <= _T_1063 @[el2_lib.scala 244:19] - node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 244:30] - node _T_1065 = andr(_T_1064) @[el2_lib.scala 244:38] - node _T_1066 = and(_T_1065, _T_849) @[el2_lib.scala 244:43] - node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 244:76] - node _T_1068 = bits(lsu_match_data_3, 31, 31) @[el2_lib.scala 244:88] - node _T_1069 = eq(_T_1067, _T_1068) @[el2_lib.scala 244:80] - node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[el2_lib.scala 244:25] - _T_846[31] <= _T_1070 @[el2_lib.scala 244:19] + node _T_854 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 244:28] + node _T_855 = andr(_T_854) @[el2_lib.scala 244:36] + node _T_856 = and(_T_855, _T_849) @[el2_lib.scala 244:41] + node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 244:74] + node _T_858 = bits(lsu_match_data_3, 1, 1) @[el2_lib.scala 244:86] + node _T_859 = eq(_T_857, _T_858) @[el2_lib.scala 244:78] + node _T_860 = mux(_T_856, UInt<1>("h01"), _T_859) @[el2_lib.scala 244:23] + _T_846[1] <= _T_860 @[el2_lib.scala 244:17] + node _T_861 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 244:28] + node _T_862 = andr(_T_861) @[el2_lib.scala 244:36] + node _T_863 = and(_T_862, _T_849) @[el2_lib.scala 244:41] + node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 244:74] + node _T_865 = bits(lsu_match_data_3, 2, 2) @[el2_lib.scala 244:86] + node _T_866 = eq(_T_864, _T_865) @[el2_lib.scala 244:78] + node _T_867 = mux(_T_863, UInt<1>("h01"), _T_866) @[el2_lib.scala 244:23] + _T_846[2] <= _T_867 @[el2_lib.scala 244:17] + node _T_868 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 244:28] + node _T_869 = andr(_T_868) @[el2_lib.scala 244:36] + node _T_870 = and(_T_869, _T_849) @[el2_lib.scala 244:41] + node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 244:74] + node _T_872 = bits(lsu_match_data_3, 3, 3) @[el2_lib.scala 244:86] + node _T_873 = eq(_T_871, _T_872) @[el2_lib.scala 244:78] + node _T_874 = mux(_T_870, UInt<1>("h01"), _T_873) @[el2_lib.scala 244:23] + _T_846[3] <= _T_874 @[el2_lib.scala 244:17] + node _T_875 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 244:28] + node _T_876 = andr(_T_875) @[el2_lib.scala 244:36] + node _T_877 = and(_T_876, _T_849) @[el2_lib.scala 244:41] + node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 244:74] + node _T_879 = bits(lsu_match_data_3, 4, 4) @[el2_lib.scala 244:86] + node _T_880 = eq(_T_878, _T_879) @[el2_lib.scala 244:78] + node _T_881 = mux(_T_877, UInt<1>("h01"), _T_880) @[el2_lib.scala 244:23] + _T_846[4] <= _T_881 @[el2_lib.scala 244:17] + node _T_882 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 244:28] + node _T_883 = andr(_T_882) @[el2_lib.scala 244:36] + node _T_884 = and(_T_883, _T_849) @[el2_lib.scala 244:41] + node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 244:74] + node _T_886 = bits(lsu_match_data_3, 5, 5) @[el2_lib.scala 244:86] + node _T_887 = eq(_T_885, _T_886) @[el2_lib.scala 244:78] + node _T_888 = mux(_T_884, UInt<1>("h01"), _T_887) @[el2_lib.scala 244:23] + _T_846[5] <= _T_888 @[el2_lib.scala 244:17] + node _T_889 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 244:28] + node _T_890 = andr(_T_889) @[el2_lib.scala 244:36] + node _T_891 = and(_T_890, _T_849) @[el2_lib.scala 244:41] + node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 244:74] + node _T_893 = bits(lsu_match_data_3, 6, 6) @[el2_lib.scala 244:86] + node _T_894 = eq(_T_892, _T_893) @[el2_lib.scala 244:78] + node _T_895 = mux(_T_891, UInt<1>("h01"), _T_894) @[el2_lib.scala 244:23] + _T_846[6] <= _T_895 @[el2_lib.scala 244:17] + node _T_896 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 244:28] + node _T_897 = andr(_T_896) @[el2_lib.scala 244:36] + node _T_898 = and(_T_897, _T_849) @[el2_lib.scala 244:41] + node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 244:74] + node _T_900 = bits(lsu_match_data_3, 7, 7) @[el2_lib.scala 244:86] + node _T_901 = eq(_T_899, _T_900) @[el2_lib.scala 244:78] + node _T_902 = mux(_T_898, UInt<1>("h01"), _T_901) @[el2_lib.scala 244:23] + _T_846[7] <= _T_902 @[el2_lib.scala 244:17] + node _T_903 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 244:28] + node _T_904 = andr(_T_903) @[el2_lib.scala 244:36] + node _T_905 = and(_T_904, _T_849) @[el2_lib.scala 244:41] + node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 244:74] + node _T_907 = bits(lsu_match_data_3, 8, 8) @[el2_lib.scala 244:86] + node _T_908 = eq(_T_906, _T_907) @[el2_lib.scala 244:78] + node _T_909 = mux(_T_905, UInt<1>("h01"), _T_908) @[el2_lib.scala 244:23] + _T_846[8] <= _T_909 @[el2_lib.scala 244:17] + node _T_910 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 244:28] + node _T_911 = andr(_T_910) @[el2_lib.scala 244:36] + node _T_912 = and(_T_911, _T_849) @[el2_lib.scala 244:41] + node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 244:74] + node _T_914 = bits(lsu_match_data_3, 9, 9) @[el2_lib.scala 244:86] + node _T_915 = eq(_T_913, _T_914) @[el2_lib.scala 244:78] + node _T_916 = mux(_T_912, UInt<1>("h01"), _T_915) @[el2_lib.scala 244:23] + _T_846[9] <= _T_916 @[el2_lib.scala 244:17] + node _T_917 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 244:28] + node _T_918 = andr(_T_917) @[el2_lib.scala 244:36] + node _T_919 = and(_T_918, _T_849) @[el2_lib.scala 244:41] + node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 244:74] + node _T_921 = bits(lsu_match_data_3, 10, 10) @[el2_lib.scala 244:86] + node _T_922 = eq(_T_920, _T_921) @[el2_lib.scala 244:78] + node _T_923 = mux(_T_919, UInt<1>("h01"), _T_922) @[el2_lib.scala 244:23] + _T_846[10] <= _T_923 @[el2_lib.scala 244:17] + node _T_924 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 244:28] + node _T_925 = andr(_T_924) @[el2_lib.scala 244:36] + node _T_926 = and(_T_925, _T_849) @[el2_lib.scala 244:41] + node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 244:74] + node _T_928 = bits(lsu_match_data_3, 11, 11) @[el2_lib.scala 244:86] + node _T_929 = eq(_T_927, _T_928) @[el2_lib.scala 244:78] + node _T_930 = mux(_T_926, UInt<1>("h01"), _T_929) @[el2_lib.scala 244:23] + _T_846[11] <= _T_930 @[el2_lib.scala 244:17] + node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 244:28] + node _T_932 = andr(_T_931) @[el2_lib.scala 244:36] + node _T_933 = and(_T_932, _T_849) @[el2_lib.scala 244:41] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 244:74] + node _T_935 = bits(lsu_match_data_3, 12, 12) @[el2_lib.scala 244:86] + node _T_936 = eq(_T_934, _T_935) @[el2_lib.scala 244:78] + node _T_937 = mux(_T_933, UInt<1>("h01"), _T_936) @[el2_lib.scala 244:23] + _T_846[12] <= _T_937 @[el2_lib.scala 244:17] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 244:28] + node _T_939 = andr(_T_938) @[el2_lib.scala 244:36] + node _T_940 = and(_T_939, _T_849) @[el2_lib.scala 244:41] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 244:74] + node _T_942 = bits(lsu_match_data_3, 13, 13) @[el2_lib.scala 244:86] + node _T_943 = eq(_T_941, _T_942) @[el2_lib.scala 244:78] + node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[el2_lib.scala 244:23] + _T_846[13] <= _T_944 @[el2_lib.scala 244:17] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 244:28] + node _T_946 = andr(_T_945) @[el2_lib.scala 244:36] + node _T_947 = and(_T_946, _T_849) @[el2_lib.scala 244:41] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 244:74] + node _T_949 = bits(lsu_match_data_3, 14, 14) @[el2_lib.scala 244:86] + node _T_950 = eq(_T_948, _T_949) @[el2_lib.scala 244:78] + node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[el2_lib.scala 244:23] + _T_846[14] <= _T_951 @[el2_lib.scala 244:17] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 244:28] + node _T_953 = andr(_T_952) @[el2_lib.scala 244:36] + node _T_954 = and(_T_953, _T_849) @[el2_lib.scala 244:41] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 244:74] + node _T_956 = bits(lsu_match_data_3, 15, 15) @[el2_lib.scala 244:86] + node _T_957 = eq(_T_955, _T_956) @[el2_lib.scala 244:78] + node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[el2_lib.scala 244:23] + _T_846[15] <= _T_958 @[el2_lib.scala 244:17] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 244:28] + node _T_960 = andr(_T_959) @[el2_lib.scala 244:36] + node _T_961 = and(_T_960, _T_849) @[el2_lib.scala 244:41] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 244:74] + node _T_963 = bits(lsu_match_data_3, 16, 16) @[el2_lib.scala 244:86] + node _T_964 = eq(_T_962, _T_963) @[el2_lib.scala 244:78] + node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[el2_lib.scala 244:23] + _T_846[16] <= _T_965 @[el2_lib.scala 244:17] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 244:28] + node _T_967 = andr(_T_966) @[el2_lib.scala 244:36] + node _T_968 = and(_T_967, _T_849) @[el2_lib.scala 244:41] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 244:74] + node _T_970 = bits(lsu_match_data_3, 17, 17) @[el2_lib.scala 244:86] + node _T_971 = eq(_T_969, _T_970) @[el2_lib.scala 244:78] + node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[el2_lib.scala 244:23] + _T_846[17] <= _T_972 @[el2_lib.scala 244:17] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 244:28] + node _T_974 = andr(_T_973) @[el2_lib.scala 244:36] + node _T_975 = and(_T_974, _T_849) @[el2_lib.scala 244:41] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 244:74] + node _T_977 = bits(lsu_match_data_3, 18, 18) @[el2_lib.scala 244:86] + node _T_978 = eq(_T_976, _T_977) @[el2_lib.scala 244:78] + node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[el2_lib.scala 244:23] + _T_846[18] <= _T_979 @[el2_lib.scala 244:17] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 244:28] + node _T_981 = andr(_T_980) @[el2_lib.scala 244:36] + node _T_982 = and(_T_981, _T_849) @[el2_lib.scala 244:41] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 244:74] + node _T_984 = bits(lsu_match_data_3, 19, 19) @[el2_lib.scala 244:86] + node _T_985 = eq(_T_983, _T_984) @[el2_lib.scala 244:78] + node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[el2_lib.scala 244:23] + _T_846[19] <= _T_986 @[el2_lib.scala 244:17] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 244:28] + node _T_988 = andr(_T_987) @[el2_lib.scala 244:36] + node _T_989 = and(_T_988, _T_849) @[el2_lib.scala 244:41] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 244:74] + node _T_991 = bits(lsu_match_data_3, 20, 20) @[el2_lib.scala 244:86] + node _T_992 = eq(_T_990, _T_991) @[el2_lib.scala 244:78] + node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[el2_lib.scala 244:23] + _T_846[20] <= _T_993 @[el2_lib.scala 244:17] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 244:28] + node _T_995 = andr(_T_994) @[el2_lib.scala 244:36] + node _T_996 = and(_T_995, _T_849) @[el2_lib.scala 244:41] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 244:74] + node _T_998 = bits(lsu_match_data_3, 21, 21) @[el2_lib.scala 244:86] + node _T_999 = eq(_T_997, _T_998) @[el2_lib.scala 244:78] + node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[el2_lib.scala 244:23] + _T_846[21] <= _T_1000 @[el2_lib.scala 244:17] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 244:28] + node _T_1002 = andr(_T_1001) @[el2_lib.scala 244:36] + node _T_1003 = and(_T_1002, _T_849) @[el2_lib.scala 244:41] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 244:74] + node _T_1005 = bits(lsu_match_data_3, 22, 22) @[el2_lib.scala 244:86] + node _T_1006 = eq(_T_1004, _T_1005) @[el2_lib.scala 244:78] + node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[el2_lib.scala 244:23] + _T_846[22] <= _T_1007 @[el2_lib.scala 244:17] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 244:28] + node _T_1009 = andr(_T_1008) @[el2_lib.scala 244:36] + node _T_1010 = and(_T_1009, _T_849) @[el2_lib.scala 244:41] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 244:74] + node _T_1012 = bits(lsu_match_data_3, 23, 23) @[el2_lib.scala 244:86] + node _T_1013 = eq(_T_1011, _T_1012) @[el2_lib.scala 244:78] + node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[el2_lib.scala 244:23] + _T_846[23] <= _T_1014 @[el2_lib.scala 244:17] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 244:28] + node _T_1016 = andr(_T_1015) @[el2_lib.scala 244:36] + node _T_1017 = and(_T_1016, _T_849) @[el2_lib.scala 244:41] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 244:74] + node _T_1019 = bits(lsu_match_data_3, 24, 24) @[el2_lib.scala 244:86] + node _T_1020 = eq(_T_1018, _T_1019) @[el2_lib.scala 244:78] + node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[el2_lib.scala 244:23] + _T_846[24] <= _T_1021 @[el2_lib.scala 244:17] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 244:28] + node _T_1023 = andr(_T_1022) @[el2_lib.scala 244:36] + node _T_1024 = and(_T_1023, _T_849) @[el2_lib.scala 244:41] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 244:74] + node _T_1026 = bits(lsu_match_data_3, 25, 25) @[el2_lib.scala 244:86] + node _T_1027 = eq(_T_1025, _T_1026) @[el2_lib.scala 244:78] + node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[el2_lib.scala 244:23] + _T_846[25] <= _T_1028 @[el2_lib.scala 244:17] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 244:28] + node _T_1030 = andr(_T_1029) @[el2_lib.scala 244:36] + node _T_1031 = and(_T_1030, _T_849) @[el2_lib.scala 244:41] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 244:74] + node _T_1033 = bits(lsu_match_data_3, 26, 26) @[el2_lib.scala 244:86] + node _T_1034 = eq(_T_1032, _T_1033) @[el2_lib.scala 244:78] + node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[el2_lib.scala 244:23] + _T_846[26] <= _T_1035 @[el2_lib.scala 244:17] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 244:28] + node _T_1037 = andr(_T_1036) @[el2_lib.scala 244:36] + node _T_1038 = and(_T_1037, _T_849) @[el2_lib.scala 244:41] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 244:74] + node _T_1040 = bits(lsu_match_data_3, 27, 27) @[el2_lib.scala 244:86] + node _T_1041 = eq(_T_1039, _T_1040) @[el2_lib.scala 244:78] + node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[el2_lib.scala 244:23] + _T_846[27] <= _T_1042 @[el2_lib.scala 244:17] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 244:28] + node _T_1044 = andr(_T_1043) @[el2_lib.scala 244:36] + node _T_1045 = and(_T_1044, _T_849) @[el2_lib.scala 244:41] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 244:74] + node _T_1047 = bits(lsu_match_data_3, 28, 28) @[el2_lib.scala 244:86] + node _T_1048 = eq(_T_1046, _T_1047) @[el2_lib.scala 244:78] + node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[el2_lib.scala 244:23] + _T_846[28] <= _T_1049 @[el2_lib.scala 244:17] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 244:28] + node _T_1051 = andr(_T_1050) @[el2_lib.scala 244:36] + node _T_1052 = and(_T_1051, _T_849) @[el2_lib.scala 244:41] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 244:74] + node _T_1054 = bits(lsu_match_data_3, 29, 29) @[el2_lib.scala 244:86] + node _T_1055 = eq(_T_1053, _T_1054) @[el2_lib.scala 244:78] + node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[el2_lib.scala 244:23] + _T_846[29] <= _T_1056 @[el2_lib.scala 244:17] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 244:28] + node _T_1058 = andr(_T_1057) @[el2_lib.scala 244:36] + node _T_1059 = and(_T_1058, _T_849) @[el2_lib.scala 244:41] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 244:74] + node _T_1061 = bits(lsu_match_data_3, 30, 30) @[el2_lib.scala 244:86] + node _T_1062 = eq(_T_1060, _T_1061) @[el2_lib.scala 244:78] + node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[el2_lib.scala 244:23] + _T_846[30] <= _T_1063 @[el2_lib.scala 244:17] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 244:28] + node _T_1065 = andr(_T_1064) @[el2_lib.scala 244:36] + node _T_1066 = and(_T_1065, _T_849) @[el2_lib.scala 244:41] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 244:74] + node _T_1068 = bits(lsu_match_data_3, 31, 31) @[el2_lib.scala 244:86] + node _T_1069 = eq(_T_1067, _T_1068) @[el2_lib.scala 244:78] + node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[el2_lib.scala 244:23] + _T_846[31] <= _T_1070 @[el2_lib.scala 244:17] node _T_1071 = cat(_T_846[1], _T_846[0]) @[el2_lib.scala 245:14] node _T_1072 = cat(_T_846[3], _T_846[2]) @[el2_lib.scala 245:14] node _T_1073 = cat(_T_1072, _T_1071) @[el2_lib.scala 245:14] @@ -15213,7 +15213,7 @@ circuit el2_lsu : module el2_lsu : input clock : Clock input reset : AsyncReset - output io : {flip clk_override : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>, lsu_pmu_misaligned_m : UInt<1>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_trigger_match_m : UInt<4>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, lsu_axi_awvalid : UInt<1>, lsu_axi_awlock : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, lsu_axi_arlock : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rlast : UInt<1>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rid : UInt<3>, flip lsu_bus_clk_en : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_write : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, flip dma_mem_tag : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_wdata : UInt<64>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_ready : UInt<1>, flip scan_mode : UInt<1>, flip free_clk : Clock} + output io : {flip clk_override : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>, lsu_pmu_misaligned_m : UInt<1>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_trigger_match_m : UInt<4>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, lsu_axi_awvalid : UInt<1>, lsu_axi_awlock : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, lsu_axi_arlock : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rlast : UInt<1>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rid : UInt<3>, flip lsu_bus_clk_en : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_write : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, flip dma_mem_tag : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_wdata : UInt<64>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_ready : UInt<1>, flip scan_mode : UInt<1>, flip free_clk : Clock} wire dma_dccm_wdata : UInt<64> dma_dccm_wdata <= UInt<64>("h00") @@ -15585,28 +15585,28 @@ circuit el2_lsu : trigger.io.trigger_pkt_any[0].execute <= io.trigger_pkt_any[0].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[0].load <= io.trigger_pkt_any[0].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[0].store <= io.trigger_pkt_any[0].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[0].match_ <= io.trigger_pkt_any[0].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[0].match_pkt <= io.trigger_pkt_any[0].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[0].select <= io.trigger_pkt_any[0].select @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].tdata2 <= io.trigger_pkt_any[1].tdata2 @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].m <= io.trigger_pkt_any[1].m @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].execute <= io.trigger_pkt_any[1].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].load <= io.trigger_pkt_any[1].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].store <= io.trigger_pkt_any[1].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[1].match_ <= io.trigger_pkt_any[1].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[1].match_pkt <= io.trigger_pkt_any[1].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].select <= io.trigger_pkt_any[1].select @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].tdata2 <= io.trigger_pkt_any[2].tdata2 @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].m <= io.trigger_pkt_any[2].m @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].execute <= io.trigger_pkt_any[2].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].load <= io.trigger_pkt_any[2].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].store <= io.trigger_pkt_any[2].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[2].match_ <= io.trigger_pkt_any[2].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[2].match_pkt <= io.trigger_pkt_any[2].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].select <= io.trigger_pkt_any[2].select @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].tdata2 <= io.trigger_pkt_any[3].tdata2 @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].m <= io.trigger_pkt_any[3].m @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].execute <= io.trigger_pkt_any[3].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].load <= io.trigger_pkt_any[3].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].store <= io.trigger_pkt_any[3].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[3].match_ <= io.trigger_pkt_any[3].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[3].match_pkt <= io.trigger_pkt_any[3].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].select <= io.trigger_pkt_any[3].select @[el2_lsu.scala 376:50] trigger.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[el2_lsu.scala 377:50] trigger.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[el2_lsu.scala 377:50] diff --git a/el2_lsu.v b/el2_lsu.v index 5d5cc794..6512bdc2 100644 --- a/el2_lsu.v +++ b/el2_lsu.v @@ -235,8 +235,8 @@ module el2_lsu_lsc_ctl( output io_lsu_error_pkt_r_bits_single_ecc_error, output io_lsu_error_pkt_r_bits_inst_type, output io_lsu_error_pkt_r_bits_exc_type, - output io_lsu_error_pkt_r_bits_mscause, - output io_lsu_error_pkt_r_bits_addr, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, output [30:0] io_lsu_fir_addr, output [1:0] io_lsu_fir_error, output io_addr_in_dccm_d, @@ -414,14 +414,13 @@ module el2_lsu_lsc_ctl( wire _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 183:78] wire _T_91 = ~access_fault_m; // @[el2_lsu_lsc_ctl.scala 183:102] wire _T_92 = _T_90 & _T_91; // @[el2_lsu_lsc_ctl.scala 183:100] - wire [3:0] _T_95 = _T_92 ? 4'h1 : exc_mscause_m; // @[el2_lsu_lsc_ctl.scala 183:49] wire _T_99 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 185:166] reg _T_105_valid; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_inst_type; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 186:75] - reg _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75] - reg _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75] + reg [3:0] _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75] + reg [31:0] _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75] reg [1:0] _T_106; // @[el2_lsu_lsc_ctl.scala 187:75] wire dma_pkt_d_bits_load = ~io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 194:30] wire dma_pkt_d_bits_by = io_dma_mem_sz == 3'h0; // @[el2_lsu_lsc_ctl.scala 195:50] @@ -684,9 +683,9 @@ initial begin _RAND_8 = {1{`RANDOM}}; _T_105_bits_exc_type = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - _T_105_bits_mscause = _RAND_9[0:0]; + _T_105_bits_mscause = _RAND_9[3:0]; _RAND_10 = {1{`RANDOM}}; - _T_105_bits_addr = _RAND_10[0:0]; + _T_105_bits_addr = _RAND_10[31:0]; _RAND_11 = {1{`RANDOM}}; _T_106 = _RAND_11[1:0]; _RAND_12 = {1{`RANDOM}}; @@ -782,10 +781,10 @@ initial begin _T_105_bits_exc_type = 1'h0; end if (reset) begin - _T_105_bits_mscause = 1'h0; + _T_105_bits_mscause = 4'h0; end if (reset) begin - _T_105_bits_addr = 1'h0; + _T_105_bits_addr = 32'h0; end if (reset) begin _T_106 = 2'h0; @@ -957,16 +956,18 @@ end // initial end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_105_bits_mscause <= 1'h0; + _T_105_bits_mscause <= 4'h0; + end else if (_T_92) begin + _T_105_bits_mscause <= 4'h1; end else begin - _T_105_bits_mscause <= _T_95[0]; + _T_105_bits_mscause <= exc_mscause_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_105_bits_addr <= 1'h0; + _T_105_bits_addr <= 32'h0; end else begin - _T_105_bits_addr <= io_lsu_addr_m[0]; + _T_105_bits_addr <= io_lsu_addr_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin @@ -4179,22 +4180,22 @@ end // initial endmodule module el2_lsu_trigger( input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_store, input io_trigger_pkt_any_0_load, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_store, input io_trigger_pkt_any_1_load, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_store, input io_trigger_pkt_any_2_load, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_store, input io_trigger_pkt_any_3_load, input [31:0] io_trigger_pkt_any_3_tdata2, @@ -4243,133 +4244,133 @@ module el2_lsu_trigger( wire _T_46 = _T_40 & _T_45; // @[el2_lsu_trigger.scala 18:94] wire _T_49 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] wire _T_50 = ~_T_49; // @[el2_lib.scala 241:39] - wire _T_51 = io_trigger_pkt_any_0_match_ & _T_50; // @[el2_lib.scala 241:37] + wire _T_51 = io_trigger_pkt_any_0_match_pkt & _T_50; // @[el2_lib.scala 241:37] wire _T_54 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[el2_lib.scala 242:52] wire _T_55 = _T_51 | _T_54; // @[el2_lib.scala 242:41] - wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:38] - wire _T_58 = _T_57 & _T_51; // @[el2_lib.scala 244:43] - wire _T_61 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[el2_lib.scala 244:80] - wire _T_62 = _T_58 | _T_61; // @[el2_lib.scala 244:25] - wire _T_64 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:38] - wire _T_65 = _T_64 & _T_51; // @[el2_lib.scala 244:43] - wire _T_68 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[el2_lib.scala 244:80] - wire _T_69 = _T_65 | _T_68; // @[el2_lib.scala 244:25] - wire _T_71 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:38] - wire _T_72 = _T_71 & _T_51; // @[el2_lib.scala 244:43] - wire _T_75 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[el2_lib.scala 244:80] - wire _T_76 = _T_72 | _T_75; // @[el2_lib.scala 244:25] - wire _T_78 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:38] - wire _T_79 = _T_78 & _T_51; // @[el2_lib.scala 244:43] - wire _T_82 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[el2_lib.scala 244:80] - wire _T_83 = _T_79 | _T_82; // @[el2_lib.scala 244:25] - wire _T_85 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:38] - wire _T_86 = _T_85 & _T_51; // @[el2_lib.scala 244:43] - wire _T_89 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[el2_lib.scala 244:80] - wire _T_90 = _T_86 | _T_89; // @[el2_lib.scala 244:25] - wire _T_92 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:38] - wire _T_93 = _T_92 & _T_51; // @[el2_lib.scala 244:43] - wire _T_96 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[el2_lib.scala 244:80] - wire _T_97 = _T_93 | _T_96; // @[el2_lib.scala 244:25] - wire _T_99 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:38] - wire _T_100 = _T_99 & _T_51; // @[el2_lib.scala 244:43] - wire _T_103 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[el2_lib.scala 244:80] - wire _T_104 = _T_100 | _T_103; // @[el2_lib.scala 244:25] - wire _T_106 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:38] - wire _T_107 = _T_106 & _T_51; // @[el2_lib.scala 244:43] - wire _T_110 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[el2_lib.scala 244:80] - wire _T_111 = _T_107 | _T_110; // @[el2_lib.scala 244:25] - wire _T_113 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:38] - wire _T_114 = _T_113 & _T_51; // @[el2_lib.scala 244:43] - wire _T_117 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[el2_lib.scala 244:80] - wire _T_118 = _T_114 | _T_117; // @[el2_lib.scala 244:25] - wire _T_120 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:38] - wire _T_121 = _T_120 & _T_51; // @[el2_lib.scala 244:43] - wire _T_124 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[el2_lib.scala 244:80] - wire _T_125 = _T_121 | _T_124; // @[el2_lib.scala 244:25] - wire _T_127 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:38] - wire _T_128 = _T_127 & _T_51; // @[el2_lib.scala 244:43] - wire _T_131 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[el2_lib.scala 244:80] - wire _T_132 = _T_128 | _T_131; // @[el2_lib.scala 244:25] - wire _T_134 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:38] - wire _T_135 = _T_134 & _T_51; // @[el2_lib.scala 244:43] - wire _T_138 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[el2_lib.scala 244:80] - wire _T_139 = _T_135 | _T_138; // @[el2_lib.scala 244:25] - wire _T_141 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:38] - wire _T_142 = _T_141 & _T_51; // @[el2_lib.scala 244:43] - wire _T_145 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[el2_lib.scala 244:80] - wire _T_146 = _T_142 | _T_145; // @[el2_lib.scala 244:25] - wire _T_148 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:38] - wire _T_149 = _T_148 & _T_51; // @[el2_lib.scala 244:43] - wire _T_152 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[el2_lib.scala 244:80] - wire _T_153 = _T_149 | _T_152; // @[el2_lib.scala 244:25] - wire _T_155 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:38] - wire _T_156 = _T_155 & _T_51; // @[el2_lib.scala 244:43] - wire _T_159 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[el2_lib.scala 244:80] - wire _T_160 = _T_156 | _T_159; // @[el2_lib.scala 244:25] - wire _T_162 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:38] - wire _T_163 = _T_162 & _T_51; // @[el2_lib.scala 244:43] - wire _T_166 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[el2_lib.scala 244:80] - wire _T_167 = _T_163 | _T_166; // @[el2_lib.scala 244:25] - wire _T_169 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:38] - wire _T_170 = _T_169 & _T_51; // @[el2_lib.scala 244:43] - wire _T_173 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[el2_lib.scala 244:80] - wire _T_174 = _T_170 | _T_173; // @[el2_lib.scala 244:25] - wire _T_176 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:38] - wire _T_177 = _T_176 & _T_51; // @[el2_lib.scala 244:43] - wire _T_180 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[el2_lib.scala 244:80] - wire _T_181 = _T_177 | _T_180; // @[el2_lib.scala 244:25] - wire _T_183 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:38] - wire _T_184 = _T_183 & _T_51; // @[el2_lib.scala 244:43] - wire _T_187 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[el2_lib.scala 244:80] - wire _T_188 = _T_184 | _T_187; // @[el2_lib.scala 244:25] - wire _T_190 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:38] - wire _T_191 = _T_190 & _T_51; // @[el2_lib.scala 244:43] - wire _T_194 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[el2_lib.scala 244:80] - wire _T_195 = _T_191 | _T_194; // @[el2_lib.scala 244:25] - wire _T_197 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:38] - wire _T_198 = _T_197 & _T_51; // @[el2_lib.scala 244:43] - wire _T_201 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[el2_lib.scala 244:80] - wire _T_202 = _T_198 | _T_201; // @[el2_lib.scala 244:25] - wire _T_204 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:38] - wire _T_205 = _T_204 & _T_51; // @[el2_lib.scala 244:43] - wire _T_208 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[el2_lib.scala 244:80] - wire _T_209 = _T_205 | _T_208; // @[el2_lib.scala 244:25] - wire _T_211 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:38] - wire _T_212 = _T_211 & _T_51; // @[el2_lib.scala 244:43] - wire _T_215 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[el2_lib.scala 244:80] - wire _T_216 = _T_212 | _T_215; // @[el2_lib.scala 244:25] - wire _T_218 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:38] - wire _T_219 = _T_218 & _T_51; // @[el2_lib.scala 244:43] - wire _T_222 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[el2_lib.scala 244:80] - wire _T_223 = _T_219 | _T_222; // @[el2_lib.scala 244:25] - wire _T_225 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:38] - wire _T_226 = _T_225 & _T_51; // @[el2_lib.scala 244:43] - wire _T_229 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[el2_lib.scala 244:80] - wire _T_230 = _T_226 | _T_229; // @[el2_lib.scala 244:25] - wire _T_232 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:38] - wire _T_233 = _T_232 & _T_51; // @[el2_lib.scala 244:43] - wire _T_236 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[el2_lib.scala 244:80] - wire _T_237 = _T_233 | _T_236; // @[el2_lib.scala 244:25] - wire _T_239 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:38] - wire _T_240 = _T_239 & _T_51; // @[el2_lib.scala 244:43] - wire _T_243 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[el2_lib.scala 244:80] - wire _T_244 = _T_240 | _T_243; // @[el2_lib.scala 244:25] - wire _T_246 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:38] - wire _T_247 = _T_246 & _T_51; // @[el2_lib.scala 244:43] - wire _T_250 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[el2_lib.scala 244:80] - wire _T_251 = _T_247 | _T_250; // @[el2_lib.scala 244:25] - wire _T_253 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:38] - wire _T_254 = _T_253 & _T_51; // @[el2_lib.scala 244:43] - wire _T_257 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[el2_lib.scala 244:80] - wire _T_258 = _T_254 | _T_257; // @[el2_lib.scala 244:25] - wire _T_260 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:38] - wire _T_261 = _T_260 & _T_51; // @[el2_lib.scala 244:43] - wire _T_264 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[el2_lib.scala 244:80] - wire _T_265 = _T_261 | _T_264; // @[el2_lib.scala 244:25] - wire _T_267 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:38] - wire _T_268 = _T_267 & _T_51; // @[el2_lib.scala 244:43] - wire _T_271 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[el2_lib.scala 244:80] - wire _T_272 = _T_268 | _T_271; // @[el2_lib.scala 244:25] + wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_58 = _T_57 & _T_51; // @[el2_lib.scala 244:41] + wire _T_61 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[el2_lib.scala 244:78] + wire _T_62 = _T_58 | _T_61; // @[el2_lib.scala 244:23] + wire _T_64 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_65 = _T_64 & _T_51; // @[el2_lib.scala 244:41] + wire _T_68 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[el2_lib.scala 244:78] + wire _T_69 = _T_65 | _T_68; // @[el2_lib.scala 244:23] + wire _T_71 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_72 = _T_71 & _T_51; // @[el2_lib.scala 244:41] + wire _T_75 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[el2_lib.scala 244:78] + wire _T_76 = _T_72 | _T_75; // @[el2_lib.scala 244:23] + wire _T_78 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_79 = _T_78 & _T_51; // @[el2_lib.scala 244:41] + wire _T_82 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[el2_lib.scala 244:78] + wire _T_83 = _T_79 | _T_82; // @[el2_lib.scala 244:23] + wire _T_85 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_86 = _T_85 & _T_51; // @[el2_lib.scala 244:41] + wire _T_89 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[el2_lib.scala 244:78] + wire _T_90 = _T_86 | _T_89; // @[el2_lib.scala 244:23] + wire _T_92 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_93 = _T_92 & _T_51; // @[el2_lib.scala 244:41] + wire _T_96 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[el2_lib.scala 244:78] + wire _T_97 = _T_93 | _T_96; // @[el2_lib.scala 244:23] + wire _T_99 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_100 = _T_99 & _T_51; // @[el2_lib.scala 244:41] + wire _T_103 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[el2_lib.scala 244:78] + wire _T_104 = _T_100 | _T_103; // @[el2_lib.scala 244:23] + wire _T_106 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_107 = _T_106 & _T_51; // @[el2_lib.scala 244:41] + wire _T_110 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[el2_lib.scala 244:78] + wire _T_111 = _T_107 | _T_110; // @[el2_lib.scala 244:23] + wire _T_113 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_114 = _T_113 & _T_51; // @[el2_lib.scala 244:41] + wire _T_117 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[el2_lib.scala 244:78] + wire _T_118 = _T_114 | _T_117; // @[el2_lib.scala 244:23] + wire _T_120 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_121 = _T_120 & _T_51; // @[el2_lib.scala 244:41] + wire _T_124 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[el2_lib.scala 244:78] + wire _T_125 = _T_121 | _T_124; // @[el2_lib.scala 244:23] + wire _T_127 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_128 = _T_127 & _T_51; // @[el2_lib.scala 244:41] + wire _T_131 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[el2_lib.scala 244:78] + wire _T_132 = _T_128 | _T_131; // @[el2_lib.scala 244:23] + wire _T_134 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_135 = _T_134 & _T_51; // @[el2_lib.scala 244:41] + wire _T_138 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[el2_lib.scala 244:78] + wire _T_139 = _T_135 | _T_138; // @[el2_lib.scala 244:23] + wire _T_141 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_142 = _T_141 & _T_51; // @[el2_lib.scala 244:41] + wire _T_145 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[el2_lib.scala 244:78] + wire _T_146 = _T_142 | _T_145; // @[el2_lib.scala 244:23] + wire _T_148 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_149 = _T_148 & _T_51; // @[el2_lib.scala 244:41] + wire _T_152 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[el2_lib.scala 244:78] + wire _T_153 = _T_149 | _T_152; // @[el2_lib.scala 244:23] + wire _T_155 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_156 = _T_155 & _T_51; // @[el2_lib.scala 244:41] + wire _T_159 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[el2_lib.scala 244:78] + wire _T_160 = _T_156 | _T_159; // @[el2_lib.scala 244:23] + wire _T_162 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_163 = _T_162 & _T_51; // @[el2_lib.scala 244:41] + wire _T_166 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[el2_lib.scala 244:78] + wire _T_167 = _T_163 | _T_166; // @[el2_lib.scala 244:23] + wire _T_169 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_170 = _T_169 & _T_51; // @[el2_lib.scala 244:41] + wire _T_173 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[el2_lib.scala 244:78] + wire _T_174 = _T_170 | _T_173; // @[el2_lib.scala 244:23] + wire _T_176 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_177 = _T_176 & _T_51; // @[el2_lib.scala 244:41] + wire _T_180 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[el2_lib.scala 244:78] + wire _T_181 = _T_177 | _T_180; // @[el2_lib.scala 244:23] + wire _T_183 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_184 = _T_183 & _T_51; // @[el2_lib.scala 244:41] + wire _T_187 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[el2_lib.scala 244:78] + wire _T_188 = _T_184 | _T_187; // @[el2_lib.scala 244:23] + wire _T_190 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_191 = _T_190 & _T_51; // @[el2_lib.scala 244:41] + wire _T_194 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[el2_lib.scala 244:78] + wire _T_195 = _T_191 | _T_194; // @[el2_lib.scala 244:23] + wire _T_197 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_198 = _T_197 & _T_51; // @[el2_lib.scala 244:41] + wire _T_201 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[el2_lib.scala 244:78] + wire _T_202 = _T_198 | _T_201; // @[el2_lib.scala 244:23] + wire _T_204 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_205 = _T_204 & _T_51; // @[el2_lib.scala 244:41] + wire _T_208 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[el2_lib.scala 244:78] + wire _T_209 = _T_205 | _T_208; // @[el2_lib.scala 244:23] + wire _T_211 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_212 = _T_211 & _T_51; // @[el2_lib.scala 244:41] + wire _T_215 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[el2_lib.scala 244:78] + wire _T_216 = _T_212 | _T_215; // @[el2_lib.scala 244:23] + wire _T_218 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_219 = _T_218 & _T_51; // @[el2_lib.scala 244:41] + wire _T_222 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[el2_lib.scala 244:78] + wire _T_223 = _T_219 | _T_222; // @[el2_lib.scala 244:23] + wire _T_225 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_226 = _T_225 & _T_51; // @[el2_lib.scala 244:41] + wire _T_229 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[el2_lib.scala 244:78] + wire _T_230 = _T_226 | _T_229; // @[el2_lib.scala 244:23] + wire _T_232 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_233 = _T_232 & _T_51; // @[el2_lib.scala 244:41] + wire _T_236 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[el2_lib.scala 244:78] + wire _T_237 = _T_233 | _T_236; // @[el2_lib.scala 244:23] + wire _T_239 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_240 = _T_239 & _T_51; // @[el2_lib.scala 244:41] + wire _T_243 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[el2_lib.scala 244:78] + wire _T_244 = _T_240 | _T_243; // @[el2_lib.scala 244:23] + wire _T_246 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_247 = _T_246 & _T_51; // @[el2_lib.scala 244:41] + wire _T_250 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[el2_lib.scala 244:78] + wire _T_251 = _T_247 | _T_250; // @[el2_lib.scala 244:23] + wire _T_253 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_254 = _T_253 & _T_51; // @[el2_lib.scala 244:41] + wire _T_257 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[el2_lib.scala 244:78] + wire _T_258 = _T_254 | _T_257; // @[el2_lib.scala 244:23] + wire _T_260 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_261 = _T_260 & _T_51; // @[el2_lib.scala 244:41] + wire _T_264 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[el2_lib.scala 244:78] + wire _T_265 = _T_261 | _T_264; // @[el2_lib.scala 244:23] + wire _T_267 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_268 = _T_267 & _T_51; // @[el2_lib.scala 244:41] + wire _T_271 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[el2_lib.scala 244:78] + wire _T_272 = _T_268 | _T_271; // @[el2_lib.scala 244:23] wire [7:0] _T_279 = {_T_104,_T_97,_T_90,_T_83,_T_76,_T_69,_T_62,_T_55}; // @[el2_lib.scala 245:14] wire [15:0] _T_287 = {_T_160,_T_153,_T_146,_T_139,_T_132,_T_125,_T_118,_T_111,_T_279}; // @[el2_lib.scala 245:14] wire [7:0] _T_294 = {_T_216,_T_209,_T_202,_T_195,_T_188,_T_181,_T_174,_T_167}; // @[el2_lib.scala 245:14] @@ -4383,133 +4384,133 @@ module el2_lsu_trigger( wire _T_312 = _T_40 & _T_311; // @[el2_lsu_trigger.scala 18:94] wire _T_315 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] wire _T_316 = ~_T_315; // @[el2_lib.scala 241:39] - wire _T_317 = io_trigger_pkt_any_1_match_ & _T_316; // @[el2_lib.scala 241:37] + wire _T_317 = io_trigger_pkt_any_1_match_pkt & _T_316; // @[el2_lib.scala 241:37] wire _T_320 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[el2_lib.scala 242:52] wire _T_321 = _T_317 | _T_320; // @[el2_lib.scala 242:41] - wire _T_323 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:38] - wire _T_324 = _T_323 & _T_317; // @[el2_lib.scala 244:43] - wire _T_327 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[el2_lib.scala 244:80] - wire _T_328 = _T_324 | _T_327; // @[el2_lib.scala 244:25] - wire _T_330 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:38] - wire _T_331 = _T_330 & _T_317; // @[el2_lib.scala 244:43] - wire _T_334 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[el2_lib.scala 244:80] - wire _T_335 = _T_331 | _T_334; // @[el2_lib.scala 244:25] - wire _T_337 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:38] - wire _T_338 = _T_337 & _T_317; // @[el2_lib.scala 244:43] - wire _T_341 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[el2_lib.scala 244:80] - wire _T_342 = _T_338 | _T_341; // @[el2_lib.scala 244:25] - wire _T_344 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:38] - wire _T_345 = _T_344 & _T_317; // @[el2_lib.scala 244:43] - wire _T_348 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[el2_lib.scala 244:80] - wire _T_349 = _T_345 | _T_348; // @[el2_lib.scala 244:25] - wire _T_351 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:38] - wire _T_352 = _T_351 & _T_317; // @[el2_lib.scala 244:43] - wire _T_355 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[el2_lib.scala 244:80] - wire _T_356 = _T_352 | _T_355; // @[el2_lib.scala 244:25] - wire _T_358 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:38] - wire _T_359 = _T_358 & _T_317; // @[el2_lib.scala 244:43] - wire _T_362 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[el2_lib.scala 244:80] - wire _T_363 = _T_359 | _T_362; // @[el2_lib.scala 244:25] - wire _T_365 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:38] - wire _T_366 = _T_365 & _T_317; // @[el2_lib.scala 244:43] - wire _T_369 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[el2_lib.scala 244:80] - wire _T_370 = _T_366 | _T_369; // @[el2_lib.scala 244:25] - wire _T_372 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:38] - wire _T_373 = _T_372 & _T_317; // @[el2_lib.scala 244:43] - wire _T_376 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[el2_lib.scala 244:80] - wire _T_377 = _T_373 | _T_376; // @[el2_lib.scala 244:25] - wire _T_379 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:38] - wire _T_380 = _T_379 & _T_317; // @[el2_lib.scala 244:43] - wire _T_383 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[el2_lib.scala 244:80] - wire _T_384 = _T_380 | _T_383; // @[el2_lib.scala 244:25] - wire _T_386 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:38] - wire _T_387 = _T_386 & _T_317; // @[el2_lib.scala 244:43] - wire _T_390 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[el2_lib.scala 244:80] - wire _T_391 = _T_387 | _T_390; // @[el2_lib.scala 244:25] - wire _T_393 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:38] - wire _T_394 = _T_393 & _T_317; // @[el2_lib.scala 244:43] - wire _T_397 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[el2_lib.scala 244:80] - wire _T_398 = _T_394 | _T_397; // @[el2_lib.scala 244:25] - wire _T_400 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:38] - wire _T_401 = _T_400 & _T_317; // @[el2_lib.scala 244:43] - wire _T_404 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[el2_lib.scala 244:80] - wire _T_405 = _T_401 | _T_404; // @[el2_lib.scala 244:25] - wire _T_407 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:38] - wire _T_408 = _T_407 & _T_317; // @[el2_lib.scala 244:43] - wire _T_411 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[el2_lib.scala 244:80] - wire _T_412 = _T_408 | _T_411; // @[el2_lib.scala 244:25] - wire _T_414 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:38] - wire _T_415 = _T_414 & _T_317; // @[el2_lib.scala 244:43] - wire _T_418 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[el2_lib.scala 244:80] - wire _T_419 = _T_415 | _T_418; // @[el2_lib.scala 244:25] - wire _T_421 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:38] - wire _T_422 = _T_421 & _T_317; // @[el2_lib.scala 244:43] - wire _T_425 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[el2_lib.scala 244:80] - wire _T_426 = _T_422 | _T_425; // @[el2_lib.scala 244:25] - wire _T_428 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:38] - wire _T_429 = _T_428 & _T_317; // @[el2_lib.scala 244:43] - wire _T_432 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[el2_lib.scala 244:80] - wire _T_433 = _T_429 | _T_432; // @[el2_lib.scala 244:25] - wire _T_435 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:38] - wire _T_436 = _T_435 & _T_317; // @[el2_lib.scala 244:43] - wire _T_439 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[el2_lib.scala 244:80] - wire _T_440 = _T_436 | _T_439; // @[el2_lib.scala 244:25] - wire _T_442 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:38] - wire _T_443 = _T_442 & _T_317; // @[el2_lib.scala 244:43] - wire _T_446 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[el2_lib.scala 244:80] - wire _T_447 = _T_443 | _T_446; // @[el2_lib.scala 244:25] - wire _T_449 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:38] - wire _T_450 = _T_449 & _T_317; // @[el2_lib.scala 244:43] - wire _T_453 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[el2_lib.scala 244:80] - wire _T_454 = _T_450 | _T_453; // @[el2_lib.scala 244:25] - wire _T_456 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:38] - wire _T_457 = _T_456 & _T_317; // @[el2_lib.scala 244:43] - wire _T_460 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[el2_lib.scala 244:80] - wire _T_461 = _T_457 | _T_460; // @[el2_lib.scala 244:25] - wire _T_463 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:38] - wire _T_464 = _T_463 & _T_317; // @[el2_lib.scala 244:43] - wire _T_467 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[el2_lib.scala 244:80] - wire _T_468 = _T_464 | _T_467; // @[el2_lib.scala 244:25] - wire _T_470 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:38] - wire _T_471 = _T_470 & _T_317; // @[el2_lib.scala 244:43] - wire _T_474 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[el2_lib.scala 244:80] - wire _T_475 = _T_471 | _T_474; // @[el2_lib.scala 244:25] - wire _T_477 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:38] - wire _T_478 = _T_477 & _T_317; // @[el2_lib.scala 244:43] - wire _T_481 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[el2_lib.scala 244:80] - wire _T_482 = _T_478 | _T_481; // @[el2_lib.scala 244:25] - wire _T_484 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:38] - wire _T_485 = _T_484 & _T_317; // @[el2_lib.scala 244:43] - wire _T_488 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[el2_lib.scala 244:80] - wire _T_489 = _T_485 | _T_488; // @[el2_lib.scala 244:25] - wire _T_491 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:38] - wire _T_492 = _T_491 & _T_317; // @[el2_lib.scala 244:43] - wire _T_495 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[el2_lib.scala 244:80] - wire _T_496 = _T_492 | _T_495; // @[el2_lib.scala 244:25] - wire _T_498 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:38] - wire _T_499 = _T_498 & _T_317; // @[el2_lib.scala 244:43] - wire _T_502 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[el2_lib.scala 244:80] - wire _T_503 = _T_499 | _T_502; // @[el2_lib.scala 244:25] - wire _T_505 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:38] - wire _T_506 = _T_505 & _T_317; // @[el2_lib.scala 244:43] - wire _T_509 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[el2_lib.scala 244:80] - wire _T_510 = _T_506 | _T_509; // @[el2_lib.scala 244:25] - wire _T_512 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:38] - wire _T_513 = _T_512 & _T_317; // @[el2_lib.scala 244:43] - wire _T_516 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[el2_lib.scala 244:80] - wire _T_517 = _T_513 | _T_516; // @[el2_lib.scala 244:25] - wire _T_519 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:38] - wire _T_520 = _T_519 & _T_317; // @[el2_lib.scala 244:43] - wire _T_523 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[el2_lib.scala 244:80] - wire _T_524 = _T_520 | _T_523; // @[el2_lib.scala 244:25] - wire _T_526 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:38] - wire _T_527 = _T_526 & _T_317; // @[el2_lib.scala 244:43] - wire _T_530 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[el2_lib.scala 244:80] - wire _T_531 = _T_527 | _T_530; // @[el2_lib.scala 244:25] - wire _T_533 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:38] - wire _T_534 = _T_533 & _T_317; // @[el2_lib.scala 244:43] - wire _T_537 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[el2_lib.scala 244:80] - wire _T_538 = _T_534 | _T_537; // @[el2_lib.scala 244:25] + wire _T_323 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_324 = _T_323 & _T_317; // @[el2_lib.scala 244:41] + wire _T_327 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[el2_lib.scala 244:78] + wire _T_328 = _T_324 | _T_327; // @[el2_lib.scala 244:23] + wire _T_330 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_331 = _T_330 & _T_317; // @[el2_lib.scala 244:41] + wire _T_334 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[el2_lib.scala 244:78] + wire _T_335 = _T_331 | _T_334; // @[el2_lib.scala 244:23] + wire _T_337 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_338 = _T_337 & _T_317; // @[el2_lib.scala 244:41] + wire _T_341 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[el2_lib.scala 244:78] + wire _T_342 = _T_338 | _T_341; // @[el2_lib.scala 244:23] + wire _T_344 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_345 = _T_344 & _T_317; // @[el2_lib.scala 244:41] + wire _T_348 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[el2_lib.scala 244:78] + wire _T_349 = _T_345 | _T_348; // @[el2_lib.scala 244:23] + wire _T_351 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_352 = _T_351 & _T_317; // @[el2_lib.scala 244:41] + wire _T_355 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[el2_lib.scala 244:78] + wire _T_356 = _T_352 | _T_355; // @[el2_lib.scala 244:23] + wire _T_358 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_359 = _T_358 & _T_317; // @[el2_lib.scala 244:41] + wire _T_362 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[el2_lib.scala 244:78] + wire _T_363 = _T_359 | _T_362; // @[el2_lib.scala 244:23] + wire _T_365 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_366 = _T_365 & _T_317; // @[el2_lib.scala 244:41] + wire _T_369 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[el2_lib.scala 244:78] + wire _T_370 = _T_366 | _T_369; // @[el2_lib.scala 244:23] + wire _T_372 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_373 = _T_372 & _T_317; // @[el2_lib.scala 244:41] + wire _T_376 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[el2_lib.scala 244:78] + wire _T_377 = _T_373 | _T_376; // @[el2_lib.scala 244:23] + wire _T_379 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_380 = _T_379 & _T_317; // @[el2_lib.scala 244:41] + wire _T_383 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[el2_lib.scala 244:78] + wire _T_384 = _T_380 | _T_383; // @[el2_lib.scala 244:23] + wire _T_386 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_387 = _T_386 & _T_317; // @[el2_lib.scala 244:41] + wire _T_390 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[el2_lib.scala 244:78] + wire _T_391 = _T_387 | _T_390; // @[el2_lib.scala 244:23] + wire _T_393 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_394 = _T_393 & _T_317; // @[el2_lib.scala 244:41] + wire _T_397 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[el2_lib.scala 244:78] + wire _T_398 = _T_394 | _T_397; // @[el2_lib.scala 244:23] + wire _T_400 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_401 = _T_400 & _T_317; // @[el2_lib.scala 244:41] + wire _T_404 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[el2_lib.scala 244:78] + wire _T_405 = _T_401 | _T_404; // @[el2_lib.scala 244:23] + wire _T_407 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_408 = _T_407 & _T_317; // @[el2_lib.scala 244:41] + wire _T_411 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[el2_lib.scala 244:78] + wire _T_412 = _T_408 | _T_411; // @[el2_lib.scala 244:23] + wire _T_414 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_415 = _T_414 & _T_317; // @[el2_lib.scala 244:41] + wire _T_418 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[el2_lib.scala 244:78] + wire _T_419 = _T_415 | _T_418; // @[el2_lib.scala 244:23] + wire _T_421 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_422 = _T_421 & _T_317; // @[el2_lib.scala 244:41] + wire _T_425 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[el2_lib.scala 244:78] + wire _T_426 = _T_422 | _T_425; // @[el2_lib.scala 244:23] + wire _T_428 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_429 = _T_428 & _T_317; // @[el2_lib.scala 244:41] + wire _T_432 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[el2_lib.scala 244:78] + wire _T_433 = _T_429 | _T_432; // @[el2_lib.scala 244:23] + wire _T_435 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_436 = _T_435 & _T_317; // @[el2_lib.scala 244:41] + wire _T_439 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[el2_lib.scala 244:78] + wire _T_440 = _T_436 | _T_439; // @[el2_lib.scala 244:23] + wire _T_442 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_443 = _T_442 & _T_317; // @[el2_lib.scala 244:41] + wire _T_446 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[el2_lib.scala 244:78] + wire _T_447 = _T_443 | _T_446; // @[el2_lib.scala 244:23] + wire _T_449 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_450 = _T_449 & _T_317; // @[el2_lib.scala 244:41] + wire _T_453 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[el2_lib.scala 244:78] + wire _T_454 = _T_450 | _T_453; // @[el2_lib.scala 244:23] + wire _T_456 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_457 = _T_456 & _T_317; // @[el2_lib.scala 244:41] + wire _T_460 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[el2_lib.scala 244:78] + wire _T_461 = _T_457 | _T_460; // @[el2_lib.scala 244:23] + wire _T_463 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_464 = _T_463 & _T_317; // @[el2_lib.scala 244:41] + wire _T_467 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[el2_lib.scala 244:78] + wire _T_468 = _T_464 | _T_467; // @[el2_lib.scala 244:23] + wire _T_470 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_471 = _T_470 & _T_317; // @[el2_lib.scala 244:41] + wire _T_474 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[el2_lib.scala 244:78] + wire _T_475 = _T_471 | _T_474; // @[el2_lib.scala 244:23] + wire _T_477 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_478 = _T_477 & _T_317; // @[el2_lib.scala 244:41] + wire _T_481 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[el2_lib.scala 244:78] + wire _T_482 = _T_478 | _T_481; // @[el2_lib.scala 244:23] + wire _T_484 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_485 = _T_484 & _T_317; // @[el2_lib.scala 244:41] + wire _T_488 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[el2_lib.scala 244:78] + wire _T_489 = _T_485 | _T_488; // @[el2_lib.scala 244:23] + wire _T_491 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_492 = _T_491 & _T_317; // @[el2_lib.scala 244:41] + wire _T_495 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[el2_lib.scala 244:78] + wire _T_496 = _T_492 | _T_495; // @[el2_lib.scala 244:23] + wire _T_498 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_499 = _T_498 & _T_317; // @[el2_lib.scala 244:41] + wire _T_502 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[el2_lib.scala 244:78] + wire _T_503 = _T_499 | _T_502; // @[el2_lib.scala 244:23] + wire _T_505 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_506 = _T_505 & _T_317; // @[el2_lib.scala 244:41] + wire _T_509 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[el2_lib.scala 244:78] + wire _T_510 = _T_506 | _T_509; // @[el2_lib.scala 244:23] + wire _T_512 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_513 = _T_512 & _T_317; // @[el2_lib.scala 244:41] + wire _T_516 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[el2_lib.scala 244:78] + wire _T_517 = _T_513 | _T_516; // @[el2_lib.scala 244:23] + wire _T_519 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_520 = _T_519 & _T_317; // @[el2_lib.scala 244:41] + wire _T_523 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[el2_lib.scala 244:78] + wire _T_524 = _T_520 | _T_523; // @[el2_lib.scala 244:23] + wire _T_526 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_527 = _T_526 & _T_317; // @[el2_lib.scala 244:41] + wire _T_530 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[el2_lib.scala 244:78] + wire _T_531 = _T_527 | _T_530; // @[el2_lib.scala 244:23] + wire _T_533 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_534 = _T_533 & _T_317; // @[el2_lib.scala 244:41] + wire _T_537 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[el2_lib.scala 244:78] + wire _T_538 = _T_534 | _T_537; // @[el2_lib.scala 244:23] wire [7:0] _T_545 = {_T_370,_T_363,_T_356,_T_349,_T_342,_T_335,_T_328,_T_321}; // @[el2_lib.scala 245:14] wire [15:0] _T_553 = {_T_426,_T_419,_T_412,_T_405,_T_398,_T_391,_T_384,_T_377,_T_545}; // @[el2_lib.scala 245:14] wire [7:0] _T_560 = {_T_482,_T_475,_T_468,_T_461,_T_454,_T_447,_T_440,_T_433}; // @[el2_lib.scala 245:14] @@ -4523,133 +4524,133 @@ module el2_lsu_trigger( wire _T_578 = _T_40 & _T_577; // @[el2_lsu_trigger.scala 18:94] wire _T_581 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] wire _T_582 = ~_T_581; // @[el2_lib.scala 241:39] - wire _T_583 = io_trigger_pkt_any_2_match_ & _T_582; // @[el2_lib.scala 241:37] + wire _T_583 = io_trigger_pkt_any_2_match_pkt & _T_582; // @[el2_lib.scala 241:37] wire _T_586 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[el2_lib.scala 242:52] wire _T_587 = _T_583 | _T_586; // @[el2_lib.scala 242:41] - wire _T_589 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:38] - wire _T_590 = _T_589 & _T_583; // @[el2_lib.scala 244:43] - wire _T_593 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[el2_lib.scala 244:80] - wire _T_594 = _T_590 | _T_593; // @[el2_lib.scala 244:25] - wire _T_596 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:38] - wire _T_597 = _T_596 & _T_583; // @[el2_lib.scala 244:43] - wire _T_600 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[el2_lib.scala 244:80] - wire _T_601 = _T_597 | _T_600; // @[el2_lib.scala 244:25] - wire _T_603 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:38] - wire _T_604 = _T_603 & _T_583; // @[el2_lib.scala 244:43] - wire _T_607 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[el2_lib.scala 244:80] - wire _T_608 = _T_604 | _T_607; // @[el2_lib.scala 244:25] - wire _T_610 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:38] - wire _T_611 = _T_610 & _T_583; // @[el2_lib.scala 244:43] - wire _T_614 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[el2_lib.scala 244:80] - wire _T_615 = _T_611 | _T_614; // @[el2_lib.scala 244:25] - wire _T_617 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:38] - wire _T_618 = _T_617 & _T_583; // @[el2_lib.scala 244:43] - wire _T_621 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[el2_lib.scala 244:80] - wire _T_622 = _T_618 | _T_621; // @[el2_lib.scala 244:25] - wire _T_624 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:38] - wire _T_625 = _T_624 & _T_583; // @[el2_lib.scala 244:43] - wire _T_628 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[el2_lib.scala 244:80] - wire _T_629 = _T_625 | _T_628; // @[el2_lib.scala 244:25] - wire _T_631 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:38] - wire _T_632 = _T_631 & _T_583; // @[el2_lib.scala 244:43] - wire _T_635 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[el2_lib.scala 244:80] - wire _T_636 = _T_632 | _T_635; // @[el2_lib.scala 244:25] - wire _T_638 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:38] - wire _T_639 = _T_638 & _T_583; // @[el2_lib.scala 244:43] - wire _T_642 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[el2_lib.scala 244:80] - wire _T_643 = _T_639 | _T_642; // @[el2_lib.scala 244:25] - wire _T_645 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:38] - wire _T_646 = _T_645 & _T_583; // @[el2_lib.scala 244:43] - wire _T_649 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[el2_lib.scala 244:80] - wire _T_650 = _T_646 | _T_649; // @[el2_lib.scala 244:25] - wire _T_652 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:38] - wire _T_653 = _T_652 & _T_583; // @[el2_lib.scala 244:43] - wire _T_656 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[el2_lib.scala 244:80] - wire _T_657 = _T_653 | _T_656; // @[el2_lib.scala 244:25] - wire _T_659 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:38] - wire _T_660 = _T_659 & _T_583; // @[el2_lib.scala 244:43] - wire _T_663 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[el2_lib.scala 244:80] - wire _T_664 = _T_660 | _T_663; // @[el2_lib.scala 244:25] - wire _T_666 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:38] - wire _T_667 = _T_666 & _T_583; // @[el2_lib.scala 244:43] - wire _T_670 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[el2_lib.scala 244:80] - wire _T_671 = _T_667 | _T_670; // @[el2_lib.scala 244:25] - wire _T_673 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:38] - wire _T_674 = _T_673 & _T_583; // @[el2_lib.scala 244:43] - wire _T_677 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[el2_lib.scala 244:80] - wire _T_678 = _T_674 | _T_677; // @[el2_lib.scala 244:25] - wire _T_680 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:38] - wire _T_681 = _T_680 & _T_583; // @[el2_lib.scala 244:43] - wire _T_684 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[el2_lib.scala 244:80] - wire _T_685 = _T_681 | _T_684; // @[el2_lib.scala 244:25] - wire _T_687 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:38] - wire _T_688 = _T_687 & _T_583; // @[el2_lib.scala 244:43] - wire _T_691 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[el2_lib.scala 244:80] - wire _T_692 = _T_688 | _T_691; // @[el2_lib.scala 244:25] - wire _T_694 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:38] - wire _T_695 = _T_694 & _T_583; // @[el2_lib.scala 244:43] - wire _T_698 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[el2_lib.scala 244:80] - wire _T_699 = _T_695 | _T_698; // @[el2_lib.scala 244:25] - wire _T_701 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:38] - wire _T_702 = _T_701 & _T_583; // @[el2_lib.scala 244:43] - wire _T_705 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[el2_lib.scala 244:80] - wire _T_706 = _T_702 | _T_705; // @[el2_lib.scala 244:25] - wire _T_708 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:38] - wire _T_709 = _T_708 & _T_583; // @[el2_lib.scala 244:43] - wire _T_712 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[el2_lib.scala 244:80] - wire _T_713 = _T_709 | _T_712; // @[el2_lib.scala 244:25] - wire _T_715 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:38] - wire _T_716 = _T_715 & _T_583; // @[el2_lib.scala 244:43] - wire _T_719 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[el2_lib.scala 244:80] - wire _T_720 = _T_716 | _T_719; // @[el2_lib.scala 244:25] - wire _T_722 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:38] - wire _T_723 = _T_722 & _T_583; // @[el2_lib.scala 244:43] - wire _T_726 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[el2_lib.scala 244:80] - wire _T_727 = _T_723 | _T_726; // @[el2_lib.scala 244:25] - wire _T_729 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:38] - wire _T_730 = _T_729 & _T_583; // @[el2_lib.scala 244:43] - wire _T_733 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[el2_lib.scala 244:80] - wire _T_734 = _T_730 | _T_733; // @[el2_lib.scala 244:25] - wire _T_736 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:38] - wire _T_737 = _T_736 & _T_583; // @[el2_lib.scala 244:43] - wire _T_740 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[el2_lib.scala 244:80] - wire _T_741 = _T_737 | _T_740; // @[el2_lib.scala 244:25] - wire _T_743 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:38] - wire _T_744 = _T_743 & _T_583; // @[el2_lib.scala 244:43] - wire _T_747 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[el2_lib.scala 244:80] - wire _T_748 = _T_744 | _T_747; // @[el2_lib.scala 244:25] - wire _T_750 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:38] - wire _T_751 = _T_750 & _T_583; // @[el2_lib.scala 244:43] - wire _T_754 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[el2_lib.scala 244:80] - wire _T_755 = _T_751 | _T_754; // @[el2_lib.scala 244:25] - wire _T_757 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:38] - wire _T_758 = _T_757 & _T_583; // @[el2_lib.scala 244:43] - wire _T_761 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[el2_lib.scala 244:80] - wire _T_762 = _T_758 | _T_761; // @[el2_lib.scala 244:25] - wire _T_764 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:38] - wire _T_765 = _T_764 & _T_583; // @[el2_lib.scala 244:43] - wire _T_768 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[el2_lib.scala 244:80] - wire _T_769 = _T_765 | _T_768; // @[el2_lib.scala 244:25] - wire _T_771 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:38] - wire _T_772 = _T_771 & _T_583; // @[el2_lib.scala 244:43] - wire _T_775 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[el2_lib.scala 244:80] - wire _T_776 = _T_772 | _T_775; // @[el2_lib.scala 244:25] - wire _T_778 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:38] - wire _T_779 = _T_778 & _T_583; // @[el2_lib.scala 244:43] - wire _T_782 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[el2_lib.scala 244:80] - wire _T_783 = _T_779 | _T_782; // @[el2_lib.scala 244:25] - wire _T_785 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:38] - wire _T_786 = _T_785 & _T_583; // @[el2_lib.scala 244:43] - wire _T_789 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[el2_lib.scala 244:80] - wire _T_790 = _T_786 | _T_789; // @[el2_lib.scala 244:25] - wire _T_792 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:38] - wire _T_793 = _T_792 & _T_583; // @[el2_lib.scala 244:43] - wire _T_796 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[el2_lib.scala 244:80] - wire _T_797 = _T_793 | _T_796; // @[el2_lib.scala 244:25] - wire _T_799 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:38] - wire _T_800 = _T_799 & _T_583; // @[el2_lib.scala 244:43] - wire _T_803 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[el2_lib.scala 244:80] - wire _T_804 = _T_800 | _T_803; // @[el2_lib.scala 244:25] + wire _T_589 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_590 = _T_589 & _T_583; // @[el2_lib.scala 244:41] + wire _T_593 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[el2_lib.scala 244:78] + wire _T_594 = _T_590 | _T_593; // @[el2_lib.scala 244:23] + wire _T_596 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_597 = _T_596 & _T_583; // @[el2_lib.scala 244:41] + wire _T_600 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[el2_lib.scala 244:78] + wire _T_601 = _T_597 | _T_600; // @[el2_lib.scala 244:23] + wire _T_603 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_604 = _T_603 & _T_583; // @[el2_lib.scala 244:41] + wire _T_607 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[el2_lib.scala 244:78] + wire _T_608 = _T_604 | _T_607; // @[el2_lib.scala 244:23] + wire _T_610 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_611 = _T_610 & _T_583; // @[el2_lib.scala 244:41] + wire _T_614 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[el2_lib.scala 244:78] + wire _T_615 = _T_611 | _T_614; // @[el2_lib.scala 244:23] + wire _T_617 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_618 = _T_617 & _T_583; // @[el2_lib.scala 244:41] + wire _T_621 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[el2_lib.scala 244:78] + wire _T_622 = _T_618 | _T_621; // @[el2_lib.scala 244:23] + wire _T_624 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_625 = _T_624 & _T_583; // @[el2_lib.scala 244:41] + wire _T_628 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[el2_lib.scala 244:78] + wire _T_629 = _T_625 | _T_628; // @[el2_lib.scala 244:23] + wire _T_631 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_632 = _T_631 & _T_583; // @[el2_lib.scala 244:41] + wire _T_635 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[el2_lib.scala 244:78] + wire _T_636 = _T_632 | _T_635; // @[el2_lib.scala 244:23] + wire _T_638 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_639 = _T_638 & _T_583; // @[el2_lib.scala 244:41] + wire _T_642 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[el2_lib.scala 244:78] + wire _T_643 = _T_639 | _T_642; // @[el2_lib.scala 244:23] + wire _T_645 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_646 = _T_645 & _T_583; // @[el2_lib.scala 244:41] + wire _T_649 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[el2_lib.scala 244:78] + wire _T_650 = _T_646 | _T_649; // @[el2_lib.scala 244:23] + wire _T_652 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_653 = _T_652 & _T_583; // @[el2_lib.scala 244:41] + wire _T_656 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[el2_lib.scala 244:78] + wire _T_657 = _T_653 | _T_656; // @[el2_lib.scala 244:23] + wire _T_659 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_660 = _T_659 & _T_583; // @[el2_lib.scala 244:41] + wire _T_663 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[el2_lib.scala 244:78] + wire _T_664 = _T_660 | _T_663; // @[el2_lib.scala 244:23] + wire _T_666 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_667 = _T_666 & _T_583; // @[el2_lib.scala 244:41] + wire _T_670 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[el2_lib.scala 244:78] + wire _T_671 = _T_667 | _T_670; // @[el2_lib.scala 244:23] + wire _T_673 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_674 = _T_673 & _T_583; // @[el2_lib.scala 244:41] + wire _T_677 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[el2_lib.scala 244:78] + wire _T_678 = _T_674 | _T_677; // @[el2_lib.scala 244:23] + wire _T_680 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_681 = _T_680 & _T_583; // @[el2_lib.scala 244:41] + wire _T_684 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[el2_lib.scala 244:78] + wire _T_685 = _T_681 | _T_684; // @[el2_lib.scala 244:23] + wire _T_687 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_688 = _T_687 & _T_583; // @[el2_lib.scala 244:41] + wire _T_691 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[el2_lib.scala 244:78] + wire _T_692 = _T_688 | _T_691; // @[el2_lib.scala 244:23] + wire _T_694 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_695 = _T_694 & _T_583; // @[el2_lib.scala 244:41] + wire _T_698 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[el2_lib.scala 244:78] + wire _T_699 = _T_695 | _T_698; // @[el2_lib.scala 244:23] + wire _T_701 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_702 = _T_701 & _T_583; // @[el2_lib.scala 244:41] + wire _T_705 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[el2_lib.scala 244:78] + wire _T_706 = _T_702 | _T_705; // @[el2_lib.scala 244:23] + wire _T_708 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_709 = _T_708 & _T_583; // @[el2_lib.scala 244:41] + wire _T_712 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[el2_lib.scala 244:78] + wire _T_713 = _T_709 | _T_712; // @[el2_lib.scala 244:23] + wire _T_715 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_716 = _T_715 & _T_583; // @[el2_lib.scala 244:41] + wire _T_719 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[el2_lib.scala 244:78] + wire _T_720 = _T_716 | _T_719; // @[el2_lib.scala 244:23] + wire _T_722 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_723 = _T_722 & _T_583; // @[el2_lib.scala 244:41] + wire _T_726 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[el2_lib.scala 244:78] + wire _T_727 = _T_723 | _T_726; // @[el2_lib.scala 244:23] + wire _T_729 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_730 = _T_729 & _T_583; // @[el2_lib.scala 244:41] + wire _T_733 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[el2_lib.scala 244:78] + wire _T_734 = _T_730 | _T_733; // @[el2_lib.scala 244:23] + wire _T_736 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_737 = _T_736 & _T_583; // @[el2_lib.scala 244:41] + wire _T_740 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[el2_lib.scala 244:78] + wire _T_741 = _T_737 | _T_740; // @[el2_lib.scala 244:23] + wire _T_743 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_744 = _T_743 & _T_583; // @[el2_lib.scala 244:41] + wire _T_747 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[el2_lib.scala 244:78] + wire _T_748 = _T_744 | _T_747; // @[el2_lib.scala 244:23] + wire _T_750 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_751 = _T_750 & _T_583; // @[el2_lib.scala 244:41] + wire _T_754 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[el2_lib.scala 244:78] + wire _T_755 = _T_751 | _T_754; // @[el2_lib.scala 244:23] + wire _T_757 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_758 = _T_757 & _T_583; // @[el2_lib.scala 244:41] + wire _T_761 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[el2_lib.scala 244:78] + wire _T_762 = _T_758 | _T_761; // @[el2_lib.scala 244:23] + wire _T_764 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_765 = _T_764 & _T_583; // @[el2_lib.scala 244:41] + wire _T_768 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[el2_lib.scala 244:78] + wire _T_769 = _T_765 | _T_768; // @[el2_lib.scala 244:23] + wire _T_771 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_772 = _T_771 & _T_583; // @[el2_lib.scala 244:41] + wire _T_775 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[el2_lib.scala 244:78] + wire _T_776 = _T_772 | _T_775; // @[el2_lib.scala 244:23] + wire _T_778 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_779 = _T_778 & _T_583; // @[el2_lib.scala 244:41] + wire _T_782 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[el2_lib.scala 244:78] + wire _T_783 = _T_779 | _T_782; // @[el2_lib.scala 244:23] + wire _T_785 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_786 = _T_785 & _T_583; // @[el2_lib.scala 244:41] + wire _T_789 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[el2_lib.scala 244:78] + wire _T_790 = _T_786 | _T_789; // @[el2_lib.scala 244:23] + wire _T_792 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_793 = _T_792 & _T_583; // @[el2_lib.scala 244:41] + wire _T_796 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[el2_lib.scala 244:78] + wire _T_797 = _T_793 | _T_796; // @[el2_lib.scala 244:23] + wire _T_799 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_800 = _T_799 & _T_583; // @[el2_lib.scala 244:41] + wire _T_803 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[el2_lib.scala 244:78] + wire _T_804 = _T_800 | _T_803; // @[el2_lib.scala 244:23] wire [7:0] _T_811 = {_T_636,_T_629,_T_622,_T_615,_T_608,_T_601,_T_594,_T_587}; // @[el2_lib.scala 245:14] wire [15:0] _T_819 = {_T_692,_T_685,_T_678,_T_671,_T_664,_T_657,_T_650,_T_643,_T_811}; // @[el2_lib.scala 245:14] wire [7:0] _T_826 = {_T_748,_T_741,_T_734,_T_727,_T_720,_T_713,_T_706,_T_699}; // @[el2_lib.scala 245:14] @@ -4663,133 +4664,133 @@ module el2_lsu_trigger( wire _T_844 = _T_40 & _T_843; // @[el2_lsu_trigger.scala 18:94] wire _T_847 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] wire _T_848 = ~_T_847; // @[el2_lib.scala 241:39] - wire _T_849 = io_trigger_pkt_any_3_match_ & _T_848; // @[el2_lib.scala 241:37] + wire _T_849 = io_trigger_pkt_any_3_match_pkt & _T_848; // @[el2_lib.scala 241:37] wire _T_852 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[el2_lib.scala 242:52] wire _T_853 = _T_849 | _T_852; // @[el2_lib.scala 242:41] - wire _T_855 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:38] - wire _T_856 = _T_855 & _T_849; // @[el2_lib.scala 244:43] - wire _T_859 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[el2_lib.scala 244:80] - wire _T_860 = _T_856 | _T_859; // @[el2_lib.scala 244:25] - wire _T_862 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:38] - wire _T_863 = _T_862 & _T_849; // @[el2_lib.scala 244:43] - wire _T_866 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[el2_lib.scala 244:80] - wire _T_867 = _T_863 | _T_866; // @[el2_lib.scala 244:25] - wire _T_869 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:38] - wire _T_870 = _T_869 & _T_849; // @[el2_lib.scala 244:43] - wire _T_873 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[el2_lib.scala 244:80] - wire _T_874 = _T_870 | _T_873; // @[el2_lib.scala 244:25] - wire _T_876 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:38] - wire _T_877 = _T_876 & _T_849; // @[el2_lib.scala 244:43] - wire _T_880 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[el2_lib.scala 244:80] - wire _T_881 = _T_877 | _T_880; // @[el2_lib.scala 244:25] - wire _T_883 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:38] - wire _T_884 = _T_883 & _T_849; // @[el2_lib.scala 244:43] - wire _T_887 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[el2_lib.scala 244:80] - wire _T_888 = _T_884 | _T_887; // @[el2_lib.scala 244:25] - wire _T_890 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:38] - wire _T_891 = _T_890 & _T_849; // @[el2_lib.scala 244:43] - wire _T_894 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[el2_lib.scala 244:80] - wire _T_895 = _T_891 | _T_894; // @[el2_lib.scala 244:25] - wire _T_897 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:38] - wire _T_898 = _T_897 & _T_849; // @[el2_lib.scala 244:43] - wire _T_901 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[el2_lib.scala 244:80] - wire _T_902 = _T_898 | _T_901; // @[el2_lib.scala 244:25] - wire _T_904 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:38] - wire _T_905 = _T_904 & _T_849; // @[el2_lib.scala 244:43] - wire _T_908 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[el2_lib.scala 244:80] - wire _T_909 = _T_905 | _T_908; // @[el2_lib.scala 244:25] - wire _T_911 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:38] - wire _T_912 = _T_911 & _T_849; // @[el2_lib.scala 244:43] - wire _T_915 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[el2_lib.scala 244:80] - wire _T_916 = _T_912 | _T_915; // @[el2_lib.scala 244:25] - wire _T_918 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:38] - wire _T_919 = _T_918 & _T_849; // @[el2_lib.scala 244:43] - wire _T_922 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[el2_lib.scala 244:80] - wire _T_923 = _T_919 | _T_922; // @[el2_lib.scala 244:25] - wire _T_925 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:38] - wire _T_926 = _T_925 & _T_849; // @[el2_lib.scala 244:43] - wire _T_929 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[el2_lib.scala 244:80] - wire _T_930 = _T_926 | _T_929; // @[el2_lib.scala 244:25] - wire _T_932 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:38] - wire _T_933 = _T_932 & _T_849; // @[el2_lib.scala 244:43] - wire _T_936 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[el2_lib.scala 244:80] - wire _T_937 = _T_933 | _T_936; // @[el2_lib.scala 244:25] - wire _T_939 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:38] - wire _T_940 = _T_939 & _T_849; // @[el2_lib.scala 244:43] - wire _T_943 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[el2_lib.scala 244:80] - wire _T_944 = _T_940 | _T_943; // @[el2_lib.scala 244:25] - wire _T_946 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:38] - wire _T_947 = _T_946 & _T_849; // @[el2_lib.scala 244:43] - wire _T_950 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[el2_lib.scala 244:80] - wire _T_951 = _T_947 | _T_950; // @[el2_lib.scala 244:25] - wire _T_953 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:38] - wire _T_954 = _T_953 & _T_849; // @[el2_lib.scala 244:43] - wire _T_957 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[el2_lib.scala 244:80] - wire _T_958 = _T_954 | _T_957; // @[el2_lib.scala 244:25] - wire _T_960 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:38] - wire _T_961 = _T_960 & _T_849; // @[el2_lib.scala 244:43] - wire _T_964 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[el2_lib.scala 244:80] - wire _T_965 = _T_961 | _T_964; // @[el2_lib.scala 244:25] - wire _T_967 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:38] - wire _T_968 = _T_967 & _T_849; // @[el2_lib.scala 244:43] - wire _T_971 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[el2_lib.scala 244:80] - wire _T_972 = _T_968 | _T_971; // @[el2_lib.scala 244:25] - wire _T_974 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:38] - wire _T_975 = _T_974 & _T_849; // @[el2_lib.scala 244:43] - wire _T_978 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[el2_lib.scala 244:80] - wire _T_979 = _T_975 | _T_978; // @[el2_lib.scala 244:25] - wire _T_981 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:38] - wire _T_982 = _T_981 & _T_849; // @[el2_lib.scala 244:43] - wire _T_985 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[el2_lib.scala 244:80] - wire _T_986 = _T_982 | _T_985; // @[el2_lib.scala 244:25] - wire _T_988 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:38] - wire _T_989 = _T_988 & _T_849; // @[el2_lib.scala 244:43] - wire _T_992 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[el2_lib.scala 244:80] - wire _T_993 = _T_989 | _T_992; // @[el2_lib.scala 244:25] - wire _T_995 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:38] - wire _T_996 = _T_995 & _T_849; // @[el2_lib.scala 244:43] - wire _T_999 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[el2_lib.scala 244:80] - wire _T_1000 = _T_996 | _T_999; // @[el2_lib.scala 244:25] - wire _T_1002 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:38] - wire _T_1003 = _T_1002 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1006 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[el2_lib.scala 244:80] - wire _T_1007 = _T_1003 | _T_1006; // @[el2_lib.scala 244:25] - wire _T_1009 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:38] - wire _T_1010 = _T_1009 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1013 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[el2_lib.scala 244:80] - wire _T_1014 = _T_1010 | _T_1013; // @[el2_lib.scala 244:25] - wire _T_1016 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:38] - wire _T_1017 = _T_1016 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1020 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[el2_lib.scala 244:80] - wire _T_1021 = _T_1017 | _T_1020; // @[el2_lib.scala 244:25] - wire _T_1023 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:38] - wire _T_1024 = _T_1023 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1027 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[el2_lib.scala 244:80] - wire _T_1028 = _T_1024 | _T_1027; // @[el2_lib.scala 244:25] - wire _T_1030 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:38] - wire _T_1031 = _T_1030 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1034 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[el2_lib.scala 244:80] - wire _T_1035 = _T_1031 | _T_1034; // @[el2_lib.scala 244:25] - wire _T_1037 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:38] - wire _T_1038 = _T_1037 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1041 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[el2_lib.scala 244:80] - wire _T_1042 = _T_1038 | _T_1041; // @[el2_lib.scala 244:25] - wire _T_1044 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:38] - wire _T_1045 = _T_1044 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1048 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[el2_lib.scala 244:80] - wire _T_1049 = _T_1045 | _T_1048; // @[el2_lib.scala 244:25] - wire _T_1051 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:38] - wire _T_1052 = _T_1051 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1055 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[el2_lib.scala 244:80] - wire _T_1056 = _T_1052 | _T_1055; // @[el2_lib.scala 244:25] - wire _T_1058 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:38] - wire _T_1059 = _T_1058 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1062 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[el2_lib.scala 244:80] - wire _T_1063 = _T_1059 | _T_1062; // @[el2_lib.scala 244:25] - wire _T_1065 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:38] - wire _T_1066 = _T_1065 & _T_849; // @[el2_lib.scala 244:43] - wire _T_1069 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[el2_lib.scala 244:80] - wire _T_1070 = _T_1066 | _T_1069; // @[el2_lib.scala 244:25] + wire _T_855 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] + wire _T_856 = _T_855 & _T_849; // @[el2_lib.scala 244:41] + wire _T_859 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[el2_lib.scala 244:78] + wire _T_860 = _T_856 | _T_859; // @[el2_lib.scala 244:23] + wire _T_862 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:36] + wire _T_863 = _T_862 & _T_849; // @[el2_lib.scala 244:41] + wire _T_866 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[el2_lib.scala 244:78] + wire _T_867 = _T_863 | _T_866; // @[el2_lib.scala 244:23] + wire _T_869 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:36] + wire _T_870 = _T_869 & _T_849; // @[el2_lib.scala 244:41] + wire _T_873 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[el2_lib.scala 244:78] + wire _T_874 = _T_870 | _T_873; // @[el2_lib.scala 244:23] + wire _T_876 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:36] + wire _T_877 = _T_876 & _T_849; // @[el2_lib.scala 244:41] + wire _T_880 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[el2_lib.scala 244:78] + wire _T_881 = _T_877 | _T_880; // @[el2_lib.scala 244:23] + wire _T_883 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:36] + wire _T_884 = _T_883 & _T_849; // @[el2_lib.scala 244:41] + wire _T_887 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[el2_lib.scala 244:78] + wire _T_888 = _T_884 | _T_887; // @[el2_lib.scala 244:23] + wire _T_890 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:36] + wire _T_891 = _T_890 & _T_849; // @[el2_lib.scala 244:41] + wire _T_894 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[el2_lib.scala 244:78] + wire _T_895 = _T_891 | _T_894; // @[el2_lib.scala 244:23] + wire _T_897 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:36] + wire _T_898 = _T_897 & _T_849; // @[el2_lib.scala 244:41] + wire _T_901 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[el2_lib.scala 244:78] + wire _T_902 = _T_898 | _T_901; // @[el2_lib.scala 244:23] + wire _T_904 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:36] + wire _T_905 = _T_904 & _T_849; // @[el2_lib.scala 244:41] + wire _T_908 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[el2_lib.scala 244:78] + wire _T_909 = _T_905 | _T_908; // @[el2_lib.scala 244:23] + wire _T_911 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:36] + wire _T_912 = _T_911 & _T_849; // @[el2_lib.scala 244:41] + wire _T_915 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[el2_lib.scala 244:78] + wire _T_916 = _T_912 | _T_915; // @[el2_lib.scala 244:23] + wire _T_918 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:36] + wire _T_919 = _T_918 & _T_849; // @[el2_lib.scala 244:41] + wire _T_922 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[el2_lib.scala 244:78] + wire _T_923 = _T_919 | _T_922; // @[el2_lib.scala 244:23] + wire _T_925 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:36] + wire _T_926 = _T_925 & _T_849; // @[el2_lib.scala 244:41] + wire _T_929 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[el2_lib.scala 244:78] + wire _T_930 = _T_926 | _T_929; // @[el2_lib.scala 244:23] + wire _T_932 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:36] + wire _T_933 = _T_932 & _T_849; // @[el2_lib.scala 244:41] + wire _T_936 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[el2_lib.scala 244:78] + wire _T_937 = _T_933 | _T_936; // @[el2_lib.scala 244:23] + wire _T_939 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:36] + wire _T_940 = _T_939 & _T_849; // @[el2_lib.scala 244:41] + wire _T_943 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[el2_lib.scala 244:78] + wire _T_944 = _T_940 | _T_943; // @[el2_lib.scala 244:23] + wire _T_946 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:36] + wire _T_947 = _T_946 & _T_849; // @[el2_lib.scala 244:41] + wire _T_950 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[el2_lib.scala 244:78] + wire _T_951 = _T_947 | _T_950; // @[el2_lib.scala 244:23] + wire _T_953 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:36] + wire _T_954 = _T_953 & _T_849; // @[el2_lib.scala 244:41] + wire _T_957 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[el2_lib.scala 244:78] + wire _T_958 = _T_954 | _T_957; // @[el2_lib.scala 244:23] + wire _T_960 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:36] + wire _T_961 = _T_960 & _T_849; // @[el2_lib.scala 244:41] + wire _T_964 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[el2_lib.scala 244:78] + wire _T_965 = _T_961 | _T_964; // @[el2_lib.scala 244:23] + wire _T_967 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:36] + wire _T_968 = _T_967 & _T_849; // @[el2_lib.scala 244:41] + wire _T_971 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[el2_lib.scala 244:78] + wire _T_972 = _T_968 | _T_971; // @[el2_lib.scala 244:23] + wire _T_974 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:36] + wire _T_975 = _T_974 & _T_849; // @[el2_lib.scala 244:41] + wire _T_978 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[el2_lib.scala 244:78] + wire _T_979 = _T_975 | _T_978; // @[el2_lib.scala 244:23] + wire _T_981 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:36] + wire _T_982 = _T_981 & _T_849; // @[el2_lib.scala 244:41] + wire _T_985 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[el2_lib.scala 244:78] + wire _T_986 = _T_982 | _T_985; // @[el2_lib.scala 244:23] + wire _T_988 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:36] + wire _T_989 = _T_988 & _T_849; // @[el2_lib.scala 244:41] + wire _T_992 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[el2_lib.scala 244:78] + wire _T_993 = _T_989 | _T_992; // @[el2_lib.scala 244:23] + wire _T_995 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:36] + wire _T_996 = _T_995 & _T_849; // @[el2_lib.scala 244:41] + wire _T_999 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[el2_lib.scala 244:78] + wire _T_1000 = _T_996 | _T_999; // @[el2_lib.scala 244:23] + wire _T_1002 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:36] + wire _T_1003 = _T_1002 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1006 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[el2_lib.scala 244:78] + wire _T_1007 = _T_1003 | _T_1006; // @[el2_lib.scala 244:23] + wire _T_1009 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:36] + wire _T_1010 = _T_1009 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1013 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[el2_lib.scala 244:78] + wire _T_1014 = _T_1010 | _T_1013; // @[el2_lib.scala 244:23] + wire _T_1016 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:36] + wire _T_1017 = _T_1016 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1020 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[el2_lib.scala 244:78] + wire _T_1021 = _T_1017 | _T_1020; // @[el2_lib.scala 244:23] + wire _T_1023 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:36] + wire _T_1024 = _T_1023 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1027 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[el2_lib.scala 244:78] + wire _T_1028 = _T_1024 | _T_1027; // @[el2_lib.scala 244:23] + wire _T_1030 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:36] + wire _T_1031 = _T_1030 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1034 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[el2_lib.scala 244:78] + wire _T_1035 = _T_1031 | _T_1034; // @[el2_lib.scala 244:23] + wire _T_1037 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:36] + wire _T_1038 = _T_1037 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1041 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[el2_lib.scala 244:78] + wire _T_1042 = _T_1038 | _T_1041; // @[el2_lib.scala 244:23] + wire _T_1044 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:36] + wire _T_1045 = _T_1044 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1048 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[el2_lib.scala 244:78] + wire _T_1049 = _T_1045 | _T_1048; // @[el2_lib.scala 244:23] + wire _T_1051 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:36] + wire _T_1052 = _T_1051 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1055 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[el2_lib.scala 244:78] + wire _T_1056 = _T_1052 | _T_1055; // @[el2_lib.scala 244:23] + wire _T_1058 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:36] + wire _T_1059 = _T_1058 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1062 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[el2_lib.scala 244:78] + wire _T_1063 = _T_1059 | _T_1062; // @[el2_lib.scala 244:23] + wire _T_1065 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:36] + wire _T_1066 = _T_1065 & _T_849; // @[el2_lib.scala 244:41] + wire _T_1069 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[el2_lib.scala 244:78] + wire _T_1070 = _T_1066 | _T_1069; // @[el2_lib.scala 244:23] wire [7:0] _T_1077 = {_T_902,_T_895,_T_888,_T_881,_T_874,_T_867,_T_860,_T_853}; // @[el2_lib.scala 245:14] wire [15:0] _T_1085 = {_T_958,_T_951,_T_944,_T_937,_T_930,_T_923,_T_916,_T_909,_T_1077}; // @[el2_lib.scala 245:14] wire [7:0] _T_1092 = {_T_1014,_T_1007,_T_1000,_T_993,_T_986,_T_979,_T_972,_T_965}; // @[el2_lib.scala 245:14] @@ -10356,28 +10357,28 @@ module el2_lsu( input io_lsu_p_bits_load_ldst_bypass_d, input io_lsu_p_bits_store_data_bypass_m, input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_store, input io_trigger_pkt_any_0_load, input io_trigger_pkt_any_0_execute, input io_trigger_pkt_any_0_m, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_store, input io_trigger_pkt_any_1_load, input io_trigger_pkt_any_1_execute, input io_trigger_pkt_any_1_m, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_store, input io_trigger_pkt_any_2_load, input io_trigger_pkt_any_2_execute, input io_trigger_pkt_any_2_m, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_store, input io_trigger_pkt_any_3_load, input io_trigger_pkt_any_3_execute, @@ -10398,8 +10399,8 @@ module el2_lsu( output io_lsu_error_pkt_r_bits_single_ecc_error, output io_lsu_error_pkt_r_bits_inst_type, output io_lsu_error_pkt_r_bits_exc_type, - output io_lsu_error_pkt_r_bits_mscause, - output io_lsu_error_pkt_r_bits_addr, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, output io_lsu_imprecise_error_load_any, output io_lsu_imprecise_error_store_any, output [31:0] io_lsu_imprecise_error_addr_any, @@ -10546,8 +10547,8 @@ module el2_lsu( wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_lsu.scala 154:30] wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[el2_lsu.scala 154:30] wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[el2_lsu.scala 154:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[el2_lsu.scala 154:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[el2_lsu.scala 154:30] + wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[el2_lsu.scala 154:30] wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[el2_lsu.scala 154:30] wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[el2_lsu.scala 154:30] wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 154:30] @@ -10787,22 +10788,22 @@ module el2_lsu( wire ecc_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 159:30] wire ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 159:30] wire trigger_io_trigger_pkt_any_0_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_0_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_0_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_0_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_0_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_1_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_1_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_1_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_1_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_1_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_2_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_2_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_2_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_2_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_2_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_3_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_3_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_3_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_3_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_3_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 160:30] @@ -11269,22 +11270,22 @@ module el2_lsu( ); el2_lsu_trigger trigger ( // @[el2_lsu.scala 160:30] .io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(trigger_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(trigger_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(trigger_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_tdata2(trigger_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(trigger_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(trigger_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(trigger_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(trigger_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(trigger_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_tdata2(trigger_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(trigger_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(trigger_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(trigger_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(trigger_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(trigger_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_tdata2(trigger_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(trigger_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(trigger_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(trigger_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(trigger_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(trigger_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_tdata2(trigger_io_trigger_pkt_any_3_tdata2), @@ -11669,22 +11670,22 @@ module el2_lsu( assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[el2_lsu.scala 371:50] assign ecc_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 372:50] assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_0_match_ = io_trigger_pkt_any_0_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_1_match_ = io_trigger_pkt_any_1_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_2_match_ = io_trigger_pkt_any_2_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_3_match_ = io_trigger_pkt_any_3_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 376:50] diff --git a/el2_swerv.fir b/el2_swerv.fir index 6ac5e4ae..95cd3189 100644 --- a/el2_swerv.fir +++ b/el2_swerv.fir @@ -28977,7 +28977,7 @@ circuit el2_swerv : module el2_ifu_bp_ctl : input clock : Clock input reset : AsyncReset - output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt} + output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt} wire leak_one_f : UInt<1> leak_one_f <= UInt<1>("h00") @@ -29004,10 +29004,10 @@ circuit el2_swerv : dec_tlu_way_wb <= UInt<1>("h00") node _T = eq(leak_one_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 72:51] node exu_mp_valid = and(io.exu_mp_pkt.bits.misp, _T) @[el2_ifu_bp_ctl.scala 72:49] - node _T_1 = or(io.dec_tlu_br0_r_pkt.bits.br_start_error, io.dec_tlu_br0_r_pkt.bits.br_error) @[el2_ifu_bp_ctl.scala 94:50] + node _T_1 = or(io.dec_tlu_br0_r_pkt.br_start_error, io.dec_tlu_br0_r_pkt.br_error) @[el2_ifu_bp_ctl.scala 94:50] dec_tlu_error_wb <= _T_1 @[el2_ifu_bp_ctl.scala 94:20] btb_error_addr_wb <= io.exu_i0_br_index_r @[el2_ifu_bp_ctl.scala 95:21] - dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu_bp_ctl.scala 96:18] + dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.way @[el2_ifu_bp_ctl.scala 96:18] node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 191:13] node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 191:51] node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 191:47] @@ -29814,8 +29814,8 @@ circuit el2_swerv : node bht_wr_en0 = and(_T_556, _T_558) @[el2_ifu_bp_ctl.scala 408:84] node _T_559 = bits(io.dec_tlu_br0_r_pkt.valid, 0, 0) @[Bitwise.scala 72:15] node _T_560 = mux(_T_559, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_561 = not(io.dec_tlu_br0_r_pkt.bits.middle) @[el2_ifu_bp_ctl.scala 409:75] - node _T_562 = cat(io.dec_tlu_br0_r_pkt.bits.middle, _T_561) @[Cat.scala 29:58] + node _T_561 = not(io.dec_tlu_br0_r_pkt.middle) @[el2_ifu_bp_ctl.scala 409:75] + node _T_562 = cat(io.dec_tlu_br0_r_pkt.middle, _T_561) @[Cat.scala 29:58] node bht_wr_en2 = and(_T_560, _T_562) @[el2_ifu_bp_ctl.scala 409:46] node _T_563 = cat(io.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58] node _T_564 = bits(_T_563, 9, 2) @[el2_lib.scala 196:16] @@ -40155,7 +40155,7 @@ circuit el2_swerv : node _T_6565 = and(_T_6562, _T_6564) @[el2_ifu_bp_ctl.scala 447:81] node _T_6566 = or(_T_6565, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6567 = bits(_T_6566, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6568 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6569 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6570 = eq(_T_6569, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40165,7 +40165,7 @@ circuit el2_swerv : node _T_6574 = and(_T_6571, _T_6573) @[el2_ifu_bp_ctl.scala 447:81] node _T_6575 = or(_T_6574, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6576 = bits(_T_6575, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6577 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6578 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6579 = eq(_T_6578, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40175,7 +40175,7 @@ circuit el2_swerv : node _T_6583 = and(_T_6580, _T_6582) @[el2_ifu_bp_ctl.scala 447:81] node _T_6584 = or(_T_6583, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6585 = bits(_T_6584, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6586 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6587 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6588 = eq(_T_6587, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40185,7 +40185,7 @@ circuit el2_swerv : node _T_6592 = and(_T_6589, _T_6591) @[el2_ifu_bp_ctl.scala 447:81] node _T_6593 = or(_T_6592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6594 = bits(_T_6593, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6595 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6596 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6597 = eq(_T_6596, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40195,7 +40195,7 @@ circuit el2_swerv : node _T_6601 = and(_T_6598, _T_6600) @[el2_ifu_bp_ctl.scala 447:81] node _T_6602 = or(_T_6601, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6603 = bits(_T_6602, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6604 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6605 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6606 = eq(_T_6605, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40205,7 +40205,7 @@ circuit el2_swerv : node _T_6610 = and(_T_6607, _T_6609) @[el2_ifu_bp_ctl.scala 447:81] node _T_6611 = or(_T_6610, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6612 = bits(_T_6611, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6613 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6614 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6615 = eq(_T_6614, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40215,7 +40215,7 @@ circuit el2_swerv : node _T_6619 = and(_T_6616, _T_6618) @[el2_ifu_bp_ctl.scala 447:81] node _T_6620 = or(_T_6619, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6621 = bits(_T_6620, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6622 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6623 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6624 = eq(_T_6623, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40225,7 +40225,7 @@ circuit el2_swerv : node _T_6628 = and(_T_6625, _T_6627) @[el2_ifu_bp_ctl.scala 447:81] node _T_6629 = or(_T_6628, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6630 = bits(_T_6629, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6631 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6632 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6633 = eq(_T_6632, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40235,7 +40235,7 @@ circuit el2_swerv : node _T_6637 = and(_T_6634, _T_6636) @[el2_ifu_bp_ctl.scala 447:81] node _T_6638 = or(_T_6637, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6639 = bits(_T_6638, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6640 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6641 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6642 = eq(_T_6641, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40245,7 +40245,7 @@ circuit el2_swerv : node _T_6646 = and(_T_6643, _T_6645) @[el2_ifu_bp_ctl.scala 447:81] node _T_6647 = or(_T_6646, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6648 = bits(_T_6647, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6649 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6650 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6651 = eq(_T_6650, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40255,7 +40255,7 @@ circuit el2_swerv : node _T_6655 = and(_T_6652, _T_6654) @[el2_ifu_bp_ctl.scala 447:81] node _T_6656 = or(_T_6655, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6657 = bits(_T_6656, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6658 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6659 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6660 = eq(_T_6659, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40265,7 +40265,7 @@ circuit el2_swerv : node _T_6664 = and(_T_6661, _T_6663) @[el2_ifu_bp_ctl.scala 447:81] node _T_6665 = or(_T_6664, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6666 = bits(_T_6665, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6667 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6668 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6669 = eq(_T_6668, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40275,7 +40275,7 @@ circuit el2_swerv : node _T_6673 = and(_T_6670, _T_6672) @[el2_ifu_bp_ctl.scala 447:81] node _T_6674 = or(_T_6673, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6675 = bits(_T_6674, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6676 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6677 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6678 = eq(_T_6677, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40285,7 +40285,7 @@ circuit el2_swerv : node _T_6682 = and(_T_6679, _T_6681) @[el2_ifu_bp_ctl.scala 447:81] node _T_6683 = or(_T_6682, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6684 = bits(_T_6683, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6685 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6686 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6687 = eq(_T_6686, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40295,7 +40295,7 @@ circuit el2_swerv : node _T_6691 = and(_T_6688, _T_6690) @[el2_ifu_bp_ctl.scala 447:81] node _T_6692 = or(_T_6691, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6693 = bits(_T_6692, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6694 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6695 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6696 = eq(_T_6695, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40305,7 +40305,7 @@ circuit el2_swerv : node _T_6700 = and(_T_6697, _T_6699) @[el2_ifu_bp_ctl.scala 447:81] node _T_6701 = or(_T_6700, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6702 = bits(_T_6701, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6703 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6704 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6705 = eq(_T_6704, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40315,7 +40315,7 @@ circuit el2_swerv : node _T_6709 = and(_T_6706, _T_6708) @[el2_ifu_bp_ctl.scala 447:81] node _T_6710 = or(_T_6709, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6711 = bits(_T_6710, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6712 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6713 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6714 = eq(_T_6713, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40325,7 +40325,7 @@ circuit el2_swerv : node _T_6718 = and(_T_6715, _T_6717) @[el2_ifu_bp_ctl.scala 447:81] node _T_6719 = or(_T_6718, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6720 = bits(_T_6719, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6721 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6722 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6723 = eq(_T_6722, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40335,7 +40335,7 @@ circuit el2_swerv : node _T_6727 = and(_T_6724, _T_6726) @[el2_ifu_bp_ctl.scala 447:81] node _T_6728 = or(_T_6727, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6729 = bits(_T_6728, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6730 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6731 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6732 = eq(_T_6731, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40345,7 +40345,7 @@ circuit el2_swerv : node _T_6736 = and(_T_6733, _T_6735) @[el2_ifu_bp_ctl.scala 447:81] node _T_6737 = or(_T_6736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6738 = bits(_T_6737, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6739 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6740 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6741 = eq(_T_6740, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40355,7 +40355,7 @@ circuit el2_swerv : node _T_6745 = and(_T_6742, _T_6744) @[el2_ifu_bp_ctl.scala 447:81] node _T_6746 = or(_T_6745, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6747 = bits(_T_6746, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6748 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6749 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6750 = eq(_T_6749, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40365,7 +40365,7 @@ circuit el2_swerv : node _T_6754 = and(_T_6751, _T_6753) @[el2_ifu_bp_ctl.scala 447:81] node _T_6755 = or(_T_6754, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6756 = bits(_T_6755, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6757 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6758 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6759 = eq(_T_6758, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40375,7 +40375,7 @@ circuit el2_swerv : node _T_6763 = and(_T_6760, _T_6762) @[el2_ifu_bp_ctl.scala 447:81] node _T_6764 = or(_T_6763, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6765 = bits(_T_6764, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6766 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6767 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6768 = eq(_T_6767, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40385,7 +40385,7 @@ circuit el2_swerv : node _T_6772 = and(_T_6769, _T_6771) @[el2_ifu_bp_ctl.scala 447:81] node _T_6773 = or(_T_6772, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6774 = bits(_T_6773, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6775 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6776 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6777 = eq(_T_6776, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40395,7 +40395,7 @@ circuit el2_swerv : node _T_6781 = and(_T_6778, _T_6780) @[el2_ifu_bp_ctl.scala 447:81] node _T_6782 = or(_T_6781, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6783 = bits(_T_6782, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6784 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6785 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6786 = eq(_T_6785, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40405,7 +40405,7 @@ circuit el2_swerv : node _T_6790 = and(_T_6787, _T_6789) @[el2_ifu_bp_ctl.scala 447:81] node _T_6791 = or(_T_6790, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6792 = bits(_T_6791, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6793 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6794 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6795 = eq(_T_6794, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40415,7 +40415,7 @@ circuit el2_swerv : node _T_6799 = and(_T_6796, _T_6798) @[el2_ifu_bp_ctl.scala 447:81] node _T_6800 = or(_T_6799, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6801 = bits(_T_6800, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6802 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6803 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6804 = eq(_T_6803, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40425,7 +40425,7 @@ circuit el2_swerv : node _T_6808 = and(_T_6805, _T_6807) @[el2_ifu_bp_ctl.scala 447:81] node _T_6809 = or(_T_6808, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6810 = bits(_T_6809, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6811 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6812 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6813 = eq(_T_6812, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40435,7 +40435,7 @@ circuit el2_swerv : node _T_6817 = and(_T_6814, _T_6816) @[el2_ifu_bp_ctl.scala 447:81] node _T_6818 = or(_T_6817, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6819 = bits(_T_6818, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6820 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6821 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6822 = eq(_T_6821, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40445,7 +40445,7 @@ circuit el2_swerv : node _T_6826 = and(_T_6823, _T_6825) @[el2_ifu_bp_ctl.scala 447:81] node _T_6827 = or(_T_6826, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6828 = bits(_T_6827, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6829 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6830 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6831 = eq(_T_6830, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40455,7 +40455,7 @@ circuit el2_swerv : node _T_6835 = and(_T_6832, _T_6834) @[el2_ifu_bp_ctl.scala 447:81] node _T_6836 = or(_T_6835, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6837 = bits(_T_6836, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6838 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6839 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6840 = eq(_T_6839, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40465,7 +40465,7 @@ circuit el2_swerv : node _T_6844 = and(_T_6841, _T_6843) @[el2_ifu_bp_ctl.scala 447:81] node _T_6845 = or(_T_6844, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6846 = bits(_T_6845, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6847 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6848 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6849 = eq(_T_6848, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40475,7 +40475,7 @@ circuit el2_swerv : node _T_6853 = and(_T_6850, _T_6852) @[el2_ifu_bp_ctl.scala 447:81] node _T_6854 = or(_T_6853, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6855 = bits(_T_6854, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6856 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6857 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6858 = eq(_T_6857, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40485,7 +40485,7 @@ circuit el2_swerv : node _T_6862 = and(_T_6859, _T_6861) @[el2_ifu_bp_ctl.scala 447:81] node _T_6863 = or(_T_6862, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6864 = bits(_T_6863, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6865 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6866 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6867 = eq(_T_6866, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40495,7 +40495,7 @@ circuit el2_swerv : node _T_6871 = and(_T_6868, _T_6870) @[el2_ifu_bp_ctl.scala 447:81] node _T_6872 = or(_T_6871, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6873 = bits(_T_6872, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6874 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6875 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6876 = eq(_T_6875, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40505,7 +40505,7 @@ circuit el2_swerv : node _T_6880 = and(_T_6877, _T_6879) @[el2_ifu_bp_ctl.scala 447:81] node _T_6881 = or(_T_6880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6882 = bits(_T_6881, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6883 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6884 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6885 = eq(_T_6884, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40515,7 +40515,7 @@ circuit el2_swerv : node _T_6889 = and(_T_6886, _T_6888) @[el2_ifu_bp_ctl.scala 447:81] node _T_6890 = or(_T_6889, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6891 = bits(_T_6890, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6892 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6893 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6894 = eq(_T_6893, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40525,7 +40525,7 @@ circuit el2_swerv : node _T_6898 = and(_T_6895, _T_6897) @[el2_ifu_bp_ctl.scala 447:81] node _T_6899 = or(_T_6898, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6900 = bits(_T_6899, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6901 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6902 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6903 = eq(_T_6902, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40535,7 +40535,7 @@ circuit el2_swerv : node _T_6907 = and(_T_6904, _T_6906) @[el2_ifu_bp_ctl.scala 447:81] node _T_6908 = or(_T_6907, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6909 = bits(_T_6908, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6910 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6911 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6912 = eq(_T_6911, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40545,7 +40545,7 @@ circuit el2_swerv : node _T_6916 = and(_T_6913, _T_6915) @[el2_ifu_bp_ctl.scala 447:81] node _T_6917 = or(_T_6916, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6918 = bits(_T_6917, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6919 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6920 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6921 = eq(_T_6920, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40555,7 +40555,7 @@ circuit el2_swerv : node _T_6925 = and(_T_6922, _T_6924) @[el2_ifu_bp_ctl.scala 447:81] node _T_6926 = or(_T_6925, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6927 = bits(_T_6926, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6928 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6929 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6930 = eq(_T_6929, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40565,7 +40565,7 @@ circuit el2_swerv : node _T_6934 = and(_T_6931, _T_6933) @[el2_ifu_bp_ctl.scala 447:81] node _T_6935 = or(_T_6934, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6936 = bits(_T_6935, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6937 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6938 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6939 = eq(_T_6938, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40575,7 +40575,7 @@ circuit el2_swerv : node _T_6943 = and(_T_6940, _T_6942) @[el2_ifu_bp_ctl.scala 447:81] node _T_6944 = or(_T_6943, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6945 = bits(_T_6944, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6946 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6947 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6948 = eq(_T_6947, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40585,7 +40585,7 @@ circuit el2_swerv : node _T_6952 = and(_T_6949, _T_6951) @[el2_ifu_bp_ctl.scala 447:81] node _T_6953 = or(_T_6952, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6954 = bits(_T_6953, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6955 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6956 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6957 = eq(_T_6956, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40595,7 +40595,7 @@ circuit el2_swerv : node _T_6961 = and(_T_6958, _T_6960) @[el2_ifu_bp_ctl.scala 447:81] node _T_6962 = or(_T_6961, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6963 = bits(_T_6962, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6964 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6965 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6966 = eq(_T_6965, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40605,7 +40605,7 @@ circuit el2_swerv : node _T_6970 = and(_T_6967, _T_6969) @[el2_ifu_bp_ctl.scala 447:81] node _T_6971 = or(_T_6970, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6972 = bits(_T_6971, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6973 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6974 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6975 = eq(_T_6974, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40615,7 +40615,7 @@ circuit el2_swerv : node _T_6979 = and(_T_6976, _T_6978) @[el2_ifu_bp_ctl.scala 447:81] node _T_6980 = or(_T_6979, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6981 = bits(_T_6980, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6982 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6983 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6984 = eq(_T_6983, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40625,7 +40625,7 @@ circuit el2_swerv : node _T_6988 = and(_T_6985, _T_6987) @[el2_ifu_bp_ctl.scala 447:81] node _T_6989 = or(_T_6988, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6990 = bits(_T_6989, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6991 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6992 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6993 = eq(_T_6992, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40635,7 +40635,7 @@ circuit el2_swerv : node _T_6997 = and(_T_6994, _T_6996) @[el2_ifu_bp_ctl.scala 447:81] node _T_6998 = or(_T_6997, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6999 = bits(_T_6998, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7000 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7001 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7002 = eq(_T_7001, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40645,7 +40645,7 @@ circuit el2_swerv : node _T_7006 = and(_T_7003, _T_7005) @[el2_ifu_bp_ctl.scala 447:81] node _T_7007 = or(_T_7006, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7008 = bits(_T_7007, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7009 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7010 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7011 = eq(_T_7010, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40655,7 +40655,7 @@ circuit el2_swerv : node _T_7015 = and(_T_7012, _T_7014) @[el2_ifu_bp_ctl.scala 447:81] node _T_7016 = or(_T_7015, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7017 = bits(_T_7016, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7018 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7019 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7020 = eq(_T_7019, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40665,7 +40665,7 @@ circuit el2_swerv : node _T_7024 = and(_T_7021, _T_7023) @[el2_ifu_bp_ctl.scala 447:81] node _T_7025 = or(_T_7024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7026 = bits(_T_7025, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7027 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7028 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7029 = eq(_T_7028, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40675,7 +40675,7 @@ circuit el2_swerv : node _T_7033 = and(_T_7030, _T_7032) @[el2_ifu_bp_ctl.scala 447:81] node _T_7034 = or(_T_7033, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7035 = bits(_T_7034, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7036 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7037 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7038 = eq(_T_7037, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40685,7 +40685,7 @@ circuit el2_swerv : node _T_7042 = and(_T_7039, _T_7041) @[el2_ifu_bp_ctl.scala 447:81] node _T_7043 = or(_T_7042, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7044 = bits(_T_7043, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7045 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7046 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7047 = eq(_T_7046, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40695,7 +40695,7 @@ circuit el2_swerv : node _T_7051 = and(_T_7048, _T_7050) @[el2_ifu_bp_ctl.scala 447:81] node _T_7052 = or(_T_7051, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7053 = bits(_T_7052, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7054 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7055 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7056 = eq(_T_7055, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40705,7 +40705,7 @@ circuit el2_swerv : node _T_7060 = and(_T_7057, _T_7059) @[el2_ifu_bp_ctl.scala 447:81] node _T_7061 = or(_T_7060, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7062 = bits(_T_7061, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7063 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7064 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7065 = eq(_T_7064, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40715,7 +40715,7 @@ circuit el2_swerv : node _T_7069 = and(_T_7066, _T_7068) @[el2_ifu_bp_ctl.scala 447:81] node _T_7070 = or(_T_7069, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7071 = bits(_T_7070, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7072 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7073 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7074 = eq(_T_7073, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40725,7 +40725,7 @@ circuit el2_swerv : node _T_7078 = and(_T_7075, _T_7077) @[el2_ifu_bp_ctl.scala 447:81] node _T_7079 = or(_T_7078, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7080 = bits(_T_7079, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7081 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7082 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7083 = eq(_T_7082, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40735,7 +40735,7 @@ circuit el2_swerv : node _T_7087 = and(_T_7084, _T_7086) @[el2_ifu_bp_ctl.scala 447:81] node _T_7088 = or(_T_7087, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7089 = bits(_T_7088, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7090 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7091 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7092 = eq(_T_7091, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40745,7 +40745,7 @@ circuit el2_swerv : node _T_7096 = and(_T_7093, _T_7095) @[el2_ifu_bp_ctl.scala 447:81] node _T_7097 = or(_T_7096, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7098 = bits(_T_7097, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7099 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7100 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7101 = eq(_T_7100, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40755,7 +40755,7 @@ circuit el2_swerv : node _T_7105 = and(_T_7102, _T_7104) @[el2_ifu_bp_ctl.scala 447:81] node _T_7106 = or(_T_7105, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7107 = bits(_T_7106, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7108 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7109 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7110 = eq(_T_7109, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40765,7 +40765,7 @@ circuit el2_swerv : node _T_7114 = and(_T_7111, _T_7113) @[el2_ifu_bp_ctl.scala 447:81] node _T_7115 = or(_T_7114, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7116 = bits(_T_7115, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7117 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7118 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7119 = eq(_T_7118, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40775,7 +40775,7 @@ circuit el2_swerv : node _T_7123 = and(_T_7120, _T_7122) @[el2_ifu_bp_ctl.scala 447:81] node _T_7124 = or(_T_7123, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7125 = bits(_T_7124, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7126 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7127 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7128 = eq(_T_7127, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40785,7 +40785,7 @@ circuit el2_swerv : node _T_7132 = and(_T_7129, _T_7131) @[el2_ifu_bp_ctl.scala 447:81] node _T_7133 = or(_T_7132, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7134 = bits(_T_7133, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7135 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7136 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7137 = eq(_T_7136, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40795,7 +40795,7 @@ circuit el2_swerv : node _T_7141 = and(_T_7138, _T_7140) @[el2_ifu_bp_ctl.scala 447:81] node _T_7142 = or(_T_7141, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7143 = bits(_T_7142, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7144 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7145 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7146 = eq(_T_7145, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40805,7 +40805,7 @@ circuit el2_swerv : node _T_7150 = and(_T_7147, _T_7149) @[el2_ifu_bp_ctl.scala 447:81] node _T_7151 = or(_T_7150, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7152 = bits(_T_7151, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7153 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7154 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7155 = eq(_T_7154, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40815,7 +40815,7 @@ circuit el2_swerv : node _T_7159 = and(_T_7156, _T_7158) @[el2_ifu_bp_ctl.scala 447:81] node _T_7160 = or(_T_7159, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7161 = bits(_T_7160, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7162 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7163 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7164 = eq(_T_7163, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40825,7 +40825,7 @@ circuit el2_swerv : node _T_7168 = and(_T_7165, _T_7167) @[el2_ifu_bp_ctl.scala 447:81] node _T_7169 = or(_T_7168, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7170 = bits(_T_7169, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7171 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7172 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7173 = eq(_T_7172, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40835,7 +40835,7 @@ circuit el2_swerv : node _T_7177 = and(_T_7174, _T_7176) @[el2_ifu_bp_ctl.scala 447:81] node _T_7178 = or(_T_7177, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7179 = bits(_T_7178, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7180 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7181 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7182 = eq(_T_7181, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40845,7 +40845,7 @@ circuit el2_swerv : node _T_7186 = and(_T_7183, _T_7185) @[el2_ifu_bp_ctl.scala 447:81] node _T_7187 = or(_T_7186, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7188 = bits(_T_7187, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7189 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7190 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7191 = eq(_T_7190, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40855,7 +40855,7 @@ circuit el2_swerv : node _T_7195 = and(_T_7192, _T_7194) @[el2_ifu_bp_ctl.scala 447:81] node _T_7196 = or(_T_7195, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7197 = bits(_T_7196, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7198 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7199 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7200 = eq(_T_7199, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40865,7 +40865,7 @@ circuit el2_swerv : node _T_7204 = and(_T_7201, _T_7203) @[el2_ifu_bp_ctl.scala 447:81] node _T_7205 = or(_T_7204, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7206 = bits(_T_7205, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7207 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7208 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7209 = eq(_T_7208, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40875,7 +40875,7 @@ circuit el2_swerv : node _T_7213 = and(_T_7210, _T_7212) @[el2_ifu_bp_ctl.scala 447:81] node _T_7214 = or(_T_7213, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7215 = bits(_T_7214, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7216 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7217 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7218 = eq(_T_7217, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40885,7 +40885,7 @@ circuit el2_swerv : node _T_7222 = and(_T_7219, _T_7221) @[el2_ifu_bp_ctl.scala 447:81] node _T_7223 = or(_T_7222, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7224 = bits(_T_7223, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7225 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7226 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7227 = eq(_T_7226, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40895,7 +40895,7 @@ circuit el2_swerv : node _T_7231 = and(_T_7228, _T_7230) @[el2_ifu_bp_ctl.scala 447:81] node _T_7232 = or(_T_7231, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7233 = bits(_T_7232, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7234 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7235 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7236 = eq(_T_7235, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40905,7 +40905,7 @@ circuit el2_swerv : node _T_7240 = and(_T_7237, _T_7239) @[el2_ifu_bp_ctl.scala 447:81] node _T_7241 = or(_T_7240, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7242 = bits(_T_7241, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7243 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7244 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7245 = eq(_T_7244, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40915,7 +40915,7 @@ circuit el2_swerv : node _T_7249 = and(_T_7246, _T_7248) @[el2_ifu_bp_ctl.scala 447:81] node _T_7250 = or(_T_7249, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7251 = bits(_T_7250, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7252 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7253 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7254 = eq(_T_7253, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40925,7 +40925,7 @@ circuit el2_swerv : node _T_7258 = and(_T_7255, _T_7257) @[el2_ifu_bp_ctl.scala 447:81] node _T_7259 = or(_T_7258, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7260 = bits(_T_7259, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7261 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7262 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7263 = eq(_T_7262, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40935,7 +40935,7 @@ circuit el2_swerv : node _T_7267 = and(_T_7264, _T_7266) @[el2_ifu_bp_ctl.scala 447:81] node _T_7268 = or(_T_7267, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7269 = bits(_T_7268, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7270 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7271 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7272 = eq(_T_7271, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40945,7 +40945,7 @@ circuit el2_swerv : node _T_7276 = and(_T_7273, _T_7275) @[el2_ifu_bp_ctl.scala 447:81] node _T_7277 = or(_T_7276, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7278 = bits(_T_7277, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7279 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7280 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7281 = eq(_T_7280, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40955,7 +40955,7 @@ circuit el2_swerv : node _T_7285 = and(_T_7282, _T_7284) @[el2_ifu_bp_ctl.scala 447:81] node _T_7286 = or(_T_7285, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7287 = bits(_T_7286, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7288 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7289 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7290 = eq(_T_7289, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40965,7 +40965,7 @@ circuit el2_swerv : node _T_7294 = and(_T_7291, _T_7293) @[el2_ifu_bp_ctl.scala 447:81] node _T_7295 = or(_T_7294, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7296 = bits(_T_7295, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7297 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7298 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7299 = eq(_T_7298, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40975,7 +40975,7 @@ circuit el2_swerv : node _T_7303 = and(_T_7300, _T_7302) @[el2_ifu_bp_ctl.scala 447:81] node _T_7304 = or(_T_7303, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7305 = bits(_T_7304, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7306 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7307 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7308 = eq(_T_7307, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40985,7 +40985,7 @@ circuit el2_swerv : node _T_7312 = and(_T_7309, _T_7311) @[el2_ifu_bp_ctl.scala 447:81] node _T_7313 = or(_T_7312, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7314 = bits(_T_7313, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7315 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7316 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7317 = eq(_T_7316, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40995,7 +40995,7 @@ circuit el2_swerv : node _T_7321 = and(_T_7318, _T_7320) @[el2_ifu_bp_ctl.scala 447:81] node _T_7322 = or(_T_7321, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7323 = bits(_T_7322, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7324 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7325 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7326 = eq(_T_7325, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41005,7 +41005,7 @@ circuit el2_swerv : node _T_7330 = and(_T_7327, _T_7329) @[el2_ifu_bp_ctl.scala 447:81] node _T_7331 = or(_T_7330, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7332 = bits(_T_7331, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7333 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7334 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7335 = eq(_T_7334, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41015,7 +41015,7 @@ circuit el2_swerv : node _T_7339 = and(_T_7336, _T_7338) @[el2_ifu_bp_ctl.scala 447:81] node _T_7340 = or(_T_7339, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7341 = bits(_T_7340, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7342 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7343 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7344 = eq(_T_7343, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41025,7 +41025,7 @@ circuit el2_swerv : node _T_7348 = and(_T_7345, _T_7347) @[el2_ifu_bp_ctl.scala 447:81] node _T_7349 = or(_T_7348, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7350 = bits(_T_7349, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7351 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7352 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7353 = eq(_T_7352, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41035,7 +41035,7 @@ circuit el2_swerv : node _T_7357 = and(_T_7354, _T_7356) @[el2_ifu_bp_ctl.scala 447:81] node _T_7358 = or(_T_7357, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7359 = bits(_T_7358, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7360 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7361 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7362 = eq(_T_7361, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41045,7 +41045,7 @@ circuit el2_swerv : node _T_7366 = and(_T_7363, _T_7365) @[el2_ifu_bp_ctl.scala 447:81] node _T_7367 = or(_T_7366, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7368 = bits(_T_7367, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7369 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7370 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7371 = eq(_T_7370, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41055,7 +41055,7 @@ circuit el2_swerv : node _T_7375 = and(_T_7372, _T_7374) @[el2_ifu_bp_ctl.scala 447:81] node _T_7376 = or(_T_7375, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7377 = bits(_T_7376, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7378 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7379 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7380 = eq(_T_7379, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41065,7 +41065,7 @@ circuit el2_swerv : node _T_7384 = and(_T_7381, _T_7383) @[el2_ifu_bp_ctl.scala 447:81] node _T_7385 = or(_T_7384, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7386 = bits(_T_7385, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7387 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7388 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7389 = eq(_T_7388, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41075,7 +41075,7 @@ circuit el2_swerv : node _T_7393 = and(_T_7390, _T_7392) @[el2_ifu_bp_ctl.scala 447:81] node _T_7394 = or(_T_7393, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7395 = bits(_T_7394, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7396 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7397 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7398 = eq(_T_7397, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41085,7 +41085,7 @@ circuit el2_swerv : node _T_7402 = and(_T_7399, _T_7401) @[el2_ifu_bp_ctl.scala 447:81] node _T_7403 = or(_T_7402, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7404 = bits(_T_7403, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7405 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7406 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7407 = eq(_T_7406, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41095,7 +41095,7 @@ circuit el2_swerv : node _T_7411 = and(_T_7408, _T_7410) @[el2_ifu_bp_ctl.scala 447:81] node _T_7412 = or(_T_7411, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7413 = bits(_T_7412, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7414 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7415 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7416 = eq(_T_7415, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41105,7 +41105,7 @@ circuit el2_swerv : node _T_7420 = and(_T_7417, _T_7419) @[el2_ifu_bp_ctl.scala 447:81] node _T_7421 = or(_T_7420, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7422 = bits(_T_7421, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7423 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7424 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7425 = eq(_T_7424, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41115,7 +41115,7 @@ circuit el2_swerv : node _T_7429 = and(_T_7426, _T_7428) @[el2_ifu_bp_ctl.scala 447:81] node _T_7430 = or(_T_7429, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7431 = bits(_T_7430, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7432 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7433 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7434 = eq(_T_7433, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41125,7 +41125,7 @@ circuit el2_swerv : node _T_7438 = and(_T_7435, _T_7437) @[el2_ifu_bp_ctl.scala 447:81] node _T_7439 = or(_T_7438, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7440 = bits(_T_7439, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7441 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7442 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7443 = eq(_T_7442, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41135,7 +41135,7 @@ circuit el2_swerv : node _T_7447 = and(_T_7444, _T_7446) @[el2_ifu_bp_ctl.scala 447:81] node _T_7448 = or(_T_7447, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7449 = bits(_T_7448, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7450 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7451 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7452 = eq(_T_7451, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41145,7 +41145,7 @@ circuit el2_swerv : node _T_7456 = and(_T_7453, _T_7455) @[el2_ifu_bp_ctl.scala 447:81] node _T_7457 = or(_T_7456, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7458 = bits(_T_7457, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7459 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7460 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7461 = eq(_T_7460, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41155,7 +41155,7 @@ circuit el2_swerv : node _T_7465 = and(_T_7462, _T_7464) @[el2_ifu_bp_ctl.scala 447:81] node _T_7466 = or(_T_7465, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7467 = bits(_T_7466, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7468 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7469 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7470 = eq(_T_7469, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41165,7 +41165,7 @@ circuit el2_swerv : node _T_7474 = and(_T_7471, _T_7473) @[el2_ifu_bp_ctl.scala 447:81] node _T_7475 = or(_T_7474, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7476 = bits(_T_7475, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7477 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7478 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7479 = eq(_T_7478, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41175,7 +41175,7 @@ circuit el2_swerv : node _T_7483 = and(_T_7480, _T_7482) @[el2_ifu_bp_ctl.scala 447:81] node _T_7484 = or(_T_7483, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7485 = bits(_T_7484, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7486 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7487 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7488 = eq(_T_7487, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41185,7 +41185,7 @@ circuit el2_swerv : node _T_7492 = and(_T_7489, _T_7491) @[el2_ifu_bp_ctl.scala 447:81] node _T_7493 = or(_T_7492, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7494 = bits(_T_7493, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7495 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7496 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7497 = eq(_T_7496, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41195,7 +41195,7 @@ circuit el2_swerv : node _T_7501 = and(_T_7498, _T_7500) @[el2_ifu_bp_ctl.scala 447:81] node _T_7502 = or(_T_7501, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7503 = bits(_T_7502, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7504 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7505 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7506 = eq(_T_7505, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41205,7 +41205,7 @@ circuit el2_swerv : node _T_7510 = and(_T_7507, _T_7509) @[el2_ifu_bp_ctl.scala 447:81] node _T_7511 = or(_T_7510, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7512 = bits(_T_7511, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7513 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7514 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7515 = eq(_T_7514, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41215,7 +41215,7 @@ circuit el2_swerv : node _T_7519 = and(_T_7516, _T_7518) @[el2_ifu_bp_ctl.scala 447:81] node _T_7520 = or(_T_7519, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7521 = bits(_T_7520, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7522 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7523 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7524 = eq(_T_7523, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41225,7 +41225,7 @@ circuit el2_swerv : node _T_7528 = and(_T_7525, _T_7527) @[el2_ifu_bp_ctl.scala 447:81] node _T_7529 = or(_T_7528, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7530 = bits(_T_7529, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7531 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7532 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7533 = eq(_T_7532, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41235,7 +41235,7 @@ circuit el2_swerv : node _T_7537 = and(_T_7534, _T_7536) @[el2_ifu_bp_ctl.scala 447:81] node _T_7538 = or(_T_7537, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7539 = bits(_T_7538, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7540 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7541 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7542 = eq(_T_7541, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41245,7 +41245,7 @@ circuit el2_swerv : node _T_7546 = and(_T_7543, _T_7545) @[el2_ifu_bp_ctl.scala 447:81] node _T_7547 = or(_T_7546, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7548 = bits(_T_7547, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7549 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7550 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7551 = eq(_T_7550, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41255,7 +41255,7 @@ circuit el2_swerv : node _T_7555 = and(_T_7552, _T_7554) @[el2_ifu_bp_ctl.scala 447:81] node _T_7556 = or(_T_7555, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7557 = bits(_T_7556, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7558 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7559 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7560 = eq(_T_7559, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41265,7 +41265,7 @@ circuit el2_swerv : node _T_7564 = and(_T_7561, _T_7563) @[el2_ifu_bp_ctl.scala 447:81] node _T_7565 = or(_T_7564, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7566 = bits(_T_7565, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7567 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7568 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7569 = eq(_T_7568, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41275,7 +41275,7 @@ circuit el2_swerv : node _T_7573 = and(_T_7570, _T_7572) @[el2_ifu_bp_ctl.scala 447:81] node _T_7574 = or(_T_7573, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7575 = bits(_T_7574, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7576 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7577 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7578 = eq(_T_7577, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41285,7 +41285,7 @@ circuit el2_swerv : node _T_7582 = and(_T_7579, _T_7581) @[el2_ifu_bp_ctl.scala 447:81] node _T_7583 = or(_T_7582, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7584 = bits(_T_7583, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7585 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7586 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7587 = eq(_T_7586, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41295,7 +41295,7 @@ circuit el2_swerv : node _T_7591 = and(_T_7588, _T_7590) @[el2_ifu_bp_ctl.scala 447:81] node _T_7592 = or(_T_7591, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7593 = bits(_T_7592, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7594 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7595 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7596 = eq(_T_7595, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41305,7 +41305,7 @@ circuit el2_swerv : node _T_7600 = and(_T_7597, _T_7599) @[el2_ifu_bp_ctl.scala 447:81] node _T_7601 = or(_T_7600, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7602 = bits(_T_7601, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7603 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7604 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7605 = eq(_T_7604, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41315,7 +41315,7 @@ circuit el2_swerv : node _T_7609 = and(_T_7606, _T_7608) @[el2_ifu_bp_ctl.scala 447:81] node _T_7610 = or(_T_7609, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7611 = bits(_T_7610, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7612 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7613 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7614 = eq(_T_7613, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41325,7 +41325,7 @@ circuit el2_swerv : node _T_7618 = and(_T_7615, _T_7617) @[el2_ifu_bp_ctl.scala 447:81] node _T_7619 = or(_T_7618, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7620 = bits(_T_7619, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7621 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7622 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7623 = eq(_T_7622, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41335,7 +41335,7 @@ circuit el2_swerv : node _T_7627 = and(_T_7624, _T_7626) @[el2_ifu_bp_ctl.scala 447:81] node _T_7628 = or(_T_7627, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7629 = bits(_T_7628, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7630 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7631 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7632 = eq(_T_7631, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41345,7 +41345,7 @@ circuit el2_swerv : node _T_7636 = and(_T_7633, _T_7635) @[el2_ifu_bp_ctl.scala 447:81] node _T_7637 = or(_T_7636, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7638 = bits(_T_7637, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7639 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7640 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7641 = eq(_T_7640, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41355,7 +41355,7 @@ circuit el2_swerv : node _T_7645 = and(_T_7642, _T_7644) @[el2_ifu_bp_ctl.scala 447:81] node _T_7646 = or(_T_7645, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7647 = bits(_T_7646, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7648 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7649 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7650 = eq(_T_7649, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41365,7 +41365,7 @@ circuit el2_swerv : node _T_7654 = and(_T_7651, _T_7653) @[el2_ifu_bp_ctl.scala 447:81] node _T_7655 = or(_T_7654, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7656 = bits(_T_7655, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7657 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7658 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7659 = eq(_T_7658, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41375,7 +41375,7 @@ circuit el2_swerv : node _T_7663 = and(_T_7660, _T_7662) @[el2_ifu_bp_ctl.scala 447:81] node _T_7664 = or(_T_7663, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7665 = bits(_T_7664, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7666 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7667 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7668 = eq(_T_7667, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41385,7 +41385,7 @@ circuit el2_swerv : node _T_7672 = and(_T_7669, _T_7671) @[el2_ifu_bp_ctl.scala 447:81] node _T_7673 = or(_T_7672, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7674 = bits(_T_7673, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7675 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7676 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7677 = eq(_T_7676, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41395,7 +41395,7 @@ circuit el2_swerv : node _T_7681 = and(_T_7678, _T_7680) @[el2_ifu_bp_ctl.scala 447:81] node _T_7682 = or(_T_7681, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7683 = bits(_T_7682, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7684 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7685 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7686 = eq(_T_7685, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41405,7 +41405,7 @@ circuit el2_swerv : node _T_7690 = and(_T_7687, _T_7689) @[el2_ifu_bp_ctl.scala 447:81] node _T_7691 = or(_T_7690, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7692 = bits(_T_7691, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7693 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7694 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7695 = eq(_T_7694, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41415,7 +41415,7 @@ circuit el2_swerv : node _T_7699 = and(_T_7696, _T_7698) @[el2_ifu_bp_ctl.scala 447:81] node _T_7700 = or(_T_7699, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7701 = bits(_T_7700, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7702 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7703 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7704 = eq(_T_7703, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41425,7 +41425,7 @@ circuit el2_swerv : node _T_7708 = and(_T_7705, _T_7707) @[el2_ifu_bp_ctl.scala 447:81] node _T_7709 = or(_T_7708, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7710 = bits(_T_7709, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7711 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7712 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7713 = eq(_T_7712, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41435,7 +41435,7 @@ circuit el2_swerv : node _T_7717 = and(_T_7714, _T_7716) @[el2_ifu_bp_ctl.scala 447:81] node _T_7718 = or(_T_7717, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7719 = bits(_T_7718, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7720 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7721 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7722 = eq(_T_7721, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41445,7 +41445,7 @@ circuit el2_swerv : node _T_7726 = and(_T_7723, _T_7725) @[el2_ifu_bp_ctl.scala 447:81] node _T_7727 = or(_T_7726, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7728 = bits(_T_7727, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7729 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7730 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7731 = eq(_T_7730, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41455,7 +41455,7 @@ circuit el2_swerv : node _T_7735 = and(_T_7732, _T_7734) @[el2_ifu_bp_ctl.scala 447:81] node _T_7736 = or(_T_7735, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7737 = bits(_T_7736, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7738 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7739 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7740 = eq(_T_7739, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41465,7 +41465,7 @@ circuit el2_swerv : node _T_7744 = and(_T_7741, _T_7743) @[el2_ifu_bp_ctl.scala 447:81] node _T_7745 = or(_T_7744, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7746 = bits(_T_7745, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7747 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7748 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7749 = eq(_T_7748, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41475,7 +41475,7 @@ circuit el2_swerv : node _T_7753 = and(_T_7750, _T_7752) @[el2_ifu_bp_ctl.scala 447:81] node _T_7754 = or(_T_7753, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7755 = bits(_T_7754, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7756 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7757 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7758 = eq(_T_7757, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41485,7 +41485,7 @@ circuit el2_swerv : node _T_7762 = and(_T_7759, _T_7761) @[el2_ifu_bp_ctl.scala 447:81] node _T_7763 = or(_T_7762, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7764 = bits(_T_7763, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7765 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7766 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7767 = eq(_T_7766, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41495,7 +41495,7 @@ circuit el2_swerv : node _T_7771 = and(_T_7768, _T_7770) @[el2_ifu_bp_ctl.scala 447:81] node _T_7772 = or(_T_7771, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7773 = bits(_T_7772, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7774 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7775 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7776 = eq(_T_7775, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41505,7 +41505,7 @@ circuit el2_swerv : node _T_7780 = and(_T_7777, _T_7779) @[el2_ifu_bp_ctl.scala 447:81] node _T_7781 = or(_T_7780, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7782 = bits(_T_7781, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7783 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7784 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7785 = eq(_T_7784, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41515,7 +41515,7 @@ circuit el2_swerv : node _T_7789 = and(_T_7786, _T_7788) @[el2_ifu_bp_ctl.scala 447:81] node _T_7790 = or(_T_7789, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7791 = bits(_T_7790, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7792 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7793 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7794 = eq(_T_7793, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41525,7 +41525,7 @@ circuit el2_swerv : node _T_7798 = and(_T_7795, _T_7797) @[el2_ifu_bp_ctl.scala 447:81] node _T_7799 = or(_T_7798, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7800 = bits(_T_7799, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7801 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7802 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7803 = eq(_T_7802, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41535,7 +41535,7 @@ circuit el2_swerv : node _T_7807 = and(_T_7804, _T_7806) @[el2_ifu_bp_ctl.scala 447:81] node _T_7808 = or(_T_7807, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7809 = bits(_T_7808, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7810 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7811 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7812 = eq(_T_7811, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41545,7 +41545,7 @@ circuit el2_swerv : node _T_7816 = and(_T_7813, _T_7815) @[el2_ifu_bp_ctl.scala 447:81] node _T_7817 = or(_T_7816, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7818 = bits(_T_7817, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7819 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7820 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7821 = eq(_T_7820, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41555,7 +41555,7 @@ circuit el2_swerv : node _T_7825 = and(_T_7822, _T_7824) @[el2_ifu_bp_ctl.scala 447:81] node _T_7826 = or(_T_7825, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7827 = bits(_T_7826, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7828 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7829 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7830 = eq(_T_7829, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41565,7 +41565,7 @@ circuit el2_swerv : node _T_7834 = and(_T_7831, _T_7833) @[el2_ifu_bp_ctl.scala 447:81] node _T_7835 = or(_T_7834, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7836 = bits(_T_7835, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7837 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7838 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7839 = eq(_T_7838, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41575,7 +41575,7 @@ circuit el2_swerv : node _T_7843 = and(_T_7840, _T_7842) @[el2_ifu_bp_ctl.scala 447:81] node _T_7844 = or(_T_7843, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7845 = bits(_T_7844, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7846 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7847 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7848 = eq(_T_7847, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41585,7 +41585,7 @@ circuit el2_swerv : node _T_7852 = and(_T_7849, _T_7851) @[el2_ifu_bp_ctl.scala 447:81] node _T_7853 = or(_T_7852, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7854 = bits(_T_7853, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7855 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7856 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7857 = eq(_T_7856, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41595,7 +41595,7 @@ circuit el2_swerv : node _T_7861 = and(_T_7858, _T_7860) @[el2_ifu_bp_ctl.scala 447:81] node _T_7862 = or(_T_7861, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7863 = bits(_T_7862, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7864 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7865 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7866 = eq(_T_7865, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41605,7 +41605,7 @@ circuit el2_swerv : node _T_7870 = and(_T_7867, _T_7869) @[el2_ifu_bp_ctl.scala 447:81] node _T_7871 = or(_T_7870, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7872 = bits(_T_7871, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7873 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7874 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7875 = eq(_T_7874, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41615,7 +41615,7 @@ circuit el2_swerv : node _T_7879 = and(_T_7876, _T_7878) @[el2_ifu_bp_ctl.scala 447:81] node _T_7880 = or(_T_7879, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7881 = bits(_T_7880, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7882 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7883 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7884 = eq(_T_7883, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41625,7 +41625,7 @@ circuit el2_swerv : node _T_7888 = and(_T_7885, _T_7887) @[el2_ifu_bp_ctl.scala 447:81] node _T_7889 = or(_T_7888, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7890 = bits(_T_7889, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7891 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7892 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7893 = eq(_T_7892, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41635,7 +41635,7 @@ circuit el2_swerv : node _T_7897 = and(_T_7894, _T_7896) @[el2_ifu_bp_ctl.scala 447:81] node _T_7898 = or(_T_7897, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7899 = bits(_T_7898, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7900 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7901 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7902 = eq(_T_7901, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41645,7 +41645,7 @@ circuit el2_swerv : node _T_7906 = and(_T_7903, _T_7905) @[el2_ifu_bp_ctl.scala 447:81] node _T_7907 = or(_T_7906, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7908 = bits(_T_7907, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7909 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7910 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7911 = eq(_T_7910, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41655,7 +41655,7 @@ circuit el2_swerv : node _T_7915 = and(_T_7912, _T_7914) @[el2_ifu_bp_ctl.scala 447:81] node _T_7916 = or(_T_7915, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7917 = bits(_T_7916, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7918 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7919 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7920 = eq(_T_7919, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41665,7 +41665,7 @@ circuit el2_swerv : node _T_7924 = and(_T_7921, _T_7923) @[el2_ifu_bp_ctl.scala 447:81] node _T_7925 = or(_T_7924, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7926 = bits(_T_7925, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7927 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7928 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7929 = eq(_T_7928, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41675,7 +41675,7 @@ circuit el2_swerv : node _T_7933 = and(_T_7930, _T_7932) @[el2_ifu_bp_ctl.scala 447:81] node _T_7934 = or(_T_7933, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7935 = bits(_T_7934, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7936 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7937 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7938 = eq(_T_7937, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41685,7 +41685,7 @@ circuit el2_swerv : node _T_7942 = and(_T_7939, _T_7941) @[el2_ifu_bp_ctl.scala 447:81] node _T_7943 = or(_T_7942, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7944 = bits(_T_7943, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7945 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7946 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7947 = eq(_T_7946, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41695,7 +41695,7 @@ circuit el2_swerv : node _T_7951 = and(_T_7948, _T_7950) @[el2_ifu_bp_ctl.scala 447:81] node _T_7952 = or(_T_7951, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7953 = bits(_T_7952, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7954 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7955 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7956 = eq(_T_7955, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41705,7 +41705,7 @@ circuit el2_swerv : node _T_7960 = and(_T_7957, _T_7959) @[el2_ifu_bp_ctl.scala 447:81] node _T_7961 = or(_T_7960, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7962 = bits(_T_7961, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7963 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7964 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7965 = eq(_T_7964, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41715,7 +41715,7 @@ circuit el2_swerv : node _T_7969 = and(_T_7966, _T_7968) @[el2_ifu_bp_ctl.scala 447:81] node _T_7970 = or(_T_7969, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7971 = bits(_T_7970, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7972 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7973 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7974 = eq(_T_7973, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41725,7 +41725,7 @@ circuit el2_swerv : node _T_7978 = and(_T_7975, _T_7977) @[el2_ifu_bp_ctl.scala 447:81] node _T_7979 = or(_T_7978, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7980 = bits(_T_7979, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7981 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7982 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7983 = eq(_T_7982, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41735,7 +41735,7 @@ circuit el2_swerv : node _T_7987 = and(_T_7984, _T_7986) @[el2_ifu_bp_ctl.scala 447:81] node _T_7988 = or(_T_7987, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7989 = bits(_T_7988, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7990 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7991 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7992 = eq(_T_7991, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41745,7 +41745,7 @@ circuit el2_swerv : node _T_7996 = and(_T_7993, _T_7995) @[el2_ifu_bp_ctl.scala 447:81] node _T_7997 = or(_T_7996, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7998 = bits(_T_7997, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7999 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8000 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8001 = eq(_T_8000, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41755,7 +41755,7 @@ circuit el2_swerv : node _T_8005 = and(_T_8002, _T_8004) @[el2_ifu_bp_ctl.scala 447:81] node _T_8006 = or(_T_8005, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8007 = bits(_T_8006, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8008 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8009 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8010 = eq(_T_8009, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41765,7 +41765,7 @@ circuit el2_swerv : node _T_8014 = and(_T_8011, _T_8013) @[el2_ifu_bp_ctl.scala 447:81] node _T_8015 = or(_T_8014, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8016 = bits(_T_8015, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8017 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8018 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8019 = eq(_T_8018, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41775,7 +41775,7 @@ circuit el2_swerv : node _T_8023 = and(_T_8020, _T_8022) @[el2_ifu_bp_ctl.scala 447:81] node _T_8024 = or(_T_8023, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8025 = bits(_T_8024, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8026 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8027 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8028 = eq(_T_8027, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41785,7 +41785,7 @@ circuit el2_swerv : node _T_8032 = and(_T_8029, _T_8031) @[el2_ifu_bp_ctl.scala 447:81] node _T_8033 = or(_T_8032, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8034 = bits(_T_8033, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8035 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8036 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8037 = eq(_T_8036, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41795,7 +41795,7 @@ circuit el2_swerv : node _T_8041 = and(_T_8038, _T_8040) @[el2_ifu_bp_ctl.scala 447:81] node _T_8042 = or(_T_8041, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8043 = bits(_T_8042, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8044 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8045 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8046 = eq(_T_8045, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41805,7 +41805,7 @@ circuit el2_swerv : node _T_8050 = and(_T_8047, _T_8049) @[el2_ifu_bp_ctl.scala 447:81] node _T_8051 = or(_T_8050, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8052 = bits(_T_8051, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8053 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8054 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8055 = eq(_T_8054, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41815,7 +41815,7 @@ circuit el2_swerv : node _T_8059 = and(_T_8056, _T_8058) @[el2_ifu_bp_ctl.scala 447:81] node _T_8060 = or(_T_8059, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8061 = bits(_T_8060, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8062 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8063 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8064 = eq(_T_8063, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41825,7 +41825,7 @@ circuit el2_swerv : node _T_8068 = and(_T_8065, _T_8067) @[el2_ifu_bp_ctl.scala 447:81] node _T_8069 = or(_T_8068, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8070 = bits(_T_8069, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8071 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8072 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8073 = eq(_T_8072, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41835,7 +41835,7 @@ circuit el2_swerv : node _T_8077 = and(_T_8074, _T_8076) @[el2_ifu_bp_ctl.scala 447:81] node _T_8078 = or(_T_8077, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8079 = bits(_T_8078, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8080 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8081 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8082 = eq(_T_8081, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41845,7 +41845,7 @@ circuit el2_swerv : node _T_8086 = and(_T_8083, _T_8085) @[el2_ifu_bp_ctl.scala 447:81] node _T_8087 = or(_T_8086, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8088 = bits(_T_8087, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8089 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8090 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8091 = eq(_T_8090, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41855,7 +41855,7 @@ circuit el2_swerv : node _T_8095 = and(_T_8092, _T_8094) @[el2_ifu_bp_ctl.scala 447:81] node _T_8096 = or(_T_8095, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8097 = bits(_T_8096, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8098 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8099 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8100 = eq(_T_8099, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41865,7 +41865,7 @@ circuit el2_swerv : node _T_8104 = and(_T_8101, _T_8103) @[el2_ifu_bp_ctl.scala 447:81] node _T_8105 = or(_T_8104, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8106 = bits(_T_8105, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8107 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8108 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8109 = eq(_T_8108, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41875,7 +41875,7 @@ circuit el2_swerv : node _T_8113 = and(_T_8110, _T_8112) @[el2_ifu_bp_ctl.scala 447:81] node _T_8114 = or(_T_8113, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8115 = bits(_T_8114, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8116 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8117 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8118 = eq(_T_8117, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41885,7 +41885,7 @@ circuit el2_swerv : node _T_8122 = and(_T_8119, _T_8121) @[el2_ifu_bp_ctl.scala 447:81] node _T_8123 = or(_T_8122, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8124 = bits(_T_8123, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8125 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8126 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8127 = eq(_T_8126, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41895,7 +41895,7 @@ circuit el2_swerv : node _T_8131 = and(_T_8128, _T_8130) @[el2_ifu_bp_ctl.scala 447:81] node _T_8132 = or(_T_8131, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8133 = bits(_T_8132, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8134 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8135 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8136 = eq(_T_8135, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41905,7 +41905,7 @@ circuit el2_swerv : node _T_8140 = and(_T_8137, _T_8139) @[el2_ifu_bp_ctl.scala 447:81] node _T_8141 = or(_T_8140, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8142 = bits(_T_8141, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8143 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8144 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8145 = eq(_T_8144, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41915,7 +41915,7 @@ circuit el2_swerv : node _T_8149 = and(_T_8146, _T_8148) @[el2_ifu_bp_ctl.scala 447:81] node _T_8150 = or(_T_8149, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8151 = bits(_T_8150, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8152 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8153 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8154 = eq(_T_8153, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41925,7 +41925,7 @@ circuit el2_swerv : node _T_8158 = and(_T_8155, _T_8157) @[el2_ifu_bp_ctl.scala 447:81] node _T_8159 = or(_T_8158, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8160 = bits(_T_8159, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8161 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8162 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8163 = eq(_T_8162, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41935,7 +41935,7 @@ circuit el2_swerv : node _T_8167 = and(_T_8164, _T_8166) @[el2_ifu_bp_ctl.scala 447:81] node _T_8168 = or(_T_8167, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8169 = bits(_T_8168, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8170 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8171 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8172 = eq(_T_8171, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41945,7 +41945,7 @@ circuit el2_swerv : node _T_8176 = and(_T_8173, _T_8175) @[el2_ifu_bp_ctl.scala 447:81] node _T_8177 = or(_T_8176, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8178 = bits(_T_8177, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8179 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8180 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8181 = eq(_T_8180, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41955,7 +41955,7 @@ circuit el2_swerv : node _T_8185 = and(_T_8182, _T_8184) @[el2_ifu_bp_ctl.scala 447:81] node _T_8186 = or(_T_8185, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8187 = bits(_T_8186, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8188 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8189 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8190 = eq(_T_8189, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41965,7 +41965,7 @@ circuit el2_swerv : node _T_8194 = and(_T_8191, _T_8193) @[el2_ifu_bp_ctl.scala 447:81] node _T_8195 = or(_T_8194, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8196 = bits(_T_8195, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8197 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8198 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8199 = eq(_T_8198, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41975,7 +41975,7 @@ circuit el2_swerv : node _T_8203 = and(_T_8200, _T_8202) @[el2_ifu_bp_ctl.scala 447:81] node _T_8204 = or(_T_8203, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8205 = bits(_T_8204, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8206 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8207 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8208 = eq(_T_8207, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41985,7 +41985,7 @@ circuit el2_swerv : node _T_8212 = and(_T_8209, _T_8211) @[el2_ifu_bp_ctl.scala 447:81] node _T_8213 = or(_T_8212, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8214 = bits(_T_8213, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8215 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8216 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8217 = eq(_T_8216, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41995,7 +41995,7 @@ circuit el2_swerv : node _T_8221 = and(_T_8218, _T_8220) @[el2_ifu_bp_ctl.scala 447:81] node _T_8222 = or(_T_8221, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8223 = bits(_T_8222, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8224 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8225 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8226 = eq(_T_8225, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42005,7 +42005,7 @@ circuit el2_swerv : node _T_8230 = and(_T_8227, _T_8229) @[el2_ifu_bp_ctl.scala 447:81] node _T_8231 = or(_T_8230, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8232 = bits(_T_8231, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8233 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8234 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8235 = eq(_T_8234, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42015,7 +42015,7 @@ circuit el2_swerv : node _T_8239 = and(_T_8236, _T_8238) @[el2_ifu_bp_ctl.scala 447:81] node _T_8240 = or(_T_8239, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8241 = bits(_T_8240, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8242 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8243 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8244 = eq(_T_8243, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42025,7 +42025,7 @@ circuit el2_swerv : node _T_8248 = and(_T_8245, _T_8247) @[el2_ifu_bp_ctl.scala 447:81] node _T_8249 = or(_T_8248, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8250 = bits(_T_8249, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8251 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8252 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8253 = eq(_T_8252, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42035,7 +42035,7 @@ circuit el2_swerv : node _T_8257 = and(_T_8254, _T_8256) @[el2_ifu_bp_ctl.scala 447:81] node _T_8258 = or(_T_8257, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8259 = bits(_T_8258, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8260 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8261 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8262 = eq(_T_8261, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42045,7 +42045,7 @@ circuit el2_swerv : node _T_8266 = and(_T_8263, _T_8265) @[el2_ifu_bp_ctl.scala 447:81] node _T_8267 = or(_T_8266, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8268 = bits(_T_8267, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8269 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8270 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8271 = eq(_T_8270, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42055,7 +42055,7 @@ circuit el2_swerv : node _T_8275 = and(_T_8272, _T_8274) @[el2_ifu_bp_ctl.scala 447:81] node _T_8276 = or(_T_8275, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8277 = bits(_T_8276, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8278 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8279 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8280 = eq(_T_8279, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42065,7 +42065,7 @@ circuit el2_swerv : node _T_8284 = and(_T_8281, _T_8283) @[el2_ifu_bp_ctl.scala 447:81] node _T_8285 = or(_T_8284, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8286 = bits(_T_8285, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8287 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8288 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8289 = eq(_T_8288, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42075,7 +42075,7 @@ circuit el2_swerv : node _T_8293 = and(_T_8290, _T_8292) @[el2_ifu_bp_ctl.scala 447:81] node _T_8294 = or(_T_8293, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8295 = bits(_T_8294, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8296 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8297 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8298 = eq(_T_8297, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42085,7 +42085,7 @@ circuit el2_swerv : node _T_8302 = and(_T_8299, _T_8301) @[el2_ifu_bp_ctl.scala 447:81] node _T_8303 = or(_T_8302, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8304 = bits(_T_8303, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8305 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8306 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8307 = eq(_T_8306, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42095,7 +42095,7 @@ circuit el2_swerv : node _T_8311 = and(_T_8308, _T_8310) @[el2_ifu_bp_ctl.scala 447:81] node _T_8312 = or(_T_8311, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8313 = bits(_T_8312, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8314 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8315 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8316 = eq(_T_8315, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42105,7 +42105,7 @@ circuit el2_swerv : node _T_8320 = and(_T_8317, _T_8319) @[el2_ifu_bp_ctl.scala 447:81] node _T_8321 = or(_T_8320, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8322 = bits(_T_8321, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8323 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8324 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8325 = eq(_T_8324, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42115,7 +42115,7 @@ circuit el2_swerv : node _T_8329 = and(_T_8326, _T_8328) @[el2_ifu_bp_ctl.scala 447:81] node _T_8330 = or(_T_8329, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8331 = bits(_T_8330, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8332 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8333 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8334 = eq(_T_8333, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42125,7 +42125,7 @@ circuit el2_swerv : node _T_8338 = and(_T_8335, _T_8337) @[el2_ifu_bp_ctl.scala 447:81] node _T_8339 = or(_T_8338, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8340 = bits(_T_8339, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8341 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8342 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8343 = eq(_T_8342, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42135,7 +42135,7 @@ circuit el2_swerv : node _T_8347 = and(_T_8344, _T_8346) @[el2_ifu_bp_ctl.scala 447:81] node _T_8348 = or(_T_8347, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8349 = bits(_T_8348, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8350 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8351 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8352 = eq(_T_8351, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42145,7 +42145,7 @@ circuit el2_swerv : node _T_8356 = and(_T_8353, _T_8355) @[el2_ifu_bp_ctl.scala 447:81] node _T_8357 = or(_T_8356, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8358 = bits(_T_8357, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8359 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8360 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8361 = eq(_T_8360, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42155,7 +42155,7 @@ circuit el2_swerv : node _T_8365 = and(_T_8362, _T_8364) @[el2_ifu_bp_ctl.scala 447:81] node _T_8366 = or(_T_8365, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8367 = bits(_T_8366, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8368 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8369 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8370 = eq(_T_8369, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42165,7 +42165,7 @@ circuit el2_swerv : node _T_8374 = and(_T_8371, _T_8373) @[el2_ifu_bp_ctl.scala 447:81] node _T_8375 = or(_T_8374, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8376 = bits(_T_8375, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8377 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8378 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8379 = eq(_T_8378, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42175,7 +42175,7 @@ circuit el2_swerv : node _T_8383 = and(_T_8380, _T_8382) @[el2_ifu_bp_ctl.scala 447:81] node _T_8384 = or(_T_8383, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8385 = bits(_T_8384, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8386 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8387 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8388 = eq(_T_8387, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42185,7 +42185,7 @@ circuit el2_swerv : node _T_8392 = and(_T_8389, _T_8391) @[el2_ifu_bp_ctl.scala 447:81] node _T_8393 = or(_T_8392, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8394 = bits(_T_8393, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8395 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8396 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8397 = eq(_T_8396, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42195,7 +42195,7 @@ circuit el2_swerv : node _T_8401 = and(_T_8398, _T_8400) @[el2_ifu_bp_ctl.scala 447:81] node _T_8402 = or(_T_8401, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8403 = bits(_T_8402, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8404 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8405 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8406 = eq(_T_8405, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42205,7 +42205,7 @@ circuit el2_swerv : node _T_8410 = and(_T_8407, _T_8409) @[el2_ifu_bp_ctl.scala 447:81] node _T_8411 = or(_T_8410, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8412 = bits(_T_8411, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8413 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8414 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8415 = eq(_T_8414, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42215,7 +42215,7 @@ circuit el2_swerv : node _T_8419 = and(_T_8416, _T_8418) @[el2_ifu_bp_ctl.scala 447:81] node _T_8420 = or(_T_8419, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8421 = bits(_T_8420, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8422 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8423 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8424 = eq(_T_8423, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42225,7 +42225,7 @@ circuit el2_swerv : node _T_8428 = and(_T_8425, _T_8427) @[el2_ifu_bp_ctl.scala 447:81] node _T_8429 = or(_T_8428, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8430 = bits(_T_8429, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8431 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8432 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8433 = eq(_T_8432, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42235,7 +42235,7 @@ circuit el2_swerv : node _T_8437 = and(_T_8434, _T_8436) @[el2_ifu_bp_ctl.scala 447:81] node _T_8438 = or(_T_8437, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8439 = bits(_T_8438, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8440 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8441 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8442 = eq(_T_8441, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42245,7 +42245,7 @@ circuit el2_swerv : node _T_8446 = and(_T_8443, _T_8445) @[el2_ifu_bp_ctl.scala 447:81] node _T_8447 = or(_T_8446, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8448 = bits(_T_8447, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8449 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8450 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8451 = eq(_T_8450, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42255,7 +42255,7 @@ circuit el2_swerv : node _T_8455 = and(_T_8452, _T_8454) @[el2_ifu_bp_ctl.scala 447:81] node _T_8456 = or(_T_8455, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8457 = bits(_T_8456, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8458 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8459 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8460 = eq(_T_8459, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42265,7 +42265,7 @@ circuit el2_swerv : node _T_8464 = and(_T_8461, _T_8463) @[el2_ifu_bp_ctl.scala 447:81] node _T_8465 = or(_T_8464, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8466 = bits(_T_8465, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8467 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8468 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8469 = eq(_T_8468, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42275,7 +42275,7 @@ circuit el2_swerv : node _T_8473 = and(_T_8470, _T_8472) @[el2_ifu_bp_ctl.scala 447:81] node _T_8474 = or(_T_8473, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8475 = bits(_T_8474, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8476 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8477 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8478 = eq(_T_8477, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42285,7 +42285,7 @@ circuit el2_swerv : node _T_8482 = and(_T_8479, _T_8481) @[el2_ifu_bp_ctl.scala 447:81] node _T_8483 = or(_T_8482, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8484 = bits(_T_8483, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8485 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8486 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8487 = eq(_T_8486, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42295,7 +42295,7 @@ circuit el2_swerv : node _T_8491 = and(_T_8488, _T_8490) @[el2_ifu_bp_ctl.scala 447:81] node _T_8492 = or(_T_8491, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8493 = bits(_T_8492, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8494 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8495 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8496 = eq(_T_8495, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42305,7 +42305,7 @@ circuit el2_swerv : node _T_8500 = and(_T_8497, _T_8499) @[el2_ifu_bp_ctl.scala 447:81] node _T_8501 = or(_T_8500, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8502 = bits(_T_8501, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8503 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8504 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8505 = eq(_T_8504, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42315,7 +42315,7 @@ circuit el2_swerv : node _T_8509 = and(_T_8506, _T_8508) @[el2_ifu_bp_ctl.scala 447:81] node _T_8510 = or(_T_8509, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8511 = bits(_T_8510, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8512 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8513 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8514 = eq(_T_8513, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42325,7 +42325,7 @@ circuit el2_swerv : node _T_8518 = and(_T_8515, _T_8517) @[el2_ifu_bp_ctl.scala 447:81] node _T_8519 = or(_T_8518, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8520 = bits(_T_8519, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8521 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8522 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8523 = eq(_T_8522, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42335,7 +42335,7 @@ circuit el2_swerv : node _T_8527 = and(_T_8524, _T_8526) @[el2_ifu_bp_ctl.scala 447:81] node _T_8528 = or(_T_8527, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8529 = bits(_T_8528, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8530 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8531 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8532 = eq(_T_8531, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42345,7 +42345,7 @@ circuit el2_swerv : node _T_8536 = and(_T_8533, _T_8535) @[el2_ifu_bp_ctl.scala 447:81] node _T_8537 = or(_T_8536, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8538 = bits(_T_8537, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8539 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8540 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8541 = eq(_T_8540, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42355,7 +42355,7 @@ circuit el2_swerv : node _T_8545 = and(_T_8542, _T_8544) @[el2_ifu_bp_ctl.scala 447:81] node _T_8546 = or(_T_8545, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8547 = bits(_T_8546, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8548 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8549 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8550 = eq(_T_8549, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42365,7 +42365,7 @@ circuit el2_swerv : node _T_8554 = and(_T_8551, _T_8553) @[el2_ifu_bp_ctl.scala 447:81] node _T_8555 = or(_T_8554, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8556 = bits(_T_8555, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8557 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8558 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8559 = eq(_T_8558, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42375,7 +42375,7 @@ circuit el2_swerv : node _T_8563 = and(_T_8560, _T_8562) @[el2_ifu_bp_ctl.scala 447:81] node _T_8564 = or(_T_8563, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8565 = bits(_T_8564, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8566 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8567 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8568 = eq(_T_8567, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42385,7 +42385,7 @@ circuit el2_swerv : node _T_8572 = and(_T_8569, _T_8571) @[el2_ifu_bp_ctl.scala 447:81] node _T_8573 = or(_T_8572, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8574 = bits(_T_8573, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8575 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8576 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8577 = eq(_T_8576, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42395,7 +42395,7 @@ circuit el2_swerv : node _T_8581 = and(_T_8578, _T_8580) @[el2_ifu_bp_ctl.scala 447:81] node _T_8582 = or(_T_8581, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8583 = bits(_T_8582, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8584 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8585 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8586 = eq(_T_8585, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42405,7 +42405,7 @@ circuit el2_swerv : node _T_8590 = and(_T_8587, _T_8589) @[el2_ifu_bp_ctl.scala 447:81] node _T_8591 = or(_T_8590, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8592 = bits(_T_8591, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8593 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8594 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8595 = eq(_T_8594, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42415,7 +42415,7 @@ circuit el2_swerv : node _T_8599 = and(_T_8596, _T_8598) @[el2_ifu_bp_ctl.scala 447:81] node _T_8600 = or(_T_8599, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8601 = bits(_T_8600, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8602 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8603 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8604 = eq(_T_8603, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42425,7 +42425,7 @@ circuit el2_swerv : node _T_8608 = and(_T_8605, _T_8607) @[el2_ifu_bp_ctl.scala 447:81] node _T_8609 = or(_T_8608, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8610 = bits(_T_8609, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8611 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8612 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8613 = eq(_T_8612, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42435,7 +42435,7 @@ circuit el2_swerv : node _T_8617 = and(_T_8614, _T_8616) @[el2_ifu_bp_ctl.scala 447:81] node _T_8618 = or(_T_8617, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8619 = bits(_T_8618, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8620 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8621 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8622 = eq(_T_8621, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42445,7 +42445,7 @@ circuit el2_swerv : node _T_8626 = and(_T_8623, _T_8625) @[el2_ifu_bp_ctl.scala 447:81] node _T_8627 = or(_T_8626, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8628 = bits(_T_8627, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8629 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8630 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8631 = eq(_T_8630, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42455,7 +42455,7 @@ circuit el2_swerv : node _T_8635 = and(_T_8632, _T_8634) @[el2_ifu_bp_ctl.scala 447:81] node _T_8636 = or(_T_8635, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8637 = bits(_T_8636, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8638 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8639 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8640 = eq(_T_8639, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42465,7 +42465,7 @@ circuit el2_swerv : node _T_8644 = and(_T_8641, _T_8643) @[el2_ifu_bp_ctl.scala 447:81] node _T_8645 = or(_T_8644, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8646 = bits(_T_8645, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8647 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8648 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8649 = eq(_T_8648, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42475,7 +42475,7 @@ circuit el2_swerv : node _T_8653 = and(_T_8650, _T_8652) @[el2_ifu_bp_ctl.scala 447:81] node _T_8654 = or(_T_8653, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8655 = bits(_T_8654, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8656 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8657 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8658 = eq(_T_8657, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42485,7 +42485,7 @@ circuit el2_swerv : node _T_8662 = and(_T_8659, _T_8661) @[el2_ifu_bp_ctl.scala 447:81] node _T_8663 = or(_T_8662, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8664 = bits(_T_8663, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8665 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8666 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8667 = eq(_T_8666, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42495,7 +42495,7 @@ circuit el2_swerv : node _T_8671 = and(_T_8668, _T_8670) @[el2_ifu_bp_ctl.scala 447:81] node _T_8672 = or(_T_8671, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8673 = bits(_T_8672, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8674 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8675 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8676 = eq(_T_8675, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42505,7 +42505,7 @@ circuit el2_swerv : node _T_8680 = and(_T_8677, _T_8679) @[el2_ifu_bp_ctl.scala 447:81] node _T_8681 = or(_T_8680, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8682 = bits(_T_8681, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8683 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8684 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8685 = eq(_T_8684, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42515,7 +42515,7 @@ circuit el2_swerv : node _T_8689 = and(_T_8686, _T_8688) @[el2_ifu_bp_ctl.scala 447:81] node _T_8690 = or(_T_8689, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8691 = bits(_T_8690, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8692 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8693 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8694 = eq(_T_8693, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42525,7 +42525,7 @@ circuit el2_swerv : node _T_8698 = and(_T_8695, _T_8697) @[el2_ifu_bp_ctl.scala 447:81] node _T_8699 = or(_T_8698, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8700 = bits(_T_8699, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8701 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8702 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8703 = eq(_T_8702, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42535,7 +42535,7 @@ circuit el2_swerv : node _T_8707 = and(_T_8704, _T_8706) @[el2_ifu_bp_ctl.scala 447:81] node _T_8708 = or(_T_8707, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8709 = bits(_T_8708, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8710 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8711 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8712 = eq(_T_8711, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42545,7 +42545,7 @@ circuit el2_swerv : node _T_8716 = and(_T_8713, _T_8715) @[el2_ifu_bp_ctl.scala 447:81] node _T_8717 = or(_T_8716, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8718 = bits(_T_8717, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8719 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8720 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8721 = eq(_T_8720, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42555,7 +42555,7 @@ circuit el2_swerv : node _T_8725 = and(_T_8722, _T_8724) @[el2_ifu_bp_ctl.scala 447:81] node _T_8726 = or(_T_8725, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8727 = bits(_T_8726, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8728 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8729 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8730 = eq(_T_8729, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42565,7 +42565,7 @@ circuit el2_swerv : node _T_8734 = and(_T_8731, _T_8733) @[el2_ifu_bp_ctl.scala 447:81] node _T_8735 = or(_T_8734, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8736 = bits(_T_8735, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8737 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8738 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8739 = eq(_T_8738, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42575,7 +42575,7 @@ circuit el2_swerv : node _T_8743 = and(_T_8740, _T_8742) @[el2_ifu_bp_ctl.scala 447:81] node _T_8744 = or(_T_8743, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8745 = bits(_T_8744, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8746 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8747 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8748 = eq(_T_8747, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42585,7 +42585,7 @@ circuit el2_swerv : node _T_8752 = and(_T_8749, _T_8751) @[el2_ifu_bp_ctl.scala 447:81] node _T_8753 = or(_T_8752, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8754 = bits(_T_8753, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8755 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8756 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8757 = eq(_T_8756, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42595,7 +42595,7 @@ circuit el2_swerv : node _T_8761 = and(_T_8758, _T_8760) @[el2_ifu_bp_ctl.scala 447:81] node _T_8762 = or(_T_8761, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8763 = bits(_T_8762, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8764 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8765 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8766 = eq(_T_8765, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42605,7 +42605,7 @@ circuit el2_swerv : node _T_8770 = and(_T_8767, _T_8769) @[el2_ifu_bp_ctl.scala 447:81] node _T_8771 = or(_T_8770, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8772 = bits(_T_8771, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8773 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8774 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8775 = eq(_T_8774, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42615,7 +42615,7 @@ circuit el2_swerv : node _T_8779 = and(_T_8776, _T_8778) @[el2_ifu_bp_ctl.scala 447:81] node _T_8780 = or(_T_8779, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8781 = bits(_T_8780, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8782 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8783 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8784 = eq(_T_8783, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42625,7 +42625,7 @@ circuit el2_swerv : node _T_8788 = and(_T_8785, _T_8787) @[el2_ifu_bp_ctl.scala 447:81] node _T_8789 = or(_T_8788, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8790 = bits(_T_8789, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8791 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8792 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8793 = eq(_T_8792, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42635,7 +42635,7 @@ circuit el2_swerv : node _T_8797 = and(_T_8794, _T_8796) @[el2_ifu_bp_ctl.scala 447:81] node _T_8798 = or(_T_8797, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8799 = bits(_T_8798, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8800 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8801 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8802 = eq(_T_8801, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42645,7 +42645,7 @@ circuit el2_swerv : node _T_8806 = and(_T_8803, _T_8805) @[el2_ifu_bp_ctl.scala 447:81] node _T_8807 = or(_T_8806, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8808 = bits(_T_8807, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8809 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8810 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8811 = eq(_T_8810, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42655,7 +42655,7 @@ circuit el2_swerv : node _T_8815 = and(_T_8812, _T_8814) @[el2_ifu_bp_ctl.scala 447:81] node _T_8816 = or(_T_8815, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8817 = bits(_T_8816, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8818 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8819 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8820 = eq(_T_8819, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42665,7 +42665,7 @@ circuit el2_swerv : node _T_8824 = and(_T_8821, _T_8823) @[el2_ifu_bp_ctl.scala 447:81] node _T_8825 = or(_T_8824, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8826 = bits(_T_8825, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8827 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8828 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8829 = eq(_T_8828, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42675,7 +42675,7 @@ circuit el2_swerv : node _T_8833 = and(_T_8830, _T_8832) @[el2_ifu_bp_ctl.scala 447:81] node _T_8834 = or(_T_8833, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8835 = bits(_T_8834, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8836 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8837 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8838 = eq(_T_8837, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42685,7 +42685,7 @@ circuit el2_swerv : node _T_8842 = and(_T_8839, _T_8841) @[el2_ifu_bp_ctl.scala 447:81] node _T_8843 = or(_T_8842, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8844 = bits(_T_8843, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8845 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8846 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8847 = eq(_T_8846, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42695,7 +42695,7 @@ circuit el2_swerv : node _T_8851 = and(_T_8848, _T_8850) @[el2_ifu_bp_ctl.scala 447:81] node _T_8852 = or(_T_8851, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8853 = bits(_T_8852, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8854 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8855 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8856 = eq(_T_8855, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42705,7 +42705,7 @@ circuit el2_swerv : node _T_8860 = and(_T_8857, _T_8859) @[el2_ifu_bp_ctl.scala 447:81] node _T_8861 = or(_T_8860, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8862 = bits(_T_8861, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8863 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8864 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8865 = eq(_T_8864, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42715,7 +42715,7 @@ circuit el2_swerv : node _T_8869 = and(_T_8866, _T_8868) @[el2_ifu_bp_ctl.scala 447:81] node _T_8870 = or(_T_8869, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8871 = bits(_T_8870, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8872 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8873 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8874 = eq(_T_8873, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42725,7 +42725,7 @@ circuit el2_swerv : node _T_8878 = and(_T_8875, _T_8877) @[el2_ifu_bp_ctl.scala 447:81] node _T_8879 = or(_T_8878, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8880 = bits(_T_8879, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8881 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8882 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8883 = eq(_T_8882, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42735,7 +42735,7 @@ circuit el2_swerv : node _T_8887 = and(_T_8884, _T_8886) @[el2_ifu_bp_ctl.scala 447:81] node _T_8888 = or(_T_8887, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8889 = bits(_T_8888, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8890 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8891 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8892 = eq(_T_8891, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42745,7 +42745,7 @@ circuit el2_swerv : node _T_8896 = and(_T_8893, _T_8895) @[el2_ifu_bp_ctl.scala 447:81] node _T_8897 = or(_T_8896, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8898 = bits(_T_8897, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8899 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8900 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8901 = eq(_T_8900, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42755,7 +42755,7 @@ circuit el2_swerv : node _T_8905 = and(_T_8902, _T_8904) @[el2_ifu_bp_ctl.scala 447:81] node _T_8906 = or(_T_8905, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8907 = bits(_T_8906, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8908 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8909 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8910 = eq(_T_8909, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42765,7 +42765,7 @@ circuit el2_swerv : node _T_8914 = and(_T_8911, _T_8913) @[el2_ifu_bp_ctl.scala 447:81] node _T_8915 = or(_T_8914, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8916 = bits(_T_8915, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8917 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8918 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8919 = eq(_T_8918, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42775,7 +42775,7 @@ circuit el2_swerv : node _T_8923 = and(_T_8920, _T_8922) @[el2_ifu_bp_ctl.scala 447:81] node _T_8924 = or(_T_8923, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8925 = bits(_T_8924, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8926 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8927 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8928 = eq(_T_8927, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42785,7 +42785,7 @@ circuit el2_swerv : node _T_8932 = and(_T_8929, _T_8931) @[el2_ifu_bp_ctl.scala 447:81] node _T_8933 = or(_T_8932, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8934 = bits(_T_8933, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8935 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8936 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8937 = eq(_T_8936, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42795,7 +42795,7 @@ circuit el2_swerv : node _T_8941 = and(_T_8938, _T_8940) @[el2_ifu_bp_ctl.scala 447:81] node _T_8942 = or(_T_8941, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8943 = bits(_T_8942, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8944 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8945 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8946 = eq(_T_8945, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42805,7 +42805,7 @@ circuit el2_swerv : node _T_8950 = and(_T_8947, _T_8949) @[el2_ifu_bp_ctl.scala 447:81] node _T_8951 = or(_T_8950, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8952 = bits(_T_8951, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8953 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8954 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8955 = eq(_T_8954, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42815,7 +42815,7 @@ circuit el2_swerv : node _T_8959 = and(_T_8956, _T_8958) @[el2_ifu_bp_ctl.scala 447:81] node _T_8960 = or(_T_8959, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8961 = bits(_T_8960, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8962 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8963 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8964 = eq(_T_8963, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42825,7 +42825,7 @@ circuit el2_swerv : node _T_8968 = and(_T_8965, _T_8967) @[el2_ifu_bp_ctl.scala 447:81] node _T_8969 = or(_T_8968, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8970 = bits(_T_8969, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8971 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8972 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8973 = eq(_T_8972, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42835,7 +42835,7 @@ circuit el2_swerv : node _T_8977 = and(_T_8974, _T_8976) @[el2_ifu_bp_ctl.scala 447:81] node _T_8978 = or(_T_8977, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8979 = bits(_T_8978, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8980 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8981 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8982 = eq(_T_8981, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42845,7 +42845,7 @@ circuit el2_swerv : node _T_8986 = and(_T_8983, _T_8985) @[el2_ifu_bp_ctl.scala 447:81] node _T_8987 = or(_T_8986, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8988 = bits(_T_8987, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8989 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8990 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8991 = eq(_T_8990, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42855,7 +42855,7 @@ circuit el2_swerv : node _T_8995 = and(_T_8992, _T_8994) @[el2_ifu_bp_ctl.scala 447:81] node _T_8996 = or(_T_8995, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8997 = bits(_T_8996, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8998 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8999 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9000 = eq(_T_8999, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42865,7 +42865,7 @@ circuit el2_swerv : node _T_9004 = and(_T_9001, _T_9003) @[el2_ifu_bp_ctl.scala 447:81] node _T_9005 = or(_T_9004, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9006 = bits(_T_9005, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9007 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9008 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9009 = eq(_T_9008, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42875,7 +42875,7 @@ circuit el2_swerv : node _T_9013 = and(_T_9010, _T_9012) @[el2_ifu_bp_ctl.scala 447:81] node _T_9014 = or(_T_9013, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9015 = bits(_T_9014, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9016 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9017 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9018 = eq(_T_9017, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42885,7 +42885,7 @@ circuit el2_swerv : node _T_9022 = and(_T_9019, _T_9021) @[el2_ifu_bp_ctl.scala 447:81] node _T_9023 = or(_T_9022, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9024 = bits(_T_9023, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9025 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9026 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9027 = eq(_T_9026, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42895,7 +42895,7 @@ circuit el2_swerv : node _T_9031 = and(_T_9028, _T_9030) @[el2_ifu_bp_ctl.scala 447:81] node _T_9032 = or(_T_9031, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9033 = bits(_T_9032, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9034 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9035 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9036 = eq(_T_9035, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42905,7 +42905,7 @@ circuit el2_swerv : node _T_9040 = and(_T_9037, _T_9039) @[el2_ifu_bp_ctl.scala 447:81] node _T_9041 = or(_T_9040, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9042 = bits(_T_9041, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9043 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9044 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9045 = eq(_T_9044, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42915,7 +42915,7 @@ circuit el2_swerv : node _T_9049 = and(_T_9046, _T_9048) @[el2_ifu_bp_ctl.scala 447:81] node _T_9050 = or(_T_9049, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9051 = bits(_T_9050, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9052 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9053 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9054 = eq(_T_9053, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42925,7 +42925,7 @@ circuit el2_swerv : node _T_9058 = and(_T_9055, _T_9057) @[el2_ifu_bp_ctl.scala 447:81] node _T_9059 = or(_T_9058, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9060 = bits(_T_9059, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9061 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9062 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9063 = eq(_T_9062, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42935,7 +42935,7 @@ circuit el2_swerv : node _T_9067 = and(_T_9064, _T_9066) @[el2_ifu_bp_ctl.scala 447:81] node _T_9068 = or(_T_9067, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9069 = bits(_T_9068, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9070 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9071 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9072 = eq(_T_9071, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42945,7 +42945,7 @@ circuit el2_swerv : node _T_9076 = and(_T_9073, _T_9075) @[el2_ifu_bp_ctl.scala 447:81] node _T_9077 = or(_T_9076, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9078 = bits(_T_9077, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9079 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9080 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9081 = eq(_T_9080, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42955,7 +42955,7 @@ circuit el2_swerv : node _T_9085 = and(_T_9082, _T_9084) @[el2_ifu_bp_ctl.scala 447:81] node _T_9086 = or(_T_9085, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9087 = bits(_T_9086, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9088 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9089 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9090 = eq(_T_9089, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42965,7 +42965,7 @@ circuit el2_swerv : node _T_9094 = and(_T_9091, _T_9093) @[el2_ifu_bp_ctl.scala 447:81] node _T_9095 = or(_T_9094, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9096 = bits(_T_9095, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9097 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9098 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9099 = eq(_T_9098, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42975,7 +42975,7 @@ circuit el2_swerv : node _T_9103 = and(_T_9100, _T_9102) @[el2_ifu_bp_ctl.scala 447:81] node _T_9104 = or(_T_9103, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9105 = bits(_T_9104, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9106 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9107 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9108 = eq(_T_9107, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42985,7 +42985,7 @@ circuit el2_swerv : node _T_9112 = and(_T_9109, _T_9111) @[el2_ifu_bp_ctl.scala 447:81] node _T_9113 = or(_T_9112, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9114 = bits(_T_9113, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9115 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9116 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9117 = eq(_T_9116, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42995,7 +42995,7 @@ circuit el2_swerv : node _T_9121 = and(_T_9118, _T_9120) @[el2_ifu_bp_ctl.scala 447:81] node _T_9122 = or(_T_9121, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9123 = bits(_T_9122, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9124 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9125 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9126 = eq(_T_9125, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43005,7 +43005,7 @@ circuit el2_swerv : node _T_9130 = and(_T_9127, _T_9129) @[el2_ifu_bp_ctl.scala 447:81] node _T_9131 = or(_T_9130, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9132 = bits(_T_9131, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9133 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9134 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9135 = eq(_T_9134, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43015,7 +43015,7 @@ circuit el2_swerv : node _T_9139 = and(_T_9136, _T_9138) @[el2_ifu_bp_ctl.scala 447:81] node _T_9140 = or(_T_9139, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9141 = bits(_T_9140, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9142 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9143 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9144 = eq(_T_9143, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43025,7 +43025,7 @@ circuit el2_swerv : node _T_9148 = and(_T_9145, _T_9147) @[el2_ifu_bp_ctl.scala 447:81] node _T_9149 = or(_T_9148, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9150 = bits(_T_9149, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9151 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9152 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9153 = eq(_T_9152, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43035,7 +43035,7 @@ circuit el2_swerv : node _T_9157 = and(_T_9154, _T_9156) @[el2_ifu_bp_ctl.scala 447:81] node _T_9158 = or(_T_9157, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9159 = bits(_T_9158, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9160 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9161 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9162 = eq(_T_9161, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43045,7 +43045,7 @@ circuit el2_swerv : node _T_9166 = and(_T_9163, _T_9165) @[el2_ifu_bp_ctl.scala 447:81] node _T_9167 = or(_T_9166, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9168 = bits(_T_9167, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9169 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9170 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9171 = eq(_T_9170, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43055,7 +43055,7 @@ circuit el2_swerv : node _T_9175 = and(_T_9172, _T_9174) @[el2_ifu_bp_ctl.scala 447:81] node _T_9176 = or(_T_9175, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9177 = bits(_T_9176, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9178 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9179 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9180 = eq(_T_9179, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43065,7 +43065,7 @@ circuit el2_swerv : node _T_9184 = and(_T_9181, _T_9183) @[el2_ifu_bp_ctl.scala 447:81] node _T_9185 = or(_T_9184, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9186 = bits(_T_9185, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9187 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9188 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9189 = eq(_T_9188, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43075,7 +43075,7 @@ circuit el2_swerv : node _T_9193 = and(_T_9190, _T_9192) @[el2_ifu_bp_ctl.scala 447:81] node _T_9194 = or(_T_9193, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9195 = bits(_T_9194, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9196 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9197 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9198 = eq(_T_9197, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43085,7 +43085,7 @@ circuit el2_swerv : node _T_9202 = and(_T_9199, _T_9201) @[el2_ifu_bp_ctl.scala 447:81] node _T_9203 = or(_T_9202, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9204 = bits(_T_9203, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9205 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9206 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9207 = eq(_T_9206, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43095,7 +43095,7 @@ circuit el2_swerv : node _T_9211 = and(_T_9208, _T_9210) @[el2_ifu_bp_ctl.scala 447:81] node _T_9212 = or(_T_9211, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9213 = bits(_T_9212, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9214 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9215 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9216 = eq(_T_9215, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43105,7 +43105,7 @@ circuit el2_swerv : node _T_9220 = and(_T_9217, _T_9219) @[el2_ifu_bp_ctl.scala 447:81] node _T_9221 = or(_T_9220, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9222 = bits(_T_9221, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9223 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9224 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9225 = eq(_T_9224, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43115,7 +43115,7 @@ circuit el2_swerv : node _T_9229 = and(_T_9226, _T_9228) @[el2_ifu_bp_ctl.scala 447:81] node _T_9230 = or(_T_9229, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9231 = bits(_T_9230, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9232 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9233 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9234 = eq(_T_9233, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43125,7 +43125,7 @@ circuit el2_swerv : node _T_9238 = and(_T_9235, _T_9237) @[el2_ifu_bp_ctl.scala 447:81] node _T_9239 = or(_T_9238, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9240 = bits(_T_9239, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9241 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9242 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9243 = eq(_T_9242, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43135,7 +43135,7 @@ circuit el2_swerv : node _T_9247 = and(_T_9244, _T_9246) @[el2_ifu_bp_ctl.scala 447:81] node _T_9248 = or(_T_9247, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9249 = bits(_T_9248, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9250 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9251 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9252 = eq(_T_9251, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43145,7 +43145,7 @@ circuit el2_swerv : node _T_9256 = and(_T_9253, _T_9255) @[el2_ifu_bp_ctl.scala 447:81] node _T_9257 = or(_T_9256, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9258 = bits(_T_9257, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9259 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9260 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9261 = eq(_T_9260, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43155,7 +43155,7 @@ circuit el2_swerv : node _T_9265 = and(_T_9262, _T_9264) @[el2_ifu_bp_ctl.scala 447:81] node _T_9266 = or(_T_9265, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9267 = bits(_T_9266, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9268 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9269 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9270 = eq(_T_9269, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43165,7 +43165,7 @@ circuit el2_swerv : node _T_9274 = and(_T_9271, _T_9273) @[el2_ifu_bp_ctl.scala 447:81] node _T_9275 = or(_T_9274, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9276 = bits(_T_9275, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9277 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9278 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9279 = eq(_T_9278, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43175,7 +43175,7 @@ circuit el2_swerv : node _T_9283 = and(_T_9280, _T_9282) @[el2_ifu_bp_ctl.scala 447:81] node _T_9284 = or(_T_9283, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9285 = bits(_T_9284, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9286 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9287 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9288 = eq(_T_9287, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43185,7 +43185,7 @@ circuit el2_swerv : node _T_9292 = and(_T_9289, _T_9291) @[el2_ifu_bp_ctl.scala 447:81] node _T_9293 = or(_T_9292, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9294 = bits(_T_9293, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9295 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9296 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9297 = eq(_T_9296, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43195,7 +43195,7 @@ circuit el2_swerv : node _T_9301 = and(_T_9298, _T_9300) @[el2_ifu_bp_ctl.scala 447:81] node _T_9302 = or(_T_9301, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9303 = bits(_T_9302, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9304 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9305 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9306 = eq(_T_9305, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43205,7 +43205,7 @@ circuit el2_swerv : node _T_9310 = and(_T_9307, _T_9309) @[el2_ifu_bp_ctl.scala 447:81] node _T_9311 = or(_T_9310, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9312 = bits(_T_9311, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9313 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9314 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9315 = eq(_T_9314, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43215,7 +43215,7 @@ circuit el2_swerv : node _T_9319 = and(_T_9316, _T_9318) @[el2_ifu_bp_ctl.scala 447:81] node _T_9320 = or(_T_9319, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9321 = bits(_T_9320, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9322 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9323 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9324 = eq(_T_9323, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43225,7 +43225,7 @@ circuit el2_swerv : node _T_9328 = and(_T_9325, _T_9327) @[el2_ifu_bp_ctl.scala 447:81] node _T_9329 = or(_T_9328, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9330 = bits(_T_9329, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9331 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9332 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9333 = eq(_T_9332, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43235,7 +43235,7 @@ circuit el2_swerv : node _T_9337 = and(_T_9334, _T_9336) @[el2_ifu_bp_ctl.scala 447:81] node _T_9338 = or(_T_9337, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9339 = bits(_T_9338, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9340 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9341 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9342 = eq(_T_9341, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43245,7 +43245,7 @@ circuit el2_swerv : node _T_9346 = and(_T_9343, _T_9345) @[el2_ifu_bp_ctl.scala 447:81] node _T_9347 = or(_T_9346, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9348 = bits(_T_9347, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9349 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9350 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9351 = eq(_T_9350, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43255,7 +43255,7 @@ circuit el2_swerv : node _T_9355 = and(_T_9352, _T_9354) @[el2_ifu_bp_ctl.scala 447:81] node _T_9356 = or(_T_9355, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9357 = bits(_T_9356, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9358 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9359 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9360 = eq(_T_9359, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43265,7 +43265,7 @@ circuit el2_swerv : node _T_9364 = and(_T_9361, _T_9363) @[el2_ifu_bp_ctl.scala 447:81] node _T_9365 = or(_T_9364, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9366 = bits(_T_9365, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9367 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9368 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9369 = eq(_T_9368, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43275,7 +43275,7 @@ circuit el2_swerv : node _T_9373 = and(_T_9370, _T_9372) @[el2_ifu_bp_ctl.scala 447:81] node _T_9374 = or(_T_9373, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9375 = bits(_T_9374, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9376 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9377 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9378 = eq(_T_9377, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43285,7 +43285,7 @@ circuit el2_swerv : node _T_9382 = and(_T_9379, _T_9381) @[el2_ifu_bp_ctl.scala 447:81] node _T_9383 = or(_T_9382, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9384 = bits(_T_9383, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9385 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9386 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9387 = eq(_T_9386, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43295,7 +43295,7 @@ circuit el2_swerv : node _T_9391 = and(_T_9388, _T_9390) @[el2_ifu_bp_ctl.scala 447:81] node _T_9392 = or(_T_9391, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9393 = bits(_T_9392, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9394 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9395 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9396 = eq(_T_9395, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43305,7 +43305,7 @@ circuit el2_swerv : node _T_9400 = and(_T_9397, _T_9399) @[el2_ifu_bp_ctl.scala 447:81] node _T_9401 = or(_T_9400, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9402 = bits(_T_9401, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9403 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9404 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9405 = eq(_T_9404, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43315,7 +43315,7 @@ circuit el2_swerv : node _T_9409 = and(_T_9406, _T_9408) @[el2_ifu_bp_ctl.scala 447:81] node _T_9410 = or(_T_9409, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9411 = bits(_T_9410, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9412 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9413 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9414 = eq(_T_9413, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43325,7 +43325,7 @@ circuit el2_swerv : node _T_9418 = and(_T_9415, _T_9417) @[el2_ifu_bp_ctl.scala 447:81] node _T_9419 = or(_T_9418, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9420 = bits(_T_9419, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9421 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9422 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9423 = eq(_T_9422, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43335,7 +43335,7 @@ circuit el2_swerv : node _T_9427 = and(_T_9424, _T_9426) @[el2_ifu_bp_ctl.scala 447:81] node _T_9428 = or(_T_9427, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9429 = bits(_T_9428, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9430 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9431 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9432 = eq(_T_9431, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43345,7 +43345,7 @@ circuit el2_swerv : node _T_9436 = and(_T_9433, _T_9435) @[el2_ifu_bp_ctl.scala 447:81] node _T_9437 = or(_T_9436, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9438 = bits(_T_9437, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9439 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9440 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9441 = eq(_T_9440, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43355,7 +43355,7 @@ circuit el2_swerv : node _T_9445 = and(_T_9442, _T_9444) @[el2_ifu_bp_ctl.scala 447:81] node _T_9446 = or(_T_9445, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9447 = bits(_T_9446, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9448 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9449 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9450 = eq(_T_9449, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43365,7 +43365,7 @@ circuit el2_swerv : node _T_9454 = and(_T_9451, _T_9453) @[el2_ifu_bp_ctl.scala 447:81] node _T_9455 = or(_T_9454, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9456 = bits(_T_9455, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9457 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9458 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9459 = eq(_T_9458, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43375,7 +43375,7 @@ circuit el2_swerv : node _T_9463 = and(_T_9460, _T_9462) @[el2_ifu_bp_ctl.scala 447:81] node _T_9464 = or(_T_9463, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9465 = bits(_T_9464, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9466 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9467 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9468 = eq(_T_9467, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43385,7 +43385,7 @@ circuit el2_swerv : node _T_9472 = and(_T_9469, _T_9471) @[el2_ifu_bp_ctl.scala 447:81] node _T_9473 = or(_T_9472, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9474 = bits(_T_9473, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9475 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9476 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9477 = eq(_T_9476, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43395,7 +43395,7 @@ circuit el2_swerv : node _T_9481 = and(_T_9478, _T_9480) @[el2_ifu_bp_ctl.scala 447:81] node _T_9482 = or(_T_9481, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9483 = bits(_T_9482, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9484 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9485 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9486 = eq(_T_9485, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43405,7 +43405,7 @@ circuit el2_swerv : node _T_9490 = and(_T_9487, _T_9489) @[el2_ifu_bp_ctl.scala 447:81] node _T_9491 = or(_T_9490, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9492 = bits(_T_9491, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9493 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9494 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9495 = eq(_T_9494, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43415,7 +43415,7 @@ circuit el2_swerv : node _T_9499 = and(_T_9496, _T_9498) @[el2_ifu_bp_ctl.scala 447:81] node _T_9500 = or(_T_9499, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9501 = bits(_T_9500, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9502 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9503 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9504 = eq(_T_9503, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43425,7 +43425,7 @@ circuit el2_swerv : node _T_9508 = and(_T_9505, _T_9507) @[el2_ifu_bp_ctl.scala 447:81] node _T_9509 = or(_T_9508, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9510 = bits(_T_9509, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9511 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9512 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9513 = eq(_T_9512, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43435,7 +43435,7 @@ circuit el2_swerv : node _T_9517 = and(_T_9514, _T_9516) @[el2_ifu_bp_ctl.scala 447:81] node _T_9518 = or(_T_9517, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9519 = bits(_T_9518, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9520 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9521 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9522 = eq(_T_9521, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43445,7 +43445,7 @@ circuit el2_swerv : node _T_9526 = and(_T_9523, _T_9525) @[el2_ifu_bp_ctl.scala 447:81] node _T_9527 = or(_T_9526, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9528 = bits(_T_9527, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9529 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9530 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9531 = eq(_T_9530, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43455,7 +43455,7 @@ circuit el2_swerv : node _T_9535 = and(_T_9532, _T_9534) @[el2_ifu_bp_ctl.scala 447:81] node _T_9536 = or(_T_9535, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9537 = bits(_T_9536, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9538 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9539 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9540 = eq(_T_9539, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43465,7 +43465,7 @@ circuit el2_swerv : node _T_9544 = and(_T_9541, _T_9543) @[el2_ifu_bp_ctl.scala 447:81] node _T_9545 = or(_T_9544, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9546 = bits(_T_9545, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9547 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9548 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9549 = eq(_T_9548, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43475,7 +43475,7 @@ circuit el2_swerv : node _T_9553 = and(_T_9550, _T_9552) @[el2_ifu_bp_ctl.scala 447:81] node _T_9554 = or(_T_9553, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9555 = bits(_T_9554, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9556 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9557 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9558 = eq(_T_9557, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43485,7 +43485,7 @@ circuit el2_swerv : node _T_9562 = and(_T_9559, _T_9561) @[el2_ifu_bp_ctl.scala 447:81] node _T_9563 = or(_T_9562, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9564 = bits(_T_9563, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9565 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9566 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9567 = eq(_T_9566, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43495,7 +43495,7 @@ circuit el2_swerv : node _T_9571 = and(_T_9568, _T_9570) @[el2_ifu_bp_ctl.scala 447:81] node _T_9572 = or(_T_9571, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9573 = bits(_T_9572, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9574 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9575 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9576 = eq(_T_9575, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43505,7 +43505,7 @@ circuit el2_swerv : node _T_9580 = and(_T_9577, _T_9579) @[el2_ifu_bp_ctl.scala 447:81] node _T_9581 = or(_T_9580, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9582 = bits(_T_9581, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9583 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9584 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9585 = eq(_T_9584, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43515,7 +43515,7 @@ circuit el2_swerv : node _T_9589 = and(_T_9586, _T_9588) @[el2_ifu_bp_ctl.scala 447:81] node _T_9590 = or(_T_9589, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9591 = bits(_T_9590, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9592 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9593 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9594 = eq(_T_9593, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43525,7 +43525,7 @@ circuit el2_swerv : node _T_9598 = and(_T_9595, _T_9597) @[el2_ifu_bp_ctl.scala 447:81] node _T_9599 = or(_T_9598, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9600 = bits(_T_9599, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9601 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9602 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9603 = eq(_T_9602, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43535,7 +43535,7 @@ circuit el2_swerv : node _T_9607 = and(_T_9604, _T_9606) @[el2_ifu_bp_ctl.scala 447:81] node _T_9608 = or(_T_9607, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9609 = bits(_T_9608, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9610 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9611 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9612 = eq(_T_9611, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43545,7 +43545,7 @@ circuit el2_swerv : node _T_9616 = and(_T_9613, _T_9615) @[el2_ifu_bp_ctl.scala 447:81] node _T_9617 = or(_T_9616, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9618 = bits(_T_9617, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9619 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9620 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9621 = eq(_T_9620, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43555,7 +43555,7 @@ circuit el2_swerv : node _T_9625 = and(_T_9622, _T_9624) @[el2_ifu_bp_ctl.scala 447:81] node _T_9626 = or(_T_9625, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9627 = bits(_T_9626, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9628 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9629 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9630 = eq(_T_9629, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43565,7 +43565,7 @@ circuit el2_swerv : node _T_9634 = and(_T_9631, _T_9633) @[el2_ifu_bp_ctl.scala 447:81] node _T_9635 = or(_T_9634, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9636 = bits(_T_9635, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9637 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9638 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9639 = eq(_T_9638, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43575,7 +43575,7 @@ circuit el2_swerv : node _T_9643 = and(_T_9640, _T_9642) @[el2_ifu_bp_ctl.scala 447:81] node _T_9644 = or(_T_9643, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9645 = bits(_T_9644, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9646 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9647 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9648 = eq(_T_9647, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43585,7 +43585,7 @@ circuit el2_swerv : node _T_9652 = and(_T_9649, _T_9651) @[el2_ifu_bp_ctl.scala 447:81] node _T_9653 = or(_T_9652, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9654 = bits(_T_9653, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9655 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9656 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9657 = eq(_T_9656, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43595,7 +43595,7 @@ circuit el2_swerv : node _T_9661 = and(_T_9658, _T_9660) @[el2_ifu_bp_ctl.scala 447:81] node _T_9662 = or(_T_9661, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9663 = bits(_T_9662, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9664 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9665 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9666 = eq(_T_9665, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43605,7 +43605,7 @@ circuit el2_swerv : node _T_9670 = and(_T_9667, _T_9669) @[el2_ifu_bp_ctl.scala 447:81] node _T_9671 = or(_T_9670, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9672 = bits(_T_9671, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9673 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9674 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9675 = eq(_T_9674, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43615,7 +43615,7 @@ circuit el2_swerv : node _T_9679 = and(_T_9676, _T_9678) @[el2_ifu_bp_ctl.scala 447:81] node _T_9680 = or(_T_9679, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9681 = bits(_T_9680, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9682 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9683 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9684 = eq(_T_9683, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43625,7 +43625,7 @@ circuit el2_swerv : node _T_9688 = and(_T_9685, _T_9687) @[el2_ifu_bp_ctl.scala 447:81] node _T_9689 = or(_T_9688, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9690 = bits(_T_9689, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9691 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9692 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9693 = eq(_T_9692, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43635,7 +43635,7 @@ circuit el2_swerv : node _T_9697 = and(_T_9694, _T_9696) @[el2_ifu_bp_ctl.scala 447:81] node _T_9698 = or(_T_9697, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9699 = bits(_T_9698, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9700 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9701 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9702 = eq(_T_9701, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43645,7 +43645,7 @@ circuit el2_swerv : node _T_9706 = and(_T_9703, _T_9705) @[el2_ifu_bp_ctl.scala 447:81] node _T_9707 = or(_T_9706, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9708 = bits(_T_9707, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9709 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9710 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9711 = eq(_T_9710, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43655,7 +43655,7 @@ circuit el2_swerv : node _T_9715 = and(_T_9712, _T_9714) @[el2_ifu_bp_ctl.scala 447:81] node _T_9716 = or(_T_9715, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9717 = bits(_T_9716, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9718 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9719 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9720 = eq(_T_9719, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43665,7 +43665,7 @@ circuit el2_swerv : node _T_9724 = and(_T_9721, _T_9723) @[el2_ifu_bp_ctl.scala 447:81] node _T_9725 = or(_T_9724, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9726 = bits(_T_9725, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9727 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9728 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9729 = eq(_T_9728, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43675,7 +43675,7 @@ circuit el2_swerv : node _T_9733 = and(_T_9730, _T_9732) @[el2_ifu_bp_ctl.scala 447:81] node _T_9734 = or(_T_9733, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9735 = bits(_T_9734, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9736 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9737 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9738 = eq(_T_9737, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43685,7 +43685,7 @@ circuit el2_swerv : node _T_9742 = and(_T_9739, _T_9741) @[el2_ifu_bp_ctl.scala 447:81] node _T_9743 = or(_T_9742, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9744 = bits(_T_9743, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9745 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9746 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9747 = eq(_T_9746, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43695,7 +43695,7 @@ circuit el2_swerv : node _T_9751 = and(_T_9748, _T_9750) @[el2_ifu_bp_ctl.scala 447:81] node _T_9752 = or(_T_9751, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9753 = bits(_T_9752, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9754 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9755 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9756 = eq(_T_9755, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43705,7 +43705,7 @@ circuit el2_swerv : node _T_9760 = and(_T_9757, _T_9759) @[el2_ifu_bp_ctl.scala 447:81] node _T_9761 = or(_T_9760, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9762 = bits(_T_9761, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9763 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9764 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9765 = eq(_T_9764, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43715,7 +43715,7 @@ circuit el2_swerv : node _T_9769 = and(_T_9766, _T_9768) @[el2_ifu_bp_ctl.scala 447:81] node _T_9770 = or(_T_9769, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9771 = bits(_T_9770, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9772 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9773 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9774 = eq(_T_9773, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43725,7 +43725,7 @@ circuit el2_swerv : node _T_9778 = and(_T_9775, _T_9777) @[el2_ifu_bp_ctl.scala 447:81] node _T_9779 = or(_T_9778, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9780 = bits(_T_9779, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9781 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9782 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9783 = eq(_T_9782, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43735,7 +43735,7 @@ circuit el2_swerv : node _T_9787 = and(_T_9784, _T_9786) @[el2_ifu_bp_ctl.scala 447:81] node _T_9788 = or(_T_9787, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9789 = bits(_T_9788, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9790 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9791 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9792 = eq(_T_9791, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43745,7 +43745,7 @@ circuit el2_swerv : node _T_9796 = and(_T_9793, _T_9795) @[el2_ifu_bp_ctl.scala 447:81] node _T_9797 = or(_T_9796, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9798 = bits(_T_9797, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9799 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9800 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9801 = eq(_T_9800, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43755,7 +43755,7 @@ circuit el2_swerv : node _T_9805 = and(_T_9802, _T_9804) @[el2_ifu_bp_ctl.scala 447:81] node _T_9806 = or(_T_9805, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9807 = bits(_T_9806, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9808 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9809 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9810 = eq(_T_9809, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43765,7 +43765,7 @@ circuit el2_swerv : node _T_9814 = and(_T_9811, _T_9813) @[el2_ifu_bp_ctl.scala 447:81] node _T_9815 = or(_T_9814, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9816 = bits(_T_9815, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9817 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9818 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9819 = eq(_T_9818, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43775,7 +43775,7 @@ circuit el2_swerv : node _T_9823 = and(_T_9820, _T_9822) @[el2_ifu_bp_ctl.scala 447:81] node _T_9824 = or(_T_9823, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9825 = bits(_T_9824, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9826 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9827 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9828 = eq(_T_9827, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43785,7 +43785,7 @@ circuit el2_swerv : node _T_9832 = and(_T_9829, _T_9831) @[el2_ifu_bp_ctl.scala 447:81] node _T_9833 = or(_T_9832, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9834 = bits(_T_9833, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9835 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9836 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9837 = eq(_T_9836, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43795,7 +43795,7 @@ circuit el2_swerv : node _T_9841 = and(_T_9838, _T_9840) @[el2_ifu_bp_ctl.scala 447:81] node _T_9842 = or(_T_9841, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9843 = bits(_T_9842, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9844 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9845 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9846 = eq(_T_9845, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43805,7 +43805,7 @@ circuit el2_swerv : node _T_9850 = and(_T_9847, _T_9849) @[el2_ifu_bp_ctl.scala 447:81] node _T_9851 = or(_T_9850, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9852 = bits(_T_9851, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9853 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9854 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9855 = eq(_T_9854, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43815,7 +43815,7 @@ circuit el2_swerv : node _T_9859 = and(_T_9856, _T_9858) @[el2_ifu_bp_ctl.scala 447:81] node _T_9860 = or(_T_9859, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9861 = bits(_T_9860, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9862 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9863 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9864 = eq(_T_9863, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43825,7 +43825,7 @@ circuit el2_swerv : node _T_9868 = and(_T_9865, _T_9867) @[el2_ifu_bp_ctl.scala 447:81] node _T_9869 = or(_T_9868, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9870 = bits(_T_9869, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9871 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9872 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9873 = eq(_T_9872, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43835,7 +43835,7 @@ circuit el2_swerv : node _T_9877 = and(_T_9874, _T_9876) @[el2_ifu_bp_ctl.scala 447:81] node _T_9878 = or(_T_9877, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9879 = bits(_T_9878, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9880 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9881 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9882 = eq(_T_9881, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43845,7 +43845,7 @@ circuit el2_swerv : node _T_9886 = and(_T_9883, _T_9885) @[el2_ifu_bp_ctl.scala 447:81] node _T_9887 = or(_T_9886, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9888 = bits(_T_9887, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9889 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9890 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9891 = eq(_T_9890, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43855,7 +43855,7 @@ circuit el2_swerv : node _T_9895 = and(_T_9892, _T_9894) @[el2_ifu_bp_ctl.scala 447:81] node _T_9896 = or(_T_9895, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9897 = bits(_T_9896, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9898 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9899 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9900 = eq(_T_9899, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43865,7 +43865,7 @@ circuit el2_swerv : node _T_9904 = and(_T_9901, _T_9903) @[el2_ifu_bp_ctl.scala 447:81] node _T_9905 = or(_T_9904, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9906 = bits(_T_9905, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9907 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9908 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9909 = eq(_T_9908, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43875,7 +43875,7 @@ circuit el2_swerv : node _T_9913 = and(_T_9910, _T_9912) @[el2_ifu_bp_ctl.scala 447:81] node _T_9914 = or(_T_9913, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9915 = bits(_T_9914, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9916 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9917 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9918 = eq(_T_9917, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43885,7 +43885,7 @@ circuit el2_swerv : node _T_9922 = and(_T_9919, _T_9921) @[el2_ifu_bp_ctl.scala 447:81] node _T_9923 = or(_T_9922, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9924 = bits(_T_9923, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9925 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9926 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9927 = eq(_T_9926, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43895,7 +43895,7 @@ circuit el2_swerv : node _T_9931 = and(_T_9928, _T_9930) @[el2_ifu_bp_ctl.scala 447:81] node _T_9932 = or(_T_9931, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9933 = bits(_T_9932, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9934 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9935 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9936 = eq(_T_9935, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43905,7 +43905,7 @@ circuit el2_swerv : node _T_9940 = and(_T_9937, _T_9939) @[el2_ifu_bp_ctl.scala 447:81] node _T_9941 = or(_T_9940, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9942 = bits(_T_9941, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9943 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9944 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9945 = eq(_T_9944, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43915,7 +43915,7 @@ circuit el2_swerv : node _T_9949 = and(_T_9946, _T_9948) @[el2_ifu_bp_ctl.scala 447:81] node _T_9950 = or(_T_9949, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9951 = bits(_T_9950, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9952 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9953 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9954 = eq(_T_9953, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43925,7 +43925,7 @@ circuit el2_swerv : node _T_9958 = and(_T_9955, _T_9957) @[el2_ifu_bp_ctl.scala 447:81] node _T_9959 = or(_T_9958, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9960 = bits(_T_9959, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9961 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9962 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9963 = eq(_T_9962, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43935,7 +43935,7 @@ circuit el2_swerv : node _T_9967 = and(_T_9964, _T_9966) @[el2_ifu_bp_ctl.scala 447:81] node _T_9968 = or(_T_9967, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9969 = bits(_T_9968, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9970 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9971 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9972 = eq(_T_9971, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43945,7 +43945,7 @@ circuit el2_swerv : node _T_9976 = and(_T_9973, _T_9975) @[el2_ifu_bp_ctl.scala 447:81] node _T_9977 = or(_T_9976, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9978 = bits(_T_9977, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9979 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9980 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9981 = eq(_T_9980, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43955,7 +43955,7 @@ circuit el2_swerv : node _T_9985 = and(_T_9982, _T_9984) @[el2_ifu_bp_ctl.scala 447:81] node _T_9986 = or(_T_9985, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9987 = bits(_T_9986, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9988 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9989 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9990 = eq(_T_9989, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43965,7 +43965,7 @@ circuit el2_swerv : node _T_9994 = and(_T_9991, _T_9993) @[el2_ifu_bp_ctl.scala 447:81] node _T_9995 = or(_T_9994, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9996 = bits(_T_9995, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9997 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9998 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9999 = eq(_T_9998, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43975,7 +43975,7 @@ circuit el2_swerv : node _T_10003 = and(_T_10000, _T_10002) @[el2_ifu_bp_ctl.scala 447:81] node _T_10004 = or(_T_10003, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10005 = bits(_T_10004, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10006 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10007 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10008 = eq(_T_10007, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43985,7 +43985,7 @@ circuit el2_swerv : node _T_10012 = and(_T_10009, _T_10011) @[el2_ifu_bp_ctl.scala 447:81] node _T_10013 = or(_T_10012, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10014 = bits(_T_10013, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10015 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10016 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10017 = eq(_T_10016, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43995,7 +43995,7 @@ circuit el2_swerv : node _T_10021 = and(_T_10018, _T_10020) @[el2_ifu_bp_ctl.scala 447:81] node _T_10022 = or(_T_10021, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10023 = bits(_T_10022, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10024 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10025 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10026 = eq(_T_10025, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44005,7 +44005,7 @@ circuit el2_swerv : node _T_10030 = and(_T_10027, _T_10029) @[el2_ifu_bp_ctl.scala 447:81] node _T_10031 = or(_T_10030, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10032 = bits(_T_10031, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10033 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10034 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10035 = eq(_T_10034, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44015,7 +44015,7 @@ circuit el2_swerv : node _T_10039 = and(_T_10036, _T_10038) @[el2_ifu_bp_ctl.scala 447:81] node _T_10040 = or(_T_10039, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10041 = bits(_T_10040, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10042 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10043 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10044 = eq(_T_10043, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44025,7 +44025,7 @@ circuit el2_swerv : node _T_10048 = and(_T_10045, _T_10047) @[el2_ifu_bp_ctl.scala 447:81] node _T_10049 = or(_T_10048, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10050 = bits(_T_10049, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10051 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10052 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10053 = eq(_T_10052, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44035,7 +44035,7 @@ circuit el2_swerv : node _T_10057 = and(_T_10054, _T_10056) @[el2_ifu_bp_ctl.scala 447:81] node _T_10058 = or(_T_10057, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10059 = bits(_T_10058, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10060 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10061 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10062 = eq(_T_10061, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44045,7 +44045,7 @@ circuit el2_swerv : node _T_10066 = and(_T_10063, _T_10065) @[el2_ifu_bp_ctl.scala 447:81] node _T_10067 = or(_T_10066, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10068 = bits(_T_10067, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10069 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10070 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10071 = eq(_T_10070, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44055,7 +44055,7 @@ circuit el2_swerv : node _T_10075 = and(_T_10072, _T_10074) @[el2_ifu_bp_ctl.scala 447:81] node _T_10076 = or(_T_10075, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10077 = bits(_T_10076, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10078 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10079 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10080 = eq(_T_10079, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44065,7 +44065,7 @@ circuit el2_swerv : node _T_10084 = and(_T_10081, _T_10083) @[el2_ifu_bp_ctl.scala 447:81] node _T_10085 = or(_T_10084, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10086 = bits(_T_10085, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10087 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10088 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10089 = eq(_T_10088, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44075,7 +44075,7 @@ circuit el2_swerv : node _T_10093 = and(_T_10090, _T_10092) @[el2_ifu_bp_ctl.scala 447:81] node _T_10094 = or(_T_10093, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10095 = bits(_T_10094, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10096 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10097 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10098 = eq(_T_10097, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44085,7 +44085,7 @@ circuit el2_swerv : node _T_10102 = and(_T_10099, _T_10101) @[el2_ifu_bp_ctl.scala 447:81] node _T_10103 = or(_T_10102, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10104 = bits(_T_10103, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10105 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10106 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10107 = eq(_T_10106, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44095,7 +44095,7 @@ circuit el2_swerv : node _T_10111 = and(_T_10108, _T_10110) @[el2_ifu_bp_ctl.scala 447:81] node _T_10112 = or(_T_10111, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10113 = bits(_T_10112, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10114 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10115 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10116 = eq(_T_10115, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44105,7 +44105,7 @@ circuit el2_swerv : node _T_10120 = and(_T_10117, _T_10119) @[el2_ifu_bp_ctl.scala 447:81] node _T_10121 = or(_T_10120, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10122 = bits(_T_10121, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10123 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10124 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10125 = eq(_T_10124, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44115,7 +44115,7 @@ circuit el2_swerv : node _T_10129 = and(_T_10126, _T_10128) @[el2_ifu_bp_ctl.scala 447:81] node _T_10130 = or(_T_10129, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10131 = bits(_T_10130, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10132 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10133 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10134 = eq(_T_10133, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44125,7 +44125,7 @@ circuit el2_swerv : node _T_10138 = and(_T_10135, _T_10137) @[el2_ifu_bp_ctl.scala 447:81] node _T_10139 = or(_T_10138, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10140 = bits(_T_10139, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10141 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10142 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10143 = eq(_T_10142, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44135,7 +44135,7 @@ circuit el2_swerv : node _T_10147 = and(_T_10144, _T_10146) @[el2_ifu_bp_ctl.scala 447:81] node _T_10148 = or(_T_10147, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10149 = bits(_T_10148, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10150 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10151 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10152 = eq(_T_10151, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44145,7 +44145,7 @@ circuit el2_swerv : node _T_10156 = and(_T_10153, _T_10155) @[el2_ifu_bp_ctl.scala 447:81] node _T_10157 = or(_T_10156, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10158 = bits(_T_10157, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10159 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10160 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10161 = eq(_T_10160, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44155,7 +44155,7 @@ circuit el2_swerv : node _T_10165 = and(_T_10162, _T_10164) @[el2_ifu_bp_ctl.scala 447:81] node _T_10166 = or(_T_10165, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10167 = bits(_T_10166, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10168 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10169 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10170 = eq(_T_10169, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44165,7 +44165,7 @@ circuit el2_swerv : node _T_10174 = and(_T_10171, _T_10173) @[el2_ifu_bp_ctl.scala 447:81] node _T_10175 = or(_T_10174, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10176 = bits(_T_10175, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10177 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10178 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10179 = eq(_T_10178, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44175,7 +44175,7 @@ circuit el2_swerv : node _T_10183 = and(_T_10180, _T_10182) @[el2_ifu_bp_ctl.scala 447:81] node _T_10184 = or(_T_10183, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10185 = bits(_T_10184, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10186 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10187 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10188 = eq(_T_10187, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44185,7 +44185,7 @@ circuit el2_swerv : node _T_10192 = and(_T_10189, _T_10191) @[el2_ifu_bp_ctl.scala 447:81] node _T_10193 = or(_T_10192, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10194 = bits(_T_10193, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10195 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10196 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10197 = eq(_T_10196, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44195,7 +44195,7 @@ circuit el2_swerv : node _T_10201 = and(_T_10198, _T_10200) @[el2_ifu_bp_ctl.scala 447:81] node _T_10202 = or(_T_10201, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10203 = bits(_T_10202, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10204 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10205 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10206 = eq(_T_10205, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44205,7 +44205,7 @@ circuit el2_swerv : node _T_10210 = and(_T_10207, _T_10209) @[el2_ifu_bp_ctl.scala 447:81] node _T_10211 = or(_T_10210, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10212 = bits(_T_10211, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10213 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10214 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10215 = eq(_T_10214, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44215,7 +44215,7 @@ circuit el2_swerv : node _T_10219 = and(_T_10216, _T_10218) @[el2_ifu_bp_ctl.scala 447:81] node _T_10220 = or(_T_10219, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10221 = bits(_T_10220, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10222 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10223 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10224 = eq(_T_10223, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44225,7 +44225,7 @@ circuit el2_swerv : node _T_10228 = and(_T_10225, _T_10227) @[el2_ifu_bp_ctl.scala 447:81] node _T_10229 = or(_T_10228, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10230 = bits(_T_10229, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10231 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10232 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10233 = eq(_T_10232, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44235,7 +44235,7 @@ circuit el2_swerv : node _T_10237 = and(_T_10234, _T_10236) @[el2_ifu_bp_ctl.scala 447:81] node _T_10238 = or(_T_10237, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10239 = bits(_T_10238, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10240 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10241 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10242 = eq(_T_10241, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44245,7 +44245,7 @@ circuit el2_swerv : node _T_10246 = and(_T_10243, _T_10245) @[el2_ifu_bp_ctl.scala 447:81] node _T_10247 = or(_T_10246, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10248 = bits(_T_10247, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10249 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10250 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10251 = eq(_T_10250, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44255,7 +44255,7 @@ circuit el2_swerv : node _T_10255 = and(_T_10252, _T_10254) @[el2_ifu_bp_ctl.scala 447:81] node _T_10256 = or(_T_10255, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10257 = bits(_T_10256, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10258 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10259 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10260 = eq(_T_10259, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44265,7 +44265,7 @@ circuit el2_swerv : node _T_10264 = and(_T_10261, _T_10263) @[el2_ifu_bp_ctl.scala 447:81] node _T_10265 = or(_T_10264, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10266 = bits(_T_10265, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10267 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10268 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10269 = eq(_T_10268, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44275,7 +44275,7 @@ circuit el2_swerv : node _T_10273 = and(_T_10270, _T_10272) @[el2_ifu_bp_ctl.scala 447:81] node _T_10274 = or(_T_10273, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10275 = bits(_T_10274, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10276 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10277 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10278 = eq(_T_10277, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44285,7 +44285,7 @@ circuit el2_swerv : node _T_10282 = and(_T_10279, _T_10281) @[el2_ifu_bp_ctl.scala 447:81] node _T_10283 = or(_T_10282, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10284 = bits(_T_10283, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10285 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10286 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10287 = eq(_T_10286, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44295,7 +44295,7 @@ circuit el2_swerv : node _T_10291 = and(_T_10288, _T_10290) @[el2_ifu_bp_ctl.scala 447:81] node _T_10292 = or(_T_10291, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10293 = bits(_T_10292, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10294 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10295 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10296 = eq(_T_10295, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44305,7 +44305,7 @@ circuit el2_swerv : node _T_10300 = and(_T_10297, _T_10299) @[el2_ifu_bp_ctl.scala 447:81] node _T_10301 = or(_T_10300, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10302 = bits(_T_10301, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10303 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10304 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10305 = eq(_T_10304, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44315,7 +44315,7 @@ circuit el2_swerv : node _T_10309 = and(_T_10306, _T_10308) @[el2_ifu_bp_ctl.scala 447:81] node _T_10310 = or(_T_10309, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10311 = bits(_T_10310, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10312 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10313 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10314 = eq(_T_10313, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44325,7 +44325,7 @@ circuit el2_swerv : node _T_10318 = and(_T_10315, _T_10317) @[el2_ifu_bp_ctl.scala 447:81] node _T_10319 = or(_T_10318, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10320 = bits(_T_10319, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10321 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10322 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10323 = eq(_T_10322, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44335,7 +44335,7 @@ circuit el2_swerv : node _T_10327 = and(_T_10324, _T_10326) @[el2_ifu_bp_ctl.scala 447:81] node _T_10328 = or(_T_10327, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10329 = bits(_T_10328, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10330 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10331 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10332 = eq(_T_10331, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44345,7 +44345,7 @@ circuit el2_swerv : node _T_10336 = and(_T_10333, _T_10335) @[el2_ifu_bp_ctl.scala 447:81] node _T_10337 = or(_T_10336, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10338 = bits(_T_10337, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10339 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10340 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10341 = eq(_T_10340, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44355,7 +44355,7 @@ circuit el2_swerv : node _T_10345 = and(_T_10342, _T_10344) @[el2_ifu_bp_ctl.scala 447:81] node _T_10346 = or(_T_10345, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10347 = bits(_T_10346, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10348 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10349 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10350 = eq(_T_10349, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44365,7 +44365,7 @@ circuit el2_swerv : node _T_10354 = and(_T_10351, _T_10353) @[el2_ifu_bp_ctl.scala 447:81] node _T_10355 = or(_T_10354, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10356 = bits(_T_10355, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10357 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10358 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10359 = eq(_T_10358, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44375,7 +44375,7 @@ circuit el2_swerv : node _T_10363 = and(_T_10360, _T_10362) @[el2_ifu_bp_ctl.scala 447:81] node _T_10364 = or(_T_10363, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10365 = bits(_T_10364, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10366 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10367 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10368 = eq(_T_10367, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44385,7 +44385,7 @@ circuit el2_swerv : node _T_10372 = and(_T_10369, _T_10371) @[el2_ifu_bp_ctl.scala 447:81] node _T_10373 = or(_T_10372, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10374 = bits(_T_10373, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10375 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10376 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10377 = eq(_T_10376, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44395,7 +44395,7 @@ circuit el2_swerv : node _T_10381 = and(_T_10378, _T_10380) @[el2_ifu_bp_ctl.scala 447:81] node _T_10382 = or(_T_10381, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10383 = bits(_T_10382, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10384 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10385 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10386 = eq(_T_10385, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44405,7 +44405,7 @@ circuit el2_swerv : node _T_10390 = and(_T_10387, _T_10389) @[el2_ifu_bp_ctl.scala 447:81] node _T_10391 = or(_T_10390, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10392 = bits(_T_10391, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10393 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10394 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10395 = eq(_T_10394, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44415,7 +44415,7 @@ circuit el2_swerv : node _T_10399 = and(_T_10396, _T_10398) @[el2_ifu_bp_ctl.scala 447:81] node _T_10400 = or(_T_10399, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10401 = bits(_T_10400, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10402 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10403 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10404 = eq(_T_10403, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44425,7 +44425,7 @@ circuit el2_swerv : node _T_10408 = and(_T_10405, _T_10407) @[el2_ifu_bp_ctl.scala 447:81] node _T_10409 = or(_T_10408, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10410 = bits(_T_10409, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10411 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10412 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10413 = eq(_T_10412, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44435,7 +44435,7 @@ circuit el2_swerv : node _T_10417 = and(_T_10414, _T_10416) @[el2_ifu_bp_ctl.scala 447:81] node _T_10418 = or(_T_10417, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10419 = bits(_T_10418, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10420 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10421 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10422 = eq(_T_10421, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44445,7 +44445,7 @@ circuit el2_swerv : node _T_10426 = and(_T_10423, _T_10425) @[el2_ifu_bp_ctl.scala 447:81] node _T_10427 = or(_T_10426, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10428 = bits(_T_10427, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10429 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10430 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10431 = eq(_T_10430, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44455,7 +44455,7 @@ circuit el2_swerv : node _T_10435 = and(_T_10432, _T_10434) @[el2_ifu_bp_ctl.scala 447:81] node _T_10436 = or(_T_10435, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10437 = bits(_T_10436, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10438 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10439 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10440 = eq(_T_10439, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44465,7 +44465,7 @@ circuit el2_swerv : node _T_10444 = and(_T_10441, _T_10443) @[el2_ifu_bp_ctl.scala 447:81] node _T_10445 = or(_T_10444, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10446 = bits(_T_10445, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10447 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10448 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10449 = eq(_T_10448, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44475,7 +44475,7 @@ circuit el2_swerv : node _T_10453 = and(_T_10450, _T_10452) @[el2_ifu_bp_ctl.scala 447:81] node _T_10454 = or(_T_10453, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10455 = bits(_T_10454, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10456 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10457 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10458 = eq(_T_10457, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44485,7 +44485,7 @@ circuit el2_swerv : node _T_10462 = and(_T_10459, _T_10461) @[el2_ifu_bp_ctl.scala 447:81] node _T_10463 = or(_T_10462, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10464 = bits(_T_10463, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10465 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10466 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10467 = eq(_T_10466, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44495,7 +44495,7 @@ circuit el2_swerv : node _T_10471 = and(_T_10468, _T_10470) @[el2_ifu_bp_ctl.scala 447:81] node _T_10472 = or(_T_10471, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10473 = bits(_T_10472, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10474 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10475 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10476 = eq(_T_10475, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44505,7 +44505,7 @@ circuit el2_swerv : node _T_10480 = and(_T_10477, _T_10479) @[el2_ifu_bp_ctl.scala 447:81] node _T_10481 = or(_T_10480, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10482 = bits(_T_10481, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10483 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10484 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10485 = eq(_T_10484, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44515,7 +44515,7 @@ circuit el2_swerv : node _T_10489 = and(_T_10486, _T_10488) @[el2_ifu_bp_ctl.scala 447:81] node _T_10490 = or(_T_10489, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10491 = bits(_T_10490, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10492 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10493 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10494 = eq(_T_10493, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44525,7 +44525,7 @@ circuit el2_swerv : node _T_10498 = and(_T_10495, _T_10497) @[el2_ifu_bp_ctl.scala 447:81] node _T_10499 = or(_T_10498, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10500 = bits(_T_10499, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10501 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10502 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10503 = eq(_T_10502, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44535,7 +44535,7 @@ circuit el2_swerv : node _T_10507 = and(_T_10504, _T_10506) @[el2_ifu_bp_ctl.scala 447:81] node _T_10508 = or(_T_10507, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10509 = bits(_T_10508, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10510 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10511 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10512 = eq(_T_10511, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44545,7 +44545,7 @@ circuit el2_swerv : node _T_10516 = and(_T_10513, _T_10515) @[el2_ifu_bp_ctl.scala 447:81] node _T_10517 = or(_T_10516, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10518 = bits(_T_10517, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10519 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10520 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10521 = eq(_T_10520, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44555,7 +44555,7 @@ circuit el2_swerv : node _T_10525 = and(_T_10522, _T_10524) @[el2_ifu_bp_ctl.scala 447:81] node _T_10526 = or(_T_10525, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10527 = bits(_T_10526, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10528 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10529 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10530 = eq(_T_10529, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44565,7 +44565,7 @@ circuit el2_swerv : node _T_10534 = and(_T_10531, _T_10533) @[el2_ifu_bp_ctl.scala 447:81] node _T_10535 = or(_T_10534, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10536 = bits(_T_10535, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10537 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10538 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10539 = eq(_T_10538, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44575,7 +44575,7 @@ circuit el2_swerv : node _T_10543 = and(_T_10540, _T_10542) @[el2_ifu_bp_ctl.scala 447:81] node _T_10544 = or(_T_10543, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10545 = bits(_T_10544, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10546 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10547 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10548 = eq(_T_10547, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44585,7 +44585,7 @@ circuit el2_swerv : node _T_10552 = and(_T_10549, _T_10551) @[el2_ifu_bp_ctl.scala 447:81] node _T_10553 = or(_T_10552, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10554 = bits(_T_10553, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10555 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10556 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10557 = eq(_T_10556, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44595,7 +44595,7 @@ circuit el2_swerv : node _T_10561 = and(_T_10558, _T_10560) @[el2_ifu_bp_ctl.scala 447:81] node _T_10562 = or(_T_10561, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10563 = bits(_T_10562, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10564 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10565 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10566 = eq(_T_10565, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44605,7 +44605,7 @@ circuit el2_swerv : node _T_10570 = and(_T_10567, _T_10569) @[el2_ifu_bp_ctl.scala 447:81] node _T_10571 = or(_T_10570, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10572 = bits(_T_10571, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10573 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10574 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10575 = eq(_T_10574, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44615,7 +44615,7 @@ circuit el2_swerv : node _T_10579 = and(_T_10576, _T_10578) @[el2_ifu_bp_ctl.scala 447:81] node _T_10580 = or(_T_10579, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10581 = bits(_T_10580, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10582 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10583 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10584 = eq(_T_10583, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44625,7 +44625,7 @@ circuit el2_swerv : node _T_10588 = and(_T_10585, _T_10587) @[el2_ifu_bp_ctl.scala 447:81] node _T_10589 = or(_T_10588, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10590 = bits(_T_10589, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10591 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10592 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10593 = eq(_T_10592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44635,7 +44635,7 @@ circuit el2_swerv : node _T_10597 = and(_T_10594, _T_10596) @[el2_ifu_bp_ctl.scala 447:81] node _T_10598 = or(_T_10597, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10599 = bits(_T_10598, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10600 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10601 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10602 = eq(_T_10601, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44645,7 +44645,7 @@ circuit el2_swerv : node _T_10606 = and(_T_10603, _T_10605) @[el2_ifu_bp_ctl.scala 447:81] node _T_10607 = or(_T_10606, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10608 = bits(_T_10607, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10609 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10610 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10611 = eq(_T_10610, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44655,7 +44655,7 @@ circuit el2_swerv : node _T_10615 = and(_T_10612, _T_10614) @[el2_ifu_bp_ctl.scala 447:81] node _T_10616 = or(_T_10615, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10617 = bits(_T_10616, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10618 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10619 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10620 = eq(_T_10619, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44665,7 +44665,7 @@ circuit el2_swerv : node _T_10624 = and(_T_10621, _T_10623) @[el2_ifu_bp_ctl.scala 447:81] node _T_10625 = or(_T_10624, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10626 = bits(_T_10625, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10627 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10628 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10629 = eq(_T_10628, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44675,7 +44675,7 @@ circuit el2_swerv : node _T_10633 = and(_T_10630, _T_10632) @[el2_ifu_bp_ctl.scala 447:81] node _T_10634 = or(_T_10633, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10635 = bits(_T_10634, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10636 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10637 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10638 = eq(_T_10637, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44685,7 +44685,7 @@ circuit el2_swerv : node _T_10642 = and(_T_10639, _T_10641) @[el2_ifu_bp_ctl.scala 447:81] node _T_10643 = or(_T_10642, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10644 = bits(_T_10643, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10645 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10646 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10647 = eq(_T_10646, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44695,7 +44695,7 @@ circuit el2_swerv : node _T_10651 = and(_T_10648, _T_10650) @[el2_ifu_bp_ctl.scala 447:81] node _T_10652 = or(_T_10651, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10653 = bits(_T_10652, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10654 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10655 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10656 = eq(_T_10655, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44705,7 +44705,7 @@ circuit el2_swerv : node _T_10660 = and(_T_10657, _T_10659) @[el2_ifu_bp_ctl.scala 447:81] node _T_10661 = or(_T_10660, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10662 = bits(_T_10661, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10663 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10664 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10665 = eq(_T_10664, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44715,7 +44715,7 @@ circuit el2_swerv : node _T_10669 = and(_T_10666, _T_10668) @[el2_ifu_bp_ctl.scala 447:81] node _T_10670 = or(_T_10669, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10671 = bits(_T_10670, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10672 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10673 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10674 = eq(_T_10673, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44725,7 +44725,7 @@ circuit el2_swerv : node _T_10678 = and(_T_10675, _T_10677) @[el2_ifu_bp_ctl.scala 447:81] node _T_10679 = or(_T_10678, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10680 = bits(_T_10679, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10681 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10682 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10683 = eq(_T_10682, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44735,7 +44735,7 @@ circuit el2_swerv : node _T_10687 = and(_T_10684, _T_10686) @[el2_ifu_bp_ctl.scala 447:81] node _T_10688 = or(_T_10687, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10689 = bits(_T_10688, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10690 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10691 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10692 = eq(_T_10691, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44745,7 +44745,7 @@ circuit el2_swerv : node _T_10696 = and(_T_10693, _T_10695) @[el2_ifu_bp_ctl.scala 447:81] node _T_10697 = or(_T_10696, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10698 = bits(_T_10697, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10699 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10700 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10701 = eq(_T_10700, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44755,7 +44755,7 @@ circuit el2_swerv : node _T_10705 = and(_T_10702, _T_10704) @[el2_ifu_bp_ctl.scala 447:81] node _T_10706 = or(_T_10705, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10707 = bits(_T_10706, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10708 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10709 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10710 = eq(_T_10709, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44765,7 +44765,7 @@ circuit el2_swerv : node _T_10714 = and(_T_10711, _T_10713) @[el2_ifu_bp_ctl.scala 447:81] node _T_10715 = or(_T_10714, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10716 = bits(_T_10715, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10717 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10718 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10719 = eq(_T_10718, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44775,7 +44775,7 @@ circuit el2_swerv : node _T_10723 = and(_T_10720, _T_10722) @[el2_ifu_bp_ctl.scala 447:81] node _T_10724 = or(_T_10723, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10725 = bits(_T_10724, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10726 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10727 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10728 = eq(_T_10727, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44785,7 +44785,7 @@ circuit el2_swerv : node _T_10732 = and(_T_10729, _T_10731) @[el2_ifu_bp_ctl.scala 447:81] node _T_10733 = or(_T_10732, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10734 = bits(_T_10733, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10735 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10736 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10737 = eq(_T_10736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44795,7 +44795,7 @@ circuit el2_swerv : node _T_10741 = and(_T_10738, _T_10740) @[el2_ifu_bp_ctl.scala 447:81] node _T_10742 = or(_T_10741, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10743 = bits(_T_10742, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10744 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10745 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10746 = eq(_T_10745, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44805,7 +44805,7 @@ circuit el2_swerv : node _T_10750 = and(_T_10747, _T_10749) @[el2_ifu_bp_ctl.scala 447:81] node _T_10751 = or(_T_10750, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10752 = bits(_T_10751, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10753 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10754 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10755 = eq(_T_10754, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44815,7 +44815,7 @@ circuit el2_swerv : node _T_10759 = and(_T_10756, _T_10758) @[el2_ifu_bp_ctl.scala 447:81] node _T_10760 = or(_T_10759, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10761 = bits(_T_10760, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10762 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10763 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10764 = eq(_T_10763, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44825,7 +44825,7 @@ circuit el2_swerv : node _T_10768 = and(_T_10765, _T_10767) @[el2_ifu_bp_ctl.scala 447:81] node _T_10769 = or(_T_10768, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10770 = bits(_T_10769, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10771 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10772 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10773 = eq(_T_10772, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44835,7 +44835,7 @@ circuit el2_swerv : node _T_10777 = and(_T_10774, _T_10776) @[el2_ifu_bp_ctl.scala 447:81] node _T_10778 = or(_T_10777, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10779 = bits(_T_10778, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10780 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10781 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10782 = eq(_T_10781, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44845,7 +44845,7 @@ circuit el2_swerv : node _T_10786 = and(_T_10783, _T_10785) @[el2_ifu_bp_ctl.scala 447:81] node _T_10787 = or(_T_10786, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10788 = bits(_T_10787, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10789 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10790 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10791 = eq(_T_10790, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44855,7 +44855,7 @@ circuit el2_swerv : node _T_10795 = and(_T_10792, _T_10794) @[el2_ifu_bp_ctl.scala 447:81] node _T_10796 = or(_T_10795, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10797 = bits(_T_10796, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10798 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10799 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10800 = eq(_T_10799, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44865,7 +44865,7 @@ circuit el2_swerv : node _T_10804 = and(_T_10801, _T_10803) @[el2_ifu_bp_ctl.scala 447:81] node _T_10805 = or(_T_10804, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10806 = bits(_T_10805, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10807 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10808 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10809 = eq(_T_10808, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44875,7 +44875,7 @@ circuit el2_swerv : node _T_10813 = and(_T_10810, _T_10812) @[el2_ifu_bp_ctl.scala 447:81] node _T_10814 = or(_T_10813, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10815 = bits(_T_10814, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10816 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10817 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10818 = eq(_T_10817, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44885,7 +44885,7 @@ circuit el2_swerv : node _T_10822 = and(_T_10819, _T_10821) @[el2_ifu_bp_ctl.scala 447:81] node _T_10823 = or(_T_10822, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10824 = bits(_T_10823, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10825 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10826 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10827 = eq(_T_10826, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44895,7 +44895,7 @@ circuit el2_swerv : node _T_10831 = and(_T_10828, _T_10830) @[el2_ifu_bp_ctl.scala 447:81] node _T_10832 = or(_T_10831, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10833 = bits(_T_10832, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10834 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10835 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10836 = eq(_T_10835, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44905,7 +44905,7 @@ circuit el2_swerv : node _T_10840 = and(_T_10837, _T_10839) @[el2_ifu_bp_ctl.scala 447:81] node _T_10841 = or(_T_10840, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10842 = bits(_T_10841, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10843 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10844 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10845 = eq(_T_10844, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44915,7 +44915,7 @@ circuit el2_swerv : node _T_10849 = and(_T_10846, _T_10848) @[el2_ifu_bp_ctl.scala 447:81] node _T_10850 = or(_T_10849, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10851 = bits(_T_10850, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10852 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10853 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10854 = eq(_T_10853, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44925,7 +44925,7 @@ circuit el2_swerv : node _T_10858 = and(_T_10855, _T_10857) @[el2_ifu_bp_ctl.scala 447:81] node _T_10859 = or(_T_10858, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10860 = bits(_T_10859, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10861 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10862 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10863 = eq(_T_10862, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44935,7 +44935,7 @@ circuit el2_swerv : node _T_10867 = and(_T_10864, _T_10866) @[el2_ifu_bp_ctl.scala 447:81] node _T_10868 = or(_T_10867, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10869 = bits(_T_10868, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10870 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10871 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10872 = eq(_T_10871, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44945,7 +44945,7 @@ circuit el2_swerv : node _T_10876 = and(_T_10873, _T_10875) @[el2_ifu_bp_ctl.scala 447:81] node _T_10877 = or(_T_10876, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10878 = bits(_T_10877, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10879 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10880 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10881 = eq(_T_10880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44955,7 +44955,7 @@ circuit el2_swerv : node _T_10885 = and(_T_10882, _T_10884) @[el2_ifu_bp_ctl.scala 447:81] node _T_10886 = or(_T_10885, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10887 = bits(_T_10886, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10888 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10889 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10890 = eq(_T_10889, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44965,7 +44965,7 @@ circuit el2_swerv : node _T_10894 = and(_T_10891, _T_10893) @[el2_ifu_bp_ctl.scala 447:81] node _T_10895 = or(_T_10894, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10896 = bits(_T_10895, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10897 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10898 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10899 = eq(_T_10898, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44975,7 +44975,7 @@ circuit el2_swerv : node _T_10903 = and(_T_10900, _T_10902) @[el2_ifu_bp_ctl.scala 447:81] node _T_10904 = or(_T_10903, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10905 = bits(_T_10904, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10906 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10907 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10908 = eq(_T_10907, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44985,7 +44985,7 @@ circuit el2_swerv : node _T_10912 = and(_T_10909, _T_10911) @[el2_ifu_bp_ctl.scala 447:81] node _T_10913 = or(_T_10912, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10914 = bits(_T_10913, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10915 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10916 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10917 = eq(_T_10916, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44995,7 +44995,7 @@ circuit el2_swerv : node _T_10921 = and(_T_10918, _T_10920) @[el2_ifu_bp_ctl.scala 447:81] node _T_10922 = or(_T_10921, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10923 = bits(_T_10922, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10924 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10925 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10926 = eq(_T_10925, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45005,7 +45005,7 @@ circuit el2_swerv : node _T_10930 = and(_T_10927, _T_10929) @[el2_ifu_bp_ctl.scala 447:81] node _T_10931 = or(_T_10930, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10932 = bits(_T_10931, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10933 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10934 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10935 = eq(_T_10934, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45015,7 +45015,7 @@ circuit el2_swerv : node _T_10939 = and(_T_10936, _T_10938) @[el2_ifu_bp_ctl.scala 447:81] node _T_10940 = or(_T_10939, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10941 = bits(_T_10940, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10942 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10943 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10944 = eq(_T_10943, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45025,7 +45025,7 @@ circuit el2_swerv : node _T_10948 = and(_T_10945, _T_10947) @[el2_ifu_bp_ctl.scala 447:81] node _T_10949 = or(_T_10948, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10950 = bits(_T_10949, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10951 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10952 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10953 = eq(_T_10952, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45035,7 +45035,7 @@ circuit el2_swerv : node _T_10957 = and(_T_10954, _T_10956) @[el2_ifu_bp_ctl.scala 447:81] node _T_10958 = or(_T_10957, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10959 = bits(_T_10958, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10960 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10961 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10962 = eq(_T_10961, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45045,7 +45045,7 @@ circuit el2_swerv : node _T_10966 = and(_T_10963, _T_10965) @[el2_ifu_bp_ctl.scala 447:81] node _T_10967 = or(_T_10966, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10968 = bits(_T_10967, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10969 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10970 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10971 = eq(_T_10970, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45055,7 +45055,7 @@ circuit el2_swerv : node _T_10975 = and(_T_10972, _T_10974) @[el2_ifu_bp_ctl.scala 447:81] node _T_10976 = or(_T_10975, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10977 = bits(_T_10976, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10978 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10979 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10980 = eq(_T_10979, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45065,7 +45065,7 @@ circuit el2_swerv : node _T_10984 = and(_T_10981, _T_10983) @[el2_ifu_bp_ctl.scala 447:81] node _T_10985 = or(_T_10984, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10986 = bits(_T_10985, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10987 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10988 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10989 = eq(_T_10988, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45075,7 +45075,7 @@ circuit el2_swerv : node _T_10993 = and(_T_10990, _T_10992) @[el2_ifu_bp_ctl.scala 447:81] node _T_10994 = or(_T_10993, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10995 = bits(_T_10994, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10996 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10997 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10998 = eq(_T_10997, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45085,7 +45085,7 @@ circuit el2_swerv : node _T_11002 = and(_T_10999, _T_11001) @[el2_ifu_bp_ctl.scala 447:81] node _T_11003 = or(_T_11002, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11004 = bits(_T_11003, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11005 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11006 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11007 = eq(_T_11006, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45095,7 +45095,7 @@ circuit el2_swerv : node _T_11011 = and(_T_11008, _T_11010) @[el2_ifu_bp_ctl.scala 447:81] node _T_11012 = or(_T_11011, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11013 = bits(_T_11012, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11014 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11015 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11016 = eq(_T_11015, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45105,7 +45105,7 @@ circuit el2_swerv : node _T_11020 = and(_T_11017, _T_11019) @[el2_ifu_bp_ctl.scala 447:81] node _T_11021 = or(_T_11020, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11022 = bits(_T_11021, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11023 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11024 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11025 = eq(_T_11024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45115,7 +45115,7 @@ circuit el2_swerv : node _T_11029 = and(_T_11026, _T_11028) @[el2_ifu_bp_ctl.scala 447:81] node _T_11030 = or(_T_11029, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11031 = bits(_T_11030, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11032 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11033 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11034 = eq(_T_11033, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45125,7 +45125,7 @@ circuit el2_swerv : node _T_11038 = and(_T_11035, _T_11037) @[el2_ifu_bp_ctl.scala 447:81] node _T_11039 = or(_T_11038, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11040 = bits(_T_11039, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11041 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11042 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11043 = eq(_T_11042, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45135,7 +45135,7 @@ circuit el2_swerv : node _T_11047 = and(_T_11044, _T_11046) @[el2_ifu_bp_ctl.scala 447:81] node _T_11048 = or(_T_11047, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11049 = bits(_T_11048, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11050 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11051 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11052 = eq(_T_11051, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45145,7 +45145,7 @@ circuit el2_swerv : node _T_11056 = and(_T_11053, _T_11055) @[el2_ifu_bp_ctl.scala 447:81] node _T_11057 = or(_T_11056, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11058 = bits(_T_11057, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11059 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11060 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11061 = eq(_T_11060, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45155,7 +45155,7 @@ circuit el2_swerv : node _T_11065 = and(_T_11062, _T_11064) @[el2_ifu_bp_ctl.scala 447:81] node _T_11066 = or(_T_11065, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11067 = bits(_T_11066, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11068 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11069 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11070 = eq(_T_11069, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45165,7 +45165,7 @@ circuit el2_swerv : node _T_11074 = and(_T_11071, _T_11073) @[el2_ifu_bp_ctl.scala 447:81] node _T_11075 = or(_T_11074, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11076 = bits(_T_11075, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11077 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11078 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11079 = eq(_T_11078, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45175,7 +45175,7 @@ circuit el2_swerv : node _T_11083 = and(_T_11080, _T_11082) @[el2_ifu_bp_ctl.scala 447:81] node _T_11084 = or(_T_11083, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11085 = bits(_T_11084, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11086 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11087 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11088 = eq(_T_11087, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45185,7 +45185,7 @@ circuit el2_swerv : node _T_11092 = and(_T_11089, _T_11091) @[el2_ifu_bp_ctl.scala 447:81] node _T_11093 = or(_T_11092, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11094 = bits(_T_11093, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11095 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11096 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11097 = eq(_T_11096, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45195,7 +45195,7 @@ circuit el2_swerv : node _T_11101 = and(_T_11098, _T_11100) @[el2_ifu_bp_ctl.scala 447:81] node _T_11102 = or(_T_11101, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11103 = bits(_T_11102, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11104 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11105 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11106 = eq(_T_11105, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45205,7 +45205,7 @@ circuit el2_swerv : node _T_11110 = and(_T_11107, _T_11109) @[el2_ifu_bp_ctl.scala 447:81] node _T_11111 = or(_T_11110, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11112 = bits(_T_11111, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11113 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11114 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11115 = eq(_T_11114, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45215,7 +45215,7 @@ circuit el2_swerv : node _T_11119 = and(_T_11116, _T_11118) @[el2_ifu_bp_ctl.scala 447:81] node _T_11120 = or(_T_11119, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11121 = bits(_T_11120, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11122 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11123 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11124 = eq(_T_11123, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45225,7 +45225,7 @@ circuit el2_swerv : node _T_11128 = and(_T_11125, _T_11127) @[el2_ifu_bp_ctl.scala 447:81] node _T_11129 = or(_T_11128, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11130 = bits(_T_11129, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11131 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11132 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11133 = eq(_T_11132, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45235,7 +45235,7 @@ circuit el2_swerv : node _T_11137 = and(_T_11134, _T_11136) @[el2_ifu_bp_ctl.scala 447:81] node _T_11138 = or(_T_11137, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11139 = bits(_T_11138, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11140 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11141 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11142 = eq(_T_11141, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45245,7 +45245,7 @@ circuit el2_swerv : node _T_11146 = and(_T_11143, _T_11145) @[el2_ifu_bp_ctl.scala 447:81] node _T_11147 = or(_T_11146, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11148 = bits(_T_11147, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11149 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11150 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11151 = eq(_T_11150, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45255,7 +45255,7 @@ circuit el2_swerv : node _T_11155 = and(_T_11152, _T_11154) @[el2_ifu_bp_ctl.scala 447:81] node _T_11156 = or(_T_11155, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11157 = bits(_T_11156, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11158 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11159 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11160 = eq(_T_11159, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45265,7 +45265,7 @@ circuit el2_swerv : node _T_11164 = and(_T_11161, _T_11163) @[el2_ifu_bp_ctl.scala 447:81] node _T_11165 = or(_T_11164, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11166 = bits(_T_11165, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] wire bht_bank_sel : UInt<1>[16][16][2] @[el2_ifu_bp_ctl.scala 449:26] node _T_11167 = bits(bht_wr_en0, 0, 0) @[el2_ifu_bp_ctl.scala 455:41] node _T_11168 = bits(mp_hashed, 3, 0) @[el2_ifu_bp_ctl.scala 455:60] @@ -62407,7 +62407,7 @@ circuit el2_swerv : module el2_ifu_aln_ctl : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}} + output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}} io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19] io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18] @@ -63516,62 +63516,62 @@ circuit el2_swerv : node _T_726 = and(_T_724, _T_725) @[el2_ifu_aln_ctl.scala 378:100] node _T_727 = or(_T_722, _T_726) @[el2_ifu_aln_ctl.scala 378:75] io.i0_brp.valid <= _T_727 @[el2_ifu_aln_ctl.scala 378:19] - node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:44] - node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:34] - node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:70] - node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:60] - node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:49] - io.i0_brp.bits.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:22] + node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:39] + node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:29] + node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:65] + node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:55] + node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:44] + io.i0_brp.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:17] node _T_733 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 382:39] node _T_734 = and(first2B, _T_733) @[el2_ifu_aln_ctl.scala 382:29] node _T_735 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 382:65] node _T_736 = and(first4B, _T_735) @[el2_ifu_aln_ctl.scala 382:55] node i0_brp_pc4 = or(_T_734, _T_736) @[el2_ifu_aln_ctl.scala 382:44] - node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:50] - node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:38] - node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:55] - node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:71] - node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:85] - node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:28] - io.i0_brp.bits.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:22] - node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:51] - node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:39] - node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:79] - node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:67] - node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:56] + node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:45] + node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:33] + node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:50] + node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:66] + node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:80] + node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:23] + io.i0_brp.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:17] + node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:46] + node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:34] + node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:74] + node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:62] + node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:51] node _T_748 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 387:26] node _T_749 = and(first2B, _T_748) @[el2_ifu_aln_ctl.scala 387:14] node _T_750 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 387:54] node _T_751 = and(first4B, _T_750) @[el2_ifu_aln_ctl.scala 387:42] node _T_752 = or(_T_749, _T_751) @[el2_ifu_aln_ctl.scala 387:31] node _T_753 = cat(_T_747, _T_752) @[Cat.scala 29:58] - io.i0_brp.bits.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:23] + io.i0_brp.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:18] node i0_ends_f1 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 389:28] - node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:44] - node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:32] - io.i0_brp.bits.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:26] - node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:42] - node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:30] - io.i0_brp.bits.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:24] - node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:56] - node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:46] - node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:72] - node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:60] - io.i0_brp.bits.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:34] - node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:62] - node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:50] - node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:67] - node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:82] - node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:95] - node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:40] - io.i0_brp.bits.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:34] - node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:47] - node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:61] - node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:94] - node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:92] - node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:106] - node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:73] - io.i0_brp.bits.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:27] + node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:39] + node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:27] + io.i0_brp.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:21] + node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:37] + node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:25] + io.i0_brp.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:19] + node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:51] + node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:41] + node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:67] + node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:55] + io.i0_brp.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:29] + node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:57] + node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:45] + node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:62] + node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:77] + node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:90] + node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:35] + io.i0_brp.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:29] + node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:42] + node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:56] + node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:89] + node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:87] + node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:101] + node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:68] + io.i0_brp.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:22] node _T_774 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 400:50] node _T_775 = or(first2B, _T_774) @[el2_ifu_aln_ctl.scala 400:38] node _T_776 = bits(_T_775, 0, 0) @[el2_ifu_aln_ctl.scala 400:55] @@ -63910,7 +63910,7 @@ circuit el2_swerv : module el2_ifu : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>} inst mem_ctl_ch of el2_ifu_mem_ctl @[el2_ifu.scala 146:26] mem_ctl_ch.clock <= clock @@ -63965,11 +63965,11 @@ circuit el2_swerv : bp_ctl_ch.io.ic_hit_f <= mem_ctl_ch.io.ic_hit_f @[el2_ifu.scala 195:25] bp_ctl_ch.io.ifc_fetch_addr_f <= ifc_ctl_ch.io.ifc_fetch_addr_f @[el2_ifu.scala 196:33] bp_ctl_ch.io.ifc_fetch_req_f <= ifc_ctl_ch.io.ifc_fetch_req_f @[el2_ifu.scala 197:32] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.middle <= io.dec_tlu_br0_r_pkt.bits.middle @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.way <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_start_error <= io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_error <= io.dec_tlu_br0_r_pkt.bits.br_error @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.hist <= io.dec_tlu_br0_r_pkt.bits.hist @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.middle <= io.dec_tlu_br0_r_pkt.middle @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.way <= io.dec_tlu_br0_r_pkt.way @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_start_error <= io.dec_tlu_br0_r_pkt.br_start_error @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_error <= io.dec_tlu_br0_r_pkt.br_error @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.hist <= io.dec_tlu_br0_r_pkt.hist @[el2_ifu.scala 198:34] bp_ctl_ch.io.dec_tlu_br0_r_pkt.valid <= io.dec_tlu_br0_r_pkt.valid @[el2_ifu.scala 198:34] bp_ctl_ch.io.exu_i0_br_fghr_r <= io.exu_i0_br_fghr_r @[el2_ifu.scala 199:33] bp_ctl_ch.io.exu_i0_br_index_r <= io.exu_i0_br_index_r @[el2_ifu.scala 200:34] @@ -64111,14 +64111,14 @@ circuit el2_swerv : io.ifu_i0_pc <= aln_ctl_ch.io.ifu_i0_pc @[el2_ifu.scala 327:16] io.ifu_i0_pc4 <= aln_ctl_ch.io.ifu_i0_pc4 @[el2_ifu.scala 328:17] io.ifu_miss_state_idle <= mem_ctl_ch.io.ifu_miss_state_idle @[el2_ifu.scala 329:26] - io.i0_brp.bits.ret <= aln_ctl_ch.io.i0_brp.bits.ret @[el2_ifu.scala 331:13] - io.i0_brp.bits.way <= aln_ctl_ch.io.i0_brp.bits.way @[el2_ifu.scala 331:13] - io.i0_brp.bits.prett <= aln_ctl_ch.io.i0_brp.bits.prett @[el2_ifu.scala 331:13] - io.i0_brp.bits.bank <= aln_ctl_ch.io.i0_brp.bits.bank @[el2_ifu.scala 331:13] - io.i0_brp.bits.br_start_error <= aln_ctl_ch.io.i0_brp.bits.br_start_error @[el2_ifu.scala 331:13] - io.i0_brp.bits.br_error <= aln_ctl_ch.io.i0_brp.bits.br_error @[el2_ifu.scala 331:13] - io.i0_brp.bits.hist <= aln_ctl_ch.io.i0_brp.bits.hist @[el2_ifu.scala 331:13] - io.i0_brp.bits.toffset <= aln_ctl_ch.io.i0_brp.bits.toffset @[el2_ifu.scala 331:13] + io.i0_brp.ret <= aln_ctl_ch.io.i0_brp.ret @[el2_ifu.scala 331:13] + io.i0_brp.way <= aln_ctl_ch.io.i0_brp.way @[el2_ifu.scala 331:13] + io.i0_brp.prett <= aln_ctl_ch.io.i0_brp.prett @[el2_ifu.scala 331:13] + io.i0_brp.bank <= aln_ctl_ch.io.i0_brp.bank @[el2_ifu.scala 331:13] + io.i0_brp.br_start_error <= aln_ctl_ch.io.i0_brp.br_start_error @[el2_ifu.scala 331:13] + io.i0_brp.br_error <= aln_ctl_ch.io.i0_brp.br_error @[el2_ifu.scala 331:13] + io.i0_brp.hist <= aln_ctl_ch.io.i0_brp.hist @[el2_ifu.scala 331:13] + io.i0_brp.toffset <= aln_ctl_ch.io.i0_brp.toffset @[el2_ifu.scala 331:13] io.i0_brp.valid <= aln_ctl_ch.io.i0_brp.valid @[el2_ifu.scala 331:13] io.ifu_i0_bp_index <= aln_ctl_ch.io.ifu_i0_bp_index @[el2_ifu.scala 332:22] io.ifu_i0_bp_fghr <= aln_ctl_ch.io.ifu_i0_bp_fghr @[el2_ifu.scala 333:21] @@ -64132,52 +64132,52 @@ circuit el2_swerv : module el2_dec_ib_ctl : input clock : Clock input reset : Reset - output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} + output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} - io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 43:31] - io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 44:31] - io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 45:31] - io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 46:31] - io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 47:31] - io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 48:31] - io.dec_i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 50:31] - io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 51:31] - io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 52:31] - node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 66:60] - node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 66:41] - node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 67:38] - node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 67:36] - node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 68:36] - node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 70:55] - node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 70:37] - node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 71:55] - node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 71:37] - node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 72:55] - node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 72:37] - node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 73:55] - node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 73:37] - node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 75:40] - node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 76:40] - node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 79:20] + io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 8:31] + io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 9:31] + io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 10:31] + io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 11:31] + io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 12:31] + io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 13:31] + io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 15:31] + io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 16:31] + io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 17:31] + node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 31:60] + node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 31:41] + node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 32:38] + node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 32:36] + node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 33:36] + node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 35:55] + node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 35:37] + node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 36:55] + node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 36:37] + node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 37:55] + node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 37:37] + node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 38:55] + node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 38:37] + node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 40:40] + node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 41:40] + node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 44:20] node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58] node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58] - node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 80:21] - node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58] - node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58] - node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 81:20] - node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58] - node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 82:21] - node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58] + node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 45:21] + node _T_11 = cat(UInt<3>("h06"), dreg) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, UInt<6>("h033")) @[Cat.scala 29:58] + node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 46:20] + node _T_14 = cat(dcsr, UInt<14>("h02073")) @[Cat.scala 29:58] + node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 47:21] + node _T_16 = cat(dcsr, UInt<13>("h01073")) @[Cat.scala 29:58] node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72] node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] @@ -64187,16 +64187,16 @@ circuit el2_swerv : node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] wire ib0_debug_in : UInt<32> @[Mux.scala 27:72] ib0_debug_in <= _T_23 @[Mux.scala 27:72] - node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 86:47] - io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 86:28] - node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 89:51] - node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 89:43] - io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 89:24] - node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 91:41] - io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 91:22] - node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 92:41] - node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 92:28] - io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 92:22] + node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 51:47] + io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 51:28] + node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 54:51] + node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 54:43] + io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 54:24] + node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 56:41] + io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 56:22] + node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 57:41] + node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 57:28] + io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 57:22] extmodule gated_latch_661 : output Q : Clock @@ -64227,2039 +64227,2024 @@ circuit el2_swerv : input reset : Reset output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} - node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 72:23] - node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 72:35] - node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 72:27] - node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 72:49] - node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:42] - node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:60] - node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 72:53] - node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 72:39] - node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 72:75] - node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:68] - node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:85] - node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 72:78] - node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 72:65] - io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 72:14] - node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 73:51] - node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 73:51] - node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 73:90] - node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 73:90] - node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 73:55] - node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 74:37] - node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 74:37] - node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 73:94] - node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 74:76] - node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 74:76] - node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 74:41] - node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_46 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_47 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_49 = and(_T_45, _T_46) @[el2_dec_dec_ctl.scala 75:38] - node _T_50 = and(_T_49, _T_48) @[el2_dec_dec_ctl.scala 75:38] - node _T_51 = or(_T_43, _T_50) @[el2_dec_dec_ctl.scala 74:80] - node _T_52 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_54 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_55 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_57 = and(_T_53, _T_54) @[el2_dec_dec_ctl.scala 75:76] - node _T_58 = and(_T_57, _T_56) @[el2_dec_dec_ctl.scala 75:76] - node _T_59 = or(_T_51, _T_58) @[el2_dec_dec_ctl.scala 75:42] - node _T_60 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_61 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_62 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_64 = and(_T_60, _T_61) @[el2_dec_dec_ctl.scala 76:37] - node _T_65 = and(_T_64, _T_63) @[el2_dec_dec_ctl.scala 76:37] - node _T_66 = or(_T_59, _T_65) @[el2_dec_dec_ctl.scala 75:80] - node _T_67 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_68 = eq(_T_67, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_69 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_70 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_71 = eq(_T_70, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_72 = and(_T_68, _T_69) @[el2_dec_dec_ctl.scala 76:75] - node _T_73 = and(_T_72, _T_71) @[el2_dec_dec_ctl.scala 76:75] - node _T_74 = or(_T_66, _T_73) @[el2_dec_dec_ctl.scala 76:41] - node _T_75 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_76 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_77 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_79 = and(_T_75, _T_76) @[el2_dec_dec_ctl.scala 77:37] - node _T_80 = and(_T_79, _T_78) @[el2_dec_dec_ctl.scala 77:37] - node _T_81 = or(_T_74, _T_80) @[el2_dec_dec_ctl.scala 76:79] - node _T_82 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_84 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_85 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_87 = and(_T_83, _T_84) @[el2_dec_dec_ctl.scala 77:75] - node _T_88 = and(_T_87, _T_86) @[el2_dec_dec_ctl.scala 77:75] - node _T_89 = or(_T_81, _T_88) @[el2_dec_dec_ctl.scala 77:41] - node _T_90 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_91 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_92 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_94 = and(_T_90, _T_91) @[el2_dec_dec_ctl.scala 78:37] - node _T_95 = and(_T_94, _T_93) @[el2_dec_dec_ctl.scala 78:37] - node _T_96 = or(_T_89, _T_95) @[el2_dec_dec_ctl.scala 77:79] - node _T_97 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_99 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_101 = and(_T_98, _T_100) @[el2_dec_dec_ctl.scala 78:71] - node _T_102 = or(_T_96, _T_101) @[el2_dec_dec_ctl.scala 78:41] - node _T_103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_104 = eq(_T_103, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_105 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_106 = eq(_T_105, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_107 = and(_T_104, _T_106) @[el2_dec_dec_ctl.scala 78:106] - node _T_108 = or(_T_102, _T_107) @[el2_dec_dec_ctl.scala 78:75] - io.out.rs1 <= _T_108 @[el2_dec_dec_ctl.scala 73:14] - node _T_109 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_112 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_114 = and(_T_109, _T_111) @[el2_dec_dec_ctl.scala 79:48] - node _T_115 = and(_T_114, _T_113) @[el2_dec_dec_ctl.scala 79:48] - node _T_116 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_118 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_119 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_121 = and(_T_117, _T_118) @[el2_dec_dec_ctl.scala 79:85] - node _T_122 = and(_T_121, _T_120) @[el2_dec_dec_ctl.scala 79:85] - node _T_123 = or(_T_115, _T_122) @[el2_dec_dec_ctl.scala 79:52] - io.out.rs2 <= _T_123 @[el2_dec_dec_ctl.scala 79:14] - node _T_124 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_126 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_127 = eq(_T_126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_128 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_129 = and(_T_125, _T_127) @[el2_dec_dec_ctl.scala 80:50] - node _T_130 = and(_T_129, _T_128) @[el2_dec_dec_ctl.scala 80:50] - node _T_131 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_132 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_134 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_135 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_137 = and(_T_131, _T_133) @[el2_dec_dec_ctl.scala 80:90] - node _T_138 = and(_T_137, _T_134) @[el2_dec_dec_ctl.scala 80:90] - node _T_139 = and(_T_138, _T_136) @[el2_dec_dec_ctl.scala 80:90] - node _T_140 = or(_T_130, _T_139) @[el2_dec_dec_ctl.scala 80:54] - node _T_141 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_142 = eq(_T_141, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_143 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_144 = eq(_T_143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_145 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_146 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_147 = and(_T_142, _T_144) @[el2_dec_dec_ctl.scala 81:40] - node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 81:40] - node _T_149 = and(_T_148, _T_146) @[el2_dec_dec_ctl.scala 81:40] - node _T_150 = or(_T_140, _T_149) @[el2_dec_dec_ctl.scala 80:94] - node _T_151 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_153 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_155 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_156 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_157 = eq(_T_156, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_158 = and(_T_152, _T_154) @[el2_dec_dec_ctl.scala 81:81] - node _T_159 = and(_T_158, _T_155) @[el2_dec_dec_ctl.scala 81:81] - node _T_160 = and(_T_159, _T_157) @[el2_dec_dec_ctl.scala 81:81] - node _T_161 = or(_T_150, _T_160) @[el2_dec_dec_ctl.scala 81:44] - io.out.imm12 <= _T_161 @[el2_dec_dec_ctl.scala 80:16] - node _T_162 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:24] - node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:17] - node _T_164 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:37] - node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:30] - node _T_166 = and(_T_163, _T_165) @[el2_dec_dec_ctl.scala 82:28] - node _T_167 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:51] - node _T_168 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:63] - node _T_169 = and(_T_167, _T_168) @[el2_dec_dec_ctl.scala 82:55] - node _T_170 = or(_T_166, _T_169) @[el2_dec_dec_ctl.scala 82:42] - node _T_171 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 82:76] - node _T_172 = or(_T_170, _T_171) @[el2_dec_dec_ctl.scala 82:68] - io.out.rd <= _T_172 @[el2_dec_dec_ctl.scala 82:13] - node _T_173 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_175 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_176 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_178 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_179 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_181 = and(_T_174, _T_175) @[el2_dec_dec_ctl.scala 83:58] - node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 83:58] - node _T_183 = and(_T_182, _T_178) @[el2_dec_dec_ctl.scala 83:58] - node _T_184 = and(_T_183, _T_180) @[el2_dec_dec_ctl.scala 83:58] - io.out.shimm5 <= _T_184 @[el2_dec_dec_ctl.scala 83:17] - node _T_185 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 84:26] - node _T_186 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 84:36] - node _T_187 = and(_T_185, _T_186) @[el2_dec_dec_ctl.scala 84:29] - node _T_188 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 84:50] - node _T_189 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 84:60] - node _T_190 = and(_T_188, _T_189) @[el2_dec_dec_ctl.scala 84:53] - node _T_191 = or(_T_187, _T_190) @[el2_dec_dec_ctl.scala 84:41] - io.out.imm20 <= _T_191 @[el2_dec_dec_ctl.scala 84:16] - node _T_192 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:24] - node _T_193 = eq(_T_192, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:17] - node _T_194 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:37] - node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:30] - node _T_196 = and(_T_193, _T_195) @[el2_dec_dec_ctl.scala 85:28] - node _T_197 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 85:49] - node _T_198 = and(_T_196, _T_197) @[el2_dec_dec_ctl.scala 85:41] - node _T_199 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:63] - node _T_200 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:75] - node _T_201 = and(_T_199, _T_200) @[el2_dec_dec_ctl.scala 85:67] - node _T_202 = or(_T_198, _T_201) @[el2_dec_dec_ctl.scala 85:54] - io.out.pc <= _T_202 @[el2_dec_dec_ctl.scala 85:13] - node _T_203 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_204 = eq(_T_203, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_205 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_207 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_209 = and(_T_204, _T_206) @[el2_dec_dec_ctl.scala 86:50] - node _T_210 = and(_T_209, _T_208) @[el2_dec_dec_ctl.scala 86:50] - io.out.load <= _T_210 @[el2_dec_dec_ctl.scala 86:15] - node _T_211 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_213 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_216 = and(_T_212, _T_213) @[el2_dec_dec_ctl.scala 87:50] - node _T_217 = and(_T_216, _T_215) @[el2_dec_dec_ctl.scala 87:50] - io.out.store <= _T_217 @[el2_dec_dec_ctl.scala 87:16] - node _T_218 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_219 = eq(_T_218, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_220 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_221 = eq(_T_220, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_222 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_223 = eq(_T_222, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_224 = and(_T_219, _T_221) @[el2_dec_dec_ctl.scala 88:49] - node _T_225 = and(_T_224, _T_223) @[el2_dec_dec_ctl.scala 88:49] - io.out.lsu <= _T_225 @[el2_dec_dec_ctl.scala 88:14] - node _T_226 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_228 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_230 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_232 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_234 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_235 = and(_T_227, _T_229) @[el2_dec_dec_ctl.scala 89:57] - node _T_236 = and(_T_235, _T_231) @[el2_dec_dec_ctl.scala 89:57] - node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 89:57] - node _T_238 = and(_T_237, _T_234) @[el2_dec_dec_ctl.scala 89:57] - node _T_239 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_241 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_243 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_244 = and(_T_240, _T_242) @[el2_dec_dec_ctl.scala 89:94] - node _T_245 = and(_T_244, _T_243) @[el2_dec_dec_ctl.scala 89:94] - node _T_246 = or(_T_238, _T_245) @[el2_dec_dec_ctl.scala 89:61] - node _T_247 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_249 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_250 = eq(_T_249, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_251 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_253 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_254 = eq(_T_253, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_255 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_257 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_259 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_260 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_261 = eq(_T_260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_262 = and(_T_248, _T_250) @[el2_dec_dec_ctl.scala 90:56] - node _T_263 = and(_T_262, _T_252) @[el2_dec_dec_ctl.scala 90:56] - node _T_264 = and(_T_263, _T_254) @[el2_dec_dec_ctl.scala 90:56] - node _T_265 = and(_T_264, _T_256) @[el2_dec_dec_ctl.scala 90:56] - node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 90:56] - node _T_267 = and(_T_266, _T_259) @[el2_dec_dec_ctl.scala 90:56] - node _T_268 = and(_T_267, _T_261) @[el2_dec_dec_ctl.scala 90:56] - node _T_269 = or(_T_246, _T_268) @[el2_dec_dec_ctl.scala 89:98] - io.out.add <= _T_269 @[el2_dec_dec_ctl.scala 89:14] - node _T_270 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] - node _T_271 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_272 = eq(_T_271, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_273 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_274 = eq(_T_273, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_275 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_276 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_279 = and(_T_270, _T_272) @[el2_dec_dec_ctl.scala 91:57] - node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 91:57] - node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 91:57] - node _T_282 = and(_T_281, _T_276) @[el2_dec_dec_ctl.scala 91:57] - node _T_283 = and(_T_282, _T_278) @[el2_dec_dec_ctl.scala 91:57] - node _T_284 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_286 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_288 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_289 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_290 = eq(_T_289, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_291 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_292 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_294 = and(_T_285, _T_287) @[el2_dec_dec_ctl.scala 91:105] - node _T_295 = and(_T_294, _T_288) @[el2_dec_dec_ctl.scala 91:105] - node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 91:105] - node _T_297 = and(_T_296, _T_291) @[el2_dec_dec_ctl.scala 91:105] - node _T_298 = and(_T_297, _T_293) @[el2_dec_dec_ctl.scala 91:105] - node _T_299 = or(_T_283, _T_298) @[el2_dec_dec_ctl.scala 91:61] - node _T_300 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_302 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_303 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_304 = eq(_T_303, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_305 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_306 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_308 = and(_T_301, _T_302) @[el2_dec_dec_ctl.scala 92:43] - node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 92:43] - node _T_310 = and(_T_309, _T_305) @[el2_dec_dec_ctl.scala 92:43] - node _T_311 = and(_T_310, _T_307) @[el2_dec_dec_ctl.scala 92:43] - node _T_312 = or(_T_299, _T_311) @[el2_dec_dec_ctl.scala 91:109] - node _T_313 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_314 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_316 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_318 = and(_T_313, _T_315) @[el2_dec_dec_ctl.scala 92:80] - node _T_319 = and(_T_318, _T_317) @[el2_dec_dec_ctl.scala 92:80] - node _T_320 = or(_T_312, _T_319) @[el2_dec_dec_ctl.scala 92:47] - io.out.sub <= _T_320 @[el2_dec_dec_ctl.scala 91:14] - node _T_321 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_322 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_323 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_324 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_326 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_328 = and(_T_321, _T_322) @[el2_dec_dec_ctl.scala 93:56] - node _T_329 = and(_T_328, _T_323) @[el2_dec_dec_ctl.scala 93:56] - node _T_330 = and(_T_329, _T_325) @[el2_dec_dec_ctl.scala 93:56] - node _T_331 = and(_T_330, _T_327) @[el2_dec_dec_ctl.scala 93:56] - node _T_332 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_334 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_335 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_336 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_337 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_339 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_341 = and(_T_333, _T_334) @[el2_dec_dec_ctl.scala 93:104] - node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 93:104] - node _T_343 = and(_T_342, _T_336) @[el2_dec_dec_ctl.scala 93:104] - node _T_344 = and(_T_343, _T_338) @[el2_dec_dec_ctl.scala 93:104] - node _T_345 = and(_T_344, _T_340) @[el2_dec_dec_ctl.scala 93:104] - node _T_346 = or(_T_331, _T_345) @[el2_dec_dec_ctl.scala 93:60] - io.out.land <= _T_346 @[el2_dec_dec_ctl.scala 93:15] - node _T_347 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_348 = eq(_T_347, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_349 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_350 = and(_T_348, _T_349) @[el2_dec_dec_ctl.scala 94:45] - node _T_351 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_353 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_354 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_355 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_356 = eq(_T_355, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_357 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_358 = eq(_T_357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_360 = eq(_T_359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_361 = and(_T_352, _T_353) @[el2_dec_dec_ctl.scala 94:94] - node _T_362 = and(_T_361, _T_354) @[el2_dec_dec_ctl.scala 94:94] - node _T_363 = and(_T_362, _T_356) @[el2_dec_dec_ctl.scala 94:94] - node _T_364 = and(_T_363, _T_358) @[el2_dec_dec_ctl.scala 94:94] - node _T_365 = and(_T_364, _T_360) @[el2_dec_dec_ctl.scala 94:94] - node _T_366 = or(_T_350, _T_365) @[el2_dec_dec_ctl.scala 94:49] - node _T_367 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_368 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_369 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_370 = and(_T_367, _T_368) @[el2_dec_dec_ctl.scala 95:34] - node _T_371 = and(_T_370, _T_369) @[el2_dec_dec_ctl.scala 95:34] - node _T_372 = or(_T_366, _T_371) @[el2_dec_dec_ctl.scala 94:98] - node _T_373 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_374 = eq(_T_373, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_375 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_377 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_378 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_379 = and(_T_374, _T_376) @[el2_dec_dec_ctl.scala 95:75] - node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 95:75] - node _T_381 = and(_T_380, _T_378) @[el2_dec_dec_ctl.scala 95:75] - node _T_382 = or(_T_372, _T_381) @[el2_dec_dec_ctl.scala 95:38] - node _T_383 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_384 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_385 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_387 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_389 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_391 = and(_T_383, _T_384) @[el2_dec_dec_ctl.scala 96:44] - node _T_392 = and(_T_391, _T_386) @[el2_dec_dec_ctl.scala 96:44] - node _T_393 = and(_T_392, _T_388) @[el2_dec_dec_ctl.scala 96:44] - node _T_394 = and(_T_393, _T_390) @[el2_dec_dec_ctl.scala 96:44] - node _T_395 = or(_T_382, _T_394) @[el2_dec_dec_ctl.scala 95:79] - io.out.lor <= _T_395 @[el2_dec_dec_ctl.scala 94:14] - node _T_396 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_398 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_399 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_401 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_403 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_404 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_405 = eq(_T_404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_406 = and(_T_397, _T_398) @[el2_dec_dec_ctl.scala 97:61] - node _T_407 = and(_T_406, _T_400) @[el2_dec_dec_ctl.scala 97:61] - node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 97:61] - node _T_409 = and(_T_408, _T_403) @[el2_dec_dec_ctl.scala 97:61] - node _T_410 = and(_T_409, _T_405) @[el2_dec_dec_ctl.scala 97:61] - node _T_411 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_412 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_414 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_415 = eq(_T_414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_416 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_418 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_419 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_421 = and(_T_411, _T_413) @[el2_dec_dec_ctl.scala 97:109] - node _T_422 = and(_T_421, _T_415) @[el2_dec_dec_ctl.scala 97:109] - node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 97:109] - node _T_424 = and(_T_423, _T_418) @[el2_dec_dec_ctl.scala 97:109] - node _T_425 = and(_T_424, _T_420) @[el2_dec_dec_ctl.scala 97:109] - node _T_426 = or(_T_410, _T_425) @[el2_dec_dec_ctl.scala 97:65] - io.out.lxor <= _T_426 @[el2_dec_dec_ctl.scala 97:15] - node _T_427 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_428 = eq(_T_427, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_429 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_431 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_433 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_434 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_436 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_437 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_438 = eq(_T_437, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_439 = and(_T_428, _T_430) @[el2_dec_dec_ctl.scala 98:63] - node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 98:63] - node _T_441 = and(_T_440, _T_433) @[el2_dec_dec_ctl.scala 98:63] - node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 98:63] - node _T_443 = and(_T_442, _T_436) @[el2_dec_dec_ctl.scala 98:63] - node _T_444 = and(_T_443, _T_438) @[el2_dec_dec_ctl.scala 98:63] - io.out.sll <= _T_444 @[el2_dec_dec_ctl.scala 98:14] - node _T_445 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] - node _T_446 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_447 = eq(_T_446, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_448 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_449 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_450 = eq(_T_449, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_451 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_452 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_454 = and(_T_445, _T_447) @[el2_dec_dec_ctl.scala 99:58] - node _T_455 = and(_T_454, _T_448) @[el2_dec_dec_ctl.scala 99:58] - node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 99:58] - node _T_457 = and(_T_456, _T_451) @[el2_dec_dec_ctl.scala 99:58] - node _T_458 = and(_T_457, _T_453) @[el2_dec_dec_ctl.scala 99:58] - io.out.sra <= _T_458 @[el2_dec_dec_ctl.scala 99:14] - node _T_459 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_461 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_463 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_464 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_466 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_467 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_469 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_470 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_471 = eq(_T_470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_472 = and(_T_460, _T_462) @[el2_dec_dec_ctl.scala 100:66] - node _T_473 = and(_T_472, _T_463) @[el2_dec_dec_ctl.scala 100:66] - node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 100:66] - node _T_475 = and(_T_474, _T_466) @[el2_dec_dec_ctl.scala 100:66] - node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 100:66] - node _T_477 = and(_T_476, _T_469) @[el2_dec_dec_ctl.scala 100:66] - node _T_478 = and(_T_477, _T_471) @[el2_dec_dec_ctl.scala 100:66] - io.out.srl <= _T_478 @[el2_dec_dec_ctl.scala 100:14] - node _T_479 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_480 = eq(_T_479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_481 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_482 = eq(_T_481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_483 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_484 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_485 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_487 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_488 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_490 = and(_T_480, _T_482) @[el2_dec_dec_ctl.scala 101:62] - node _T_491 = and(_T_490, _T_483) @[el2_dec_dec_ctl.scala 101:62] - node _T_492 = and(_T_491, _T_484) @[el2_dec_dec_ctl.scala 101:62] - node _T_493 = and(_T_492, _T_486) @[el2_dec_dec_ctl.scala 101:62] - node _T_494 = and(_T_493, _T_487) @[el2_dec_dec_ctl.scala 101:62] - node _T_495 = and(_T_494, _T_489) @[el2_dec_dec_ctl.scala 101:62] - node _T_496 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_498 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_499 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_501 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_502 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_503 = eq(_T_502, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_504 = and(_T_497, _T_498) @[el2_dec_dec_ctl.scala 101:106] - node _T_505 = and(_T_504, _T_500) @[el2_dec_dec_ctl.scala 101:106] - node _T_506 = and(_T_505, _T_501) @[el2_dec_dec_ctl.scala 101:106] - node _T_507 = and(_T_506, _T_503) @[el2_dec_dec_ctl.scala 101:106] - node _T_508 = or(_T_495, _T_507) @[el2_dec_dec_ctl.scala 101:66] - io.out.slt <= _T_508 @[el2_dec_dec_ctl.scala 101:14] - node _T_509 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_510 = eq(_T_509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_511 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_512 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_513 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_515 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_516 = eq(_T_515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_517 = and(_T_510, _T_511) @[el2_dec_dec_ctl.scala 102:59] - node _T_518 = and(_T_517, _T_512) @[el2_dec_dec_ctl.scala 102:59] - node _T_519 = and(_T_518, _T_514) @[el2_dec_dec_ctl.scala 102:59] - node _T_520 = and(_T_519, _T_516) @[el2_dec_dec_ctl.scala 102:59] - node _T_521 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_522 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_523 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_524 = eq(_T_523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_525 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_527 = and(_T_521, _T_522) @[el2_dec_dec_ctl.scala 102:99] - node _T_528 = and(_T_527, _T_524) @[el2_dec_dec_ctl.scala 102:99] - node _T_529 = and(_T_528, _T_526) @[el2_dec_dec_ctl.scala 102:99] - node _T_530 = or(_T_520, _T_529) @[el2_dec_dec_ctl.scala 102:63] - node _T_531 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_532 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_534 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_536 = and(_T_531, _T_533) @[el2_dec_dec_ctl.scala 103:37] - node _T_537 = and(_T_536, _T_535) @[el2_dec_dec_ctl.scala 103:37] - node _T_538 = or(_T_530, _T_537) @[el2_dec_dec_ctl.scala 102:103] - node _T_539 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_540 = eq(_T_539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_541 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_543 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_544 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_545 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_547 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_549 = and(_T_540, _T_542) @[el2_dec_dec_ctl.scala 103:86] - node _T_550 = and(_T_549, _T_543) @[el2_dec_dec_ctl.scala 103:86] - node _T_551 = and(_T_550, _T_544) @[el2_dec_dec_ctl.scala 103:86] - node _T_552 = and(_T_551, _T_546) @[el2_dec_dec_ctl.scala 103:86] - node _T_553 = and(_T_552, _T_548) @[el2_dec_dec_ctl.scala 103:86] - node _T_554 = or(_T_538, _T_553) @[el2_dec_dec_ctl.scala 103:41] - node _T_555 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_556 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_557 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_558 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_560 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_561 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_563 = and(_T_555, _T_556) @[el2_dec_dec_ctl.scala 104:45] - node _T_564 = and(_T_563, _T_557) @[el2_dec_dec_ctl.scala 104:45] - node _T_565 = and(_T_564, _T_559) @[el2_dec_dec_ctl.scala 104:45] - node _T_566 = and(_T_565, _T_560) @[el2_dec_dec_ctl.scala 104:45] - node _T_567 = and(_T_566, _T_562) @[el2_dec_dec_ctl.scala 104:45] - node _T_568 = or(_T_554, _T_567) @[el2_dec_dec_ctl.scala 103:90] - io.out.unsign <= _T_568 @[el2_dec_dec_ctl.scala 102:17] - node _T_569 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_570 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_571 = eq(_T_570, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_572 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_573 = eq(_T_572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_574 = and(_T_569, _T_571) @[el2_dec_dec_ctl.scala 105:51] - node _T_575 = and(_T_574, _T_573) @[el2_dec_dec_ctl.scala 105:51] - io.out.condbr <= _T_575 @[el2_dec_dec_ctl.scala 105:17] - node _T_576 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_577 = eq(_T_576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_578 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_580 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_581 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_583 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_584 = eq(_T_583, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_585 = and(_T_577, _T_579) @[el2_dec_dec_ctl.scala 106:56] - node _T_586 = and(_T_585, _T_580) @[el2_dec_dec_ctl.scala 106:56] - node _T_587 = and(_T_586, _T_582) @[el2_dec_dec_ctl.scala 106:56] - node _T_588 = and(_T_587, _T_584) @[el2_dec_dec_ctl.scala 106:56] - io.out.beq <= _T_588 @[el2_dec_dec_ctl.scala 106:14] - node _T_589 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_590 = eq(_T_589, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_591 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_592 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_593 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_594 = eq(_T_593, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_595 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_597 = and(_T_590, _T_591) @[el2_dec_dec_ctl.scala 107:55] - node _T_598 = and(_T_597, _T_592) @[el2_dec_dec_ctl.scala 107:55] - node _T_599 = and(_T_598, _T_594) @[el2_dec_dec_ctl.scala 107:55] - node _T_600 = and(_T_599, _T_596) @[el2_dec_dec_ctl.scala 107:55] - io.out.bne <= _T_600 @[el2_dec_dec_ctl.scala 107:14] - node _T_601 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_602 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_603 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_604 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_606 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_608 = and(_T_601, _T_602) @[el2_dec_dec_ctl.scala 108:54] - node _T_609 = and(_T_608, _T_603) @[el2_dec_dec_ctl.scala 108:54] - node _T_610 = and(_T_609, _T_605) @[el2_dec_dec_ctl.scala 108:54] - node _T_611 = and(_T_610, _T_607) @[el2_dec_dec_ctl.scala 108:54] - io.out.bge <= _T_611 @[el2_dec_dec_ctl.scala 108:14] - node _T_612 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_613 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_615 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_616 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_617 = eq(_T_616, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_618 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_620 = and(_T_612, _T_614) @[el2_dec_dec_ctl.scala 109:55] - node _T_621 = and(_T_620, _T_615) @[el2_dec_dec_ctl.scala 109:55] - node _T_622 = and(_T_621, _T_617) @[el2_dec_dec_ctl.scala 109:55] - node _T_623 = and(_T_622, _T_619) @[el2_dec_dec_ctl.scala 109:55] - io.out.blt <= _T_623 @[el2_dec_dec_ctl.scala 109:14] - node _T_624 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_625 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_626 = and(_T_624, _T_625) @[el2_dec_dec_ctl.scala 110:44] - io.out.jal <= _T_626 @[el2_dec_dec_ctl.scala 110:14] - node _T_627 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_628 = eq(_T_627, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_629 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_631 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_632 = eq(_T_631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_633 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_635 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_636 = eq(_T_635, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_637 = and(_T_628, _T_630) @[el2_dec_dec_ctl.scala 111:56] - node _T_638 = and(_T_637, _T_632) @[el2_dec_dec_ctl.scala 111:56] - node _T_639 = and(_T_638, _T_634) @[el2_dec_dec_ctl.scala 111:56] - node _T_640 = and(_T_639, _T_636) @[el2_dec_dec_ctl.scala 111:56] - io.out.by <= _T_640 @[el2_dec_dec_ctl.scala 111:13] - node _T_641 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_642 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_644 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_646 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_647 = eq(_T_646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_648 = and(_T_641, _T_643) @[el2_dec_dec_ctl.scala 112:53] - node _T_649 = and(_T_648, _T_645) @[el2_dec_dec_ctl.scala 112:53] - node _T_650 = and(_T_649, _T_647) @[el2_dec_dec_ctl.scala 112:53] - io.out.half <= _T_650 @[el2_dec_dec_ctl.scala 112:15] - node _T_651 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_652 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_654 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_656 = and(_T_651, _T_653) @[el2_dec_dec_ctl.scala 113:50] - node _T_657 = and(_T_656, _T_655) @[el2_dec_dec_ctl.scala 113:50] - io.out.word <= _T_657 @[el2_dec_dec_ctl.scala 113:15] - node _T_658 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_659 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_660 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_661 = and(_T_658, _T_659) @[el2_dec_dec_ctl.scala 114:52] - node _T_662 = and(_T_661, _T_660) @[el2_dec_dec_ctl.scala 114:52] - node _T_663 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_664 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_665 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_666 = and(_T_663, _T_664) @[el2_dec_dec_ctl.scala 114:87] - node _T_667 = and(_T_666, _T_665) @[el2_dec_dec_ctl.scala 114:87] - node _T_668 = or(_T_662, _T_667) @[el2_dec_dec_ctl.scala 114:56] - node _T_669 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_670 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_672 = and(_T_669, _T_670) @[el2_dec_dec_ctl.scala 115:34] - node _T_673 = and(_T_672, _T_671) @[el2_dec_dec_ctl.scala 115:34] - node _T_674 = or(_T_668, _T_673) @[el2_dec_dec_ctl.scala 114:91] - node _T_675 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_676 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_677 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_678 = and(_T_675, _T_676) @[el2_dec_dec_ctl.scala 115:69] - node _T_679 = and(_T_678, _T_677) @[el2_dec_dec_ctl.scala 115:69] - node _T_680 = or(_T_674, _T_679) @[el2_dec_dec_ctl.scala 115:38] - node _T_681 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_682 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_683 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_684 = and(_T_681, _T_682) @[el2_dec_dec_ctl.scala 115:105] - node _T_685 = and(_T_684, _T_683) @[el2_dec_dec_ctl.scala 115:105] - node _T_686 = or(_T_680, _T_685) @[el2_dec_dec_ctl.scala 115:73] - node _T_687 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_688 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_690 = and(_T_687, _T_688) @[el2_dec_dec_ctl.scala 116:35] - node _T_691 = and(_T_690, _T_689) @[el2_dec_dec_ctl.scala 116:35] - node _T_692 = or(_T_686, _T_691) @[el2_dec_dec_ctl.scala 115:109] - io.out.csr_read <= _T_692 @[el2_dec_dec_ctl.scala 114:19] - node _T_693 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_694 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_695 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_696 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_697 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_698 = and(_T_693, _T_694) @[el2_dec_dec_ctl.scala 117:57] - node _T_699 = and(_T_698, _T_695) @[el2_dec_dec_ctl.scala 117:57] - node _T_700 = and(_T_699, _T_696) @[el2_dec_dec_ctl.scala 117:57] - node _T_701 = and(_T_700, _T_697) @[el2_dec_dec_ctl.scala 117:57] - node _T_702 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_703 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_704 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_705 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_706 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_707 = and(_T_702, _T_703) @[el2_dec_dec_ctl.scala 117:99] - node _T_708 = and(_T_707, _T_704) @[el2_dec_dec_ctl.scala 117:99] - node _T_709 = and(_T_708, _T_705) @[el2_dec_dec_ctl.scala 117:99] - node _T_710 = and(_T_709, _T_706) @[el2_dec_dec_ctl.scala 117:99] - node _T_711 = or(_T_701, _T_710) @[el2_dec_dec_ctl.scala 117:61] - node _T_712 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_713 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_714 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_715 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_716 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_717 = and(_T_712, _T_713) @[el2_dec_dec_ctl.scala 118:41] - node _T_718 = and(_T_717, _T_714) @[el2_dec_dec_ctl.scala 118:41] - node _T_719 = and(_T_718, _T_715) @[el2_dec_dec_ctl.scala 118:41] - node _T_720 = and(_T_719, _T_716) @[el2_dec_dec_ctl.scala 118:41] - node _T_721 = or(_T_711, _T_720) @[el2_dec_dec_ctl.scala 117:103] - node _T_722 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_723 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_724 = eq(_T_723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_725 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_726 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_727 = and(_T_722, _T_724) @[el2_dec_dec_ctl.scala 118:81] - node _T_728 = and(_T_727, _T_725) @[el2_dec_dec_ctl.scala 118:81] - node _T_729 = and(_T_728, _T_726) @[el2_dec_dec_ctl.scala 118:81] - node _T_730 = or(_T_721, _T_729) @[el2_dec_dec_ctl.scala 118:45] - node _T_731 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_732 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_733 = eq(_T_732, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_734 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_735 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_736 = and(_T_731, _T_733) @[el2_dec_dec_ctl.scala 119:39] - node _T_737 = and(_T_736, _T_734) @[el2_dec_dec_ctl.scala 119:39] - node _T_738 = and(_T_737, _T_735) @[el2_dec_dec_ctl.scala 119:39] - node _T_739 = or(_T_730, _T_738) @[el2_dec_dec_ctl.scala 118:85] - io.out.csr_clr <= _T_739 @[el2_dec_dec_ctl.scala 117:18] - node _T_740 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_741 = eq(_T_740, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_742 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_743 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_744 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_745 = and(_T_741, _T_742) @[el2_dec_dec_ctl.scala 120:57] - node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 120:57] - node _T_747 = and(_T_746, _T_744) @[el2_dec_dec_ctl.scala 120:57] - io.out.csr_write <= _T_747 @[el2_dec_dec_ctl.scala 120:20] - node _T_748 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_749 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_750 = eq(_T_749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_752 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_753 = and(_T_748, _T_750) @[el2_dec_dec_ctl.scala 121:55] - node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 121:55] - node _T_755 = and(_T_754, _T_752) @[el2_dec_dec_ctl.scala 121:55] - node _T_756 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_757 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_758 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_759 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_760 = and(_T_756, _T_757) @[el2_dec_dec_ctl.scala 121:94] - node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 121:94] - node _T_762 = and(_T_761, _T_759) @[el2_dec_dec_ctl.scala 121:94] - node _T_763 = or(_T_755, _T_762) @[el2_dec_dec_ctl.scala 121:59] - node _T_764 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_765 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_766 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_767 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_768 = and(_T_764, _T_765) @[el2_dec_dec_ctl.scala 122:38] - node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 122:38] - node _T_770 = and(_T_769, _T_767) @[el2_dec_dec_ctl.scala 122:38] - node _T_771 = or(_T_763, _T_770) @[el2_dec_dec_ctl.scala 121:98] - node _T_772 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_773 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_774 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_775 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_776 = and(_T_772, _T_773) @[el2_dec_dec_ctl.scala 122:77] - node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 122:77] - node _T_778 = and(_T_777, _T_775) @[el2_dec_dec_ctl.scala 122:77] - node _T_779 = or(_T_771, _T_778) @[el2_dec_dec_ctl.scala 122:42] - node _T_780 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_781 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_782 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_783 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_784 = and(_T_780, _T_781) @[el2_dec_dec_ctl.scala 123:38] - node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 123:38] - node _T_786 = and(_T_785, _T_783) @[el2_dec_dec_ctl.scala 123:38] - node _T_787 = or(_T_779, _T_786) @[el2_dec_dec_ctl.scala 122:81] - node _T_788 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_789 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_790 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_791 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_792 = and(_T_788, _T_789) @[el2_dec_dec_ctl.scala 123:77] - node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 123:77] - node _T_794 = and(_T_793, _T_791) @[el2_dec_dec_ctl.scala 123:77] - node _T_795 = or(_T_787, _T_794) @[el2_dec_dec_ctl.scala 123:42] - io.out.csr_imm <= _T_795 @[el2_dec_dec_ctl.scala 121:18] - node _T_796 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_797 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_799 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_800 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_801 = and(_T_796, _T_798) @[el2_dec_dec_ctl.scala 124:55] - node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 124:55] - node _T_803 = and(_T_802, _T_800) @[el2_dec_dec_ctl.scala 124:55] - node _T_804 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_805 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_806 = eq(_T_805, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_807 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_808 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_809 = and(_T_804, _T_806) @[el2_dec_dec_ctl.scala 124:95] - node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 124:95] - node _T_811 = and(_T_810, _T_808) @[el2_dec_dec_ctl.scala 124:95] - node _T_812 = or(_T_803, _T_811) @[el2_dec_dec_ctl.scala 124:59] - node _T_813 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_815 = eq(_T_814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_816 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_817 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_818 = and(_T_813, _T_815) @[el2_dec_dec_ctl.scala 125:39] - node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 125:39] - node _T_820 = and(_T_819, _T_817) @[el2_dec_dec_ctl.scala 125:39] - node _T_821 = or(_T_812, _T_820) @[el2_dec_dec_ctl.scala 124:99] - node _T_822 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_823 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_824 = eq(_T_823, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_825 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_826 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_827 = and(_T_822, _T_824) @[el2_dec_dec_ctl.scala 125:79] - node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 125:79] - node _T_829 = and(_T_828, _T_826) @[el2_dec_dec_ctl.scala 125:79] - node _T_830 = or(_T_821, _T_829) @[el2_dec_dec_ctl.scala 125:43] - node _T_831 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_832 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_834 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_835 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_836 = and(_T_831, _T_833) @[el2_dec_dec_ctl.scala 126:39] - node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 126:39] - node _T_838 = and(_T_837, _T_835) @[el2_dec_dec_ctl.scala 126:39] - node _T_839 = or(_T_830, _T_838) @[el2_dec_dec_ctl.scala 125:83] - io.out.csr_set <= _T_839 @[el2_dec_dec_ctl.scala 124:18] - node _T_840 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_841 = eq(_T_840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_842 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] - node _T_843 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_845 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_846 = eq(_T_845, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_847 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_848 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_849 = and(_T_841, _T_842) @[el2_dec_dec_ctl.scala 127:62] - node _T_850 = and(_T_849, _T_844) @[el2_dec_dec_ctl.scala 127:62] - node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 127:62] - node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 127:62] - node _T_853 = and(_T_852, _T_848) @[el2_dec_dec_ctl.scala 127:62] - io.out.ebreak <= _T_853 @[el2_dec_dec_ctl.scala 127:17] - node _T_854 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_856 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] - node _T_857 = eq(_T_856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_858 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_859 = eq(_T_858, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_860 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_861 = eq(_T_860, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_862 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_864 = and(_T_855, _T_857) @[el2_dec_dec_ctl.scala 128:62] - node _T_865 = and(_T_864, _T_859) @[el2_dec_dec_ctl.scala 128:62] - node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 128:62] - node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 128:62] - node _T_868 = and(_T_867, _T_863) @[el2_dec_dec_ctl.scala 128:62] - io.out.ecall <= _T_868 @[el2_dec_dec_ctl.scala 128:16] - node _T_869 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] - node _T_870 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_872 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_873 = eq(_T_872, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_874 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_875 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_876 = and(_T_869, _T_871) @[el2_dec_dec_ctl.scala 129:56] - node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 129:56] - node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 129:56] - node _T_879 = and(_T_878, _T_875) @[el2_dec_dec_ctl.scala 129:56] - io.out.mret <= _T_879 @[el2_dec_dec_ctl.scala 129:15] - node _T_880 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_881 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_883 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_885 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_886 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_887 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_888 = eq(_T_887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_889 = and(_T_880, _T_882) @[el2_dec_dec_ctl.scala 130:57] - node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 130:57] - node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 130:57] - node _T_892 = and(_T_891, _T_886) @[el2_dec_dec_ctl.scala 130:57] - node _T_893 = and(_T_892, _T_888) @[el2_dec_dec_ctl.scala 130:57] - io.out.mul <= _T_893 @[el2_dec_dec_ctl.scala 130:14] - node _T_894 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_895 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_896 = eq(_T_895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_897 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_898 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_902 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_903 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_904 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_905 = eq(_T_904, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_906 = and(_T_894, _T_896) @[el2_dec_dec_ctl.scala 131:69] - node _T_907 = and(_T_906, _T_897) @[el2_dec_dec_ctl.scala 131:69] - node _T_908 = and(_T_907, _T_899) @[el2_dec_dec_ctl.scala 131:69] - node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 131:69] - node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 131:69] - node _T_911 = and(_T_910, _T_903) @[el2_dec_dec_ctl.scala 131:69] - node _T_912 = and(_T_911, _T_905) @[el2_dec_dec_ctl.scala 131:69] - node _T_913 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_914 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_915 = eq(_T_914, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_916 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_917 = eq(_T_916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_918 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_919 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_921 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_922 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_923 = eq(_T_922, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_924 = and(_T_913, _T_915) @[el2_dec_dec_ctl.scala 132:50] - node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 132:50] - node _T_926 = and(_T_925, _T_918) @[el2_dec_dec_ctl.scala 132:50] - node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 132:50] - node _T_928 = and(_T_927, _T_921) @[el2_dec_dec_ctl.scala 132:50] - node _T_929 = and(_T_928, _T_923) @[el2_dec_dec_ctl.scala 132:50] - node _T_930 = or(_T_912, _T_929) @[el2_dec_dec_ctl.scala 131:73] - io.out.rs1_sign <= _T_930 @[el2_dec_dec_ctl.scala 131:19] - node _T_931 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_934 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_935 = eq(_T_934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_936 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_937 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_938 = eq(_T_937, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_939 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_940 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_942 = and(_T_931, _T_933) @[el2_dec_dec_ctl.scala 133:67] - node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 133:67] - node _T_944 = and(_T_943, _T_936) @[el2_dec_dec_ctl.scala 133:67] - node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 133:67] - node _T_946 = and(_T_945, _T_939) @[el2_dec_dec_ctl.scala 133:67] - node _T_947 = and(_T_946, _T_941) @[el2_dec_dec_ctl.scala 133:67] - io.out.rs2_sign <= _T_947 @[el2_dec_dec_ctl.scala 133:19] - node _T_948 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_949 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_950 = eq(_T_949, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_951 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_952 = eq(_T_951, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_953 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_955 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_957 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_959 = and(_T_948, _T_950) @[el2_dec_dec_ctl.scala 134:62] - node _T_960 = and(_T_959, _T_952) @[el2_dec_dec_ctl.scala 134:62] - node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 134:62] - node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 134:62] - node _T_963 = and(_T_962, _T_956) @[el2_dec_dec_ctl.scala 134:62] - node _T_964 = and(_T_963, _T_958) @[el2_dec_dec_ctl.scala 134:62] - io.out.low <= _T_964 @[el2_dec_dec_ctl.scala 134:14] - node _T_965 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_966 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_969 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_970 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_971 = eq(_T_970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_972 = and(_T_965, _T_966) @[el2_dec_dec_ctl.scala 135:54] - node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 135:54] - node _T_974 = and(_T_973, _T_969) @[el2_dec_dec_ctl.scala 135:54] - node _T_975 = and(_T_974, _T_971) @[el2_dec_dec_ctl.scala 135:54] - io.out.div <= _T_975 @[el2_dec_dec_ctl.scala 135:14] - node _T_976 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_977 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_978 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_979 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_981 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_982 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_983 = eq(_T_982, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_984 = and(_T_976, _T_977) @[el2_dec_dec_ctl.scala 136:57] - node _T_985 = and(_T_984, _T_978) @[el2_dec_dec_ctl.scala 136:57] - node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 136:57] - node _T_987 = and(_T_986, _T_981) @[el2_dec_dec_ctl.scala 136:57] - node _T_988 = and(_T_987, _T_983) @[el2_dec_dec_ctl.scala 136:57] - io.out.rem <= _T_988 @[el2_dec_dec_ctl.scala 136:14] - node _T_989 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_990 = eq(_T_989, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_991 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_992 = and(_T_990, _T_991) @[el2_dec_dec_ctl.scala 137:47] - io.out.fence <= _T_992 @[el2_dec_dec_ctl.scala 137:16] - node _T_993 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_994 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_995 = eq(_T_994, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_996 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_997 = and(_T_993, _T_995) @[el2_dec_dec_ctl.scala 138:52] - node _T_998 = and(_T_997, _T_996) @[el2_dec_dec_ctl.scala 138:52] - io.out.fence_i <= _T_998 @[el2_dec_dec_ctl.scala 138:18] - node _T_999 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] - node _T_1000 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] - node _T_1001 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1003 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1005 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1006 = and(_T_999, _T_1000) @[el2_dec_dec_ctl.scala 139:59] - node _T_1007 = and(_T_1006, _T_1002) @[el2_dec_dec_ctl.scala 139:59] - node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 139:59] - node _T_1009 = and(_T_1008, _T_1005) @[el2_dec_dec_ctl.scala 139:59] - node _T_1010 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1011 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1012 = and(_T_1010, _T_1011) @[el2_dec_dec_ctl.scala 139:92] - node _T_1013 = or(_T_1009, _T_1012) @[el2_dec_dec_ctl.scala 139:63] - node _T_1014 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1015 = eq(_T_1014, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1016 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1017 = eq(_T_1016, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1018 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1019 = and(_T_1015, _T_1017) @[el2_dec_dec_ctl.scala 140:37] - node _T_1020 = and(_T_1019, _T_1018) @[el2_dec_dec_ctl.scala 140:37] - node _T_1021 = or(_T_1013, _T_1020) @[el2_dec_dec_ctl.scala 139:96] - node _T_1022 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1024 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1025 = and(_T_1023, _T_1024) @[el2_dec_dec_ctl.scala 140:71] - node _T_1026 = or(_T_1021, _T_1025) @[el2_dec_dec_ctl.scala 140:41] - io.out.pm_alu <= _T_1026 @[el2_dec_dec_ctl.scala 139:17] - node _T_1027 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1028 = eq(_T_1027, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1029 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1030 = and(_T_1028, _T_1029) @[el2_dec_dec_ctl.scala 141:49] - node _T_1031 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1032 = eq(_T_1031, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1033 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_1034 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1035 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1036 = and(_T_1032, _T_1033) @[el2_dec_dec_ctl.scala 141:88] - node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 141:88] - node _T_1038 = and(_T_1037, _T_1035) @[el2_dec_dec_ctl.scala 141:88] - node _T_1039 = or(_T_1030, _T_1038) @[el2_dec_dec_ctl.scala 141:53] - node _T_1040 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1042 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_1043 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1044 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1045 = and(_T_1041, _T_1042) @[el2_dec_dec_ctl.scala 142:38] - node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 142:38] - node _T_1047 = and(_T_1046, _T_1044) @[el2_dec_dec_ctl.scala 142:38] - node _T_1048 = or(_T_1039, _T_1047) @[el2_dec_dec_ctl.scala 141:92] - node _T_1049 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1051 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_1052 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1053 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1054 = and(_T_1050, _T_1051) @[el2_dec_dec_ctl.scala 142:77] - node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 142:77] - node _T_1056 = and(_T_1055, _T_1053) @[el2_dec_dec_ctl.scala 142:77] - node _T_1057 = or(_T_1048, _T_1056) @[el2_dec_dec_ctl.scala 142:42] - node _T_1058 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1059 = eq(_T_1058, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1060 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_1061 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1062 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1063 = and(_T_1059, _T_1060) @[el2_dec_dec_ctl.scala 143:38] - node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 143:38] - node _T_1065 = and(_T_1064, _T_1062) @[el2_dec_dec_ctl.scala 143:38] - node _T_1066 = or(_T_1057, _T_1065) @[el2_dec_dec_ctl.scala 142:81] - node _T_1067 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1069 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_1070 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1071 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1072 = and(_T_1068, _T_1069) @[el2_dec_dec_ctl.scala 143:78] - node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 143:78] - node _T_1074 = and(_T_1073, _T_1071) @[el2_dec_dec_ctl.scala 143:78] - node _T_1075 = or(_T_1066, _T_1074) @[el2_dec_dec_ctl.scala 143:42] - node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1078 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_1079 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1080 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1081 = and(_T_1077, _T_1078) @[el2_dec_dec_ctl.scala 144:39] - node _T_1082 = and(_T_1081, _T_1079) @[el2_dec_dec_ctl.scala 144:39] - node _T_1083 = and(_T_1082, _T_1080) @[el2_dec_dec_ctl.scala 144:39] - node _T_1084 = or(_T_1075, _T_1083) @[el2_dec_dec_ctl.scala 143:82] - node _T_1085 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_1086 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1087 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1088 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1089 = and(_T_1085, _T_1086) @[el2_dec_dec_ctl.scala 144:78] - node _T_1090 = and(_T_1089, _T_1087) @[el2_dec_dec_ctl.scala 144:78] - node _T_1091 = and(_T_1090, _T_1088) @[el2_dec_dec_ctl.scala 144:78] - node _T_1092 = or(_T_1084, _T_1091) @[el2_dec_dec_ctl.scala 144:43] - node _T_1093 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_1094 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1095 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1096 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1097 = and(_T_1093, _T_1094) @[el2_dec_dec_ctl.scala 145:38] - node _T_1098 = and(_T_1097, _T_1095) @[el2_dec_dec_ctl.scala 145:38] - node _T_1099 = and(_T_1098, _T_1096) @[el2_dec_dec_ctl.scala 145:38] - node _T_1100 = or(_T_1092, _T_1099) @[el2_dec_dec_ctl.scala 144:82] - node _T_1101 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_1102 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1104 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1105 = and(_T_1101, _T_1102) @[el2_dec_dec_ctl.scala 145:77] - node _T_1106 = and(_T_1105, _T_1103) @[el2_dec_dec_ctl.scala 145:77] - node _T_1107 = and(_T_1106, _T_1104) @[el2_dec_dec_ctl.scala 145:77] - node _T_1108 = or(_T_1100, _T_1107) @[el2_dec_dec_ctl.scala 145:42] - node _T_1109 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_1110 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1111 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1112 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1113 = and(_T_1109, _T_1110) @[el2_dec_dec_ctl.scala 146:38] - node _T_1114 = and(_T_1113, _T_1111) @[el2_dec_dec_ctl.scala 146:38] - node _T_1115 = and(_T_1114, _T_1112) @[el2_dec_dec_ctl.scala 146:38] - node _T_1116 = or(_T_1108, _T_1115) @[el2_dec_dec_ctl.scala 145:81] - node _T_1117 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_1118 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1119 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1120 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1121 = and(_T_1117, _T_1118) @[el2_dec_dec_ctl.scala 146:77] - node _T_1122 = and(_T_1121, _T_1119) @[el2_dec_dec_ctl.scala 146:77] - node _T_1123 = and(_T_1122, _T_1120) @[el2_dec_dec_ctl.scala 146:77] - node _T_1124 = or(_T_1116, _T_1123) @[el2_dec_dec_ctl.scala 146:42] - io.out.presync <= _T_1124 @[el2_dec_dec_ctl.scala 141:18] - node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_1126 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1128 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1129 = and(_T_1125, _T_1127) @[el2_dec_dec_ctl.scala 147:53] - node _T_1130 = and(_T_1129, _T_1128) @[el2_dec_dec_ctl.scala 147:53] - node _T_1131 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1133 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1135 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1139 = and(_T_1132, _T_1134) @[el2_dec_dec_ctl.scala 147:98] - node _T_1140 = and(_T_1139, _T_1136) @[el2_dec_dec_ctl.scala 147:98] - node _T_1141 = and(_T_1140, _T_1137) @[el2_dec_dec_ctl.scala 147:98] - node _T_1142 = and(_T_1141, _T_1138) @[el2_dec_dec_ctl.scala 147:98] - node _T_1143 = or(_T_1130, _T_1142) @[el2_dec_dec_ctl.scala 147:57] - node _T_1144 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1146 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_1147 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1148 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1149 = and(_T_1145, _T_1146) @[el2_dec_dec_ctl.scala 148:38] - node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 148:38] - node _T_1151 = and(_T_1150, _T_1148) @[el2_dec_dec_ctl.scala 148:38] - node _T_1152 = or(_T_1143, _T_1151) @[el2_dec_dec_ctl.scala 147:102] - node _T_1153 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1155 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_1156 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1157 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1158 = and(_T_1154, _T_1155) @[el2_dec_dec_ctl.scala 148:77] - node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 148:77] - node _T_1160 = and(_T_1159, _T_1157) @[el2_dec_dec_ctl.scala 148:77] - node _T_1161 = or(_T_1152, _T_1160) @[el2_dec_dec_ctl.scala 148:42] - node _T_1162 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1164 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_1165 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1166 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1167 = and(_T_1163, _T_1164) @[el2_dec_dec_ctl.scala 149:38] - node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 149:38] - node _T_1169 = and(_T_1168, _T_1166) @[el2_dec_dec_ctl.scala 149:38] - node _T_1170 = or(_T_1161, _T_1169) @[el2_dec_dec_ctl.scala 148:81] - node _T_1171 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1172 = eq(_T_1171, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1173 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_1174 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1175 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1176 = and(_T_1172, _T_1173) @[el2_dec_dec_ctl.scala 149:78] - node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 149:78] - node _T_1178 = and(_T_1177, _T_1175) @[el2_dec_dec_ctl.scala 149:78] - node _T_1179 = or(_T_1170, _T_1178) @[el2_dec_dec_ctl.scala 149:42] - node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1182 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_1183 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1184 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1185 = and(_T_1181, _T_1182) @[el2_dec_dec_ctl.scala 150:39] - node _T_1186 = and(_T_1185, _T_1183) @[el2_dec_dec_ctl.scala 150:39] - node _T_1187 = and(_T_1186, _T_1184) @[el2_dec_dec_ctl.scala 150:39] - node _T_1188 = or(_T_1179, _T_1187) @[el2_dec_dec_ctl.scala 149:82] - node _T_1189 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_1190 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1191 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1192 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1193 = and(_T_1189, _T_1190) @[el2_dec_dec_ctl.scala 150:78] - node _T_1194 = and(_T_1193, _T_1191) @[el2_dec_dec_ctl.scala 150:78] - node _T_1195 = and(_T_1194, _T_1192) @[el2_dec_dec_ctl.scala 150:78] - node _T_1196 = or(_T_1188, _T_1195) @[el2_dec_dec_ctl.scala 150:43] - node _T_1197 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_1198 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1199 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1200 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1201 = and(_T_1197, _T_1198) @[el2_dec_dec_ctl.scala 151:38] - node _T_1202 = and(_T_1201, _T_1199) @[el2_dec_dec_ctl.scala 151:38] - node _T_1203 = and(_T_1202, _T_1200) @[el2_dec_dec_ctl.scala 151:38] - node _T_1204 = or(_T_1196, _T_1203) @[el2_dec_dec_ctl.scala 150:82] - node _T_1205 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_1206 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1207 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1208 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1209 = and(_T_1205, _T_1206) @[el2_dec_dec_ctl.scala 151:77] - node _T_1210 = and(_T_1209, _T_1207) @[el2_dec_dec_ctl.scala 151:77] - node _T_1211 = and(_T_1210, _T_1208) @[el2_dec_dec_ctl.scala 151:77] - node _T_1212 = or(_T_1204, _T_1211) @[el2_dec_dec_ctl.scala 151:42] - node _T_1213 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_1214 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1215 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1216 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1217 = and(_T_1213, _T_1214) @[el2_dec_dec_ctl.scala 152:38] - node _T_1218 = and(_T_1217, _T_1215) @[el2_dec_dec_ctl.scala 152:38] - node _T_1219 = and(_T_1218, _T_1216) @[el2_dec_dec_ctl.scala 152:38] - node _T_1220 = or(_T_1212, _T_1219) @[el2_dec_dec_ctl.scala 151:81] - node _T_1221 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_1222 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1223 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1224 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1225 = and(_T_1221, _T_1222) @[el2_dec_dec_ctl.scala 152:77] - node _T_1226 = and(_T_1225, _T_1223) @[el2_dec_dec_ctl.scala 152:77] - node _T_1227 = and(_T_1226, _T_1224) @[el2_dec_dec_ctl.scala 152:77] - node _T_1228 = or(_T_1220, _T_1227) @[el2_dec_dec_ctl.scala 152:42] - io.out.postsync <= _T_1228 @[el2_dec_dec_ctl.scala 147:19] - node _T_1229 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1231 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1233 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] - node _T_1234 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] - node _T_1235 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1237 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1238 = eq(_T_1237, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1239 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1241 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1243 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1244 = eq(_T_1243, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1245 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1246 = eq(_T_1245, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1247 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:33] - node _T_1248 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] - node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1250 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1252 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1254 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1256 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1258 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1260 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1262 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1264 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1266 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1267 = eq(_T_1266, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1268 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1269 = eq(_T_1268, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1270 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1273 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1274 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1275 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1279 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1280 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1281 = eq(_T_1280, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1282 = and(_T_1230, _T_1232) @[el2_dec_dec_ctl.scala 153:144] - node _T_1283 = and(_T_1282, _T_1233) @[el2_dec_dec_ctl.scala 153:144] - node _T_1284 = and(_T_1283, _T_1234) @[el2_dec_dec_ctl.scala 153:144] - node _T_1285 = and(_T_1284, _T_1236) @[el2_dec_dec_ctl.scala 153:144] - node _T_1286 = and(_T_1285, _T_1238) @[el2_dec_dec_ctl.scala 153:144] - node _T_1287 = and(_T_1286, _T_1240) @[el2_dec_dec_ctl.scala 153:144] - node _T_1288 = and(_T_1287, _T_1242) @[el2_dec_dec_ctl.scala 153:144] - node _T_1289 = and(_T_1288, _T_1244) @[el2_dec_dec_ctl.scala 153:144] - node _T_1290 = and(_T_1289, _T_1246) @[el2_dec_dec_ctl.scala 153:144] - node _T_1291 = and(_T_1290, _T_1247) @[el2_dec_dec_ctl.scala 153:144] - node _T_1292 = and(_T_1291, _T_1249) @[el2_dec_dec_ctl.scala 153:144] - node _T_1293 = and(_T_1292, _T_1251) @[el2_dec_dec_ctl.scala 153:144] - node _T_1294 = and(_T_1293, _T_1253) @[el2_dec_dec_ctl.scala 153:144] - node _T_1295 = and(_T_1294, _T_1255) @[el2_dec_dec_ctl.scala 153:144] - node _T_1296 = and(_T_1295, _T_1257) @[el2_dec_dec_ctl.scala 153:144] - node _T_1297 = and(_T_1296, _T_1259) @[el2_dec_dec_ctl.scala 153:144] - node _T_1298 = and(_T_1297, _T_1261) @[el2_dec_dec_ctl.scala 153:144] - node _T_1299 = and(_T_1298, _T_1263) @[el2_dec_dec_ctl.scala 153:144] - node _T_1300 = and(_T_1299, _T_1265) @[el2_dec_dec_ctl.scala 153:144] - node _T_1301 = and(_T_1300, _T_1267) @[el2_dec_dec_ctl.scala 153:144] - node _T_1302 = and(_T_1301, _T_1269) @[el2_dec_dec_ctl.scala 153:144] - node _T_1303 = and(_T_1302, _T_1271) @[el2_dec_dec_ctl.scala 153:144] - node _T_1304 = and(_T_1303, _T_1272) @[el2_dec_dec_ctl.scala 153:144] - node _T_1305 = and(_T_1304, _T_1273) @[el2_dec_dec_ctl.scala 153:144] - node _T_1306 = and(_T_1305, _T_1274) @[el2_dec_dec_ctl.scala 153:144] - node _T_1307 = and(_T_1306, _T_1276) @[el2_dec_dec_ctl.scala 153:144] - node _T_1308 = and(_T_1307, _T_1278) @[el2_dec_dec_ctl.scala 153:144] - node _T_1309 = and(_T_1308, _T_1279) @[el2_dec_dec_ctl.scala 153:144] - node _T_1310 = and(_T_1309, _T_1281) @[el2_dec_dec_ctl.scala 153:144] - node _T_1311 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1313 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1315 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1317 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] - node _T_1318 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1320 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1321 = eq(_T_1320, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1322 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1324 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1326 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1328 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] - node _T_1329 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1331 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] - node _T_1332 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1334 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1336 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1338 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1339 = eq(_T_1338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1340 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1342 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1343 = eq(_T_1342, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1344 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1345 = eq(_T_1344, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1346 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1348 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1350 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1352 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1354 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1355 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1356 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1357 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1358 = eq(_T_1357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1360 = eq(_T_1359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1361 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1362 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1364 = and(_T_1312, _T_1314) @[el2_dec_dec_ctl.scala 154:130] - node _T_1365 = and(_T_1364, _T_1316) @[el2_dec_dec_ctl.scala 154:130] - node _T_1366 = and(_T_1365, _T_1317) @[el2_dec_dec_ctl.scala 154:130] - node _T_1367 = and(_T_1366, _T_1319) @[el2_dec_dec_ctl.scala 154:130] - node _T_1368 = and(_T_1367, _T_1321) @[el2_dec_dec_ctl.scala 154:130] - node _T_1369 = and(_T_1368, _T_1323) @[el2_dec_dec_ctl.scala 154:130] - node _T_1370 = and(_T_1369, _T_1325) @[el2_dec_dec_ctl.scala 154:130] - node _T_1371 = and(_T_1370, _T_1327) @[el2_dec_dec_ctl.scala 154:130] - node _T_1372 = and(_T_1371, _T_1328) @[el2_dec_dec_ctl.scala 154:130] - node _T_1373 = and(_T_1372, _T_1330) @[el2_dec_dec_ctl.scala 154:130] - node _T_1374 = and(_T_1373, _T_1331) @[el2_dec_dec_ctl.scala 154:130] - node _T_1375 = and(_T_1374, _T_1333) @[el2_dec_dec_ctl.scala 154:130] - node _T_1376 = and(_T_1375, _T_1335) @[el2_dec_dec_ctl.scala 154:130] - node _T_1377 = and(_T_1376, _T_1337) @[el2_dec_dec_ctl.scala 154:130] - node _T_1378 = and(_T_1377, _T_1339) @[el2_dec_dec_ctl.scala 154:130] - node _T_1379 = and(_T_1378, _T_1341) @[el2_dec_dec_ctl.scala 154:130] - node _T_1380 = and(_T_1379, _T_1343) @[el2_dec_dec_ctl.scala 154:130] - node _T_1381 = and(_T_1380, _T_1345) @[el2_dec_dec_ctl.scala 154:130] - node _T_1382 = and(_T_1381, _T_1347) @[el2_dec_dec_ctl.scala 154:130] - node _T_1383 = and(_T_1382, _T_1349) @[el2_dec_dec_ctl.scala 154:130] - node _T_1384 = and(_T_1383, _T_1351) @[el2_dec_dec_ctl.scala 154:130] - node _T_1385 = and(_T_1384, _T_1353) @[el2_dec_dec_ctl.scala 154:130] - node _T_1386 = and(_T_1385, _T_1354) @[el2_dec_dec_ctl.scala 154:130] - node _T_1387 = and(_T_1386, _T_1355) @[el2_dec_dec_ctl.scala 154:130] - node _T_1388 = and(_T_1387, _T_1356) @[el2_dec_dec_ctl.scala 154:130] - node _T_1389 = and(_T_1388, _T_1358) @[el2_dec_dec_ctl.scala 154:130] - node _T_1390 = and(_T_1389, _T_1360) @[el2_dec_dec_ctl.scala 154:130] - node _T_1391 = and(_T_1390, _T_1361) @[el2_dec_dec_ctl.scala 154:130] - node _T_1392 = and(_T_1391, _T_1363) @[el2_dec_dec_ctl.scala 154:130] - node _T_1393 = or(_T_1310, _T_1392) @[el2_dec_dec_ctl.scala 153:148] - node _T_1394 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1396 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1398 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1400 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1402 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1404 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1406 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1408 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1410 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1412 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1414 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1416 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1418 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1420 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1422 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1424 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1426 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1428 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1430 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1432 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1434 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1436 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1437 = eq(_T_1436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1438 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1439 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1440 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1442 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1444 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1445 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1447 = and(_T_1395, _T_1397) @[el2_dec_dec_ctl.scala 155:127] - node _T_1448 = and(_T_1447, _T_1399) @[el2_dec_dec_ctl.scala 155:127] - node _T_1449 = and(_T_1448, _T_1401) @[el2_dec_dec_ctl.scala 155:127] - node _T_1450 = and(_T_1449, _T_1403) @[el2_dec_dec_ctl.scala 155:127] - node _T_1451 = and(_T_1450, _T_1405) @[el2_dec_dec_ctl.scala 155:127] - node _T_1452 = and(_T_1451, _T_1407) @[el2_dec_dec_ctl.scala 155:127] - node _T_1453 = and(_T_1452, _T_1409) @[el2_dec_dec_ctl.scala 155:127] - node _T_1454 = and(_T_1453, _T_1411) @[el2_dec_dec_ctl.scala 155:127] - node _T_1455 = and(_T_1454, _T_1413) @[el2_dec_dec_ctl.scala 155:127] - node _T_1456 = and(_T_1455, _T_1415) @[el2_dec_dec_ctl.scala 155:127] - node _T_1457 = and(_T_1456, _T_1417) @[el2_dec_dec_ctl.scala 155:127] - node _T_1458 = and(_T_1457, _T_1419) @[el2_dec_dec_ctl.scala 155:127] - node _T_1459 = and(_T_1458, _T_1421) @[el2_dec_dec_ctl.scala 155:127] - node _T_1460 = and(_T_1459, _T_1423) @[el2_dec_dec_ctl.scala 155:127] - node _T_1461 = and(_T_1460, _T_1425) @[el2_dec_dec_ctl.scala 155:127] - node _T_1462 = and(_T_1461, _T_1427) @[el2_dec_dec_ctl.scala 155:127] - node _T_1463 = and(_T_1462, _T_1429) @[el2_dec_dec_ctl.scala 155:127] - node _T_1464 = and(_T_1463, _T_1431) @[el2_dec_dec_ctl.scala 155:127] - node _T_1465 = and(_T_1464, _T_1433) @[el2_dec_dec_ctl.scala 155:127] - node _T_1466 = and(_T_1465, _T_1435) @[el2_dec_dec_ctl.scala 155:127] - node _T_1467 = and(_T_1466, _T_1437) @[el2_dec_dec_ctl.scala 155:127] - node _T_1468 = and(_T_1467, _T_1438) @[el2_dec_dec_ctl.scala 155:127] - node _T_1469 = and(_T_1468, _T_1439) @[el2_dec_dec_ctl.scala 155:127] - node _T_1470 = and(_T_1469, _T_1441) @[el2_dec_dec_ctl.scala 155:127] - node _T_1471 = and(_T_1470, _T_1443) @[el2_dec_dec_ctl.scala 155:127] - node _T_1472 = and(_T_1471, _T_1444) @[el2_dec_dec_ctl.scala 155:127] - node _T_1473 = and(_T_1472, _T_1446) @[el2_dec_dec_ctl.scala 155:127] - node _T_1474 = or(_T_1393, _T_1473) @[el2_dec_dec_ctl.scala 154:134] - node _T_1475 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1477 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1479 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1481 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1483 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1485 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1486 = eq(_T_1485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1487 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1489 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1491 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1492 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1494 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1495 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1497 = and(_T_1476, _T_1478) @[el2_dec_dec_ctl.scala 156:68] - node _T_1498 = and(_T_1497, _T_1480) @[el2_dec_dec_ctl.scala 156:68] - node _T_1499 = and(_T_1498, _T_1482) @[el2_dec_dec_ctl.scala 156:68] - node _T_1500 = and(_T_1499, _T_1484) @[el2_dec_dec_ctl.scala 156:68] - node _T_1501 = and(_T_1500, _T_1486) @[el2_dec_dec_ctl.scala 156:68] - node _T_1502 = and(_T_1501, _T_1488) @[el2_dec_dec_ctl.scala 156:68] - node _T_1503 = and(_T_1502, _T_1490) @[el2_dec_dec_ctl.scala 156:68] - node _T_1504 = and(_T_1503, _T_1491) @[el2_dec_dec_ctl.scala 156:68] - node _T_1505 = and(_T_1504, _T_1493) @[el2_dec_dec_ctl.scala 156:68] - node _T_1506 = and(_T_1505, _T_1494) @[el2_dec_dec_ctl.scala 156:68] - node _T_1507 = and(_T_1506, _T_1496) @[el2_dec_dec_ctl.scala 156:68] - node _T_1508 = or(_T_1474, _T_1507) @[el2_dec_dec_ctl.scala 155:131] - node _T_1509 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1511 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1513 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1515 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1517 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1519 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1520 = eq(_T_1519, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1521 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1523 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1525 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1527 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1529 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1530 = eq(_T_1529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1531 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1532 = eq(_T_1531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1533 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1534 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1536 = and(_T_1510, _T_1512) @[el2_dec_dec_ctl.scala 157:77] - node _T_1537 = and(_T_1536, _T_1514) @[el2_dec_dec_ctl.scala 157:77] - node _T_1538 = and(_T_1537, _T_1516) @[el2_dec_dec_ctl.scala 157:77] - node _T_1539 = and(_T_1538, _T_1518) @[el2_dec_dec_ctl.scala 157:77] - node _T_1540 = and(_T_1539, _T_1520) @[el2_dec_dec_ctl.scala 157:77] - node _T_1541 = and(_T_1540, _T_1522) @[el2_dec_dec_ctl.scala 157:77] - node _T_1542 = and(_T_1541, _T_1524) @[el2_dec_dec_ctl.scala 157:77] - node _T_1543 = and(_T_1542, _T_1526) @[el2_dec_dec_ctl.scala 157:77] - node _T_1544 = and(_T_1543, _T_1528) @[el2_dec_dec_ctl.scala 157:77] - node _T_1545 = and(_T_1544, _T_1530) @[el2_dec_dec_ctl.scala 157:77] - node _T_1546 = and(_T_1545, _T_1532) @[el2_dec_dec_ctl.scala 157:77] - node _T_1547 = and(_T_1546, _T_1533) @[el2_dec_dec_ctl.scala 157:77] - node _T_1548 = and(_T_1547, _T_1535) @[el2_dec_dec_ctl.scala 157:77] - node _T_1549 = or(_T_1508, _T_1548) @[el2_dec_dec_ctl.scala 156:72] - node _T_1550 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1552 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1554 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1556 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1558 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1559 = eq(_T_1558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1560 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1562 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_1563 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1564 = eq(_T_1563, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1565 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_1566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1567 = eq(_T_1566, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1568 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1569 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1571 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1572 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1574 = and(_T_1551, _T_1553) @[el2_dec_dec_ctl.scala 158:74] - node _T_1575 = and(_T_1574, _T_1555) @[el2_dec_dec_ctl.scala 158:74] - node _T_1576 = and(_T_1575, _T_1557) @[el2_dec_dec_ctl.scala 158:74] - node _T_1577 = and(_T_1576, _T_1559) @[el2_dec_dec_ctl.scala 158:74] - node _T_1578 = and(_T_1577, _T_1561) @[el2_dec_dec_ctl.scala 158:74] - node _T_1579 = and(_T_1578, _T_1562) @[el2_dec_dec_ctl.scala 158:74] - node _T_1580 = and(_T_1579, _T_1564) @[el2_dec_dec_ctl.scala 158:74] - node _T_1581 = and(_T_1580, _T_1565) @[el2_dec_dec_ctl.scala 158:74] - node _T_1582 = and(_T_1581, _T_1567) @[el2_dec_dec_ctl.scala 158:74] - node _T_1583 = and(_T_1582, _T_1568) @[el2_dec_dec_ctl.scala 158:74] - node _T_1584 = and(_T_1583, _T_1570) @[el2_dec_dec_ctl.scala 158:74] - node _T_1585 = and(_T_1584, _T_1571) @[el2_dec_dec_ctl.scala 158:74] - node _T_1586 = and(_T_1585, _T_1573) @[el2_dec_dec_ctl.scala 158:74] - node _T_1587 = or(_T_1549, _T_1586) @[el2_dec_dec_ctl.scala 157:81] - node _T_1588 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1590 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1592 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1594 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1596 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1598 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1599 = eq(_T_1598, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1600 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1601 = eq(_T_1600, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1602 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1603 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1604 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1606 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1607 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1609 = and(_T_1589, _T_1591) @[el2_dec_dec_ctl.scala 159:66] - node _T_1610 = and(_T_1609, _T_1593) @[el2_dec_dec_ctl.scala 159:66] - node _T_1611 = and(_T_1610, _T_1595) @[el2_dec_dec_ctl.scala 159:66] - node _T_1612 = and(_T_1611, _T_1597) @[el2_dec_dec_ctl.scala 159:66] - node _T_1613 = and(_T_1612, _T_1599) @[el2_dec_dec_ctl.scala 159:66] - node _T_1614 = and(_T_1613, _T_1601) @[el2_dec_dec_ctl.scala 159:66] - node _T_1615 = and(_T_1614, _T_1602) @[el2_dec_dec_ctl.scala 159:66] - node _T_1616 = and(_T_1615, _T_1603) @[el2_dec_dec_ctl.scala 159:66] - node _T_1617 = and(_T_1616, _T_1605) @[el2_dec_dec_ctl.scala 159:66] - node _T_1618 = and(_T_1617, _T_1606) @[el2_dec_dec_ctl.scala 159:66] - node _T_1619 = and(_T_1618, _T_1608) @[el2_dec_dec_ctl.scala 159:66] - node _T_1620 = or(_T_1587, _T_1619) @[el2_dec_dec_ctl.scala 158:78] - node _T_1621 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1622 = eq(_T_1621, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1623 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1624 = eq(_T_1623, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1625 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1627 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1628 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1629 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1631 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1632 = eq(_T_1631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1633 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1634 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1636 = and(_T_1622, _T_1624) @[el2_dec_dec_ctl.scala 160:54] - node _T_1637 = and(_T_1636, _T_1626) @[el2_dec_dec_ctl.scala 160:54] - node _T_1638 = and(_T_1637, _T_1627) @[el2_dec_dec_ctl.scala 160:54] - node _T_1639 = and(_T_1638, _T_1628) @[el2_dec_dec_ctl.scala 160:54] - node _T_1640 = and(_T_1639, _T_1630) @[el2_dec_dec_ctl.scala 160:54] - node _T_1641 = and(_T_1640, _T_1632) @[el2_dec_dec_ctl.scala 160:54] - node _T_1642 = and(_T_1641, _T_1633) @[el2_dec_dec_ctl.scala 160:54] - node _T_1643 = and(_T_1642, _T_1635) @[el2_dec_dec_ctl.scala 160:54] - node _T_1644 = or(_T_1620, _T_1643) @[el2_dec_dec_ctl.scala 159:70] - node _T_1645 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_1646 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1647 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1648 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1650 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1652 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1653 = eq(_T_1652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1654 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1655 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1656 = eq(_T_1655, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1657 = and(_T_1645, _T_1646) @[el2_dec_dec_ctl.scala 161:48] - node _T_1658 = and(_T_1657, _T_1647) @[el2_dec_dec_ctl.scala 161:48] - node _T_1659 = and(_T_1658, _T_1649) @[el2_dec_dec_ctl.scala 161:48] - node _T_1660 = and(_T_1659, _T_1651) @[el2_dec_dec_ctl.scala 161:48] - node _T_1661 = and(_T_1660, _T_1653) @[el2_dec_dec_ctl.scala 161:48] - node _T_1662 = and(_T_1661, _T_1654) @[el2_dec_dec_ctl.scala 161:48] - node _T_1663 = and(_T_1662, _T_1656) @[el2_dec_dec_ctl.scala 161:48] - node _T_1664 = or(_T_1644, _T_1663) @[el2_dec_dec_ctl.scala 160:58] - node _T_1665 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1666 = eq(_T_1665, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1668 = eq(_T_1667, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1669 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1672 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1673 = eq(_T_1672, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1674 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1675 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1677 = and(_T_1666, _T_1668) @[el2_dec_dec_ctl.scala 162:47] - node _T_1678 = and(_T_1677, _T_1670) @[el2_dec_dec_ctl.scala 162:47] - node _T_1679 = and(_T_1678, _T_1671) @[el2_dec_dec_ctl.scala 162:47] - node _T_1680 = and(_T_1679, _T_1673) @[el2_dec_dec_ctl.scala 162:47] - node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 162:47] - node _T_1682 = and(_T_1681, _T_1676) @[el2_dec_dec_ctl.scala 162:47] - node _T_1683 = or(_T_1664, _T_1682) @[el2_dec_dec_ctl.scala 161:52] - node _T_1684 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1685 = eq(_T_1684, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1686 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1688 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1691 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1693 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1695 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1696 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1697 = eq(_T_1696, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1698 = and(_T_1685, _T_1687) @[el2_dec_dec_ctl.scala 162:99] - node _T_1699 = and(_T_1698, _T_1688) @[el2_dec_dec_ctl.scala 162:99] - node _T_1700 = and(_T_1699, _T_1690) @[el2_dec_dec_ctl.scala 162:99] - node _T_1701 = and(_T_1700, _T_1692) @[el2_dec_dec_ctl.scala 162:99] - node _T_1702 = and(_T_1701, _T_1694) @[el2_dec_dec_ctl.scala 162:99] - node _T_1703 = and(_T_1702, _T_1695) @[el2_dec_dec_ctl.scala 162:99] - node _T_1704 = and(_T_1703, _T_1697) @[el2_dec_dec_ctl.scala 162:99] - node _T_1705 = or(_T_1683, _T_1704) @[el2_dec_dec_ctl.scala 162:51] - node _T_1706 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_1707 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1708 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1709 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1710 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1711 = eq(_T_1710, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1712 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1714 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1715 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1717 = and(_T_1706, _T_1707) @[el2_dec_dec_ctl.scala 163:47] - node _T_1718 = and(_T_1717, _T_1708) @[el2_dec_dec_ctl.scala 163:47] - node _T_1719 = and(_T_1718, _T_1709) @[el2_dec_dec_ctl.scala 163:47] - node _T_1720 = and(_T_1719, _T_1711) @[el2_dec_dec_ctl.scala 163:47] - node _T_1721 = and(_T_1720, _T_1713) @[el2_dec_dec_ctl.scala 163:47] - node _T_1722 = and(_T_1721, _T_1714) @[el2_dec_dec_ctl.scala 163:47] - node _T_1723 = and(_T_1722, _T_1716) @[el2_dec_dec_ctl.scala 163:47] - node _T_1724 = or(_T_1705, _T_1723) @[el2_dec_dec_ctl.scala 162:103] - node _T_1725 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1727 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1729 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1731 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1733 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1735 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1737 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1739 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1741 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1743 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1745 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1747 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] - node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1749 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1751 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1753 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1755 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1757 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1759 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1761 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1762 = eq(_T_1761, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1763 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1764 = eq(_T_1763, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1765 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1767 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1768 = eq(_T_1767, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1769 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1770 = eq(_T_1769, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1771 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1773 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1775 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1777 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1778 = eq(_T_1777, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1779 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1781 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1782 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1783 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1784 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1785 = eq(_T_1784, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1786 = and(_T_1726, _T_1728) @[el2_dec_dec_ctl.scala 164:142] - node _T_1787 = and(_T_1786, _T_1730) @[el2_dec_dec_ctl.scala 164:142] - node _T_1788 = and(_T_1787, _T_1732) @[el2_dec_dec_ctl.scala 164:142] - node _T_1789 = and(_T_1788, _T_1734) @[el2_dec_dec_ctl.scala 164:142] - node _T_1790 = and(_T_1789, _T_1736) @[el2_dec_dec_ctl.scala 164:142] - node _T_1791 = and(_T_1790, _T_1738) @[el2_dec_dec_ctl.scala 164:142] - node _T_1792 = and(_T_1791, _T_1740) @[el2_dec_dec_ctl.scala 164:142] - node _T_1793 = and(_T_1792, _T_1742) @[el2_dec_dec_ctl.scala 164:142] - node _T_1794 = and(_T_1793, _T_1744) @[el2_dec_dec_ctl.scala 164:142] - node _T_1795 = and(_T_1794, _T_1746) @[el2_dec_dec_ctl.scala 164:142] - node _T_1796 = and(_T_1795, _T_1748) @[el2_dec_dec_ctl.scala 164:142] - node _T_1797 = and(_T_1796, _T_1750) @[el2_dec_dec_ctl.scala 164:142] - node _T_1798 = and(_T_1797, _T_1752) @[el2_dec_dec_ctl.scala 164:142] - node _T_1799 = and(_T_1798, _T_1754) @[el2_dec_dec_ctl.scala 164:142] - node _T_1800 = and(_T_1799, _T_1756) @[el2_dec_dec_ctl.scala 164:142] - node _T_1801 = and(_T_1800, _T_1758) @[el2_dec_dec_ctl.scala 164:142] - node _T_1802 = and(_T_1801, _T_1760) @[el2_dec_dec_ctl.scala 164:142] - node _T_1803 = and(_T_1802, _T_1762) @[el2_dec_dec_ctl.scala 164:142] - node _T_1804 = and(_T_1803, _T_1764) @[el2_dec_dec_ctl.scala 164:142] - node _T_1805 = and(_T_1804, _T_1766) @[el2_dec_dec_ctl.scala 164:142] - node _T_1806 = and(_T_1805, _T_1768) @[el2_dec_dec_ctl.scala 164:142] - node _T_1807 = and(_T_1806, _T_1770) @[el2_dec_dec_ctl.scala 164:142] - node _T_1808 = and(_T_1807, _T_1772) @[el2_dec_dec_ctl.scala 164:142] - node _T_1809 = and(_T_1808, _T_1774) @[el2_dec_dec_ctl.scala 164:142] - node _T_1810 = and(_T_1809, _T_1776) @[el2_dec_dec_ctl.scala 164:142] - node _T_1811 = and(_T_1810, _T_1778) @[el2_dec_dec_ctl.scala 164:142] - node _T_1812 = and(_T_1811, _T_1780) @[el2_dec_dec_ctl.scala 164:142] - node _T_1813 = and(_T_1812, _T_1781) @[el2_dec_dec_ctl.scala 164:142] - node _T_1814 = and(_T_1813, _T_1782) @[el2_dec_dec_ctl.scala 164:142] - node _T_1815 = and(_T_1814, _T_1783) @[el2_dec_dec_ctl.scala 164:142] - node _T_1816 = and(_T_1815, _T_1785) @[el2_dec_dec_ctl.scala 164:142] - node _T_1817 = or(_T_1724, _T_1816) @[el2_dec_dec_ctl.scala 163:51] - node _T_1818 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1820 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1822 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1824 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1826 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1828 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1830 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1832 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1833 = eq(_T_1832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1834 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1835 = eq(_T_1834, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1836 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1837 = eq(_T_1836, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1838 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1839 = eq(_T_1838, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1840 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1841 = eq(_T_1840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1842 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1843 = eq(_T_1842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1844 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1846 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1848 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1849 = eq(_T_1848, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1850 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1851 = eq(_T_1850, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1852 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1854 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1855 = eq(_T_1854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1856 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1857 = eq(_T_1856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1858 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1859 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1860 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1861 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1863 = and(_T_1819, _T_1821) @[el2_dec_dec_ctl.scala 165:110] - node _T_1864 = and(_T_1863, _T_1823) @[el2_dec_dec_ctl.scala 165:110] - node _T_1865 = and(_T_1864, _T_1825) @[el2_dec_dec_ctl.scala 165:110] - node _T_1866 = and(_T_1865, _T_1827) @[el2_dec_dec_ctl.scala 165:110] - node _T_1867 = and(_T_1866, _T_1829) @[el2_dec_dec_ctl.scala 165:110] - node _T_1868 = and(_T_1867, _T_1831) @[el2_dec_dec_ctl.scala 165:110] - node _T_1869 = and(_T_1868, _T_1833) @[el2_dec_dec_ctl.scala 165:110] - node _T_1870 = and(_T_1869, _T_1835) @[el2_dec_dec_ctl.scala 165:110] - node _T_1871 = and(_T_1870, _T_1837) @[el2_dec_dec_ctl.scala 165:110] - node _T_1872 = and(_T_1871, _T_1839) @[el2_dec_dec_ctl.scala 165:110] - node _T_1873 = and(_T_1872, _T_1841) @[el2_dec_dec_ctl.scala 165:110] - node _T_1874 = and(_T_1873, _T_1843) @[el2_dec_dec_ctl.scala 165:110] - node _T_1875 = and(_T_1874, _T_1845) @[el2_dec_dec_ctl.scala 165:110] - node _T_1876 = and(_T_1875, _T_1847) @[el2_dec_dec_ctl.scala 165:110] - node _T_1877 = and(_T_1876, _T_1849) @[el2_dec_dec_ctl.scala 165:110] - node _T_1878 = and(_T_1877, _T_1851) @[el2_dec_dec_ctl.scala 165:110] - node _T_1879 = and(_T_1878, _T_1853) @[el2_dec_dec_ctl.scala 165:110] - node _T_1880 = and(_T_1879, _T_1855) @[el2_dec_dec_ctl.scala 165:110] - node _T_1881 = and(_T_1880, _T_1857) @[el2_dec_dec_ctl.scala 165:110] - node _T_1882 = and(_T_1881, _T_1858) @[el2_dec_dec_ctl.scala 165:110] - node _T_1883 = and(_T_1882, _T_1859) @[el2_dec_dec_ctl.scala 165:110] - node _T_1884 = and(_T_1883, _T_1860) @[el2_dec_dec_ctl.scala 165:110] - node _T_1885 = and(_T_1884, _T_1862) @[el2_dec_dec_ctl.scala 165:110] - node _T_1886 = or(_T_1817, _T_1885) @[el2_dec_dec_ctl.scala 164:146] - node _T_1887 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1888 = eq(_T_1887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1889 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1891 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1892 = eq(_T_1891, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1893 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1895 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1897 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1898 = eq(_T_1897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1899 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1900 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1902 = and(_T_1888, _T_1890) @[el2_dec_dec_ctl.scala 166:51] - node _T_1903 = and(_T_1902, _T_1892) @[el2_dec_dec_ctl.scala 166:51] - node _T_1904 = and(_T_1903, _T_1894) @[el2_dec_dec_ctl.scala 166:51] - node _T_1905 = and(_T_1904, _T_1896) @[el2_dec_dec_ctl.scala 166:51] - node _T_1906 = and(_T_1905, _T_1898) @[el2_dec_dec_ctl.scala 166:51] - node _T_1907 = and(_T_1906, _T_1899) @[el2_dec_dec_ctl.scala 166:51] - node _T_1908 = and(_T_1907, _T_1901) @[el2_dec_dec_ctl.scala 166:51] - node _T_1909 = or(_T_1886, _T_1908) @[el2_dec_dec_ctl.scala 165:114] - node _T_1910 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1911 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1912 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1914 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1915 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1916 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1917 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1919 = and(_T_1910, _T_1911) @[el2_dec_dec_ctl.scala 166:95] - node _T_1920 = and(_T_1919, _T_1913) @[el2_dec_dec_ctl.scala 166:95] - node _T_1921 = and(_T_1920, _T_1914) @[el2_dec_dec_ctl.scala 166:95] - node _T_1922 = and(_T_1921, _T_1915) @[el2_dec_dec_ctl.scala 166:95] - node _T_1923 = and(_T_1922, _T_1916) @[el2_dec_dec_ctl.scala 166:95] - node _T_1924 = and(_T_1923, _T_1918) @[el2_dec_dec_ctl.scala 166:95] - node _T_1925 = or(_T_1909, _T_1924) @[el2_dec_dec_ctl.scala 166:55] - node _T_1926 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1927 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1928 = eq(_T_1927, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1929 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1930 = eq(_T_1929, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1931 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1932 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1934 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1935 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1937 = and(_T_1926, _T_1928) @[el2_dec_dec_ctl.scala 167:46] - node _T_1938 = and(_T_1937, _T_1930) @[el2_dec_dec_ctl.scala 167:46] - node _T_1939 = and(_T_1938, _T_1931) @[el2_dec_dec_ctl.scala 167:46] - node _T_1940 = and(_T_1939, _T_1933) @[el2_dec_dec_ctl.scala 167:46] - node _T_1941 = and(_T_1940, _T_1934) @[el2_dec_dec_ctl.scala 167:46] - node _T_1942 = and(_T_1941, _T_1936) @[el2_dec_dec_ctl.scala 167:46] - node _T_1943 = or(_T_1925, _T_1942) @[el2_dec_dec_ctl.scala 166:99] - node _T_1944 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1946 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1947 = eq(_T_1946, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1948 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1949 = eq(_T_1948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1950 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1952 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1954 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1956 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1957 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1959 = and(_T_1945, _T_1947) @[el2_dec_dec_ctl.scala 167:99] - node _T_1960 = and(_T_1959, _T_1949) @[el2_dec_dec_ctl.scala 167:99] - node _T_1961 = and(_T_1960, _T_1951) @[el2_dec_dec_ctl.scala 167:99] - node _T_1962 = and(_T_1961, _T_1953) @[el2_dec_dec_ctl.scala 167:99] - node _T_1963 = and(_T_1962, _T_1955) @[el2_dec_dec_ctl.scala 167:99] - node _T_1964 = and(_T_1963, _T_1956) @[el2_dec_dec_ctl.scala 167:99] - node _T_1965 = and(_T_1964, _T_1958) @[el2_dec_dec_ctl.scala 167:99] - node _T_1966 = or(_T_1943, _T_1965) @[el2_dec_dec_ctl.scala 167:50] - node _T_1967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1974 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1975 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1976 = eq(_T_1975, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1977 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:43] - node _T_1978 = and(_T_1977, _T_1971) @[el2_dec_dec_ctl.scala 168:43] - node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:43] - node _T_1980 = and(_T_1979, _T_1974) @[el2_dec_dec_ctl.scala 168:43] - node _T_1981 = and(_T_1980, _T_1976) @[el2_dec_dec_ctl.scala 168:43] - node _T_1982 = or(_T_1966, _T_1981) @[el2_dec_dec_ctl.scala 167:103] - io.out.legal <= _T_1982 @[el2_dec_dec_ctl.scala 153:16] + node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 20:23] + node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 20:35] + node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 20:27] + node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 20:49] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 20:42] + node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 20:60] + node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 20:53] + node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 20:39] + node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 20:75] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 20:68] + node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 20:85] + node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 20:78] + node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 20:65] + io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 20:14] + node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 17:17] + node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 17:17] + node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 17:17] + node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 17:17] + node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 21:43] + node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 17:17] + node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 17:17] + node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 21:70] + node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 17:17] + node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 17:17] + node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 22:29] + node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_45 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_46 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_48 = and(_T_44, _T_45) @[el2_dec_dec_ctl.scala 17:17] + node _T_49 = and(_T_48, _T_47) @[el2_dec_dec_ctl.scala 17:17] + node _T_50 = or(_T_43, _T_49) @[el2_dec_dec_ctl.scala 22:56] + node _T_51 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_53 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_54 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_56 = and(_T_52, _T_53) @[el2_dec_dec_ctl.scala 17:17] + node _T_57 = and(_T_56, _T_55) @[el2_dec_dec_ctl.scala 17:17] + node _T_58 = or(_T_50, _T_57) @[el2_dec_dec_ctl.scala 23:29] + node _T_59 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_60 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_61 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_63 = and(_T_59, _T_60) @[el2_dec_dec_ctl.scala 17:17] + node _T_64 = and(_T_63, _T_62) @[el2_dec_dec_ctl.scala 17:17] + node _T_65 = or(_T_58, _T_64) @[el2_dec_dec_ctl.scala 23:55] + node _T_66 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_68 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_69 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_70 = eq(_T_69, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_71 = and(_T_67, _T_68) @[el2_dec_dec_ctl.scala 17:17] + node _T_72 = and(_T_71, _T_70) @[el2_dec_dec_ctl.scala 17:17] + node _T_73 = or(_T_65, _T_72) @[el2_dec_dec_ctl.scala 24:29] + node _T_74 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_75 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_76 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_77 = eq(_T_76, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_78 = and(_T_74, _T_75) @[el2_dec_dec_ctl.scala 17:17] + node _T_79 = and(_T_78, _T_77) @[el2_dec_dec_ctl.scala 17:17] + node _T_80 = or(_T_73, _T_79) @[el2_dec_dec_ctl.scala 24:55] + node _T_81 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_83 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_84 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_86 = and(_T_82, _T_83) @[el2_dec_dec_ctl.scala 17:17] + node _T_87 = and(_T_86, _T_85) @[el2_dec_dec_ctl.scala 17:17] + node _T_88 = or(_T_80, _T_87) @[el2_dec_dec_ctl.scala 25:29] + node _T_89 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_90 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_91 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_93 = and(_T_89, _T_90) @[el2_dec_dec_ctl.scala 17:17] + node _T_94 = and(_T_93, _T_92) @[el2_dec_dec_ctl.scala 17:17] + node _T_95 = or(_T_88, _T_94) @[el2_dec_dec_ctl.scala 25:55] + node _T_96 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_97 = eq(_T_96, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_98 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_99 = eq(_T_98, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_100 = and(_T_97, _T_99) @[el2_dec_dec_ctl.scala 17:17] + node _T_101 = or(_T_95, _T_100) @[el2_dec_dec_ctl.scala 26:29] + node _T_102 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_104 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_105 = eq(_T_104, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_106 = and(_T_103, _T_105) @[el2_dec_dec_ctl.scala 17:17] + node _T_107 = or(_T_101, _T_106) @[el2_dec_dec_ctl.scala 26:51] + io.out.rs1 <= _T_107 @[el2_dec_dec_ctl.scala 21:14] + node _T_108 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_109 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_111 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_113 = and(_T_108, _T_110) @[el2_dec_dec_ctl.scala 17:17] + node _T_114 = and(_T_113, _T_112) @[el2_dec_dec_ctl.scala 17:17] + node _T_115 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_117 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_118 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_119 = eq(_T_118, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_120 = and(_T_116, _T_117) @[el2_dec_dec_ctl.scala 17:17] + node _T_121 = and(_T_120, _T_119) @[el2_dec_dec_ctl.scala 17:17] + node _T_122 = or(_T_114, _T_121) @[el2_dec_dec_ctl.scala 27:40] + io.out.rs2 <= _T_122 @[el2_dec_dec_ctl.scala 27:14] + node _T_123 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_125 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_127 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_128 = and(_T_124, _T_126) @[el2_dec_dec_ctl.scala 17:17] + node _T_129 = and(_T_128, _T_127) @[el2_dec_dec_ctl.scala 17:17] + node _T_130 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_131 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_133 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_134 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_136 = and(_T_130, _T_132) @[el2_dec_dec_ctl.scala 17:17] + node _T_137 = and(_T_136, _T_133) @[el2_dec_dec_ctl.scala 17:17] + node _T_138 = and(_T_137, _T_135) @[el2_dec_dec_ctl.scala 17:17] + node _T_139 = or(_T_129, _T_138) @[el2_dec_dec_ctl.scala 28:42] + node _T_140 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_142 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_143 = eq(_T_142, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_144 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_145 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_146 = and(_T_141, _T_143) @[el2_dec_dec_ctl.scala 17:17] + node _T_147 = and(_T_146, _T_144) @[el2_dec_dec_ctl.scala 17:17] + node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 17:17] + node _T_149 = or(_T_139, _T_148) @[el2_dec_dec_ctl.scala 28:70] + node _T_150 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_152 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_154 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_155 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_156 = eq(_T_155, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_157 = and(_T_151, _T_153) @[el2_dec_dec_ctl.scala 17:17] + node _T_158 = and(_T_157, _T_154) @[el2_dec_dec_ctl.scala 17:17] + node _T_159 = and(_T_158, _T_156) @[el2_dec_dec_ctl.scala 17:17] + node _T_160 = or(_T_149, _T_159) @[el2_dec_dec_ctl.scala 29:32] + io.out.imm12 <= _T_160 @[el2_dec_dec_ctl.scala 28:16] + node _T_161 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 30:24] + node _T_162 = eq(_T_161, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 30:17] + node _T_163 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 30:37] + node _T_164 = eq(_T_163, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 30:30] + node _T_165 = and(_T_162, _T_164) @[el2_dec_dec_ctl.scala 30:28] + node _T_166 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 30:51] + node _T_167 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 30:63] + node _T_168 = and(_T_166, _T_167) @[el2_dec_dec_ctl.scala 30:55] + node _T_169 = or(_T_165, _T_168) @[el2_dec_dec_ctl.scala 30:42] + node _T_170 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 30:76] + node _T_171 = or(_T_169, _T_170) @[el2_dec_dec_ctl.scala 30:68] + io.out.rd <= _T_171 @[el2_dec_dec_ctl.scala 30:13] + node _T_172 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_173 = eq(_T_172, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_174 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_175 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_177 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_178 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_180 = and(_T_173, _T_174) @[el2_dec_dec_ctl.scala 17:17] + node _T_181 = and(_T_180, _T_176) @[el2_dec_dec_ctl.scala 17:17] + node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 17:17] + node _T_183 = and(_T_182, _T_179) @[el2_dec_dec_ctl.scala 17:17] + io.out.shimm5 <= _T_183 @[el2_dec_dec_ctl.scala 31:17] + node _T_184 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 32:26] + node _T_185 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 32:36] + node _T_186 = and(_T_184, _T_185) @[el2_dec_dec_ctl.scala 32:29] + node _T_187 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 32:50] + node _T_188 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 32:60] + node _T_189 = and(_T_187, _T_188) @[el2_dec_dec_ctl.scala 32:53] + node _T_190 = or(_T_186, _T_189) @[el2_dec_dec_ctl.scala 32:41] + io.out.imm20 <= _T_190 @[el2_dec_dec_ctl.scala 32:16] + node _T_191 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 33:24] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 33:17] + node _T_193 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 33:37] + node _T_194 = eq(_T_193, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 33:30] + node _T_195 = and(_T_192, _T_194) @[el2_dec_dec_ctl.scala 33:28] + node _T_196 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 33:49] + node _T_197 = and(_T_195, _T_196) @[el2_dec_dec_ctl.scala 33:41] + node _T_198 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 33:63] + node _T_199 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 33:75] + node _T_200 = and(_T_198, _T_199) @[el2_dec_dec_ctl.scala 33:67] + node _T_201 = or(_T_197, _T_200) @[el2_dec_dec_ctl.scala 33:54] + io.out.pc <= _T_201 @[el2_dec_dec_ctl.scala 33:13] + node _T_202 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_203 = eq(_T_202, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_204 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_206 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_208 = and(_T_203, _T_205) @[el2_dec_dec_ctl.scala 17:17] + node _T_209 = and(_T_208, _T_207) @[el2_dec_dec_ctl.scala 17:17] + io.out.load <= _T_209 @[el2_dec_dec_ctl.scala 34:15] + node _T_210 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_212 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_213 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_215 = and(_T_211, _T_212) @[el2_dec_dec_ctl.scala 17:17] + node _T_216 = and(_T_215, _T_214) @[el2_dec_dec_ctl.scala 17:17] + io.out.store <= _T_216 @[el2_dec_dec_ctl.scala 35:16] + node _T_217 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_218 = eq(_T_217, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_219 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_221 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_222 = eq(_T_221, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_223 = and(_T_218, _T_220) @[el2_dec_dec_ctl.scala 17:17] + node _T_224 = and(_T_223, _T_222) @[el2_dec_dec_ctl.scala 17:17] + io.out.lsu <= _T_224 @[el2_dec_dec_ctl.scala 36:14] + node _T_225 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_227 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_229 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_231 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_232 = eq(_T_231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_233 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_234 = and(_T_226, _T_228) @[el2_dec_dec_ctl.scala 17:17] + node _T_235 = and(_T_234, _T_230) @[el2_dec_dec_ctl.scala 17:17] + node _T_236 = and(_T_235, _T_232) @[el2_dec_dec_ctl.scala 17:17] + node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 17:17] + node _T_238 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_240 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_242 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_243 = and(_T_239, _T_241) @[el2_dec_dec_ctl.scala 17:17] + node _T_244 = and(_T_243, _T_242) @[el2_dec_dec_ctl.scala 17:17] + node _T_245 = or(_T_237, _T_244) @[el2_dec_dec_ctl.scala 37:49] + node _T_246 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_247 = eq(_T_246, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_248 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_250 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_251 = eq(_T_250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_252 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_254 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_256 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_258 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_259 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_261 = and(_T_247, _T_249) @[el2_dec_dec_ctl.scala 17:17] + node _T_262 = and(_T_261, _T_251) @[el2_dec_dec_ctl.scala 17:17] + node _T_263 = and(_T_262, _T_253) @[el2_dec_dec_ctl.scala 17:17] + node _T_264 = and(_T_263, _T_255) @[el2_dec_dec_ctl.scala 17:17] + node _T_265 = and(_T_264, _T_257) @[el2_dec_dec_ctl.scala 17:17] + node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 17:17] + node _T_267 = and(_T_266, _T_260) @[el2_dec_dec_ctl.scala 17:17] + node _T_268 = or(_T_245, _T_267) @[el2_dec_dec_ctl.scala 37:74] + io.out.add <= _T_268 @[el2_dec_dec_ctl.scala 37:14] + node _T_269 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:34] + node _T_270 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_274 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_275 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_276 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_278 = and(_T_269, _T_271) @[el2_dec_dec_ctl.scala 17:17] + node _T_279 = and(_T_278, _T_273) @[el2_dec_dec_ctl.scala 17:17] + node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 17:17] + node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 17:17] + node _T_282 = and(_T_281, _T_277) @[el2_dec_dec_ctl.scala 17:17] + node _T_283 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_285 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_286 = eq(_T_285, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_287 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_288 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_290 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_291 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_293 = and(_T_284, _T_286) @[el2_dec_dec_ctl.scala 17:17] + node _T_294 = and(_T_293, _T_287) @[el2_dec_dec_ctl.scala 17:17] + node _T_295 = and(_T_294, _T_289) @[el2_dec_dec_ctl.scala 17:17] + node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 17:17] + node _T_297 = and(_T_296, _T_292) @[el2_dec_dec_ctl.scala 17:17] + node _T_298 = or(_T_282, _T_297) @[el2_dec_dec_ctl.scala 39:49] + node _T_299 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_300 = eq(_T_299, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_301 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_302 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_304 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_305 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_307 = and(_T_300, _T_301) @[el2_dec_dec_ctl.scala 17:17] + node _T_308 = and(_T_307, _T_303) @[el2_dec_dec_ctl.scala 17:17] + node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 17:17] + node _T_310 = and(_T_309, _T_306) @[el2_dec_dec_ctl.scala 17:17] + node _T_311 = or(_T_298, _T_310) @[el2_dec_dec_ctl.scala 39:85] + node _T_312 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_313 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_315 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_316 = eq(_T_315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_317 = and(_T_312, _T_314) @[el2_dec_dec_ctl.scala 17:17] + node _T_318 = and(_T_317, _T_316) @[el2_dec_dec_ctl.scala 17:17] + node _T_319 = or(_T_311, _T_318) @[el2_dec_dec_ctl.scala 40:35] + io.out.sub <= _T_319 @[el2_dec_dec_ctl.scala 39:14] + node _T_320 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_321 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_322 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_323 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_324 = eq(_T_323, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_325 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_326 = eq(_T_325, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_327 = and(_T_320, _T_321) @[el2_dec_dec_ctl.scala 17:17] + node _T_328 = and(_T_327, _T_322) @[el2_dec_dec_ctl.scala 17:17] + node _T_329 = and(_T_328, _T_324) @[el2_dec_dec_ctl.scala 17:17] + node _T_330 = and(_T_329, _T_326) @[el2_dec_dec_ctl.scala 17:17] + node _T_331 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_332 = eq(_T_331, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_333 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_334 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_335 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_336 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_337 = eq(_T_336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_338 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_340 = and(_T_332, _T_333) @[el2_dec_dec_ctl.scala 17:17] + node _T_341 = and(_T_340, _T_334) @[el2_dec_dec_ctl.scala 17:17] + node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 17:17] + node _T_343 = and(_T_342, _T_337) @[el2_dec_dec_ctl.scala 17:17] + node _T_344 = and(_T_343, _T_339) @[el2_dec_dec_ctl.scala 17:17] + node _T_345 = or(_T_330, _T_344) @[el2_dec_dec_ctl.scala 41:48] + io.out.land <= _T_345 @[el2_dec_dec_ctl.scala 41:15] + node _T_346 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_347 = eq(_T_346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_348 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_349 = and(_T_347, _T_348) @[el2_dec_dec_ctl.scala 17:17] + node _T_350 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_351 = eq(_T_350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_352 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_353 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_354 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_356 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_358 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_360 = and(_T_351, _T_352) @[el2_dec_dec_ctl.scala 17:17] + node _T_361 = and(_T_360, _T_353) @[el2_dec_dec_ctl.scala 17:17] + node _T_362 = and(_T_361, _T_355) @[el2_dec_dec_ctl.scala 17:17] + node _T_363 = and(_T_362, _T_357) @[el2_dec_dec_ctl.scala 17:17] + node _T_364 = and(_T_363, _T_359) @[el2_dec_dec_ctl.scala 17:17] + node _T_365 = or(_T_349, _T_364) @[el2_dec_dec_ctl.scala 42:37] + node _T_366 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_367 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_368 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_369 = and(_T_366, _T_367) @[el2_dec_dec_ctl.scala 17:17] + node _T_370 = and(_T_369, _T_368) @[el2_dec_dec_ctl.scala 17:17] + node _T_371 = or(_T_365, _T_370) @[el2_dec_dec_ctl.scala 42:74] + node _T_372 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_374 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_376 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_377 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_378 = and(_T_373, _T_375) @[el2_dec_dec_ctl.scala 17:17] + node _T_379 = and(_T_378, _T_376) @[el2_dec_dec_ctl.scala 17:17] + node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 17:17] + node _T_381 = or(_T_371, _T_380) @[el2_dec_dec_ctl.scala 43:26] + node _T_382 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_383 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_384 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_385 = eq(_T_384, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_386 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_388 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_390 = and(_T_382, _T_383) @[el2_dec_dec_ctl.scala 17:17] + node _T_391 = and(_T_390, _T_385) @[el2_dec_dec_ctl.scala 17:17] + node _T_392 = and(_T_391, _T_387) @[el2_dec_dec_ctl.scala 17:17] + node _T_393 = and(_T_392, _T_389) @[el2_dec_dec_ctl.scala 17:17] + node _T_394 = or(_T_381, _T_393) @[el2_dec_dec_ctl.scala 43:55] + io.out.lor <= _T_394 @[el2_dec_dec_ctl.scala 42:14] + node _T_395 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_397 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_398 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_399 = eq(_T_398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_400 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_401 = eq(_T_400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_402 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_403 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_405 = and(_T_396, _T_397) @[el2_dec_dec_ctl.scala 17:17] + node _T_406 = and(_T_405, _T_399) @[el2_dec_dec_ctl.scala 17:17] + node _T_407 = and(_T_406, _T_401) @[el2_dec_dec_ctl.scala 17:17] + node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 17:17] + node _T_409 = and(_T_408, _T_404) @[el2_dec_dec_ctl.scala 17:17] + node _T_410 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_411 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_412 = eq(_T_411, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_413 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_414 = eq(_T_413, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_415 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_417 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_418 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_420 = and(_T_410, _T_412) @[el2_dec_dec_ctl.scala 17:17] + node _T_421 = and(_T_420, _T_414) @[el2_dec_dec_ctl.scala 17:17] + node _T_422 = and(_T_421, _T_416) @[el2_dec_dec_ctl.scala 17:17] + node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 17:17] + node _T_424 = and(_T_423, _T_419) @[el2_dec_dec_ctl.scala 17:17] + node _T_425 = or(_T_409, _T_424) @[el2_dec_dec_ctl.scala 45:53] + io.out.lxor <= _T_425 @[el2_dec_dec_ctl.scala 45:15] + node _T_426 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_428 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_430 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_431 = eq(_T_430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_432 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_433 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_434 = eq(_T_433, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_435 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_436 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_438 = and(_T_427, _T_429) @[el2_dec_dec_ctl.scala 17:17] + node _T_439 = and(_T_438, _T_431) @[el2_dec_dec_ctl.scala 17:17] + node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 17:17] + node _T_441 = and(_T_440, _T_434) @[el2_dec_dec_ctl.scala 17:17] + node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 17:17] + node _T_443 = and(_T_442, _T_437) @[el2_dec_dec_ctl.scala 17:17] + io.out.sll <= _T_443 @[el2_dec_dec_ctl.scala 46:14] + node _T_444 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:34] + node _T_445 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_447 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_448 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_449 = eq(_T_448, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_450 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_451 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_453 = and(_T_444, _T_446) @[el2_dec_dec_ctl.scala 17:17] + node _T_454 = and(_T_453, _T_447) @[el2_dec_dec_ctl.scala 17:17] + node _T_455 = and(_T_454, _T_449) @[el2_dec_dec_ctl.scala 17:17] + node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 17:17] + node _T_457 = and(_T_456, _T_452) @[el2_dec_dec_ctl.scala 17:17] + io.out.sra <= _T_457 @[el2_dec_dec_ctl.scala 47:14] + node _T_458 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_460 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_461 = eq(_T_460, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_462 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_463 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_464 = eq(_T_463, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_465 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_466 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_468 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_469 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_471 = and(_T_459, _T_461) @[el2_dec_dec_ctl.scala 17:17] + node _T_472 = and(_T_471, _T_462) @[el2_dec_dec_ctl.scala 17:17] + node _T_473 = and(_T_472, _T_464) @[el2_dec_dec_ctl.scala 17:17] + node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 17:17] + node _T_475 = and(_T_474, _T_467) @[el2_dec_dec_ctl.scala 17:17] + node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 17:17] + node _T_477 = and(_T_476, _T_470) @[el2_dec_dec_ctl.scala 17:17] + io.out.srl <= _T_477 @[el2_dec_dec_ctl.scala 48:14] + node _T_478 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_479 = eq(_T_478, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_480 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_482 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_483 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_485 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_486 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_487 = eq(_T_486, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_488 = and(_T_479, _T_481) @[el2_dec_dec_ctl.scala 17:17] + node _T_489 = and(_T_488, _T_482) @[el2_dec_dec_ctl.scala 17:17] + node _T_490 = and(_T_489, _T_484) @[el2_dec_dec_ctl.scala 17:17] + node _T_491 = and(_T_490, _T_485) @[el2_dec_dec_ctl.scala 17:17] + node _T_492 = and(_T_491, _T_487) @[el2_dec_dec_ctl.scala 17:17] + node _T_493 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_495 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_496 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_498 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_499 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_501 = and(_T_494, _T_495) @[el2_dec_dec_ctl.scala 17:17] + node _T_502 = and(_T_501, _T_497) @[el2_dec_dec_ctl.scala 17:17] + node _T_503 = and(_T_502, _T_498) @[el2_dec_dec_ctl.scala 17:17] + node _T_504 = and(_T_503, _T_500) @[el2_dec_dec_ctl.scala 17:17] + node _T_505 = or(_T_492, _T_504) @[el2_dec_dec_ctl.scala 49:51] + io.out.slt <= _T_505 @[el2_dec_dec_ctl.scala 49:14] + node _T_506 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_507 = eq(_T_506, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_508 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_509 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_510 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_511 = eq(_T_510, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_512 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_513 = eq(_T_512, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_514 = and(_T_507, _T_508) @[el2_dec_dec_ctl.scala 17:17] + node _T_515 = and(_T_514, _T_509) @[el2_dec_dec_ctl.scala 17:17] + node _T_516 = and(_T_515, _T_511) @[el2_dec_dec_ctl.scala 17:17] + node _T_517 = and(_T_516, _T_513) @[el2_dec_dec_ctl.scala 17:17] + node _T_518 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_519 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_520 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_522 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_523 = eq(_T_522, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_524 = and(_T_518, _T_519) @[el2_dec_dec_ctl.scala 17:17] + node _T_525 = and(_T_524, _T_521) @[el2_dec_dec_ctl.scala 17:17] + node _T_526 = and(_T_525, _T_523) @[el2_dec_dec_ctl.scala 17:17] + node _T_527 = or(_T_517, _T_526) @[el2_dec_dec_ctl.scala 50:51] + node _T_528 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_529 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_530 = eq(_T_529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_531 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_533 = and(_T_528, _T_530) @[el2_dec_dec_ctl.scala 17:17] + node _T_534 = and(_T_533, _T_532) @[el2_dec_dec_ctl.scala 17:17] + node _T_535 = or(_T_527, _T_534) @[el2_dec_dec_ctl.scala 50:79] + node _T_536 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_537 = eq(_T_536, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_538 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_540 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_541 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_542 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_543 = eq(_T_542, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_544 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_545 = eq(_T_544, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_546 = and(_T_537, _T_539) @[el2_dec_dec_ctl.scala 17:17] + node _T_547 = and(_T_546, _T_540) @[el2_dec_dec_ctl.scala 17:17] + node _T_548 = and(_T_547, _T_541) @[el2_dec_dec_ctl.scala 17:17] + node _T_549 = and(_T_548, _T_543) @[el2_dec_dec_ctl.scala 17:17] + node _T_550 = and(_T_549, _T_545) @[el2_dec_dec_ctl.scala 17:17] + node _T_551 = or(_T_535, _T_550) @[el2_dec_dec_ctl.scala 51:29] + node _T_552 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_553 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_554 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_555 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_557 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_558 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_560 = and(_T_552, _T_553) @[el2_dec_dec_ctl.scala 17:17] + node _T_561 = and(_T_560, _T_554) @[el2_dec_dec_ctl.scala 17:17] + node _T_562 = and(_T_561, _T_556) @[el2_dec_dec_ctl.scala 17:17] + node _T_563 = and(_T_562, _T_557) @[el2_dec_dec_ctl.scala 17:17] + node _T_564 = and(_T_563, _T_559) @[el2_dec_dec_ctl.scala 17:17] + node _T_565 = or(_T_551, _T_564) @[el2_dec_dec_ctl.scala 51:66] + io.out.unsign <= _T_565 @[el2_dec_dec_ctl.scala 50:17] + node _T_566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_567 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_569 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_570 = eq(_T_569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_571 = and(_T_566, _T_568) @[el2_dec_dec_ctl.scala 17:17] + node _T_572 = and(_T_571, _T_570) @[el2_dec_dec_ctl.scala 17:17] + io.out.condbr <= _T_572 @[el2_dec_dec_ctl.scala 53:17] + node _T_573 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_574 = eq(_T_573, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_575 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_576 = eq(_T_575, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_577 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_578 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_580 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_582 = and(_T_574, _T_576) @[el2_dec_dec_ctl.scala 17:17] + node _T_583 = and(_T_582, _T_577) @[el2_dec_dec_ctl.scala 17:17] + node _T_584 = and(_T_583, _T_579) @[el2_dec_dec_ctl.scala 17:17] + node _T_585 = and(_T_584, _T_581) @[el2_dec_dec_ctl.scala 17:17] + io.out.beq <= _T_585 @[el2_dec_dec_ctl.scala 54:14] + node _T_586 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_587 = eq(_T_586, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_588 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_589 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_590 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_591 = eq(_T_590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_592 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_593 = eq(_T_592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_594 = and(_T_587, _T_588) @[el2_dec_dec_ctl.scala 17:17] + node _T_595 = and(_T_594, _T_589) @[el2_dec_dec_ctl.scala 17:17] + node _T_596 = and(_T_595, _T_591) @[el2_dec_dec_ctl.scala 17:17] + node _T_597 = and(_T_596, _T_593) @[el2_dec_dec_ctl.scala 17:17] + io.out.bne <= _T_597 @[el2_dec_dec_ctl.scala 55:14] + node _T_598 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_599 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_600 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_601 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_603 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_605 = and(_T_598, _T_599) @[el2_dec_dec_ctl.scala 17:17] + node _T_606 = and(_T_605, _T_600) @[el2_dec_dec_ctl.scala 17:17] + node _T_607 = and(_T_606, _T_602) @[el2_dec_dec_ctl.scala 17:17] + node _T_608 = and(_T_607, _T_604) @[el2_dec_dec_ctl.scala 17:17] + io.out.bge <= _T_608 @[el2_dec_dec_ctl.scala 56:14] + node _T_609 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_610 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_611 = eq(_T_610, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_612 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_613 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_615 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_616 = eq(_T_615, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_617 = and(_T_609, _T_611) @[el2_dec_dec_ctl.scala 17:17] + node _T_618 = and(_T_617, _T_612) @[el2_dec_dec_ctl.scala 17:17] + node _T_619 = and(_T_618, _T_614) @[el2_dec_dec_ctl.scala 17:17] + node _T_620 = and(_T_619, _T_616) @[el2_dec_dec_ctl.scala 17:17] + io.out.blt <= _T_620 @[el2_dec_dec_ctl.scala 57:14] + node _T_621 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_622 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_623 = and(_T_621, _T_622) @[el2_dec_dec_ctl.scala 17:17] + io.out.jal <= _T_623 @[el2_dec_dec_ctl.scala 58:14] + node _T_624 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_626 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_628 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_629 = eq(_T_628, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_630 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_632 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_634 = and(_T_625, _T_627) @[el2_dec_dec_ctl.scala 17:17] + node _T_635 = and(_T_634, _T_629) @[el2_dec_dec_ctl.scala 17:17] + node _T_636 = and(_T_635, _T_631) @[el2_dec_dec_ctl.scala 17:17] + node _T_637 = and(_T_636, _T_633) @[el2_dec_dec_ctl.scala 17:17] + io.out.by <= _T_637 @[el2_dec_dec_ctl.scala 59:13] + node _T_638 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_639 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_641 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_642 = eq(_T_641, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_643 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_644 = eq(_T_643, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_645 = and(_T_638, _T_640) @[el2_dec_dec_ctl.scala 17:17] + node _T_646 = and(_T_645, _T_642) @[el2_dec_dec_ctl.scala 17:17] + node _T_647 = and(_T_646, _T_644) @[el2_dec_dec_ctl.scala 17:17] + io.out.half <= _T_647 @[el2_dec_dec_ctl.scala 60:15] + node _T_648 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_649 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_650 = eq(_T_649, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_651 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_652 = eq(_T_651, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_653 = and(_T_648, _T_650) @[el2_dec_dec_ctl.scala 17:17] + node _T_654 = and(_T_653, _T_652) @[el2_dec_dec_ctl.scala 17:17] + io.out.word <= _T_654 @[el2_dec_dec_ctl.scala 61:15] + node _T_655 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_656 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_657 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_658 = and(_T_655, _T_656) @[el2_dec_dec_ctl.scala 17:17] + node _T_659 = and(_T_658, _T_657) @[el2_dec_dec_ctl.scala 17:17] + node _T_660 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_661 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_662 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_663 = and(_T_660, _T_661) @[el2_dec_dec_ctl.scala 17:17] + node _T_664 = and(_T_663, _T_662) @[el2_dec_dec_ctl.scala 17:17] + node _T_665 = or(_T_659, _T_664) @[el2_dec_dec_ctl.scala 62:44] + node _T_666 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_668 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_669 = and(_T_666, _T_667) @[el2_dec_dec_ctl.scala 17:17] + node _T_670 = and(_T_669, _T_668) @[el2_dec_dec_ctl.scala 17:17] + node _T_671 = or(_T_665, _T_670) @[el2_dec_dec_ctl.scala 62:67] + node _T_672 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_673 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_674 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_675 = and(_T_672, _T_673) @[el2_dec_dec_ctl.scala 17:17] + node _T_676 = and(_T_675, _T_674) @[el2_dec_dec_ctl.scala 17:17] + node _T_677 = or(_T_671, _T_676) @[el2_dec_dec_ctl.scala 63:26] + node _T_678 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_679 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_680 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_681 = and(_T_678, _T_679) @[el2_dec_dec_ctl.scala 17:17] + node _T_682 = and(_T_681, _T_680) @[el2_dec_dec_ctl.scala 17:17] + node _T_683 = or(_T_677, _T_682) @[el2_dec_dec_ctl.scala 63:49] + node _T_684 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_685 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_686 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_687 = and(_T_684, _T_685) @[el2_dec_dec_ctl.scala 17:17] + node _T_688 = and(_T_687, _T_686) @[el2_dec_dec_ctl.scala 17:17] + node _T_689 = or(_T_683, _T_688) @[el2_dec_dec_ctl.scala 63:73] + io.out.csr_read <= _T_689 @[el2_dec_dec_ctl.scala 62:19] + node _T_690 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_691 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_692 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_693 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_694 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_695 = and(_T_690, _T_691) @[el2_dec_dec_ctl.scala 17:17] + node _T_696 = and(_T_695, _T_692) @[el2_dec_dec_ctl.scala 17:17] + node _T_697 = and(_T_696, _T_693) @[el2_dec_dec_ctl.scala 17:17] + node _T_698 = and(_T_697, _T_694) @[el2_dec_dec_ctl.scala 17:17] + node _T_699 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_700 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_701 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_702 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_703 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_704 = and(_T_699, _T_700) @[el2_dec_dec_ctl.scala 17:17] + node _T_705 = and(_T_704, _T_701) @[el2_dec_dec_ctl.scala 17:17] + node _T_706 = and(_T_705, _T_702) @[el2_dec_dec_ctl.scala 17:17] + node _T_707 = and(_T_706, _T_703) @[el2_dec_dec_ctl.scala 17:17] + node _T_708 = or(_T_698, _T_707) @[el2_dec_dec_ctl.scala 65:49] + node _T_709 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_710 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_711 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_712 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_713 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_714 = and(_T_709, _T_710) @[el2_dec_dec_ctl.scala 17:17] + node _T_715 = and(_T_714, _T_711) @[el2_dec_dec_ctl.scala 17:17] + node _T_716 = and(_T_715, _T_712) @[el2_dec_dec_ctl.scala 17:17] + node _T_717 = and(_T_716, _T_713) @[el2_dec_dec_ctl.scala 17:17] + node _T_718 = or(_T_708, _T_717) @[el2_dec_dec_ctl.scala 65:79] + node _T_719 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_720 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_721 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_722 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_723 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_724 = and(_T_719, _T_720) @[el2_dec_dec_ctl.scala 17:17] + node _T_725 = and(_T_724, _T_721) @[el2_dec_dec_ctl.scala 17:17] + node _T_726 = and(_T_725, _T_722) @[el2_dec_dec_ctl.scala 17:17] + node _T_727 = and(_T_726, _T_723) @[el2_dec_dec_ctl.scala 17:17] + node _T_728 = or(_T_718, _T_727) @[el2_dec_dec_ctl.scala 66:33] + node _T_729 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_730 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_731 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_732 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_733 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_734 = and(_T_729, _T_730) @[el2_dec_dec_ctl.scala 17:17] + node _T_735 = and(_T_734, _T_731) @[el2_dec_dec_ctl.scala 17:17] + node _T_736 = and(_T_735, _T_732) @[el2_dec_dec_ctl.scala 17:17] + node _T_737 = and(_T_736, _T_733) @[el2_dec_dec_ctl.scala 17:17] + node _T_738 = or(_T_728, _T_737) @[el2_dec_dec_ctl.scala 66:63] + io.out.csr_clr <= _T_738 @[el2_dec_dec_ctl.scala 65:18] + node _T_739 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_740 = eq(_T_739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_741 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_742 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_743 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_744 = and(_T_740, _T_741) @[el2_dec_dec_ctl.scala 17:17] + node _T_745 = and(_T_744, _T_742) @[el2_dec_dec_ctl.scala 17:17] + node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 17:17] + io.out.csr_write <= _T_746 @[el2_dec_dec_ctl.scala 68:20] + node _T_747 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_748 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_749 = eq(_T_748, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_750 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_751 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_752 = and(_T_747, _T_749) @[el2_dec_dec_ctl.scala 17:17] + node _T_753 = and(_T_752, _T_750) @[el2_dec_dec_ctl.scala 17:17] + node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 17:17] + node _T_755 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_756 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_757 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_758 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_759 = and(_T_755, _T_756) @[el2_dec_dec_ctl.scala 17:17] + node _T_760 = and(_T_759, _T_757) @[el2_dec_dec_ctl.scala 17:17] + node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 17:17] + node _T_762 = or(_T_754, _T_761) @[el2_dec_dec_ctl.scala 69:47] + node _T_763 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_764 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_765 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_766 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_767 = and(_T_763, _T_764) @[el2_dec_dec_ctl.scala 17:17] + node _T_768 = and(_T_767, _T_765) @[el2_dec_dec_ctl.scala 17:17] + node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 17:17] + node _T_770 = or(_T_762, _T_769) @[el2_dec_dec_ctl.scala 69:74] + node _T_771 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_772 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_773 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_774 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_775 = and(_T_771, _T_772) @[el2_dec_dec_ctl.scala 17:17] + node _T_776 = and(_T_775, _T_773) @[el2_dec_dec_ctl.scala 17:17] + node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 17:17] + node _T_778 = or(_T_770, _T_777) @[el2_dec_dec_ctl.scala 70:30] + node _T_779 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_780 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_781 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_782 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_783 = and(_T_779, _T_780) @[el2_dec_dec_ctl.scala 17:17] + node _T_784 = and(_T_783, _T_781) @[el2_dec_dec_ctl.scala 17:17] + node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 17:17] + node _T_786 = or(_T_778, _T_785) @[el2_dec_dec_ctl.scala 70:57] + node _T_787 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_788 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_789 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_790 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_791 = and(_T_787, _T_788) @[el2_dec_dec_ctl.scala 17:17] + node _T_792 = and(_T_791, _T_789) @[el2_dec_dec_ctl.scala 17:17] + node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 17:17] + node _T_794 = or(_T_786, _T_793) @[el2_dec_dec_ctl.scala 71:30] + io.out.csr_imm <= _T_794 @[el2_dec_dec_ctl.scala 69:18] + node _T_795 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_796 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_798 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_799 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_800 = and(_T_795, _T_797) @[el2_dec_dec_ctl.scala 17:17] + node _T_801 = and(_T_800, _T_798) @[el2_dec_dec_ctl.scala 17:17] + node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 17:17] + node _T_803 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_804 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_805 = eq(_T_804, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_806 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_807 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_808 = and(_T_803, _T_805) @[el2_dec_dec_ctl.scala 17:17] + node _T_809 = and(_T_808, _T_806) @[el2_dec_dec_ctl.scala 17:17] + node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 17:17] + node _T_811 = or(_T_802, _T_810) @[el2_dec_dec_ctl.scala 72:47] + node _T_812 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_813 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_814 = eq(_T_813, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_815 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_816 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_817 = and(_T_812, _T_814) @[el2_dec_dec_ctl.scala 17:17] + node _T_818 = and(_T_817, _T_815) @[el2_dec_dec_ctl.scala 17:17] + node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 17:17] + node _T_820 = or(_T_811, _T_819) @[el2_dec_dec_ctl.scala 72:75] + node _T_821 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_822 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_823 = eq(_T_822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_824 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_825 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_826 = and(_T_821, _T_823) @[el2_dec_dec_ctl.scala 17:17] + node _T_827 = and(_T_826, _T_824) @[el2_dec_dec_ctl.scala 17:17] + node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 17:17] + node _T_829 = or(_T_820, _T_828) @[el2_dec_dec_ctl.scala 73:31] + node _T_830 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_831 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_832 = eq(_T_831, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_833 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_834 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_835 = and(_T_830, _T_832) @[el2_dec_dec_ctl.scala 17:17] + node _T_836 = and(_T_835, _T_833) @[el2_dec_dec_ctl.scala 17:17] + node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 17:17] + node _T_838 = or(_T_829, _T_837) @[el2_dec_dec_ctl.scala 73:59] + io.out.csr_set <= _T_838 @[el2_dec_dec_ctl.scala 72:18] + node _T_839 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_840 = eq(_T_839, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_841 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:34] + node _T_842 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_843 = eq(_T_842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_844 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_845 = eq(_T_844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_846 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_847 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_848 = and(_T_840, _T_841) @[el2_dec_dec_ctl.scala 17:17] + node _T_849 = and(_T_848, _T_843) @[el2_dec_dec_ctl.scala 17:17] + node _T_850 = and(_T_849, _T_845) @[el2_dec_dec_ctl.scala 17:17] + node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 17:17] + node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 17:17] + io.out.ebreak <= _T_852 @[el2_dec_dec_ctl.scala 75:17] + node _T_853 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_854 = eq(_T_853, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_855 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53] + node _T_856 = eq(_T_855, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_857 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_859 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_861 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_862 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_863 = and(_T_854, _T_856) @[el2_dec_dec_ctl.scala 17:17] + node _T_864 = and(_T_863, _T_858) @[el2_dec_dec_ctl.scala 17:17] + node _T_865 = and(_T_864, _T_860) @[el2_dec_dec_ctl.scala 17:17] + node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 17:17] + node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 17:17] + io.out.ecall <= _T_867 @[el2_dec_dec_ctl.scala 76:16] + node _T_868 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:34] + node _T_869 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_870 = eq(_T_869, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_871 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_872 = eq(_T_871, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_873 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_874 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_875 = and(_T_868, _T_870) @[el2_dec_dec_ctl.scala 17:17] + node _T_876 = and(_T_875, _T_872) @[el2_dec_dec_ctl.scala 17:17] + node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 17:17] + node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 17:17] + io.out.mret <= _T_878 @[el2_dec_dec_ctl.scala 77:15] + node _T_879 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_880 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_881 = eq(_T_880, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_882 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_883 = eq(_T_882, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_884 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_885 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_886 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_887 = eq(_T_886, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_888 = and(_T_879, _T_881) @[el2_dec_dec_ctl.scala 17:17] + node _T_889 = and(_T_888, _T_883) @[el2_dec_dec_ctl.scala 17:17] + node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 17:17] + node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 17:17] + node _T_892 = and(_T_891, _T_887) @[el2_dec_dec_ctl.scala 17:17] + io.out.mul <= _T_892 @[el2_dec_dec_ctl.scala 78:14] + node _T_893 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_894 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_896 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_897 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_898 = eq(_T_897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_899 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_900 = eq(_T_899, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_901 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_902 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_903 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_904 = eq(_T_903, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_905 = and(_T_893, _T_895) @[el2_dec_dec_ctl.scala 17:17] + node _T_906 = and(_T_905, _T_896) @[el2_dec_dec_ctl.scala 17:17] + node _T_907 = and(_T_906, _T_898) @[el2_dec_dec_ctl.scala 17:17] + node _T_908 = and(_T_907, _T_900) @[el2_dec_dec_ctl.scala 17:17] + node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 17:17] + node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 17:17] + node _T_911 = and(_T_910, _T_904) @[el2_dec_dec_ctl.scala 17:17] + node _T_912 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_913 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_914 = eq(_T_913, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_915 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_917 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_918 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_919 = eq(_T_918, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_920 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_921 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_922 = eq(_T_921, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_923 = and(_T_912, _T_914) @[el2_dec_dec_ctl.scala 17:17] + node _T_924 = and(_T_923, _T_916) @[el2_dec_dec_ctl.scala 17:17] + node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 17:17] + node _T_926 = and(_T_925, _T_919) @[el2_dec_dec_ctl.scala 17:17] + node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 17:17] + node _T_928 = and(_T_927, _T_922) @[el2_dec_dec_ctl.scala 17:17] + node _T_929 = or(_T_911, _T_928) @[el2_dec_dec_ctl.scala 79:61] + io.out.rs1_sign <= _T_929 @[el2_dec_dec_ctl.scala 79:19] + node _T_930 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_931 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_932 = eq(_T_931, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_933 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_934 = eq(_T_933, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_935 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_936 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_937 = eq(_T_936, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_938 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_939 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_941 = and(_T_930, _T_932) @[el2_dec_dec_ctl.scala 17:17] + node _T_942 = and(_T_941, _T_934) @[el2_dec_dec_ctl.scala 17:17] + node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 17:17] + node _T_944 = and(_T_943, _T_937) @[el2_dec_dec_ctl.scala 17:17] + node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 17:17] + node _T_946 = and(_T_945, _T_940) @[el2_dec_dec_ctl.scala 17:17] + io.out.rs2_sign <= _T_946 @[el2_dec_dec_ctl.scala 81:19] + node _T_947 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_948 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_950 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_952 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_953 = eq(_T_952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_954 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_955 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_956 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_957 = eq(_T_956, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_958 = and(_T_947, _T_949) @[el2_dec_dec_ctl.scala 17:17] + node _T_959 = and(_T_958, _T_951) @[el2_dec_dec_ctl.scala 17:17] + node _T_960 = and(_T_959, _T_953) @[el2_dec_dec_ctl.scala 17:17] + node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 17:17] + node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 17:17] + node _T_963 = and(_T_962, _T_957) @[el2_dec_dec_ctl.scala 17:17] + io.out.low <= _T_963 @[el2_dec_dec_ctl.scala 82:14] + node _T_964 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_965 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_966 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_967 = eq(_T_966, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_968 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_969 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_970 = eq(_T_969, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_971 = and(_T_964, _T_965) @[el2_dec_dec_ctl.scala 17:17] + node _T_972 = and(_T_971, _T_967) @[el2_dec_dec_ctl.scala 17:17] + node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 17:17] + node _T_974 = and(_T_973, _T_970) @[el2_dec_dec_ctl.scala 17:17] + io.out.div <= _T_974 @[el2_dec_dec_ctl.scala 83:14] + node _T_975 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_976 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_977 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_978 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_979 = eq(_T_978, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_980 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_981 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_983 = and(_T_975, _T_976) @[el2_dec_dec_ctl.scala 17:17] + node _T_984 = and(_T_983, _T_977) @[el2_dec_dec_ctl.scala 17:17] + node _T_985 = and(_T_984, _T_979) @[el2_dec_dec_ctl.scala 17:17] + node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 17:17] + node _T_987 = and(_T_986, _T_982) @[el2_dec_dec_ctl.scala 17:17] + io.out.rem <= _T_987 @[el2_dec_dec_ctl.scala 84:14] + node _T_988 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_989 = eq(_T_988, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_990 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_991 = and(_T_989, _T_990) @[el2_dec_dec_ctl.scala 17:17] + io.out.fence <= _T_991 @[el2_dec_dec_ctl.scala 85:16] + node _T_992 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_993 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_995 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_996 = and(_T_992, _T_994) @[el2_dec_dec_ctl.scala 17:17] + node _T_997 = and(_T_996, _T_995) @[el2_dec_dec_ctl.scala 17:17] + io.out.fence_i <= _T_997 @[el2_dec_dec_ctl.scala 86:18] + node _T_998 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34] + node _T_999 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:34] + node _T_1000 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1001 = eq(_T_1000, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1002 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1003 = eq(_T_1002, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1004 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1005 = and(_T_998, _T_999) @[el2_dec_dec_ctl.scala 17:17] + node _T_1006 = and(_T_1005, _T_1001) @[el2_dec_dec_ctl.scala 17:17] + node _T_1007 = and(_T_1006, _T_1003) @[el2_dec_dec_ctl.scala 17:17] + node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 17:17] + node _T_1009 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1010 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1011 = and(_T_1009, _T_1010) @[el2_dec_dec_ctl.scala 17:17] + node _T_1012 = or(_T_1008, _T_1011) @[el2_dec_dec_ctl.scala 87:51] + node _T_1013 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1015 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1016 = eq(_T_1015, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1017 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1018 = and(_T_1014, _T_1016) @[el2_dec_dec_ctl.scala 17:17] + node _T_1019 = and(_T_1018, _T_1017) @[el2_dec_dec_ctl.scala 17:17] + node _T_1020 = or(_T_1012, _T_1019) @[el2_dec_dec_ctl.scala 87:72] + node _T_1021 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1022 = eq(_T_1021, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1023 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1024 = and(_T_1022, _T_1023) @[el2_dec_dec_ctl.scala 17:17] + node _T_1025 = or(_T_1020, _T_1024) @[el2_dec_dec_ctl.scala 88:29] + io.out.pm_alu <= _T_1025 @[el2_dec_dec_ctl.scala 87:17] + node _T_1026 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1028 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1029 = and(_T_1027, _T_1028) @[el2_dec_dec_ctl.scala 17:17] + node _T_1030 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1032 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_1033 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1034 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1035 = and(_T_1031, _T_1032) @[el2_dec_dec_ctl.scala 17:17] + node _T_1036 = and(_T_1035, _T_1033) @[el2_dec_dec_ctl.scala 17:17] + node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 17:17] + node _T_1038 = or(_T_1029, _T_1037) @[el2_dec_dec_ctl.scala 89:41] + node _T_1039 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1040 = eq(_T_1039, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1041 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_1042 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1043 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1044 = and(_T_1040, _T_1041) @[el2_dec_dec_ctl.scala 17:17] + node _T_1045 = and(_T_1044, _T_1042) @[el2_dec_dec_ctl.scala 17:17] + node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 17:17] + node _T_1047 = or(_T_1038, _T_1046) @[el2_dec_dec_ctl.scala 89:68] + node _T_1048 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1049 = eq(_T_1048, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1050 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_1051 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1052 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1053 = and(_T_1049, _T_1050) @[el2_dec_dec_ctl.scala 17:17] + node _T_1054 = and(_T_1053, _T_1051) @[el2_dec_dec_ctl.scala 17:17] + node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 17:17] + node _T_1056 = or(_T_1047, _T_1055) @[el2_dec_dec_ctl.scala 90:30] + node _T_1057 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1058 = eq(_T_1057, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1059 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_1060 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1061 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1062 = and(_T_1058, _T_1059) @[el2_dec_dec_ctl.scala 17:17] + node _T_1063 = and(_T_1062, _T_1060) @[el2_dec_dec_ctl.scala 17:17] + node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 17:17] + node _T_1065 = or(_T_1056, _T_1064) @[el2_dec_dec_ctl.scala 90:57] + node _T_1066 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1068 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_1069 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1070 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1071 = and(_T_1067, _T_1068) @[el2_dec_dec_ctl.scala 17:17] + node _T_1072 = and(_T_1071, _T_1069) @[el2_dec_dec_ctl.scala 17:17] + node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 17:17] + node _T_1074 = or(_T_1065, _T_1073) @[el2_dec_dec_ctl.scala 91:31] + node _T_1075 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1077 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1078 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1079 = and(_T_1075, _T_1076) @[el2_dec_dec_ctl.scala 17:17] + node _T_1080 = and(_T_1079, _T_1077) @[el2_dec_dec_ctl.scala 17:17] + node _T_1081 = and(_T_1080, _T_1078) @[el2_dec_dec_ctl.scala 17:17] + node _T_1082 = or(_T_1074, _T_1081) @[el2_dec_dec_ctl.scala 91:59] + node _T_1083 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_1084 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1085 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1086 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1087 = and(_T_1083, _T_1084) @[el2_dec_dec_ctl.scala 17:17] + node _T_1088 = and(_T_1087, _T_1085) @[el2_dec_dec_ctl.scala 17:17] + node _T_1089 = and(_T_1088, _T_1086) @[el2_dec_dec_ctl.scala 17:17] + node _T_1090 = or(_T_1082, _T_1089) @[el2_dec_dec_ctl.scala 92:30] + node _T_1091 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_1092 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1093 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1094 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1095 = and(_T_1091, _T_1092) @[el2_dec_dec_ctl.scala 17:17] + node _T_1096 = and(_T_1095, _T_1093) @[el2_dec_dec_ctl.scala 17:17] + node _T_1097 = and(_T_1096, _T_1094) @[el2_dec_dec_ctl.scala 17:17] + node _T_1098 = or(_T_1090, _T_1097) @[el2_dec_dec_ctl.scala 92:57] + node _T_1099 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_1100 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1101 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1102 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1103 = and(_T_1099, _T_1100) @[el2_dec_dec_ctl.scala 17:17] + node _T_1104 = and(_T_1103, _T_1101) @[el2_dec_dec_ctl.scala 17:17] + node _T_1105 = and(_T_1104, _T_1102) @[el2_dec_dec_ctl.scala 17:17] + node _T_1106 = or(_T_1098, _T_1105) @[el2_dec_dec_ctl.scala 93:30] + node _T_1107 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_1108 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1109 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1111 = and(_T_1107, _T_1108) @[el2_dec_dec_ctl.scala 17:17] + node _T_1112 = and(_T_1111, _T_1109) @[el2_dec_dec_ctl.scala 17:17] + node _T_1113 = and(_T_1112, _T_1110) @[el2_dec_dec_ctl.scala 17:17] + node _T_1114 = or(_T_1106, _T_1113) @[el2_dec_dec_ctl.scala 93:57] + io.out.presync <= _T_1114 @[el2_dec_dec_ctl.scala 89:18] + node _T_1115 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_1116 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1118 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1119 = and(_T_1115, _T_1117) @[el2_dec_dec_ctl.scala 17:17] + node _T_1120 = and(_T_1119, _T_1118) @[el2_dec_dec_ctl.scala 17:17] + node _T_1121 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1123 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1126 = eq(_T_1125, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1127 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1128 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1129 = and(_T_1122, _T_1124) @[el2_dec_dec_ctl.scala 17:17] + node _T_1130 = and(_T_1129, _T_1126) @[el2_dec_dec_ctl.scala 17:17] + node _T_1131 = and(_T_1130, _T_1127) @[el2_dec_dec_ctl.scala 17:17] + node _T_1132 = and(_T_1131, _T_1128) @[el2_dec_dec_ctl.scala 17:17] + node _T_1133 = or(_T_1120, _T_1132) @[el2_dec_dec_ctl.scala 95:45] + node _T_1134 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1135 = eq(_T_1134, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1136 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1139 = and(_T_1135, _T_1136) @[el2_dec_dec_ctl.scala 17:17] + node _T_1140 = and(_T_1139, _T_1137) @[el2_dec_dec_ctl.scala 17:17] + node _T_1141 = and(_T_1140, _T_1138) @[el2_dec_dec_ctl.scala 17:17] + node _T_1142 = or(_T_1133, _T_1141) @[el2_dec_dec_ctl.scala 95:78] + node _T_1143 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1145 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_1146 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1147 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1148 = and(_T_1144, _T_1145) @[el2_dec_dec_ctl.scala 17:17] + node _T_1149 = and(_T_1148, _T_1146) @[el2_dec_dec_ctl.scala 17:17] + node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 17:17] + node _T_1151 = or(_T_1142, _T_1150) @[el2_dec_dec_ctl.scala 96:30] + node _T_1152 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1153 = eq(_T_1152, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1154 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_1155 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1156 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1157 = and(_T_1153, _T_1154) @[el2_dec_dec_ctl.scala 17:17] + node _T_1158 = and(_T_1157, _T_1155) @[el2_dec_dec_ctl.scala 17:17] + node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 17:17] + node _T_1160 = or(_T_1151, _T_1159) @[el2_dec_dec_ctl.scala 96:57] + node _T_1161 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1162 = eq(_T_1161, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1163 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_1164 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1165 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1166 = and(_T_1162, _T_1163) @[el2_dec_dec_ctl.scala 17:17] + node _T_1167 = and(_T_1166, _T_1164) @[el2_dec_dec_ctl.scala 17:17] + node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 17:17] + node _T_1169 = or(_T_1160, _T_1168) @[el2_dec_dec_ctl.scala 97:30] + node _T_1170 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1172 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_1173 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1174 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1175 = and(_T_1171, _T_1172) @[el2_dec_dec_ctl.scala 17:17] + node _T_1176 = and(_T_1175, _T_1173) @[el2_dec_dec_ctl.scala 17:17] + node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 17:17] + node _T_1178 = or(_T_1169, _T_1177) @[el2_dec_dec_ctl.scala 97:58] + node _T_1179 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1181 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1182 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1183 = and(_T_1179, _T_1180) @[el2_dec_dec_ctl.scala 17:17] + node _T_1184 = and(_T_1183, _T_1181) @[el2_dec_dec_ctl.scala 17:17] + node _T_1185 = and(_T_1184, _T_1182) @[el2_dec_dec_ctl.scala 17:17] + node _T_1186 = or(_T_1178, _T_1185) @[el2_dec_dec_ctl.scala 98:31] + node _T_1187 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_1188 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1189 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1190 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1191 = and(_T_1187, _T_1188) @[el2_dec_dec_ctl.scala 17:17] + node _T_1192 = and(_T_1191, _T_1189) @[el2_dec_dec_ctl.scala 17:17] + node _T_1193 = and(_T_1192, _T_1190) @[el2_dec_dec_ctl.scala 17:17] + node _T_1194 = or(_T_1186, _T_1193) @[el2_dec_dec_ctl.scala 98:58] + node _T_1195 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_1196 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1197 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1198 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1199 = and(_T_1195, _T_1196) @[el2_dec_dec_ctl.scala 17:17] + node _T_1200 = and(_T_1199, _T_1197) @[el2_dec_dec_ctl.scala 17:17] + node _T_1201 = and(_T_1200, _T_1198) @[el2_dec_dec_ctl.scala 17:17] + node _T_1202 = or(_T_1194, _T_1201) @[el2_dec_dec_ctl.scala 99:30] + node _T_1203 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_1204 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1205 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1206 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1207 = and(_T_1203, _T_1204) @[el2_dec_dec_ctl.scala 17:17] + node _T_1208 = and(_T_1207, _T_1205) @[el2_dec_dec_ctl.scala 17:17] + node _T_1209 = and(_T_1208, _T_1206) @[el2_dec_dec_ctl.scala 17:17] + node _T_1210 = or(_T_1202, _T_1209) @[el2_dec_dec_ctl.scala 99:57] + node _T_1211 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_1212 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1213 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1215 = and(_T_1211, _T_1212) @[el2_dec_dec_ctl.scala 17:17] + node _T_1216 = and(_T_1215, _T_1213) @[el2_dec_dec_ctl.scala 17:17] + node _T_1217 = and(_T_1216, _T_1214) @[el2_dec_dec_ctl.scala 17:17] + node _T_1218 = or(_T_1210, _T_1217) @[el2_dec_dec_ctl.scala 100:30] + io.out.postsync <= _T_1218 @[el2_dec_dec_ctl.scala 95:19] + node _T_1219 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1220 = eq(_T_1219, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1221 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1222 = eq(_T_1221, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1223 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:34] + node _T_1224 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34] + node _T_1225 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1226 = eq(_T_1225, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1227 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1228 = eq(_T_1227, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1229 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1231 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1233 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1234 = eq(_T_1233, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1235 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1237 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:34] + node _T_1238 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53] + node _T_1239 = eq(_T_1238, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1240 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1242 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1243 = eq(_T_1242, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1244 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1245 = eq(_T_1244, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1246 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1247 = eq(_T_1246, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1248 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1250 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1252 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1254 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1256 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1258 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1260 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1262 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1263 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1264 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1265 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1266 = eq(_T_1265, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1267 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1269 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1270 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1271 = and(_T_1220, _T_1222) @[el2_dec_dec_ctl.scala 17:17] + node _T_1272 = and(_T_1271, _T_1223) @[el2_dec_dec_ctl.scala 17:17] + node _T_1273 = and(_T_1272, _T_1224) @[el2_dec_dec_ctl.scala 17:17] + node _T_1274 = and(_T_1273, _T_1226) @[el2_dec_dec_ctl.scala 17:17] + node _T_1275 = and(_T_1274, _T_1228) @[el2_dec_dec_ctl.scala 17:17] + node _T_1276 = and(_T_1275, _T_1230) @[el2_dec_dec_ctl.scala 17:17] + node _T_1277 = and(_T_1276, _T_1232) @[el2_dec_dec_ctl.scala 17:17] + node _T_1278 = and(_T_1277, _T_1234) @[el2_dec_dec_ctl.scala 17:17] + node _T_1279 = and(_T_1278, _T_1236) @[el2_dec_dec_ctl.scala 17:17] + node _T_1280 = and(_T_1279, _T_1237) @[el2_dec_dec_ctl.scala 17:17] + node _T_1281 = and(_T_1280, _T_1239) @[el2_dec_dec_ctl.scala 17:17] + node _T_1282 = and(_T_1281, _T_1241) @[el2_dec_dec_ctl.scala 17:17] + node _T_1283 = and(_T_1282, _T_1243) @[el2_dec_dec_ctl.scala 17:17] + node _T_1284 = and(_T_1283, _T_1245) @[el2_dec_dec_ctl.scala 17:17] + node _T_1285 = and(_T_1284, _T_1247) @[el2_dec_dec_ctl.scala 17:17] + node _T_1286 = and(_T_1285, _T_1249) @[el2_dec_dec_ctl.scala 17:17] + node _T_1287 = and(_T_1286, _T_1251) @[el2_dec_dec_ctl.scala 17:17] + node _T_1288 = and(_T_1287, _T_1253) @[el2_dec_dec_ctl.scala 17:17] + node _T_1289 = and(_T_1288, _T_1255) @[el2_dec_dec_ctl.scala 17:17] + node _T_1290 = and(_T_1289, _T_1257) @[el2_dec_dec_ctl.scala 17:17] + node _T_1291 = and(_T_1290, _T_1259) @[el2_dec_dec_ctl.scala 17:17] + node _T_1292 = and(_T_1291, _T_1261) @[el2_dec_dec_ctl.scala 17:17] + node _T_1293 = and(_T_1292, _T_1262) @[el2_dec_dec_ctl.scala 17:17] + node _T_1294 = and(_T_1293, _T_1263) @[el2_dec_dec_ctl.scala 17:17] + node _T_1295 = and(_T_1294, _T_1264) @[el2_dec_dec_ctl.scala 17:17] + node _T_1296 = and(_T_1295, _T_1266) @[el2_dec_dec_ctl.scala 17:17] + node _T_1297 = and(_T_1296, _T_1268) @[el2_dec_dec_ctl.scala 17:17] + node _T_1298 = and(_T_1297, _T_1269) @[el2_dec_dec_ctl.scala 17:17] + node _T_1299 = and(_T_1298, _T_1270) @[el2_dec_dec_ctl.scala 17:17] + node _T_1300 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1302 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1304 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1306 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34] + node _T_1307 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1309 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1310 = eq(_T_1309, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1311 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1313 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1315 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1317 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:34] + node _T_1318 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1320 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:34] + node _T_1321 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1322 = eq(_T_1321, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1323 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1324 = eq(_T_1323, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1325 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1326 = eq(_T_1325, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1327 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1329 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1331 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1332 = eq(_T_1331, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1333 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1334 = eq(_T_1333, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1335 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1336 = eq(_T_1335, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1337 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1338 = eq(_T_1337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1339 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1340 = eq(_T_1339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1341 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1342 = eq(_T_1341, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1343 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1344 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1345 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1346 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1348 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1350 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1351 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1352 = and(_T_1301, _T_1303) @[el2_dec_dec_ctl.scala 17:17] + node _T_1353 = and(_T_1352, _T_1305) @[el2_dec_dec_ctl.scala 17:17] + node _T_1354 = and(_T_1353, _T_1306) @[el2_dec_dec_ctl.scala 17:17] + node _T_1355 = and(_T_1354, _T_1308) @[el2_dec_dec_ctl.scala 17:17] + node _T_1356 = and(_T_1355, _T_1310) @[el2_dec_dec_ctl.scala 17:17] + node _T_1357 = and(_T_1356, _T_1312) @[el2_dec_dec_ctl.scala 17:17] + node _T_1358 = and(_T_1357, _T_1314) @[el2_dec_dec_ctl.scala 17:17] + node _T_1359 = and(_T_1358, _T_1316) @[el2_dec_dec_ctl.scala 17:17] + node _T_1360 = and(_T_1359, _T_1317) @[el2_dec_dec_ctl.scala 17:17] + node _T_1361 = and(_T_1360, _T_1319) @[el2_dec_dec_ctl.scala 17:17] + node _T_1362 = and(_T_1361, _T_1320) @[el2_dec_dec_ctl.scala 17:17] + node _T_1363 = and(_T_1362, _T_1322) @[el2_dec_dec_ctl.scala 17:17] + node _T_1364 = and(_T_1363, _T_1324) @[el2_dec_dec_ctl.scala 17:17] + node _T_1365 = and(_T_1364, _T_1326) @[el2_dec_dec_ctl.scala 17:17] + node _T_1366 = and(_T_1365, _T_1328) @[el2_dec_dec_ctl.scala 17:17] + node _T_1367 = and(_T_1366, _T_1330) @[el2_dec_dec_ctl.scala 17:17] + node _T_1368 = and(_T_1367, _T_1332) @[el2_dec_dec_ctl.scala 17:17] + node _T_1369 = and(_T_1368, _T_1334) @[el2_dec_dec_ctl.scala 17:17] + node _T_1370 = and(_T_1369, _T_1336) @[el2_dec_dec_ctl.scala 17:17] + node _T_1371 = and(_T_1370, _T_1338) @[el2_dec_dec_ctl.scala 17:17] + node _T_1372 = and(_T_1371, _T_1340) @[el2_dec_dec_ctl.scala 17:17] + node _T_1373 = and(_T_1372, _T_1342) @[el2_dec_dec_ctl.scala 17:17] + node _T_1374 = and(_T_1373, _T_1343) @[el2_dec_dec_ctl.scala 17:17] + node _T_1375 = and(_T_1374, _T_1344) @[el2_dec_dec_ctl.scala 17:17] + node _T_1376 = and(_T_1375, _T_1345) @[el2_dec_dec_ctl.scala 17:17] + node _T_1377 = and(_T_1376, _T_1347) @[el2_dec_dec_ctl.scala 17:17] + node _T_1378 = and(_T_1377, _T_1349) @[el2_dec_dec_ctl.scala 17:17] + node _T_1379 = and(_T_1378, _T_1350) @[el2_dec_dec_ctl.scala 17:17] + node _T_1380 = and(_T_1379, _T_1351) @[el2_dec_dec_ctl.scala 17:17] + node _T_1381 = or(_T_1299, _T_1380) @[el2_dec_dec_ctl.scala 101:136] + node _T_1382 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1383 = eq(_T_1382, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1384 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1385 = eq(_T_1384, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1386 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1388 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1390 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1391 = eq(_T_1390, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1392 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1393 = eq(_T_1392, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1394 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1396 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1398 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1400 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1402 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1404 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1406 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1408 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1410 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1412 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1414 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1416 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1418 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1420 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1422 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1424 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1426 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1427 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1428 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1430 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1432 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1433 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1434 = and(_T_1383, _T_1385) @[el2_dec_dec_ctl.scala 17:17] + node _T_1435 = and(_T_1434, _T_1387) @[el2_dec_dec_ctl.scala 17:17] + node _T_1436 = and(_T_1435, _T_1389) @[el2_dec_dec_ctl.scala 17:17] + node _T_1437 = and(_T_1436, _T_1391) @[el2_dec_dec_ctl.scala 17:17] + node _T_1438 = and(_T_1437, _T_1393) @[el2_dec_dec_ctl.scala 17:17] + node _T_1439 = and(_T_1438, _T_1395) @[el2_dec_dec_ctl.scala 17:17] + node _T_1440 = and(_T_1439, _T_1397) @[el2_dec_dec_ctl.scala 17:17] + node _T_1441 = and(_T_1440, _T_1399) @[el2_dec_dec_ctl.scala 17:17] + node _T_1442 = and(_T_1441, _T_1401) @[el2_dec_dec_ctl.scala 17:17] + node _T_1443 = and(_T_1442, _T_1403) @[el2_dec_dec_ctl.scala 17:17] + node _T_1444 = and(_T_1443, _T_1405) @[el2_dec_dec_ctl.scala 17:17] + node _T_1445 = and(_T_1444, _T_1407) @[el2_dec_dec_ctl.scala 17:17] + node _T_1446 = and(_T_1445, _T_1409) @[el2_dec_dec_ctl.scala 17:17] + node _T_1447 = and(_T_1446, _T_1411) @[el2_dec_dec_ctl.scala 17:17] + node _T_1448 = and(_T_1447, _T_1413) @[el2_dec_dec_ctl.scala 17:17] + node _T_1449 = and(_T_1448, _T_1415) @[el2_dec_dec_ctl.scala 17:17] + node _T_1450 = and(_T_1449, _T_1417) @[el2_dec_dec_ctl.scala 17:17] + node _T_1451 = and(_T_1450, _T_1419) @[el2_dec_dec_ctl.scala 17:17] + node _T_1452 = and(_T_1451, _T_1421) @[el2_dec_dec_ctl.scala 17:17] + node _T_1453 = and(_T_1452, _T_1423) @[el2_dec_dec_ctl.scala 17:17] + node _T_1454 = and(_T_1453, _T_1425) @[el2_dec_dec_ctl.scala 17:17] + node _T_1455 = and(_T_1454, _T_1426) @[el2_dec_dec_ctl.scala 17:17] + node _T_1456 = and(_T_1455, _T_1427) @[el2_dec_dec_ctl.scala 17:17] + node _T_1457 = and(_T_1456, _T_1429) @[el2_dec_dec_ctl.scala 17:17] + node _T_1458 = and(_T_1457, _T_1431) @[el2_dec_dec_ctl.scala 17:17] + node _T_1459 = and(_T_1458, _T_1432) @[el2_dec_dec_ctl.scala 17:17] + node _T_1460 = and(_T_1459, _T_1433) @[el2_dec_dec_ctl.scala 17:17] + node _T_1461 = or(_T_1381, _T_1460) @[el2_dec_dec_ctl.scala 102:122] + node _T_1462 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1463 = eq(_T_1462, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1464 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1465 = eq(_T_1464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1466 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1467 = eq(_T_1466, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1468 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1469 = eq(_T_1468, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1470 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1471 = eq(_T_1470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1472 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1473 = eq(_T_1472, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1474 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1475 = eq(_T_1474, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1476 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1478 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1479 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1481 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1482 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1483 = and(_T_1463, _T_1465) @[el2_dec_dec_ctl.scala 17:17] + node _T_1484 = and(_T_1483, _T_1467) @[el2_dec_dec_ctl.scala 17:17] + node _T_1485 = and(_T_1484, _T_1469) @[el2_dec_dec_ctl.scala 17:17] + node _T_1486 = and(_T_1485, _T_1471) @[el2_dec_dec_ctl.scala 17:17] + node _T_1487 = and(_T_1486, _T_1473) @[el2_dec_dec_ctl.scala 17:17] + node _T_1488 = and(_T_1487, _T_1475) @[el2_dec_dec_ctl.scala 17:17] + node _T_1489 = and(_T_1488, _T_1477) @[el2_dec_dec_ctl.scala 17:17] + node _T_1490 = and(_T_1489, _T_1478) @[el2_dec_dec_ctl.scala 17:17] + node _T_1491 = and(_T_1490, _T_1480) @[el2_dec_dec_ctl.scala 17:17] + node _T_1492 = and(_T_1491, _T_1481) @[el2_dec_dec_ctl.scala 17:17] + node _T_1493 = and(_T_1492, _T_1482) @[el2_dec_dec_ctl.scala 17:17] + node _T_1494 = or(_T_1461, _T_1493) @[el2_dec_dec_ctl.scala 103:119] + node _T_1495 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1497 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1499 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1500 = eq(_T_1499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1501 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1502 = eq(_T_1501, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1503 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1504 = eq(_T_1503, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1505 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1506 = eq(_T_1505, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1507 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1508 = eq(_T_1507, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1509 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1511 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1513 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1515 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1517 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1519 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1520 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1521 = and(_T_1496, _T_1498) @[el2_dec_dec_ctl.scala 17:17] + node _T_1522 = and(_T_1521, _T_1500) @[el2_dec_dec_ctl.scala 17:17] + node _T_1523 = and(_T_1522, _T_1502) @[el2_dec_dec_ctl.scala 17:17] + node _T_1524 = and(_T_1523, _T_1504) @[el2_dec_dec_ctl.scala 17:17] + node _T_1525 = and(_T_1524, _T_1506) @[el2_dec_dec_ctl.scala 17:17] + node _T_1526 = and(_T_1525, _T_1508) @[el2_dec_dec_ctl.scala 17:17] + node _T_1527 = and(_T_1526, _T_1510) @[el2_dec_dec_ctl.scala 17:17] + node _T_1528 = and(_T_1527, _T_1512) @[el2_dec_dec_ctl.scala 17:17] + node _T_1529 = and(_T_1528, _T_1514) @[el2_dec_dec_ctl.scala 17:17] + node _T_1530 = and(_T_1529, _T_1516) @[el2_dec_dec_ctl.scala 17:17] + node _T_1531 = and(_T_1530, _T_1518) @[el2_dec_dec_ctl.scala 17:17] + node _T_1532 = and(_T_1531, _T_1519) @[el2_dec_dec_ctl.scala 17:17] + node _T_1533 = and(_T_1532, _T_1520) @[el2_dec_dec_ctl.scala 17:17] + node _T_1534 = or(_T_1494, _T_1533) @[el2_dec_dec_ctl.scala 104:60] + node _T_1535 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1536 = eq(_T_1535, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1537 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1538 = eq(_T_1537, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1539 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1541 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1542 = eq(_T_1541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1543 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1544 = eq(_T_1543, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1545 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1547 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_1548 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1550 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_1551 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1552 = eq(_T_1551, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1553 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1554 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1556 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1557 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1558 = and(_T_1536, _T_1538) @[el2_dec_dec_ctl.scala 17:17] + node _T_1559 = and(_T_1558, _T_1540) @[el2_dec_dec_ctl.scala 17:17] + node _T_1560 = and(_T_1559, _T_1542) @[el2_dec_dec_ctl.scala 17:17] + node _T_1561 = and(_T_1560, _T_1544) @[el2_dec_dec_ctl.scala 17:17] + node _T_1562 = and(_T_1561, _T_1546) @[el2_dec_dec_ctl.scala 17:17] + node _T_1563 = and(_T_1562, _T_1547) @[el2_dec_dec_ctl.scala 17:17] + node _T_1564 = and(_T_1563, _T_1549) @[el2_dec_dec_ctl.scala 17:17] + node _T_1565 = and(_T_1564, _T_1550) @[el2_dec_dec_ctl.scala 17:17] + node _T_1566 = and(_T_1565, _T_1552) @[el2_dec_dec_ctl.scala 17:17] + node _T_1567 = and(_T_1566, _T_1553) @[el2_dec_dec_ctl.scala 17:17] + node _T_1568 = and(_T_1567, _T_1555) @[el2_dec_dec_ctl.scala 17:17] + node _T_1569 = and(_T_1568, _T_1556) @[el2_dec_dec_ctl.scala 17:17] + node _T_1570 = and(_T_1569, _T_1557) @[el2_dec_dec_ctl.scala 17:17] + node _T_1571 = or(_T_1534, _T_1570) @[el2_dec_dec_ctl.scala 105:69] + node _T_1572 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1574 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1575 = eq(_T_1574, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1576 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1577 = eq(_T_1576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1578 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1579 = eq(_T_1578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1580 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1581 = eq(_T_1580, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1582 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1584 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1586 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1587 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1588 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1590 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1591 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1592 = and(_T_1573, _T_1575) @[el2_dec_dec_ctl.scala 17:17] + node _T_1593 = and(_T_1592, _T_1577) @[el2_dec_dec_ctl.scala 17:17] + node _T_1594 = and(_T_1593, _T_1579) @[el2_dec_dec_ctl.scala 17:17] + node _T_1595 = and(_T_1594, _T_1581) @[el2_dec_dec_ctl.scala 17:17] + node _T_1596 = and(_T_1595, _T_1583) @[el2_dec_dec_ctl.scala 17:17] + node _T_1597 = and(_T_1596, _T_1585) @[el2_dec_dec_ctl.scala 17:17] + node _T_1598 = and(_T_1597, _T_1586) @[el2_dec_dec_ctl.scala 17:17] + node _T_1599 = and(_T_1598, _T_1587) @[el2_dec_dec_ctl.scala 17:17] + node _T_1600 = and(_T_1599, _T_1589) @[el2_dec_dec_ctl.scala 17:17] + node _T_1601 = and(_T_1600, _T_1590) @[el2_dec_dec_ctl.scala 17:17] + node _T_1602 = and(_T_1601, _T_1591) @[el2_dec_dec_ctl.scala 17:17] + node _T_1603 = or(_T_1571, _T_1602) @[el2_dec_dec_ctl.scala 106:66] + node _T_1604 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1606 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1607 = eq(_T_1606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1608 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1609 = eq(_T_1608, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1610 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1611 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1612 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1613 = eq(_T_1612, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1614 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1615 = eq(_T_1614, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1616 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1617 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1618 = and(_T_1605, _T_1607) @[el2_dec_dec_ctl.scala 17:17] + node _T_1619 = and(_T_1618, _T_1609) @[el2_dec_dec_ctl.scala 17:17] + node _T_1620 = and(_T_1619, _T_1610) @[el2_dec_dec_ctl.scala 17:17] + node _T_1621 = and(_T_1620, _T_1611) @[el2_dec_dec_ctl.scala 17:17] + node _T_1622 = and(_T_1621, _T_1613) @[el2_dec_dec_ctl.scala 17:17] + node _T_1623 = and(_T_1622, _T_1615) @[el2_dec_dec_ctl.scala 17:17] + node _T_1624 = and(_T_1623, _T_1616) @[el2_dec_dec_ctl.scala 17:17] + node _T_1625 = and(_T_1624, _T_1617) @[el2_dec_dec_ctl.scala 17:17] + node _T_1626 = or(_T_1603, _T_1625) @[el2_dec_dec_ctl.scala 107:58] + node _T_1627 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_1628 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1629 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1630 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1631 = eq(_T_1630, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1632 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1633 = eq(_T_1632, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1634 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1636 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1637 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1638 = and(_T_1627, _T_1628) @[el2_dec_dec_ctl.scala 17:17] + node _T_1639 = and(_T_1638, _T_1629) @[el2_dec_dec_ctl.scala 17:17] + node _T_1640 = and(_T_1639, _T_1631) @[el2_dec_dec_ctl.scala 17:17] + node _T_1641 = and(_T_1640, _T_1633) @[el2_dec_dec_ctl.scala 17:17] + node _T_1642 = and(_T_1641, _T_1635) @[el2_dec_dec_ctl.scala 17:17] + node _T_1643 = and(_T_1642, _T_1636) @[el2_dec_dec_ctl.scala 17:17] + node _T_1644 = and(_T_1643, _T_1637) @[el2_dec_dec_ctl.scala 17:17] + node _T_1645 = or(_T_1626, _T_1644) @[el2_dec_dec_ctl.scala 108:46] + node _T_1646 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1647 = eq(_T_1646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1648 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1650 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1652 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1653 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1654 = eq(_T_1653, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1655 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1656 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1657 = and(_T_1647, _T_1649) @[el2_dec_dec_ctl.scala 17:17] + node _T_1658 = and(_T_1657, _T_1651) @[el2_dec_dec_ctl.scala 17:17] + node _T_1659 = and(_T_1658, _T_1652) @[el2_dec_dec_ctl.scala 17:17] + node _T_1660 = and(_T_1659, _T_1654) @[el2_dec_dec_ctl.scala 17:17] + node _T_1661 = and(_T_1660, _T_1655) @[el2_dec_dec_ctl.scala 17:17] + node _T_1662 = and(_T_1661, _T_1656) @[el2_dec_dec_ctl.scala 17:17] + node _T_1663 = or(_T_1645, _T_1662) @[el2_dec_dec_ctl.scala 109:40] + node _T_1664 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1665 = eq(_T_1664, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1666 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1668 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1669 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1671 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1672 = eq(_T_1671, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1673 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1674 = eq(_T_1673, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1675 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1676 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1677 = and(_T_1665, _T_1667) @[el2_dec_dec_ctl.scala 17:17] + node _T_1678 = and(_T_1677, _T_1668) @[el2_dec_dec_ctl.scala 17:17] + node _T_1679 = and(_T_1678, _T_1670) @[el2_dec_dec_ctl.scala 17:17] + node _T_1680 = and(_T_1679, _T_1672) @[el2_dec_dec_ctl.scala 17:17] + node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 17:17] + node _T_1682 = and(_T_1681, _T_1675) @[el2_dec_dec_ctl.scala 17:17] + node _T_1683 = and(_T_1682, _T_1676) @[el2_dec_dec_ctl.scala 17:17] + node _T_1684 = or(_T_1663, _T_1683) @[el2_dec_dec_ctl.scala 110:39] + node _T_1685 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_1686 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1687 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1688 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1689 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1691 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1693 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1694 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1695 = and(_T_1685, _T_1686) @[el2_dec_dec_ctl.scala 17:17] + node _T_1696 = and(_T_1695, _T_1687) @[el2_dec_dec_ctl.scala 17:17] + node _T_1697 = and(_T_1696, _T_1688) @[el2_dec_dec_ctl.scala 17:17] + node _T_1698 = and(_T_1697, _T_1690) @[el2_dec_dec_ctl.scala 17:17] + node _T_1699 = and(_T_1698, _T_1692) @[el2_dec_dec_ctl.scala 17:17] + node _T_1700 = and(_T_1699, _T_1693) @[el2_dec_dec_ctl.scala 17:17] + node _T_1701 = and(_T_1700, _T_1694) @[el2_dec_dec_ctl.scala 17:17] + node _T_1702 = or(_T_1684, _T_1701) @[el2_dec_dec_ctl.scala 111:43] + node _T_1703 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1704 = eq(_T_1703, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1705 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1706 = eq(_T_1705, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1707 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1708 = eq(_T_1707, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1709 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1711 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1712 = eq(_T_1711, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1713 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1714 = eq(_T_1713, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1715 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1717 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1718 = eq(_T_1717, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1719 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1720 = eq(_T_1719, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1721 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1722 = eq(_T_1721, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1723 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_1724 = eq(_T_1723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1725 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53] + node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1727 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1729 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1731 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1733 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1735 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1737 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1739 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1741 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1743 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1745 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1747 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1749 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1753 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1755 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1757 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1758 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1759 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1760 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1761 = and(_T_1704, _T_1706) @[el2_dec_dec_ctl.scala 17:17] + node _T_1762 = and(_T_1761, _T_1708) @[el2_dec_dec_ctl.scala 17:17] + node _T_1763 = and(_T_1762, _T_1710) @[el2_dec_dec_ctl.scala 17:17] + node _T_1764 = and(_T_1763, _T_1712) @[el2_dec_dec_ctl.scala 17:17] + node _T_1765 = and(_T_1764, _T_1714) @[el2_dec_dec_ctl.scala 17:17] + node _T_1766 = and(_T_1765, _T_1716) @[el2_dec_dec_ctl.scala 17:17] + node _T_1767 = and(_T_1766, _T_1718) @[el2_dec_dec_ctl.scala 17:17] + node _T_1768 = and(_T_1767, _T_1720) @[el2_dec_dec_ctl.scala 17:17] + node _T_1769 = and(_T_1768, _T_1722) @[el2_dec_dec_ctl.scala 17:17] + node _T_1770 = and(_T_1769, _T_1724) @[el2_dec_dec_ctl.scala 17:17] + node _T_1771 = and(_T_1770, _T_1726) @[el2_dec_dec_ctl.scala 17:17] + node _T_1772 = and(_T_1771, _T_1728) @[el2_dec_dec_ctl.scala 17:17] + node _T_1773 = and(_T_1772, _T_1730) @[el2_dec_dec_ctl.scala 17:17] + node _T_1774 = and(_T_1773, _T_1732) @[el2_dec_dec_ctl.scala 17:17] + node _T_1775 = and(_T_1774, _T_1734) @[el2_dec_dec_ctl.scala 17:17] + node _T_1776 = and(_T_1775, _T_1736) @[el2_dec_dec_ctl.scala 17:17] + node _T_1777 = and(_T_1776, _T_1738) @[el2_dec_dec_ctl.scala 17:17] + node _T_1778 = and(_T_1777, _T_1740) @[el2_dec_dec_ctl.scala 17:17] + node _T_1779 = and(_T_1778, _T_1742) @[el2_dec_dec_ctl.scala 17:17] + node _T_1780 = and(_T_1779, _T_1744) @[el2_dec_dec_ctl.scala 17:17] + node _T_1781 = and(_T_1780, _T_1746) @[el2_dec_dec_ctl.scala 17:17] + node _T_1782 = and(_T_1781, _T_1748) @[el2_dec_dec_ctl.scala 17:17] + node _T_1783 = and(_T_1782, _T_1750) @[el2_dec_dec_ctl.scala 17:17] + node _T_1784 = and(_T_1783, _T_1752) @[el2_dec_dec_ctl.scala 17:17] + node _T_1785 = and(_T_1784, _T_1754) @[el2_dec_dec_ctl.scala 17:17] + node _T_1786 = and(_T_1785, _T_1756) @[el2_dec_dec_ctl.scala 17:17] + node _T_1787 = and(_T_1786, _T_1757) @[el2_dec_dec_ctl.scala 17:17] + node _T_1788 = and(_T_1787, _T_1758) @[el2_dec_dec_ctl.scala 17:17] + node _T_1789 = and(_T_1788, _T_1759) @[el2_dec_dec_ctl.scala 17:17] + node _T_1790 = and(_T_1789, _T_1760) @[el2_dec_dec_ctl.scala 17:17] + node _T_1791 = or(_T_1702, _T_1790) @[el2_dec_dec_ctl.scala 112:39] + node _T_1792 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1793 = eq(_T_1792, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1794 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1796 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1797 = eq(_T_1796, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1798 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1799 = eq(_T_1798, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1800 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1802 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1803 = eq(_T_1802, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1804 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1805 = eq(_T_1804, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1806 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1807 = eq(_T_1806, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1808 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1809 = eq(_T_1808, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1810 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1811 = eq(_T_1810, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1812 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1813 = eq(_T_1812, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1815 = eq(_T_1814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1816 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1817 = eq(_T_1816, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1818 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1820 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1822 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1824 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1826 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1828 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1830 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1832 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1833 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1834 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1835 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1836 = and(_T_1793, _T_1795) @[el2_dec_dec_ctl.scala 17:17] + node _T_1837 = and(_T_1836, _T_1797) @[el2_dec_dec_ctl.scala 17:17] + node _T_1838 = and(_T_1837, _T_1799) @[el2_dec_dec_ctl.scala 17:17] + node _T_1839 = and(_T_1838, _T_1801) @[el2_dec_dec_ctl.scala 17:17] + node _T_1840 = and(_T_1839, _T_1803) @[el2_dec_dec_ctl.scala 17:17] + node _T_1841 = and(_T_1840, _T_1805) @[el2_dec_dec_ctl.scala 17:17] + node _T_1842 = and(_T_1841, _T_1807) @[el2_dec_dec_ctl.scala 17:17] + node _T_1843 = and(_T_1842, _T_1809) @[el2_dec_dec_ctl.scala 17:17] + node _T_1844 = and(_T_1843, _T_1811) @[el2_dec_dec_ctl.scala 17:17] + node _T_1845 = and(_T_1844, _T_1813) @[el2_dec_dec_ctl.scala 17:17] + node _T_1846 = and(_T_1845, _T_1815) @[el2_dec_dec_ctl.scala 17:17] + node _T_1847 = and(_T_1846, _T_1817) @[el2_dec_dec_ctl.scala 17:17] + node _T_1848 = and(_T_1847, _T_1819) @[el2_dec_dec_ctl.scala 17:17] + node _T_1849 = and(_T_1848, _T_1821) @[el2_dec_dec_ctl.scala 17:17] + node _T_1850 = and(_T_1849, _T_1823) @[el2_dec_dec_ctl.scala 17:17] + node _T_1851 = and(_T_1850, _T_1825) @[el2_dec_dec_ctl.scala 17:17] + node _T_1852 = and(_T_1851, _T_1827) @[el2_dec_dec_ctl.scala 17:17] + node _T_1853 = and(_T_1852, _T_1829) @[el2_dec_dec_ctl.scala 17:17] + node _T_1854 = and(_T_1853, _T_1831) @[el2_dec_dec_ctl.scala 17:17] + node _T_1855 = and(_T_1854, _T_1832) @[el2_dec_dec_ctl.scala 17:17] + node _T_1856 = and(_T_1855, _T_1833) @[el2_dec_dec_ctl.scala 17:17] + node _T_1857 = and(_T_1856, _T_1834) @[el2_dec_dec_ctl.scala 17:17] + node _T_1858 = and(_T_1857, _T_1835) @[el2_dec_dec_ctl.scala 17:17] + node _T_1859 = or(_T_1791, _T_1858) @[el2_dec_dec_ctl.scala 113:130] + node _T_1860 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1861 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1862 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1864 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1866 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1867 = eq(_T_1866, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1868 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1869 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1870 = and(_T_1860, _T_1861) @[el2_dec_dec_ctl.scala 17:17] + node _T_1871 = and(_T_1870, _T_1862) @[el2_dec_dec_ctl.scala 17:17] + node _T_1872 = and(_T_1871, _T_1863) @[el2_dec_dec_ctl.scala 17:17] + node _T_1873 = and(_T_1872, _T_1865) @[el2_dec_dec_ctl.scala 17:17] + node _T_1874 = and(_T_1873, _T_1867) @[el2_dec_dec_ctl.scala 17:17] + node _T_1875 = and(_T_1874, _T_1868) @[el2_dec_dec_ctl.scala 17:17] + node _T_1876 = and(_T_1875, _T_1869) @[el2_dec_dec_ctl.scala 17:17] + node _T_1877 = or(_T_1859, _T_1876) @[el2_dec_dec_ctl.scala 114:102] + node _T_1878 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1879 = eq(_T_1878, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1880 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1881 = eq(_T_1880, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1882 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1883 = eq(_T_1882, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1884 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1885 = eq(_T_1884, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1886 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1887 = eq(_T_1886, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1888 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1889 = eq(_T_1888, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1890 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1891 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1892 = and(_T_1879, _T_1881) @[el2_dec_dec_ctl.scala 17:17] + node _T_1893 = and(_T_1892, _T_1883) @[el2_dec_dec_ctl.scala 17:17] + node _T_1894 = and(_T_1893, _T_1885) @[el2_dec_dec_ctl.scala 17:17] + node _T_1895 = and(_T_1894, _T_1887) @[el2_dec_dec_ctl.scala 17:17] + node _T_1896 = and(_T_1895, _T_1889) @[el2_dec_dec_ctl.scala 17:17] + node _T_1897 = and(_T_1896, _T_1890) @[el2_dec_dec_ctl.scala 17:17] + node _T_1898 = and(_T_1897, _T_1891) @[el2_dec_dec_ctl.scala 17:17] + node _T_1899 = or(_T_1877, _T_1898) @[el2_dec_dec_ctl.scala 115:39] + node _T_1900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1901 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1902 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1903 = eq(_T_1902, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1904 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1905 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1906 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1907 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1908 = and(_T_1900, _T_1901) @[el2_dec_dec_ctl.scala 17:17] + node _T_1909 = and(_T_1908, _T_1903) @[el2_dec_dec_ctl.scala 17:17] + node _T_1910 = and(_T_1909, _T_1904) @[el2_dec_dec_ctl.scala 17:17] + node _T_1911 = and(_T_1910, _T_1905) @[el2_dec_dec_ctl.scala 17:17] + node _T_1912 = and(_T_1911, _T_1906) @[el2_dec_dec_ctl.scala 17:17] + node _T_1913 = and(_T_1912, _T_1907) @[el2_dec_dec_ctl.scala 17:17] + node _T_1914 = or(_T_1899, _T_1913) @[el2_dec_dec_ctl.scala 116:43] + node _T_1915 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1916 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1917 = eq(_T_1916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1918 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1920 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1921 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1922 = eq(_T_1921, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1923 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1924 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1925 = and(_T_1915, _T_1917) @[el2_dec_dec_ctl.scala 17:17] + node _T_1926 = and(_T_1925, _T_1919) @[el2_dec_dec_ctl.scala 17:17] + node _T_1927 = and(_T_1926, _T_1920) @[el2_dec_dec_ctl.scala 17:17] + node _T_1928 = and(_T_1927, _T_1922) @[el2_dec_dec_ctl.scala 17:17] + node _T_1929 = and(_T_1928, _T_1923) @[el2_dec_dec_ctl.scala 17:17] + node _T_1930 = and(_T_1929, _T_1924) @[el2_dec_dec_ctl.scala 17:17] + node _T_1931 = or(_T_1914, _T_1930) @[el2_dec_dec_ctl.scala 117:35] + node _T_1932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1934 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1935 = eq(_T_1934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1936 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1937 = eq(_T_1936, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1938 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1939 = eq(_T_1938, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1940 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1942 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1943 = eq(_T_1942, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1944 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1945 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1946 = and(_T_1933, _T_1935) @[el2_dec_dec_ctl.scala 17:17] + node _T_1947 = and(_T_1946, _T_1937) @[el2_dec_dec_ctl.scala 17:17] + node _T_1948 = and(_T_1947, _T_1939) @[el2_dec_dec_ctl.scala 17:17] + node _T_1949 = and(_T_1948, _T_1941) @[el2_dec_dec_ctl.scala 17:17] + node _T_1950 = and(_T_1949, _T_1943) @[el2_dec_dec_ctl.scala 17:17] + node _T_1951 = and(_T_1950, _T_1944) @[el2_dec_dec_ctl.scala 17:17] + node _T_1952 = and(_T_1951, _T_1945) @[el2_dec_dec_ctl.scala 17:17] + node _T_1953 = or(_T_1931, _T_1952) @[el2_dec_dec_ctl.scala 118:38] + node _T_1954 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1957 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1959 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1960 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1961 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1962 = and(_T_1955, _T_1956) @[el2_dec_dec_ctl.scala 17:17] + node _T_1963 = and(_T_1962, _T_1958) @[el2_dec_dec_ctl.scala 17:17] + node _T_1964 = and(_T_1963, _T_1959) @[el2_dec_dec_ctl.scala 17:17] + node _T_1965 = and(_T_1964, _T_1960) @[el2_dec_dec_ctl.scala 17:17] + node _T_1966 = and(_T_1965, _T_1961) @[el2_dec_dec_ctl.scala 17:17] + node _T_1967 = or(_T_1953, _T_1966) @[el2_dec_dec_ctl.scala 119:44] + io.out.legal <= _T_1967 @[el2_dec_dec_ctl.scala 101:16] extmodule gated_latch_662 : output Q : Clock @@ -66720,7 +66705,7 @@ circuit el2_swerv : module el2_dec_decode_ctl : input clock : Clock input reset : AsyncReset - output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[el2_dec_decode_ctl.scala 126:27] _T.bits.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] @@ -66771,11 +66756,11 @@ circuit el2_swerv : wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] - wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 136:17] - wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 137:17] - wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 138:17] - wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 139:20] - wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 140:17] + wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] + wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] + wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] + wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] + wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] @@ -66785,14 +66770,14 @@ circuit el2_swerv : i0_rs2_depth_d <= UInt<1>("h00") wire cam_wen : UInt<4> cam_wen <= UInt<1>("h00") - wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 147:17] + wire cam : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 147:17] wire cam_write : UInt<1> cam_write <= UInt<1>("h00") wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29] wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30] wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31] - wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 152:20] - wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 153:20] + wire cam_raw : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 152:20] + wire cam_in : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 153:20] wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18] wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22] wire i0_rs1bypass : UInt<3> @@ -66914,967 +66899,965 @@ circuit el2_swerv : node _T_15 = or(_T_13, _T_14) @[el2_dec_decode_ctl.scala 217:56] node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[el2_dec_decode_ctl.scala 219:32] node data_gate_en = or(_T_15, _T_16) @[el2_dec_decode_ctl.scala 218:56] - inst data_gated_cgc of rvclkhdr_661 @[el2_dec_decode_ctl.scala 222:29] - data_gated_cgc.clock <= clock - data_gated_cgc.reset <= reset - data_gated_cgc.io.en <= data_gate_en @[el2_dec_decode_ctl.scala 223:31] - data_gated_cgc.io.scan_mode <= io.scan_mode @[el2_dec_decode_ctl.scala 224:31] - data_gated_cgc.io.clk <= clock @[el2_dec_decode_ctl.scala 225:31] - node _T_17 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 230:62] - node i0_brp_valid = and(io.dec_i0_brp.valid, _T_17) @[el2_dec_decode_ctl.scala 230:60] - io.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 231:43] - io.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 232:43] - io.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 233:43] - io.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 234:43] - io.dec_i0_predict_p_d.bits.pja <= i0_pja @[el2_dec_decode_ctl.scala 235:43] - io.dec_i0_predict_p_d.bits.pret <= i0_pret @[el2_dec_decode_ctl.scala 236:43] - io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[el2_dec_decode_ctl.scala 237:43] - io.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 238:43] - io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[el2_dec_decode_ctl.scala 239:43] - node _T_18 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 240:55] - io.dec_i0_predict_p_d.valid <= _T_18 @[el2_dec_decode_ctl.scala 240:38] - node _T_19 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 241:75] - node _T_20 = or(_T_19, i0_pja_raw) @[el2_dec_decode_ctl.scala 241:90] - node _T_21 = or(_T_20, i0_pret_raw) @[el2_dec_decode_ctl.scala 241:103] - node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:56] - node i0_notbr_error = and(i0_brp_valid, _T_22) @[el2_dec_decode_ctl.scala 241:54] - node _T_23 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 244:72] - node _T_24 = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 244:47] - node _T_25 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 244:106] - node _T_26 = and(_T_24, _T_25) @[el2_dec_decode_ctl.scala 244:76] - node _T_27 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:126] - node i0_br_toffset_error = and(_T_26, _T_27) @[el2_dec_decode_ctl.scala 244:124] - node _T_28 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[el2_dec_decode_ctl.scala 245:47] - node _T_29 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 245:74] - node i0_ret_error = and(_T_28, _T_29) @[el2_dec_decode_ctl.scala 245:72] - node _T_30 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 246:62] - node _T_31 = or(_T_30, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 246:79] - node i0_br_error = or(_T_31, i0_ret_error) @[el2_dec_decode_ctl.scala 246:101] - node _T_32 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 247:72] - node _T_33 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:94] - node _T_34 = and(_T_32, _T_33) @[el2_dec_decode_ctl.scala 247:92] - io.dec_i0_predict_p_d.bits.br_error <= _T_34 @[el2_dec_decode_ctl.scala 247:56] - node _T_35 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 248:94] - node _T_36 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 248:116] - node _T_37 = and(_T_35, _T_36) @[el2_dec_decode_ctl.scala 248:114] - io.dec_i0_predict_p_d.bits.br_start_error <= _T_37 @[el2_dec_decode_ctl.scala 248:56] - io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 249:32] - io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 250:32] - node _T_38 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[el2_dec_decode_ctl.scala 251:47] - node _T_39 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 251:86] - node i0_br_error_all = and(_T_38, _T_39) @[el2_dec_decode_ctl.scala 251:84] - io.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 252:49] - io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 253:32] - io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[el2_dec_decode_ctl.scala 254:56] - node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 260:36] - i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 263:9] - i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 263:9] - i0_dp.fence_i <= i0_dp_raw.fence_i @[el2_dec_decode_ctl.scala 263:9] - i0_dp.fence <= i0_dp_raw.fence @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rem <= i0_dp_raw.rem @[el2_dec_decode_ctl.scala 263:9] - i0_dp.div <= i0_dp_raw.div @[el2_dec_decode_ctl.scala 263:9] - i0_dp.low <= i0_dp_raw.low @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[el2_dec_decode_ctl.scala 263:9] - i0_dp.mul <= i0_dp_raw.mul @[el2_dec_decode_ctl.scala 263:9] - i0_dp.mret <= i0_dp_raw.mret @[el2_dec_decode_ctl.scala 263:9] - i0_dp.ecall <= i0_dp_raw.ecall @[el2_dec_decode_ctl.scala 263:9] - i0_dp.ebreak <= i0_dp_raw.ebreak @[el2_dec_decode_ctl.scala 263:9] - i0_dp.postsync <= i0_dp_raw.postsync @[el2_dec_decode_ctl.scala 263:9] - i0_dp.presync <= i0_dp_raw.presync @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_imm <= i0_dp_raw.csr_imm @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_write <= i0_dp_raw.csr_write @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_set <= i0_dp_raw.csr_set @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_clr <= i0_dp_raw.csr_clr @[el2_dec_decode_ctl.scala 263:9] - i0_dp.csr_read <= i0_dp_raw.csr_read @[el2_dec_decode_ctl.scala 263:9] - i0_dp.word <= i0_dp_raw.word @[el2_dec_decode_ctl.scala 263:9] - i0_dp.half <= i0_dp_raw.half @[el2_dec_decode_ctl.scala 263:9] - i0_dp.by <= i0_dp_raw.by @[el2_dec_decode_ctl.scala 263:9] - i0_dp.jal <= i0_dp_raw.jal @[el2_dec_decode_ctl.scala 263:9] - i0_dp.blt <= i0_dp_raw.blt @[el2_dec_decode_ctl.scala 263:9] - i0_dp.bge <= i0_dp_raw.bge @[el2_dec_decode_ctl.scala 263:9] - i0_dp.bne <= i0_dp_raw.bne @[el2_dec_decode_ctl.scala 263:9] - i0_dp.beq <= i0_dp_raw.beq @[el2_dec_decode_ctl.scala 263:9] - i0_dp.condbr <= i0_dp_raw.condbr @[el2_dec_decode_ctl.scala 263:9] - i0_dp.unsign <= i0_dp_raw.unsign @[el2_dec_decode_ctl.scala 263:9] - i0_dp.slt <= i0_dp_raw.slt @[el2_dec_decode_ctl.scala 263:9] - i0_dp.srl <= i0_dp_raw.srl @[el2_dec_decode_ctl.scala 263:9] - i0_dp.sra <= i0_dp_raw.sra @[el2_dec_decode_ctl.scala 263:9] - i0_dp.sll <= i0_dp_raw.sll @[el2_dec_decode_ctl.scala 263:9] - i0_dp.lxor <= i0_dp_raw.lxor @[el2_dec_decode_ctl.scala 263:9] - i0_dp.lor <= i0_dp_raw.lor @[el2_dec_decode_ctl.scala 263:9] - i0_dp.land <= i0_dp_raw.land @[el2_dec_decode_ctl.scala 263:9] - i0_dp.sub <= i0_dp_raw.sub @[el2_dec_decode_ctl.scala 263:9] - i0_dp.add <= i0_dp_raw.add @[el2_dec_decode_ctl.scala 263:9] - i0_dp.lsu <= i0_dp_raw.lsu @[el2_dec_decode_ctl.scala 263:9] - i0_dp.store <= i0_dp_raw.store @[el2_dec_decode_ctl.scala 263:9] - i0_dp.load <= i0_dp_raw.load @[el2_dec_decode_ctl.scala 263:9] - i0_dp.pc <= i0_dp_raw.pc @[el2_dec_decode_ctl.scala 263:9] - i0_dp.imm20 <= i0_dp_raw.imm20 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.shimm5 <= i0_dp_raw.shimm5 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rd <= i0_dp_raw.rd @[el2_dec_decode_ctl.scala 263:9] - i0_dp.imm12 <= i0_dp_raw.imm12 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rs2 <= i0_dp_raw.rs2 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.rs1 <= i0_dp_raw.rs1 @[el2_dec_decode_ctl.scala 263:9] - i0_dp.alu <= i0_dp_raw.alu @[el2_dec_decode_ctl.scala 263:9] - node _T_40 = or(i0_br_error_all, i0_icaf_d) @[el2_dec_decode_ctl.scala 264:25] - node _T_41 = bits(_T_40, 0, 0) @[el2_dec_decode_ctl.scala 264:43] - when _T_41 : @[el2_dec_decode_ctl.scala 264:50] - wire _T_42 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 265:35] - _T_42.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.pm_alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.fence <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rem <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.div <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.mret <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.ecall <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.ebreak <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.postsync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.presync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_imm <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_write <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_set <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_clr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.csr_read <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.jal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.blt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.bge <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.bne <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.beq <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.condbr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.slt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.srl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.sra <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.sll <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.lxor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.lor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.land <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.sub <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.add <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.lsu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.pc <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.imm20 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.shimm5 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rd <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.imm12 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rs2 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.rs1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - _T_42.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] - i0_dp.legal <= _T_42.legal @[el2_dec_decode_ctl.scala 265:20] - i0_dp.pm_alu <= _T_42.pm_alu @[el2_dec_decode_ctl.scala 265:20] - i0_dp.fence_i <= _T_42.fence_i @[el2_dec_decode_ctl.scala 265:20] - i0_dp.fence <= _T_42.fence @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rem <= _T_42.rem @[el2_dec_decode_ctl.scala 265:20] - i0_dp.div <= _T_42.div @[el2_dec_decode_ctl.scala 265:20] - i0_dp.low <= _T_42.low @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rs2_sign <= _T_42.rs2_sign @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rs1_sign <= _T_42.rs1_sign @[el2_dec_decode_ctl.scala 265:20] - i0_dp.mul <= _T_42.mul @[el2_dec_decode_ctl.scala 265:20] - i0_dp.mret <= _T_42.mret @[el2_dec_decode_ctl.scala 265:20] - i0_dp.ecall <= _T_42.ecall @[el2_dec_decode_ctl.scala 265:20] - i0_dp.ebreak <= _T_42.ebreak @[el2_dec_decode_ctl.scala 265:20] - i0_dp.postsync <= _T_42.postsync @[el2_dec_decode_ctl.scala 265:20] - i0_dp.presync <= _T_42.presync @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_imm <= _T_42.csr_imm @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_write <= _T_42.csr_write @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_set <= _T_42.csr_set @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_clr <= _T_42.csr_clr @[el2_dec_decode_ctl.scala 265:20] - i0_dp.csr_read <= _T_42.csr_read @[el2_dec_decode_ctl.scala 265:20] - i0_dp.word <= _T_42.word @[el2_dec_decode_ctl.scala 265:20] - i0_dp.half <= _T_42.half @[el2_dec_decode_ctl.scala 265:20] - i0_dp.by <= _T_42.by @[el2_dec_decode_ctl.scala 265:20] - i0_dp.jal <= _T_42.jal @[el2_dec_decode_ctl.scala 265:20] - i0_dp.blt <= _T_42.blt @[el2_dec_decode_ctl.scala 265:20] - i0_dp.bge <= _T_42.bge @[el2_dec_decode_ctl.scala 265:20] - i0_dp.bne <= _T_42.bne @[el2_dec_decode_ctl.scala 265:20] - i0_dp.beq <= _T_42.beq @[el2_dec_decode_ctl.scala 265:20] - i0_dp.condbr <= _T_42.condbr @[el2_dec_decode_ctl.scala 265:20] - i0_dp.unsign <= _T_42.unsign @[el2_dec_decode_ctl.scala 265:20] - i0_dp.slt <= _T_42.slt @[el2_dec_decode_ctl.scala 265:20] - i0_dp.srl <= _T_42.srl @[el2_dec_decode_ctl.scala 265:20] - i0_dp.sra <= _T_42.sra @[el2_dec_decode_ctl.scala 265:20] - i0_dp.sll <= _T_42.sll @[el2_dec_decode_ctl.scala 265:20] - i0_dp.lxor <= _T_42.lxor @[el2_dec_decode_ctl.scala 265:20] - i0_dp.lor <= _T_42.lor @[el2_dec_decode_ctl.scala 265:20] - i0_dp.land <= _T_42.land @[el2_dec_decode_ctl.scala 265:20] - i0_dp.sub <= _T_42.sub @[el2_dec_decode_ctl.scala 265:20] - i0_dp.add <= _T_42.add @[el2_dec_decode_ctl.scala 265:20] - i0_dp.lsu <= _T_42.lsu @[el2_dec_decode_ctl.scala 265:20] - i0_dp.store <= _T_42.store @[el2_dec_decode_ctl.scala 265:20] - i0_dp.load <= _T_42.load @[el2_dec_decode_ctl.scala 265:20] - i0_dp.pc <= _T_42.pc @[el2_dec_decode_ctl.scala 265:20] - i0_dp.imm20 <= _T_42.imm20 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.shimm5 <= _T_42.shimm5 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rd <= _T_42.rd @[el2_dec_decode_ctl.scala 265:20] - i0_dp.imm12 <= _T_42.imm12 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rs2 <= _T_42.rs2 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.rs1 <= _T_42.rs1 @[el2_dec_decode_ctl.scala 265:20] - i0_dp.alu <= _T_42.alu @[el2_dec_decode_ctl.scala 265:20] - i0_dp.alu <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 266:20] - i0_dp.rs1 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 267:20] - i0_dp.rs2 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 268:20] - i0_dp.lor <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 269:20] - i0_dp.legal <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 270:20] - i0_dp.postsync <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 271:20] - skip @[el2_dec_decode_ctl.scala 264:50] - io.dec_i0_select_pc_d <= i0_dp.pc @[el2_dec_decode_ctl.scala 275:25] - node _T_43 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 278:38] - node _T_44 = or(_T_43, i0_pja) @[el2_dec_decode_ctl.scala 278:49] - node i0_predict_br = or(_T_44, i0_pret) @[el2_dec_decode_ctl.scala 278:58] - node _T_45 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 280:51] - node _T_46 = and(_T_45, i0_brp_valid) @[el2_dec_decode_ctl.scala 280:55] - node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 280:26] - node i0_predict_nt = and(_T_47, i0_predict_br) @[el2_dec_decode_ctl.scala 280:71] - node _T_48 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 281:51] - node _T_49 = and(_T_48, i0_brp_valid) @[el2_dec_decode_ctl.scala 281:55] - node i0_predict_t = and(_T_49, i0_predict_br) @[el2_dec_decode_ctl.scala 281:71] - node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 282:20] - io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 284:26] - io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 285:26] - io.i0_ap.add <= i0_dp.add @[el2_dec_decode_ctl.scala 287:20] - io.i0_ap.sub <= i0_dp.sub @[el2_dec_decode_ctl.scala 288:20] - io.i0_ap.land <= i0_dp.land @[el2_dec_decode_ctl.scala 289:20] - io.i0_ap.lor <= i0_dp.lor @[el2_dec_decode_ctl.scala 290:20] - io.i0_ap.lxor <= i0_dp.lxor @[el2_dec_decode_ctl.scala 291:20] - io.i0_ap.sll <= i0_dp.sll @[el2_dec_decode_ctl.scala 292:20] - io.i0_ap.srl <= i0_dp.srl @[el2_dec_decode_ctl.scala 293:20] - io.i0_ap.sra <= i0_dp.sra @[el2_dec_decode_ctl.scala 294:20] - io.i0_ap.slt <= i0_dp.slt @[el2_dec_decode_ctl.scala 295:20] - io.i0_ap.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 296:20] - io.i0_ap.beq <= i0_dp.beq @[el2_dec_decode_ctl.scala 297:20] - io.i0_ap.bne <= i0_dp.bne @[el2_dec_decode_ctl.scala 298:20] - io.i0_ap.blt <= i0_dp.blt @[el2_dec_decode_ctl.scala 299:20] - io.i0_ap.bge <= i0_dp.bge @[el2_dec_decode_ctl.scala 300:20] - io.i0_ap.csr_write <= i0_csr_write_only_d @[el2_dec_decode_ctl.scala 301:22] - io.i0_ap.csr_imm <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 302:22] - io.i0_ap.jal <= i0_jal @[el2_dec_decode_ctl.scala 303:22] - node _T_50 = eq(cam[0].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] - node _T_51 = bits(_T_50, 0, 0) @[el2_dec_decode_ctl.scala 307:137] - node _T_52 = shl(cam_write, 0) @[el2_dec_decode_ctl.scala 307:158] - node _T_53 = eq(cam[1].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] - node _T_54 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_55 = bits(_T_53, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_56 = and(_T_54, _T_55) @[el2_dec_decode_ctl.scala 307:126] - node _T_57 = bits(_T_56, 0, 0) @[el2_dec_decode_ctl.scala 307:137] - node _T_58 = shl(cam_write, 1) @[el2_dec_decode_ctl.scala 307:158] - node _T_59 = eq(cam[2].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] - node _T_60 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_61 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_62 = and(_T_60, _T_61) @[el2_dec_decode_ctl.scala 307:126] - node _T_63 = bits(_T_62, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_64 = bits(_T_59, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_65 = and(_T_63, _T_64) @[el2_dec_decode_ctl.scala 307:126] - node _T_66 = bits(_T_65, 0, 0) @[el2_dec_decode_ctl.scala 307:137] - node _T_67 = shl(cam_write, 2) @[el2_dec_decode_ctl.scala 307:158] - node _T_68 = eq(cam[3].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] - node _T_69 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_70 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_71 = and(_T_69, _T_70) @[el2_dec_decode_ctl.scala 307:126] - node _T_72 = bits(_T_71, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_73 = bits(cam[2].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_74 = and(_T_72, _T_73) @[el2_dec_decode_ctl.scala 307:126] - node _T_75 = bits(_T_74, 0, 0) @[el2_dec_decode_ctl.scala 307:120] - node _T_76 = bits(_T_68, 0, 0) @[el2_dec_decode_ctl.scala 307:129] - node _T_77 = and(_T_75, _T_76) @[el2_dec_decode_ctl.scala 307:126] - node _T_78 = bits(_T_77, 0, 0) @[el2_dec_decode_ctl.scala 307:137] - node _T_79 = shl(cam_write, 3) @[el2_dec_decode_ctl.scala 307:158] - node _T_80 = mux(_T_51, _T_52, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_81 = mux(_T_57, _T_58, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_82 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_83 = mux(_T_78, _T_79, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_84 = or(_T_80, _T_81) @[Mux.scala 27:72] - node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] + node _T_17 = bits(data_gate_en, 0, 0) @[el2_dec_decode_ctl.scala 222:56] + inst rvclkhdr of rvclkhdr_661 @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= _T_17 @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 226:62] + node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[el2_dec_decode_ctl.scala 226:60] + io.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 227:43] + io.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 228:43] + io.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 229:43] + io.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 230:43] + io.dec_i0_predict_p_d.bits.pja <= i0_pja @[el2_dec_decode_ctl.scala 231:43] + io.dec_i0_predict_p_d.bits.pret <= i0_pret @[el2_dec_decode_ctl.scala 232:43] + io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.prett @[el2_dec_decode_ctl.scala 233:43] + io.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 234:43] + io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.hist @[el2_dec_decode_ctl.scala 235:43] + node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 236:55] + io.dec_i0_predict_p_d.valid <= _T_19 @[el2_dec_decode_ctl.scala 236:38] + node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 237:75] + node _T_21 = or(_T_20, i0_pja_raw) @[el2_dec_decode_ctl.scala 237:90] + node _T_22 = or(_T_21, i0_pret_raw) @[el2_dec_decode_ctl.scala 237:103] + node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 237:56] + node i0_notbr_error = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 237:54] + node _T_24 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:67] + node _T_25 = and(i0_brp_valid, _T_24) @[el2_dec_decode_ctl.scala 240:47] + node _T_26 = neq(io.dec_i0_brp.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:96] + node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:71] + node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:116] + node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:114] + node _T_29 = and(i0_brp_valid, io.dec_i0_brp.ret) @[el2_dec_decode_ctl.scala 241:47] + node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:69] + node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:67] + node _T_31 = or(io.dec_i0_brp.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:57] + node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:74] + node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:96] + node _T_33 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 243:72] + node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 243:94] + node _T_35 = and(_T_33, _T_34) @[el2_dec_decode_ctl.scala 243:92] + io.dec_i0_predict_p_d.bits.br_error <= _T_35 @[el2_dec_decode_ctl.scala 243:56] + node _T_36 = and(io.dec_i0_brp.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:89] + node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:111] + node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:109] + io.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[el2_dec_decode_ctl.scala 244:56] + io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 245:32] + io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 246:32] + node _T_39 = or(i0_br_error, io.dec_i0_brp.br_start_error) @[el2_dec_decode_ctl.scala 247:47] + node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:81] + node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:79] + io.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 248:49] + io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 249:32] + io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.way @[el2_dec_decode_ctl.scala 250:56] + node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 256:36] + i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 259:9] + i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 259:9] + i0_dp.fence_i <= i0_dp_raw.fence_i @[el2_dec_decode_ctl.scala 259:9] + i0_dp.fence <= i0_dp_raw.fence @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rem <= i0_dp_raw.rem @[el2_dec_decode_ctl.scala 259:9] + i0_dp.div <= i0_dp_raw.div @[el2_dec_decode_ctl.scala 259:9] + i0_dp.low <= i0_dp_raw.low @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[el2_dec_decode_ctl.scala 259:9] + i0_dp.mul <= i0_dp_raw.mul @[el2_dec_decode_ctl.scala 259:9] + i0_dp.mret <= i0_dp_raw.mret @[el2_dec_decode_ctl.scala 259:9] + i0_dp.ecall <= i0_dp_raw.ecall @[el2_dec_decode_ctl.scala 259:9] + i0_dp.ebreak <= i0_dp_raw.ebreak @[el2_dec_decode_ctl.scala 259:9] + i0_dp.postsync <= i0_dp_raw.postsync @[el2_dec_decode_ctl.scala 259:9] + i0_dp.presync <= i0_dp_raw.presync @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_imm <= i0_dp_raw.csr_imm @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_write <= i0_dp_raw.csr_write @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_set <= i0_dp_raw.csr_set @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_clr <= i0_dp_raw.csr_clr @[el2_dec_decode_ctl.scala 259:9] + i0_dp.csr_read <= i0_dp_raw.csr_read @[el2_dec_decode_ctl.scala 259:9] + i0_dp.word <= i0_dp_raw.word @[el2_dec_decode_ctl.scala 259:9] + i0_dp.half <= i0_dp_raw.half @[el2_dec_decode_ctl.scala 259:9] + i0_dp.by <= i0_dp_raw.by @[el2_dec_decode_ctl.scala 259:9] + i0_dp.jal <= i0_dp_raw.jal @[el2_dec_decode_ctl.scala 259:9] + i0_dp.blt <= i0_dp_raw.blt @[el2_dec_decode_ctl.scala 259:9] + i0_dp.bge <= i0_dp_raw.bge @[el2_dec_decode_ctl.scala 259:9] + i0_dp.bne <= i0_dp_raw.bne @[el2_dec_decode_ctl.scala 259:9] + i0_dp.beq <= i0_dp_raw.beq @[el2_dec_decode_ctl.scala 259:9] + i0_dp.condbr <= i0_dp_raw.condbr @[el2_dec_decode_ctl.scala 259:9] + i0_dp.unsign <= i0_dp_raw.unsign @[el2_dec_decode_ctl.scala 259:9] + i0_dp.slt <= i0_dp_raw.slt @[el2_dec_decode_ctl.scala 259:9] + i0_dp.srl <= i0_dp_raw.srl @[el2_dec_decode_ctl.scala 259:9] + i0_dp.sra <= i0_dp_raw.sra @[el2_dec_decode_ctl.scala 259:9] + i0_dp.sll <= i0_dp_raw.sll @[el2_dec_decode_ctl.scala 259:9] + i0_dp.lxor <= i0_dp_raw.lxor @[el2_dec_decode_ctl.scala 259:9] + i0_dp.lor <= i0_dp_raw.lor @[el2_dec_decode_ctl.scala 259:9] + i0_dp.land <= i0_dp_raw.land @[el2_dec_decode_ctl.scala 259:9] + i0_dp.sub <= i0_dp_raw.sub @[el2_dec_decode_ctl.scala 259:9] + i0_dp.add <= i0_dp_raw.add @[el2_dec_decode_ctl.scala 259:9] + i0_dp.lsu <= i0_dp_raw.lsu @[el2_dec_decode_ctl.scala 259:9] + i0_dp.store <= i0_dp_raw.store @[el2_dec_decode_ctl.scala 259:9] + i0_dp.load <= i0_dp_raw.load @[el2_dec_decode_ctl.scala 259:9] + i0_dp.pc <= i0_dp_raw.pc @[el2_dec_decode_ctl.scala 259:9] + i0_dp.imm20 <= i0_dp_raw.imm20 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.shimm5 <= i0_dp_raw.shimm5 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rd <= i0_dp_raw.rd @[el2_dec_decode_ctl.scala 259:9] + i0_dp.imm12 <= i0_dp_raw.imm12 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rs2 <= i0_dp_raw.rs2 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.rs1 <= i0_dp_raw.rs1 @[el2_dec_decode_ctl.scala 259:9] + i0_dp.alu <= i0_dp_raw.alu @[el2_dec_decode_ctl.scala 259:9] + node _T_41 = or(i0_br_error_all, i0_icaf_d) @[el2_dec_decode_ctl.scala 260:25] + node _T_42 = bits(_T_41, 0, 0) @[el2_dec_decode_ctl.scala 260:43] + when _T_42 : @[el2_dec_decode_ctl.scala 260:50] + wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 261:35] + _T_43.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.pm_alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.fence <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rem <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.div <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.mret <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.ecall <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.ebreak <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.postsync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.presync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_imm <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_write <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_set <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_clr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.csr_read <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.jal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.blt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.bge <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.bne <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.beq <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.condbr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.slt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.srl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.sra <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.sll <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.lxor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.lor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.land <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.sub <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.add <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.lsu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.pc <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.imm20 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.shimm5 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rd <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.imm12 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rs2 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.rs1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + _T_43.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 261:35] + i0_dp.legal <= _T_43.legal @[el2_dec_decode_ctl.scala 261:20] + i0_dp.pm_alu <= _T_43.pm_alu @[el2_dec_decode_ctl.scala 261:20] + i0_dp.fence_i <= _T_43.fence_i @[el2_dec_decode_ctl.scala 261:20] + i0_dp.fence <= _T_43.fence @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rem <= _T_43.rem @[el2_dec_decode_ctl.scala 261:20] + i0_dp.div <= _T_43.div @[el2_dec_decode_ctl.scala 261:20] + i0_dp.low <= _T_43.low @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rs2_sign <= _T_43.rs2_sign @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rs1_sign <= _T_43.rs1_sign @[el2_dec_decode_ctl.scala 261:20] + i0_dp.mul <= _T_43.mul @[el2_dec_decode_ctl.scala 261:20] + i0_dp.mret <= _T_43.mret @[el2_dec_decode_ctl.scala 261:20] + i0_dp.ecall <= _T_43.ecall @[el2_dec_decode_ctl.scala 261:20] + i0_dp.ebreak <= _T_43.ebreak @[el2_dec_decode_ctl.scala 261:20] + i0_dp.postsync <= _T_43.postsync @[el2_dec_decode_ctl.scala 261:20] + i0_dp.presync <= _T_43.presync @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_imm <= _T_43.csr_imm @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_write <= _T_43.csr_write @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_set <= _T_43.csr_set @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_clr <= _T_43.csr_clr @[el2_dec_decode_ctl.scala 261:20] + i0_dp.csr_read <= _T_43.csr_read @[el2_dec_decode_ctl.scala 261:20] + i0_dp.word <= _T_43.word @[el2_dec_decode_ctl.scala 261:20] + i0_dp.half <= _T_43.half @[el2_dec_decode_ctl.scala 261:20] + i0_dp.by <= _T_43.by @[el2_dec_decode_ctl.scala 261:20] + i0_dp.jal <= _T_43.jal @[el2_dec_decode_ctl.scala 261:20] + i0_dp.blt <= _T_43.blt @[el2_dec_decode_ctl.scala 261:20] + i0_dp.bge <= _T_43.bge @[el2_dec_decode_ctl.scala 261:20] + i0_dp.bne <= _T_43.bne @[el2_dec_decode_ctl.scala 261:20] + i0_dp.beq <= _T_43.beq @[el2_dec_decode_ctl.scala 261:20] + i0_dp.condbr <= _T_43.condbr @[el2_dec_decode_ctl.scala 261:20] + i0_dp.unsign <= _T_43.unsign @[el2_dec_decode_ctl.scala 261:20] + i0_dp.slt <= _T_43.slt @[el2_dec_decode_ctl.scala 261:20] + i0_dp.srl <= _T_43.srl @[el2_dec_decode_ctl.scala 261:20] + i0_dp.sra <= _T_43.sra @[el2_dec_decode_ctl.scala 261:20] + i0_dp.sll <= _T_43.sll @[el2_dec_decode_ctl.scala 261:20] + i0_dp.lxor <= _T_43.lxor @[el2_dec_decode_ctl.scala 261:20] + i0_dp.lor <= _T_43.lor @[el2_dec_decode_ctl.scala 261:20] + i0_dp.land <= _T_43.land @[el2_dec_decode_ctl.scala 261:20] + i0_dp.sub <= _T_43.sub @[el2_dec_decode_ctl.scala 261:20] + i0_dp.add <= _T_43.add @[el2_dec_decode_ctl.scala 261:20] + i0_dp.lsu <= _T_43.lsu @[el2_dec_decode_ctl.scala 261:20] + i0_dp.store <= _T_43.store @[el2_dec_decode_ctl.scala 261:20] + i0_dp.load <= _T_43.load @[el2_dec_decode_ctl.scala 261:20] + i0_dp.pc <= _T_43.pc @[el2_dec_decode_ctl.scala 261:20] + i0_dp.imm20 <= _T_43.imm20 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.shimm5 <= _T_43.shimm5 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rd <= _T_43.rd @[el2_dec_decode_ctl.scala 261:20] + i0_dp.imm12 <= _T_43.imm12 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rs2 <= _T_43.rs2 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.rs1 <= _T_43.rs1 @[el2_dec_decode_ctl.scala 261:20] + i0_dp.alu <= _T_43.alu @[el2_dec_decode_ctl.scala 261:20] + i0_dp.alu <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 262:20] + i0_dp.rs1 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 263:20] + i0_dp.rs2 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 264:20] + i0_dp.lor <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 265:20] + i0_dp.legal <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 266:20] + i0_dp.postsync <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 267:20] + skip @[el2_dec_decode_ctl.scala 260:50] + io.dec_i0_select_pc_d <= i0_dp.pc @[el2_dec_decode_ctl.scala 271:25] + node _T_44 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 274:38] + node _T_45 = or(_T_44, i0_pja) @[el2_dec_decode_ctl.scala 274:49] + node i0_predict_br = or(_T_45, i0_pret) @[el2_dec_decode_ctl.scala 274:58] + node _T_46 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:46] + node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:50] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 276:26] + node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:66] + node _T_49 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:46] + node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:50] + node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:66] + node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 278:20] + io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 280:26] + io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 281:26] + io.i0_ap.add <= i0_dp.add @[el2_dec_decode_ctl.scala 283:20] + io.i0_ap.sub <= i0_dp.sub @[el2_dec_decode_ctl.scala 284:20] + io.i0_ap.land <= i0_dp.land @[el2_dec_decode_ctl.scala 285:20] + io.i0_ap.lor <= i0_dp.lor @[el2_dec_decode_ctl.scala 286:20] + io.i0_ap.lxor <= i0_dp.lxor @[el2_dec_decode_ctl.scala 287:20] + io.i0_ap.sll <= i0_dp.sll @[el2_dec_decode_ctl.scala 288:20] + io.i0_ap.srl <= i0_dp.srl @[el2_dec_decode_ctl.scala 289:20] + io.i0_ap.sra <= i0_dp.sra @[el2_dec_decode_ctl.scala 290:20] + io.i0_ap.slt <= i0_dp.slt @[el2_dec_decode_ctl.scala 291:20] + io.i0_ap.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 292:20] + io.i0_ap.beq <= i0_dp.beq @[el2_dec_decode_ctl.scala 293:20] + io.i0_ap.bne <= i0_dp.bne @[el2_dec_decode_ctl.scala 294:20] + io.i0_ap.blt <= i0_dp.blt @[el2_dec_decode_ctl.scala 295:20] + io.i0_ap.bge <= i0_dp.bge @[el2_dec_decode_ctl.scala 296:20] + io.i0_ap.csr_write <= i0_csr_write_only_d @[el2_dec_decode_ctl.scala 297:22] + io.i0_ap.csr_imm <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 298:22] + io.i0_ap.jal <= i0_jal @[el2_dec_decode_ctl.scala 299:22] + node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78] + node _T_52 = bits(_T_51, 0, 0) @[el2_dec_decode_ctl.scala 303:137] + node _T_53 = shl(cam_write, 0) @[el2_dec_decode_ctl.scala 303:158] + node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78] + node _T_55 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_56 = bits(_T_54, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_57 = and(_T_55, _T_56) @[el2_dec_decode_ctl.scala 303:126] + node _T_58 = bits(_T_57, 0, 0) @[el2_dec_decode_ctl.scala 303:137] + node _T_59 = shl(cam_write, 1) @[el2_dec_decode_ctl.scala 303:158] + node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78] + node _T_61 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_62 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_63 = and(_T_61, _T_62) @[el2_dec_decode_ctl.scala 303:126] + node _T_64 = bits(_T_63, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_65 = bits(_T_60, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_66 = and(_T_64, _T_65) @[el2_dec_decode_ctl.scala 303:126] + node _T_67 = bits(_T_66, 0, 0) @[el2_dec_decode_ctl.scala 303:137] + node _T_68 = shl(cam_write, 2) @[el2_dec_decode_ctl.scala 303:158] + node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 303:78] + node _T_70 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_71 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_72 = and(_T_70, _T_71) @[el2_dec_decode_ctl.scala 303:126] + node _T_73 = bits(_T_72, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_74 = bits(cam[2].valid, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_75 = and(_T_73, _T_74) @[el2_dec_decode_ctl.scala 303:126] + node _T_76 = bits(_T_75, 0, 0) @[el2_dec_decode_ctl.scala 303:120] + node _T_77 = bits(_T_69, 0, 0) @[el2_dec_decode_ctl.scala 303:129] + node _T_78 = and(_T_76, _T_77) @[el2_dec_decode_ctl.scala 303:126] + node _T_79 = bits(_T_78, 0, 0) @[el2_dec_decode_ctl.scala 303:137] + node _T_80 = shl(cam_write, 3) @[el2_dec_decode_ctl.scala 303:158] + node _T_81 = mux(_T_52, _T_53, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_82 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_83 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_84 = mux(_T_79, _T_80, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_85 = or(_T_81, _T_82) @[Mux.scala 27:72] node _T_86 = or(_T_85, _T_83) @[Mux.scala 27:72] - wire _T_87 : UInt<4> @[Mux.scala 27:72] - _T_87 <= _T_86 @[Mux.scala 27:72] - cam_wen <= _T_87 @[el2_dec_decode_ctl.scala 307:11] - cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 309:25] - node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 310:54] - node cam_inv_reset_tag = bits(io.lsu_nonblock_load_inv_tag_r, 1, 0) @[el2_dec_decode_ctl.scala 313:59] - node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 315:63] - node cam_data_reset_tag = bits(io.lsu_nonblock_load_data_tag, 1, 0) @[el2_dec_decode_ctl.scala 316:60] - node _T_88 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 318:48] - node nonblock_load_rd = mux(_T_88, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 318:31] - node _T_89 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 322:116] + node _T_87 = or(_T_86, _T_84) @[Mux.scala 27:72] + wire _T_88 : UInt<4> @[Mux.scala 27:72] + _T_88 <= _T_87 @[Mux.scala 27:72] + cam_wen <= _T_88 @[el2_dec_decode_ctl.scala 303:11] + cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25] + node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54] + node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63] + node _T_89 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:43] + node nonblock_load_rd = mux(_T_89, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] + node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_89 : @[Reg.scala 28:19] + when _T_90 : @[Reg.scala 28:19] nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 323:56] - node _T_90 = eq(cam_inv_reset_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 325:66] - node _T_91 = and(io.lsu_nonblock_load_inv_r, _T_90) @[el2_dec_decode_ctl.scala 325:45] - node _T_92 = and(_T_91, cam[0].valid) @[el2_dec_decode_ctl.scala 325:87] - cam_inv_reset_val[0] <= _T_92 @[el2_dec_decode_ctl.scala 325:26] - node _T_93 = eq(cam_data_reset_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 326:67] - node _T_94 = and(cam_data_reset, _T_93) @[el2_dec_decode_ctl.scala 326:45] - node _T_95 = and(_T_94, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 326:88] - cam_data_reset_val[0] <= _T_95 @[el2_dec_decode_ctl.scala 326:27] - wire _T_96 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 327:28] - _T_96.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_96.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_96.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_96.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - cam_in[0].bits.rd <= _T_96.bits.rd @[el2_dec_decode_ctl.scala 327:14] - cam_in[0].bits.tag <= _T_96.bits.tag @[el2_dec_decode_ctl.scala 327:14] - cam_in[0].bits.wb <= _T_96.bits.wb @[el2_dec_decode_ctl.scala 327:14] - cam_in[0].valid <= _T_96.valid @[el2_dec_decode_ctl.scala 327:14] - cam[0].bits.rd <= cam_raw[0].bits.rd @[el2_dec_decode_ctl.scala 328:11] - cam[0].bits.tag <= cam_raw[0].bits.tag @[el2_dec_decode_ctl.scala 328:11] - cam[0].bits.wb <= cam_raw[0].bits.wb @[el2_dec_decode_ctl.scala 328:11] - cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 328:11] - node _T_97 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 330:32] - when _T_97 : @[el2_dec_decode_ctl.scala 330:39] - cam[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] - skip @[el2_dec_decode_ctl.scala 330:39] - node _T_98 = bits(cam_wen, 0, 0) @[el2_dec_decode_ctl.scala 333:17] - node _T_99 = bits(_T_98, 0, 0) @[el2_dec_decode_ctl.scala 333:21] - when _T_99 : @[el2_dec_decode_ctl.scala 333:28] - cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] - cam_in[0].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:32] - cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:32] - cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:32] - skip @[el2_dec_decode_ctl.scala 333:28] - else : @[el2_dec_decode_ctl.scala 338:131] - node _T_100 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 338:37] - node _T_101 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] - node _T_102 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 338:85] - node _T_103 = and(_T_101, _T_102) @[el2_dec_decode_ctl.scala 338:64] - node _T_104 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 338:123] - node _T_105 = and(_T_103, _T_104) @[el2_dec_decode_ctl.scala 338:105] - node _T_106 = or(_T_100, _T_105) @[el2_dec_decode_ctl.scala 338:44] - when _T_106 : @[el2_dec_decode_ctl.scala 338:131] - cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] - skip @[el2_dec_decode_ctl.scala 338:131] - else : @[el2_dec_decode_ctl.scala 340:16] - cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 341:22] - cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 341:22] - cam_in[0].bits.wb <= cam[0].bits.wb @[el2_dec_decode_ctl.scala 341:22] - cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 341:22] - skip @[el2_dec_decode_ctl.scala 340:16] - node _T_107 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] - node _T_108 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 343:79] - node _T_109 = and(_T_107, _T_108) @[el2_dec_decode_ctl.scala 343:44] - node _T_110 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:115] - node _T_111 = and(_T_109, _T_110) @[el2_dec_decode_ctl.scala 343:100] - when _T_111 : @[el2_dec_decode_ctl.scala 343:122] - cam_in[0].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:25] - skip @[el2_dec_decode_ctl.scala 343:122] - when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] - cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] - skip @[el2_dec_decode_ctl.scala 347:32] - wire _T_112 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 351:70] - _T_112.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_112.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_112.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_112.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - reg _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_112)) @[el2_dec_decode_ctl.scala 351:47] - _T_113.bits.rd <= cam_in[0].bits.rd @[el2_dec_decode_ctl.scala 351:47] - _T_113.bits.tag <= cam_in[0].bits.tag @[el2_dec_decode_ctl.scala 351:47] - _T_113.bits.wb <= cam_in[0].bits.wb @[el2_dec_decode_ctl.scala 351:47] - _T_113.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 351:47] - cam_raw[0].bits.rd <= _T_113.bits.rd @[el2_dec_decode_ctl.scala 351:15] - cam_raw[0].bits.tag <= _T_113.bits.tag @[el2_dec_decode_ctl.scala 351:15] - cam_raw[0].bits.wb <= _T_113.bits.wb @[el2_dec_decode_ctl.scala 351:15] - cam_raw[0].valid <= _T_113.valid @[el2_dec_decode_ctl.scala 351:15] - node _T_114 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[el2_dec_decode_ctl.scala 352:46] - node _T_115 = and(_T_114, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 352:71] - nonblock_load_write[0] <= _T_115 @[el2_dec_decode_ctl.scala 352:28] - node _T_116 = eq(cam_inv_reset_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 325:66] - node _T_117 = and(io.lsu_nonblock_load_inv_r, _T_116) @[el2_dec_decode_ctl.scala 325:45] - node _T_118 = and(_T_117, cam[1].valid) @[el2_dec_decode_ctl.scala 325:87] - cam_inv_reset_val[1] <= _T_118 @[el2_dec_decode_ctl.scala 325:26] - node _T_119 = eq(cam_data_reset_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 326:67] - node _T_120 = and(cam_data_reset, _T_119) @[el2_dec_decode_ctl.scala 326:45] - node _T_121 = and(_T_120, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 326:88] - cam_data_reset_val[1] <= _T_121 @[el2_dec_decode_ctl.scala 326:27] - wire _T_122 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 327:28] - _T_122.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_122.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_122.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_122.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - cam_in[1].bits.rd <= _T_122.bits.rd @[el2_dec_decode_ctl.scala 327:14] - cam_in[1].bits.tag <= _T_122.bits.tag @[el2_dec_decode_ctl.scala 327:14] - cam_in[1].bits.wb <= _T_122.bits.wb @[el2_dec_decode_ctl.scala 327:14] - cam_in[1].valid <= _T_122.valid @[el2_dec_decode_ctl.scala 327:14] - cam[1].bits.rd <= cam_raw[1].bits.rd @[el2_dec_decode_ctl.scala 328:11] - cam[1].bits.tag <= cam_raw[1].bits.tag @[el2_dec_decode_ctl.scala 328:11] - cam[1].bits.wb <= cam_raw[1].bits.wb @[el2_dec_decode_ctl.scala 328:11] - cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 328:11] - node _T_123 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 330:32] - when _T_123 : @[el2_dec_decode_ctl.scala 330:39] - cam[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] - skip @[el2_dec_decode_ctl.scala 330:39] - node _T_124 = bits(cam_wen, 1, 1) @[el2_dec_decode_ctl.scala 333:17] - node _T_125 = bits(_T_124, 0, 0) @[el2_dec_decode_ctl.scala 333:21] - when _T_125 : @[el2_dec_decode_ctl.scala 333:28] - cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] - cam_in[1].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:32] - cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:32] - cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:32] - skip @[el2_dec_decode_ctl.scala 333:28] - else : @[el2_dec_decode_ctl.scala 338:131] - node _T_126 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 338:37] - node _T_127 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] - node _T_128 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 338:85] - node _T_129 = and(_T_127, _T_128) @[el2_dec_decode_ctl.scala 338:64] - node _T_130 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 338:123] - node _T_131 = and(_T_129, _T_130) @[el2_dec_decode_ctl.scala 338:105] - node _T_132 = or(_T_126, _T_131) @[el2_dec_decode_ctl.scala 338:44] - when _T_132 : @[el2_dec_decode_ctl.scala 338:131] - cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] - skip @[el2_dec_decode_ctl.scala 338:131] - else : @[el2_dec_decode_ctl.scala 340:16] - cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 341:22] - cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 341:22] - cam_in[1].bits.wb <= cam[1].bits.wb @[el2_dec_decode_ctl.scala 341:22] - cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 341:22] - skip @[el2_dec_decode_ctl.scala 340:16] - node _T_133 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] - node _T_134 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 343:79] - node _T_135 = and(_T_133, _T_134) @[el2_dec_decode_ctl.scala 343:44] - node _T_136 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:115] - node _T_137 = and(_T_135, _T_136) @[el2_dec_decode_ctl.scala 343:100] - when _T_137 : @[el2_dec_decode_ctl.scala 343:122] - cam_in[1].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:25] - skip @[el2_dec_decode_ctl.scala 343:122] - when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] - cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] - skip @[el2_dec_decode_ctl.scala 347:32] - wire _T_138 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 351:70] - _T_138.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_138.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_138.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_138.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - reg _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_138)) @[el2_dec_decode_ctl.scala 351:47] - _T_139.bits.rd <= cam_in[1].bits.rd @[el2_dec_decode_ctl.scala 351:47] - _T_139.bits.tag <= cam_in[1].bits.tag @[el2_dec_decode_ctl.scala 351:47] - _T_139.bits.wb <= cam_in[1].bits.wb @[el2_dec_decode_ctl.scala 351:47] - _T_139.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 351:47] - cam_raw[1].bits.rd <= _T_139.bits.rd @[el2_dec_decode_ctl.scala 351:15] - cam_raw[1].bits.tag <= _T_139.bits.tag @[el2_dec_decode_ctl.scala 351:15] - cam_raw[1].bits.wb <= _T_139.bits.wb @[el2_dec_decode_ctl.scala 351:15] - cam_raw[1].valid <= _T_139.valid @[el2_dec_decode_ctl.scala 351:15] - node _T_140 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[el2_dec_decode_ctl.scala 352:46] - node _T_141 = and(_T_140, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 352:71] - nonblock_load_write[1] <= _T_141 @[el2_dec_decode_ctl.scala 352:28] - node _T_142 = eq(cam_inv_reset_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 325:66] - node _T_143 = and(io.lsu_nonblock_load_inv_r, _T_142) @[el2_dec_decode_ctl.scala 325:45] - node _T_144 = and(_T_143, cam[2].valid) @[el2_dec_decode_ctl.scala 325:87] - cam_inv_reset_val[2] <= _T_144 @[el2_dec_decode_ctl.scala 325:26] - node _T_145 = eq(cam_data_reset_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 326:67] - node _T_146 = and(cam_data_reset, _T_145) @[el2_dec_decode_ctl.scala 326:45] - node _T_147 = and(_T_146, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 326:88] - cam_data_reset_val[2] <= _T_147 @[el2_dec_decode_ctl.scala 326:27] - wire _T_148 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 327:28] - _T_148.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_148.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_148.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_148.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - cam_in[2].bits.rd <= _T_148.bits.rd @[el2_dec_decode_ctl.scala 327:14] - cam_in[2].bits.tag <= _T_148.bits.tag @[el2_dec_decode_ctl.scala 327:14] - cam_in[2].bits.wb <= _T_148.bits.wb @[el2_dec_decode_ctl.scala 327:14] - cam_in[2].valid <= _T_148.valid @[el2_dec_decode_ctl.scala 327:14] - cam[2].bits.rd <= cam_raw[2].bits.rd @[el2_dec_decode_ctl.scala 328:11] - cam[2].bits.tag <= cam_raw[2].bits.tag @[el2_dec_decode_ctl.scala 328:11] - cam[2].bits.wb <= cam_raw[2].bits.wb @[el2_dec_decode_ctl.scala 328:11] - cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 328:11] - node _T_149 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 330:32] - when _T_149 : @[el2_dec_decode_ctl.scala 330:39] - cam[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] - skip @[el2_dec_decode_ctl.scala 330:39] - node _T_150 = bits(cam_wen, 2, 2) @[el2_dec_decode_ctl.scala 333:17] - node _T_151 = bits(_T_150, 0, 0) @[el2_dec_decode_ctl.scala 333:21] - when _T_151 : @[el2_dec_decode_ctl.scala 333:28] - cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] - cam_in[2].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:32] - cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:32] - cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:32] - skip @[el2_dec_decode_ctl.scala 333:28] - else : @[el2_dec_decode_ctl.scala 338:131] - node _T_152 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 338:37] - node _T_153 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] - node _T_154 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 338:85] - node _T_155 = and(_T_153, _T_154) @[el2_dec_decode_ctl.scala 338:64] - node _T_156 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 338:123] - node _T_157 = and(_T_155, _T_156) @[el2_dec_decode_ctl.scala 338:105] - node _T_158 = or(_T_152, _T_157) @[el2_dec_decode_ctl.scala 338:44] - when _T_158 : @[el2_dec_decode_ctl.scala 338:131] - cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] - skip @[el2_dec_decode_ctl.scala 338:131] - else : @[el2_dec_decode_ctl.scala 340:16] - cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 341:22] - cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 341:22] - cam_in[2].bits.wb <= cam[2].bits.wb @[el2_dec_decode_ctl.scala 341:22] - cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 341:22] - skip @[el2_dec_decode_ctl.scala 340:16] - node _T_159 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] - node _T_160 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 343:79] - node _T_161 = and(_T_159, _T_160) @[el2_dec_decode_ctl.scala 343:44] - node _T_162 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:115] - node _T_163 = and(_T_161, _T_162) @[el2_dec_decode_ctl.scala 343:100] - when _T_163 : @[el2_dec_decode_ctl.scala 343:122] - cam_in[2].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:25] - skip @[el2_dec_decode_ctl.scala 343:122] - when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] - cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] - skip @[el2_dec_decode_ctl.scala 347:32] - wire _T_164 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 351:70] - _T_164.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_164.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_164.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_164.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - reg _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_164)) @[el2_dec_decode_ctl.scala 351:47] - _T_165.bits.rd <= cam_in[2].bits.rd @[el2_dec_decode_ctl.scala 351:47] - _T_165.bits.tag <= cam_in[2].bits.tag @[el2_dec_decode_ctl.scala 351:47] - _T_165.bits.wb <= cam_in[2].bits.wb @[el2_dec_decode_ctl.scala 351:47] - _T_165.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 351:47] - cam_raw[2].bits.rd <= _T_165.bits.rd @[el2_dec_decode_ctl.scala 351:15] - cam_raw[2].bits.tag <= _T_165.bits.tag @[el2_dec_decode_ctl.scala 351:15] - cam_raw[2].bits.wb <= _T_165.bits.wb @[el2_dec_decode_ctl.scala 351:15] - cam_raw[2].valid <= _T_165.valid @[el2_dec_decode_ctl.scala 351:15] - node _T_166 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[el2_dec_decode_ctl.scala 352:46] - node _T_167 = and(_T_166, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 352:71] - nonblock_load_write[2] <= _T_167 @[el2_dec_decode_ctl.scala 352:28] - node _T_168 = eq(cam_inv_reset_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 325:66] - node _T_169 = and(io.lsu_nonblock_load_inv_r, _T_168) @[el2_dec_decode_ctl.scala 325:45] - node _T_170 = and(_T_169, cam[3].valid) @[el2_dec_decode_ctl.scala 325:87] - cam_inv_reset_val[3] <= _T_170 @[el2_dec_decode_ctl.scala 325:26] - node _T_171 = eq(cam_data_reset_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 326:67] - node _T_172 = and(cam_data_reset, _T_171) @[el2_dec_decode_ctl.scala 326:45] - node _T_173 = and(_T_172, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 326:88] - cam_data_reset_val[3] <= _T_173 @[el2_dec_decode_ctl.scala 326:27] - wire _T_174 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 327:28] - _T_174.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_174.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_174.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - _T_174.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] - cam_in[3].bits.rd <= _T_174.bits.rd @[el2_dec_decode_ctl.scala 327:14] - cam_in[3].bits.tag <= _T_174.bits.tag @[el2_dec_decode_ctl.scala 327:14] - cam_in[3].bits.wb <= _T_174.bits.wb @[el2_dec_decode_ctl.scala 327:14] - cam_in[3].valid <= _T_174.valid @[el2_dec_decode_ctl.scala 327:14] - cam[3].bits.rd <= cam_raw[3].bits.rd @[el2_dec_decode_ctl.scala 328:11] - cam[3].bits.tag <= cam_raw[3].bits.tag @[el2_dec_decode_ctl.scala 328:11] - cam[3].bits.wb <= cam_raw[3].bits.wb @[el2_dec_decode_ctl.scala 328:11] - cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 328:11] - node _T_175 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 330:32] - when _T_175 : @[el2_dec_decode_ctl.scala 330:39] - cam[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] - skip @[el2_dec_decode_ctl.scala 330:39] - node _T_176 = bits(cam_wen, 3, 3) @[el2_dec_decode_ctl.scala 333:17] - node _T_177 = bits(_T_176, 0, 0) @[el2_dec_decode_ctl.scala 333:21] - when _T_177 : @[el2_dec_decode_ctl.scala 333:28] - cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] - cam_in[3].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:32] - cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:32] - cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:32] - skip @[el2_dec_decode_ctl.scala 333:28] - else : @[el2_dec_decode_ctl.scala 338:131] - node _T_178 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 338:37] - node _T_179 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] - node _T_180 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 338:85] - node _T_181 = and(_T_179, _T_180) @[el2_dec_decode_ctl.scala 338:64] - node _T_182 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 338:123] - node _T_183 = and(_T_181, _T_182) @[el2_dec_decode_ctl.scala 338:105] - node _T_184 = or(_T_178, _T_183) @[el2_dec_decode_ctl.scala 338:44] - when _T_184 : @[el2_dec_decode_ctl.scala 338:131] - cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] - skip @[el2_dec_decode_ctl.scala 338:131] - else : @[el2_dec_decode_ctl.scala 340:16] - cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 341:22] - cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 341:22] - cam_in[3].bits.wb <= cam[3].bits.wb @[el2_dec_decode_ctl.scala 341:22] - cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 341:22] - skip @[el2_dec_decode_ctl.scala 340:16] - node _T_185 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] - node _T_186 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 343:79] - node _T_187 = and(_T_185, _T_186) @[el2_dec_decode_ctl.scala 343:44] - node _T_188 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:115] - node _T_189 = and(_T_187, _T_188) @[el2_dec_decode_ctl.scala 343:100] - when _T_189 : @[el2_dec_decode_ctl.scala 343:122] - cam_in[3].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:25] - skip @[el2_dec_decode_ctl.scala 343:122] - when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] - cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] - skip @[el2_dec_decode_ctl.scala 347:32] - wire _T_190 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 351:70] - _T_190.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_190.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_190.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - _T_190.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] - reg _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_190)) @[el2_dec_decode_ctl.scala 351:47] - _T_191.bits.rd <= cam_in[3].bits.rd @[el2_dec_decode_ctl.scala 351:47] - _T_191.bits.tag <= cam_in[3].bits.tag @[el2_dec_decode_ctl.scala 351:47] - _T_191.bits.wb <= cam_in[3].bits.wb @[el2_dec_decode_ctl.scala 351:47] - _T_191.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 351:47] - cam_raw[3].bits.rd <= _T_191.bits.rd @[el2_dec_decode_ctl.scala 351:15] - cam_raw[3].bits.tag <= _T_191.bits.tag @[el2_dec_decode_ctl.scala 351:15] - cam_raw[3].bits.wb <= _T_191.bits.wb @[el2_dec_decode_ctl.scala 351:15] - cam_raw[3].valid <= _T_191.valid @[el2_dec_decode_ctl.scala 351:15] - node _T_192 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[el2_dec_decode_ctl.scala 352:46] - node _T_193 = and(_T_192, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 352:71] - nonblock_load_write[3] <= _T_193 @[el2_dec_decode_ctl.scala 352:28] - io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 355:29] - node _T_194 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 357:49] - node nonblock_load_cancel = and(_T_194, i0_wen_r) @[el2_dec_decode_ctl.scala 357:81] - node _T_195 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 358:95] - node _T_196 = or(_T_195, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 358:95] - node _T_197 = or(_T_196, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 358:95] - node _T_198 = bits(_T_197, 0, 0) @[el2_dec_decode_ctl.scala 358:99] - node _T_199 = and(io.lsu_nonblock_load_data_valid, _T_198) @[el2_dec_decode_ctl.scala 358:64] - node _T_200 = eq(nonblock_load_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 358:109] - node _T_201 = and(_T_199, _T_200) @[el2_dec_decode_ctl.scala 358:106] - io.dec_nonblock_load_wen <= _T_201 @[el2_dec_decode_ctl.scala 358:28] - node _T_202 = eq(nonblock_load_rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:54] - node _T_203 = and(_T_202, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 359:66] - node _T_204 = and(_T_203, io.dec_i0_rs1_en_d) @[el2_dec_decode_ctl.scala 359:97] - node _T_205 = eq(nonblock_load_rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:137] - node _T_206 = and(_T_205, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 359:149] - node _T_207 = and(_T_206, io.dec_i0_rs2_en_d) @[el2_dec_decode_ctl.scala 359:180] - node i0_nonblock_boundary_stall = or(_T_204, _T_207) @[el2_dec_decode_ctl.scala 359:118] - i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 361:26] - node _T_208 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] - node _T_209 = mux(_T_208, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_210 = and(_T_209, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 363:88] - node _T_211 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 363:126] - node _T_212 = eq(cam[0].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:159] - node _T_213 = and(_T_211, _T_212) @[el2_dec_decode_ctl.scala 363:141] - node _T_214 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 363:192] - node _T_215 = eq(cam[0].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:225] - node _T_216 = and(_T_214, _T_215) @[el2_dec_decode_ctl.scala 363:207] - node _T_217 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] - node _T_218 = mux(_T_217, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_219 = and(_T_218, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 363:88] - node _T_220 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 363:126] - node _T_221 = eq(cam[1].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:159] - node _T_222 = and(_T_220, _T_221) @[el2_dec_decode_ctl.scala 363:141] - node _T_223 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 363:192] - node _T_224 = eq(cam[1].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:225] - node _T_225 = and(_T_223, _T_224) @[el2_dec_decode_ctl.scala 363:207] - node _T_226 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] - node _T_227 = mux(_T_226, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_228 = and(_T_227, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 363:88] - node _T_229 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 363:126] - node _T_230 = eq(cam[2].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:159] - node _T_231 = and(_T_229, _T_230) @[el2_dec_decode_ctl.scala 363:141] - node _T_232 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 363:192] - node _T_233 = eq(cam[2].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:225] - node _T_234 = and(_T_232, _T_233) @[el2_dec_decode_ctl.scala 363:207] - node _T_235 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] - node _T_236 = mux(_T_235, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_237 = and(_T_236, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 363:88] - node _T_238 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 363:126] - node _T_239 = eq(cam[3].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:159] - node _T_240 = and(_T_238, _T_239) @[el2_dec_decode_ctl.scala 363:141] - node _T_241 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 363:192] - node _T_242 = eq(cam[3].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:225] - node _T_243 = and(_T_241, _T_242) @[el2_dec_decode_ctl.scala 363:207] - node _T_244 = or(_T_210, _T_219) @[el2_dec_decode_ctl.scala 364:69] - node _T_245 = or(_T_244, _T_228) @[el2_dec_decode_ctl.scala 364:69] - node waddr = or(_T_245, _T_237) @[el2_dec_decode_ctl.scala 364:69] - node _T_246 = or(_T_213, _T_222) @[el2_dec_decode_ctl.scala 364:102] - node _T_247 = or(_T_246, _T_231) @[el2_dec_decode_ctl.scala 364:102] - node ld_stall_1 = or(_T_247, _T_240) @[el2_dec_decode_ctl.scala 364:102] - node _T_248 = or(_T_216, _T_225) @[el2_dec_decode_ctl.scala 364:134] - node _T_249 = or(_T_248, _T_234) @[el2_dec_decode_ctl.scala 364:134] - node ld_stall_2 = or(_T_249, _T_243) @[el2_dec_decode_ctl.scala 364:134] - io.dec_nonblock_load_waddr <= waddr @[el2_dec_decode_ctl.scala 365:29] - node _T_250 = or(ld_stall_1, ld_stall_2) @[el2_dec_decode_ctl.scala 366:38] - node _T_251 = or(_T_250, i0_nonblock_boundary_stall) @[el2_dec_decode_ctl.scala 366:51] - i0_nonblock_load_stall <= _T_251 @[el2_dec_decode_ctl.scala 366:25] - node _T_252 = eq(i0_predict_br, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 375:34] - node i0_br_unpred = and(i0_dp.jal, _T_252) @[el2_dec_decode_ctl.scala 375:32] - node _T_253 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] - node _T_254 = mux(_T_253, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_255 = and(csr_read, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 387:16] - node _T_256 = bits(_T_255, 0, 0) @[el2_dec_decode_ctl.scala 387:30] - node _T_257 = eq(csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 388:6] - node _T_258 = and(_T_257, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 388:16] - node _T_259 = bits(_T_258, 0, 0) @[el2_dec_decode_ctl.scala 388:30] - node _T_260 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 389:18] - node _T_261 = and(csr_read, _T_260) @[el2_dec_decode_ctl.scala 389:16] - node _T_262 = bits(_T_261, 0, 0) @[el2_dec_decode_ctl.scala 389:30] - node _T_263 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] - node _T_264 = mux(i0_dp.load, UInt<4>("h02"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(i0_dp.store, UInt<4>("h03"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_262, UInt<4>("h05"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_259, UInt<4>("h06"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_256, UInt<4>("h07"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_269) @[Mux.scala 98:16] - node _T_271 = mux(i0_dp.ecall, UInt<4>("h09"), _T_270) @[Mux.scala 98:16] - node _T_272 = mux(i0_dp.fence, UInt<4>("h0a"), _T_271) @[Mux.scala 98:16] - node _T_273 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_272) @[Mux.scala 98:16] - node _T_274 = mux(i0_dp.mret, UInt<4>("h0c"), _T_273) @[Mux.scala 98:16] - node _T_275 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_274) @[Mux.scala 98:16] - node _T_276 = mux(i0_dp.jal, UInt<4>("h0e"), _T_275) @[Mux.scala 98:16] - node _T_277 = and(_T_254, _T_276) @[el2_dec_decode_ctl.scala 379:49] - d_t.pmu_i0_itype <= _T_277 @[el2_dec_decode_ctl.scala 379:21] - inst i0_dec of el2_dec_dec_ctl @[el2_dec_decode_ctl.scala 396:22] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 319:56] + node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45] + node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:82] + cam_inv_reset_val[0] <= _T_93 @[el2_dec_decode_ctl.scala 321:26] + node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_95 = and(cam_data_reset, _T_94) @[el2_dec_decode_ctl.scala 322:45] + node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:83] + cam_data_reset_val[0] <= _T_96 @[el2_dec_decode_ctl.scala 322:27] + wire _T_97 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_97.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + cam_in[0].rd <= _T_97.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].tag <= _T_97.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].wb <= _T_97.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].valid <= _T_97.valid @[el2_dec_decode_ctl.scala 323:14] + cam[0].rd <= cam_raw[0].rd @[el2_dec_decode_ctl.scala 324:11] + cam[0].tag <= cam_raw[0].tag @[el2_dec_decode_ctl.scala 324:11] + cam[0].wb <= cam_raw[0].wb @[el2_dec_decode_ctl.scala 324:11] + cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 324:11] + node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 326:32] + when _T_98 : @[el2_dec_decode_ctl.scala 326:39] + cam[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20] + skip @[el2_dec_decode_ctl.scala 326:39] + node _T_99 = bits(cam_wen, 0, 0) @[el2_dec_decode_ctl.scala 329:17] + node _T_100 = bits(_T_99, 0, 0) @[el2_dec_decode_ctl.scala 329:21] + when _T_100 : @[el2_dec_decode_ctl.scala 329:28] + cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] + cam_in[0].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[0].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[0].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] + skip @[el2_dec_decode_ctl.scala 329:28] + else : @[el2_dec_decode_ctl.scala 334:116] + node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37] + node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] + node _T_103 = eq(r_d_in.i0rd, cam[0].rd) @[el2_dec_decode_ctl.scala 334:80] + node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64] + node _T_105 = bits(cam[0].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:95] + node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44] + when _T_107 : @[el2_dec_decode_ctl.scala 334:116] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] + skip @[el2_dec_decode_ctl.scala 334:116] + else : @[el2_dec_decode_ctl.scala 336:16] + cam_in[0].rd <= cam[0].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].tag <= cam[0].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].wb <= cam[0].wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 337:22] + skip @[el2_dec_decode_ctl.scala 336:16] + node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] + node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_110 = and(_T_108, _T_109) @[el2_dec_decode_ctl.scala 339:44] + node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:95] + when _T_112 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[0].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] + skip @[el2_dec_decode_ctl.scala 343:32] + wire _T_113 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_113.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + reg _T_114 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47] + _T_114.rd <= cam_in[0].rd @[el2_dec_decode_ctl.scala 347:47] + _T_114.tag <= cam_in[0].tag @[el2_dec_decode_ctl.scala 347:47] + _T_114.wb <= cam_in[0].wb @[el2_dec_decode_ctl.scala 347:47] + _T_114.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 347:47] + cam_raw[0].rd <= _T_114.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].tag <= _T_114.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].wb <= _T_114.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].valid <= _T_114.valid @[el2_dec_decode_ctl.scala 347:15] + node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:66] + nonblock_load_write[0] <= _T_116 @[el2_dec_decode_ctl.scala 348:28] + node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_118 = and(io.lsu_nonblock_load_inv_r, _T_117) @[el2_dec_decode_ctl.scala 321:45] + node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:82] + cam_inv_reset_val[1] <= _T_119 @[el2_dec_decode_ctl.scala 321:26] + node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_121 = and(cam_data_reset, _T_120) @[el2_dec_decode_ctl.scala 322:45] + node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:83] + cam_data_reset_val[1] <= _T_122 @[el2_dec_decode_ctl.scala 322:27] + wire _T_123 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_123.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + cam_in[1].rd <= _T_123.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].tag <= _T_123.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].wb <= _T_123.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].valid <= _T_123.valid @[el2_dec_decode_ctl.scala 323:14] + cam[1].rd <= cam_raw[1].rd @[el2_dec_decode_ctl.scala 324:11] + cam[1].tag <= cam_raw[1].tag @[el2_dec_decode_ctl.scala 324:11] + cam[1].wb <= cam_raw[1].wb @[el2_dec_decode_ctl.scala 324:11] + cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 324:11] + node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 326:32] + when _T_124 : @[el2_dec_decode_ctl.scala 326:39] + cam[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20] + skip @[el2_dec_decode_ctl.scala 326:39] + node _T_125 = bits(cam_wen, 1, 1) @[el2_dec_decode_ctl.scala 329:17] + node _T_126 = bits(_T_125, 0, 0) @[el2_dec_decode_ctl.scala 329:21] + when _T_126 : @[el2_dec_decode_ctl.scala 329:28] + cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] + cam_in[1].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[1].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[1].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] + skip @[el2_dec_decode_ctl.scala 329:28] + else : @[el2_dec_decode_ctl.scala 334:116] + node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37] + node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] + node _T_129 = eq(r_d_in.i0rd, cam[1].rd) @[el2_dec_decode_ctl.scala 334:80] + node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64] + node _T_131 = bits(cam[1].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:95] + node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44] + when _T_133 : @[el2_dec_decode_ctl.scala 334:116] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] + skip @[el2_dec_decode_ctl.scala 334:116] + else : @[el2_dec_decode_ctl.scala 336:16] + cam_in[1].rd <= cam[1].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].tag <= cam[1].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].wb <= cam[1].wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 337:22] + skip @[el2_dec_decode_ctl.scala 336:16] + node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] + node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_136 = and(_T_134, _T_135) @[el2_dec_decode_ctl.scala 339:44] + node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:95] + when _T_138 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[1].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] + skip @[el2_dec_decode_ctl.scala 343:32] + wire _T_139 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_139.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + reg _T_140 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47] + _T_140.rd <= cam_in[1].rd @[el2_dec_decode_ctl.scala 347:47] + _T_140.tag <= cam_in[1].tag @[el2_dec_decode_ctl.scala 347:47] + _T_140.wb <= cam_in[1].wb @[el2_dec_decode_ctl.scala 347:47] + _T_140.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 347:47] + cam_raw[1].rd <= _T_140.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].tag <= _T_140.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].wb <= _T_140.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].valid <= _T_140.valid @[el2_dec_decode_ctl.scala 347:15] + node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:66] + nonblock_load_write[1] <= _T_142 @[el2_dec_decode_ctl.scala 348:28] + node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_144 = and(io.lsu_nonblock_load_inv_r, _T_143) @[el2_dec_decode_ctl.scala 321:45] + node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:82] + cam_inv_reset_val[2] <= _T_145 @[el2_dec_decode_ctl.scala 321:26] + node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_147 = and(cam_data_reset, _T_146) @[el2_dec_decode_ctl.scala 322:45] + node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:83] + cam_data_reset_val[2] <= _T_148 @[el2_dec_decode_ctl.scala 322:27] + wire _T_149 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_149.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + cam_in[2].rd <= _T_149.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].tag <= _T_149.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].wb <= _T_149.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].valid <= _T_149.valid @[el2_dec_decode_ctl.scala 323:14] + cam[2].rd <= cam_raw[2].rd @[el2_dec_decode_ctl.scala 324:11] + cam[2].tag <= cam_raw[2].tag @[el2_dec_decode_ctl.scala 324:11] + cam[2].wb <= cam_raw[2].wb @[el2_dec_decode_ctl.scala 324:11] + cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 324:11] + node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 326:32] + when _T_150 : @[el2_dec_decode_ctl.scala 326:39] + cam[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20] + skip @[el2_dec_decode_ctl.scala 326:39] + node _T_151 = bits(cam_wen, 2, 2) @[el2_dec_decode_ctl.scala 329:17] + node _T_152 = bits(_T_151, 0, 0) @[el2_dec_decode_ctl.scala 329:21] + when _T_152 : @[el2_dec_decode_ctl.scala 329:28] + cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] + cam_in[2].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[2].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[2].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] + skip @[el2_dec_decode_ctl.scala 329:28] + else : @[el2_dec_decode_ctl.scala 334:116] + node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37] + node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] + node _T_155 = eq(r_d_in.i0rd, cam[2].rd) @[el2_dec_decode_ctl.scala 334:80] + node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64] + node _T_157 = bits(cam[2].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:95] + node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44] + when _T_159 : @[el2_dec_decode_ctl.scala 334:116] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] + skip @[el2_dec_decode_ctl.scala 334:116] + else : @[el2_dec_decode_ctl.scala 336:16] + cam_in[2].rd <= cam[2].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].tag <= cam[2].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].wb <= cam[2].wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 337:22] + skip @[el2_dec_decode_ctl.scala 336:16] + node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] + node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_162 = and(_T_160, _T_161) @[el2_dec_decode_ctl.scala 339:44] + node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:95] + when _T_164 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[2].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] + skip @[el2_dec_decode_ctl.scala 343:32] + wire _T_165 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_165.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + reg _T_166 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47] + _T_166.rd <= cam_in[2].rd @[el2_dec_decode_ctl.scala 347:47] + _T_166.tag <= cam_in[2].tag @[el2_dec_decode_ctl.scala 347:47] + _T_166.wb <= cam_in[2].wb @[el2_dec_decode_ctl.scala 347:47] + _T_166.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 347:47] + cam_raw[2].rd <= _T_166.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].tag <= _T_166.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].wb <= _T_166.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].valid <= _T_166.valid @[el2_dec_decode_ctl.scala 347:15] + node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:66] + nonblock_load_write[2] <= _T_168 @[el2_dec_decode_ctl.scala 348:28] + node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_170 = and(io.lsu_nonblock_load_inv_r, _T_169) @[el2_dec_decode_ctl.scala 321:45] + node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:82] + cam_inv_reset_val[3] <= _T_171 @[el2_dec_decode_ctl.scala 321:26] + node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_173 = and(cam_data_reset, _T_172) @[el2_dec_decode_ctl.scala 322:45] + node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:83] + cam_data_reset_val[3] <= _T_174 @[el2_dec_decode_ctl.scala 322:27] + wire _T_175 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_175.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + cam_in[3].rd <= _T_175.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].tag <= _T_175.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].wb <= _T_175.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].valid <= _T_175.valid @[el2_dec_decode_ctl.scala 323:14] + cam[3].rd <= cam_raw[3].rd @[el2_dec_decode_ctl.scala 324:11] + cam[3].tag <= cam_raw[3].tag @[el2_dec_decode_ctl.scala 324:11] + cam[3].wb <= cam_raw[3].wb @[el2_dec_decode_ctl.scala 324:11] + cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 324:11] + node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 326:32] + when _T_176 : @[el2_dec_decode_ctl.scala 326:39] + cam[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:20] + skip @[el2_dec_decode_ctl.scala 326:39] + node _T_177 = bits(cam_wen, 3, 3) @[el2_dec_decode_ctl.scala 329:17] + node _T_178 = bits(_T_177, 0, 0) @[el2_dec_decode_ctl.scala 329:21] + when _T_178 : @[el2_dec_decode_ctl.scala 329:28] + cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] + cam_in[3].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[3].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[3].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] + skip @[el2_dec_decode_ctl.scala 329:28] + else : @[el2_dec_decode_ctl.scala 334:116] + node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37] + node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] + node _T_181 = eq(r_d_in.i0rd, cam[3].rd) @[el2_dec_decode_ctl.scala 334:80] + node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64] + node _T_183 = bits(cam[3].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:95] + node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44] + when _T_185 : @[el2_dec_decode_ctl.scala 334:116] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] + skip @[el2_dec_decode_ctl.scala 334:116] + else : @[el2_dec_decode_ctl.scala 336:16] + cam_in[3].rd <= cam[3].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].tag <= cam[3].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].wb <= cam[3].wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 337:22] + skip @[el2_dec_decode_ctl.scala 336:16] + node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] + node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_188 = and(_T_186, _T_187) @[el2_dec_decode_ctl.scala 339:44] + node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:95] + when _T_190 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[3].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] + skip @[el2_dec_decode_ctl.scala 343:32] + wire _T_191 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_191.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + reg _T_192 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47] + _T_192.rd <= cam_in[3].rd @[el2_dec_decode_ctl.scala 347:47] + _T_192.tag <= cam_in[3].tag @[el2_dec_decode_ctl.scala 347:47] + _T_192.wb <= cam_in[3].wb @[el2_dec_decode_ctl.scala 347:47] + _T_192.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 347:47] + cam_raw[3].rd <= _T_192.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].tag <= _T_192.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].wb <= _T_192.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].valid <= _T_192.valid @[el2_dec_decode_ctl.scala 347:15] + node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:66] + nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28] + io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29] + node _T_195 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:44] + node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:76] + node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95] + node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95] + node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95] + node _T_199 = bits(_T_198, 0, 0) @[el2_dec_decode_ctl.scala 354:99] + node _T_200 = and(io.lsu_nonblock_load_data_valid, _T_199) @[el2_dec_decode_ctl.scala 354:64] + node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 354:109] + node _T_202 = and(_T_200, _T_201) @[el2_dec_decode_ctl.scala 354:106] + io.dec_nonblock_load_wen <= _T_202 @[el2_dec_decode_ctl.scala 354:28] + node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[el2_dec_decode_ctl.scala 355:54] + node _T_204 = and(_T_203, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 355:66] + node _T_205 = and(_T_204, io.dec_i0_rs1_en_d) @[el2_dec_decode_ctl.scala 355:97] + node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[el2_dec_decode_ctl.scala 355:137] + node _T_207 = and(_T_206, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 355:149] + node _T_208 = and(_T_207, io.dec_i0_rs2_en_d) @[el2_dec_decode_ctl.scala 355:180] + node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[el2_dec_decode_ctl.scala 355:118] + i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 357:26] + node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] + node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_211 = and(_T_210, cam[0].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_213 = eq(cam[0].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:136] + node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_216 = eq(cam[0].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:197] + node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] + node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_220 = and(_T_219, cam[1].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_222 = eq(cam[1].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:136] + node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_225 = eq(cam[1].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:197] + node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] + node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_229 = and(_T_228, cam[2].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_231 = eq(cam[2].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:136] + node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_234 = eq(cam[2].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:197] + node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] + node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_238 = and(_T_237, cam[3].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_240 = eq(cam[3].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:136] + node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_243 = eq(cam[3].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:197] + node _T_245 = or(_T_211, _T_220) @[el2_dec_decode_ctl.scala 360:69] + node _T_246 = or(_T_245, _T_229) @[el2_dec_decode_ctl.scala 360:69] + node waddr = or(_T_246, _T_238) @[el2_dec_decode_ctl.scala 360:69] + node _T_247 = or(_T_214, _T_223) @[el2_dec_decode_ctl.scala 360:102] + node _T_248 = or(_T_247, _T_232) @[el2_dec_decode_ctl.scala 360:102] + node ld_stall_1 = or(_T_248, _T_241) @[el2_dec_decode_ctl.scala 360:102] + node _T_249 = or(_T_217, _T_226) @[el2_dec_decode_ctl.scala 360:134] + node _T_250 = or(_T_249, _T_235) @[el2_dec_decode_ctl.scala 360:134] + node ld_stall_2 = or(_T_250, _T_244) @[el2_dec_decode_ctl.scala 360:134] + io.dec_nonblock_load_waddr <= waddr @[el2_dec_decode_ctl.scala 361:29] + node _T_251 = or(ld_stall_1, ld_stall_2) @[el2_dec_decode_ctl.scala 362:38] + node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[el2_dec_decode_ctl.scala 362:51] + i0_nonblock_load_stall <= _T_252 @[el2_dec_decode_ctl.scala 362:25] + node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 371:34] + node i0_br_unpred = and(i0_dp.jal, _T_253) @[el2_dec_decode_ctl.scala 371:32] + node _T_254 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] + node _T_255 = mux(_T_254, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 383:16] + node _T_257 = bits(_T_256, 0, 0) @[el2_dec_decode_ctl.scala 383:30] + node _T_258 = eq(csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 384:6] + node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 384:16] + node _T_260 = bits(_T_259, 0, 0) @[el2_dec_decode_ctl.scala 384:30] + node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 385:18] + node _T_262 = and(csr_read, _T_261) @[el2_dec_decode_ctl.scala 385:16] + node _T_263 = bits(_T_262, 0, 0) @[el2_dec_decode_ctl.scala 385:30] + node _T_264 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] + node _T_265 = mux(i0_dp.load, UInt<4>("h02"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(i0_dp.store, UInt<4>("h03"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_263, UInt<4>("h05"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_260, UInt<4>("h06"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_257, UInt<4>("h07"), _T_269) @[Mux.scala 98:16] + node _T_271 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_270) @[Mux.scala 98:16] + node _T_272 = mux(i0_dp.ecall, UInt<4>("h09"), _T_271) @[Mux.scala 98:16] + node _T_273 = mux(i0_dp.fence, UInt<4>("h0a"), _T_272) @[Mux.scala 98:16] + node _T_274 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_273) @[Mux.scala 98:16] + node _T_275 = mux(i0_dp.mret, UInt<4>("h0c"), _T_274) @[Mux.scala 98:16] + node _T_276 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_275) @[Mux.scala 98:16] + node _T_277 = mux(i0_dp.jal, UInt<4>("h0e"), _T_276) @[Mux.scala 98:16] + node _T_278 = and(_T_255, _T_277) @[el2_dec_decode_ctl.scala 375:49] + d_t.pmu_i0_itype <= _T_278 @[el2_dec_decode_ctl.scala 375:21] + inst i0_dec of el2_dec_dec_ctl @[el2_dec_decode_ctl.scala 392:22] i0_dec.clock <= clock i0_dec.reset <= reset - i0_dec.io.ins <= io.dec_i0_instr_d @[el2_dec_decode_ctl.scala 397:16] - i0_dp_raw.legal <= i0_dec.io.out.legal @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.fence <= i0_dec.io.out.fence @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rem <= i0_dec.io.out.rem @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.div <= i0_dec.io.out.div @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.low <= i0_dec.io.out.low @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.mul <= i0_dec.io.out.mul @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.mret <= i0_dec.io.out.mret @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.ecall <= i0_dec.io.out.ecall @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.postsync <= i0_dec.io.out.postsync @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.presync <= i0_dec.io.out.presync @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.word <= i0_dec.io.out.word @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.half <= i0_dec.io.out.half @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.by <= i0_dec.io.out.by @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.jal <= i0_dec.io.out.jal @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.blt <= i0_dec.io.out.blt @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.bge <= i0_dec.io.out.bge @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.bne <= i0_dec.io.out.bne @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.beq <= i0_dec.io.out.beq @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.condbr <= i0_dec.io.out.condbr @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.unsign <= i0_dec.io.out.unsign @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.slt <= i0_dec.io.out.slt @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.srl <= i0_dec.io.out.srl @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.sra <= i0_dec.io.out.sra @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.sll <= i0_dec.io.out.sll @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.lxor <= i0_dec.io.out.lxor @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.lor <= i0_dec.io.out.lor @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.land <= i0_dec.io.out.land @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.sub <= i0_dec.io.out.sub @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.add <= i0_dec.io.out.add @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.lsu <= i0_dec.io.out.lsu @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.store <= i0_dec.io.out.store @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.load <= i0_dec.io.out.load @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.pc <= i0_dec.io.out.pc @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rd <= i0_dec.io.out.rd @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[el2_dec_decode_ctl.scala 398:12] - i0_dp_raw.alu <= i0_dec.io.out.alu @[el2_dec_decode_ctl.scala 398:12] - reg _T_278 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 400:45] - _T_278 <= io.lsu_idle_any @[el2_dec_decode_ctl.scala 400:45] - lsu_idle <= _T_278 @[el2_dec_decode_ctl.scala 400:11] - node _T_279 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 403:73] - node _T_280 = and(leak1_i1_stall, _T_279) @[el2_dec_decode_ctl.scala 403:71] - node _T_281 = or(io.dec_tlu_flush_leak_one_r, _T_280) @[el2_dec_decode_ctl.scala 403:53] - leak1_i1_stall_in <= _T_281 @[el2_dec_decode_ctl.scala 403:21] - reg _T_282 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 404:56] - _T_282 <= leak1_i1_stall_in @[el2_dec_decode_ctl.scala 404:56] - leak1_i1_stall <= _T_282 @[el2_dec_decode_ctl.scala 404:21] - leak1_mode <= leak1_i1_stall @[el2_dec_decode_ctl.scala 405:14] - node _T_283 = and(io.dec_i0_decode_d, leak1_i1_stall) @[el2_dec_decode_ctl.scala 406:45] - node _T_284 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 406:83] - node _T_285 = and(leak1_i0_stall, _T_284) @[el2_dec_decode_ctl.scala 406:81] - node _T_286 = or(_T_283, _T_285) @[el2_dec_decode_ctl.scala 406:63] - leak1_i0_stall_in <= _T_286 @[el2_dec_decode_ctl.scala 406:21] - reg _T_287 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 407:56] - _T_287 <= leak1_i0_stall_in @[el2_dec_decode_ctl.scala 407:56] - leak1_i0_stall <= _T_287 @[el2_dec_decode_ctl.scala 407:21] - node _T_288 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 411:29] - node _T_289 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 411:36] - node _T_290 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 411:46] - node _T_291 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 411:53] - node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_293 = cat(_T_288, _T_289) @[Cat.scala 29:58] - node _T_294 = cat(_T_293, _T_290) @[Cat.scala 29:58] - node i0_pcall_imm = cat(_T_294, _T_292) @[Cat.scala 29:58] - node _T_295 = bits(i0_pcall_imm, 12, 12) @[el2_dec_decode_ctl.scala 412:46] - node _T_296 = bits(_T_295, 0, 0) @[el2_dec_decode_ctl.scala 412:51] - node _T_297 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 412:71] - node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[el2_dec_decode_ctl.scala 412:79] - node _T_299 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 412:104] - node _T_300 = eq(_T_299, UInt<8>("h00")) @[el2_dec_decode_ctl.scala 412:112] - node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[el2_dec_decode_ctl.scala 412:33] - node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 413:47] - node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 413:76] - node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 413:98] - node _T_304 = or(_T_302, _T_303) @[el2_dec_decode_ctl.scala 413:89] - node i0_pcall_case = and(_T_301, _T_304) @[el2_dec_decode_ctl.scala 413:65] - node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 414:47] - node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 414:76] - node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 414:98] - node _T_308 = or(_T_306, _T_307) @[el2_dec_decode_ctl.scala 414:89] - node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 414:67] - node i0_pja_case = and(_T_305, _T_309) @[el2_dec_decode_ctl.scala 414:65] - node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 415:38] - i0_pcall_raw <= _T_310 @[el2_dec_decode_ctl.scala 415:20] - node _T_311 = and(i0_dp.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 416:38] - i0_pcall <= _T_311 @[el2_dec_decode_ctl.scala 416:20] - node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 417:38] - i0_pja_raw <= _T_312 @[el2_dec_decode_ctl.scala 417:20] - node _T_313 = and(i0_dp.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 418:38] - i0_pja <= _T_313 @[el2_dec_decode_ctl.scala 418:20] - node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[el2_dec_decode_ctl.scala 419:41] - node _T_315 = bits(_T_314, 0, 0) @[el2_dec_decode_ctl.scala 419:55] - node _T_316 = bits(i0_pcall_imm, 12, 1) @[el2_dec_decode_ctl.scala 419:75] - node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 419:90] - node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[el2_dec_decode_ctl.scala 419:97] - node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[el2_dec_decode_ctl.scala 419:103] - node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[el2_dec_decode_ctl.scala 419:113] + i0_dec.io.ins <= io.dec_i0_instr_d @[el2_dec_decode_ctl.scala 393:16] + i0_dp_raw.legal <= i0_dec.io.out.legal @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.fence <= i0_dec.io.out.fence @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rem <= i0_dec.io.out.rem @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.div <= i0_dec.io.out.div @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.low <= i0_dec.io.out.low @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.mul <= i0_dec.io.out.mul @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.mret <= i0_dec.io.out.mret @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.ecall <= i0_dec.io.out.ecall @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.postsync <= i0_dec.io.out.postsync @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.presync <= i0_dec.io.out.presync @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.word <= i0_dec.io.out.word @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.half <= i0_dec.io.out.half @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.by <= i0_dec.io.out.by @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.jal <= i0_dec.io.out.jal @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.blt <= i0_dec.io.out.blt @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.bge <= i0_dec.io.out.bge @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.bne <= i0_dec.io.out.bne @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.beq <= i0_dec.io.out.beq @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.condbr <= i0_dec.io.out.condbr @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.unsign <= i0_dec.io.out.unsign @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.slt <= i0_dec.io.out.slt @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.srl <= i0_dec.io.out.srl @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.sra <= i0_dec.io.out.sra @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.sll <= i0_dec.io.out.sll @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.lxor <= i0_dec.io.out.lxor @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.lor <= i0_dec.io.out.lor @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.land <= i0_dec.io.out.land @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.sub <= i0_dec.io.out.sub @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.add <= i0_dec.io.out.add @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.lsu <= i0_dec.io.out.lsu @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.store <= i0_dec.io.out.store @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.load <= i0_dec.io.out.load @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.pc <= i0_dec.io.out.pc @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rd <= i0_dec.io.out.rd @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[el2_dec_decode_ctl.scala 394:12] + i0_dp_raw.alu <= i0_dec.io.out.alu @[el2_dec_decode_ctl.scala 394:12] + reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 396:45] + _T_279 <= io.lsu_idle_any @[el2_dec_decode_ctl.scala 396:45] + lsu_idle <= _T_279 @[el2_dec_decode_ctl.scala 396:11] + node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 399:73] + node _T_281 = and(leak1_i1_stall, _T_280) @[el2_dec_decode_ctl.scala 399:71] + node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[el2_dec_decode_ctl.scala 399:53] + leak1_i1_stall_in <= _T_282 @[el2_dec_decode_ctl.scala 399:21] + reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 400:56] + _T_283 <= leak1_i1_stall_in @[el2_dec_decode_ctl.scala 400:56] + leak1_i1_stall <= _T_283 @[el2_dec_decode_ctl.scala 400:21] + leak1_mode <= leak1_i1_stall @[el2_dec_decode_ctl.scala 401:14] + node _T_284 = and(io.dec_i0_decode_d, leak1_i1_stall) @[el2_dec_decode_ctl.scala 402:45] + node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 402:83] + node _T_286 = and(leak1_i0_stall, _T_285) @[el2_dec_decode_ctl.scala 402:81] + node _T_287 = or(_T_284, _T_286) @[el2_dec_decode_ctl.scala 402:63] + leak1_i0_stall_in <= _T_287 @[el2_dec_decode_ctl.scala 402:21] + reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 403:56] + _T_288 <= leak1_i0_stall_in @[el2_dec_decode_ctl.scala 403:56] + leak1_i0_stall <= _T_288 @[el2_dec_decode_ctl.scala 403:21] + node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 407:29] + node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 407:36] + node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 407:46] + node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 407:53] + node _T_293 = cat(_T_291, _T_292) @[Cat.scala 29:58] + node _T_294 = cat(_T_289, _T_290) @[Cat.scala 29:58] + node i0_pcall_imm = cat(_T_294, _T_293) @[Cat.scala 29:58] + node _T_295 = bits(i0_pcall_imm, 11, 11) @[el2_dec_decode_ctl.scala 408:46] + node _T_296 = bits(_T_295, 0, 0) @[el2_dec_decode_ctl.scala 408:51] + node _T_297 = bits(i0_pcall_imm, 19, 12) @[el2_dec_decode_ctl.scala 408:71] + node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[el2_dec_decode_ctl.scala 408:79] + node _T_299 = bits(i0_pcall_imm, 19, 12) @[el2_dec_decode_ctl.scala 408:104] + node _T_300 = eq(_T_299, UInt<8>("h00")) @[el2_dec_decode_ctl.scala 408:112] + node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[el2_dec_decode_ctl.scala 408:33] + node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 409:47] + node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 409:76] + node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 409:98] + node _T_304 = or(_T_302, _T_303) @[el2_dec_decode_ctl.scala 409:89] + node i0_pcall_case = and(_T_301, _T_304) @[el2_dec_decode_ctl.scala 409:65] + node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 410:47] + node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 410:76] + node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 410:98] + node _T_308 = or(_T_306, _T_307) @[el2_dec_decode_ctl.scala 410:89] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 410:67] + node i0_pja_case = and(_T_305, _T_309) @[el2_dec_decode_ctl.scala 410:65] + node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 411:38] + i0_pcall_raw <= _T_310 @[el2_dec_decode_ctl.scala 411:20] + node _T_311 = and(i0_dp.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 412:38] + i0_pcall <= _T_311 @[el2_dec_decode_ctl.scala 412:20] + node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 413:38] + i0_pja_raw <= _T_312 @[el2_dec_decode_ctl.scala 413:20] + node _T_313 = and(i0_dp.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 414:38] + i0_pja <= _T_313 @[el2_dec_decode_ctl.scala 414:20] + node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[el2_dec_decode_ctl.scala 415:41] + node _T_315 = bits(_T_314, 0, 0) @[el2_dec_decode_ctl.scala 415:55] + node _T_316 = bits(i0_pcall_imm, 11, 0) @[el2_dec_decode_ctl.scala 415:75] + node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 415:90] + node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[el2_dec_decode_ctl.scala 415:97] + node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[el2_dec_decode_ctl.scala 415:103] + node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[el2_dec_decode_ctl.scala 415:113] node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58] node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58] node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58] - node _T_324 = mux(_T_315, _T_316, _T_323) @[el2_dec_decode_ctl.scala 419:26] - i0_br_offset <= _T_324 @[el2_dec_decode_ctl.scala 419:20] - node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[el2_dec_decode_ctl.scala 421:37] - node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 421:65] - node _T_327 = and(_T_325, _T_326) @[el2_dec_decode_ctl.scala 421:55] - node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 421:89] - node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 421:111] - node _T_330 = or(_T_328, _T_329) @[el2_dec_decode_ctl.scala 421:101] - node i0_pret_case = and(_T_327, _T_330) @[el2_dec_decode_ctl.scala 421:79] - node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 422:32] - i0_pret_raw <= _T_331 @[el2_dec_decode_ctl.scala 422:15] - node _T_332 = and(i0_dp.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 423:32] - i0_pret <= _T_332 @[el2_dec_decode_ctl.scala 423:15] - node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:35] - node _T_334 = and(i0_dp.jal, _T_333) @[el2_dec_decode_ctl.scala 424:32] - node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:52] - node _T_336 = and(_T_334, _T_335) @[el2_dec_decode_ctl.scala 424:50] - node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:67] - node _T_338 = and(_T_336, _T_337) @[el2_dec_decode_ctl.scala 424:65] - i0_jal <= _T_338 @[el2_dec_decode_ctl.scala 424:15] - io.div_p.valid <= div_decode_d @[el2_dec_decode_ctl.scala 427:21] - io.div_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 428:26] - io.div_p.bits.rem <= i0_dp.rem @[el2_dec_decode_ctl.scala 429:26] - io.mul_p.valid <= mul_decode_d @[el2_dec_decode_ctl.scala 431:21] - io.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[el2_dec_decode_ctl.scala 432:26] - io.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[el2_dec_decode_ctl.scala 433:26] - io.mul_p.bits.low <= i0_dp.low @[el2_dec_decode_ctl.scala 434:26] - reg _T_339 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 436:58] - _T_339 <= io.dec_tlu_flush_extint @[el2_dec_decode_ctl.scala 436:58] - io.dec_extint_stall <= _T_339 @[el2_dec_decode_ctl.scala 436:23] - wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.dma <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.dword <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.bits.fast_int <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - _T_340.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] - io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.dma <= _T_340.bits.dma @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.unsign <= _T_340.bits.unsign @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.store <= _T_340.bits.store @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.load <= _T_340.bits.load @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.dword <= _T_340.bits.dword @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.word <= _T_340.bits.word @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.half <= _T_340.bits.half @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.by <= _T_340.bits.by @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[el2_dec_decode_ctl.scala 438:12] - io.lsu_p.valid <= _T_340.valid @[el2_dec_decode_ctl.scala 438:12] - when io.dec_extint_stall : @[el2_dec_decode_ctl.scala 439:29] - io.lsu_p.bits.load <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 440:29] - io.lsu_p.bits.word <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 441:29] - io.lsu_p.bits.fast_int <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 442:29] - io.lsu_p.valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 443:24] - skip @[el2_dec_decode_ctl.scala 439:29] - else : @[el2_dec_decode_ctl.scala 444:15] - io.lsu_p.valid <= lsu_decode_d @[el2_dec_decode_ctl.scala 445:35] - io.lsu_p.bits.load <= i0_dp.load @[el2_dec_decode_ctl.scala 446:40] - io.lsu_p.bits.store <= i0_dp.store @[el2_dec_decode_ctl.scala 447:40] - io.lsu_p.bits.by <= i0_dp.by @[el2_dec_decode_ctl.scala 448:40] - io.lsu_p.bits.half <= i0_dp.half @[el2_dec_decode_ctl.scala 449:40] - io.lsu_p.bits.word <= i0_dp.word @[el2_dec_decode_ctl.scala 450:40] - io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[el2_dec_decode_ctl.scala 451:40] - io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[el2_dec_decode_ctl.scala 452:40] - io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[el2_dec_decode_ctl.scala 453:40] - io.lsu_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 454:40] - skip @[el2_dec_decode_ctl.scala 444:15] - io.dec_csr_ren_d <= i0_dp.csr_read @[el2_dec_decode_ctl.scala 458:21] - node _T_341 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 459:56] - node _T_342 = and(i0_dp.csr_read, _T_341) @[el2_dec_decode_ctl.scala 459:36] - csr_read <= _T_342 @[el2_dec_decode_ctl.scala 459:18] - node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 461:42] - node i0_csr_write = and(i0_dp.csr_write, _T_343) @[el2_dec_decode_ctl.scala 461:40] - node _T_344 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 462:61] - node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[el2_dec_decode_ctl.scala 462:41] - node _T_345 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 463:59] - node csr_set_d = and(i0_dp.csr_set, _T_345) @[el2_dec_decode_ctl.scala 463:39] - node _T_346 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 464:59] - node csr_write_d = and(i0_csr_write, _T_346) @[el2_dec_decode_ctl.scala 464:39] - node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 466:41] - node _T_348 = and(i0_csr_write, _T_347) @[el2_dec_decode_ctl.scala 466:39] - i0_csr_write_only_d <= _T_348 @[el2_dec_decode_ctl.scala 466:23] - node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[el2_dec_decode_ctl.scala 467:42] - node _T_350 = or(_T_349, i0_csr_write) @[el2_dec_decode_ctl.scala 467:58] - io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 467:24] - node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 470:30] - io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 470:24] - io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 471:23] - node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 475:39] - node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 475:53] - node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 475:51] - io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 475:20] - node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 478:50] - node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 478:85] - node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 478:64] - node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 478:100] - node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 478:118] - node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 478:132] - node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 478:130] - io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 478:27] - reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 480:52] - csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 480:52] - reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 481:51] - csr_clr_x <= csr_clr_d @[el2_dec_decode_ctl.scala 481:51] - reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 482:51] - csr_set_x <= csr_set_d @[el2_dec_decode_ctl.scala 482:51] - reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 483:53] - csr_write_x <= csr_write_d @[el2_dec_decode_ctl.scala 483:53] - reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 484:51] - csr_imm_x <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 484:51] - node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 487:27] - node _T_363 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 487:48] - inst rvclkhdr of rvclkhdr_662 @[el2_lib.scala 508:23] - rvclkhdr.clock <= clock - rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_363 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg csrimm_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - csrimm_x <= _T_362 @[el2_lib.scala 514:16] - node _T_364 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 488:62] - inst rvclkhdr_1 of rvclkhdr_663 @[el2_lib.scala 508:23] + node _T_324 = mux(_T_315, _T_316, _T_323) @[el2_dec_decode_ctl.scala 415:26] + i0_br_offset <= _T_324 @[el2_dec_decode_ctl.scala 415:20] + node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[el2_dec_decode_ctl.scala 417:37] + node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 417:65] + node _T_327 = and(_T_325, _T_326) @[el2_dec_decode_ctl.scala 417:55] + node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 417:89] + node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 417:111] + node _T_330 = or(_T_328, _T_329) @[el2_dec_decode_ctl.scala 417:101] + node i0_pret_case = and(_T_327, _T_330) @[el2_dec_decode_ctl.scala 417:79] + node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 418:32] + i0_pret_raw <= _T_331 @[el2_dec_decode_ctl.scala 418:15] + node _T_332 = and(i0_dp.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 419:32] + i0_pret <= _T_332 @[el2_dec_decode_ctl.scala 419:15] + node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 420:35] + node _T_334 = and(i0_dp.jal, _T_333) @[el2_dec_decode_ctl.scala 420:32] + node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 420:52] + node _T_336 = and(_T_334, _T_335) @[el2_dec_decode_ctl.scala 420:50] + node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 420:67] + node _T_338 = and(_T_336, _T_337) @[el2_dec_decode_ctl.scala 420:65] + i0_jal <= _T_338 @[el2_dec_decode_ctl.scala 420:15] + io.div_p.valid <= div_decode_d @[el2_dec_decode_ctl.scala 423:21] + io.div_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 424:26] + io.div_p.bits.rem <= i0_dp.rem @[el2_dec_decode_ctl.scala 425:26] + io.mul_p.valid <= mul_decode_d @[el2_dec_decode_ctl.scala 427:21] + io.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[el2_dec_decode_ctl.scala 428:26] + io.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[el2_dec_decode_ctl.scala 429:26] + io.mul_p.bits.low <= i0_dp.low @[el2_dec_decode_ctl.scala 430:26] + reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 432:58] + _T_339 <= io.dec_tlu_flush_extint @[el2_dec_decode_ctl.scala 432:58] + io.dec_extint_stall <= _T_339 @[el2_dec_decode_ctl.scala 432:23] + wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.dma <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.dword <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.bits.fast_int <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + _T_340.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 434:27] + io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.dma <= _T_340.bits.dma @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.unsign <= _T_340.bits.unsign @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.store <= _T_340.bits.store @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.load <= _T_340.bits.load @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.dword <= _T_340.bits.dword @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.word <= _T_340.bits.word @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.half <= _T_340.bits.half @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.by <= _T_340.bits.by @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[el2_dec_decode_ctl.scala 434:12] + io.lsu_p.valid <= _T_340.valid @[el2_dec_decode_ctl.scala 434:12] + when io.dec_extint_stall : @[el2_dec_decode_ctl.scala 435:29] + io.lsu_p.bits.load <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 436:29] + io.lsu_p.bits.word <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 437:29] + io.lsu_p.bits.fast_int <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 438:29] + io.lsu_p.valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 439:24] + skip @[el2_dec_decode_ctl.scala 435:29] + else : @[el2_dec_decode_ctl.scala 440:15] + io.lsu_p.valid <= lsu_decode_d @[el2_dec_decode_ctl.scala 441:35] + io.lsu_p.bits.load <= i0_dp.load @[el2_dec_decode_ctl.scala 442:40] + io.lsu_p.bits.store <= i0_dp.store @[el2_dec_decode_ctl.scala 443:40] + io.lsu_p.bits.by <= i0_dp.by @[el2_dec_decode_ctl.scala 444:40] + io.lsu_p.bits.half <= i0_dp.half @[el2_dec_decode_ctl.scala 445:40] + io.lsu_p.bits.word <= i0_dp.word @[el2_dec_decode_ctl.scala 446:40] + io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[el2_dec_decode_ctl.scala 447:40] + io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[el2_dec_decode_ctl.scala 448:40] + io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[el2_dec_decode_ctl.scala 449:40] + io.lsu_p.bits.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 450:40] + skip @[el2_dec_decode_ctl.scala 440:15] + io.dec_csr_ren_d <= i0_dp.csr_read @[el2_dec_decode_ctl.scala 454:21] + node _T_341 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 455:56] + node _T_342 = and(i0_dp.csr_read, _T_341) @[el2_dec_decode_ctl.scala 455:36] + csr_read <= _T_342 @[el2_dec_decode_ctl.scala 455:18] + node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 457:42] + node i0_csr_write = and(i0_dp.csr_write, _T_343) @[el2_dec_decode_ctl.scala 457:40] + node _T_344 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 458:61] + node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[el2_dec_decode_ctl.scala 458:41] + node _T_345 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 459:59] + node csr_set_d = and(i0_dp.csr_set, _T_345) @[el2_dec_decode_ctl.scala 459:39] + node _T_346 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 460:59] + node csr_write_d = and(i0_csr_write, _T_346) @[el2_dec_decode_ctl.scala 460:39] + node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 462:41] + node _T_348 = and(i0_csr_write, _T_347) @[el2_dec_decode_ctl.scala 462:39] + i0_csr_write_only_d <= _T_348 @[el2_dec_decode_ctl.scala 462:23] + node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[el2_dec_decode_ctl.scala 463:42] + node _T_350 = or(_T_349, i0_csr_write) @[el2_dec_decode_ctl.scala 463:58] + io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24] + node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30] + io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24] + io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 467:23] + node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 471:34] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:50] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:48] + io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20] + node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:45] + node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:75] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:59] + node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 474:90] + node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 474:103] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:119] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:117] + io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27] + reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52] + csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52] + reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 477:51] + csr_clr_x <= csr_clr_d @[el2_dec_decode_ctl.scala 477:51] + reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 478:51] + csr_set_x <= csr_set_d @[el2_dec_decode_ctl.scala 478:51] + reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 479:53] + csr_write_x <= csr_write_d @[el2_dec_decode_ctl.scala 479:53] + reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 480:51] + csr_imm_x <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 480:51] + node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 483:27] + node _T_363 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 483:48] + inst rvclkhdr_1 of rvclkhdr_662 @[el2_lib.scala 508:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_364 @[el2_lib.scala 511:17] + rvclkhdr_1.io.en <= _T_363 @[el2_lib.scala 511:17] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg csr_rddata_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + reg csrimm_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + csrimm_x <= _T_362 @[el2_lib.scala 514:16] + node _T_364 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 484:62] + inst rvclkhdr_2 of rvclkhdr_663 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_364 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg csr_rddata_x : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] csr_rddata_x <= io.dec_csr_rddata_d @[el2_lib.scala 514:16] - node _T_365 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 491:15] + node _T_365 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 487:15] wire _T_366 : UInt<1>[27] @[el2_lib.scala 162:48] _T_366[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_366[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -67929,18 +67912,18 @@ circuit el2_swerv : node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58] node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58] node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58] - node _T_393 = bits(csrimm_x, 4, 0) @[el2_dec_decode_ctl.scala 491:53] + node _T_393 = bits(csrimm_x, 4, 0) @[el2_dec_decode_ctl.scala 487:53] node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58] - node _T_395 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 492:16] - node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 492:5] + node _T_395 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 488:16] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 488:5] node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72] node _T_398 = mux(_T_396, io.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72] node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72] wire csr_mask_x : UInt<32> @[Mux.scala 27:72] csr_mask_x <= _T_399 @[Mux.scala 27:72] - node _T_400 = not(csr_mask_x) @[el2_dec_decode_ctl.scala 495:38] - node _T_401 = and(csr_rddata_x, _T_400) @[el2_dec_decode_ctl.scala 495:35] - node _T_402 = or(csr_rddata_x, csr_mask_x) @[el2_dec_decode_ctl.scala 496:35] + node _T_400 = not(csr_mask_x) @[el2_dec_decode_ctl.scala 491:38] + node _T_401 = and(csr_rddata_x, _T_400) @[el2_dec_decode_ctl.scala 491:35] + node _T_402 = or(csr_rddata_x, csr_mask_x) @[el2_dec_decode_ctl.scala 492:35] node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72] node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72] node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -67948,74 +67931,74 @@ circuit el2_swerv : node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72] wire write_csr_data_x : UInt @[Mux.scala 27:72] write_csr_data_x <= _T_407 @[Mux.scala 27:72] - node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 499:49] - node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[el2_dec_decode_ctl.scala 499:47] - node _T_410 = eq(write_csr_data, UInt<31>("h00")) @[el2_dec_decode_ctl.scala 499:109] - node _T_411 = and(pause_stall, _T_410) @[el2_dec_decode_ctl.scala 499:91] - node clear_pause = or(_T_409, _T_411) @[el2_dec_decode_ctl.scala 499:76] - node _T_412 = or(io.dec_tlu_wr_pause_r, pause_stall) @[el2_dec_decode_ctl.scala 500:44] - node _T_413 = eq(clear_pause, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 500:61] - node _T_414 = and(_T_412, _T_413) @[el2_dec_decode_ctl.scala 500:59] - pause_state_in <= _T_414 @[el2_dec_decode_ctl.scala 500:18] - reg _T_415 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 501:50] - _T_415 <= pause_state_in @[el2_dec_decode_ctl.scala 501:50] - pause_stall <= _T_415 @[el2_dec_decode_ctl.scala 501:15] - io.dec_pause_state <= pause_stall @[el2_dec_decode_ctl.scala 502:22] - reg _T_416 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 503:29] - _T_416 <= io.dec_tlu_wr_pause_r @[el2_dec_decode_ctl.scala 503:29] - tlu_wr_pause_r1 <= _T_416 @[el2_dec_decode_ctl.scala 503:19] - reg _T_417 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 504:29] - _T_417 <= tlu_wr_pause_r1 @[el2_dec_decode_ctl.scala 504:29] - tlu_wr_pause_r2 <= _T_417 @[el2_dec_decode_ctl.scala 504:19] - node _T_418 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 506:44] - node _T_419 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 506:64] - node _T_420 = and(_T_418, _T_419) @[el2_dec_decode_ctl.scala 506:61] - node _T_421 = and(pause_stall, _T_420) @[el2_dec_decode_ctl.scala 506:41] - io.dec_pause_state_cg <= _T_421 @[el2_dec_decode_ctl.scala 506:25] - node _T_422 = sub(write_csr_data, UInt<32>("h01")) @[el2_dec_decode_ctl.scala 509:59] - node _T_423 = tail(_T_422, 1) @[el2_dec_decode_ctl.scala 509:59] - node _T_424 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[el2_dec_decode_ctl.scala 510:8] - node write_csr_data_in = mux(pause_stall, _T_423, _T_424) @[el2_dec_decode_ctl.scala 509:30] - node _T_425 = or(csr_clr_x, csr_set_x) @[el2_dec_decode_ctl.scala 511:34] - node _T_426 = or(_T_425, csr_write_x) @[el2_dec_decode_ctl.scala 511:46] - node _T_427 = and(_T_426, csr_read_x) @[el2_dec_decode_ctl.scala 511:61] - node _T_428 = or(_T_427, io.dec_tlu_wr_pause_r) @[el2_dec_decode_ctl.scala 511:75] - node csr_data_wen = or(_T_428, pause_stall) @[el2_dec_decode_ctl.scala 511:99] - inst rvclkhdr_2 of rvclkhdr_664 @[el2_lib.scala 508:23] - rvclkhdr_2.clock <= clock - rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= csr_data_wen @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_429 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 495:49] + node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[el2_dec_decode_ctl.scala 495:47] + node _T_410 = eq(write_csr_data, UInt<31>("h00")) @[el2_dec_decode_ctl.scala 495:109] + node _T_411 = and(pause_stall, _T_410) @[el2_dec_decode_ctl.scala 495:91] + node clear_pause = or(_T_409, _T_411) @[el2_dec_decode_ctl.scala 495:76] + node _T_412 = or(io.dec_tlu_wr_pause_r, pause_stall) @[el2_dec_decode_ctl.scala 496:44] + node _T_413 = eq(clear_pause, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 496:61] + node _T_414 = and(_T_412, _T_413) @[el2_dec_decode_ctl.scala 496:59] + pause_state_in <= _T_414 @[el2_dec_decode_ctl.scala 496:18] + reg _T_415 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 497:50] + _T_415 <= pause_state_in @[el2_dec_decode_ctl.scala 497:50] + pause_stall <= _T_415 @[el2_dec_decode_ctl.scala 497:15] + io.dec_pause_state <= pause_stall @[el2_dec_decode_ctl.scala 498:22] + reg _T_416 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 499:55] + _T_416 <= io.dec_tlu_wr_pause_r @[el2_dec_decode_ctl.scala 499:55] + tlu_wr_pause_r1 <= _T_416 @[el2_dec_decode_ctl.scala 499:19] + reg _T_417 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 500:55] + _T_417 <= tlu_wr_pause_r1 @[el2_dec_decode_ctl.scala 500:55] + tlu_wr_pause_r2 <= _T_417 @[el2_dec_decode_ctl.scala 500:19] + node _T_418 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 502:44] + node _T_419 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 502:64] + node _T_420 = and(_T_418, _T_419) @[el2_dec_decode_ctl.scala 502:61] + node _T_421 = and(pause_stall, _T_420) @[el2_dec_decode_ctl.scala 502:41] + io.dec_pause_state_cg <= _T_421 @[el2_dec_decode_ctl.scala 502:25] + node _T_422 = sub(write_csr_data, UInt<32>("h01")) @[el2_dec_decode_ctl.scala 505:59] + node _T_423 = tail(_T_422, 1) @[el2_dec_decode_ctl.scala 505:59] + node _T_424 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[el2_dec_decode_ctl.scala 506:8] + node write_csr_data_in = mux(pause_stall, _T_423, _T_424) @[el2_dec_decode_ctl.scala 505:30] + node _T_425 = or(csr_clr_x, csr_set_x) @[el2_dec_decode_ctl.scala 507:34] + node _T_426 = or(_T_425, csr_write_x) @[el2_dec_decode_ctl.scala 507:46] + node _T_427 = and(_T_426, csr_read_x) @[el2_dec_decode_ctl.scala 507:61] + node _T_428 = or(_T_427, io.dec_tlu_wr_pause_r) @[el2_dec_decode_ctl.scala 507:75] + node csr_data_wen = or(_T_428, pause_stall) @[el2_dec_decode_ctl.scala 507:99] + inst rvclkhdr_3 of rvclkhdr_664 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= csr_data_wen @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_429 <= write_csr_data_in @[el2_lib.scala 514:16] - write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 512:18] - node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 518:49] - node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 518:30] - io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 518:24] - node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 520:43] - node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 520:63] - node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 522:67] - node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 522:48] - node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 523:67] - node debug_fence_raw = and(io.dec_debug_fence_d, _T_434) @[el2_dec_decode_ctl.scala 523:48] - node _T_435 = or(debug_fence_raw, debug_fence_i) @[el2_dec_decode_ctl.scala 524:40] - debug_fence <= _T_435 @[el2_dec_decode_ctl.scala 524:21] - node _T_436 = or(i0_dp.presync, io.dec_tlu_presync_d) @[el2_dec_decode_ctl.scala 527:34] - node _T_437 = or(_T_436, debug_fence_i) @[el2_dec_decode_ctl.scala 527:57] - node _T_438 = or(_T_437, debug_fence_raw) @[el2_dec_decode_ctl.scala 527:73] - node i0_presync = or(_T_438, io.dec_tlu_pipelining_disable) @[el2_dec_decode_ctl.scala 527:91] - node _T_439 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[el2_dec_decode_ctl.scala 530:36] - node _T_440 = or(_T_439, debug_fence_i) @[el2_dec_decode_ctl.scala 530:60] - node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 530:104] - node _T_442 = eq(_T_441, UInt<11>("h07c2")) @[el2_dec_decode_ctl.scala 530:112] - node _T_443 = and(i0_csr_write_only_d, _T_442) @[el2_dec_decode_ctl.scala 530:99] - node i0_postsync = or(_T_440, _T_443) @[el2_dec_decode_ctl.scala 530:76] - node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[el2_dec_decode_ctl.scala 532:34] - io.dec_csr_any_unq_d <= any_csr_d @[el2_dec_decode_ctl.scala 533:24] - node _T_444 = eq(any_csr_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 534:40] - node _T_445 = or(_T_444, io.dec_csr_legal_d) @[el2_dec_decode_ctl.scala 534:51] - node i0_legal = and(i0_dp.legal, _T_445) @[el2_dec_decode_ctl.scala 534:37] + write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18] + node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:44] + node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30] + io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24] + node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 516:38] + node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 516:53] + node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67] + node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48] + node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67] + node debug_fence_raw = and(io.dec_debug_fence_d, _T_434) @[el2_dec_decode_ctl.scala 519:48] + node _T_435 = or(debug_fence_raw, debug_fence_i) @[el2_dec_decode_ctl.scala 520:40] + debug_fence <= _T_435 @[el2_dec_decode_ctl.scala 520:21] + node _T_436 = or(i0_dp.presync, io.dec_tlu_presync_d) @[el2_dec_decode_ctl.scala 523:34] + node _T_437 = or(_T_436, debug_fence_i) @[el2_dec_decode_ctl.scala 523:57] + node _T_438 = or(_T_437, debug_fence_raw) @[el2_dec_decode_ctl.scala 523:73] + node i0_presync = or(_T_438, io.dec_tlu_pipelining_disable) @[el2_dec_decode_ctl.scala 523:91] + node _T_439 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[el2_dec_decode_ctl.scala 526:36] + node _T_440 = or(_T_439, debug_fence_i) @[el2_dec_decode_ctl.scala 526:60] + node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 526:104] + node _T_442 = eq(_T_441, UInt<11>("h07c2")) @[el2_dec_decode_ctl.scala 526:112] + node _T_443 = and(i0_csr_write_only_d, _T_442) @[el2_dec_decode_ctl.scala 526:99] + node i0_postsync = or(_T_440, _T_443) @[el2_dec_decode_ctl.scala 526:76] + node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[el2_dec_decode_ctl.scala 528:34] + io.dec_csr_any_unq_d <= any_csr_d @[el2_dec_decode_ctl.scala 529:24] + node _T_444 = eq(any_csr_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 530:40] + node _T_445 = or(_T_444, io.dec_csr_legal_d) @[el2_dec_decode_ctl.scala 530:51] + node i0_legal = and(i0_dp.legal, _T_445) @[el2_dec_decode_ctl.scala 530:37] wire _T_446 : UInt<1>[16] @[el2_lib.scala 162:48] _T_446[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_446[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68049,107 +68032,107 @@ circuit el2_swerv : node _T_460 = cat(_T_459, _T_446[14]) @[Cat.scala 29:58] node _T_461 = cat(_T_460, _T_446[15]) @[Cat.scala 29:58] node _T_462 = cat(_T_461, io.ifu_i0_cinst) @[Cat.scala 29:58] - node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_462) @[el2_dec_decode_ctl.scala 535:27] - node _T_463 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 538:49] - node shift_illegal = and(io.dec_i0_decode_d, _T_463) @[el2_dec_decode_ctl.scala 538:47] - node _T_464 = eq(illegal_lockout, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 539:44] - node illegal_inst_en = and(shift_illegal, _T_464) @[el2_dec_decode_ctl.scala 539:42] - inst rvclkhdr_3 of rvclkhdr_665 @[el2_lib.scala 508:23] - rvclkhdr_3.clock <= clock - rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= illegal_inst_en @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_465 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_462) @[el2_dec_decode_ctl.scala 531:27] + node _T_463 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 534:49] + node shift_illegal = and(io.dec_i0_decode_d, _T_463) @[el2_dec_decode_ctl.scala 534:47] + node _T_464 = eq(illegal_lockout, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 535:44] + node illegal_inst_en = and(shift_illegal, _T_464) @[el2_dec_decode_ctl.scala 535:42] + inst rvclkhdr_4 of rvclkhdr_665 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= illegal_inst_en @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_465 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_465 <= i0_inst_d @[el2_lib.scala 514:16] - io.dec_illegal_inst <= _T_465 @[el2_dec_decode_ctl.scala 540:23] - node _T_466 = or(shift_illegal, illegal_lockout) @[el2_dec_decode_ctl.scala 541:40] - node _T_467 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 541:61] - node _T_468 = and(_T_466, _T_467) @[el2_dec_decode_ctl.scala 541:59] - illegal_lockout_in <= _T_468 @[el2_dec_decode_ctl.scala 541:22] - reg _T_469 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 542:54] - _T_469 <= illegal_lockout_in @[el2_dec_decode_ctl.scala 542:54] - illegal_lockout <= _T_469 @[el2_dec_decode_ctl.scala 542:19] - node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[el2_dec_decode_ctl.scala 543:42] - node _T_470 = and(i0_dp.csr_read, prior_csr_write) @[el2_dec_decode_ctl.scala 545:40] - node _T_471 = or(_T_470, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 545:59] - node _T_472 = or(_T_471, pause_stall) @[el2_dec_decode_ctl.scala 545:81] - node _T_473 = or(_T_472, leak1_i0_stall) @[el2_dec_decode_ctl.scala 545:95] - node _T_474 = or(_T_473, io.dec_tlu_debug_stall) @[el2_dec_decode_ctl.scala 546:20] - node _T_475 = or(_T_474, postsync_stall) @[el2_dec_decode_ctl.scala 546:45] - node _T_476 = or(_T_475, presync_stall) @[el2_dec_decode_ctl.scala 546:62] - node _T_477 = or(i0_dp.fence, debug_fence) @[el2_dec_decode_ctl.scala 547:19] - node _T_478 = eq(lsu_idle, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 547:36] - node _T_479 = and(_T_477, _T_478) @[el2_dec_decode_ctl.scala 547:34] - node _T_480 = or(_T_476, _T_479) @[el2_dec_decode_ctl.scala 546:79] - node _T_481 = or(_T_480, i0_nonblock_load_stall) @[el2_dec_decode_ctl.scala 547:47] - node _T_482 = or(_T_481, i0_load_block_d) @[el2_dec_decode_ctl.scala 547:72] - node _T_483 = or(_T_482, i0_nonblock_div_stall) @[el2_dec_decode_ctl.scala 548:21] - node i0_block_raw_d = or(_T_483, i0_div_prior_div_stall) @[el2_dec_decode_ctl.scala 548:45] - node _T_484 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 550:65] - node i0_store_stall_d = and(i0_dp.store, _T_484) @[el2_dec_decode_ctl.scala 550:39] - node _T_485 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 551:63] - node i0_load_stall_d = and(i0_dp.load, _T_485) @[el2_dec_decode_ctl.scala 551:38] - node _T_486 = or(i0_block_raw_d, i0_store_stall_d) @[el2_dec_decode_ctl.scala 552:38] - node i0_block_d = or(_T_486, i0_load_stall_d) @[el2_dec_decode_ctl.scala 552:57] - node _T_487 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:46] - node _T_488 = and(io.dec_ib0_valid_d, _T_487) @[el2_dec_decode_ctl.scala 556:44] - node _T_489 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:63] - node _T_490 = and(_T_488, _T_489) @[el2_dec_decode_ctl.scala 556:61] - node _T_491 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:91] - node _T_492 = and(_T_490, _T_491) @[el2_dec_decode_ctl.scala 556:89] - io.dec_i0_decode_d <= _T_492 @[el2_dec_decode_ctl.scala 556:22] - node _T_493 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:46] - node _T_494 = and(io.dec_ib0_valid_d, _T_493) @[el2_dec_decode_ctl.scala 557:44] - node _T_495 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:63] - node _T_496 = and(_T_494, _T_495) @[el2_dec_decode_ctl.scala 557:61] - node _T_497 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:91] - node i0_exudecode_d = and(_T_496, _T_497) @[el2_dec_decode_ctl.scala 557:89] - node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[el2_dec_decode_ctl.scala 558:46] - io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 561:28] - node _T_498 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 562:51] - node _T_499 = and(io.dec_ib0_valid_d, _T_498) @[el2_dec_decode_ctl.scala 562:49] - io.dec_pmu_decode_stall <= _T_499 @[el2_dec_decode_ctl.scala 562:27] - node _T_500 = bits(postsync_stall, 0, 0) @[el2_dec_decode_ctl.scala 563:47] - io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 563:29] - node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 564:46] - io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 564:29] - node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 568:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 569:31] - node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 571:37] - presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 571:22] - reg _T_503 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 572:53] - _T_503 <= ps_stall_in @[el2_dec_decode_ctl.scala 572:53] - postsync_stall <= _T_503 @[el2_dec_decode_ctl.scala 572:18] - node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 574:56] - node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 574:54] - node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 574:39] - node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 574:88] - node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 574:69] - ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 574:15] - node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 576:50] - io.dec_i0_alu_decode_d <= _T_509 @[el2_dec_decode_ctl.scala 576:26] - node _T_510 = and(i0_legal_decode_d, i0_dp.lsu) @[el2_dec_decode_ctl.scala 578:40] - lsu_decode_d <= _T_510 @[el2_dec_decode_ctl.scala 578:16] - node _T_511 = and(i0_exulegal_decode_d, i0_dp.mul) @[el2_dec_decode_ctl.scala 579:40] - mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 579:16] - node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 580:40] - div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 580:16] - node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 582:45] - node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 582:43] - io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 582:29] - d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 585:26] - node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 586:40] - d_t.icaf <= _T_515 @[el2_dec_decode_ctl.scala 586:26] - node _T_516 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 587:50] - d_t.icaf_f1 <= _T_516 @[el2_dec_decode_ctl.scala 587:26] - d_t.icaf_type <= io.dec_i0_icaf_type_d @[el2_dec_decode_ctl.scala 588:26] - node _T_517 = or(i0_dp.fence_i, debug_fence_i) @[el2_dec_decode_ctl.scala 590:44] - node _T_518 = and(_T_517, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 590:61] - d_t.fence_i <= _T_518 @[el2_dec_decode_ctl.scala 590:26] - d_t.pmu_i0_br_unpred <= i0_br_unpred @[el2_dec_decode_ctl.scala 593:26] - d_t.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 594:26] - d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 595:26] + io.dec_illegal_inst <= _T_465 @[el2_dec_decode_ctl.scala 536:23] + node _T_466 = or(shift_illegal, illegal_lockout) @[el2_dec_decode_ctl.scala 537:40] + node _T_467 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 537:61] + node _T_468 = and(_T_466, _T_467) @[el2_dec_decode_ctl.scala 537:59] + illegal_lockout_in <= _T_468 @[el2_dec_decode_ctl.scala 537:22] + reg _T_469 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 538:54] + _T_469 <= illegal_lockout_in @[el2_dec_decode_ctl.scala 538:54] + illegal_lockout <= _T_469 @[el2_dec_decode_ctl.scala 538:19] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[el2_dec_decode_ctl.scala 539:42] + node _T_470 = and(i0_dp.csr_read, prior_csr_write) @[el2_dec_decode_ctl.scala 541:40] + node _T_471 = or(_T_470, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 541:59] + node _T_472 = or(_T_471, pause_stall) @[el2_dec_decode_ctl.scala 541:81] + node _T_473 = or(_T_472, leak1_i0_stall) @[el2_dec_decode_ctl.scala 541:95] + node _T_474 = or(_T_473, io.dec_tlu_debug_stall) @[el2_dec_decode_ctl.scala 542:20] + node _T_475 = or(_T_474, postsync_stall) @[el2_dec_decode_ctl.scala 542:45] + node _T_476 = or(_T_475, presync_stall) @[el2_dec_decode_ctl.scala 542:62] + node _T_477 = or(i0_dp.fence, debug_fence) @[el2_dec_decode_ctl.scala 543:19] + node _T_478 = eq(lsu_idle, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 543:36] + node _T_479 = and(_T_477, _T_478) @[el2_dec_decode_ctl.scala 543:34] + node _T_480 = or(_T_476, _T_479) @[el2_dec_decode_ctl.scala 542:79] + node _T_481 = or(_T_480, i0_nonblock_load_stall) @[el2_dec_decode_ctl.scala 543:47] + node _T_482 = or(_T_481, i0_load_block_d) @[el2_dec_decode_ctl.scala 543:72] + node _T_483 = or(_T_482, i0_nonblock_div_stall) @[el2_dec_decode_ctl.scala 544:21] + node i0_block_raw_d = or(_T_483, i0_div_prior_div_stall) @[el2_dec_decode_ctl.scala 544:45] + node _T_484 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 546:65] + node i0_store_stall_d = and(i0_dp.store, _T_484) @[el2_dec_decode_ctl.scala 546:39] + node _T_485 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 547:63] + node i0_load_stall_d = and(i0_dp.load, _T_485) @[el2_dec_decode_ctl.scala 547:38] + node _T_486 = or(i0_block_raw_d, i0_store_stall_d) @[el2_dec_decode_ctl.scala 548:38] + node i0_block_d = or(_T_486, i0_load_stall_d) @[el2_dec_decode_ctl.scala 548:57] + node _T_487 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 552:46] + node _T_488 = and(io.dec_ib0_valid_d, _T_487) @[el2_dec_decode_ctl.scala 552:44] + node _T_489 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 552:63] + node _T_490 = and(_T_488, _T_489) @[el2_dec_decode_ctl.scala 552:61] + node _T_491 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 552:91] + node _T_492 = and(_T_490, _T_491) @[el2_dec_decode_ctl.scala 552:89] + io.dec_i0_decode_d <= _T_492 @[el2_dec_decode_ctl.scala 552:22] + node _T_493 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 553:46] + node _T_494 = and(io.dec_ib0_valid_d, _T_493) @[el2_dec_decode_ctl.scala 553:44] + node _T_495 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 553:63] + node _T_496 = and(_T_494, _T_495) @[el2_dec_decode_ctl.scala 553:61] + node _T_497 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 553:91] + node i0_exudecode_d = and(_T_496, _T_497) @[el2_dec_decode_ctl.scala 553:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[el2_dec_decode_ctl.scala 554:46] + io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 557:28] + node _T_498 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 558:51] + node _T_499 = and(io.dec_ib0_valid_d, _T_498) @[el2_dec_decode_ctl.scala 558:49] + io.dec_pmu_decode_stall <= _T_499 @[el2_dec_decode_ctl.scala 558:27] + node _T_500 = bits(postsync_stall, 0, 0) @[el2_dec_decode_ctl.scala 559:47] + io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29] + node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46] + io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29] + node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 564:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] + node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37] + presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22] + reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53] + _T_503 <= ps_stall_in @[el2_dec_decode_ctl.scala 568:53] + postsync_stall <= _T_503 @[el2_dec_decode_ctl.scala 568:18] + node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56] + node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54] + node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39] + node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 570:88] + node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69] + ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15] + node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50] + io.dec_i0_alu_decode_d <= _T_509 @[el2_dec_decode_ctl.scala 572:26] + node _T_510 = and(i0_legal_decode_d, i0_dp.lsu) @[el2_dec_decode_ctl.scala 574:40] + lsu_decode_d <= _T_510 @[el2_dec_decode_ctl.scala 574:16] + node _T_511 = and(i0_exulegal_decode_d, i0_dp.mul) @[el2_dec_decode_ctl.scala 575:40] + mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16] + node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40] + div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:47] + node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 578:45] + io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29] + d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26] + node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40] + d_t.icaf <= _T_515 @[el2_dec_decode_ctl.scala 582:26] + node _T_516 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 583:50] + d_t.icaf_f1 <= _T_516 @[el2_dec_decode_ctl.scala 583:26] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[el2_dec_decode_ctl.scala 584:26] + node _T_517 = or(i0_dp.fence_i, debug_fence_i) @[el2_dec_decode_ctl.scala 586:44] + node _T_518 = and(_T_517, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 586:61] + d_t.fence_i <= _T_518 @[el2_dec_decode_ctl.scala 586:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[el2_dec_decode_ctl.scala 589:26] + d_t.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 590:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 591:26] wire _T_519 : UInt<1>[4] @[el2_lib.scala 162:48] _T_519[0] <= io.dec_i0_decode_d @[el2_lib.scala 162:48] _T_519[1] <= io.dec_i0_decode_d @[el2_lib.scala 162:48] @@ -68158,15 +68141,15 @@ circuit el2_swerv : node _T_520 = cat(_T_519[0], _T_519[1]) @[Cat.scala 29:58] node _T_521 = cat(_T_520, _T_519[2]) @[Cat.scala 29:58] node _T_522 = cat(_T_521, _T_519[3]) @[Cat.scala 29:58] - node _T_523 = and(io.dec_i0_trigger_match_d, _T_522) @[el2_dec_decode_ctl.scala 597:56] - d_t.i0trigger <= _T_523 @[el2_dec_decode_ctl.scala 597:26] - node _T_524 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 600:33] - inst rvclkhdr_4 of rvclkhdr_666 @[el2_lib.scala 518:23] - rvclkhdr_4.clock <= clock - rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_4.io.en <= _T_524 @[el2_lib.scala 521:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + node _T_523 = and(io.dec_i0_trigger_match_d, _T_522) @[el2_dec_decode_ctl.scala 593:56] + d_t.i0trigger <= _T_523 @[el2_dec_decode_ctl.scala 593:26] + node _T_524 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 596:33] + inst rvclkhdr_5 of rvclkhdr_666 @[el2_lib.scala 518:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_5.io.en <= _T_524 @[el2_lib.scala 521:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] wire _T_525 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33] _T_525.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_525.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33] @@ -68178,7 +68161,7 @@ circuit el2_swerv : _T_525.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_525.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_525.legal <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_526 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_4.io.l1clk with : (reset => (reset, _T_525)) @[el2_lib.scala 524:16] + reg _T_526 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_525)) @[el2_lib.scala 524:16] _T_526.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[el2_lib.scala 524:16] _T_526.pmu_divide <= d_t.pmu_divide @[el2_lib.scala 524:16] _T_526.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[el2_lib.scala 524:16] @@ -68189,26 +68172,26 @@ circuit el2_swerv : _T_526.icaf_f1 <= d_t.icaf_f1 @[el2_lib.scala 524:16] _T_526.icaf <= d_t.icaf @[el2_lib.scala 524:16] _T_526.legal <= d_t.legal @[el2_lib.scala 524:16] - x_t.pmu_lsu_misaligned <= _T_526.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 600:7] - x_t.pmu_divide <= _T_526.pmu_divide @[el2_dec_decode_ctl.scala 600:7] - x_t.pmu_i0_br_unpred <= _T_526.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 600:7] - x_t.pmu_i0_itype <= _T_526.pmu_i0_itype @[el2_dec_decode_ctl.scala 600:7] - x_t.i0trigger <= _T_526.i0trigger @[el2_dec_decode_ctl.scala 600:7] - x_t.fence_i <= _T_526.fence_i @[el2_dec_decode_ctl.scala 600:7] - x_t.icaf_type <= _T_526.icaf_type @[el2_dec_decode_ctl.scala 600:7] - x_t.icaf_f1 <= _T_526.icaf_f1 @[el2_dec_decode_ctl.scala 600:7] - x_t.icaf <= _T_526.icaf @[el2_dec_decode_ctl.scala 600:7] - x_t.legal <= _T_526.legal @[el2_dec_decode_ctl.scala 600:7] - x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 602:10] - x_t_in.pmu_divide <= x_t.pmu_divide @[el2_dec_decode_ctl.scala 602:10] - x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 602:10] - x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 602:10] - x_t_in.i0trigger <= x_t.i0trigger @[el2_dec_decode_ctl.scala 602:10] - x_t_in.fence_i <= x_t.fence_i @[el2_dec_decode_ctl.scala 602:10] - x_t_in.icaf_type <= x_t.icaf_type @[el2_dec_decode_ctl.scala 602:10] - x_t_in.icaf_f1 <= x_t.icaf_f1 @[el2_dec_decode_ctl.scala 602:10] - x_t_in.icaf <= x_t.icaf @[el2_dec_decode_ctl.scala 602:10] - x_t_in.legal <= x_t.legal @[el2_dec_decode_ctl.scala 602:10] + x_t.pmu_lsu_misaligned <= _T_526.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 596:7] + x_t.pmu_divide <= _T_526.pmu_divide @[el2_dec_decode_ctl.scala 596:7] + x_t.pmu_i0_br_unpred <= _T_526.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 596:7] + x_t.pmu_i0_itype <= _T_526.pmu_i0_itype @[el2_dec_decode_ctl.scala 596:7] + x_t.i0trigger <= _T_526.i0trigger @[el2_dec_decode_ctl.scala 596:7] + x_t.fence_i <= _T_526.fence_i @[el2_dec_decode_ctl.scala 596:7] + x_t.icaf_type <= _T_526.icaf_type @[el2_dec_decode_ctl.scala 596:7] + x_t.icaf_f1 <= _T_526.icaf_f1 @[el2_dec_decode_ctl.scala 596:7] + x_t.icaf <= _T_526.icaf @[el2_dec_decode_ctl.scala 596:7] + x_t.legal <= _T_526.legal @[el2_dec_decode_ctl.scala 596:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 598:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[el2_dec_decode_ctl.scala 598:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 598:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 598:10] + x_t_in.i0trigger <= x_t.i0trigger @[el2_dec_decode_ctl.scala 598:10] + x_t_in.fence_i <= x_t.fence_i @[el2_dec_decode_ctl.scala 598:10] + x_t_in.icaf_type <= x_t.icaf_type @[el2_dec_decode_ctl.scala 598:10] + x_t_in.icaf_f1 <= x_t.icaf_f1 @[el2_dec_decode_ctl.scala 598:10] + x_t_in.icaf <= x_t.icaf @[el2_dec_decode_ctl.scala 598:10] + x_t_in.legal <= x_t.legal @[el2_dec_decode_ctl.scala 598:10] wire _T_527 : UInt<1>[4] @[el2_lib.scala 162:48] _T_527[0] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48] _T_527[1] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48] @@ -68217,16 +68200,16 @@ circuit el2_swerv : node _T_528 = cat(_T_527[0], _T_527[1]) @[Cat.scala 29:58] node _T_529 = cat(_T_528, _T_527[2]) @[Cat.scala 29:58] node _T_530 = cat(_T_529, _T_527[3]) @[Cat.scala 29:58] - node _T_531 = not(_T_530) @[el2_dec_decode_ctl.scala 603:39] - node _T_532 = and(x_t.i0trigger, _T_531) @[el2_dec_decode_ctl.scala 603:37] - x_t_in.i0trigger <= _T_532 @[el2_dec_decode_ctl.scala 603:20] - node _T_533 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 605:36] - inst rvclkhdr_5 of rvclkhdr_667 @[el2_lib.scala 518:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_5.io.en <= _T_533 @[el2_lib.scala 521:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + node _T_531 = not(_T_530) @[el2_dec_decode_ctl.scala 599:39] + node _T_532 = and(x_t.i0trigger, _T_531) @[el2_dec_decode_ctl.scala 599:37] + x_t_in.i0trigger <= _T_532 @[el2_dec_decode_ctl.scala 599:20] + node _T_533 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 601:36] + inst rvclkhdr_6 of rvclkhdr_667 @[el2_lib.scala 518:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_6.io.en <= _T_533 @[el2_lib.scala 521:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] wire _T_534 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33] _T_534.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_534.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33] @@ -68238,7 +68221,7 @@ circuit el2_swerv : _T_534.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_534.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33] _T_534.legal <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_535 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_534)) @[el2_lib.scala 524:16] + reg _T_535 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_534)) @[el2_lib.scala 524:16] _T_535.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[el2_lib.scala 524:16] _T_535.pmu_divide <= x_t_in.pmu_divide @[el2_lib.scala 524:16] _T_535.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[el2_lib.scala 524:16] @@ -68249,31 +68232,31 @@ circuit el2_swerv : _T_535.icaf_f1 <= x_t_in.icaf_f1 @[el2_lib.scala 524:16] _T_535.icaf <= x_t_in.icaf @[el2_lib.scala 524:16] _T_535.legal <= x_t_in.legal @[el2_lib.scala 524:16] - r_t.pmu_lsu_misaligned <= _T_535.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 605:7] - r_t.pmu_divide <= _T_535.pmu_divide @[el2_dec_decode_ctl.scala 605:7] - r_t.pmu_i0_br_unpred <= _T_535.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 605:7] - r_t.pmu_i0_itype <= _T_535.pmu_i0_itype @[el2_dec_decode_ctl.scala 605:7] - r_t.i0trigger <= _T_535.i0trigger @[el2_dec_decode_ctl.scala 605:7] - r_t.fence_i <= _T_535.fence_i @[el2_dec_decode_ctl.scala 605:7] - r_t.icaf_type <= _T_535.icaf_type @[el2_dec_decode_ctl.scala 605:7] - r_t.icaf_f1 <= _T_535.icaf_f1 @[el2_dec_decode_ctl.scala 605:7] - r_t.icaf <= _T_535.icaf @[el2_dec_decode_ctl.scala 605:7] - r_t.legal <= _T_535.legal @[el2_dec_decode_ctl.scala 605:7] - reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 606:36] - lsu_trigger_match_r <= io.lsu_trigger_match_m @[el2_dec_decode_ctl.scala 606:36] - reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 607:37] - lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[el2_dec_decode_ctl.scala 607:37] - r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 609:10] - r_t_in.pmu_divide <= r_t.pmu_divide @[el2_dec_decode_ctl.scala 609:10] - r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 609:10] - r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 609:10] - r_t_in.i0trigger <= r_t.i0trigger @[el2_dec_decode_ctl.scala 609:10] - r_t_in.fence_i <= r_t.fence_i @[el2_dec_decode_ctl.scala 609:10] - r_t_in.icaf_type <= r_t.icaf_type @[el2_dec_decode_ctl.scala 609:10] - r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 609:10] - r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 609:10] - r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 609:10] - node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 611:61] + r_t.pmu_lsu_misaligned <= _T_535.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 601:7] + r_t.pmu_divide <= _T_535.pmu_divide @[el2_dec_decode_ctl.scala 601:7] + r_t.pmu_i0_br_unpred <= _T_535.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 601:7] + r_t.pmu_i0_itype <= _T_535.pmu_i0_itype @[el2_dec_decode_ctl.scala 601:7] + r_t.i0trigger <= _T_535.i0trigger @[el2_dec_decode_ctl.scala 601:7] + r_t.fence_i <= _T_535.fence_i @[el2_dec_decode_ctl.scala 601:7] + r_t.icaf_type <= _T_535.icaf_type @[el2_dec_decode_ctl.scala 601:7] + r_t.icaf_f1 <= _T_535.icaf_f1 @[el2_dec_decode_ctl.scala 601:7] + r_t.icaf <= _T_535.icaf @[el2_dec_decode_ctl.scala 601:7] + r_t.legal <= _T_535.legal @[el2_dec_decode_ctl.scala 601:7] + reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 602:36] + lsu_trigger_match_r <= io.lsu_trigger_match_m @[el2_dec_decode_ctl.scala 602:36] + reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 603:37] + lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[el2_dec_decode_ctl.scala 603:37] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 605:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[el2_dec_decode_ctl.scala 605:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 605:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 605:10] + r_t_in.i0trigger <= r_t.i0trigger @[el2_dec_decode_ctl.scala 605:10] + r_t_in.fence_i <= r_t.fence_i @[el2_dec_decode_ctl.scala 605:10] + r_t_in.icaf_type <= r_t.icaf_type @[el2_dec_decode_ctl.scala 605:10] + r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10] + r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10] + r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10] + node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 607:56] wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48] _T_537[0] <= _T_536 @[el2_lib.scala 162:48] _T_537[1] <= _T_536 @[el2_lib.scala 162:48] @@ -68282,83 +68265,83 @@ circuit el2_swerv : node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] - node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 611:82] - node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 611:105] - r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 611:33] - r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 612:33] - node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 614:35] - when _T_543 : @[el2_dec_decode_ctl.scala 614:43] - wire _T_544 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 614:66] - _T_544.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.pmu_i0_itype <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.i0trigger <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.icaf_type <= UInt<2>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.icaf_f1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.icaf <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - _T_544.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] - r_t_in.pmu_lsu_misaligned <= _T_544.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 614:51] - r_t_in.pmu_divide <= _T_544.pmu_divide @[el2_dec_decode_ctl.scala 614:51] - r_t_in.pmu_i0_br_unpred <= _T_544.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 614:51] - r_t_in.pmu_i0_itype <= _T_544.pmu_i0_itype @[el2_dec_decode_ctl.scala 614:51] - r_t_in.i0trigger <= _T_544.i0trigger @[el2_dec_decode_ctl.scala 614:51] - r_t_in.fence_i <= _T_544.fence_i @[el2_dec_decode_ctl.scala 614:51] - r_t_in.icaf_type <= _T_544.icaf_type @[el2_dec_decode_ctl.scala 614:51] - r_t_in.icaf_f1 <= _T_544.icaf_f1 @[el2_dec_decode_ctl.scala 614:51] - r_t_in.icaf <= _T_544.icaf @[el2_dec_decode_ctl.scala 614:51] - r_t_in.legal <= _T_544.legal @[el2_dec_decode_ctl.scala 614:51] - skip @[el2_dec_decode_ctl.scala 614:43] - io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 616:39] - io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 616:39] - node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 617:58] - io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 617:39] - reg _T_546 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 620:52] - _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 620:52] - flush_final_r <= _T_546 @[el2_dec_decode_ctl.scala 620:17] - node _T_547 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:46] - node _T_548 = and(io.dec_ib0_valid_d, _T_547) @[el2_dec_decode_ctl.scala 622:44] - node _T_549 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:60] - node _T_550 = and(_T_548, _T_549) @[el2_dec_decode_ctl.scala 622:58] - node _T_551 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:88] - node _T_552 = and(_T_550, _T_551) @[el2_dec_decode_ctl.scala 622:86] - io.dec_i0_decode_d <= _T_552 @[el2_dec_decode_ctl.scala 622:22] - node _T_553 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 624:16] - i0r.rs1 <= _T_553 @[el2_dec_decode_ctl.scala 624:11] - node _T_554 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 625:16] - i0r.rs2 <= _T_554 @[el2_dec_decode_ctl.scala 625:11] - node _T_555 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 626:16] - i0r.rd <= _T_555 @[el2_dec_decode_ctl.scala 626:11] - node _T_556 = neq(i0r.rs1, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 628:49] - node _T_557 = and(i0_dp.rs1, _T_556) @[el2_dec_decode_ctl.scala 628:38] - io.dec_i0_rs1_en_d <= _T_557 @[el2_dec_decode_ctl.scala 628:24] - node _T_558 = neq(i0r.rs2, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 629:49] - node _T_559 = and(i0_dp.rs2, _T_558) @[el2_dec_decode_ctl.scala 629:38] - io.dec_i0_rs2_en_d <= _T_559 @[el2_dec_decode_ctl.scala 629:24] - node _T_560 = neq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 630:48] - node i0_rd_en_d = and(i0_dp.rd, _T_560) @[el2_dec_decode_ctl.scala 630:37] - io.dec_i0_rs1_d <= i0r.rs1 @[el2_dec_decode_ctl.scala 631:19] - io.dec_i0_rs2_d <= i0r.rs2 @[el2_dec_decode_ctl.scala 632:19] - node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[el2_dec_decode_ctl.scala 634:38] - node _T_561 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 635:27] - node i0_uiimm20 = and(_T_561, i0_dp.imm20) @[el2_dec_decode_ctl.scala 635:38] - node _T_562 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 639:5] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:72] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:95] + r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33] + node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35] + when _T_543 : @[el2_dec_decode_ctl.scala 610:43] + wire _T_544 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 610:66] + _T_544.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.pmu_i0_itype <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.i0trigger <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.icaf_type <= UInt<2>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.icaf_f1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.icaf <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + _T_544.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 610:66] + r_t_in.pmu_lsu_misaligned <= _T_544.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 610:51] + r_t_in.pmu_divide <= _T_544.pmu_divide @[el2_dec_decode_ctl.scala 610:51] + r_t_in.pmu_i0_br_unpred <= _T_544.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 610:51] + r_t_in.pmu_i0_itype <= _T_544.pmu_i0_itype @[el2_dec_decode_ctl.scala 610:51] + r_t_in.i0trigger <= _T_544.i0trigger @[el2_dec_decode_ctl.scala 610:51] + r_t_in.fence_i <= _T_544.fence_i @[el2_dec_decode_ctl.scala 610:51] + r_t_in.icaf_type <= _T_544.icaf_type @[el2_dec_decode_ctl.scala 610:51] + r_t_in.icaf_f1 <= _T_544.icaf_f1 @[el2_dec_decode_ctl.scala 610:51] + r_t_in.icaf <= _T_544.icaf @[el2_dec_decode_ctl.scala 610:51] + r_t_in.legal <= _T_544.legal @[el2_dec_decode_ctl.scala 610:51] + skip @[el2_dec_decode_ctl.scala 610:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39] + node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 613:53] + io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39] + reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52] + _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52] + flush_final_r <= _T_546 @[el2_dec_decode_ctl.scala 616:17] + node _T_547 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 618:46] + node _T_548 = and(io.dec_ib0_valid_d, _T_547) @[el2_dec_decode_ctl.scala 618:44] + node _T_549 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 618:60] + node _T_550 = and(_T_548, _T_549) @[el2_dec_decode_ctl.scala 618:58] + node _T_551 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 618:88] + node _T_552 = and(_T_550, _T_551) @[el2_dec_decode_ctl.scala 618:86] + io.dec_i0_decode_d <= _T_552 @[el2_dec_decode_ctl.scala 618:22] + node _T_553 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 620:16] + i0r.rs1 <= _T_553 @[el2_dec_decode_ctl.scala 620:11] + node _T_554 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 621:16] + i0r.rs2 <= _T_554 @[el2_dec_decode_ctl.scala 621:11] + node _T_555 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 622:16] + i0r.rd <= _T_555 @[el2_dec_decode_ctl.scala 622:11] + node _T_556 = neq(i0r.rs1, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 624:49] + node _T_557 = and(i0_dp.rs1, _T_556) @[el2_dec_decode_ctl.scala 624:38] + io.dec_i0_rs1_en_d <= _T_557 @[el2_dec_decode_ctl.scala 624:24] + node _T_558 = neq(i0r.rs2, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 625:49] + node _T_559 = and(i0_dp.rs2, _T_558) @[el2_dec_decode_ctl.scala 625:38] + io.dec_i0_rs2_en_d <= _T_559 @[el2_dec_decode_ctl.scala 625:24] + node _T_560 = neq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 626:48] + node i0_rd_en_d = and(i0_dp.rd, _T_560) @[el2_dec_decode_ctl.scala 626:37] + io.dec_i0_rs1_d <= i0r.rs1 @[el2_dec_decode_ctl.scala 627:19] + io.dec_i0_rs2_d <= i0r.rs2 @[el2_dec_decode_ctl.scala 628:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[el2_dec_decode_ctl.scala 630:38] + node _T_561 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 631:27] + node i0_uiimm20 = and(_T_561, i0_dp.imm20) @[el2_dec_decode_ctl.scala 631:38] + node _T_562 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 635:5] node _T_563 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_564 = mux(_T_562, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_565 = or(_T_563, _T_564) @[Mux.scala 27:72] wire _T_566 : UInt<32> @[Mux.scala 27:72] _T_566 <= _T_565 @[Mux.scala 27:72] - io.dec_i0_immed_d <= _T_566 @[el2_dec_decode_ctl.scala 637:21] - node _T_567 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 642:38] + io.dec_i0_immed_d <= _T_566 @[el2_dec_decode_ctl.scala 633:21] + node _T_567 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 638:38] wire _T_568 : UInt<1>[20] @[el2_lib.scala 162:48] _T_568[0] <= _T_567 @[el2_lib.scala 162:48] _T_568[1] <= _T_567 @[el2_lib.scala 162:48] @@ -68399,7 +68382,7 @@ circuit el2_swerv : node _T_585 = cat(_T_584, _T_568[17]) @[Cat.scala 29:58] node _T_586 = cat(_T_585, _T_568[18]) @[Cat.scala 29:58] node _T_587 = cat(_T_586, _T_568[19]) @[Cat.scala 29:58] - node _T_588 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 642:46] + node _T_588 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 638:46] node _T_589 = cat(_T_587, _T_588) @[Cat.scala 29:58] wire _T_590 : UInt<1>[27] @[el2_lib.scala 162:48] _T_590[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68455,9 +68438,9 @@ circuit el2_swerv : node _T_614 = cat(_T_613, _T_590[24]) @[Cat.scala 29:58] node _T_615 = cat(_T_614, _T_590[25]) @[Cat.scala 29:58] node _T_616 = cat(_T_615, _T_590[26]) @[Cat.scala 29:58] - node _T_617 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 643:43] + node _T_617 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 639:43] node _T_618 = cat(_T_616, _T_617) @[Cat.scala 29:58] - node _T_619 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 644:38] + node _T_619 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 640:38] wire _T_620 : UInt<1>[12] @[el2_lib.scala 162:48] _T_620[0] <= _T_619 @[el2_lib.scala 162:48] _T_620[1] <= _T_619 @[el2_lib.scala 162:48] @@ -68482,14 +68465,14 @@ circuit el2_swerv : node _T_629 = cat(_T_628, _T_620[9]) @[Cat.scala 29:58] node _T_630 = cat(_T_629, _T_620[10]) @[Cat.scala 29:58] node _T_631 = cat(_T_630, _T_620[11]) @[Cat.scala 29:58] - node _T_632 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 644:46] - node _T_633 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 644:56] - node _T_634 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 644:63] + node _T_632 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 640:46] + node _T_633 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 640:56] + node _T_634 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 640:63] node _T_635 = cat(_T_634, UInt<1>("h00")) @[Cat.scala 29:58] node _T_636 = cat(_T_631, _T_632) @[Cat.scala 29:58] node _T_637 = cat(_T_636, _T_633) @[Cat.scala 29:58] node _T_638 = cat(_T_637, _T_635) @[Cat.scala 29:58] - node _T_639 = bits(io.dec_i0_instr_d, 31, 12) @[el2_dec_decode_ctl.scala 645:30] + node _T_639 = bits(io.dec_i0_instr_d, 31, 12) @[el2_dec_decode_ctl.scala 641:30] wire _T_640 : UInt<1>[12] @[el2_lib.scala 162:48] _T_640[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_640[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68515,8 +68498,8 @@ circuit el2_swerv : node _T_650 = cat(_T_649, _T_640[10]) @[Cat.scala 29:58] node _T_651 = cat(_T_650, _T_640[11]) @[Cat.scala 29:58] node _T_652 = cat(_T_639, _T_651) @[Cat.scala 29:58] - node _T_653 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[el2_dec_decode_ctl.scala 646:26] - node _T_654 = bits(_T_653, 0, 0) @[el2_dec_decode_ctl.scala 646:43] + node _T_653 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[el2_dec_decode_ctl.scala 642:26] + node _T_654 = bits(_T_653, 0, 0) @[el2_dec_decode_ctl.scala 642:43] wire _T_655 : UInt<1>[27] @[el2_lib.scala 162:48] _T_655[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_655[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68571,7 +68554,7 @@ circuit el2_swerv : node _T_679 = cat(_T_678, _T_655[24]) @[Cat.scala 29:58] node _T_680 = cat(_T_679, _T_655[25]) @[Cat.scala 29:58] node _T_681 = cat(_T_680, _T_655[26]) @[Cat.scala 29:58] - node _T_682 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 646:72] + node _T_682 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 642:72] node _T_683 = cat(_T_681, _T_682) @[Cat.scala 29:58] node _T_684 = mux(i0_dp.imm12, _T_589, UInt<1>("h00")) @[Mux.scala 27:72] node _T_685 = mux(i0_dp.shimm5, _T_618, UInt<1>("h00")) @[Mux.scala 27:72] @@ -68584,259 +68567,259 @@ circuit el2_swerv : node _T_692 = or(_T_691, _T_688) @[Mux.scala 27:72] wire _T_693 : UInt<32> @[Mux.scala 27:72] _T_693 <= _T_692 @[Mux.scala 27:72] - i0_immed_d <= _T_693 @[el2_dec_decode_ctl.scala 641:14] - node _T_694 = and(io.dec_i0_decode_d, i0_legal) @[el2_dec_decode_ctl.scala 648:46] - i0_legal_decode_d <= _T_694 @[el2_dec_decode_ctl.scala 648:24] - node _T_695 = and(i0_dp.mul, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 650:44] - i0_d_c.mul <= _T_695 @[el2_dec_decode_ctl.scala 650:29] - node _T_696 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 651:44] - i0_d_c.load <= _T_696 @[el2_dec_decode_ctl.scala 651:29] - node _T_697 = and(i0_dp.alu, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 652:44] - i0_d_c.alu <= _T_697 @[el2_dec_decode_ctl.scala 652:29] - node _T_698 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 654:71] + i0_immed_d <= _T_693 @[el2_dec_decode_ctl.scala 637:14] + node _T_694 = and(io.dec_i0_decode_d, i0_legal) @[el2_dec_decode_ctl.scala 644:46] + i0_legal_decode_d <= _T_694 @[el2_dec_decode_ctl.scala 644:24] + node _T_695 = and(i0_dp.mul, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 646:44] + i0_d_c.mul <= _T_695 @[el2_dec_decode_ctl.scala 646:29] + node _T_696 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 647:44] + i0_d_c.load <= _T_696 @[el2_dec_decode_ctl.scala 647:29] + node _T_697 = and(i0_dp.alu, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 648:44] + i0_d_c.alu <= _T_697 @[el2_dec_decode_ctl.scala 648:29] + node _T_698 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 650:71] reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] when _T_698 : @[Reg.scala 16:19] i0_x_c.alu <= i0_d_c.alu @[Reg.scala 16:23] i0_x_c.load <= i0_d_c.load @[Reg.scala 16:23] i0_x_c.mul <= i0_d_c.mul @[Reg.scala 16:23] skip @[Reg.scala 16:19] - node _T_699 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 655:71] + node _T_699 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 651:71] reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] when _T_699 : @[Reg.scala 16:19] i0_r_c.alu <= i0_x_c.alu @[Reg.scala 16:23] i0_r_c.load <= i0_x_c.load @[Reg.scala 16:23] i0_r_c.mul <= i0_x_c.mul @[Reg.scala 16:23] skip @[Reg.scala 16:19] - node _T_700 = bits(i0_pipe_en, 3, 1) @[el2_dec_decode_ctl.scala 656:83] - reg _T_701 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 656:72] - _T_701 <= _T_700 @[el2_dec_decode_ctl.scala 656:72] + node _T_700 = bits(i0_pipe_en, 3, 1) @[el2_dec_decode_ctl.scala 652:83] + reg _T_701 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 652:72] + _T_701 <= _T_700 @[el2_dec_decode_ctl.scala 652:72] node _T_702 = cat(io.dec_i0_decode_d, _T_701) @[Cat.scala 29:58] - i0_pipe_en <= _T_702 @[el2_dec_decode_ctl.scala 656:14] - node _T_703 = bits(i0_pipe_en, 3, 2) @[el2_dec_decode_ctl.scala 658:43] - node _T_704 = orr(_T_703) @[el2_dec_decode_ctl.scala 658:49] - node _T_705 = or(_T_704, io.clk_override) @[el2_dec_decode_ctl.scala 658:53] - i0_x_ctl_en <= _T_705 @[el2_dec_decode_ctl.scala 658:29] - node _T_706 = bits(i0_pipe_en, 2, 1) @[el2_dec_decode_ctl.scala 659:43] - node _T_707 = orr(_T_706) @[el2_dec_decode_ctl.scala 659:49] - node _T_708 = or(_T_707, io.clk_override) @[el2_dec_decode_ctl.scala 659:53] - i0_r_ctl_en <= _T_708 @[el2_dec_decode_ctl.scala 659:29] - node _T_709 = bits(i0_pipe_en, 1, 0) @[el2_dec_decode_ctl.scala 660:43] - node _T_710 = orr(_T_709) @[el2_dec_decode_ctl.scala 660:49] - node _T_711 = or(_T_710, io.clk_override) @[el2_dec_decode_ctl.scala 660:53] - i0_wb_ctl_en <= _T_711 @[el2_dec_decode_ctl.scala 660:29] - node _T_712 = bits(i0_pipe_en, 3, 3) @[el2_dec_decode_ctl.scala 661:44] - node _T_713 = or(_T_712, io.clk_override) @[el2_dec_decode_ctl.scala 661:50] - i0_x_data_en <= _T_713 @[el2_dec_decode_ctl.scala 661:29] - node _T_714 = bits(i0_pipe_en, 2, 2) @[el2_dec_decode_ctl.scala 662:44] - node _T_715 = or(_T_714, io.clk_override) @[el2_dec_decode_ctl.scala 662:50] - i0_r_data_en <= _T_715 @[el2_dec_decode_ctl.scala 662:29] - node _T_716 = bits(i0_pipe_en, 1, 1) @[el2_dec_decode_ctl.scala 663:44] - node _T_717 = or(_T_716, io.clk_override) @[el2_dec_decode_ctl.scala 663:50] - i0_wb_data_en <= _T_717 @[el2_dec_decode_ctl.scala 663:29] - node _T_718 = bits(i0_pipe_en, 0, 0) @[el2_dec_decode_ctl.scala 664:44] - node _T_719 = or(_T_718, io.clk_override) @[el2_dec_decode_ctl.scala 664:50] - i0_wb1_data_en <= _T_719 @[el2_dec_decode_ctl.scala 664:29] + i0_pipe_en <= _T_702 @[el2_dec_decode_ctl.scala 652:14] + node _T_703 = bits(i0_pipe_en, 3, 2) @[el2_dec_decode_ctl.scala 654:43] + node _T_704 = orr(_T_703) @[el2_dec_decode_ctl.scala 654:49] + node _T_705 = or(_T_704, io.clk_override) @[el2_dec_decode_ctl.scala 654:53] + i0_x_ctl_en <= _T_705 @[el2_dec_decode_ctl.scala 654:29] + node _T_706 = bits(i0_pipe_en, 2, 1) @[el2_dec_decode_ctl.scala 655:43] + node _T_707 = orr(_T_706) @[el2_dec_decode_ctl.scala 655:49] + node _T_708 = or(_T_707, io.clk_override) @[el2_dec_decode_ctl.scala 655:53] + i0_r_ctl_en <= _T_708 @[el2_dec_decode_ctl.scala 655:29] + node _T_709 = bits(i0_pipe_en, 1, 0) @[el2_dec_decode_ctl.scala 656:43] + node _T_710 = orr(_T_709) @[el2_dec_decode_ctl.scala 656:49] + node _T_711 = or(_T_710, io.clk_override) @[el2_dec_decode_ctl.scala 656:53] + i0_wb_ctl_en <= _T_711 @[el2_dec_decode_ctl.scala 656:29] + node _T_712 = bits(i0_pipe_en, 3, 3) @[el2_dec_decode_ctl.scala 657:44] + node _T_713 = or(_T_712, io.clk_override) @[el2_dec_decode_ctl.scala 657:50] + i0_x_data_en <= _T_713 @[el2_dec_decode_ctl.scala 657:29] + node _T_714 = bits(i0_pipe_en, 2, 2) @[el2_dec_decode_ctl.scala 658:44] + node _T_715 = or(_T_714, io.clk_override) @[el2_dec_decode_ctl.scala 658:50] + i0_r_data_en <= _T_715 @[el2_dec_decode_ctl.scala 658:29] + node _T_716 = bits(i0_pipe_en, 1, 1) @[el2_dec_decode_ctl.scala 659:44] + node _T_717 = or(_T_716, io.clk_override) @[el2_dec_decode_ctl.scala 659:50] + i0_wb_data_en <= _T_717 @[el2_dec_decode_ctl.scala 659:29] + node _T_718 = bits(i0_pipe_en, 0, 0) @[el2_dec_decode_ctl.scala 660:44] + node _T_719 = or(_T_718, io.clk_override) @[el2_dec_decode_ctl.scala 660:50] + i0_wb1_data_en <= _T_719 @[el2_dec_decode_ctl.scala 660:29] node _T_720 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] - io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 666:27] + io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27] node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] - io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 667:27] - d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 669:34] - node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50] - d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 670:34] - d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 671:27] - node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:50] - d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 673:34] - node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 674:50] - d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 674:34] - node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 675:50] - d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 675:34] - node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 677:61] - d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 677:34] - node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 678:58] - d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 678:34] - node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 679:40] - d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 679:34] - node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 681:34] - inst rvclkhdr_6 of rvclkhdr_668 @[el2_lib.scala 518:23] - rvclkhdr_6.clock <= clock - rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_6.io.en <= _T_729 @[el2_lib.scala 521:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_730 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_730.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_730.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] - _T_731.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16] - _T_731.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16] - _T_731.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16] - _T_731.bits.i0v <= d_d.bits.i0v @[el2_lib.scala 524:16] - _T_731.bits.i0div <= d_d.bits.i0div @[el2_lib.scala 524:16] - _T_731.bits.i0store <= d_d.bits.i0store @[el2_lib.scala 524:16] - _T_731.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16] - _T_731.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16] - _T_731.valid <= d_d.valid @[el2_lib.scala 524:16] - x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 681:7] - x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 681:7] - x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 681:7] - wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 682:20] - x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 683:10] - x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 683:10] - x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 683:10] - node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:49] - node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 684:47] - node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:78] - node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 684:76] - x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 684:27] - node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 685:35] - node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 685:33] - node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 685:64] - node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 685:62] - x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 685:20] - node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 687:36] - inst rvclkhdr_7 of rvclkhdr_669 @[el2_lib.scala 518:23] + io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27] + d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:29] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:45] + d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:29] + d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:29] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:45] + d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:29] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:45] + d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:29] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:45] + d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:29] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:56] + d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:29] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:53] + d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:29] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:35] + d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:29] + node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34] + inst rvclkhdr_7 of rvclkhdr_668 @[el2_lib.scala 518:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_7.io.en <= _T_740 @[el2_lib.scala 521:17] + rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_741 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_741.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_741.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] - _T_742.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_742.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_742.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_742.bits.i0v <= x_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_742.bits.i0div <= x_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_742.bits.i0store <= x_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_742.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_742.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_742.valid <= x_d_in.valid @[el2_lib.scala 524:16] - r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 687:7] - r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 687:7] - r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 687:7] - r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 688:10] - r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 688:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 689:22] - node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 691:51] - node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 691:49] - r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 691:27] - node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 692:37] - node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 692:35] - r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 692:20] - node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 693:51] - node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 693:49] - r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 693:27] - node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 694:51] - node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 694:49] - r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 694:27] - node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 696:37] - inst rvclkhdr_8 of rvclkhdr_670 @[el2_lib.scala 518:23] + wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] + _T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 524:16] + _T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 524:16] + _T_731.csrwen <= d_d.csrwen @[el2_lib.scala 524:16] + _T_731.i0valid <= d_d.i0valid @[el2_lib.scala 524:16] + _T_731.i0v <= d_d.i0v @[el2_lib.scala 524:16] + _T_731.i0div <= d_d.i0div @[el2_lib.scala 524:16] + _T_731.i0store <= d_d.i0store @[el2_lib.scala 524:16] + _T_731.i0load <= d_d.i0load @[el2_lib.scala 524:16] + _T_731.i0rd <= d_d.i0rd @[el2_lib.scala 524:16] + x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 677:7] + x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 677:7] + x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 677:7] + x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 677:7] + x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 677:7] + x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 677:7] + x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 677:7] + wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 678:20] + x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 679:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:39] + node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:37] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:68] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:66] + x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:22] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:39] + node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 681:37] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:68] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:66] + x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 681:22] + node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36] + inst rvclkhdr_8 of rvclkhdr_669 @[el2_lib.scala 518:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_8.io.en <= _T_751 @[el2_lib.scala 521:17] + rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_752 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_752.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_752.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] - _T_753.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_753.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_753.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_753.bits.i0v <= r_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_753.bits.i0div <= r_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_753.bits.i0store <= r_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_753.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_753.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_753.valid <= r_d_in.valid @[el2_lib.scala 524:16] - wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 696:7] - wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 696:7] - wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 696:7] - io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 698:27] - node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 699:47] - node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 699:45] - i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 699:25] - node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 700:49] - node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 700:47] - node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 700:70] - node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 700:68] - io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 700:32] - io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 701:26] - node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 703:57] - inst rvclkhdr_9 of rvclkhdr_671 @[el2_lib.scala 508:23] + wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] + _T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 524:16] + _T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 524:16] + _T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 524:16] + _T_742.i0v <= x_d_in.i0v @[el2_lib.scala 524:16] + _T_742.i0div <= x_d_in.i0div @[el2_lib.scala 524:16] + _T_742.i0store <= x_d_in.i0store @[el2_lib.scala 524:16] + _T_742.i0load <= x_d_in.i0load @[el2_lib.scala 524:16] + _T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 524:16] + r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 683:7] + r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 683:7] + r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 683:7] + r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 683:7] + r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 683:7] + r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 683:7] + r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 683:7] + r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 685:17] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:41] + node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:39] + r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:22] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:41] + node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 688:39] + r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 688:22] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:41] + node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:39] + r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:22] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:41] + node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:39] + r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:22] + node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37] + inst rvclkhdr_9 of rvclkhdr_670 @[el2_lib.scala 518:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_9.io.en <= _T_760 @[el2_lib.scala 511:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_result_r_raw : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] + _T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 524:16] + _T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 524:16] + _T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 524:16] + _T_753.i0v <= r_d_in.i0v @[el2_lib.scala 524:16] + _T_753.i0div <= r_d_in.i0div @[el2_lib.scala 524:16] + _T_753.i0store <= r_d_in.i0store @[el2_lib.scala 524:16] + _T_753.i0load <= r_d_in.i0load @[el2_lib.scala 524:16] + _T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 524:16] + wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 692:7] + wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 692:7] + wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 692:7] + wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 692:7] + wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 692:7] + wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 692:7] + wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 692:7] + io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 694:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:42] + node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:40] + i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25] + node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] + node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:65] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:63] + io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26] + node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57] + inst rvclkhdr_10 of rvclkhdr_671 @[el2_lib.scala 508:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_10.io.en <= _T_760 @[el2_lib.scala 511:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] - node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 709:47] - node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 709:66] - node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 709:32] - i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 709:26] - i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 710:26] - node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 714:42] - node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 714:61] - node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 714:27] - i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 714:21] - node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 715:54] - node _T_768 = and(io.i0_ap.predict_nt, _T_767) @[el2_dec_decode_ctl.scala 715:52] - node _T_769 = bits(_T_768, 0, 0) @[el2_dec_decode_ctl.scala 715:66] + node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 705:42] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:56] + node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32] + i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26] + i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26] + node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 710:37] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:51] + node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27] + i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21] + node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54] + node _T_768 = and(io.i0_ap.predict_nt, _T_767) @[el2_dec_decode_ctl.scala 711:52] + node _T_769 = bits(_T_768, 0, 0) @[el2_dec_decode_ctl.scala 711:66] wire _T_770 : UInt<1>[10] @[el2_lib.scala 162:48] _T_770[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_770[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68859,11 +68842,11 @@ circuit el2_swerv : node _T_779 = cat(_T_778, _T_770[9]) @[Cat.scala 29:58] node _T_780 = cat(_T_779, io.dec_i0_pc4_d) @[Cat.scala 29:58] node _T_781 = cat(_T_780, i0_ap_pc2) @[Cat.scala 29:58] - node _T_782 = mux(_T_769, i0_br_offset, _T_781) @[el2_dec_decode_ctl.scala 715:30] - io.dec_i0_br_immed_d <= _T_782 @[el2_dec_decode_ctl.scala 715:24] + node _T_782 = mux(_T_769, i0_br_offset, _T_781) @[el2_dec_decode_ctl.scala 711:30] + io.dec_i0_br_immed_d <= _T_782 @[el2_dec_decode_ctl.scala 711:24] wire last_br_immed_d : UInt<12> last_br_immed_d <= UInt<1>("h00") - node _T_783 = bits(io.i0_ap.predict_nt, 0, 0) @[el2_dec_decode_ctl.scala 717:48] + node _T_783 = bits(io.i0_ap.predict_nt, 0, 0) @[el2_dec_decode_ctl.scala 713:48] wire _T_784 : UInt<1>[10] @[el2_lib.scala 162:48] _T_784[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] _T_784[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] @@ -68886,141 +68869,141 @@ circuit el2_swerv : node _T_793 = cat(_T_792, _T_784[9]) @[Cat.scala 29:58] node _T_794 = cat(_T_793, io.dec_i0_pc4_d) @[Cat.scala 29:58] node _T_795 = cat(_T_794, i0_ap_pc2) @[Cat.scala 29:58] - node _T_796 = mux(_T_783, _T_795, i0_br_offset) @[el2_dec_decode_ctl.scala 717:25] - last_br_immed_d <= _T_796 @[el2_dec_decode_ctl.scala 717:19] + node _T_796 = mux(_T_783, _T_795, i0_br_offset) @[el2_dec_decode_ctl.scala 713:25] + last_br_immed_d <= _T_796 @[el2_dec_decode_ctl.scala 713:19] wire last_br_immed_x : UInt<12> last_br_immed_x <= UInt<1>("h00") - node _T_797 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 719:58] - inst rvclkhdr_10 of rvclkhdr_672 @[el2_lib.scala 508:23] - rvclkhdr_10.clock <= clock - rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_10.io.en <= _T_797 @[el2_lib.scala 511:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_798 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + node _T_797 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 715:58] + inst rvclkhdr_11 of rvclkhdr_672 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= _T_797 @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_798 <= last_br_immed_d @[el2_lib.scala 514:16] - last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 719:19] - node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 723:45] - node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:76] - node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 723:58] - node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 725:48] - node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 725:77] - node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 725:60] - node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 726:21] - node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 726:33] - node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 725:94] - node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 727:21] - node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 727:33] - node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 727:60] - node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 726:62] - node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 731:51] - node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 732:26] - node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 732:24] - node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 732:56] - node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 732:39] - node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 732:77] - node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 731:65] - node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 734:53] - io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 734:29] - node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 735:55] - node _T_817 = eq(io.exu_div_wren, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 737:62] - node _T_818 = and(io.dec_div_active, _T_817) @[el2_dec_decode_ctl.scala 737:60] - node _T_819 = eq(nonblock_div_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 737:81] - node _T_820 = and(_T_818, _T_819) @[el2_dec_decode_ctl.scala 737:79] - node div_active_in = or(i0_div_decode_d, _T_820) @[el2_dec_decode_ctl.scala 737:39] - reg _T_821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 739:54] - _T_821 <= div_active_in @[el2_dec_decode_ctl.scala 739:54] - io.dec_div_active <= _T_821 @[el2_dec_decode_ctl.scala 739:21] - node _T_822 = and(io.dec_i0_rs1_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 742:49] - node _T_823 = eq(io.div_waddr_wb, i0r.rs1) @[el2_dec_decode_ctl.scala 742:88] - node _T_824 = and(_T_822, _T_823) @[el2_dec_decode_ctl.scala 742:69] - node _T_825 = and(io.dec_i0_rs2_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 743:25] - node _T_826 = eq(io.div_waddr_wb, i0r.rs2) @[el2_dec_decode_ctl.scala 743:64] - node _T_827 = and(_T_825, _T_826) @[el2_dec_decode_ctl.scala 743:45] - node _T_828 = or(_T_824, _T_827) @[el2_dec_decode_ctl.scala 742:102] - i0_nonblock_div_stall <= _T_828 @[el2_dec_decode_ctl.scala 742:26] - node _T_829 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 745:59] + last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19] + node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 719:40] + node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 719:68] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:55] + node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 721:43] + node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:69] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:57] + node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 722:16] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:30] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:86] + node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 723:16] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:30] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:57] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:59] + node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51] + node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26] + node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24] + node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:51] + node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:72] + node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65] + node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53] + io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 731:55] + node _T_817 = eq(io.exu_div_wren, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 733:62] + node _T_818 = and(io.dec_div_active, _T_817) @[el2_dec_decode_ctl.scala 733:60] + node _T_819 = eq(nonblock_div_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 733:81] + node _T_820 = and(_T_818, _T_819) @[el2_dec_decode_ctl.scala 733:79] + node div_active_in = or(i0_div_decode_d, _T_820) @[el2_dec_decode_ctl.scala 733:39] + reg _T_821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 735:54] + _T_821 <= div_active_in @[el2_dec_decode_ctl.scala 735:54] + io.dec_div_active <= _T_821 @[el2_dec_decode_ctl.scala 735:21] + node _T_822 = and(io.dec_i0_rs1_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 738:49] + node _T_823 = eq(io.div_waddr_wb, i0r.rs1) @[el2_dec_decode_ctl.scala 738:88] + node _T_824 = and(_T_822, _T_823) @[el2_dec_decode_ctl.scala 738:69] + node _T_825 = and(io.dec_i0_rs2_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 739:25] + node _T_826 = eq(io.div_waddr_wb, i0r.rs2) @[el2_dec_decode_ctl.scala 739:64] + node _T_827 = and(_T_825, _T_826) @[el2_dec_decode_ctl.scala 739:45] + node _T_828 = or(_T_824, _T_827) @[el2_dec_decode_ctl.scala 738:102] + i0_nonblock_div_stall <= _T_828 @[el2_dec_decode_ctl.scala 738:26] + node _T_829 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 741:59] reg _T_830 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_829 : @[Reg.scala 28:19] _T_830 <= i0r.rd @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.div_waddr_wb <= _T_830 @[el2_dec_decode_ctl.scala 745:19] - node _T_831 = bits(i0_inst_d, 24, 7) @[el2_dec_decode_ctl.scala 752:34] - node _T_832 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 752:57] - inst rvclkhdr_11 of rvclkhdr_673 @[el2_lib.scala 508:23] - rvclkhdr_11.clock <= clock - rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= _T_832 @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg div_inst : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - div_inst <= _T_831 @[el2_lib.scala 514:16] - node _T_833 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 753:49] - inst rvclkhdr_12 of rvclkhdr_674 @[el2_lib.scala 508:23] + io.div_waddr_wb <= _T_830 @[el2_dec_decode_ctl.scala 741:19] + node _T_831 = bits(i0_inst_d, 24, 7) @[el2_dec_decode_ctl.scala 748:34] + node _T_832 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 748:57] + inst rvclkhdr_12 of rvclkhdr_673 @[el2_lib.scala 508:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_12.io.en <= _T_833 @[el2_lib.scala 511:17] + rvclkhdr_12.io.en <= _T_832 @[el2_lib.scala 511:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_inst_x : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_inst_x <= i0_inst_d @[el2_lib.scala 514:16] - node _T_834 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 754:49] - inst rvclkhdr_13 of rvclkhdr_675 @[el2_lib.scala 508:23] + reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + div_inst <= _T_831 @[el2_lib.scala 514:16] + node _T_833 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 749:49] + inst rvclkhdr_13 of rvclkhdr_674 @[el2_lib.scala 508:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_13.io.en <= _T_834 @[el2_lib.scala 511:17] + rvclkhdr_13.io.en <= _T_833 @[el2_lib.scala 511:17] rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_inst_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_inst_r <= i0_inst_x @[el2_lib.scala 514:16] - node _T_835 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 756:50] - inst rvclkhdr_14 of rvclkhdr_676 @[el2_lib.scala 508:23] + reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_inst_x <= i0_inst_d @[el2_lib.scala 514:16] + node _T_834 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 750:49] + inst rvclkhdr_14 of rvclkhdr_675 @[el2_lib.scala 508:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_14.io.en <= _T_835 @[el2_lib.scala 511:17] + rvclkhdr_14.io.en <= _T_834 @[el2_lib.scala 511:17] rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_inst_wb : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_inst_wb <= i0_inst_r @[el2_lib.scala 514:16] - node _T_836 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 757:53] - inst rvclkhdr_15 of rvclkhdr_677 @[el2_lib.scala 508:23] + reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_inst_r <= i0_inst_x @[el2_lib.scala 514:16] + node _T_835 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 752:50] + inst rvclkhdr_15 of rvclkhdr_676 @[el2_lib.scala 508:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_15.io.en <= _T_836 @[el2_lib.scala 511:17] + rvclkhdr_15.io.en <= _T_835 @[el2_lib.scala 511:17] rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_837 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_837 <= i0_inst_wb @[el2_lib.scala 514:16] - io.dec_i0_inst_wb1 <= _T_837 @[el2_dec_decode_ctl.scala 757:22] - node _T_838 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 758:53] - inst rvclkhdr_16 of rvclkhdr_678 @[el2_lib.scala 508:23] + reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_inst_wb <= i0_inst_r @[el2_lib.scala 514:16] + node _T_836 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 753:53] + inst rvclkhdr_16 of rvclkhdr_677 @[el2_lib.scala 508:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_16.io.en <= _T_838 @[el2_lib.scala 511:17] + rvclkhdr_16.io.en <= _T_836 @[el2_lib.scala 511:17] rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_pc_wb : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 514:16] - node _T_839 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 760:49] - inst rvclkhdr_17 of rvclkhdr_679 @[el2_lib.scala 508:23] + reg _T_837 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_837 <= i0_inst_wb @[el2_lib.scala 514:16] + io.dec_i0_inst_wb1 <= _T_837 @[el2_dec_decode_ctl.scala 753:22] + node _T_838 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 754:53] + inst rvclkhdr_17 of rvclkhdr_678 @[el2_lib.scala 508:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_17.io.en <= _T_839 @[el2_lib.scala 511:17] + rvclkhdr_17.io.en <= _T_838 @[el2_lib.scala 511:17] rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_840 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_840 <= i0_pc_wb @[el2_lib.scala 514:16] - io.dec_i0_pc_wb1 <= _T_840 @[el2_dec_decode_ctl.scala 760:20] - node _T_841 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 761:56] - inst rvclkhdr_18 of rvclkhdr_680 @[el2_lib.scala 508:23] + reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 514:16] + node _T_839 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 756:49] + inst rvclkhdr_18 of rvclkhdr_679 @[el2_lib.scala 508:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_18.io.en <= _T_841 @[el2_lib.scala 511:17] + rvclkhdr_18.io.en <= _T_839 @[el2_lib.scala 511:17] rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg dec_i0_pc_r : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + reg _T_840 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_840 <= i0_pc_wb @[el2_lib.scala 514:16] + io.dec_i0_pc_wb1 <= _T_840 @[el2_dec_decode_ctl.scala 756:20] + node _T_841 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 757:56] + inst rvclkhdr_19 of rvclkhdr_680 @[el2_lib.scala 508:23] + rvclkhdr_19.clock <= clock + rvclkhdr_19.reset <= reset + rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_19.io.en <= _T_841 @[el2_lib.scala 511:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] dec_i0_pc_r <= io.exu_i0_pc_x @[el2_lib.scala 514:16] - io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[el2_dec_decode_ctl.scala 763:27] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[el2_dec_decode_ctl.scala 759:27] node _T_842 = cat(io.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] node _T_843 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] node _T_844 = bits(_T_842, 12, 1) @[el2_lib.scala 208:24] @@ -69056,124 +69039,124 @@ circuit el2_swerv : node _T_873 = bits(_T_846, 11, 0) @[el2_lib.scala 214:94] node _T_874 = cat(_T_872, _T_873) @[Cat.scala 29:58] node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 768:51] - io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 768:25] - node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48] - node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 772:80] - node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 772:63] - node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 773:48] - node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 773:80] - node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 773:63] - node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 775:48] - node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 775:80] - node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 775:63] - node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 776:48] - node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 776:80] - node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 776:63] - node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 778:44] - node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 778:81] - wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 778:109] - _T_886.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109] - _T_886.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109] - _T_886.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109] - node _T_887 = mux(_T_885, i0_r_c, _T_886) @[el2_dec_decode_ctl.scala 778:61] - node _T_888 = mux(_T_884, i0_x_c, _T_887) @[el2_dec_decode_ctl.scala 778:24] - i0_rs1_class_d.alu <= _T_888.alu @[el2_dec_decode_ctl.scala 778:18] - i0_rs1_class_d.load <= _T_888.load @[el2_dec_decode_ctl.scala 778:18] - i0_rs1_class_d.mul <= _T_888.mul @[el2_dec_decode_ctl.scala 778:18] - node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 779:44] - node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 779:83] - node _T_891 = mux(_T_890, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 779:63] - node _T_892 = mux(_T_889, UInt<2>("h01"), _T_891) @[el2_dec_decode_ctl.scala 779:24] - i0_rs1_depth_d <= _T_892 @[el2_dec_decode_ctl.scala 779:18] - node _T_893 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 780:44] - node _T_894 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 780:81] - wire _T_895 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 780:109] - _T_895.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109] - _T_895.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109] - _T_895.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109] - node _T_896 = mux(_T_894, i0_r_c, _T_895) @[el2_dec_decode_ctl.scala 780:61] - node _T_897 = mux(_T_893, i0_x_c, _T_896) @[el2_dec_decode_ctl.scala 780:24] - i0_rs2_class_d.alu <= _T_897.alu @[el2_dec_decode_ctl.scala 780:18] - i0_rs2_class_d.load <= _T_897.load @[el2_dec_decode_ctl.scala 780:18] - i0_rs2_class_d.mul <= _T_897.mul @[el2_dec_decode_ctl.scala 780:18] - node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 781:44] - node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 781:83] - node _T_900 = mux(_T_899, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 781:63] - node _T_901 = mux(_T_898, UInt<2>("h01"), _T_900) @[el2_dec_decode_ctl.scala 781:24] - i0_rs2_depth_d <= _T_901 @[el2_dec_decode_ctl.scala 781:18] - i0_load_block_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 791:21] - node _T_902 = or(i0_dp.load, i0_dp.store) @[el2_dec_decode_ctl.scala 792:43] - node _T_903 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 792:74] - node _T_904 = and(_T_902, _T_903) @[el2_dec_decode_ctl.scala 792:58] - node _T_905 = and(_T_904, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 792:78] - load_ldst_bypass_d <= _T_905 @[el2_dec_decode_ctl.scala 792:27] - node _T_906 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 793:59] - node _T_907 = and(i0_dp.store, _T_906) @[el2_dec_decode_ctl.scala 793:43] - node _T_908 = and(_T_907, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 793:63] - store_data_bypass_d <= _T_908 @[el2_dec_decode_ctl.scala 793:25] - store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 794:25] - node _T_909 = and(io.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 798:62] - node _T_910 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[el2_dec_decode_ctl.scala 798:119] - node i0_rs1_nonblock_load_bypass_en_d = and(_T_909, _T_910) @[el2_dec_decode_ctl.scala 798:89] - node _T_911 = and(io.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 800:62] - node _T_912 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[el2_dec_decode_ctl.scala 800:119] - node i0_rs2_nonblock_load_bypass_en_d = and(_T_911, _T_912) @[el2_dec_decode_ctl.scala 800:89] - node _T_913 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 803:41] - node _T_914 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 803:66] - node _T_915 = and(_T_913, _T_914) @[el2_dec_decode_ctl.scala 803:45] - node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 803:104] - node _T_917 = and(_T_916, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 803:108] - node _T_918 = bits(i0_rs1_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 803:149] - node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 803:175] - node _T_920 = or(_T_919, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 803:196] - node _T_921 = and(_T_918, _T_920) @[el2_dec_decode_ctl.scala 803:153] + node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51] + io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 768:48] + node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:70] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:58] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 769:48] + node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:70] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:58] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 771:48] + node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:70] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:58] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:70] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:58] + node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44] + node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81] + wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109] + _T_886.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 774:109] + _T_886.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 774:109] + _T_886.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 774:109] + node _T_887 = mux(_T_885, i0_r_c, _T_886) @[el2_dec_decode_ctl.scala 774:61] + node _T_888 = mux(_T_884, i0_x_c, _T_887) @[el2_dec_decode_ctl.scala 774:24] + i0_rs1_class_d.alu <= _T_888.alu @[el2_dec_decode_ctl.scala 774:18] + i0_rs1_class_d.load <= _T_888.load @[el2_dec_decode_ctl.scala 774:18] + i0_rs1_class_d.mul <= _T_888.mul @[el2_dec_decode_ctl.scala 774:18] + node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 775:44] + node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 775:83] + node _T_891 = mux(_T_890, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 775:63] + node _T_892 = mux(_T_889, UInt<2>("h01"), _T_891) @[el2_dec_decode_ctl.scala 775:24] + i0_rs1_depth_d <= _T_892 @[el2_dec_decode_ctl.scala 775:18] + node _T_893 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 776:44] + node _T_894 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 776:81] + wire _T_895 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 776:109] + _T_895.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 776:109] + _T_895.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 776:109] + _T_895.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 776:109] + node _T_896 = mux(_T_894, i0_r_c, _T_895) @[el2_dec_decode_ctl.scala 776:61] + node _T_897 = mux(_T_893, i0_x_c, _T_896) @[el2_dec_decode_ctl.scala 776:24] + i0_rs2_class_d.alu <= _T_897.alu @[el2_dec_decode_ctl.scala 776:18] + i0_rs2_class_d.load <= _T_897.load @[el2_dec_decode_ctl.scala 776:18] + i0_rs2_class_d.mul <= _T_897.mul @[el2_dec_decode_ctl.scala 776:18] + node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 777:44] + node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 777:83] + node _T_900 = mux(_T_899, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 777:63] + node _T_901 = mux(_T_898, UInt<2>("h01"), _T_900) @[el2_dec_decode_ctl.scala 777:24] + i0_rs2_depth_d <= _T_901 @[el2_dec_decode_ctl.scala 777:18] + i0_load_block_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 787:21] + node _T_902 = or(i0_dp.load, i0_dp.store) @[el2_dec_decode_ctl.scala 788:43] + node _T_903 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 788:74] + node _T_904 = and(_T_902, _T_903) @[el2_dec_decode_ctl.scala 788:58] + node _T_905 = and(_T_904, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 788:78] + load_ldst_bypass_d <= _T_905 @[el2_dec_decode_ctl.scala 788:27] + node _T_906 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 789:59] + node _T_907 = and(i0_dp.store, _T_906) @[el2_dec_decode_ctl.scala 789:43] + node _T_908 = and(_T_907, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 789:63] + store_data_bypass_d <= _T_908 @[el2_dec_decode_ctl.scala 789:25] + store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 790:25] + node _T_909 = and(io.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 794:62] + node _T_910 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[el2_dec_decode_ctl.scala 794:119] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_909, _T_910) @[el2_dec_decode_ctl.scala 794:89] + node _T_911 = and(io.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 796:62] + node _T_912 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[el2_dec_decode_ctl.scala 796:119] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_911, _T_912) @[el2_dec_decode_ctl.scala 796:89] + node _T_913 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 799:41] + node _T_914 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 799:66] + node _T_915 = and(_T_913, _T_914) @[el2_dec_decode_ctl.scala 799:45] + node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 799:104] + node _T_917 = and(_T_916, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 799:108] + node _T_918 = bits(i0_rs1_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 799:149] + node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 799:175] + node _T_920 = or(_T_919, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 799:196] + node _T_921 = and(_T_918, _T_920) @[el2_dec_decode_ctl.scala 799:153] node _T_922 = cat(_T_915, _T_917) @[Cat.scala 29:58] node _T_923 = cat(_T_922, _T_921) @[Cat.scala 29:58] - i0_rs1bypass <= _T_923 @[el2_dec_decode_ctl.scala 803:18] - node _T_924 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 805:41] - node _T_925 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 805:67] - node _T_926 = and(_T_924, _T_925) @[el2_dec_decode_ctl.scala 805:45] - node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 805:105] - node _T_928 = and(_T_927, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 805:109] - node _T_929 = bits(i0_rs2_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 805:149] - node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 805:175] - node _T_931 = or(_T_930, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 805:196] - node _T_932 = and(_T_929, _T_931) @[el2_dec_decode_ctl.scala 805:153] + i0_rs1bypass <= _T_923 @[el2_dec_decode_ctl.scala 799:18] + node _T_924 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 801:41] + node _T_925 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 801:67] + node _T_926 = and(_T_924, _T_925) @[el2_dec_decode_ctl.scala 801:45] + node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 801:105] + node _T_928 = and(_T_927, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 801:109] + node _T_929 = bits(i0_rs2_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 801:149] + node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 801:175] + node _T_931 = or(_T_930, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 801:196] + node _T_932 = and(_T_929, _T_931) @[el2_dec_decode_ctl.scala 801:153] node _T_933 = cat(_T_926, _T_928) @[Cat.scala 29:58] node _T_934 = cat(_T_933, _T_932) @[Cat.scala 29:58] - i0_rs2bypass <= _T_934 @[el2_dec_decode_ctl.scala 805:18] - node _T_935 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:54] - node _T_936 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 807:71] - node _T_937 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 807:89] - node _T_938 = or(_T_936, _T_937) @[el2_dec_decode_ctl.scala 807:75] - node _T_939 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:109] - node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 807:96] - node _T_941 = and(_T_940, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 807:113] - node _T_942 = or(_T_938, _T_941) @[el2_dec_decode_ctl.scala 807:93] + i0_rs2bypass <= _T_934 @[el2_dec_decode_ctl.scala 801:18] + node _T_935 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 803:54] + node _T_936 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 803:71] + node _T_937 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 803:89] + node _T_938 = or(_T_936, _T_937) @[el2_dec_decode_ctl.scala 803:75] + node _T_939 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 803:109] + node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 803:96] + node _T_941 = and(_T_940, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 803:113] + node _T_942 = or(_T_938, _T_941) @[el2_dec_decode_ctl.scala 803:93] node _T_943 = cat(_T_935, _T_942) @[Cat.scala 29:58] - io.dec_i0_rs1_bypass_en_d <= _T_943 @[el2_dec_decode_ctl.scala 807:34] - node _T_944 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 808:54] - node _T_945 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 808:71] - node _T_946 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 808:89] - node _T_947 = or(_T_945, _T_946) @[el2_dec_decode_ctl.scala 808:75] - node _T_948 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 808:109] - node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 808:96] - node _T_950 = and(_T_949, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 808:113] - node _T_951 = or(_T_947, _T_950) @[el2_dec_decode_ctl.scala 808:93] + io.dec_i0_rs1_bypass_en_d <= _T_943 @[el2_dec_decode_ctl.scala 803:34] + node _T_944 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 804:54] + node _T_945 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 804:71] + node _T_946 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 804:89] + node _T_947 = or(_T_945, _T_946) @[el2_dec_decode_ctl.scala 804:75] + node _T_948 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 804:109] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 804:96] + node _T_950 = and(_T_949, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 804:113] + node _T_951 = or(_T_947, _T_950) @[el2_dec_decode_ctl.scala 804:93] node _T_952 = cat(_T_944, _T_951) @[Cat.scala 29:58] - io.dec_i0_rs2_bypass_en_d <= _T_952 @[el2_dec_decode_ctl.scala 808:34] - node _T_953 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 811:17] - node _T_954 = bits(_T_953, 0, 0) @[el2_dec_decode_ctl.scala 811:21] - node _T_955 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 812:17] - node _T_956 = bits(_T_955, 0, 0) @[el2_dec_decode_ctl.scala 812:21] - node _T_957 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 813:19] - node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 813:6] - node _T_959 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 813:38] - node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 813:25] - node _T_961 = and(_T_958, _T_960) @[el2_dec_decode_ctl.scala 813:23] - node _T_962 = and(_T_961, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 813:42] - node _T_963 = bits(_T_962, 0, 0) @[el2_dec_decode_ctl.scala 813:78] + io.dec_i0_rs2_bypass_en_d <= _T_952 @[el2_dec_decode_ctl.scala 804:34] + node _T_953 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 808:17] + node _T_954 = bits(_T_953, 0, 0) @[el2_dec_decode_ctl.scala 808:21] + node _T_955 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 809:17] + node _T_956 = bits(_T_955, 0, 0) @[el2_dec_decode_ctl.scala 809:21] + node _T_957 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 810:19] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 810:6] + node _T_959 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 810:38] + node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 810:25] + node _T_961 = and(_T_958, _T_960) @[el2_dec_decode_ctl.scala 810:23] + node _T_962 = and(_T_961, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 810:42] + node _T_963 = bits(_T_962, 0, 0) @[el2_dec_decode_ctl.scala 810:78] node _T_964 = mux(_T_954, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_965 = mux(_T_956, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_966 = mux(_T_963, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] @@ -69181,18 +69164,18 @@ circuit el2_swerv : node _T_968 = or(_T_967, _T_966) @[Mux.scala 27:72] wire _T_969 : UInt<32> @[Mux.scala 27:72] _T_969 <= _T_968 @[Mux.scala 27:72] - io.dec_i0_rs1_bypass_data_d <= _T_969 @[el2_dec_decode_ctl.scala 810:31] - node _T_970 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 816:17] - node _T_971 = bits(_T_970, 0, 0) @[el2_dec_decode_ctl.scala 816:21] - node _T_972 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 817:17] - node _T_973 = bits(_T_972, 0, 0) @[el2_dec_decode_ctl.scala 817:21] - node _T_974 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 818:19] - node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 818:6] - node _T_976 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 818:38] - node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 818:25] - node _T_978 = and(_T_975, _T_977) @[el2_dec_decode_ctl.scala 818:23] - node _T_979 = and(_T_978, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 818:42] - node _T_980 = bits(_T_979, 0, 0) @[el2_dec_decode_ctl.scala 818:78] + io.dec_i0_rs1_bypass_data_d <= _T_969 @[el2_dec_decode_ctl.scala 807:31] + node _T_970 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 813:17] + node _T_971 = bits(_T_970, 0, 0) @[el2_dec_decode_ctl.scala 813:21] + node _T_972 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 814:17] + node _T_973 = bits(_T_972, 0, 0) @[el2_dec_decode_ctl.scala 814:21] + node _T_974 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 815:19] + node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 815:6] + node _T_976 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 815:38] + node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 815:25] + node _T_978 = and(_T_975, _T_977) @[el2_dec_decode_ctl.scala 815:23] + node _T_979 = and(_T_978, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 815:42] + node _T_980 = bits(_T_979, 0, 0) @[el2_dec_decode_ctl.scala 815:78] node _T_981 = mux(_T_971, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_982 = mux(_T_973, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_983 = mux(_T_980, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] @@ -69200,33 +69183,33 @@ circuit el2_swerv : node _T_985 = or(_T_984, _T_983) @[Mux.scala 27:72] wire _T_986 : UInt<32> @[Mux.scala 27:72] _T_986 <= _T_985 @[Mux.scala 27:72] - io.dec_i0_rs2_bypass_data_d <= _T_986 @[el2_dec_decode_ctl.scala 815:31] - node _T_987 = or(i0_dp_raw.load, i0_dp_raw.store) @[el2_dec_decode_ctl.scala 820:68] - node _T_988 = and(io.dec_ib0_valid_d, _T_987) @[el2_dec_decode_ctl.scala 820:50] - node _T_989 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:89] - node _T_990 = and(_T_988, _T_989) @[el2_dec_decode_ctl.scala 820:87] - node _T_991 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:114] - node _T_992 = and(_T_990, _T_991) @[el2_dec_decode_ctl.scala 820:112] - node _T_993 = or(_T_992, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 820:131] - io.dec_lsu_valid_raw_d <= _T_993 @[el2_dec_decode_ctl.scala 820:26] - node _T_994 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 822:6] - node _T_995 = and(_T_994, i0_dp.lsu) @[el2_dec_decode_ctl.scala 822:27] - node _T_996 = and(_T_995, i0_dp.load) @[el2_dec_decode_ctl.scala 822:39] - node _T_997 = bits(_T_996, 0, 0) @[el2_dec_decode_ctl.scala 822:53] - node _T_998 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 822:70] - node _T_999 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 823:6] - node _T_1000 = and(_T_999, i0_dp.lsu) @[el2_dec_decode_ctl.scala 823:27] - node _T_1001 = and(_T_1000, i0_dp.store) @[el2_dec_decode_ctl.scala 823:39] - node _T_1002 = bits(_T_1001, 0, 0) @[el2_dec_decode_ctl.scala 823:54] - node _T_1003 = bits(io.dec_i0_instr_d, 31, 25) @[el2_dec_decode_ctl.scala 823:74] - node _T_1004 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 823:84] + io.dec_i0_rs2_bypass_data_d <= _T_986 @[el2_dec_decode_ctl.scala 812:31] + node _T_987 = or(i0_dp_raw.load, i0_dp_raw.store) @[el2_dec_decode_ctl.scala 817:68] + node _T_988 = and(io.dec_ib0_valid_d, _T_987) @[el2_dec_decode_ctl.scala 817:50] + node _T_989 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:89] + node _T_990 = and(_T_988, _T_989) @[el2_dec_decode_ctl.scala 817:87] + node _T_991 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 817:114] + node _T_992 = and(_T_990, _T_991) @[el2_dec_decode_ctl.scala 817:112] + node _T_993 = or(_T_992, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 817:131] + io.dec_lsu_valid_raw_d <= _T_993 @[el2_dec_decode_ctl.scala 817:26] + node _T_994 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 819:6] + node _T_995 = and(_T_994, i0_dp.lsu) @[el2_dec_decode_ctl.scala 819:27] + node _T_996 = and(_T_995, i0_dp.load) @[el2_dec_decode_ctl.scala 819:39] + node _T_997 = bits(_T_996, 0, 0) @[el2_dec_decode_ctl.scala 819:53] + node _T_998 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 819:70] + node _T_999 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:6] + node _T_1000 = and(_T_999, i0_dp.lsu) @[el2_dec_decode_ctl.scala 820:27] + node _T_1001 = and(_T_1000, i0_dp.store) @[el2_dec_decode_ctl.scala 820:39] + node _T_1002 = bits(_T_1001, 0, 0) @[el2_dec_decode_ctl.scala 820:54] + node _T_1003 = bits(io.dec_i0_instr_d, 31, 25) @[el2_dec_decode_ctl.scala 820:74] + node _T_1004 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 820:84] node _T_1005 = cat(_T_1003, _T_1004) @[Cat.scala 29:58] node _T_1006 = mux(_T_997, _T_998, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1007 = mux(_T_1002, _T_1005, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1008 = or(_T_1006, _T_1007) @[Mux.scala 27:72] wire _T_1009 : UInt<12> @[Mux.scala 27:72] _T_1009 <= _T_1008 @[Mux.scala 27:72] - io.dec_lsu_offset_d <= _T_1009 @[el2_dec_decode_ctl.scala 821:23] + io.dec_lsu_offset_d <= _T_1009 @[el2_dec_decode_ctl.scala 818:23] extmodule gated_latch_681 : output Q : Clock @@ -69978,766 +69961,927 @@ circuit el2_swerv : output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, rd0 : UInt<32>, rd1 : UInt<32>, flip scan_mode : UInt<1>} wire w0v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 10:30] - wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 11:30] - wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 12:30] - wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 13:22] - wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 14:22] - wire gpr_wr_en : UInt<32> @[el2_dec_gpr_ctl.scala 15:22] - w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 16:9] - w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:9] - w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 18:9] - gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 19:13] - gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:12] - io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 21:9] - io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 22:9] - node _T = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] - node _T_1 = cat(w0v[2], _T) @[Cat.scala 29:58] - node _T_2 = cat(w0v[3], _T_1) @[Cat.scala 29:58] - node _T_3 = cat(w0v[4], _T_2) @[Cat.scala 29:58] - node _T_4 = cat(w0v[5], _T_3) @[Cat.scala 29:58] - node _T_5 = cat(w0v[6], _T_4) @[Cat.scala 29:58] - node _T_6 = cat(w0v[7], _T_5) @[Cat.scala 29:58] - node _T_7 = cat(w0v[8], _T_6) @[Cat.scala 29:58] - node _T_8 = cat(w0v[9], _T_7) @[Cat.scala 29:58] - node _T_9 = cat(w0v[10], _T_8) @[Cat.scala 29:58] - node _T_10 = cat(w0v[11], _T_9) @[Cat.scala 29:58] - node _T_11 = cat(w0v[12], _T_10) @[Cat.scala 29:58] - node _T_12 = cat(w0v[13], _T_11) @[Cat.scala 29:58] - node _T_13 = cat(w0v[14], _T_12) @[Cat.scala 29:58] - node _T_14 = cat(w0v[15], _T_13) @[Cat.scala 29:58] - node _T_15 = cat(w0v[16], _T_14) @[Cat.scala 29:58] - node _T_16 = cat(w0v[17], _T_15) @[Cat.scala 29:58] - node _T_17 = cat(w0v[18], _T_16) @[Cat.scala 29:58] - node _T_18 = cat(w0v[19], _T_17) @[Cat.scala 29:58] - node _T_19 = cat(w0v[20], _T_18) @[Cat.scala 29:58] - node _T_20 = cat(w0v[21], _T_19) @[Cat.scala 29:58] - node _T_21 = cat(w0v[22], _T_20) @[Cat.scala 29:58] - node _T_22 = cat(w0v[23], _T_21) @[Cat.scala 29:58] - node _T_23 = cat(w0v[24], _T_22) @[Cat.scala 29:58] - node _T_24 = cat(w0v[25], _T_23) @[Cat.scala 29:58] - node _T_25 = cat(w0v[26], _T_24) @[Cat.scala 29:58] - node _T_26 = cat(w0v[27], _T_25) @[Cat.scala 29:58] - node _T_27 = cat(w0v[28], _T_26) @[Cat.scala 29:58] - node _T_28 = cat(w0v[29], _T_27) @[Cat.scala 29:58] - node _T_29 = cat(w0v[30], _T_28) @[Cat.scala 29:58] - node _T_30 = cat(w0v[31], _T_29) @[Cat.scala 29:58] - node _T_31 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] - node _T_32 = cat(w1v[2], _T_31) @[Cat.scala 29:58] - node _T_33 = cat(w1v[3], _T_32) @[Cat.scala 29:58] - node _T_34 = cat(w1v[4], _T_33) @[Cat.scala 29:58] - node _T_35 = cat(w1v[5], _T_34) @[Cat.scala 29:58] - node _T_36 = cat(w1v[6], _T_35) @[Cat.scala 29:58] - node _T_37 = cat(w1v[7], _T_36) @[Cat.scala 29:58] - node _T_38 = cat(w1v[8], _T_37) @[Cat.scala 29:58] - node _T_39 = cat(w1v[9], _T_38) @[Cat.scala 29:58] - node _T_40 = cat(w1v[10], _T_39) @[Cat.scala 29:58] - node _T_41 = cat(w1v[11], _T_40) @[Cat.scala 29:58] - node _T_42 = cat(w1v[12], _T_41) @[Cat.scala 29:58] - node _T_43 = cat(w1v[13], _T_42) @[Cat.scala 29:58] - node _T_44 = cat(w1v[14], _T_43) @[Cat.scala 29:58] - node _T_45 = cat(w1v[15], _T_44) @[Cat.scala 29:58] - node _T_46 = cat(w1v[16], _T_45) @[Cat.scala 29:58] - node _T_47 = cat(w1v[17], _T_46) @[Cat.scala 29:58] - node _T_48 = cat(w1v[18], _T_47) @[Cat.scala 29:58] - node _T_49 = cat(w1v[19], _T_48) @[Cat.scala 29:58] - node _T_50 = cat(w1v[20], _T_49) @[Cat.scala 29:58] - node _T_51 = cat(w1v[21], _T_50) @[Cat.scala 29:58] - node _T_52 = cat(w1v[22], _T_51) @[Cat.scala 29:58] - node _T_53 = cat(w1v[23], _T_52) @[Cat.scala 29:58] - node _T_54 = cat(w1v[24], _T_53) @[Cat.scala 29:58] - node _T_55 = cat(w1v[25], _T_54) @[Cat.scala 29:58] - node _T_56 = cat(w1v[26], _T_55) @[Cat.scala 29:58] - node _T_57 = cat(w1v[27], _T_56) @[Cat.scala 29:58] - node _T_58 = cat(w1v[28], _T_57) @[Cat.scala 29:58] - node _T_59 = cat(w1v[29], _T_58) @[Cat.scala 29:58] - node _T_60 = cat(w1v[30], _T_59) @[Cat.scala 29:58] - node _T_61 = cat(w1v[31], _T_60) @[Cat.scala 29:58] - node _T_62 = or(_T_30, _T_61) @[el2_dec_gpr_ctl.scala 23:51] - node _T_63 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] - node _T_64 = cat(w2v[2], _T_63) @[Cat.scala 29:58] - node _T_65 = cat(w2v[3], _T_64) @[Cat.scala 29:58] - node _T_66 = cat(w2v[4], _T_65) @[Cat.scala 29:58] - node _T_67 = cat(w2v[5], _T_66) @[Cat.scala 29:58] - node _T_68 = cat(w2v[6], _T_67) @[Cat.scala 29:58] - node _T_69 = cat(w2v[7], _T_68) @[Cat.scala 29:58] - node _T_70 = cat(w2v[8], _T_69) @[Cat.scala 29:58] - node _T_71 = cat(w2v[9], _T_70) @[Cat.scala 29:58] - node _T_72 = cat(w2v[10], _T_71) @[Cat.scala 29:58] - node _T_73 = cat(w2v[11], _T_72) @[Cat.scala 29:58] - node _T_74 = cat(w2v[12], _T_73) @[Cat.scala 29:58] - node _T_75 = cat(w2v[13], _T_74) @[Cat.scala 29:58] - node _T_76 = cat(w2v[14], _T_75) @[Cat.scala 29:58] - node _T_77 = cat(w2v[15], _T_76) @[Cat.scala 29:58] - node _T_78 = cat(w2v[16], _T_77) @[Cat.scala 29:58] - node _T_79 = cat(w2v[17], _T_78) @[Cat.scala 29:58] - node _T_80 = cat(w2v[18], _T_79) @[Cat.scala 29:58] - node _T_81 = cat(w2v[19], _T_80) @[Cat.scala 29:58] - node _T_82 = cat(w2v[20], _T_81) @[Cat.scala 29:58] - node _T_83 = cat(w2v[21], _T_82) @[Cat.scala 29:58] - node _T_84 = cat(w2v[22], _T_83) @[Cat.scala 29:58] - node _T_85 = cat(w2v[23], _T_84) @[Cat.scala 29:58] - node _T_86 = cat(w2v[24], _T_85) @[Cat.scala 29:58] - node _T_87 = cat(w2v[25], _T_86) @[Cat.scala 29:58] - node _T_88 = cat(w2v[26], _T_87) @[Cat.scala 29:58] - node _T_89 = cat(w2v[27], _T_88) @[Cat.scala 29:58] - node _T_90 = cat(w2v[28], _T_89) @[Cat.scala 29:58] - node _T_91 = cat(w2v[29], _T_90) @[Cat.scala 29:58] - node _T_92 = cat(w2v[30], _T_91) @[Cat.scala 29:58] - node _T_93 = cat(w2v[31], _T_92) @[Cat.scala 29:58] - node _T_94 = or(_T_62, _T_93) @[el2_dec_gpr_ctl.scala 23:89] - gpr_wr_en <= _T_94 @[el2_dec_gpr_ctl.scala 23:12] - node _T_95 = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_96 = and(io.wen0, _T_95) @[el2_dec_gpr_ctl.scala 26:28] - w0v[1] <= _T_96 @[el2_dec_gpr_ctl.scala 26:16] - node _T_97 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_98 = and(io.wen1, _T_97) @[el2_dec_gpr_ctl.scala 27:28] - w1v[1] <= _T_98 @[el2_dec_gpr_ctl.scala 27:16] - node _T_99 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_100 = and(io.wen2, _T_99) @[el2_dec_gpr_ctl.scala 28:28] - w2v[1] <= _T_100 @[el2_dec_gpr_ctl.scala 28:16] - node _T_101 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] - node _T_102 = mux(_T_101, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_103 = and(_T_102, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_104 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] - node _T_105 = mux(_T_104, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_106 = and(_T_105, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_107 = or(_T_103, _T_106) @[el2_dec_gpr_ctl.scala 29:47] - node _T_108 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 13:30] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 16:30] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 19:22] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 22:22] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + wire gpr_wr_en : UInt<32> + gpr_wr_en <= UInt<1>("h00") + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 26:9] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 27:9] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 28:9] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 29:13] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 30:12] + io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 31:9] + io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 32:9] + node _T = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_1 = and(io.wen0, _T) @[el2_dec_gpr_ctl.scala 35:28] + w0v[1] <= _T_1 @[el2_dec_gpr_ctl.scala 35:16] + node _T_2 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_3 = and(io.wen1, _T_2) @[el2_dec_gpr_ctl.scala 36:28] + w1v[1] <= _T_3 @[el2_dec_gpr_ctl.scala 36:16] + node _T_4 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_5 = and(io.wen2, _T_4) @[el2_dec_gpr_ctl.scala 37:28] + w2v[1] <= _T_5 @[el2_dec_gpr_ctl.scala 37:16] + node _T_6 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_7 = mux(_T_6, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_8 = and(_T_7, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_9 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_10 = mux(_T_9, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_11 = and(_T_10, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_12 = or(_T_8, _T_11) @[el2_dec_gpr_ctl.scala 38:47] + node _T_13 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_14 = mux(_T_13, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_15 = and(_T_14, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_16 = or(_T_12, _T_15) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[1] <= _T_16 @[el2_dec_gpr_ctl.scala 38:16] + node _T_17 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_18 = and(io.wen0, _T_17) @[el2_dec_gpr_ctl.scala 35:28] + w0v[2] <= _T_18 @[el2_dec_gpr_ctl.scala 35:16] + node _T_19 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_20 = and(io.wen1, _T_19) @[el2_dec_gpr_ctl.scala 36:28] + w1v[2] <= _T_20 @[el2_dec_gpr_ctl.scala 36:16] + node _T_21 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_22 = and(io.wen2, _T_21) @[el2_dec_gpr_ctl.scala 37:28] + w2v[2] <= _T_22 @[el2_dec_gpr_ctl.scala 37:16] + node _T_23 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_24 = mux(_T_23, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_25 = and(_T_24, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_26 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_27 = mux(_T_26, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_28 = and(_T_27, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_29 = or(_T_25, _T_28) @[el2_dec_gpr_ctl.scala 38:47] + node _T_30 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_31 = mux(_T_30, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_32 = and(_T_31, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_33 = or(_T_29, _T_32) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[2] <= _T_33 @[el2_dec_gpr_ctl.scala 38:16] + node _T_34 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_35 = and(io.wen0, _T_34) @[el2_dec_gpr_ctl.scala 35:28] + w0v[3] <= _T_35 @[el2_dec_gpr_ctl.scala 35:16] + node _T_36 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_37 = and(io.wen1, _T_36) @[el2_dec_gpr_ctl.scala 36:28] + w1v[3] <= _T_37 @[el2_dec_gpr_ctl.scala 36:16] + node _T_38 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_39 = and(io.wen2, _T_38) @[el2_dec_gpr_ctl.scala 37:28] + w2v[3] <= _T_39 @[el2_dec_gpr_ctl.scala 37:16] + node _T_40 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_41 = mux(_T_40, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_42 = and(_T_41, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_43 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_46 = or(_T_42, _T_45) @[el2_dec_gpr_ctl.scala 38:47] + node _T_47 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_48 = mux(_T_47, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_49 = and(_T_48, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_50 = or(_T_46, _T_49) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[3] <= _T_50 @[el2_dec_gpr_ctl.scala 38:16] + node _T_51 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_52 = and(io.wen0, _T_51) @[el2_dec_gpr_ctl.scala 35:28] + w0v[4] <= _T_52 @[el2_dec_gpr_ctl.scala 35:16] + node _T_53 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_54 = and(io.wen1, _T_53) @[el2_dec_gpr_ctl.scala 36:28] + w1v[4] <= _T_54 @[el2_dec_gpr_ctl.scala 36:16] + node _T_55 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_56 = and(io.wen2, _T_55) @[el2_dec_gpr_ctl.scala 37:28] + w2v[4] <= _T_56 @[el2_dec_gpr_ctl.scala 37:16] + node _T_57 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_59 = and(_T_58, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_60 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_61 = mux(_T_60, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_62 = and(_T_61, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_63 = or(_T_59, _T_62) @[el2_dec_gpr_ctl.scala 38:47] + node _T_64 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_65 = mux(_T_64, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_66 = and(_T_65, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_67 = or(_T_63, _T_66) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[4] <= _T_67 @[el2_dec_gpr_ctl.scala 38:16] + node _T_68 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_69 = and(io.wen0, _T_68) @[el2_dec_gpr_ctl.scala 35:28] + w0v[5] <= _T_69 @[el2_dec_gpr_ctl.scala 35:16] + node _T_70 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_71 = and(io.wen1, _T_70) @[el2_dec_gpr_ctl.scala 36:28] + w1v[5] <= _T_71 @[el2_dec_gpr_ctl.scala 36:16] + node _T_72 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_73 = and(io.wen2, _T_72) @[el2_dec_gpr_ctl.scala 37:28] + w2v[5] <= _T_73 @[el2_dec_gpr_ctl.scala 37:16] + node _T_74 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_75 = mux(_T_74, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_76 = and(_T_75, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_77 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_79 = and(_T_78, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_80 = or(_T_76, _T_79) @[el2_dec_gpr_ctl.scala 38:47] + node _T_81 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_82 = mux(_T_81, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_83 = and(_T_82, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_84 = or(_T_80, _T_83) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[5] <= _T_84 @[el2_dec_gpr_ctl.scala 38:16] + node _T_85 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_86 = and(io.wen0, _T_85) @[el2_dec_gpr_ctl.scala 35:28] + w0v[6] <= _T_86 @[el2_dec_gpr_ctl.scala 35:16] + node _T_87 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_88 = and(io.wen1, _T_87) @[el2_dec_gpr_ctl.scala 36:28] + w1v[6] <= _T_88 @[el2_dec_gpr_ctl.scala 36:16] + node _T_89 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_90 = and(io.wen2, _T_89) @[el2_dec_gpr_ctl.scala 37:28] + w2v[6] <= _T_90 @[el2_dec_gpr_ctl.scala 37:16] + node _T_91 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_93 = and(_T_92, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_94 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_96 = and(_T_95, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_97 = or(_T_93, _T_96) @[el2_dec_gpr_ctl.scala 38:47] + node _T_98 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_101 = or(_T_97, _T_100) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[6] <= _T_101 @[el2_dec_gpr_ctl.scala 38:16] + node _T_102 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_103 = and(io.wen0, _T_102) @[el2_dec_gpr_ctl.scala 35:28] + w0v[7] <= _T_103 @[el2_dec_gpr_ctl.scala 35:16] + node _T_104 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_105 = and(io.wen1, _T_104) @[el2_dec_gpr_ctl.scala 36:28] + w1v[7] <= _T_105 @[el2_dec_gpr_ctl.scala 36:16] + node _T_106 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_107 = and(io.wen2, _T_106) @[el2_dec_gpr_ctl.scala 37:28] + w2v[7] <= _T_107 @[el2_dec_gpr_ctl.scala 37:16] + node _T_108 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_110 = and(_T_109, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_111 = or(_T_107, _T_110) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[1] <= _T_111 @[el2_dec_gpr_ctl.scala 29:16] - node _T_112 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_113 = and(io.wen0, _T_112) @[el2_dec_gpr_ctl.scala 26:28] - w0v[2] <= _T_113 @[el2_dec_gpr_ctl.scala 26:16] - node _T_114 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_115 = and(io.wen1, _T_114) @[el2_dec_gpr_ctl.scala 27:28] - w1v[2] <= _T_115 @[el2_dec_gpr_ctl.scala 27:16] - node _T_116 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_117 = and(io.wen2, _T_116) @[el2_dec_gpr_ctl.scala 28:28] - w2v[2] <= _T_117 @[el2_dec_gpr_ctl.scala 28:16] - node _T_118 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] - node _T_119 = mux(_T_118, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_120 = and(_T_119, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_121 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] - node _T_122 = mux(_T_121, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_123 = and(_T_122, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_124 = or(_T_120, _T_123) @[el2_dec_gpr_ctl.scala 29:47] - node _T_125 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_110 = and(_T_109, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_111 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_113 = and(_T_112, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_114 = or(_T_110, _T_113) @[el2_dec_gpr_ctl.scala 38:47] + node _T_115 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_116 = mux(_T_115, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_117 = and(_T_116, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_118 = or(_T_114, _T_117) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[7] <= _T_118 @[el2_dec_gpr_ctl.scala 38:16] + node _T_119 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_120 = and(io.wen0, _T_119) @[el2_dec_gpr_ctl.scala 35:28] + w0v[8] <= _T_120 @[el2_dec_gpr_ctl.scala 35:16] + node _T_121 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_122 = and(io.wen1, _T_121) @[el2_dec_gpr_ctl.scala 36:28] + w1v[8] <= _T_122 @[el2_dec_gpr_ctl.scala 36:16] + node _T_123 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_124 = and(io.wen2, _T_123) @[el2_dec_gpr_ctl.scala 37:28] + w2v[8] <= _T_124 @[el2_dec_gpr_ctl.scala 37:16] + node _T_125 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_127 = and(_T_126, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_128 = or(_T_124, _T_127) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[2] <= _T_128 @[el2_dec_gpr_ctl.scala 29:16] - node _T_129 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_130 = and(io.wen0, _T_129) @[el2_dec_gpr_ctl.scala 26:28] - w0v[3] <= _T_130 @[el2_dec_gpr_ctl.scala 26:16] - node _T_131 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_132 = and(io.wen1, _T_131) @[el2_dec_gpr_ctl.scala 27:28] - w1v[3] <= _T_132 @[el2_dec_gpr_ctl.scala 27:16] - node _T_133 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_134 = and(io.wen2, _T_133) @[el2_dec_gpr_ctl.scala 28:28] - w2v[3] <= _T_134 @[el2_dec_gpr_ctl.scala 28:16] - node _T_135 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] - node _T_136 = mux(_T_135, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_137 = and(_T_136, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_138 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] - node _T_139 = mux(_T_138, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_140 = and(_T_139, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_141 = or(_T_137, _T_140) @[el2_dec_gpr_ctl.scala 29:47] - node _T_142 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_127 = and(_T_126, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_128 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_130 = and(_T_129, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_131 = or(_T_127, _T_130) @[el2_dec_gpr_ctl.scala 38:47] + node _T_132 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_133 = mux(_T_132, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_134 = and(_T_133, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_135 = or(_T_131, _T_134) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[8] <= _T_135 @[el2_dec_gpr_ctl.scala 38:16] + node _T_136 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_137 = and(io.wen0, _T_136) @[el2_dec_gpr_ctl.scala 35:28] + w0v[9] <= _T_137 @[el2_dec_gpr_ctl.scala 35:16] + node _T_138 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_139 = and(io.wen1, _T_138) @[el2_dec_gpr_ctl.scala 36:28] + w1v[9] <= _T_139 @[el2_dec_gpr_ctl.scala 36:16] + node _T_140 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_141 = and(io.wen2, _T_140) @[el2_dec_gpr_ctl.scala 37:28] + w2v[9] <= _T_141 @[el2_dec_gpr_ctl.scala 37:16] + node _T_142 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_144 = and(_T_143, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_145 = or(_T_141, _T_144) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[3] <= _T_145 @[el2_dec_gpr_ctl.scala 29:16] - node _T_146 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_147 = and(io.wen0, _T_146) @[el2_dec_gpr_ctl.scala 26:28] - w0v[4] <= _T_147 @[el2_dec_gpr_ctl.scala 26:16] - node _T_148 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_149 = and(io.wen1, _T_148) @[el2_dec_gpr_ctl.scala 27:28] - w1v[4] <= _T_149 @[el2_dec_gpr_ctl.scala 27:16] - node _T_150 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_151 = and(io.wen2, _T_150) @[el2_dec_gpr_ctl.scala 28:28] - w2v[4] <= _T_151 @[el2_dec_gpr_ctl.scala 28:16] - node _T_152 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] - node _T_153 = mux(_T_152, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_154 = and(_T_153, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_155 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] - node _T_156 = mux(_T_155, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_157 = and(_T_156, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_158 = or(_T_154, _T_157) @[el2_dec_gpr_ctl.scala 29:47] - node _T_159 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_144 = and(_T_143, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_145 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_146 = mux(_T_145, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_147 = and(_T_146, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_148 = or(_T_144, _T_147) @[el2_dec_gpr_ctl.scala 38:47] + node _T_149 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_150 = mux(_T_149, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_151 = and(_T_150, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_152 = or(_T_148, _T_151) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[9] <= _T_152 @[el2_dec_gpr_ctl.scala 38:16] + node _T_153 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_154 = and(io.wen0, _T_153) @[el2_dec_gpr_ctl.scala 35:28] + w0v[10] <= _T_154 @[el2_dec_gpr_ctl.scala 35:16] + node _T_155 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_156 = and(io.wen1, _T_155) @[el2_dec_gpr_ctl.scala 36:28] + w1v[10] <= _T_156 @[el2_dec_gpr_ctl.scala 36:16] + node _T_157 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_158 = and(io.wen2, _T_157) @[el2_dec_gpr_ctl.scala 37:28] + w2v[10] <= _T_158 @[el2_dec_gpr_ctl.scala 37:16] + node _T_159 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_161 = and(_T_160, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_162 = or(_T_158, _T_161) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[4] <= _T_162 @[el2_dec_gpr_ctl.scala 29:16] - node _T_163 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_164 = and(io.wen0, _T_163) @[el2_dec_gpr_ctl.scala 26:28] - w0v[5] <= _T_164 @[el2_dec_gpr_ctl.scala 26:16] - node _T_165 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_166 = and(io.wen1, _T_165) @[el2_dec_gpr_ctl.scala 27:28] - w1v[5] <= _T_166 @[el2_dec_gpr_ctl.scala 27:16] - node _T_167 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_168 = and(io.wen2, _T_167) @[el2_dec_gpr_ctl.scala 28:28] - w2v[5] <= _T_168 @[el2_dec_gpr_ctl.scala 28:16] - node _T_169 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] - node _T_170 = mux(_T_169, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_171 = and(_T_170, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_172 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(_T_173, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_175 = or(_T_171, _T_174) @[el2_dec_gpr_ctl.scala 29:47] - node _T_176 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_161 = and(_T_160, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_162 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_163 = mux(_T_162, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_164 = and(_T_163, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_165 = or(_T_161, _T_164) @[el2_dec_gpr_ctl.scala 38:47] + node _T_166 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_167 = mux(_T_166, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_168 = and(_T_167, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_169 = or(_T_165, _T_168) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[10] <= _T_169 @[el2_dec_gpr_ctl.scala 38:16] + node _T_170 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_171 = and(io.wen0, _T_170) @[el2_dec_gpr_ctl.scala 35:28] + w0v[11] <= _T_171 @[el2_dec_gpr_ctl.scala 35:16] + node _T_172 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_173 = and(io.wen1, _T_172) @[el2_dec_gpr_ctl.scala 36:28] + w1v[11] <= _T_173 @[el2_dec_gpr_ctl.scala 36:16] + node _T_174 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_175 = and(io.wen2, _T_174) @[el2_dec_gpr_ctl.scala 37:28] + w2v[11] <= _T_175 @[el2_dec_gpr_ctl.scala 37:16] + node _T_176 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_178 = and(_T_177, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_179 = or(_T_175, _T_178) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[5] <= _T_179 @[el2_dec_gpr_ctl.scala 29:16] - node _T_180 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_181 = and(io.wen0, _T_180) @[el2_dec_gpr_ctl.scala 26:28] - w0v[6] <= _T_181 @[el2_dec_gpr_ctl.scala 26:16] - node _T_182 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_183 = and(io.wen1, _T_182) @[el2_dec_gpr_ctl.scala 27:28] - w1v[6] <= _T_183 @[el2_dec_gpr_ctl.scala 27:16] - node _T_184 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_185 = and(io.wen2, _T_184) @[el2_dec_gpr_ctl.scala 28:28] - w2v[6] <= _T_185 @[el2_dec_gpr_ctl.scala 28:16] - node _T_186 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] - node _T_187 = mux(_T_186, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_188 = and(_T_187, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_189 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] - node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_191 = and(_T_190, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_192 = or(_T_188, _T_191) @[el2_dec_gpr_ctl.scala 29:47] - node _T_193 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_178 = and(_T_177, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_179 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_180 = mux(_T_179, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_181 = and(_T_180, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_182 = or(_T_178, _T_181) @[el2_dec_gpr_ctl.scala 38:47] + node _T_183 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(_T_184, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_186 = or(_T_182, _T_185) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[11] <= _T_186 @[el2_dec_gpr_ctl.scala 38:16] + node _T_187 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_188 = and(io.wen0, _T_187) @[el2_dec_gpr_ctl.scala 35:28] + w0v[12] <= _T_188 @[el2_dec_gpr_ctl.scala 35:16] + node _T_189 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_190 = and(io.wen1, _T_189) @[el2_dec_gpr_ctl.scala 36:28] + w1v[12] <= _T_190 @[el2_dec_gpr_ctl.scala 36:16] + node _T_191 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_192 = and(io.wen2, _T_191) @[el2_dec_gpr_ctl.scala 37:28] + w2v[12] <= _T_192 @[el2_dec_gpr_ctl.scala 37:16] + node _T_193 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_195 = and(_T_194, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_196 = or(_T_192, _T_195) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[6] <= _T_196 @[el2_dec_gpr_ctl.scala 29:16] - node _T_197 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_198 = and(io.wen0, _T_197) @[el2_dec_gpr_ctl.scala 26:28] - w0v[7] <= _T_198 @[el2_dec_gpr_ctl.scala 26:16] - node _T_199 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_200 = and(io.wen1, _T_199) @[el2_dec_gpr_ctl.scala 27:28] - w1v[7] <= _T_200 @[el2_dec_gpr_ctl.scala 27:16] - node _T_201 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_202 = and(io.wen2, _T_201) @[el2_dec_gpr_ctl.scala 28:28] - w2v[7] <= _T_202 @[el2_dec_gpr_ctl.scala 28:16] - node _T_203 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] - node _T_204 = mux(_T_203, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_205 = and(_T_204, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_206 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] - node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_208 = and(_T_207, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_209 = or(_T_205, _T_208) @[el2_dec_gpr_ctl.scala 29:47] - node _T_210 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_195 = and(_T_194, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_196 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_197 = mux(_T_196, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_198 = and(_T_197, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_199 = or(_T_195, _T_198) @[el2_dec_gpr_ctl.scala 38:47] + node _T_200 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_202 = and(_T_201, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_203 = or(_T_199, _T_202) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[12] <= _T_203 @[el2_dec_gpr_ctl.scala 38:16] + node _T_204 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_205 = and(io.wen0, _T_204) @[el2_dec_gpr_ctl.scala 35:28] + w0v[13] <= _T_205 @[el2_dec_gpr_ctl.scala 35:16] + node _T_206 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_207 = and(io.wen1, _T_206) @[el2_dec_gpr_ctl.scala 36:28] + w1v[13] <= _T_207 @[el2_dec_gpr_ctl.scala 36:16] + node _T_208 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_209 = and(io.wen2, _T_208) @[el2_dec_gpr_ctl.scala 37:28] + w2v[13] <= _T_209 @[el2_dec_gpr_ctl.scala 37:16] + node _T_210 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_212 = and(_T_211, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_213 = or(_T_209, _T_212) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[7] <= _T_213 @[el2_dec_gpr_ctl.scala 29:16] - node _T_214 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_215 = and(io.wen0, _T_214) @[el2_dec_gpr_ctl.scala 26:28] - w0v[8] <= _T_215 @[el2_dec_gpr_ctl.scala 26:16] - node _T_216 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_217 = and(io.wen1, _T_216) @[el2_dec_gpr_ctl.scala 27:28] - w1v[8] <= _T_217 @[el2_dec_gpr_ctl.scala 27:16] - node _T_218 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_219 = and(io.wen2, _T_218) @[el2_dec_gpr_ctl.scala 28:28] - w2v[8] <= _T_219 @[el2_dec_gpr_ctl.scala 28:16] - node _T_220 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] - node _T_221 = mux(_T_220, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_222 = and(_T_221, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_223 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] - node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_225 = and(_T_224, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_226 = or(_T_222, _T_225) @[el2_dec_gpr_ctl.scala 29:47] - node _T_227 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_212 = and(_T_211, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_213 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_214 = mux(_T_213, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_215 = and(_T_214, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_216 = or(_T_212, _T_215) @[el2_dec_gpr_ctl.scala 38:47] + node _T_217 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_218 = mux(_T_217, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_219 = and(_T_218, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_220 = or(_T_216, _T_219) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[13] <= _T_220 @[el2_dec_gpr_ctl.scala 38:16] + node _T_221 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_222 = and(io.wen0, _T_221) @[el2_dec_gpr_ctl.scala 35:28] + w0v[14] <= _T_222 @[el2_dec_gpr_ctl.scala 35:16] + node _T_223 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_224 = and(io.wen1, _T_223) @[el2_dec_gpr_ctl.scala 36:28] + w1v[14] <= _T_224 @[el2_dec_gpr_ctl.scala 36:16] + node _T_225 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_226 = and(io.wen2, _T_225) @[el2_dec_gpr_ctl.scala 37:28] + w2v[14] <= _T_226 @[el2_dec_gpr_ctl.scala 37:16] + node _T_227 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_229 = and(_T_228, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_230 = or(_T_226, _T_229) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[8] <= _T_230 @[el2_dec_gpr_ctl.scala 29:16] - node _T_231 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_232 = and(io.wen0, _T_231) @[el2_dec_gpr_ctl.scala 26:28] - w0v[9] <= _T_232 @[el2_dec_gpr_ctl.scala 26:16] - node _T_233 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_234 = and(io.wen1, _T_233) @[el2_dec_gpr_ctl.scala 27:28] - w1v[9] <= _T_234 @[el2_dec_gpr_ctl.scala 27:16] - node _T_235 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_236 = and(io.wen2, _T_235) @[el2_dec_gpr_ctl.scala 28:28] - w2v[9] <= _T_236 @[el2_dec_gpr_ctl.scala 28:16] - node _T_237 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] - node _T_238 = mux(_T_237, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_239 = and(_T_238, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_240 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] - node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_242 = and(_T_241, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_243 = or(_T_239, _T_242) @[el2_dec_gpr_ctl.scala 29:47] - node _T_244 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_229 = and(_T_228, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_230 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_232 = and(_T_231, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_233 = or(_T_229, _T_232) @[el2_dec_gpr_ctl.scala 38:47] + node _T_234 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = and(_T_235, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_237 = or(_T_233, _T_236) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[14] <= _T_237 @[el2_dec_gpr_ctl.scala 38:16] + node _T_238 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_239 = and(io.wen0, _T_238) @[el2_dec_gpr_ctl.scala 35:28] + w0v[15] <= _T_239 @[el2_dec_gpr_ctl.scala 35:16] + node _T_240 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_241 = and(io.wen1, _T_240) @[el2_dec_gpr_ctl.scala 36:28] + w1v[15] <= _T_241 @[el2_dec_gpr_ctl.scala 36:16] + node _T_242 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_243 = and(io.wen2, _T_242) @[el2_dec_gpr_ctl.scala 37:28] + w2v[15] <= _T_243 @[el2_dec_gpr_ctl.scala 37:16] + node _T_244 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_246 = and(_T_245, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_247 = or(_T_243, _T_246) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[9] <= _T_247 @[el2_dec_gpr_ctl.scala 29:16] - node _T_248 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_249 = and(io.wen0, _T_248) @[el2_dec_gpr_ctl.scala 26:28] - w0v[10] <= _T_249 @[el2_dec_gpr_ctl.scala 26:16] - node _T_250 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_251 = and(io.wen1, _T_250) @[el2_dec_gpr_ctl.scala 27:28] - w1v[10] <= _T_251 @[el2_dec_gpr_ctl.scala 27:16] - node _T_252 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_253 = and(io.wen2, _T_252) @[el2_dec_gpr_ctl.scala 28:28] - w2v[10] <= _T_253 @[el2_dec_gpr_ctl.scala 28:16] - node _T_254 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] - node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_256 = and(_T_255, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_257 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] - node _T_258 = mux(_T_257, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_259 = and(_T_258, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_260 = or(_T_256, _T_259) @[el2_dec_gpr_ctl.scala 29:47] - node _T_261 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_246 = and(_T_245, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_247 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_249 = and(_T_248, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_250 = or(_T_246, _T_249) @[el2_dec_gpr_ctl.scala 38:47] + node _T_251 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_253 = and(_T_252, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_254 = or(_T_250, _T_253) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[15] <= _T_254 @[el2_dec_gpr_ctl.scala 38:16] + node _T_255 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_256 = and(io.wen0, _T_255) @[el2_dec_gpr_ctl.scala 35:28] + w0v[16] <= _T_256 @[el2_dec_gpr_ctl.scala 35:16] + node _T_257 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_258 = and(io.wen1, _T_257) @[el2_dec_gpr_ctl.scala 36:28] + w1v[16] <= _T_258 @[el2_dec_gpr_ctl.scala 36:16] + node _T_259 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_260 = and(io.wen2, _T_259) @[el2_dec_gpr_ctl.scala 37:28] + w2v[16] <= _T_260 @[el2_dec_gpr_ctl.scala 37:16] + node _T_261 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_263 = and(_T_262, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_264 = or(_T_260, _T_263) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[10] <= _T_264 @[el2_dec_gpr_ctl.scala 29:16] - node _T_265 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_266 = and(io.wen0, _T_265) @[el2_dec_gpr_ctl.scala 26:28] - w0v[11] <= _T_266 @[el2_dec_gpr_ctl.scala 26:16] - node _T_267 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_268 = and(io.wen1, _T_267) @[el2_dec_gpr_ctl.scala 27:28] - w1v[11] <= _T_268 @[el2_dec_gpr_ctl.scala 27:16] - node _T_269 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_270 = and(io.wen2, _T_269) @[el2_dec_gpr_ctl.scala 28:28] - w2v[11] <= _T_270 @[el2_dec_gpr_ctl.scala 28:16] - node _T_271 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] - node _T_272 = mux(_T_271, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_273 = and(_T_272, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_274 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] - node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_276 = and(_T_275, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_277 = or(_T_273, _T_276) @[el2_dec_gpr_ctl.scala 29:47] - node _T_278 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_263 = and(_T_262, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_264 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_265 = mux(_T_264, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_266 = and(_T_265, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_267 = or(_T_263, _T_266) @[el2_dec_gpr_ctl.scala 38:47] + node _T_268 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_269 = mux(_T_268, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_270 = and(_T_269, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_271 = or(_T_267, _T_270) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[16] <= _T_271 @[el2_dec_gpr_ctl.scala 38:16] + node _T_272 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_273 = and(io.wen0, _T_272) @[el2_dec_gpr_ctl.scala 35:28] + w0v[17] <= _T_273 @[el2_dec_gpr_ctl.scala 35:16] + node _T_274 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_275 = and(io.wen1, _T_274) @[el2_dec_gpr_ctl.scala 36:28] + w1v[17] <= _T_275 @[el2_dec_gpr_ctl.scala 36:16] + node _T_276 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_277 = and(io.wen2, _T_276) @[el2_dec_gpr_ctl.scala 37:28] + w2v[17] <= _T_277 @[el2_dec_gpr_ctl.scala 37:16] + node _T_278 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_281 = or(_T_277, _T_280) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[11] <= _T_281 @[el2_dec_gpr_ctl.scala 29:16] - node _T_282 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_283 = and(io.wen0, _T_282) @[el2_dec_gpr_ctl.scala 26:28] - w0v[12] <= _T_283 @[el2_dec_gpr_ctl.scala 26:16] - node _T_284 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_285 = and(io.wen1, _T_284) @[el2_dec_gpr_ctl.scala 27:28] - w1v[12] <= _T_285 @[el2_dec_gpr_ctl.scala 27:16] - node _T_286 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_287 = and(io.wen2, _T_286) @[el2_dec_gpr_ctl.scala 28:28] - w2v[12] <= _T_287 @[el2_dec_gpr_ctl.scala 28:16] - node _T_288 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] - node _T_289 = mux(_T_288, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_290 = and(_T_289, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_291 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] - node _T_292 = mux(_T_291, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_293 = and(_T_292, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_294 = or(_T_290, _T_293) @[el2_dec_gpr_ctl.scala 29:47] - node _T_295 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_280 = and(_T_279, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_281 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_282 = mux(_T_281, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_283 = and(_T_282, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_284 = or(_T_280, _T_283) @[el2_dec_gpr_ctl.scala 38:47] + node _T_285 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_287 = and(_T_286, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_288 = or(_T_284, _T_287) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[17] <= _T_288 @[el2_dec_gpr_ctl.scala 38:16] + node _T_289 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_290 = and(io.wen0, _T_289) @[el2_dec_gpr_ctl.scala 35:28] + w0v[18] <= _T_290 @[el2_dec_gpr_ctl.scala 35:16] + node _T_291 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_292 = and(io.wen1, _T_291) @[el2_dec_gpr_ctl.scala 36:28] + w1v[18] <= _T_292 @[el2_dec_gpr_ctl.scala 36:16] + node _T_293 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_294 = and(io.wen2, _T_293) @[el2_dec_gpr_ctl.scala 37:28] + w2v[18] <= _T_294 @[el2_dec_gpr_ctl.scala 37:16] + node _T_295 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_297 = and(_T_296, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_298 = or(_T_294, _T_297) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[12] <= _T_298 @[el2_dec_gpr_ctl.scala 29:16] - node _T_299 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_300 = and(io.wen0, _T_299) @[el2_dec_gpr_ctl.scala 26:28] - w0v[13] <= _T_300 @[el2_dec_gpr_ctl.scala 26:16] - node _T_301 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_302 = and(io.wen1, _T_301) @[el2_dec_gpr_ctl.scala 27:28] - w1v[13] <= _T_302 @[el2_dec_gpr_ctl.scala 27:16] - node _T_303 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_304 = and(io.wen2, _T_303) @[el2_dec_gpr_ctl.scala 28:28] - w2v[13] <= _T_304 @[el2_dec_gpr_ctl.scala 28:16] - node _T_305 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] - node _T_306 = mux(_T_305, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_307 = and(_T_306, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_308 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] - node _T_309 = mux(_T_308, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_310 = and(_T_309, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_311 = or(_T_307, _T_310) @[el2_dec_gpr_ctl.scala 29:47] - node _T_312 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_297 = and(_T_296, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_298 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_300 = and(_T_299, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_301 = or(_T_297, _T_300) @[el2_dec_gpr_ctl.scala 38:47] + node _T_302 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_303 = mux(_T_302, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_304 = and(_T_303, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_305 = or(_T_301, _T_304) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[18] <= _T_305 @[el2_dec_gpr_ctl.scala 38:16] + node _T_306 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_307 = and(io.wen0, _T_306) @[el2_dec_gpr_ctl.scala 35:28] + w0v[19] <= _T_307 @[el2_dec_gpr_ctl.scala 35:16] + node _T_308 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_309 = and(io.wen1, _T_308) @[el2_dec_gpr_ctl.scala 36:28] + w1v[19] <= _T_309 @[el2_dec_gpr_ctl.scala 36:16] + node _T_310 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_311 = and(io.wen2, _T_310) @[el2_dec_gpr_ctl.scala 37:28] + w2v[19] <= _T_311 @[el2_dec_gpr_ctl.scala 37:16] + node _T_312 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_314 = and(_T_313, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_315 = or(_T_311, _T_314) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[13] <= _T_315 @[el2_dec_gpr_ctl.scala 29:16] - node _T_316 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_317 = and(io.wen0, _T_316) @[el2_dec_gpr_ctl.scala 26:28] - w0v[14] <= _T_317 @[el2_dec_gpr_ctl.scala 26:16] - node _T_318 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_319 = and(io.wen1, _T_318) @[el2_dec_gpr_ctl.scala 27:28] - w1v[14] <= _T_319 @[el2_dec_gpr_ctl.scala 27:16] - node _T_320 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_321 = and(io.wen2, _T_320) @[el2_dec_gpr_ctl.scala 28:28] - w2v[14] <= _T_321 @[el2_dec_gpr_ctl.scala 28:16] - node _T_322 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] - node _T_323 = mux(_T_322, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_324 = and(_T_323, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_325 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] - node _T_326 = mux(_T_325, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_327 = and(_T_326, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_328 = or(_T_324, _T_327) @[el2_dec_gpr_ctl.scala 29:47] - node _T_329 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_314 = and(_T_313, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_315 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_316 = mux(_T_315, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_317 = and(_T_316, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_318 = or(_T_314, _T_317) @[el2_dec_gpr_ctl.scala 38:47] + node _T_319 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_320 = mux(_T_319, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_321 = and(_T_320, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_322 = or(_T_318, _T_321) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[19] <= _T_322 @[el2_dec_gpr_ctl.scala 38:16] + node _T_323 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_324 = and(io.wen0, _T_323) @[el2_dec_gpr_ctl.scala 35:28] + w0v[20] <= _T_324 @[el2_dec_gpr_ctl.scala 35:16] + node _T_325 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_326 = and(io.wen1, _T_325) @[el2_dec_gpr_ctl.scala 36:28] + w1v[20] <= _T_326 @[el2_dec_gpr_ctl.scala 36:16] + node _T_327 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_328 = and(io.wen2, _T_327) @[el2_dec_gpr_ctl.scala 37:28] + w2v[20] <= _T_328 @[el2_dec_gpr_ctl.scala 37:16] + node _T_329 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_331 = and(_T_330, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_332 = or(_T_328, _T_331) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[14] <= _T_332 @[el2_dec_gpr_ctl.scala 29:16] - node _T_333 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_334 = and(io.wen0, _T_333) @[el2_dec_gpr_ctl.scala 26:28] - w0v[15] <= _T_334 @[el2_dec_gpr_ctl.scala 26:16] - node _T_335 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_336 = and(io.wen1, _T_335) @[el2_dec_gpr_ctl.scala 27:28] - w1v[15] <= _T_336 @[el2_dec_gpr_ctl.scala 27:16] - node _T_337 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_338 = and(io.wen2, _T_337) @[el2_dec_gpr_ctl.scala 28:28] - w2v[15] <= _T_338 @[el2_dec_gpr_ctl.scala 28:16] - node _T_339 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] - node _T_340 = mux(_T_339, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_341 = and(_T_340, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_342 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] - node _T_343 = mux(_T_342, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_344 = and(_T_343, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_345 = or(_T_341, _T_344) @[el2_dec_gpr_ctl.scala 29:47] - node _T_346 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_331 = and(_T_330, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_332 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_333 = mux(_T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_334 = and(_T_333, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_335 = or(_T_331, _T_334) @[el2_dec_gpr_ctl.scala 38:47] + node _T_336 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_337 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_338 = and(_T_337, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_339 = or(_T_335, _T_338) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[20] <= _T_339 @[el2_dec_gpr_ctl.scala 38:16] + node _T_340 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_341 = and(io.wen0, _T_340) @[el2_dec_gpr_ctl.scala 35:28] + w0v[21] <= _T_341 @[el2_dec_gpr_ctl.scala 35:16] + node _T_342 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_343 = and(io.wen1, _T_342) @[el2_dec_gpr_ctl.scala 36:28] + w1v[21] <= _T_343 @[el2_dec_gpr_ctl.scala 36:16] + node _T_344 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_345 = and(io.wen2, _T_344) @[el2_dec_gpr_ctl.scala 37:28] + w2v[21] <= _T_345 @[el2_dec_gpr_ctl.scala 37:16] + node _T_346 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_348 = and(_T_347, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_349 = or(_T_345, _T_348) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[15] <= _T_349 @[el2_dec_gpr_ctl.scala 29:16] - node _T_350 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_351 = and(io.wen0, _T_350) @[el2_dec_gpr_ctl.scala 26:28] - w0v[16] <= _T_351 @[el2_dec_gpr_ctl.scala 26:16] - node _T_352 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_353 = and(io.wen1, _T_352) @[el2_dec_gpr_ctl.scala 27:28] - w1v[16] <= _T_353 @[el2_dec_gpr_ctl.scala 27:16] - node _T_354 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_355 = and(io.wen2, _T_354) @[el2_dec_gpr_ctl.scala 28:28] - w2v[16] <= _T_355 @[el2_dec_gpr_ctl.scala 28:16] - node _T_356 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] - node _T_357 = mux(_T_356, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_358 = and(_T_357, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_359 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] - node _T_360 = mux(_T_359, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_361 = and(_T_360, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_362 = or(_T_358, _T_361) @[el2_dec_gpr_ctl.scala 29:47] - node _T_363 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_348 = and(_T_347, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_349 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_350 = mux(_T_349, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_351 = and(_T_350, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_352 = or(_T_348, _T_351) @[el2_dec_gpr_ctl.scala 38:47] + node _T_353 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_354 = mux(_T_353, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_355 = and(_T_354, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_356 = or(_T_352, _T_355) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[21] <= _T_356 @[el2_dec_gpr_ctl.scala 38:16] + node _T_357 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_358 = and(io.wen0, _T_357) @[el2_dec_gpr_ctl.scala 35:28] + w0v[22] <= _T_358 @[el2_dec_gpr_ctl.scala 35:16] + node _T_359 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_360 = and(io.wen1, _T_359) @[el2_dec_gpr_ctl.scala 36:28] + w1v[22] <= _T_360 @[el2_dec_gpr_ctl.scala 36:16] + node _T_361 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_362 = and(io.wen2, _T_361) @[el2_dec_gpr_ctl.scala 37:28] + w2v[22] <= _T_362 @[el2_dec_gpr_ctl.scala 37:16] + node _T_363 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_365 = and(_T_364, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_366 = or(_T_362, _T_365) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[16] <= _T_366 @[el2_dec_gpr_ctl.scala 29:16] - node _T_367 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_368 = and(io.wen0, _T_367) @[el2_dec_gpr_ctl.scala 26:28] - w0v[17] <= _T_368 @[el2_dec_gpr_ctl.scala 26:16] - node _T_369 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_370 = and(io.wen1, _T_369) @[el2_dec_gpr_ctl.scala 27:28] - w1v[17] <= _T_370 @[el2_dec_gpr_ctl.scala 27:16] - node _T_371 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_372 = and(io.wen2, _T_371) @[el2_dec_gpr_ctl.scala 28:28] - w2v[17] <= _T_372 @[el2_dec_gpr_ctl.scala 28:16] - node _T_373 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] - node _T_374 = mux(_T_373, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_375 = and(_T_374, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_376 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] - node _T_377 = mux(_T_376, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_378 = and(_T_377, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_379 = or(_T_375, _T_378) @[el2_dec_gpr_ctl.scala 29:47] - node _T_380 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_365 = and(_T_364, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_366 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_367 = mux(_T_366, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_368 = and(_T_367, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_369 = or(_T_365, _T_368) @[el2_dec_gpr_ctl.scala 38:47] + node _T_370 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_371 = mux(_T_370, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_372 = and(_T_371, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_373 = or(_T_369, _T_372) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[22] <= _T_373 @[el2_dec_gpr_ctl.scala 38:16] + node _T_374 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_375 = and(io.wen0, _T_374) @[el2_dec_gpr_ctl.scala 35:28] + w0v[23] <= _T_375 @[el2_dec_gpr_ctl.scala 35:16] + node _T_376 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_377 = and(io.wen1, _T_376) @[el2_dec_gpr_ctl.scala 36:28] + w1v[23] <= _T_377 @[el2_dec_gpr_ctl.scala 36:16] + node _T_378 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_379 = and(io.wen2, _T_378) @[el2_dec_gpr_ctl.scala 37:28] + w2v[23] <= _T_379 @[el2_dec_gpr_ctl.scala 37:16] + node _T_380 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_382 = and(_T_381, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_383 = or(_T_379, _T_382) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[17] <= _T_383 @[el2_dec_gpr_ctl.scala 29:16] - node _T_384 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_385 = and(io.wen0, _T_384) @[el2_dec_gpr_ctl.scala 26:28] - w0v[18] <= _T_385 @[el2_dec_gpr_ctl.scala 26:16] - node _T_386 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_387 = and(io.wen1, _T_386) @[el2_dec_gpr_ctl.scala 27:28] - w1v[18] <= _T_387 @[el2_dec_gpr_ctl.scala 27:16] - node _T_388 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_389 = and(io.wen2, _T_388) @[el2_dec_gpr_ctl.scala 28:28] - w2v[18] <= _T_389 @[el2_dec_gpr_ctl.scala 28:16] - node _T_390 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] - node _T_391 = mux(_T_390, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_392 = and(_T_391, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_393 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] - node _T_394 = mux(_T_393, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_395 = and(_T_394, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_396 = or(_T_392, _T_395) @[el2_dec_gpr_ctl.scala 29:47] - node _T_397 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_382 = and(_T_381, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_383 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_384 = mux(_T_383, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_385 = and(_T_384, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_386 = or(_T_382, _T_385) @[el2_dec_gpr_ctl.scala 38:47] + node _T_387 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_388 = mux(_T_387, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_389 = and(_T_388, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_390 = or(_T_386, _T_389) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[23] <= _T_390 @[el2_dec_gpr_ctl.scala 38:16] + node _T_391 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_392 = and(io.wen0, _T_391) @[el2_dec_gpr_ctl.scala 35:28] + w0v[24] <= _T_392 @[el2_dec_gpr_ctl.scala 35:16] + node _T_393 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_394 = and(io.wen1, _T_393) @[el2_dec_gpr_ctl.scala 36:28] + w1v[24] <= _T_394 @[el2_dec_gpr_ctl.scala 36:16] + node _T_395 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_396 = and(io.wen2, _T_395) @[el2_dec_gpr_ctl.scala 37:28] + w2v[24] <= _T_396 @[el2_dec_gpr_ctl.scala 37:16] + node _T_397 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_399 = and(_T_398, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_400 = or(_T_396, _T_399) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[18] <= _T_400 @[el2_dec_gpr_ctl.scala 29:16] - node _T_401 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_402 = and(io.wen0, _T_401) @[el2_dec_gpr_ctl.scala 26:28] - w0v[19] <= _T_402 @[el2_dec_gpr_ctl.scala 26:16] - node _T_403 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_404 = and(io.wen1, _T_403) @[el2_dec_gpr_ctl.scala 27:28] - w1v[19] <= _T_404 @[el2_dec_gpr_ctl.scala 27:16] - node _T_405 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_406 = and(io.wen2, _T_405) @[el2_dec_gpr_ctl.scala 28:28] - w2v[19] <= _T_406 @[el2_dec_gpr_ctl.scala 28:16] - node _T_407 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] - node _T_408 = mux(_T_407, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_409 = and(_T_408, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_410 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] - node _T_411 = mux(_T_410, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_412 = and(_T_411, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_413 = or(_T_409, _T_412) @[el2_dec_gpr_ctl.scala 29:47] - node _T_414 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_399 = and(_T_398, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_400 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_401 = mux(_T_400, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_402 = and(_T_401, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_403 = or(_T_399, _T_402) @[el2_dec_gpr_ctl.scala 38:47] + node _T_404 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_406 = and(_T_405, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_407 = or(_T_403, _T_406) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[24] <= _T_407 @[el2_dec_gpr_ctl.scala 38:16] + node _T_408 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_409 = and(io.wen0, _T_408) @[el2_dec_gpr_ctl.scala 35:28] + w0v[25] <= _T_409 @[el2_dec_gpr_ctl.scala 35:16] + node _T_410 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_411 = and(io.wen1, _T_410) @[el2_dec_gpr_ctl.scala 36:28] + w1v[25] <= _T_411 @[el2_dec_gpr_ctl.scala 36:16] + node _T_412 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_413 = and(io.wen2, _T_412) @[el2_dec_gpr_ctl.scala 37:28] + w2v[25] <= _T_413 @[el2_dec_gpr_ctl.scala 37:16] + node _T_414 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_416 = and(_T_415, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_417 = or(_T_413, _T_416) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[19] <= _T_417 @[el2_dec_gpr_ctl.scala 29:16] - node _T_418 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_419 = and(io.wen0, _T_418) @[el2_dec_gpr_ctl.scala 26:28] - w0v[20] <= _T_419 @[el2_dec_gpr_ctl.scala 26:16] - node _T_420 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_421 = and(io.wen1, _T_420) @[el2_dec_gpr_ctl.scala 27:28] - w1v[20] <= _T_421 @[el2_dec_gpr_ctl.scala 27:16] - node _T_422 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_423 = and(io.wen2, _T_422) @[el2_dec_gpr_ctl.scala 28:28] - w2v[20] <= _T_423 @[el2_dec_gpr_ctl.scala 28:16] - node _T_424 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] - node _T_425 = mux(_T_424, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_426 = and(_T_425, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_427 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] - node _T_428 = mux(_T_427, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_429 = and(_T_428, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_430 = or(_T_426, _T_429) @[el2_dec_gpr_ctl.scala 29:47] - node _T_431 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_416 = and(_T_415, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_417 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_418 = mux(_T_417, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_419 = and(_T_418, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_420 = or(_T_416, _T_419) @[el2_dec_gpr_ctl.scala 38:47] + node _T_421 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_422 = mux(_T_421, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_423 = and(_T_422, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_424 = or(_T_420, _T_423) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[25] <= _T_424 @[el2_dec_gpr_ctl.scala 38:16] + node _T_425 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_426 = and(io.wen0, _T_425) @[el2_dec_gpr_ctl.scala 35:28] + w0v[26] <= _T_426 @[el2_dec_gpr_ctl.scala 35:16] + node _T_427 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_428 = and(io.wen1, _T_427) @[el2_dec_gpr_ctl.scala 36:28] + w1v[26] <= _T_428 @[el2_dec_gpr_ctl.scala 36:16] + node _T_429 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_430 = and(io.wen2, _T_429) @[el2_dec_gpr_ctl.scala 37:28] + w2v[26] <= _T_430 @[el2_dec_gpr_ctl.scala 37:16] + node _T_431 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_433 = and(_T_432, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_434 = or(_T_430, _T_433) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[20] <= _T_434 @[el2_dec_gpr_ctl.scala 29:16] - node _T_435 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_436 = and(io.wen0, _T_435) @[el2_dec_gpr_ctl.scala 26:28] - w0v[21] <= _T_436 @[el2_dec_gpr_ctl.scala 26:16] - node _T_437 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_438 = and(io.wen1, _T_437) @[el2_dec_gpr_ctl.scala 27:28] - w1v[21] <= _T_438 @[el2_dec_gpr_ctl.scala 27:16] - node _T_439 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_440 = and(io.wen2, _T_439) @[el2_dec_gpr_ctl.scala 28:28] - w2v[21] <= _T_440 @[el2_dec_gpr_ctl.scala 28:16] - node _T_441 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] - node _T_442 = mux(_T_441, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_443 = and(_T_442, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_444 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] - node _T_445 = mux(_T_444, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_446 = and(_T_445, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_447 = or(_T_443, _T_446) @[el2_dec_gpr_ctl.scala 29:47] - node _T_448 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_433 = and(_T_432, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_434 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_436 = and(_T_435, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_437 = or(_T_433, _T_436) @[el2_dec_gpr_ctl.scala 38:47] + node _T_438 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_441 = or(_T_437, _T_440) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[26] <= _T_441 @[el2_dec_gpr_ctl.scala 38:16] + node _T_442 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_443 = and(io.wen0, _T_442) @[el2_dec_gpr_ctl.scala 35:28] + w0v[27] <= _T_443 @[el2_dec_gpr_ctl.scala 35:16] + node _T_444 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_445 = and(io.wen1, _T_444) @[el2_dec_gpr_ctl.scala 36:28] + w1v[27] <= _T_445 @[el2_dec_gpr_ctl.scala 36:16] + node _T_446 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_447 = and(io.wen2, _T_446) @[el2_dec_gpr_ctl.scala 37:28] + w2v[27] <= _T_447 @[el2_dec_gpr_ctl.scala 37:16] + node _T_448 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_450 = and(_T_449, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_451 = or(_T_447, _T_450) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[21] <= _T_451 @[el2_dec_gpr_ctl.scala 29:16] - node _T_452 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_453 = and(io.wen0, _T_452) @[el2_dec_gpr_ctl.scala 26:28] - w0v[22] <= _T_453 @[el2_dec_gpr_ctl.scala 26:16] - node _T_454 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_455 = and(io.wen1, _T_454) @[el2_dec_gpr_ctl.scala 27:28] - w1v[22] <= _T_455 @[el2_dec_gpr_ctl.scala 27:16] - node _T_456 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_457 = and(io.wen2, _T_456) @[el2_dec_gpr_ctl.scala 28:28] - w2v[22] <= _T_457 @[el2_dec_gpr_ctl.scala 28:16] - node _T_458 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] - node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_460 = and(_T_459, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_461 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] - node _T_462 = mux(_T_461, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_463 = and(_T_462, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_464 = or(_T_460, _T_463) @[el2_dec_gpr_ctl.scala 29:47] - node _T_465 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_450 = and(_T_449, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_451 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_452 = mux(_T_451, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_453 = and(_T_452, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_454 = or(_T_450, _T_453) @[el2_dec_gpr_ctl.scala 38:47] + node _T_455 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(_T_456, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_458 = or(_T_454, _T_457) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[27] <= _T_458 @[el2_dec_gpr_ctl.scala 38:16] + node _T_459 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_460 = and(io.wen0, _T_459) @[el2_dec_gpr_ctl.scala 35:28] + w0v[28] <= _T_460 @[el2_dec_gpr_ctl.scala 35:16] + node _T_461 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_462 = and(io.wen1, _T_461) @[el2_dec_gpr_ctl.scala 36:28] + w1v[28] <= _T_462 @[el2_dec_gpr_ctl.scala 36:16] + node _T_463 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_464 = and(io.wen2, _T_463) @[el2_dec_gpr_ctl.scala 37:28] + w2v[28] <= _T_464 @[el2_dec_gpr_ctl.scala 37:16] + node _T_465 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_467 = and(_T_466, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_468 = or(_T_464, _T_467) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[22] <= _T_468 @[el2_dec_gpr_ctl.scala 29:16] - node _T_469 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_470 = and(io.wen0, _T_469) @[el2_dec_gpr_ctl.scala 26:28] - w0v[23] <= _T_470 @[el2_dec_gpr_ctl.scala 26:16] - node _T_471 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_472 = and(io.wen1, _T_471) @[el2_dec_gpr_ctl.scala 27:28] - w1v[23] <= _T_472 @[el2_dec_gpr_ctl.scala 27:16] - node _T_473 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_474 = and(io.wen2, _T_473) @[el2_dec_gpr_ctl.scala 28:28] - w2v[23] <= _T_474 @[el2_dec_gpr_ctl.scala 28:16] - node _T_475 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(_T_476, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_478 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] - node _T_479 = mux(_T_478, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_480 = and(_T_479, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_481 = or(_T_477, _T_480) @[el2_dec_gpr_ctl.scala 29:47] - node _T_482 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_467 = and(_T_466, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_468 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_470 = and(_T_469, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_471 = or(_T_467, _T_470) @[el2_dec_gpr_ctl.scala 38:47] + node _T_472 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_473 = mux(_T_472, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_474 = and(_T_473, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_475 = or(_T_471, _T_474) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[28] <= _T_475 @[el2_dec_gpr_ctl.scala 38:16] + node _T_476 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_477 = and(io.wen0, _T_476) @[el2_dec_gpr_ctl.scala 35:28] + w0v[29] <= _T_477 @[el2_dec_gpr_ctl.scala 35:16] + node _T_478 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_479 = and(io.wen1, _T_478) @[el2_dec_gpr_ctl.scala 36:28] + w1v[29] <= _T_479 @[el2_dec_gpr_ctl.scala 36:16] + node _T_480 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_481 = and(io.wen2, _T_480) @[el2_dec_gpr_ctl.scala 37:28] + w2v[29] <= _T_481 @[el2_dec_gpr_ctl.scala 37:16] + node _T_482 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_484 = and(_T_483, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_485 = or(_T_481, _T_484) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[23] <= _T_485 @[el2_dec_gpr_ctl.scala 29:16] - node _T_486 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_487 = and(io.wen0, _T_486) @[el2_dec_gpr_ctl.scala 26:28] - w0v[24] <= _T_487 @[el2_dec_gpr_ctl.scala 26:16] - node _T_488 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_489 = and(io.wen1, _T_488) @[el2_dec_gpr_ctl.scala 27:28] - w1v[24] <= _T_489 @[el2_dec_gpr_ctl.scala 27:16] - node _T_490 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_491 = and(io.wen2, _T_490) @[el2_dec_gpr_ctl.scala 28:28] - w2v[24] <= _T_491 @[el2_dec_gpr_ctl.scala 28:16] - node _T_492 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] - node _T_493 = mux(_T_492, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_494 = and(_T_493, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_495 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] - node _T_496 = mux(_T_495, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_497 = and(_T_496, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_498 = or(_T_494, _T_497) @[el2_dec_gpr_ctl.scala 29:47] - node _T_499 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_484 = and(_T_483, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_485 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_486 = mux(_T_485, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_487 = and(_T_486, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_488 = or(_T_484, _T_487) @[el2_dec_gpr_ctl.scala 38:47] + node _T_489 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_490 = mux(_T_489, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_491 = and(_T_490, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_492 = or(_T_488, _T_491) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[29] <= _T_492 @[el2_dec_gpr_ctl.scala 38:16] + node _T_493 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_494 = and(io.wen0, _T_493) @[el2_dec_gpr_ctl.scala 35:28] + w0v[30] <= _T_494 @[el2_dec_gpr_ctl.scala 35:16] + node _T_495 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_496 = and(io.wen1, _T_495) @[el2_dec_gpr_ctl.scala 36:28] + w1v[30] <= _T_496 @[el2_dec_gpr_ctl.scala 36:16] + node _T_497 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_498 = and(io.wen2, _T_497) @[el2_dec_gpr_ctl.scala 37:28] + w2v[30] <= _T_498 @[el2_dec_gpr_ctl.scala 37:16] + node _T_499 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_501 = and(_T_500, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_502 = or(_T_498, _T_501) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[24] <= _T_502 @[el2_dec_gpr_ctl.scala 29:16] - node _T_503 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_504 = and(io.wen0, _T_503) @[el2_dec_gpr_ctl.scala 26:28] - w0v[25] <= _T_504 @[el2_dec_gpr_ctl.scala 26:16] - node _T_505 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_506 = and(io.wen1, _T_505) @[el2_dec_gpr_ctl.scala 27:28] - w1v[25] <= _T_506 @[el2_dec_gpr_ctl.scala 27:16] - node _T_507 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_508 = and(io.wen2, _T_507) @[el2_dec_gpr_ctl.scala 28:28] - w2v[25] <= _T_508 @[el2_dec_gpr_ctl.scala 28:16] - node _T_509 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] - node _T_510 = mux(_T_509, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_511 = and(_T_510, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_512 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] - node _T_513 = mux(_T_512, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_514 = and(_T_513, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_515 = or(_T_511, _T_514) @[el2_dec_gpr_ctl.scala 29:47] - node _T_516 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_501 = and(_T_500, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_502 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_503 = mux(_T_502, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_504 = and(_T_503, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_505 = or(_T_501, _T_504) @[el2_dec_gpr_ctl.scala 38:47] + node _T_506 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_508 = and(_T_507, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_509 = or(_T_505, _T_508) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[30] <= _T_509 @[el2_dec_gpr_ctl.scala 38:16] + node _T_510 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_511 = and(io.wen0, _T_510) @[el2_dec_gpr_ctl.scala 35:28] + w0v[31] <= _T_511 @[el2_dec_gpr_ctl.scala 35:16] + node _T_512 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_513 = and(io.wen1, _T_512) @[el2_dec_gpr_ctl.scala 36:28] + w1v[31] <= _T_513 @[el2_dec_gpr_ctl.scala 36:16] + node _T_514 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_515 = and(io.wen2, _T_514) @[el2_dec_gpr_ctl.scala 37:28] + w2v[31] <= _T_515 @[el2_dec_gpr_ctl.scala 37:16] + node _T_516 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_518 = and(_T_517, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_519 = or(_T_515, _T_518) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[25] <= _T_519 @[el2_dec_gpr_ctl.scala 29:16] - node _T_520 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_521 = and(io.wen0, _T_520) @[el2_dec_gpr_ctl.scala 26:28] - w0v[26] <= _T_521 @[el2_dec_gpr_ctl.scala 26:16] - node _T_522 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_523 = and(io.wen1, _T_522) @[el2_dec_gpr_ctl.scala 27:28] - w1v[26] <= _T_523 @[el2_dec_gpr_ctl.scala 27:16] - node _T_524 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_525 = and(io.wen2, _T_524) @[el2_dec_gpr_ctl.scala 28:28] - w2v[26] <= _T_525 @[el2_dec_gpr_ctl.scala 28:16] - node _T_526 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(_T_527, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_529 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] - node _T_530 = mux(_T_529, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_531 = and(_T_530, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_532 = or(_T_528, _T_531) @[el2_dec_gpr_ctl.scala 29:47] - node _T_533 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] - node _T_534 = mux(_T_533, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_535 = and(_T_534, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_536 = or(_T_532, _T_535) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[26] <= _T_536 @[el2_dec_gpr_ctl.scala 29:16] - node _T_537 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_538 = and(io.wen0, _T_537) @[el2_dec_gpr_ctl.scala 26:28] - w0v[27] <= _T_538 @[el2_dec_gpr_ctl.scala 26:16] - node _T_539 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_540 = and(io.wen1, _T_539) @[el2_dec_gpr_ctl.scala 27:28] - w1v[27] <= _T_540 @[el2_dec_gpr_ctl.scala 27:16] - node _T_541 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_542 = and(io.wen2, _T_541) @[el2_dec_gpr_ctl.scala 28:28] - w2v[27] <= _T_542 @[el2_dec_gpr_ctl.scala 28:16] - node _T_543 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] - node _T_544 = mux(_T_543, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_545 = and(_T_544, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_546 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] - node _T_547 = mux(_T_546, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_548 = and(_T_547, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_549 = or(_T_545, _T_548) @[el2_dec_gpr_ctl.scala 29:47] - node _T_550 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] - node _T_551 = mux(_T_550, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_552 = and(_T_551, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_553 = or(_T_549, _T_552) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[27] <= _T_553 @[el2_dec_gpr_ctl.scala 29:16] - node _T_554 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_555 = and(io.wen0, _T_554) @[el2_dec_gpr_ctl.scala 26:28] - w0v[28] <= _T_555 @[el2_dec_gpr_ctl.scala 26:16] - node _T_556 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_557 = and(io.wen1, _T_556) @[el2_dec_gpr_ctl.scala 27:28] - w1v[28] <= _T_557 @[el2_dec_gpr_ctl.scala 27:16] - node _T_558 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_559 = and(io.wen2, _T_558) @[el2_dec_gpr_ctl.scala 28:28] - w2v[28] <= _T_559 @[el2_dec_gpr_ctl.scala 28:16] - node _T_560 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] - node _T_561 = mux(_T_560, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_562 = and(_T_561, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_563 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] - node _T_564 = mux(_T_563, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_565 = and(_T_564, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_566 = or(_T_562, _T_565) @[el2_dec_gpr_ctl.scala 29:47] - node _T_567 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] - node _T_568 = mux(_T_567, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_569 = and(_T_568, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_570 = or(_T_566, _T_569) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[28] <= _T_570 @[el2_dec_gpr_ctl.scala 29:16] - node _T_571 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_572 = and(io.wen0, _T_571) @[el2_dec_gpr_ctl.scala 26:28] - w0v[29] <= _T_572 @[el2_dec_gpr_ctl.scala 26:16] - node _T_573 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_574 = and(io.wen1, _T_573) @[el2_dec_gpr_ctl.scala 27:28] - w1v[29] <= _T_574 @[el2_dec_gpr_ctl.scala 27:16] - node _T_575 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_576 = and(io.wen2, _T_575) @[el2_dec_gpr_ctl.scala 28:28] - w2v[29] <= _T_576 @[el2_dec_gpr_ctl.scala 28:16] - node _T_577 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] - node _T_578 = mux(_T_577, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_579 = and(_T_578, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_580 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] - node _T_581 = mux(_T_580, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_582 = and(_T_581, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_583 = or(_T_579, _T_582) @[el2_dec_gpr_ctl.scala 29:47] - node _T_584 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] - node _T_585 = mux(_T_584, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_586 = and(_T_585, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_587 = or(_T_583, _T_586) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[29] <= _T_587 @[el2_dec_gpr_ctl.scala 29:16] - node _T_588 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_589 = and(io.wen0, _T_588) @[el2_dec_gpr_ctl.scala 26:28] - w0v[30] <= _T_589 @[el2_dec_gpr_ctl.scala 26:16] - node _T_590 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_591 = and(io.wen1, _T_590) @[el2_dec_gpr_ctl.scala 27:28] - w1v[30] <= _T_591 @[el2_dec_gpr_ctl.scala 27:16] - node _T_592 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_593 = and(io.wen2, _T_592) @[el2_dec_gpr_ctl.scala 28:28] - w2v[30] <= _T_593 @[el2_dec_gpr_ctl.scala 28:16] - node _T_594 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] - node _T_595 = mux(_T_594, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_596 = and(_T_595, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_597 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_600 = or(_T_596, _T_599) @[el2_dec_gpr_ctl.scala 29:47] - node _T_601 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] - node _T_602 = mux(_T_601, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_603 = and(_T_602, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_604 = or(_T_600, _T_603) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[30] <= _T_604 @[el2_dec_gpr_ctl.scala 29:16] - node _T_605 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_606 = and(io.wen0, _T_605) @[el2_dec_gpr_ctl.scala 26:28] - w0v[31] <= _T_606 @[el2_dec_gpr_ctl.scala 26:16] - node _T_607 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_608 = and(io.wen1, _T_607) @[el2_dec_gpr_ctl.scala 27:28] - w1v[31] <= _T_608 @[el2_dec_gpr_ctl.scala 27:16] - node _T_609 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_610 = and(io.wen2, _T_609) @[el2_dec_gpr_ctl.scala 28:28] - w2v[31] <= _T_610 @[el2_dec_gpr_ctl.scala 28:16] - node _T_611 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] - node _T_612 = mux(_T_611, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_613 = and(_T_612, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_614 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] - node _T_615 = mux(_T_614, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_616 = and(_T_615, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_617 = or(_T_613, _T_616) @[el2_dec_gpr_ctl.scala 29:47] - node _T_618 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] - node _T_619 = mux(_T_618, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_620 = and(_T_619, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_621 = or(_T_617, _T_620) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[31] <= _T_621 @[el2_dec_gpr_ctl.scala 29:16] - node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 33:43] + node _T_518 = and(_T_517, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_519 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_520 = mux(_T_519, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_521 = and(_T_520, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_522 = or(_T_518, _T_521) @[el2_dec_gpr_ctl.scala 38:47] + node _T_523 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_524 = mux(_T_523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_525 = and(_T_524, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_526 = or(_T_522, _T_525) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[31] <= _T_526 @[el2_dec_gpr_ctl.scala 38:16] + node _T_527 = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] + node _T_528 = cat(w0v[2], _T_527) @[Cat.scala 29:58] + node _T_529 = cat(w0v[3], _T_528) @[Cat.scala 29:58] + node _T_530 = cat(w0v[4], _T_529) @[Cat.scala 29:58] + node _T_531 = cat(w0v[5], _T_530) @[Cat.scala 29:58] + node _T_532 = cat(w0v[6], _T_531) @[Cat.scala 29:58] + node _T_533 = cat(w0v[7], _T_532) @[Cat.scala 29:58] + node _T_534 = cat(w0v[8], _T_533) @[Cat.scala 29:58] + node _T_535 = cat(w0v[9], _T_534) @[Cat.scala 29:58] + node _T_536 = cat(w0v[10], _T_535) @[Cat.scala 29:58] + node _T_537 = cat(w0v[11], _T_536) @[Cat.scala 29:58] + node _T_538 = cat(w0v[12], _T_537) @[Cat.scala 29:58] + node _T_539 = cat(w0v[13], _T_538) @[Cat.scala 29:58] + node _T_540 = cat(w0v[14], _T_539) @[Cat.scala 29:58] + node _T_541 = cat(w0v[15], _T_540) @[Cat.scala 29:58] + node _T_542 = cat(w0v[16], _T_541) @[Cat.scala 29:58] + node _T_543 = cat(w0v[17], _T_542) @[Cat.scala 29:58] + node _T_544 = cat(w0v[18], _T_543) @[Cat.scala 29:58] + node _T_545 = cat(w0v[19], _T_544) @[Cat.scala 29:58] + node _T_546 = cat(w0v[20], _T_545) @[Cat.scala 29:58] + node _T_547 = cat(w0v[21], _T_546) @[Cat.scala 29:58] + node _T_548 = cat(w0v[22], _T_547) @[Cat.scala 29:58] + node _T_549 = cat(w0v[23], _T_548) @[Cat.scala 29:58] + node _T_550 = cat(w0v[24], _T_549) @[Cat.scala 29:58] + node _T_551 = cat(w0v[25], _T_550) @[Cat.scala 29:58] + node _T_552 = cat(w0v[26], _T_551) @[Cat.scala 29:58] + node _T_553 = cat(w0v[27], _T_552) @[Cat.scala 29:58] + node _T_554 = cat(w0v[28], _T_553) @[Cat.scala 29:58] + node _T_555 = cat(w0v[29], _T_554) @[Cat.scala 29:58] + node _T_556 = cat(w0v[30], _T_555) @[Cat.scala 29:58] + node _T_557 = cat(w0v[31], _T_556) @[Cat.scala 29:58] + node _T_558 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] + node _T_559 = cat(w1v[2], _T_558) @[Cat.scala 29:58] + node _T_560 = cat(w1v[3], _T_559) @[Cat.scala 29:58] + node _T_561 = cat(w1v[4], _T_560) @[Cat.scala 29:58] + node _T_562 = cat(w1v[5], _T_561) @[Cat.scala 29:58] + node _T_563 = cat(w1v[6], _T_562) @[Cat.scala 29:58] + node _T_564 = cat(w1v[7], _T_563) @[Cat.scala 29:58] + node _T_565 = cat(w1v[8], _T_564) @[Cat.scala 29:58] + node _T_566 = cat(w1v[9], _T_565) @[Cat.scala 29:58] + node _T_567 = cat(w1v[10], _T_566) @[Cat.scala 29:58] + node _T_568 = cat(w1v[11], _T_567) @[Cat.scala 29:58] + node _T_569 = cat(w1v[12], _T_568) @[Cat.scala 29:58] + node _T_570 = cat(w1v[13], _T_569) @[Cat.scala 29:58] + node _T_571 = cat(w1v[14], _T_570) @[Cat.scala 29:58] + node _T_572 = cat(w1v[15], _T_571) @[Cat.scala 29:58] + node _T_573 = cat(w1v[16], _T_572) @[Cat.scala 29:58] + node _T_574 = cat(w1v[17], _T_573) @[Cat.scala 29:58] + node _T_575 = cat(w1v[18], _T_574) @[Cat.scala 29:58] + node _T_576 = cat(w1v[19], _T_575) @[Cat.scala 29:58] + node _T_577 = cat(w1v[20], _T_576) @[Cat.scala 29:58] + node _T_578 = cat(w1v[21], _T_577) @[Cat.scala 29:58] + node _T_579 = cat(w1v[22], _T_578) @[Cat.scala 29:58] + node _T_580 = cat(w1v[23], _T_579) @[Cat.scala 29:58] + node _T_581 = cat(w1v[24], _T_580) @[Cat.scala 29:58] + node _T_582 = cat(w1v[25], _T_581) @[Cat.scala 29:58] + node _T_583 = cat(w1v[26], _T_582) @[Cat.scala 29:58] + node _T_584 = cat(w1v[27], _T_583) @[Cat.scala 29:58] + node _T_585 = cat(w1v[28], _T_584) @[Cat.scala 29:58] + node _T_586 = cat(w1v[29], _T_585) @[Cat.scala 29:58] + node _T_587 = cat(w1v[30], _T_586) @[Cat.scala 29:58] + node _T_588 = cat(w1v[31], _T_587) @[Cat.scala 29:58] + node _T_589 = or(_T_557, _T_588) @[el2_dec_gpr_ctl.scala 40:51] + node _T_590 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] + node _T_591 = cat(w2v[2], _T_590) @[Cat.scala 29:58] + node _T_592 = cat(w2v[3], _T_591) @[Cat.scala 29:58] + node _T_593 = cat(w2v[4], _T_592) @[Cat.scala 29:58] + node _T_594 = cat(w2v[5], _T_593) @[Cat.scala 29:58] + node _T_595 = cat(w2v[6], _T_594) @[Cat.scala 29:58] + node _T_596 = cat(w2v[7], _T_595) @[Cat.scala 29:58] + node _T_597 = cat(w2v[8], _T_596) @[Cat.scala 29:58] + node _T_598 = cat(w2v[9], _T_597) @[Cat.scala 29:58] + node _T_599 = cat(w2v[10], _T_598) @[Cat.scala 29:58] + node _T_600 = cat(w2v[11], _T_599) @[Cat.scala 29:58] + node _T_601 = cat(w2v[12], _T_600) @[Cat.scala 29:58] + node _T_602 = cat(w2v[13], _T_601) @[Cat.scala 29:58] + node _T_603 = cat(w2v[14], _T_602) @[Cat.scala 29:58] + node _T_604 = cat(w2v[15], _T_603) @[Cat.scala 29:58] + node _T_605 = cat(w2v[16], _T_604) @[Cat.scala 29:58] + node _T_606 = cat(w2v[17], _T_605) @[Cat.scala 29:58] + node _T_607 = cat(w2v[18], _T_606) @[Cat.scala 29:58] + node _T_608 = cat(w2v[19], _T_607) @[Cat.scala 29:58] + node _T_609 = cat(w2v[20], _T_608) @[Cat.scala 29:58] + node _T_610 = cat(w2v[21], _T_609) @[Cat.scala 29:58] + node _T_611 = cat(w2v[22], _T_610) @[Cat.scala 29:58] + node _T_612 = cat(w2v[23], _T_611) @[Cat.scala 29:58] + node _T_613 = cat(w2v[24], _T_612) @[Cat.scala 29:58] + node _T_614 = cat(w2v[25], _T_613) @[Cat.scala 29:58] + node _T_615 = cat(w2v[26], _T_614) @[Cat.scala 29:58] + node _T_616 = cat(w2v[27], _T_615) @[Cat.scala 29:58] + node _T_617 = cat(w2v[28], _T_616) @[Cat.scala 29:58] + node _T_618 = cat(w2v[29], _T_617) @[Cat.scala 29:58] + node _T_619 = cat(w2v[30], _T_618) @[Cat.scala 29:58] + node _T_620 = cat(w2v[31], _T_619) @[Cat.scala 29:58] + node _T_621 = or(_T_589, _T_620) @[el2_dec_gpr_ctl.scala 40:89] + gpr_wr_en <= _T_621 @[el2_dec_gpr_ctl.scala 40:12] + node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr of rvclkhdr_681 @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -70746,8 +70890,8 @@ circuit el2_swerv : rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_623 <= gpr_in[1] @[el2_lib.scala 514:16] - gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 33:15] - node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 44:15] + node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_1 of rvclkhdr_682 @[el2_lib.scala 508:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -70756,8 +70900,8 @@ circuit el2_swerv : rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_625 <= gpr_in[2] @[el2_lib.scala 514:16] - gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 33:15] - node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 44:15] + node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_2 of rvclkhdr_683 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -70766,8 +70910,8 @@ circuit el2_swerv : rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_627 <= gpr_in[3] @[el2_lib.scala 514:16] - gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 33:15] - node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 44:15] + node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_3 of rvclkhdr_684 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -70776,8 +70920,8 @@ circuit el2_swerv : rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_629 <= gpr_in[4] @[el2_lib.scala 514:16] - gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 33:15] - node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 44:15] + node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_4 of rvclkhdr_685 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -70786,8 +70930,8 @@ circuit el2_swerv : rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_631 <= gpr_in[5] @[el2_lib.scala 514:16] - gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 33:15] - node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 44:15] + node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_5 of rvclkhdr_686 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -70796,8 +70940,8 @@ circuit el2_swerv : rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_633 <= gpr_in[6] @[el2_lib.scala 514:16] - gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 33:15] - node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 44:15] + node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_6 of rvclkhdr_687 @[el2_lib.scala 508:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -70806,8 +70950,8 @@ circuit el2_swerv : rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_635 <= gpr_in[7] @[el2_lib.scala 514:16] - gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 33:15] - node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 44:15] + node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_7 of rvclkhdr_688 @[el2_lib.scala 508:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -70816,8 +70960,8 @@ circuit el2_swerv : rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_637 <= gpr_in[8] @[el2_lib.scala 514:16] - gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 33:15] - node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 44:15] + node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_8 of rvclkhdr_689 @[el2_lib.scala 508:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -70826,8 +70970,8 @@ circuit el2_swerv : rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_639 <= gpr_in[9] @[el2_lib.scala 514:16] - gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 33:15] - node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 44:15] + node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_9 of rvclkhdr_690 @[el2_lib.scala 508:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -70836,8 +70980,8 @@ circuit el2_swerv : rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_641 <= gpr_in[10] @[el2_lib.scala 514:16] - gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 33:15] - node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 44:15] + node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_10 of rvclkhdr_691 @[el2_lib.scala 508:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -70846,8 +70990,8 @@ circuit el2_swerv : rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_643 <= gpr_in[11] @[el2_lib.scala 514:16] - gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 33:15] - node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 44:15] + node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_11 of rvclkhdr_692 @[el2_lib.scala 508:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset @@ -70856,8 +71000,8 @@ circuit el2_swerv : rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_645 <= gpr_in[12] @[el2_lib.scala 514:16] - gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 33:15] - node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 44:15] + node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_12 of rvclkhdr_693 @[el2_lib.scala 508:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset @@ -70866,8 +71010,8 @@ circuit el2_swerv : rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_647 <= gpr_in[13] @[el2_lib.scala 514:16] - gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 33:15] - node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 44:15] + node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_13 of rvclkhdr_694 @[el2_lib.scala 508:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset @@ -70876,8 +71020,8 @@ circuit el2_swerv : rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_649 <= gpr_in[14] @[el2_lib.scala 514:16] - gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 33:15] - node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 44:15] + node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_14 of rvclkhdr_695 @[el2_lib.scala 508:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset @@ -70886,8 +71030,8 @@ circuit el2_swerv : rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_651 <= gpr_in[15] @[el2_lib.scala 514:16] - gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 33:15] - node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 44:15] + node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_15 of rvclkhdr_696 @[el2_lib.scala 508:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset @@ -70896,8 +71040,8 @@ circuit el2_swerv : rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_653 <= gpr_in[16] @[el2_lib.scala 514:16] - gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 33:15] - node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 44:15] + node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_16 of rvclkhdr_697 @[el2_lib.scala 508:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset @@ -70906,8 +71050,8 @@ circuit el2_swerv : rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_655 <= gpr_in[17] @[el2_lib.scala 514:16] - gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 33:15] - node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 44:15] + node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_17 of rvclkhdr_698 @[el2_lib.scala 508:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset @@ -70916,8 +71060,8 @@ circuit el2_swerv : rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_657 <= gpr_in[18] @[el2_lib.scala 514:16] - gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 33:15] - node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 44:15] + node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_18 of rvclkhdr_699 @[el2_lib.scala 508:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset @@ -70926,8 +71070,8 @@ circuit el2_swerv : rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_659 <= gpr_in[19] @[el2_lib.scala 514:16] - gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 33:15] - node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 44:15] + node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_19 of rvclkhdr_700 @[el2_lib.scala 508:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset @@ -70936,8 +71080,8 @@ circuit el2_swerv : rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_661 <= gpr_in[20] @[el2_lib.scala 514:16] - gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 33:15] - node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 44:15] + node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_20 of rvclkhdr_701 @[el2_lib.scala 508:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset @@ -70946,8 +71090,8 @@ circuit el2_swerv : rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_663 <= gpr_in[21] @[el2_lib.scala 514:16] - gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 33:15] - node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 44:15] + node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_21 of rvclkhdr_702 @[el2_lib.scala 508:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset @@ -70956,8 +71100,8 @@ circuit el2_swerv : rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_665 <= gpr_in[22] @[el2_lib.scala 514:16] - gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 33:15] - node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 44:15] + node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_22 of rvclkhdr_703 @[el2_lib.scala 508:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset @@ -70966,8 +71110,8 @@ circuit el2_swerv : rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_667 <= gpr_in[23] @[el2_lib.scala 514:16] - gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 33:15] - node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 44:15] + node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_23 of rvclkhdr_704 @[el2_lib.scala 508:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset @@ -70976,8 +71120,8 @@ circuit el2_swerv : rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_669 <= gpr_in[24] @[el2_lib.scala 514:16] - gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 33:15] - node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 44:15] + node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_24 of rvclkhdr_705 @[el2_lib.scala 508:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset @@ -70986,8 +71130,8 @@ circuit el2_swerv : rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_671 <= gpr_in[25] @[el2_lib.scala 514:16] - gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 33:15] - node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 44:15] + node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_25 of rvclkhdr_706 @[el2_lib.scala 508:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset @@ -70996,8 +71140,8 @@ circuit el2_swerv : rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_673 <= gpr_in[26] @[el2_lib.scala 514:16] - gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 33:15] - node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 44:15] + node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_26 of rvclkhdr_707 @[el2_lib.scala 508:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset @@ -71006,8 +71150,8 @@ circuit el2_swerv : rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_675 <= gpr_in[27] @[el2_lib.scala 514:16] - gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 33:15] - node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 44:15] + node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_27 of rvclkhdr_708 @[el2_lib.scala 508:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset @@ -71016,8 +71160,8 @@ circuit el2_swerv : rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_677 <= gpr_in[28] @[el2_lib.scala 514:16] - gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 33:15] - node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 44:15] + node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_28 of rvclkhdr_709 @[el2_lib.scala 508:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset @@ -71026,8 +71170,8 @@ circuit el2_swerv : rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_679 <= gpr_in[29] @[el2_lib.scala 514:16] - gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 33:15] - node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 44:15] + node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_29 of rvclkhdr_710 @[el2_lib.scala 508:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset @@ -71036,8 +71180,8 @@ circuit el2_swerv : rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_681 <= gpr_in[30] @[el2_lib.scala 514:16] - gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 33:15] - node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 44:15] + node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_30 of rvclkhdr_711 @[el2_lib.scala 508:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset @@ -71046,69 +71190,69 @@ circuit el2_swerv : rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_683 <= gpr_in[31] @[el2_lib.scala 514:16] - gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 33:15] - node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 44:15] + node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] @@ -71172,69 +71316,69 @@ circuit el2_swerv : node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72] wire _T_807 : UInt<32> @[Mux.scala 27:72] _T_807 <= _T_806 @[Mux.scala 27:72] - io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 36:9] - node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 47:9] + node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] @@ -71298,7 +71442,7 @@ circuit el2_swerv : node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72] wire _T_931 : UInt<32> @[Mux.scala 27:72] _T_931 <= _T_930 @[Mux.scala 27:72] - io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 37:9] + io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 48:9] extmodule gated_latch_712 : output Q : Clock @@ -71398,15 +71542,21 @@ circuit el2_swerv : module el2_dec_timer_ctl : input clock : Clock - input reset : Reset + input reset : AsyncReset output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>} - wire mitctl1 : UInt<4> @[el2_dec_tlu_ctl.scala 2745:19] - wire mitctl0 : UInt<3> @[el2_dec_tlu_ctl.scala 2746:19] - wire mitb1 : UInt<32> @[el2_dec_tlu_ctl.scala 2747:19] - wire mitb0 : UInt<32> @[el2_dec_tlu_ctl.scala 2748:19] - wire mitcnt1 : UInt<32> @[el2_dec_tlu_ctl.scala 2749:19] - wire mitcnt0 : UInt<32> @[el2_dec_tlu_ctl.scala 2750:19] + wire mitctl1 : UInt<4> + mitctl1 <= UInt<1>("h00") + wire mitctl0 : UInt<3> + mitctl0 <= UInt<1>("h00") + wire mitb1 : UInt<32> + mitb1 <= UInt<1>("h00") + wire mitb0 : UInt<32> + mitb0 <= UInt<1>("h00") + wire mitcnt1 : UInt<32> + mitcnt1 <= UInt<1>("h00") + wire mitcnt0 : UInt<32> + mitcnt0 <= UInt<1>("h00") node mit0_match_ns = geq(mitcnt0, mitb0) @[el2_dec_tlu_ctl.scala 2752:30] node mit1_match_ns = geq(mitcnt1, mitb1) @[el2_dec_tlu_ctl.scala 2753:30] io.dec_timer_t0_pulse <= mit0_match_ns @[el2_dec_tlu_ctl.scala 2755:25] @@ -71430,9 +71580,9 @@ circuit el2_swerv : node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2767:68] node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[el2_dec_tlu_ctl.scala 2767:54] node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[el2_dec_tlu_ctl.scala 2767:23] - node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:60] - node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:77] - node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:94] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:59] + node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:76] + node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:93] inst rvclkhdr of rvclkhdr_712 @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -71494,7 +71644,7 @@ circuit el2_swerv : mitb0 <= _T_46 @[el2_dec_tlu_ctl.scala 2791:11] node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[el2_dec_tlu_ctl.scala 2798:63] node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[el2_dec_tlu_ctl.scala 2798:41] - node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:24] + node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:23] node _T_49 = bits(wr_mitb1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2799:56] inst rvclkhdr_3 of rvclkhdr_715 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock @@ -72508,15 +72658,21 @@ circuit el2_swerv : module csr_tlu : input clock : Clock - input reset : Reset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]} + input reset : AsyncReset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]} - wire miccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1454:41] - wire mice_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1455:41] - wire mdccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1456:41] - wire pc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 1457:41] - wire mpmc_b_ns : UInt<1> @[el2_dec_tlu_ctl.scala 1458:41] - wire mpmc_b : UInt<1> @[el2_dec_tlu_ctl.scala 1459:41] + wire miccme_ce_req : UInt<1> + miccme_ce_req <= UInt<1>("h00") + wire mice_ce_req : UInt<1> + mice_ce_req <= UInt<1>("h00") + wire mdccme_ce_req : UInt<1> + mdccme_ce_req <= UInt<1>("h00") + wire pc_r_d1 : UInt<31> + pc_r_d1 <= UInt<1>("h00") + wire mpmc_b_ns : UInt<1> + mpmc_b_ns <= UInt<1>("h00") + wire mpmc_b : UInt<1> + mpmc_b <= UInt<1>("h00") wire wr_mcycleh_r : UInt<1> wr_mcycleh_r <= UInt<1>("h00") wire mcycleh : UInt<32> @@ -73971,8 +74127,8 @@ circuit el2_swerv : mtdata1_tsel_out <= _T_941 @[Mux.scala 27:72] node _T_942 = bits(io.mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[0].select <= _T_942 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[0].match_ <= _T_943 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[0].match_pkt <= _T_943 @[el2_dec_tlu_ctl.scala 2309:39] node _T_944 = bits(io.mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[0].store <= _T_944 @[el2_dec_tlu_ctl.scala 2310:36] node _T_945 = bits(io.mtdata1_t[0], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -73983,8 +74139,8 @@ circuit el2_swerv : io.trigger_pkt_any[0].m <= _T_947 @[el2_dec_tlu_ctl.scala 2313:36] node _T_948 = bits(io.mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[1].select <= _T_948 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[1].match_ <= _T_949 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[1].match_pkt <= _T_949 @[el2_dec_tlu_ctl.scala 2309:39] node _T_950 = bits(io.mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[1].store <= _T_950 @[el2_dec_tlu_ctl.scala 2310:36] node _T_951 = bits(io.mtdata1_t[1], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -73995,8 +74151,8 @@ circuit el2_swerv : io.trigger_pkt_any[1].m <= _T_953 @[el2_dec_tlu_ctl.scala 2313:36] node _T_954 = bits(io.mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[2].select <= _T_954 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[2].match_ <= _T_955 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[2].match_pkt <= _T_955 @[el2_dec_tlu_ctl.scala 2309:39] node _T_956 = bits(io.mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[2].store <= _T_956 @[el2_dec_tlu_ctl.scala 2310:36] node _T_957 = bits(io.mtdata1_t[2], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -74007,8 +74163,8 @@ circuit el2_swerv : io.trigger_pkt_any[2].m <= _T_959 @[el2_dec_tlu_ctl.scala 2313:36] node _T_960 = bits(io.mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[3].select <= _T_960 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[3].match_ <= _T_961 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[3].match_pkt <= _T_961 @[el2_dec_tlu_ctl.scala 2309:39] node _T_962 = bits(io.mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[3].store <= _T_962 @[el2_dec_tlu_ctl.scala 2310:36] node _T_963 = bits(io.mtdata1_t[3], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -75889,7 +76045,7 @@ circuit el2_swerv : module el2_dec_decode_csr_read : input clock : Clock - input reset : Reset + input reset : AsyncReset output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] @@ -77571,124 +77727,238 @@ circuit el2_swerv : module el2_dec_tlu_ctl : input clock : Clock input reset : AsyncReset - output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>} + output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>} wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 236:59] - wire pause_expired_wb : UInt<1> @[el2_dec_tlu_ctl.scala 237:54] - wire take_nmi_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 238:62] - wire exc_or_int_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 239:54] - wire interrupt_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 240:54] - wire tlu_flush_lower_r : UInt<1> @[el2_dec_tlu_ctl.scala 241:54] - wire synchronous_flush_r : UInt<1> @[el2_dec_tlu_ctl.scala 242:62] - wire interrupt_valid_r : UInt<1> @[el2_dec_tlu_ctl.scala 243:54] - wire take_nmi : UInt<1> @[el2_dec_tlu_ctl.scala 244:62] - wire take_reset : UInt<1> @[el2_dec_tlu_ctl.scala 245:70] - wire take_int_timer1_int : UInt<1> @[el2_dec_tlu_ctl.scala 246:62] - wire take_int_timer0_int : UInt<1> @[el2_dec_tlu_ctl.scala 247:62] - wire take_timer_int : UInt<1> @[el2_dec_tlu_ctl.scala 248:62] - wire take_soft_int : UInt<1> @[el2_dec_tlu_ctl.scala 249:62] - wire take_ce_int : UInt<1> @[el2_dec_tlu_ctl.scala 250:70] - wire take_ext_int_start : UInt<1> @[el2_dec_tlu_ctl.scala 251:62] - wire ext_int_freeze : UInt<1> @[el2_dec_tlu_ctl.scala 252:62] - wire ext_int_freeze_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 253:62] - wire take_ext_int_start_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 254:54] - wire take_ext_int_start_d2 : UInt<1> @[el2_dec_tlu_ctl.scala 255:54] - wire take_ext_int_start_d3 : UInt<1> @[el2_dec_tlu_ctl.scala 256:54] - wire fast_int_meicpct : UInt<1> @[el2_dec_tlu_ctl.scala 257:54] - wire ignore_ext_int_due_to_lsu_stall : UInt<1> @[el2_dec_tlu_ctl.scala 258:44] - wire take_ext_int : UInt<1> @[el2_dec_tlu_ctl.scala 259:62] - wire internal_dbg_halt_timers : UInt<1> @[el2_dec_tlu_ctl.scala 260:46] - wire int_timer1_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 261:62] - wire int_timer0_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 262:62] - wire mhwakeup_ready : UInt<1> @[el2_dec_tlu_ctl.scala 263:62] - wire ext_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 264:54] - wire ce_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 265:54] - wire soft_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 266:54] - wire timer_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 267:54] - wire ebreak_to_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 268:54] - wire ebreak_to_debug_mode_r : UInt<1> @[el2_dec_tlu_ctl.scala 269:54] - wire inst_acc_r : UInt<1> @[el2_dec_tlu_ctl.scala 270:70] - wire inst_acc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 271:62] - wire iccm_sbecc_r : UInt<1> @[el2_dec_tlu_ctl.scala 272:62] - wire ic_perr_r : UInt<1> @[el2_dec_tlu_ctl.scala 273:62] - wire fence_i_r : UInt<1> @[el2_dec_tlu_ctl.scala 274:62] - wire ebreak_r : UInt<1> @[el2_dec_tlu_ctl.scala 275:62] - wire ecall_r : UInt<1> @[el2_dec_tlu_ctl.scala 276:62] - wire illegal_r : UInt<1> @[el2_dec_tlu_ctl.scala 277:62] - wire mret_r : UInt<1> @[el2_dec_tlu_ctl.scala 278:62] - wire iccm_repair_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 279:54] - wire rfpc_i0_r : UInt<1> @[el2_dec_tlu_ctl.scala 280:70] - wire tlu_i0_kill_writeb_r : UInt<1> @[el2_dec_tlu_ctl.scala 281:54] - wire lsu_exc_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 282:62] - wire lsu_i0_exc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 283:54] - wire mdseac_locked_f : UInt<1> @[el2_dec_tlu_ctl.scala 284:62] - wire i_cpu_run_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 285:54] - wire cpu_run_ack : UInt<1> @[el2_dec_tlu_ctl.scala 286:70] - wire cpu_halt_status : UInt<1> @[el2_dec_tlu_ctl.scala 287:62] - wire cpu_halt_ack : UInt<1> @[el2_dec_tlu_ctl.scala 288:62] - wire pmu_fw_tlu_halted : UInt<1> @[el2_dec_tlu_ctl.scala 289:54] - wire internal_pmu_fw_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 290:46] - wire pmu_fw_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 291:62] - wire pmu_fw_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 292:62] - wire pmu_fw_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 293:54] - wire int_timer0_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 294:54] - wire int_timer1_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 295:54] - wire trigger_hit_dmode_r : UInt<1> @[el2_dec_tlu_ctl.scala 296:54] - wire i0_trigger_hit_r : UInt<1> @[el2_dec_tlu_ctl.scala 297:54] - wire pause_expired_r : UInt<1> @[el2_dec_tlu_ctl.scala 298:62] - wire dec_tlu_pmu_fw_halted : UInt<1> @[el2_dec_tlu_ctl.scala 299:54] - wire dec_tlu_flush_noredir_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 300:54] - wire halt_taken_f : UInt<1> @[el2_dec_tlu_ctl.scala 301:62] - wire lsu_idle_any_f : UInt<1> @[el2_dec_tlu_ctl.scala 302:62] - wire ifu_miss_state_idle_f : UInt<1> @[el2_dec_tlu_ctl.scala 303:54] - wire dbg_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 304:54] - wire debug_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 305:54] - wire debug_resume_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 306:62] - wire trigger_hit_dmode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 307:54] - wire dcsr_single_step_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 308:54] - wire debug_halt_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 309:54] - wire request_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 310:54] - wire request_debug_mode_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 311:46] - wire dcsr_single_step_running_f : UInt<1> @[el2_dec_tlu_ctl.scala 312:54] - wire dec_tlu_flush_pause_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 313:46] - wire dbg_halt_req_held : UInt<1> @[el2_dec_tlu_ctl.scala 314:54] - wire debug_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 315:62] - wire internal_dbg_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 316:54] - wire core_empty : UInt<1> @[el2_dec_tlu_ctl.scala 317:70] - wire dbg_halt_req_final : UInt<1> @[el2_dec_tlu_ctl.scala 318:62] - wire debug_brkpt_status_ns : UInt<1> @[el2_dec_tlu_ctl.scala 319:54] - wire mpc_debug_halt_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 320:54] - wire mpc_debug_run_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 321:54] - wire mpc_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 322:62] - wire mpc_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 323:54] - wire dbg_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 324:62] - wire dbg_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 325:54] - wire dbg_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 326:54] - wire mpc_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 327:54] - wire nmi_int_detected : UInt<1> @[el2_dec_tlu_ctl.scala 328:54] - wire nmi_lsu_load_type : UInt<1> @[el2_dec_tlu_ctl.scala 329:62] - wire nmi_lsu_store_type : UInt<1> @[el2_dec_tlu_ctl.scala 330:62] - wire reset_delayed : UInt<1> @[el2_dec_tlu_ctl.scala 331:62] - wire debug_mode_status : UInt<1> @[el2_dec_tlu_ctl.scala 332:46] - wire e5_valid : UInt<1> @[el2_dec_tlu_ctl.scala 333:62] - wire ic_perr_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 334:62] - wire iccm_sbecc_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 335:62] - wire npc_r : UInt<31> @[el2_dec_tlu_ctl.scala 337:41] - wire npc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 338:41] - wire mie_ns : UInt<6> @[el2_dec_tlu_ctl.scala 339:41] - wire mepc : UInt<31> @[el2_dec_tlu_ctl.scala 340:41] - wire mdseac_locked_ns : UInt<1> @[el2_dec_tlu_ctl.scala 341:41] - wire force_halt : UInt<1> @[el2_dec_tlu_ctl.scala 342:57] - wire dpc : UInt<31> @[el2_dec_tlu_ctl.scala 343:41] - wire mstatus_mie_ns : UInt<1> @[el2_dec_tlu_ctl.scala 344:41] - wire dec_csr_wen_r_mod : UInt<1> @[el2_dec_tlu_ctl.scala 345:41] - wire fw_halt_req : UInt<1> @[el2_dec_tlu_ctl.scala 346:41] - wire mstatus : UInt<2> @[el2_dec_tlu_ctl.scala 347:41] - wire dcsr : UInt<16> @[el2_dec_tlu_ctl.scala 348:41] - wire mtvec : UInt<31> @[el2_dec_tlu_ctl.scala 349:41] - wire mip : UInt<6> @[el2_dec_tlu_ctl.scala 350:41] + wire pause_expired_wb : UInt<1> + pause_expired_wb <= UInt<1>("h00") + wire take_nmi_r_d1 : UInt<1> + take_nmi_r_d1 <= UInt<1>("h00") + wire exc_or_int_valid_r_d1 : UInt<1> + exc_or_int_valid_r_d1 <= UInt<1>("h00") + wire interrupt_valid_r_d1 : UInt<1> + interrupt_valid_r_d1 <= UInt<1>("h00") + wire tlu_flush_lower_r : UInt<1> + tlu_flush_lower_r <= UInt<1>("h00") + wire synchronous_flush_r : UInt<1> + synchronous_flush_r <= UInt<1>("h00") + wire interrupt_valid_r : UInt<1> + interrupt_valid_r <= UInt<1>("h00") + wire take_nmi : UInt<1> + take_nmi <= UInt<1>("h00") + wire take_reset : UInt<1> + take_reset <= UInt<1>("h00") + wire take_int_timer1_int : UInt<1> + take_int_timer1_int <= UInt<1>("h00") + wire take_int_timer0_int : UInt<1> + take_int_timer0_int <= UInt<1>("h00") + wire take_timer_int : UInt<1> + take_timer_int <= UInt<1>("h00") + wire take_soft_int : UInt<1> + take_soft_int <= UInt<1>("h00") + wire take_ce_int : UInt<1> + take_ce_int <= UInt<1>("h00") + wire take_ext_int_start : UInt<1> + take_ext_int_start <= UInt<1>("h00") + wire ext_int_freeze : UInt<1> + ext_int_freeze <= UInt<1>("h00") + wire ext_int_freeze_d1 : UInt<1> + ext_int_freeze_d1 <= UInt<1>("h00") + wire take_ext_int_start_d1 : UInt<1> + take_ext_int_start_d1 <= UInt<1>("h00") + wire take_ext_int_start_d2 : UInt<1> + take_ext_int_start_d2 <= UInt<1>("h00") + wire take_ext_int_start_d3 : UInt<1> + take_ext_int_start_d3 <= UInt<1>("h00") + wire fast_int_meicpct : UInt<1> + fast_int_meicpct <= UInt<1>("h00") + wire ignore_ext_int_due_to_lsu_stall : UInt<1> + ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00") + wire take_ext_int : UInt<1> + take_ext_int <= UInt<1>("h00") + wire internal_dbg_halt_timers : UInt<1> + internal_dbg_halt_timers <= UInt<1>("h00") + wire int_timer1_int_hold : UInt<1> + int_timer1_int_hold <= UInt<1>("h00") + wire int_timer0_int_hold : UInt<1> + int_timer0_int_hold <= UInt<1>("h00") + wire mhwakeup_ready : UInt<1> + mhwakeup_ready <= UInt<1>("h00") + wire ext_int_ready : UInt<1> + ext_int_ready <= UInt<1>("h00") + wire ce_int_ready : UInt<1> + ce_int_ready <= UInt<1>("h00") + wire soft_int_ready : UInt<1> + soft_int_ready <= UInt<1>("h00") + wire timer_int_ready : UInt<1> + timer_int_ready <= UInt<1>("h00") + wire ebreak_to_debug_mode_r_d1 : UInt<1> + ebreak_to_debug_mode_r_d1 <= UInt<1>("h00") + wire ebreak_to_debug_mode_r : UInt<1> + ebreak_to_debug_mode_r <= UInt<1>("h00") + wire inst_acc_r : UInt<1> + inst_acc_r <= UInt<1>("h00") + wire inst_acc_r_raw : UInt<1> + inst_acc_r_raw <= UInt<1>("h00") + wire iccm_sbecc_r : UInt<1> + iccm_sbecc_r <= UInt<1>("h00") + wire ic_perr_r : UInt<1> + ic_perr_r <= UInt<1>("h00") + wire fence_i_r : UInt<1> + fence_i_r <= UInt<1>("h00") + wire ebreak_r : UInt<1> + ebreak_r <= UInt<1>("h00") + wire ecall_r : UInt<1> + ecall_r <= UInt<1>("h00") + wire illegal_r : UInt<1> + illegal_r <= UInt<1>("h00") + wire mret_r : UInt<1> + mret_r <= UInt<1>("h00") + wire iccm_repair_state_ns : UInt<1> + iccm_repair_state_ns <= UInt<1>("h00") + wire rfpc_i0_r : UInt<1> + rfpc_i0_r <= UInt<1>("h00") + wire tlu_i0_kill_writeb_r : UInt<1> + tlu_i0_kill_writeb_r <= UInt<1>("h00") + wire lsu_exc_valid_r_d1 : UInt<1> + lsu_exc_valid_r_d1 <= UInt<1>("h00") + wire lsu_i0_exc_r_raw : UInt<1> + lsu_i0_exc_r_raw <= UInt<1>("h00") + wire mdseac_locked_f : UInt<1> + mdseac_locked_f <= UInt<1>("h00") + wire i_cpu_run_req_d1 : UInt<1> + i_cpu_run_req_d1 <= UInt<1>("h00") + wire cpu_run_ack : UInt<1> + cpu_run_ack <= UInt<1>("h00") + wire cpu_halt_status : UInt<1> + cpu_halt_status <= UInt<1>("h00") + wire cpu_halt_ack : UInt<1> + cpu_halt_ack <= UInt<1>("h00") + wire pmu_fw_tlu_halted : UInt<1> + pmu_fw_tlu_halted <= UInt<1>("h00") + wire internal_pmu_fw_halt_mode : UInt<1> + internal_pmu_fw_halt_mode <= UInt<1>("h00") + wire pmu_fw_halt_req_ns : UInt<1> + pmu_fw_halt_req_ns <= UInt<1>("h00") + wire pmu_fw_halt_req_f : UInt<1> + pmu_fw_halt_req_f <= UInt<1>("h00") + wire pmu_fw_tlu_halted_f : UInt<1> + pmu_fw_tlu_halted_f <= UInt<1>("h00") + wire int_timer0_int_hold_f : UInt<1> + int_timer0_int_hold_f <= UInt<1>("h00") + wire int_timer1_int_hold_f : UInt<1> + int_timer1_int_hold_f <= UInt<1>("h00") + wire trigger_hit_dmode_r : UInt<1> + trigger_hit_dmode_r <= UInt<1>("h00") + wire i0_trigger_hit_r : UInt<1> + i0_trigger_hit_r <= UInt<1>("h00") + wire pause_expired_r : UInt<1> + pause_expired_r <= UInt<1>("h00") + wire dec_tlu_pmu_fw_halted : UInt<1> + dec_tlu_pmu_fw_halted <= UInt<1>("h00") + wire dec_tlu_flush_noredir_r_d1 : UInt<1> + dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00") + wire halt_taken_f : UInt<1> + halt_taken_f <= UInt<1>("h00") + wire lsu_idle_any_f : UInt<1> + lsu_idle_any_f <= UInt<1>("h00") + wire ifu_miss_state_idle_f : UInt<1> + ifu_miss_state_idle_f <= UInt<1>("h00") + wire dbg_tlu_halted_f : UInt<1> + dbg_tlu_halted_f <= UInt<1>("h00") + wire debug_halt_req_f : UInt<1> + debug_halt_req_f <= UInt<1>("h00") + wire debug_resume_req_f : UInt<1> + debug_resume_req_f <= UInt<1>("h00") + wire trigger_hit_dmode_r_d1 : UInt<1> + trigger_hit_dmode_r_d1 <= UInt<1>("h00") + wire dcsr_single_step_done_f : UInt<1> + dcsr_single_step_done_f <= UInt<1>("h00") + wire debug_halt_req_d1 : UInt<1> + debug_halt_req_d1 <= UInt<1>("h00") + wire request_debug_mode_r_d1 : UInt<1> + request_debug_mode_r_d1 <= UInt<1>("h00") + wire request_debug_mode_done_f : UInt<1> + request_debug_mode_done_f <= UInt<1>("h00") + wire dcsr_single_step_running_f : UInt<1> + dcsr_single_step_running_f <= UInt<1>("h00") + wire dec_tlu_flush_pause_r_d1 : UInt<1> + dec_tlu_flush_pause_r_d1 <= UInt<1>("h00") + wire dbg_halt_req_held : UInt<1> + dbg_halt_req_held <= UInt<1>("h00") + wire debug_halt_req_ns : UInt<1> + debug_halt_req_ns <= UInt<1>("h00") + wire internal_dbg_halt_mode : UInt<1> + internal_dbg_halt_mode <= UInt<1>("h00") + wire core_empty : UInt<1> + core_empty <= UInt<1>("h00") + wire dbg_halt_req_final : UInt<1> + dbg_halt_req_final <= UInt<1>("h00") + wire debug_brkpt_status_ns : UInt<1> + debug_brkpt_status_ns <= UInt<1>("h00") + wire mpc_debug_halt_ack_ns : UInt<1> + mpc_debug_halt_ack_ns <= UInt<1>("h00") + wire mpc_debug_run_ack_ns : UInt<1> + mpc_debug_run_ack_ns <= UInt<1>("h00") + wire mpc_halt_state_ns : UInt<1> + mpc_halt_state_ns <= UInt<1>("h00") + wire mpc_run_state_ns : UInt<1> + mpc_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_ns : UInt<1> + dbg_halt_state_ns <= UInt<1>("h00") + wire dbg_run_state_ns : UInt<1> + dbg_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_f : UInt<1> + dbg_halt_state_f <= UInt<1>("h00") + wire mpc_halt_state_f : UInt<1> + mpc_halt_state_f <= UInt<1>("h00") + wire nmi_int_detected : UInt<1> + nmi_int_detected <= UInt<1>("h00") + wire nmi_lsu_load_type : UInt<1> + nmi_lsu_load_type <= UInt<1>("h00") + wire nmi_lsu_store_type : UInt<1> + nmi_lsu_store_type <= UInt<1>("h00") + wire reset_delayed : UInt<1> + reset_delayed <= UInt<1>("h00") + wire debug_mode_status : UInt<1> + debug_mode_status <= UInt<1>("h00") + wire e5_valid : UInt<1> + e5_valid <= UInt<1>("h00") + wire ic_perr_r_d1 : UInt<1> + ic_perr_r_d1 <= UInt<1>("h00") + wire iccm_sbecc_r_d1 : UInt<1> + iccm_sbecc_r_d1 <= UInt<1>("h00") + wire npc_r : UInt<31> + npc_r <= UInt<1>("h00") + wire npc_r_d1 : UInt<31> + npc_r_d1 <= UInt<1>("h00") + wire mie_ns : UInt<6> + mie_ns <= UInt<1>("h00") + wire mepc : UInt<31> + mepc <= UInt<1>("h00") + wire mdseac_locked_ns : UInt<1> + mdseac_locked_ns <= UInt<1>("h00") + wire force_halt : UInt<1> + force_halt <= UInt<1>("h00") + wire dpc : UInt<31> + dpc <= UInt<1>("h00") + wire mstatus_mie_ns : UInt<1> + mstatus_mie_ns <= UInt<1>("h00") + wire dec_csr_wen_r_mod : UInt<1> + dec_csr_wen_r_mod <= UInt<1>("h00") + wire fw_halt_req : UInt<1> + fw_halt_req <= UInt<1>("h00") + wire mstatus : UInt<2> + mstatus <= UInt<1>("h00") + wire dcsr : UInt<16> + dcsr <= UInt<1>("h00") + wire mtvec : UInt<31> + mtvec <= UInt<1>("h00") + wire mip : UInt<6> + mip <= UInt<1>("h00") wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[el2_dec_tlu_ctl.scala 351:41] - wire dec_tlu_mpc_halted_only_ns : UInt<1> @[el2_dec_tlu_ctl.scala 352:41] + wire dec_tlu_mpc_halted_only_ns : UInt<1> + dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") node _T = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 354:33] node _T_1 = and(_T, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 354:51] dec_tlu_mpc_halted_only_ns <= _T_1 @[el2_dec_tlu_ctl.scala 354:30] @@ -78420,12 +78690,12 @@ circuit el2_swerv : node _T_461 = not(io.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 727:118] node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 727:116] node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 727:94] - io.dec_tlu_br0_r_pkt.bits.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:57] - io.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49] - io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:49] + io.dec_tlu_br0_r_pkt.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:49] + io.dec_tlu_br0_r_pkt.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49] + io.dec_tlu_br0_r_pkt.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:41] io.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 733:49] - io.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:57] - io.dec_tlu_br0_r_pkt.bits.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:57] + io.dec_tlu_br0_r_pkt.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:49] + io.dec_tlu_br0_r_pkt.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:49] node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 738:51] node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64] node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90] @@ -78998,28 +79268,28 @@ circuit el2_swerv : io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[0].match_ <= csr.io.trigger_pkt_any[0].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[1].match_ <= csr.io.trigger_pkt_any[1].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[2].match_ <= csr.io.trigger_pkt_any[2].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[3].match_ <= csr.io.trigger_pkt_any[3].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[el2_dec_tlu_ctl.scala 962:40] io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[el2_dec_tlu_ctl.scala 963:40] io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[el2_dec_tlu_ctl.scala 964:40] @@ -79335,7 +79605,7 @@ circuit el2_swerv : module el2_dec_trigger : input clock : Clock input reset : Reset - output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[el2_dec_trigger.scala 14:93] @@ -79619,7 +79889,7 @@ circuit el2_swerv : dec_i0_match_data[2] <= _T_110 @[el2_dec_trigger.scala 14:46] dec_i0_match_data[3] <= _T_147 @[el2_dec_trigger.scala 14:46] node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[el2_dec_trigger.scala 15:83] - node _T_149 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_149 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_150 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] node _T_152 = not(_T_151) @[el2_lib.scala 241:39] @@ -79910,7 +80180,7 @@ circuit el2_swerv : node _T_405 = cat(_T_404, _T_389) @[el2_lib.scala 245:14] node _T_406 = and(_T_148, _T_405) @[el2_dec_trigger.scala 15:109] node _T_407 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[el2_dec_trigger.scala 15:83] - node _T_408 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_408 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_409 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_410 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] node _T_411 = not(_T_410) @[el2_lib.scala 241:39] @@ -80201,7 +80471,7 @@ circuit el2_swerv : node _T_664 = cat(_T_663, _T_648) @[el2_lib.scala 245:14] node _T_665 = and(_T_407, _T_664) @[el2_dec_trigger.scala 15:109] node _T_666 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[el2_dec_trigger.scala 15:83] - node _T_667 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_667 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_668 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_669 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] node _T_670 = not(_T_669) @[el2_lib.scala 241:39] @@ -80492,7 +80762,7 @@ circuit el2_swerv : node _T_923 = cat(_T_922, _T_907) @[el2_lib.scala 245:14] node _T_924 = and(_T_666, _T_923) @[el2_dec_trigger.scala 15:109] node _T_925 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[el2_dec_trigger.scala 15:83] - node _T_926 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_926 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_927 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_928 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] node _T_929 = not(_T_928) @[el2_lib.scala 241:39] @@ -80790,9 +81060,8 @@ circuit el2_swerv : module el2_dec : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<32>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<32>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<32>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<32>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<9>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<32>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<32>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<32>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<70>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<32>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<13>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<32>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<32>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<32>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<9>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} - io.dec_i0_pc_d <= UInt<1>("h00") @[el2_dec.scala 273:18] wire dec_i0_inst_wb1 : UInt<32> dec_i0_inst_wb1 <= UInt<1>("h00") wire dec_i0_pc_wb1 : UInt<32> @@ -80807,509 +81076,445 @@ circuit el2_swerv : dec_tlu_mtval_wb1 <= UInt<1>("h00") wire dec_tlu_i0_exc_valid_wb1 : UInt<1> dec_tlu_i0_exc_valid_wb1 <= UInt<1>("h00") - inst instbuff of el2_dec_ib_ctl @[el2_dec.scala 353:24] + inst instbuff of el2_dec_ib_ctl @[el2_dec.scala 285:24] instbuff.clock <= clock instbuff.reset <= reset - inst decode of el2_dec_decode_ctl @[el2_dec.scala 354:22] + inst decode of el2_dec_decode_ctl @[el2_dec.scala 286:22] decode.clock <= clock decode.reset <= reset - inst gpr of el2_dec_gpr_ctl @[el2_dec.scala 355:19] + inst gpr of el2_dec_gpr_ctl @[el2_dec.scala 287:19] gpr.clock <= clock gpr.reset <= reset - inst tlu of el2_dec_tlu_ctl @[el2_dec.scala 356:19] + inst tlu of el2_dec_tlu_ctl @[el2_dec.scala 288:19] tlu.clock <= clock tlu.reset <= reset - inst dec_trigger of el2_dec_trigger @[el2_dec.scala 357:27] + inst dec_trigger of el2_dec_trigger @[el2_dec.scala 289:27] dec_trigger.clock <= clock dec_trigger.reset <= reset - instbuff.io.dbg_cmd_valid <= io.dbg_cmd_valid @[el2_dec.scala 364:45] - instbuff.io.dbg_cmd_write <= io.dbg_cmd_write @[el2_dec.scala 365:45] - instbuff.io.dbg_cmd_type <= io.dbg_cmd_type @[el2_dec.scala 366:45] - instbuff.io.dbg_cmd_addr <= io.dbg_cmd_addr @[el2_dec.scala 367:45] - instbuff.io.i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec.scala 368:55] - instbuff.io.i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec.scala 368:55] - instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 368:55] - instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 369:35] - instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 370:35] - instbuff.io.ifu_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec.scala 371:35] - instbuff.io.ifu_i0_pc4 <= io.ifu_i0_pc4 @[el2_dec.scala 372:35] - instbuff.io.ifu_i0_valid <= io.ifu_i0_valid @[el2_dec.scala 373:35] - instbuff.io.ifu_i0_icaf <= io.ifu_i0_icaf @[el2_dec.scala 374:35] - instbuff.io.ifu_i0_icaf_type <= io.ifu_i0_icaf_type @[el2_dec.scala 375:35] - instbuff.io.ifu_i0_icaf_f1 <= io.ifu_i0_icaf_f1 @[el2_dec.scala 376:35] - instbuff.io.ifu_i0_dbecc <= io.ifu_i0_dbecc @[el2_dec.scala 377:35] - instbuff.io.ifu_i0_instr <= io.ifu_i0_instr @[el2_dec.scala 378:35] - instbuff.io.ifu_i0_pc <= io.ifu_i0_pc @[el2_dec.scala 379:35] - decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[el2_dec.scala 381:38] - decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 382:38] - decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[el2_dec.scala 383:38] - decode.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 384:38] - decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[el2_dec.scala 385:38] - decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 386:38] - decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 386:38] - decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 387:38] - decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 388:38] - decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[el2_dec.scala 389:38] - decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[el2_dec.scala 390:38] - decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 391:38] - decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 392:38] - io.dec_debug_wdata_rs1_d <= instbuff.io.dec_debug_wdata_rs1_d @[el2_dec.scala 393:38] - decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[el2_dec.scala 394:38] - dec_trigger.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 400:30] - dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 401:34] - dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 401:34] - decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 410:48] - decode.io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 411:48] - decode.io.ifu_i0_cinst <= io.ifu_i0_cinst @[el2_dec.scala 412:48] - decode.io.lsu_nonblock_load_valid_m <= io.lsu_nonblock_load_valid_m @[el2_dec.scala 413:48] - decode.io.lsu_nonblock_load_tag_m <= io.lsu_nonblock_load_tag_m @[el2_dec.scala 414:48] - decode.io.lsu_nonblock_load_inv_r <= io.lsu_nonblock_load_inv_r @[el2_dec.scala 415:48] - decode.io.lsu_nonblock_load_inv_tag_r <= io.lsu_nonblock_load_inv_tag_r @[el2_dec.scala 416:48] - decode.io.lsu_nonblock_load_data_valid <= io.lsu_nonblock_load_data_valid @[el2_dec.scala 417:48] - decode.io.lsu_nonblock_load_data_error <= io.lsu_nonblock_load_data_error @[el2_dec.scala 418:48] - decode.io.lsu_nonblock_load_data_tag <= io.lsu_nonblock_load_data_tag @[el2_dec.scala 419:48] - decode.io.lsu_nonblock_load_data <= io.lsu_nonblock_load_data @[el2_dec.scala 420:48] - decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[el2_dec.scala 421:48] - decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[el2_dec.scala 422:48] - decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[el2_dec.scala 423:48] - decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[el2_dec.scala 424:48] - decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 425:48] - decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[el2_dec.scala 426:48] - decode.io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 427:48] - decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[el2_dec.scala 428:48] - decode.io.dbg_cmd_wrdata <= io.dbg_cmd_wrdata @[el2_dec.scala 429:48] - decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[el2_dec.scala 430:48] - decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 431:48] - decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 432:48] - decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 433:48] - decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 434:48] - decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 434:48] - decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 435:48] - decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 436:48] - decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[el2_dec.scala 437:48] - decode.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 438:48] - decode.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 439:48] - decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[el2_dec.scala 440:48] - decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 441:48] - decode.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 442:48] - decode.io.exu_div_wren <= io.exu_div_wren @[el2_dec.scala 443:48] - decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[el2_dec.scala 444:48] - decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[el2_dec.scala 445:48] - decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 446:48] - decode.io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 447:48] - decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[el2_dec.scala 448:48] - decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[el2_dec.scala 449:48] - decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[el2_dec.scala 450:48] - decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 451:48] - decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[el2_dec.scala 452:48] - decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[el2_dec.scala 453:48] - decode.io.exu_csr_rs1_x <= io.exu_csr_rs1_x @[el2_dec.scala 454:48] - decode.io.lsu_result_m <= io.lsu_result_m @[el2_dec.scala 455:48] - decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[el2_dec.scala 456:48] - decode.io.exu_flush_final <= io.exu_flush_final @[el2_dec.scala 457:48] - decode.io.exu_i0_pc_x <= io.exu_i0_pc_x @[el2_dec.scala 458:48] - decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[el2_dec.scala 459:48] - decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[el2_dec.scala 460:48] - decode.io.exu_i0_result_x <= io.exu_i0_result_x @[el2_dec.scala 461:48] - decode.io.free_clk <= io.free_clk @[el2_dec.scala 463:48] - decode.io.active_clk <= io.active_clk @[el2_dec.scala 464:48] - decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[el2_dec.scala 465:48] - decode.io.scan_mode <= io.scan_mode @[el2_dec.scala 467:48] - io.dec_extint_stall <= decode.io.dec_extint_stall @[el2_dec.scala 469:40] - dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb1 @[el2_dec.scala 470:40] - dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb1 @[el2_dec.scala 471:40] - io.dec_i0_rs1_en_d <= decode.io.dec_i0_rs1_en_d @[el2_dec.scala 472:40] - io.dec_i0_rs2_en_d <= decode.io.dec_i0_rs2_en_d @[el2_dec.scala 473:40] - gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[el2_dec.scala 474:40] - gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[el2_dec.scala 475:40] - io.dec_i0_immed_d <= decode.io.dec_i0_immed_d @[el2_dec.scala 476:40] - io.dec_i0_br_immed_d <= decode.io.dec_i0_br_immed_d @[el2_dec.scala 477:40] - io.i0_ap.csr_imm <= decode.io.i0_ap.csr_imm @[el2_dec.scala 478:40] - io.i0_ap.csr_write <= decode.io.i0_ap.csr_write @[el2_dec.scala 478:40] - io.i0_ap.predict_nt <= decode.io.i0_ap.predict_nt @[el2_dec.scala 478:40] - io.i0_ap.predict_t <= decode.io.i0_ap.predict_t @[el2_dec.scala 478:40] - io.i0_ap.jal <= decode.io.i0_ap.jal @[el2_dec.scala 478:40] - io.i0_ap.unsign <= decode.io.i0_ap.unsign @[el2_dec.scala 478:40] - io.i0_ap.slt <= decode.io.i0_ap.slt @[el2_dec.scala 478:40] - io.i0_ap.sub <= decode.io.i0_ap.sub @[el2_dec.scala 478:40] - io.i0_ap.add <= decode.io.i0_ap.add @[el2_dec.scala 478:40] - io.i0_ap.bge <= decode.io.i0_ap.bge @[el2_dec.scala 478:40] - io.i0_ap.blt <= decode.io.i0_ap.blt @[el2_dec.scala 478:40] - io.i0_ap.bne <= decode.io.i0_ap.bne @[el2_dec.scala 478:40] - io.i0_ap.beq <= decode.io.i0_ap.beq @[el2_dec.scala 478:40] - io.i0_ap.sra <= decode.io.i0_ap.sra @[el2_dec.scala 478:40] - io.i0_ap.srl <= decode.io.i0_ap.srl @[el2_dec.scala 478:40] - io.i0_ap.sll <= decode.io.i0_ap.sll @[el2_dec.scala 478:40] - io.i0_ap.lxor <= decode.io.i0_ap.lxor @[el2_dec.scala 478:40] - io.i0_ap.lor <= decode.io.i0_ap.lor @[el2_dec.scala 478:40] - io.i0_ap.land <= decode.io.i0_ap.land @[el2_dec.scala 478:40] - io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 479:40] - io.dec_i0_alu_decode_d <= decode.io.dec_i0_alu_decode_d @[el2_dec.scala 480:40] - io.dec_i0_rs1_bypass_data_d <= decode.io.dec_i0_rs1_bypass_data_d @[el2_dec.scala 481:40] - io.dec_i0_rs2_bypass_data_d <= decode.io.dec_i0_rs2_bypass_data_d @[el2_dec.scala 482:40] - gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[el2_dec.scala 483:40] - gpr.io.wen0 <= decode.io.dec_i0_wen_r @[el2_dec.scala 484:40] - gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[el2_dec.scala 485:40] - io.dec_i0_select_pc_d <= decode.io.dec_i0_select_pc_d @[el2_dec.scala 486:40] - io.dec_i0_rs1_bypass_en_d <= decode.io.dec_i0_rs1_bypass_en_d @[el2_dec.scala 487:40] - io.dec_i0_rs2_bypass_en_d <= decode.io.dec_i0_rs2_bypass_en_d @[el2_dec.scala 488:40] - io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[el2_dec.scala 489:40] - io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[el2_dec.scala 489:40] - io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[el2_dec.scala 489:40] - io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[el2_dec.scala 489:40] - io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[el2_dec.scala 489:40] - io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[el2_dec.scala 489:40] - io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[el2_dec.scala 489:40] - io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[el2_dec.scala 489:40] - io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[el2_dec.scala 489:40] - io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[el2_dec.scala 489:40] - io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[el2_dec.scala 489:40] - io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[el2_dec.scala 489:40] - io.lsu_p.valid <= decode.io.lsu_p.valid @[el2_dec.scala 489:40] - io.mul_p.bits.bfp <= decode.io.mul_p.bits.bfp @[el2_dec.scala 490:40] - io.mul_p.bits.crc32c_w <= decode.io.mul_p.bits.crc32c_w @[el2_dec.scala 490:40] - io.mul_p.bits.crc32c_h <= decode.io.mul_p.bits.crc32c_h @[el2_dec.scala 490:40] - io.mul_p.bits.crc32c_b <= decode.io.mul_p.bits.crc32c_b @[el2_dec.scala 490:40] - io.mul_p.bits.crc32_w <= decode.io.mul_p.bits.crc32_w @[el2_dec.scala 490:40] - io.mul_p.bits.crc32_h <= decode.io.mul_p.bits.crc32_h @[el2_dec.scala 490:40] - io.mul_p.bits.crc32_b <= decode.io.mul_p.bits.crc32_b @[el2_dec.scala 490:40] - io.mul_p.bits.unshfl <= decode.io.mul_p.bits.unshfl @[el2_dec.scala 490:40] - io.mul_p.bits.shfl <= decode.io.mul_p.bits.shfl @[el2_dec.scala 490:40] - io.mul_p.bits.grev <= decode.io.mul_p.bits.grev @[el2_dec.scala 490:40] - io.mul_p.bits.clmulr <= decode.io.mul_p.bits.clmulr @[el2_dec.scala 490:40] - io.mul_p.bits.clmulh <= decode.io.mul_p.bits.clmulh @[el2_dec.scala 490:40] - io.mul_p.bits.clmul <= decode.io.mul_p.bits.clmul @[el2_dec.scala 490:40] - io.mul_p.bits.bdep <= decode.io.mul_p.bits.bdep @[el2_dec.scala 490:40] - io.mul_p.bits.bext <= decode.io.mul_p.bits.bext @[el2_dec.scala 490:40] - io.mul_p.bits.low <= decode.io.mul_p.bits.low @[el2_dec.scala 490:40] - io.mul_p.bits.rs2_sign <= decode.io.mul_p.bits.rs2_sign @[el2_dec.scala 490:40] - io.mul_p.bits.rs1_sign <= decode.io.mul_p.bits.rs1_sign @[el2_dec.scala 490:40] - io.mul_p.valid <= decode.io.mul_p.valid @[el2_dec.scala 490:40] - io.div_p.bits.rem <= decode.io.div_p.bits.rem @[el2_dec.scala 491:40] - io.div_p.bits.unsign <= decode.io.div_p.bits.unsign @[el2_dec.scala 491:40] - io.div_p.valid <= decode.io.div_p.valid @[el2_dec.scala 491:40] - gpr.io.waddr2 <= decode.io.div_waddr_wb @[el2_dec.scala 492:40] - io.dec_div_cancel <= decode.io.dec_div_cancel @[el2_dec.scala 493:40] - io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[el2_dec.scala 494:40] - io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[el2_dec.scala 495:40] - io.dec_csr_ren_d <= decode.io.dec_csr_ren_d @[el2_dec.scala 496:40] - tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[el2_dec.scala 497:40] - tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[el2_dec.scala 498:40] - tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[el2_dec.scala 499:40] - tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[el2_dec.scala 500:40] - tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[el2_dec.scala 501:40] - tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[el2_dec.scala 502:40] - tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[el2_dec.scala 503:40] - tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[el2_dec.scala 504:40] - tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[el2_dec.scala 505:40] - tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[el2_dec.scala 505:40] - tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[el2_dec.scala 506:40] - tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[el2_dec.scala 507:40] - io.pred_correct_npc_x <= decode.io.pred_correct_npc_x @[el2_dec.scala 508:40] - io.dec_i0_predict_p_d.bits.way <= decode.io.dec_i0_predict_p_d.bits.way @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.pja <= decode.io.dec_i0_predict_p_d.bits.pja @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.pret <= decode.io.dec_i0_predict_p_d.bits.pret @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.pcall <= decode.io.dec_i0_predict_p_d.bits.pcall @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.prett <= decode.io.dec_i0_predict_p_d.bits.prett @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.br_start_error <= decode.io.dec_i0_predict_p_d.bits.br_start_error @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.br_error <= decode.io.dec_i0_predict_p_d.bits.br_error @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.toffset <= decode.io.dec_i0_predict_p_d.bits.toffset @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.hist <= decode.io.dec_i0_predict_p_d.bits.hist @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.pc4 <= decode.io.dec_i0_predict_p_d.bits.pc4 @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.boffset <= decode.io.dec_i0_predict_p_d.bits.boffset @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.ataken <= decode.io.dec_i0_predict_p_d.bits.ataken @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.bits.misp <= decode.io.dec_i0_predict_p_d.bits.misp @[el2_dec.scala 509:40] - io.dec_i0_predict_p_d.valid <= decode.io.dec_i0_predict_p_d.valid @[el2_dec.scala 509:40] - io.i0_predict_fghr_d <= decode.io.i0_predict_fghr_d @[el2_dec.scala 510:40] - io.i0_predict_index_d <= decode.io.i0_predict_index_d @[el2_dec.scala 511:40] - io.i0_predict_btag_d <= decode.io.i0_predict_btag_d @[el2_dec.scala 512:40] - io.dec_data_en <= decode.io.dec_data_en @[el2_dec.scala 513:40] - io.dec_ctl_en <= decode.io.dec_ctl_en @[el2_dec.scala 514:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_instr_decoded @[el2_dec.scala 515:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_decode_stall @[el2_dec.scala 516:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_presync_stall @[el2_dec.scala 517:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[el2_dec.scala 518:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_nonblock_load_wen @[el2_dec.scala 519:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_nonblock_load_waddr @[el2_dec.scala 520:40] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pause_state @[el2_dec.scala 521:40] - io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[el2_dec.scala 522:40] - tlu.io.dec_div_active <= decode.io.dec_div_active @[el2_dec.scala 523:40] - gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[el2_dec.scala 530:23] - gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[el2_dec.scala 531:23] - gpr.io.wen0 <= decode.io.dec_i0_wen_r @[el2_dec.scala 532:23] - gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[el2_dec.scala 533:23] - gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[el2_dec.scala 534:23] - gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[el2_dec.scala 535:23] - gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[el2_dec.scala 536:23] - gpr.io.wd1 <= io.lsu_nonblock_load_data @[el2_dec.scala 537:23] - gpr.io.wen2 <= io.exu_div_wren @[el2_dec.scala 538:23] - gpr.io.waddr2 <= decode.io.div_waddr_wb @[el2_dec.scala 539:23] - gpr.io.wd2 <= io.exu_div_result @[el2_dec.scala 540:23] - gpr.io.scan_mode <= io.scan_mode @[el2_dec.scala 543:23] - io.gpr_i0_rs1_d <= gpr.io.rd0 @[el2_dec.scala 545:19] - io.gpr_i0_rs2_d <= gpr.io.rd1 @[el2_dec.scala 546:19] - tlu.io.active_clk <= io.active_clk @[el2_dec.scala 555:45] - tlu.io.free_clk <= io.free_clk @[el2_dec.scala 556:45] - tlu.io.scan_mode <= io.scan_mode @[el2_dec.scala 558:45] - tlu.io.rst_vec <= io.rst_vec @[el2_dec.scala 559:45] - tlu.io.nmi_int <= io.nmi_int @[el2_dec.scala 560:45] - tlu.io.nmi_vec <= io.nmi_vec @[el2_dec.scala 561:45] - tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[el2_dec.scala 562:45] - tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[el2_dec.scala 563:45] - tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[el2_dec.scala 564:45] - tlu.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec.scala 565:45] - tlu.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[el2_dec.scala 566:45] - tlu.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[el2_dec.scala 567:45] - tlu.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[el2_dec.scala 568:45] - tlu.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[el2_dec.scala 569:45] - tlu.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[el2_dec.scala 570:45] - tlu.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[el2_dec.scala 571:45] - tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[el2_dec.scala 572:45] - tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[el2_dec.scala 573:45] - tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[el2_dec.scala 574:45] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[el2_dec.scala 575:45] - tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 576:45] - tlu.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 577:45] - tlu.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec.scala 578:45] - tlu.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[el2_dec.scala 579:45] - tlu.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[el2_dec.scala 580:45] - tlu.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[el2_dec.scala 581:45] - tlu.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[el2_dec.scala 582:45] - tlu.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 583:45] - tlu.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[el2_dec.scala 584:45] - tlu.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[el2_dec.scala 585:45] - tlu.io.lsu_pmu_load_external_m <= io.lsu_pmu_load_external_m @[el2_dec.scala 586:45] - tlu.io.lsu_pmu_store_external_m <= io.lsu_pmu_store_external_m @[el2_dec.scala 587:45] - tlu.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec.scala 588:45] - tlu.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec.scala 589:45] - tlu.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec.scala 590:45] - tlu.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec.scala 591:45] - tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[el2_dec.scala 592:45] - tlu.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec.scala 593:45] - tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec.scala 594:45] - tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec.scala 595:45] - tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec.scala 595:45] - tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[el2_dec.scala 596:45] - tlu.io.dec_pause_state <= decode.io.dec_pause_state @[el2_dec.scala 597:45] - tlu.io.lsu_imprecise_error_store_any <= io.lsu_imprecise_error_store_any @[el2_dec.scala 598:45] - tlu.io.lsu_imprecise_error_load_any <= io.lsu_imprecise_error_load_any @[el2_dec.scala 599:45] - tlu.io.lsu_imprecise_error_addr_any <= io.lsu_imprecise_error_addr_any @[el2_dec.scala 600:45] - tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[el2_dec.scala 601:45] - tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[el2_dec.scala 602:45] - tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[el2_dec.scala 603:45] - tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[el2_dec.scala 604:45] - tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[el2_dec.scala 605:45] - tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[el2_dec.scala 606:45] - tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[el2_dec.scala 607:45] - tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[el2_dec.scala 608:45] - tlu.io.exu_npc_r <= io.exu_npc_r @[el2_dec.scala 609:45] - tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[el2_dec.scala 610:45] - tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[el2_dec.scala 611:45] - tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[el2_dec.scala 611:45] - tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[el2_dec.scala 612:45] - tlu.io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 613:45] - tlu.io.exu_i0_br_hist_r <= io.exu_i0_br_hist_r @[el2_dec.scala 614:45] - tlu.io.exu_i0_br_error_r <= io.exu_i0_br_error_r @[el2_dec.scala 615:45] - tlu.io.exu_i0_br_start_error_r <= io.exu_i0_br_start_error_r @[el2_dec.scala 616:45] - tlu.io.exu_i0_br_valid_r <= io.exu_i0_br_valid_r @[el2_dec.scala 617:45] - tlu.io.exu_i0_br_mp_r <= io.exu_i0_br_mp_r @[el2_dec.scala 618:45] - tlu.io.exu_i0_br_middle_r <= io.exu_i0_br_middle_r @[el2_dec.scala 619:45] - tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[el2_dec.scala 620:45] - tlu.io.dbg_halt_req <= io.dbg_halt_req @[el2_dec.scala 621:45] - tlu.io.dbg_resume_req <= io.dbg_resume_req @[el2_dec.scala 622:45] - tlu.io.ifu_miss_state_idle <= io.ifu_miss_state_idle @[el2_dec.scala 623:45] - tlu.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 624:45] - tlu.io.dec_div_active <= decode.io.dec_div_active @[el2_dec.scala 625:45] - tlu.io.ifu_ic_error_start <= io.ifu_ic_error_start @[el2_dec.scala 626:45] - tlu.io.ifu_iccm_rd_ecc_single_err <= io.ifu_iccm_rd_ecc_single_err @[el2_dec.scala 627:45] - tlu.io.ifu_ic_debug_rd_data <= io.ifu_ic_debug_rd_data @[el2_dec.scala 628:45] - tlu.io.ifu_ic_debug_rd_data_valid <= io.ifu_ic_debug_rd_data_valid @[el2_dec.scala 629:45] - tlu.io.pic_claimid <= io.pic_claimid @[el2_dec.scala 630:45] - tlu.io.pic_pl <= io.pic_pl @[el2_dec.scala 631:45] - tlu.io.mhwakeup <= io.mhwakeup @[el2_dec.scala 632:45] - tlu.io.mexintpend <= io.mexintpend @[el2_dec.scala 633:45] - tlu.io.timer_int <= io.timer_int @[el2_dec.scala 634:45] - tlu.io.soft_int <= io.soft_int @[el2_dec.scala 635:45] - tlu.io.core_id <= io.core_id @[el2_dec.scala 636:45] - tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[el2_dec.scala 637:45] - tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[el2_dec.scala 638:45] - tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec.scala 639:45] - io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[el2_dec.scala 641:28] - io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[el2_dec.scala 642:28] - io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[el2_dec.scala 643:28] - io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[el2_dec.scala 644:28] - io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[el2_dec.scala 645:28] - decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[el2_dec.scala 646:36] - io.dec_tlu_flush_noredir_r <= tlu.io.dec_tlu_flush_noredir_r @[el2_dec.scala 647:34] - io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[el2_dec.scala 648:34] - io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 649:34] - io.dec_tlu_flush_err_r <= tlu.io.dec_tlu_flush_err_r @[el2_dec.scala 650:34] - decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 651:37] - io.dec_tlu_meihap <= tlu.io.dec_tlu_meihap @[el2_dec.scala 652:29] - io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 653:29] - io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 653:29] - io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 653:29] - io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 653:29] - io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 653:29] - io.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec.scala 654:29] - io.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec.scala 654:29] - io.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec.scala 654:29] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec.scala 654:29] - io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[el2_dec.scala 655:29] - io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[el2_dec.scala 656:29] - io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[el2_dec.scala 657:29] - io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[el2_dec.scala 658:29] - io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[el2_dec.scala 659:29] - io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[el2_dec.scala 660:29] - io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[el2_dec.scala 661:29] - io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[el2_dec.scala 662:29] - io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[el2_dec.scala 663:29] - decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[el2_dec.scala 664:33] - decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[el2_dec.scala 665:33] - io.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.dec_tlu_br0_r_pkt.bits.middle @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.bits.way <= tlu.io.dec_tlu_br0_r_pkt.bits.way @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.dec_tlu_br0_r_pkt.bits.hist @[el2_dec.scala 666:42] - io.dec_tlu_br0_r_pkt.valid <= tlu.io.dec_tlu_br0_r_pkt.valid @[el2_dec.scala 666:42] - decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[el2_dec.scala 667:42] - decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[el2_dec.scala 668:42] - io.dec_tlu_i0_commit_cmt <= tlu.io.dec_tlu_i0_commit_cmt @[el2_dec.scala 669:34] - io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 670:34] - io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 671:34] - io.dec_tlu_flush_path_r <= tlu.io.dec_tlu_flush_path_r @[el2_dec.scala 672:34] - io.dec_tlu_fence_i_r <= tlu.io.dec_tlu_fence_i_r @[el2_dec.scala 673:34] - decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[el2_dec.scala 674:35] - decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[el2_dec.scala 675:35] - decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[el2_dec.scala 676:35] - decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[el2_dec.scala 677:35] - io.dec_tlu_mrac_ff <= tlu.io.dec_tlu_mrac_ff @[el2_dec.scala 678:29] - io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 679:29] - io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[el2_dec.scala 680:29] - io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[el2_dec.scala 681:29] - io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[el2_dec.scala 682:29] - io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[el2_dec.scala 683:29] - dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec.scala 684:32] - dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[el2_dec.scala 685:32] - dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[el2_dec.scala 686:32] - dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[el2_dec.scala 687:32] - dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[el2_dec.scala 688:32] - io.dec_tlu_external_ldfwd_disable <= tlu.io.dec_tlu_external_ldfwd_disable @[el2_dec.scala 689:43] - io.dec_tlu_sideeffect_posted_disable <= tlu.io.dec_tlu_sideeffect_posted_disable @[el2_dec.scala 690:43] - io.dec_tlu_core_ecc_disable <= tlu.io.dec_tlu_core_ecc_disable @[el2_dec.scala 691:43] - io.dec_tlu_bpred_disable <= tlu.io.dec_tlu_bpred_disable @[el2_dec.scala 692:43] - io.dec_tlu_wb_coalescing_disable <= tlu.io.dec_tlu_wb_coalescing_disable @[el2_dec.scala 693:43] - io.dec_tlu_dma_qos_prty <= tlu.io.dec_tlu_dma_qos_prty @[el2_dec.scala 695:35] - io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[el2_dec.scala 696:35] - io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[el2_dec.scala 698:36] - io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[el2_dec.scala 699:36] - io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[el2_dec.scala 700:36] - io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[el2_dec.scala 701:36] - io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[el2_dec.scala 702:36] - io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[el2_dec.scala 703:36] - io.rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb1 @[el2_dec.scala 707:32] + io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 291:18] + instbuff.io.dbg_cmd_valid <= io.dbg_cmd_valid @[el2_dec.scala 297:45] + instbuff.io.dbg_cmd_write <= io.dbg_cmd_write @[el2_dec.scala 298:45] + instbuff.io.dbg_cmd_type <= io.dbg_cmd_type @[el2_dec.scala 299:45] + instbuff.io.dbg_cmd_addr <= io.dbg_cmd_addr @[el2_dec.scala 300:45] + instbuff.io.i0_brp.ret <= io.i0_brp.ret @[el2_dec.scala 301:55] + instbuff.io.i0_brp.way <= io.i0_brp.way @[el2_dec.scala 301:55] + instbuff.io.i0_brp.prett <= io.i0_brp.prett @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bank <= io.i0_brp.bank @[el2_dec.scala 301:55] + instbuff.io.i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec.scala 301:55] + instbuff.io.i0_brp.br_error <= io.i0_brp.br_error @[el2_dec.scala 301:55] + instbuff.io.i0_brp.hist <= io.i0_brp.hist @[el2_dec.scala 301:55] + instbuff.io.i0_brp.toffset <= io.i0_brp.toffset @[el2_dec.scala 301:55] + instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 301:55] + instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 302:35] + instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 303:35] + instbuff.io.ifu_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec.scala 304:35] + instbuff.io.ifu_i0_pc4 <= io.ifu_i0_pc4 @[el2_dec.scala 305:35] + instbuff.io.ifu_i0_valid <= io.ifu_i0_valid @[el2_dec.scala 306:35] + instbuff.io.ifu_i0_icaf <= io.ifu_i0_icaf @[el2_dec.scala 307:35] + instbuff.io.ifu_i0_icaf_type <= io.ifu_i0_icaf_type @[el2_dec.scala 308:35] + instbuff.io.ifu_i0_icaf_f1 <= io.ifu_i0_icaf_f1 @[el2_dec.scala 309:35] + instbuff.io.ifu_i0_dbecc <= io.ifu_i0_dbecc @[el2_dec.scala 310:35] + instbuff.io.ifu_i0_instr <= io.ifu_i0_instr @[el2_dec.scala 311:35] + instbuff.io.ifu_i0_pc <= io.ifu_i0_pc @[el2_dec.scala 312:35] + io.dec_debug_wdata_rs1_d <= instbuff.io.dec_debug_wdata_rs1_d @[el2_dec.scala 314:38] + dec_trigger.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 320:30] + dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 321:34] + decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 330:48] + decode.io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 331:48] + decode.io.ifu_i0_cinst <= io.ifu_i0_cinst @[el2_dec.scala 332:48] + decode.io.lsu_nonblock_load_valid_m <= io.lsu_nonblock_load_valid_m @[el2_dec.scala 333:48] + decode.io.lsu_nonblock_load_tag_m <= io.lsu_nonblock_load_tag_m @[el2_dec.scala 334:48] + decode.io.lsu_nonblock_load_inv_r <= io.lsu_nonblock_load_inv_r @[el2_dec.scala 335:48] + decode.io.lsu_nonblock_load_inv_tag_r <= io.lsu_nonblock_load_inv_tag_r @[el2_dec.scala 336:48] + decode.io.lsu_nonblock_load_data_valid <= io.lsu_nonblock_load_data_valid @[el2_dec.scala 337:48] + decode.io.lsu_nonblock_load_data_error <= io.lsu_nonblock_load_data_error @[el2_dec.scala 338:48] + decode.io.lsu_nonblock_load_data_tag <= io.lsu_nonblock_load_data_tag @[el2_dec.scala 339:48] + decode.io.lsu_nonblock_load_data <= io.lsu_nonblock_load_data @[el2_dec.scala 340:48] + decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[el2_dec.scala 341:48] + decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[el2_dec.scala 342:48] + decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[el2_dec.scala 343:48] + decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[el2_dec.scala 344:48] + decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 345:48] + decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[el2_dec.scala 346:48] + decode.io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 347:48] + decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[el2_dec.scala 348:48] + decode.io.dbg_cmd_wrdata <= io.dbg_cmd_wrdata @[el2_dec.scala 349:48] + decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[el2_dec.scala 350:48] + decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 351:48] + decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 352:48] + decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 353:48] + decode.io.dec_i0_brp.ret <= instbuff.io.dec_i0_brp.ret @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.way <= instbuff.io.dec_i0_brp.way @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.prett <= instbuff.io.dec_i0_brp.prett @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bank <= instbuff.io.dec_i0_brp.bank @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.br_start_error <= instbuff.io.dec_i0_brp.br_start_error @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.br_error <= instbuff.io.dec_i0_brp.br_error @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.hist <= instbuff.io.dec_i0_brp.hist @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.toffset <= instbuff.io.dec_i0_brp.toffset @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 354:48] + decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 355:48] + decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 356:48] + decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[el2_dec.scala 357:48] + decode.io.dec_i0_pc_d <= instbuff.io.dec_i0_pc_d @[el2_dec.scala 358:48] + decode.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 359:48] + decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[el2_dec.scala 360:48] + decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 361:48] + decode.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 362:48] + decode.io.exu_div_wren <= io.exu_div_wren @[el2_dec.scala 363:48] + decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[el2_dec.scala 364:48] + decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[el2_dec.scala 365:48] + decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 366:48] + decode.io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 367:48] + decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[el2_dec.scala 368:48] + decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[el2_dec.scala 369:48] + decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[el2_dec.scala 370:48] + decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[el2_dec.scala 371:48] + decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[el2_dec.scala 372:48] + decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[el2_dec.scala 373:48] + decode.io.exu_csr_rs1_x <= io.exu_csr_rs1_x @[el2_dec.scala 374:48] + decode.io.lsu_result_m <= io.lsu_result_m @[el2_dec.scala 375:48] + decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[el2_dec.scala 376:48] + decode.io.exu_flush_final <= io.exu_flush_final @[el2_dec.scala 377:48] + decode.io.exu_i0_pc_x <= io.exu_i0_pc_x @[el2_dec.scala 378:48] + decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[el2_dec.scala 379:48] + decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[el2_dec.scala 380:48] + decode.io.exu_i0_result_x <= io.exu_i0_result_x @[el2_dec.scala 381:48] + decode.io.free_clk <= io.free_clk @[el2_dec.scala 383:48] + decode.io.active_clk <= io.active_clk @[el2_dec.scala 384:48] + decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[el2_dec.scala 385:48] + decode.io.scan_mode <= io.scan_mode @[el2_dec.scala 387:48] + io.dec_extint_stall <= decode.io.dec_extint_stall @[el2_dec.scala 389:40] + dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb1 @[el2_dec.scala 390:40] + dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb1 @[el2_dec.scala 391:40] + io.dec_i0_rs1_en_d <= decode.io.dec_i0_rs1_en_d @[el2_dec.scala 392:40] + io.dec_i0_rs2_en_d <= decode.io.dec_i0_rs2_en_d @[el2_dec.scala 393:40] + io.dec_i0_immed_d <= decode.io.dec_i0_immed_d @[el2_dec.scala 394:40] + io.dec_i0_br_immed_d <= decode.io.dec_i0_br_immed_d @[el2_dec.scala 395:40] + io.i0_ap.csr_imm <= decode.io.i0_ap.csr_imm @[el2_dec.scala 396:40] + io.i0_ap.csr_write <= decode.io.i0_ap.csr_write @[el2_dec.scala 396:40] + io.i0_ap.predict_nt <= decode.io.i0_ap.predict_nt @[el2_dec.scala 396:40] + io.i0_ap.predict_t <= decode.io.i0_ap.predict_t @[el2_dec.scala 396:40] + io.i0_ap.jal <= decode.io.i0_ap.jal @[el2_dec.scala 396:40] + io.i0_ap.unsign <= decode.io.i0_ap.unsign @[el2_dec.scala 396:40] + io.i0_ap.slt <= decode.io.i0_ap.slt @[el2_dec.scala 396:40] + io.i0_ap.sub <= decode.io.i0_ap.sub @[el2_dec.scala 396:40] + io.i0_ap.add <= decode.io.i0_ap.add @[el2_dec.scala 396:40] + io.i0_ap.bge <= decode.io.i0_ap.bge @[el2_dec.scala 396:40] + io.i0_ap.blt <= decode.io.i0_ap.blt @[el2_dec.scala 396:40] + io.i0_ap.bne <= decode.io.i0_ap.bne @[el2_dec.scala 396:40] + io.i0_ap.beq <= decode.io.i0_ap.beq @[el2_dec.scala 396:40] + io.i0_ap.sra <= decode.io.i0_ap.sra @[el2_dec.scala 396:40] + io.i0_ap.srl <= decode.io.i0_ap.srl @[el2_dec.scala 396:40] + io.i0_ap.sll <= decode.io.i0_ap.sll @[el2_dec.scala 396:40] + io.i0_ap.lxor <= decode.io.i0_ap.lxor @[el2_dec.scala 396:40] + io.i0_ap.lor <= decode.io.i0_ap.lor @[el2_dec.scala 396:40] + io.i0_ap.land <= decode.io.i0_ap.land @[el2_dec.scala 396:40] + io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 397:40] + io.dec_i0_alu_decode_d <= decode.io.dec_i0_alu_decode_d @[el2_dec.scala 398:40] + io.dec_i0_rs1_bypass_data_d <= decode.io.dec_i0_rs1_bypass_data_d @[el2_dec.scala 399:40] + io.dec_i0_rs2_bypass_data_d <= decode.io.dec_i0_rs2_bypass_data_d @[el2_dec.scala 400:40] + io.dec_i0_select_pc_d <= decode.io.dec_i0_select_pc_d @[el2_dec.scala 401:40] + io.dec_i0_rs1_bypass_en_d <= decode.io.dec_i0_rs1_bypass_en_d @[el2_dec.scala 402:40] + io.dec_i0_rs2_bypass_en_d <= decode.io.dec_i0_rs2_bypass_en_d @[el2_dec.scala 403:40] + io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[el2_dec.scala 404:40] + io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[el2_dec.scala 404:40] + io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[el2_dec.scala 404:40] + io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[el2_dec.scala 404:40] + io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[el2_dec.scala 404:40] + io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[el2_dec.scala 404:40] + io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[el2_dec.scala 404:40] + io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[el2_dec.scala 404:40] + io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[el2_dec.scala 404:40] + io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[el2_dec.scala 404:40] + io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[el2_dec.scala 404:40] + io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[el2_dec.scala 404:40] + io.lsu_p.valid <= decode.io.lsu_p.valid @[el2_dec.scala 404:40] + io.mul_p.bits.bfp <= decode.io.mul_p.bits.bfp @[el2_dec.scala 405:40] + io.mul_p.bits.crc32c_w <= decode.io.mul_p.bits.crc32c_w @[el2_dec.scala 405:40] + io.mul_p.bits.crc32c_h <= decode.io.mul_p.bits.crc32c_h @[el2_dec.scala 405:40] + io.mul_p.bits.crc32c_b <= decode.io.mul_p.bits.crc32c_b @[el2_dec.scala 405:40] + io.mul_p.bits.crc32_w <= decode.io.mul_p.bits.crc32_w @[el2_dec.scala 405:40] + io.mul_p.bits.crc32_h <= decode.io.mul_p.bits.crc32_h @[el2_dec.scala 405:40] + io.mul_p.bits.crc32_b <= decode.io.mul_p.bits.crc32_b @[el2_dec.scala 405:40] + io.mul_p.bits.unshfl <= decode.io.mul_p.bits.unshfl @[el2_dec.scala 405:40] + io.mul_p.bits.shfl <= decode.io.mul_p.bits.shfl @[el2_dec.scala 405:40] + io.mul_p.bits.grev <= decode.io.mul_p.bits.grev @[el2_dec.scala 405:40] + io.mul_p.bits.clmulr <= decode.io.mul_p.bits.clmulr @[el2_dec.scala 405:40] + io.mul_p.bits.clmulh <= decode.io.mul_p.bits.clmulh @[el2_dec.scala 405:40] + io.mul_p.bits.clmul <= decode.io.mul_p.bits.clmul @[el2_dec.scala 405:40] + io.mul_p.bits.bdep <= decode.io.mul_p.bits.bdep @[el2_dec.scala 405:40] + io.mul_p.bits.bext <= decode.io.mul_p.bits.bext @[el2_dec.scala 405:40] + io.mul_p.bits.low <= decode.io.mul_p.bits.low @[el2_dec.scala 405:40] + io.mul_p.bits.rs2_sign <= decode.io.mul_p.bits.rs2_sign @[el2_dec.scala 405:40] + io.mul_p.bits.rs1_sign <= decode.io.mul_p.bits.rs1_sign @[el2_dec.scala 405:40] + io.mul_p.valid <= decode.io.mul_p.valid @[el2_dec.scala 405:40] + io.div_p.bits.rem <= decode.io.div_p.bits.rem @[el2_dec.scala 406:40] + io.div_p.bits.unsign <= decode.io.div_p.bits.unsign @[el2_dec.scala 406:40] + io.div_p.valid <= decode.io.div_p.valid @[el2_dec.scala 406:40] + io.dec_div_cancel <= decode.io.dec_div_cancel @[el2_dec.scala 407:40] + io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[el2_dec.scala 408:40] + io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[el2_dec.scala 409:40] + io.dec_csr_ren_d <= decode.io.dec_csr_ren_d @[el2_dec.scala 410:40] + io.pred_correct_npc_x <= decode.io.pred_correct_npc_x @[el2_dec.scala 411:40] + io.dec_i0_predict_p_d.bits.way <= decode.io.dec_i0_predict_p_d.bits.way @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.pja <= decode.io.dec_i0_predict_p_d.bits.pja @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.pret <= decode.io.dec_i0_predict_p_d.bits.pret @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.pcall <= decode.io.dec_i0_predict_p_d.bits.pcall @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.prett <= decode.io.dec_i0_predict_p_d.bits.prett @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.br_start_error <= decode.io.dec_i0_predict_p_d.bits.br_start_error @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.br_error <= decode.io.dec_i0_predict_p_d.bits.br_error @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.toffset <= decode.io.dec_i0_predict_p_d.bits.toffset @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.hist <= decode.io.dec_i0_predict_p_d.bits.hist @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.pc4 <= decode.io.dec_i0_predict_p_d.bits.pc4 @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.boffset <= decode.io.dec_i0_predict_p_d.bits.boffset @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.ataken <= decode.io.dec_i0_predict_p_d.bits.ataken @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.bits.misp <= decode.io.dec_i0_predict_p_d.bits.misp @[el2_dec.scala 412:40] + io.dec_i0_predict_p_d.valid <= decode.io.dec_i0_predict_p_d.valid @[el2_dec.scala 412:40] + io.i0_predict_fghr_d <= decode.io.i0_predict_fghr_d @[el2_dec.scala 413:40] + io.i0_predict_index_d <= decode.io.i0_predict_index_d @[el2_dec.scala 414:40] + io.i0_predict_btag_d <= decode.io.i0_predict_btag_d @[el2_dec.scala 415:40] + io.dec_data_en <= decode.io.dec_data_en @[el2_dec.scala 416:40] + io.dec_ctl_en <= decode.io.dec_ctl_en @[el2_dec.scala 417:40] + io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[el2_dec.scala 418:40] + gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[el2_dec.scala 425:23] + gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[el2_dec.scala 426:23] + gpr.io.wen0 <= decode.io.dec_i0_wen_r @[el2_dec.scala 427:23] + gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[el2_dec.scala 428:23] + gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[el2_dec.scala 429:23] + gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[el2_dec.scala 430:23] + gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[el2_dec.scala 431:23] + gpr.io.wd1 <= io.lsu_nonblock_load_data @[el2_dec.scala 432:23] + gpr.io.wen2 <= io.exu_div_wren @[el2_dec.scala 433:23] + gpr.io.waddr2 <= decode.io.div_waddr_wb @[el2_dec.scala 434:23] + gpr.io.wd2 <= io.exu_div_result @[el2_dec.scala 435:23] + gpr.io.scan_mode <= io.scan_mode @[el2_dec.scala 438:23] + io.gpr_i0_rs1_d <= gpr.io.rd0 @[el2_dec.scala 440:19] + io.gpr_i0_rs2_d <= gpr.io.rd1 @[el2_dec.scala 441:19] + tlu.io.active_clk <= io.active_clk @[el2_dec.scala 450:45] + tlu.io.free_clk <= io.free_clk @[el2_dec.scala 451:45] + tlu.io.scan_mode <= io.scan_mode @[el2_dec.scala 453:45] + tlu.io.rst_vec <= io.rst_vec @[el2_dec.scala 454:45] + tlu.io.nmi_int <= io.nmi_int @[el2_dec.scala 455:45] + tlu.io.nmi_vec <= io.nmi_vec @[el2_dec.scala 456:45] + tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[el2_dec.scala 457:45] + tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[el2_dec.scala 458:45] + tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[el2_dec.scala 459:45] + tlu.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[el2_dec.scala 460:45] + tlu.io.ifu_pmu_fetch_stall <= io.ifu_pmu_fetch_stall @[el2_dec.scala 461:45] + tlu.io.ifu_pmu_ic_miss <= io.ifu_pmu_ic_miss @[el2_dec.scala 462:45] + tlu.io.ifu_pmu_ic_hit <= io.ifu_pmu_ic_hit @[el2_dec.scala 463:45] + tlu.io.ifu_pmu_bus_error <= io.ifu_pmu_bus_error @[el2_dec.scala 464:45] + tlu.io.ifu_pmu_bus_busy <= io.ifu_pmu_bus_busy @[el2_dec.scala 465:45] + tlu.io.ifu_pmu_bus_trxn <= io.ifu_pmu_bus_trxn @[el2_dec.scala 466:45] + tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[el2_dec.scala 467:45] + tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[el2_dec.scala 468:45] + tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[el2_dec.scala 469:45] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[el2_dec.scala 470:45] + tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[el2_dec.scala 471:45] + tlu.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[el2_dec.scala 472:45] + tlu.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[el2_dec.scala 473:45] + tlu.io.exu_pmu_i0_br_misp <= io.exu_pmu_i0_br_misp @[el2_dec.scala 474:45] + tlu.io.exu_pmu_i0_br_ataken <= io.exu_pmu_i0_br_ataken @[el2_dec.scala 475:45] + tlu.io.exu_pmu_i0_pc4 <= io.exu_pmu_i0_pc4 @[el2_dec.scala 476:45] + tlu.io.lsu_pmu_bus_trxn <= io.lsu_pmu_bus_trxn @[el2_dec.scala 477:45] + tlu.io.lsu_pmu_bus_misaligned <= io.lsu_pmu_bus_misaligned @[el2_dec.scala 478:45] + tlu.io.lsu_pmu_bus_error <= io.lsu_pmu_bus_error @[el2_dec.scala 479:45] + tlu.io.lsu_pmu_bus_busy <= io.lsu_pmu_bus_busy @[el2_dec.scala 480:45] + tlu.io.lsu_pmu_load_external_m <= io.lsu_pmu_load_external_m @[el2_dec.scala 481:45] + tlu.io.lsu_pmu_store_external_m <= io.lsu_pmu_store_external_m @[el2_dec.scala 482:45] + tlu.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[el2_dec.scala 483:45] + tlu.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[el2_dec.scala 484:45] + tlu.io.dma_pmu_any_read <= io.dma_pmu_any_read @[el2_dec.scala 485:45] + tlu.io.dma_pmu_any_write <= io.dma_pmu_any_write @[el2_dec.scala 486:45] + tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[el2_dec.scala 487:45] + tlu.io.lsu_fir_error <= io.lsu_fir_error @[el2_dec.scala 488:45] + tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[el2_dec.scala 489:45] + tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[el2_dec.scala 490:45] + tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[el2_dec.scala 490:45] + tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[el2_dec.scala 491:45] + tlu.io.dec_pause_state <= decode.io.dec_pause_state @[el2_dec.scala 492:45] + tlu.io.lsu_imprecise_error_store_any <= io.lsu_imprecise_error_store_any @[el2_dec.scala 493:45] + tlu.io.lsu_imprecise_error_load_any <= io.lsu_imprecise_error_load_any @[el2_dec.scala 494:45] + tlu.io.lsu_imprecise_error_addr_any <= io.lsu_imprecise_error_addr_any @[el2_dec.scala 495:45] + tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[el2_dec.scala 496:45] + tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[el2_dec.scala 497:45] + tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[el2_dec.scala 498:45] + tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[el2_dec.scala 499:45] + tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[el2_dec.scala 500:45] + tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[el2_dec.scala 501:45] + tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[el2_dec.scala 502:45] + tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[el2_dec.scala 503:45] + tlu.io.exu_npc_r <= io.exu_npc_r @[el2_dec.scala 504:45] + tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[el2_dec.scala 505:45] + tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[el2_dec.scala 506:45] + tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[el2_dec.scala 506:45] + tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[el2_dec.scala 507:45] + tlu.io.dec_i0_decode_d <= decode.io.dec_i0_decode_d @[el2_dec.scala 508:45] + tlu.io.exu_i0_br_hist_r <= io.exu_i0_br_hist_r @[el2_dec.scala 509:45] + tlu.io.exu_i0_br_error_r <= io.exu_i0_br_error_r @[el2_dec.scala 510:45] + tlu.io.exu_i0_br_start_error_r <= io.exu_i0_br_start_error_r @[el2_dec.scala 511:45] + tlu.io.exu_i0_br_valid_r <= io.exu_i0_br_valid_r @[el2_dec.scala 512:45] + tlu.io.exu_i0_br_mp_r <= io.exu_i0_br_mp_r @[el2_dec.scala 513:45] + tlu.io.exu_i0_br_middle_r <= io.exu_i0_br_middle_r @[el2_dec.scala 514:45] + tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[el2_dec.scala 515:45] + tlu.io.dbg_halt_req <= io.dbg_halt_req @[el2_dec.scala 516:45] + tlu.io.dbg_resume_req <= io.dbg_resume_req @[el2_dec.scala 517:45] + tlu.io.ifu_miss_state_idle <= io.ifu_miss_state_idle @[el2_dec.scala 518:45] + tlu.io.lsu_idle_any <= io.lsu_idle_any @[el2_dec.scala 519:45] + tlu.io.dec_div_active <= decode.io.dec_div_active @[el2_dec.scala 520:45] + tlu.io.ifu_ic_error_start <= io.ifu_ic_error_start @[el2_dec.scala 521:45] + tlu.io.ifu_iccm_rd_ecc_single_err <= io.ifu_iccm_rd_ecc_single_err @[el2_dec.scala 522:45] + tlu.io.ifu_ic_debug_rd_data <= io.ifu_ic_debug_rd_data @[el2_dec.scala 523:45] + tlu.io.ifu_ic_debug_rd_data_valid <= io.ifu_ic_debug_rd_data_valid @[el2_dec.scala 524:45] + tlu.io.pic_claimid <= io.pic_claimid @[el2_dec.scala 525:45] + tlu.io.pic_pl <= io.pic_pl @[el2_dec.scala 526:45] + tlu.io.mhwakeup <= io.mhwakeup @[el2_dec.scala 527:45] + tlu.io.mexintpend <= io.mexintpend @[el2_dec.scala 528:45] + tlu.io.timer_int <= io.timer_int @[el2_dec.scala 529:45] + tlu.io.soft_int <= io.soft_int @[el2_dec.scala 530:45] + tlu.io.core_id <= io.core_id @[el2_dec.scala 531:45] + tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[el2_dec.scala 532:45] + tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[el2_dec.scala 533:45] + tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_dec.scala 534:45] + io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[el2_dec.scala 536:28] + io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[el2_dec.scala 537:28] + io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[el2_dec.scala 538:28] + io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[el2_dec.scala 539:28] + io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[el2_dec.scala 540:28] + io.dec_tlu_flush_noredir_r <= tlu.io.dec_tlu_flush_noredir_r @[el2_dec.scala 541:34] + io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[el2_dec.scala 542:34] + io.dec_tlu_flush_leak_one_r <= tlu.io.dec_tlu_flush_leak_one_r @[el2_dec.scala 543:34] + io.dec_tlu_flush_err_r <= tlu.io.dec_tlu_flush_err_r @[el2_dec.scala 544:34] + io.dec_tlu_meihap <= tlu.io.dec_tlu_meihap @[el2_dec.scala 545:29] + io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 546:29] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec.scala 547:29] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec.scala 547:29] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_dec.scala 547:29] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_dec.scala 547:29] + io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[el2_dec.scala 548:29] + io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[el2_dec.scala 549:29] + io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[el2_dec.scala 550:29] + io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[el2_dec.scala 551:29] + io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[el2_dec.scala 552:29] + io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[el2_dec.scala 553:29] + io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[el2_dec.scala 554:29] + io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[el2_dec.scala 555:29] + io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[el2_dec.scala 556:29] + io.dec_tlu_br0_r_pkt.middle <= tlu.io.dec_tlu_br0_r_pkt.middle @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.way <= tlu.io.dec_tlu_br0_r_pkt.way @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.br_start_error @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.br_error <= tlu.io.dec_tlu_br0_r_pkt.br_error @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.hist <= tlu.io.dec_tlu_br0_r_pkt.hist @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.valid <= tlu.io.dec_tlu_br0_r_pkt.valid @[el2_dec.scala 557:42] + io.dec_tlu_i0_commit_cmt <= tlu.io.dec_tlu_i0_commit_cmt @[el2_dec.scala 558:34] + io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 559:34] + io.dec_tlu_flush_lower_r <= tlu.io.dec_tlu_flush_lower_r @[el2_dec.scala 560:34] + io.dec_tlu_flush_path_r <= tlu.io.dec_tlu_flush_path_r @[el2_dec.scala 561:34] + io.dec_tlu_fence_i_r <= tlu.io.dec_tlu_fence_i_r @[el2_dec.scala 562:34] + io.dec_tlu_mrac_ff <= tlu.io.dec_tlu_mrac_ff @[el2_dec.scala 563:29] + io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 564:29] + io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[el2_dec.scala 565:29] + io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[el2_dec.scala 566:29] + io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[el2_dec.scala 567:29] + io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[el2_dec.scala 568:29] + dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[el2_dec.scala 569:32] + dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[el2_dec.scala 570:32] + dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[el2_dec.scala 571:32] + dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[el2_dec.scala 572:32] + dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[el2_dec.scala 573:32] + io.dec_tlu_external_ldfwd_disable <= tlu.io.dec_tlu_external_ldfwd_disable @[el2_dec.scala 574:43] + io.dec_tlu_sideeffect_posted_disable <= tlu.io.dec_tlu_sideeffect_posted_disable @[el2_dec.scala 575:43] + io.dec_tlu_core_ecc_disable <= tlu.io.dec_tlu_core_ecc_disable @[el2_dec.scala 576:43] + io.dec_tlu_bpred_disable <= tlu.io.dec_tlu_bpred_disable @[el2_dec.scala 577:43] + io.dec_tlu_wb_coalescing_disable <= tlu.io.dec_tlu_wb_coalescing_disable @[el2_dec.scala 578:43] + io.dec_tlu_dma_qos_prty <= tlu.io.dec_tlu_dma_qos_prty @[el2_dec.scala 579:35] + io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[el2_dec.scala 580:35] + io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[el2_dec.scala 581:36] + io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[el2_dec.scala 582:36] + io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[el2_dec.scala 583:36] + io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[el2_dec.scala 584:36] + io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[el2_dec.scala 585:36] + io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[el2_dec.scala 586:36] + io.rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb1 @[el2_dec.scala 590:32] node _T = cat(decode.io.dec_i0_pc_wb1, UInt<1>("h00")) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_address_ip <= _T @[el2_dec.scala 708:35] - node _T_1 = or(tlu.io.dec_tlu_i0_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[el2_dec.scala 709:98] + io.rv_trace_pkt.rv_i_address_ip <= _T @[el2_dec.scala 591:35] + node _T_1 = or(tlu.io.dec_tlu_i0_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[el2_dec.scala 592:98] node _T_2 = cat(tlu.io.dec_tlu_int_valid_wb1, _T_1) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_valid_ip <= _T_2 @[el2_dec.scala 709:33] + io.rv_trace_pkt.rv_i_valid_ip <= _T_2 @[el2_dec.scala 592:33] node _T_3 = cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_exception_ip <= _T_3 @[el2_dec.scala 710:37] - node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[el2_dec.scala 711:65] - io.rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[el2_dec.scala 711:34] + io.rv_trace_pkt.rv_i_exception_ip <= _T_3 @[el2_dec.scala 593:37] + node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[el2_dec.scala 594:65] + io.rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[el2_dec.scala 594:34] node _T_5 = cat(tlu.io.dec_tlu_int_valid_wb1, UInt<1>("h00")) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_interrupt_ip <= _T_5 @[el2_dec.scala 712:37] - io.rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[el2_dec.scala 713:32] - io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[el2_dec.scala 717:21] + io.rv_trace_pkt.rv_i_interrupt_ip <= _T_5 @[el2_dec.scala 595:37] + io.rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[el2_dec.scala 596:32] + io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[el2_dec.scala 600:21] extmodule gated_latch_755 : output Q : Clock @@ -81458,7 +81663,7 @@ circuit el2_swerv : module el2_dbg : input clock : Clock input reset : AsyncReset - output io : {dbg_cmd_addr : UInt<32>, dbg_cmd_wrdata : UInt<32>, dbg_cmd_valid : UInt<1>, dbg_cmd_write : UInt<1>, dbg_cmd_type : UInt<2>, dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_dma_bubble : UInt<1>, flip dma_dbg_ready : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : AsyncReset, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} + output io : {dbg_cmd_addr : UInt<32>, dbg_cmd_wrdata : UInt<32>, dbg_cmd_valid : UInt<1>, dbg_cmd_write : UInt<1>, dbg_cmd_type : UInt<2>, dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_dma_bubble : UInt<1>, flip dma_dbg_ready : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} wire dbg_state : UInt<3> dbg_state <= UInt<3>("h00") @@ -81537,7 +81742,7 @@ circuit el2_swerv : rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_1.io.en <= sb_free_clken @[el2_lib.scala 485:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - node _T_7 = asUInt(io.dbg_rst_l) @[el2_dbg.scala 130:41] + node _T_7 = bits(io.dbg_rst_l, 0, 0) @[el2_dbg.scala 130:41] node _T_8 = bits(dmcontrol_reg, 0, 0) @[el2_dbg.scala 130:60] node _T_9 = or(_T_8, io.scan_mode) @[el2_dbg.scala 130:64] node dbg_dm_rst_l = and(_T_7, _T_9) @[el2_dbg.scala 130:44] @@ -86466,12 +86671,12 @@ circuit el2_swerv : module el2_lsu_lsc_ctl : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} + output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 96:29] wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 97:29] wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 98:29] - wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 99:29] + wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 99:29] node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 101:52] node lsu_rs1_d = mux(_T, io.exu_lsu_rs1_d, io.dma_mem_addr) @[el2_lsu_lsc_ctl.scala 101:28] node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 102:44] @@ -86645,14 +86850,14 @@ circuit el2_swerv : node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[el2_lsu_lsc_ctl.scala 185:92] node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[el2_lsu_lsc_ctl.scala 185:44] lsu_fir_error_m <= _T_103 @[el2_lsu_lsc_ctl.scala 185:38] - wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 186:104] - _T_104.bits.addr <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] - _T_104.bits.mscause <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.bits.addr <= UInt<32>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.bits.mscause <= UInt<4>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.exc_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.inst_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.single_ecc_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] - reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75] + reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.addr <= lsu_error_pkt_m.bits.addr @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.mscause <= lsu_error_pkt_m.bits.mscause @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[el2_lsu_lsc_ctl.scala 186:75] @@ -92575,7 +92780,7 @@ circuit el2_swerv : module el2_lsu_trigger : input clock : Clock input reset : AsyncReset - output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_1 = mux(_T, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] @@ -92633,7 +92838,7 @@ circuit el2_swerv : node _T_44 = and(_T_42, _T_43) @[el2_lsu_trigger.scala 19:58] node _T_45 = or(_T_41, _T_44) @[el2_lsu_trigger.scala 18:152] node _T_46 = and(_T_40, _T_45) @[el2_lsu_trigger.scala 18:94] - node _T_47 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_47 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_48 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_49 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] node _T_50 = not(_T_49) @[el2_lib.scala 241:39] @@ -92931,7 +93136,7 @@ circuit el2_swerv : node _T_310 = and(_T_308, _T_309) @[el2_lsu_trigger.scala 19:58] node _T_311 = or(_T_307, _T_310) @[el2_lsu_trigger.scala 18:152] node _T_312 = and(_T_306, _T_311) @[el2_lsu_trigger.scala 18:94] - node _T_313 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_313 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_314 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_315 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] node _T_316 = not(_T_315) @[el2_lib.scala 241:39] @@ -93229,7 +93434,7 @@ circuit el2_swerv : node _T_576 = and(_T_574, _T_575) @[el2_lsu_trigger.scala 19:58] node _T_577 = or(_T_573, _T_576) @[el2_lsu_trigger.scala 18:152] node _T_578 = and(_T_572, _T_577) @[el2_lsu_trigger.scala 18:94] - node _T_579 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_579 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_580 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_581 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] node _T_582 = not(_T_581) @[el2_lib.scala 241:39] @@ -93527,7 +93732,7 @@ circuit el2_swerv : node _T_842 = and(_T_840, _T_841) @[el2_lsu_trigger.scala 19:58] node _T_843 = or(_T_839, _T_842) @[el2_lsu_trigger.scala 18:152] node _T_844 = and(_T_838, _T_843) @[el2_lsu_trigger.scala 18:94] - node _T_845 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_845 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_846 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_847 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] node _T_848 = not(_T_847) @[el2_lib.scala 241:39] @@ -101426,7 +101631,7 @@ circuit el2_swerv : module el2_lsu : input clock : Clock input reset : AsyncReset - output io : {flip clk_override : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>, lsu_pmu_misaligned_m : UInt<1>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_trigger_match_m : UInt<4>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, lsu_axi_awvalid : UInt<1>, lsu_axi_awlock : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, lsu_axi_arlock : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rlast : UInt<1>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rid : UInt<3>, flip lsu_bus_clk_en : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_write : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, flip dma_mem_tag : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_wdata : UInt<64>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_ready : UInt<1>, flip scan_mode : UInt<1>, flip free_clk : Clock} + output io : {flip clk_override : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>, lsu_pmu_misaligned_m : UInt<1>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_trigger_match_m : UInt<4>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, lsu_axi_awvalid : UInt<1>, lsu_axi_awlock : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, lsu_axi_arlock : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rlast : UInt<1>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rid : UInt<3>, flip lsu_bus_clk_en : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_write : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, flip dma_mem_tag : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_wdata : UInt<64>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_ready : UInt<1>, flip scan_mode : UInt<1>, flip free_clk : Clock} wire dma_dccm_wdata : UInt<64> dma_dccm_wdata <= UInt<64>("h00") @@ -101798,28 +102003,28 @@ circuit el2_swerv : trigger.io.trigger_pkt_any[0].execute <= io.trigger_pkt_any[0].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[0].load <= io.trigger_pkt_any[0].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[0].store <= io.trigger_pkt_any[0].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[0].match_ <= io.trigger_pkt_any[0].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[0].match_pkt <= io.trigger_pkt_any[0].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[0].select <= io.trigger_pkt_any[0].select @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].tdata2 <= io.trigger_pkt_any[1].tdata2 @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].m <= io.trigger_pkt_any[1].m @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].execute <= io.trigger_pkt_any[1].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].load <= io.trigger_pkt_any[1].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].store <= io.trigger_pkt_any[1].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[1].match_ <= io.trigger_pkt_any[1].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[1].match_pkt <= io.trigger_pkt_any[1].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].select <= io.trigger_pkt_any[1].select @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].tdata2 <= io.trigger_pkt_any[2].tdata2 @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].m <= io.trigger_pkt_any[2].m @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].execute <= io.trigger_pkt_any[2].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].load <= io.trigger_pkt_any[2].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].store <= io.trigger_pkt_any[2].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[2].match_ <= io.trigger_pkt_any[2].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[2].match_pkt <= io.trigger_pkt_any[2].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].select <= io.trigger_pkt_any[2].select @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].tdata2 <= io.trigger_pkt_any[3].tdata2 @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].m <= io.trigger_pkt_any[3].m @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].execute <= io.trigger_pkt_any[3].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].load <= io.trigger_pkt_any[3].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].store <= io.trigger_pkt_any[3].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[3].match_ <= io.trigger_pkt_any[3].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[3].match_pkt <= io.trigger_pkt_any[3].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].select <= io.trigger_pkt_any[3].select @[el2_lsu.scala 376:50] trigger.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[el2_lsu.scala 377:50] trigger.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[el2_lsu.scala 377:50] @@ -108791,39 +108996,38 @@ circuit el2_swerv : module el2_swerv : input clock : Clock input reset : AsyncReset - output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, trace_rv_i_insn_ip : UInt<32>, trace_rv_i_address_ip : UInt<32>, trace_rv_i_valid_ip : UInt<2>, trace_rv_i_exception_ip : UInt<2>, trace_rv_i_ecause_ip : UInt<5>, trace_rv_i_interrupt_ip : UInt<2>, trace_rv_i_tval_ip : UInt<32>, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, iccm_rw_addr : UInt<16>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_size : UInt<3>, iccm_wr_data : UInt<78>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ic_rw_addr : UInt<31>, ic_tag_valid : UInt<2>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rlast : UInt<1>, ifu_axi_awvalid : UInt<1>, flip ifu_axi_awready : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wready : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, flip ifu_axi_bvalid : UInt<1>, ifu_axi_bready : UInt<1>, flip ifu_axi_bresp : UInt<2>, flip ifu_axi_bid : UInt<3>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_axi_rlast : UInt<1>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, flip sb_axi_bid : UInt<1>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rid : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip sb_axi_rlast : UInt<1>, flip dma_axi_awvalid : UInt<1>, dma_axi_awready : UInt<1>, flip dma_axi_awid : UInt<1>, flip dma_axi_awaddr : UInt<32>, flip dma_axi_awsize : UInt<3>, flip dma_axi_awprot : UInt<3>, flip dma_axi_awlen : UInt<8>, flip dma_axi_awburst : UInt<2>, flip dma_axi_wvalid : UInt<1>, dma_axi_wready : UInt<1>, flip dma_axi_wdata : UInt<64>, flip dma_axi_wstrb : UInt<8>, flip dma_axi_wlast : UInt<1>, dma_axi_bvalid : UInt<1>, flip dma_axi_bready : UInt<1>, dma_axi_bresp : UInt<2>, dma_axi_bid : UInt<1>, flip dma_axi_arvalid : UInt<1>, dma_axi_arready : UInt<1>, flip dma_axi_arid : UInt<1>, flip dma_axi_araddr : UInt<32>, flip dma_axi_arsize : UInt<3>, flip dma_axi_arprot : UInt<3>, flip dma_axi_arlen : UInt<8>, flip dma_axi_arburst : UInt<2>, dma_axi_rvalid : UInt<1>, flip dma_axi_rready : UInt<1>, dma_axi_rid : UInt<1>, dma_axi_rdata : UInt<64>, dma_axi_rresp : UInt<2>, dma_axi_rlast : UInt<1>, haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>, lsu_haddr : UInt<32>, lsu_hburst : UInt<3>, lsu_hmastlock : UInt<1>, lsu_hprot : UInt<4>, lsu_hsize : UInt<3>, lsu_htrans : UInt<2>, lsu_hwrite : UInt<1>, lsu_hwdata : UInt<64>, flip lsu_hrdata : UInt<64>, flip lsu_hready : UInt<1>, flip lsu_hresp : UInt<1>, sb_haddr : UInt<32>, sb_hburst : UInt<3>, sb_hmastlock : UInt<1>, sb_hprot : UInt<4>, sb_hsize : UInt<3>, sb_htrans : UInt<2>, sb_hwrite : UInt<1>, sb_hwdata : UInt<64>, flip sb_hrdata : UInt<64>, flip sb_hready : UInt<1>, flip sb_hresp : UInt<1>, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, trace_rv_i_insn_ip : UInt<32>, trace_rv_i_address_ip : UInt<32>, trace_rv_i_valid_ip : UInt<2>, trace_rv_i_exception_ip : UInt<2>, trace_rv_i_ecause_ip : UInt<5>, trace_rv_i_interrupt_ip : UInt<2>, trace_rv_i_tval_ip : UInt<32>, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_size : UInt<3>, iccm_wr_data : UInt<78>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ic_rw_addr : UInt<31>, ic_tag_valid : UInt<2>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rlast : UInt<1>, ifu_axi_awvalid : UInt<1>, flip ifu_axi_awready : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, flip ifu_axi_wready : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, flip ifu_axi_bvalid : UInt<1>, ifu_axi_bready : UInt<1>, flip ifu_axi_bresp : UInt<2>, flip ifu_axi_bid : UInt<3>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_axi_rlast : UInt<1>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, flip sb_axi_bid : UInt<1>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rid : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip sb_axi_rlast : UInt<1>, flip dma_axi_awvalid : UInt<1>, dma_axi_awready : UInt<1>, flip dma_axi_awid : UInt<1>, flip dma_axi_awaddr : UInt<32>, flip dma_axi_awsize : UInt<3>, flip dma_axi_awprot : UInt<3>, flip dma_axi_awlen : UInt<8>, flip dma_axi_awburst : UInt<2>, flip dma_axi_wvalid : UInt<1>, dma_axi_wready : UInt<1>, flip dma_axi_wdata : UInt<64>, flip dma_axi_wstrb : UInt<8>, flip dma_axi_wlast : UInt<1>, dma_axi_bvalid : UInt<1>, flip dma_axi_bready : UInt<1>, dma_axi_bresp : UInt<2>, dma_axi_bid : UInt<1>, flip dma_axi_arvalid : UInt<1>, dma_axi_arready : UInt<1>, flip dma_axi_arid : UInt<1>, flip dma_axi_araddr : UInt<32>, flip dma_axi_arsize : UInt<3>, flip dma_axi_arprot : UInt<3>, flip dma_axi_arlen : UInt<8>, flip dma_axi_arburst : UInt<2>, dma_axi_rvalid : UInt<1>, flip dma_axi_rready : UInt<1>, dma_axi_rid : UInt<1>, dma_axi_rdata : UInt<64>, dma_axi_rresp : UInt<2>, dma_axi_rlast : UInt<1>, haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>, lsu_haddr : UInt<32>, lsu_hburst : UInt<3>, lsu_hmastlock : UInt<1>, lsu_hprot : UInt<4>, lsu_hsize : UInt<3>, lsu_htrans : UInt<2>, lsu_hwrite : UInt<1>, lsu_hwdata : UInt<64>, flip lsu_hrdata : UInt<64>, flip lsu_hready : UInt<1>, flip lsu_hresp : UInt<1>, sb_haddr : UInt<32>, sb_hburst : UInt<3>, sb_hmastlock : UInt<1>, sb_hprot : UInt<4>, sb_hsize : UInt<3>, sb_htrans : UInt<2>, sb_hwrite : UInt<1>, sb_hwdata : UInt<64>, flip sb_hrdata : UInt<64>, flip sb_hready : UInt<1>, flip sb_hresp : UInt<1>, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} - inst ifu of el2_ifu @[el2_swerv.scala 323:19] + inst ifu of el2_ifu @[el2_swerv.scala 321:19] ifu.clock <= clock ifu.reset <= reset - inst dec of el2_dec @[el2_swerv.scala 324:19] + inst dec of el2_dec @[el2_swerv.scala 322:19] dec.clock <= clock dec.reset <= reset - inst dbg of el2_dbg @[el2_swerv.scala 325:19] + inst dbg of el2_dbg @[el2_swerv.scala 323:19] dbg.clock <= clock dbg.reset <= reset - inst exu of el2_exu @[el2_swerv.scala 326:19] + inst exu of el2_exu @[el2_swerv.scala 324:19] exu.clock <= clock exu.reset <= reset - inst lsu of el2_lsu @[el2_swerv.scala 327:19] + inst lsu of el2_lsu @[el2_swerv.scala 325:19] lsu.clock <= clock lsu.reset <= reset - inst pic_ctl_inst of el2_pic_ctrl @[el2_swerv.scala 328:28] - pic_ctl_inst.clock <= clock - pic_ctl_inst.reset <= reset - inst dma_ctrl of el2_dma_ctrl @[el2_swerv.scala 329:24] + inst pic_ctrl_inst of el2_pic_ctrl @[el2_swerv.scala 326:29] + pic_ctrl_inst.clock <= clock + pic_ctrl_inst.reset <= reset + inst dma_ctrl of el2_dma_ctrl @[el2_swerv.scala 327:24] dma_ctrl.clock <= clock dma_ctrl.reset <= reset - node _T = asUInt(reset) @[el2_swerv.scala 334:35] - node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[el2_swerv.scala 334:69] - node _T_2 = or(_T_1, io.scan_mode) @[el2_swerv.scala 334:72] - node _T_3 = and(_T, _T_2) @[el2_swerv.scala 334:38] - node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_swerv.scala 334:21] - node _T_5 = asAsyncReset(_T_4) @[el2_swerv.scala 334:102] - io.core_rst_l <= _T_5 @[el2_swerv.scala 334:17] - node _T_6 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[el2_swerv.scala 335:23] - node _T_7 = or(_T_6, dec.io.dec_tlu_flush_lower_r) @[el2_swerv.scala 335:50] - node active_state = or(_T_7, dec.io.dec_tlu_misc_clk_override) @[el2_swerv.scala 335:82] + node _T = asUInt(reset) @[el2_swerv.scala 332:33] + node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[el2_swerv.scala 332:67] + node _T_2 = or(_T_1, io.scan_mode) @[el2_swerv.scala 332:70] + node _T_3 = and(_T, _T_2) @[el2_swerv.scala 332:36] + node _T_4 = asAsyncReset(_T_3) @[el2_swerv.scala 332:99] + io.core_rst_l <= _T_4 @[el2_swerv.scala 332:17] + node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[el2_swerv.scala 333:23] + node _T_6 = or(_T_5, dec.io.dec_tlu_flush_lower_r) @[el2_swerv.scala 333:50] + node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[el2_swerv.scala 333:82] inst rvclkhdr of rvclkhdr_845 @[el2_lib.scala 483:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -108836,623 +109040,623 @@ circuit el2_swerv : rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_1.io.en <= active_state @[el2_lib.scala 485:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[el2_swerv.scala 338:56] - node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[el2_swerv.scala 339:56] - node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[el2_swerv.scala 340:28] - ifu.reset <= io.core_rst_l @[el2_swerv.scala 346:13] - ifu.io.scan_mode <= io.scan_mode @[el2_swerv.scala 347:20] - ifu.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 348:19] - ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[el2_swerv.scala 349:21] - ifu.io.iccm_rd_data_ecc <= io.iccm_rd_data_ecc @[el2_swerv.scala 350:27] - ifu.io.dec_i0_decode_d <= dec.io.dec_i0_decode_d @[el2_swerv.scala 351:26] - ifu.io.exu_flush_final <= dec.io.exu_flush_final @[el2_swerv.scala 352:26] - ifu.io.dec_tlu_i0_commit_cmt <= dec.io.dec_tlu_i0_commit_cmt @[el2_swerv.scala 353:32] - ifu.io.dec_tlu_flush_err_wb <= dec.io.dec_tlu_flush_err_r @[el2_swerv.scala 354:31] - ifu.io.dec_tlu_flush_noredir_wb <= dec.io.dec_tlu_flush_noredir_r @[el2_swerv.scala 355:35] - ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[el2_swerv.scala 356:31] - ifu.io.dec_tlu_mrac_ff <= dec.io.dec_tlu_mrac_ff @[el2_swerv.scala 357:26] - ifu.io.dec_tlu_fence_i_wb <= dec.io.dec_tlu_fence_i_r @[el2_swerv.scala 358:29] - ifu.io.dec_tlu_flush_leak_one_wb <= dec.io.dec_tlu_flush_leak_one_r @[el2_swerv.scala 359:36] - ifu.io.dec_tlu_bpred_disable <= dec.io.dec_tlu_bpred_disable @[el2_swerv.scala 360:32] - ifu.io.dec_tlu_core_ecc_disable <= dec.io.dec_tlu_core_ecc_disable @[el2_swerv.scala 361:35] - ifu.io.dec_tlu_force_halt <= dec.io.dec_tlu_force_halt @[el2_swerv.scala 362:29] - node _T_8 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_arready) @[el2_swerv.scala 363:32] - ifu.io.ifu_axi_arready <= _T_8 @[el2_swerv.scala 363:26] - node _T_9 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_rvalid) @[el2_swerv.scala 364:31] - ifu.io.ifu_axi_rvalid <= _T_9 @[el2_swerv.scala 364:25] - node _T_10 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_rid) @[el2_swerv.scala 365:28] - ifu.io.ifu_axi_rid <= _T_10 @[el2_swerv.scala 365:22] - node _T_11 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_rdata) @[el2_swerv.scala 366:30] - ifu.io.ifu_axi_rdata <= _T_11 @[el2_swerv.scala 366:24] - node _T_12 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_rresp) @[el2_swerv.scala 367:30] - ifu.io.ifu_axi_rresp <= _T_12 @[el2_swerv.scala 367:24] - ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_swerv.scala 368:25] - ifu.io.dma_iccm_req <= dma_ctrl.io.dma_iccm_req @[el2_swerv.scala 369:23] - ifu.io.dma_mem_addr <= dma_ctrl.io.dma_mem_addr @[el2_swerv.scala 370:23] - ifu.io.dma_mem_sz <= dma_ctrl.io.dma_mem_sz @[el2_swerv.scala 371:21] - ifu.io.dma_mem_write <= dma_ctrl.io.dma_mem_write @[el2_swerv.scala 372:24] - ifu.io.dma_mem_wdata <= dma_ctrl.io.dma_mem_wdata @[el2_swerv.scala 373:24] - ifu.io.dma_mem_tag <= dma_ctrl.io.dma_mem_tag @[el2_swerv.scala 374:22] - ifu.io.dma_iccm_stall_any <= dma_ctrl.io.dma_iccm_stall_any @[el2_swerv.scala 375:29] - ifu.io.ic_rd_data <= io.ic_rd_data @[el2_swerv.scala 376:21] - ifu.io.ic_debug_rd_data <= io.ic_debug_rd_data @[el2_swerv.scala 377:27] - ifu.io.ictag_debug_rd_data <= io.ictag_debug_rd_data @[el2_swerv.scala 378:30] - ifu.io.ic_eccerr <= io.ic_eccerr @[el2_swerv.scala 379:20] - ifu.io.ic_parerr <= io.ic_parerr @[el2_swerv.scala 380:20] - ifu.io.ic_rd_hit <= io.ic_rd_hit @[el2_swerv.scala 381:20] - ifu.io.ic_tag_perr <= io.ic_tag_perr @[el2_swerv.scala 382:22] - ifu.io.iccm_rd_data <= io.iccm_rd_data @[el2_swerv.scala 383:23] - ifu.io.exu_mp_pkt.bits.way <= exu.io.exu_mp_pkt.bits.way @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.pja <= exu.io.exu_mp_pkt.bits.pja @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.pret <= exu.io.exu_mp_pkt.bits.pret @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.pcall <= exu.io.exu_mp_pkt.bits.pcall @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.prett <= exu.io.exu_mp_pkt.bits.prett @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.br_start_error <= exu.io.exu_mp_pkt.bits.br_start_error @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.br_error <= exu.io.exu_mp_pkt.bits.br_error @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.toffset <= exu.io.exu_mp_pkt.bits.toffset @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.hist <= exu.io.exu_mp_pkt.bits.hist @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.pc4 <= exu.io.exu_mp_pkt.bits.pc4 @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.boffset <= exu.io.exu_mp_pkt.bits.boffset @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.ataken <= exu.io.exu_mp_pkt.bits.ataken @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.bits.misp <= exu.io.exu_mp_pkt.bits.misp @[el2_swerv.scala 384:21] - ifu.io.exu_mp_pkt.valid <= exu.io.exu_mp_pkt.valid @[el2_swerv.scala 384:21] - ifu.io.exu_mp_eghr <= exu.io.exu_mp_eghr @[el2_swerv.scala 385:22] - ifu.io.exu_mp_fghr <= exu.io.exu_mp_fghr @[el2_swerv.scala 386:22] - ifu.io.exu_mp_index <= exu.io.exu_mp_index @[el2_swerv.scala 387:23] - ifu.io.exu_mp_btag <= exu.io.exu_mp_btag @[el2_swerv.scala 388:22] - ifu.io.dec_tlu_br0_r_pkt.bits.middle <= dec.io.dec_tlu_br0_r_pkt.bits.middle @[el2_swerv.scala 389:28] - ifu.io.dec_tlu_br0_r_pkt.bits.way <= dec.io.dec_tlu_br0_r_pkt.bits.way @[el2_swerv.scala 389:28] - ifu.io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_swerv.scala 389:28] - ifu.io.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_swerv.scala 389:28] - ifu.io.dec_tlu_br0_r_pkt.bits.hist <= dec.io.dec_tlu_br0_r_pkt.bits.hist @[el2_swerv.scala 389:28] - ifu.io.dec_tlu_br0_r_pkt.valid <= dec.io.dec_tlu_br0_r_pkt.valid @[el2_swerv.scala 389:28] - ifu.io.exu_i0_br_fghr_r <= exu.io.exu_i0_br_fghr_r @[el2_swerv.scala 390:27] - ifu.io.exu_i0_br_index_r <= exu.io.exu_i0_br_index_r @[el2_swerv.scala 391:28] - ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_tlu_flush_lower_r @[el2_swerv.scala 392:33] - ifu.io.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_swerv.scala 393:30] - ifu.io.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_swerv.scala 393:30] - ifu.io.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_swerv.scala 393:30] - ifu.io.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_swerv.scala 393:30] - dec.reset <= io.core_rst_l @[el2_swerv.scala 396:13] - dec.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 397:19] - dec.io.active_clk <= rvclkhdr_1.io.l1clk @[el2_swerv.scala 398:21] - dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[el2_swerv.scala 399:32] - dec.io.rst_vec <= io.rst_vec @[el2_swerv.scala 400:18] - dec.io.nmi_int <= io.nmi_int @[el2_swerv.scala 401:18] - dec.io.nmi_vec <= io.nmi_vec @[el2_swerv.scala 402:18] - dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[el2_swerv.scala 403:25] - dec.io.i_cpu_run_req <= io.i_cpu_run_req @[el2_swerv.scala 404:24] - dec.io.core_id <= io.core_id @[el2_swerv.scala 405:18] - dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[el2_swerv.scala 406:29] - dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[el2_swerv.scala 407:28] - dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_swerv.scala 408:28] - dec.io.exu_pmu_i0_br_misp <= exu.io.exu_pmu_i0_br_misp @[el2_swerv.scala 409:29] - dec.io.exu_pmu_i0_br_ataken <= exu.io.exu_pmu_i0_br_ataken @[el2_swerv.scala 410:31] - dec.io.exu_pmu_i0_pc4 <= exu.io.exu_pmu_i0_pc4 @[el2_swerv.scala 411:25] - dec.io.lsu_nonblock_load_valid_m <= lsu.io.lsu_nonblock_load_valid_m @[el2_swerv.scala 412:36] - dec.io.lsu_nonblock_load_tag_m <= lsu.io.lsu_nonblock_load_tag_m @[el2_swerv.scala 413:34] - dec.io.lsu_nonblock_load_inv_r <= lsu.io.lsu_nonblock_load_inv_r @[el2_swerv.scala 414:34] - dec.io.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_nonblock_load_inv_tag_r @[el2_swerv.scala 415:38] - dec.io.lsu_nonblock_load_data_valid <= lsu.io.lsu_nonblock_load_data_valid @[el2_swerv.scala 416:39] - dec.io.lsu_nonblock_load_data_error <= lsu.io.lsu_nonblock_load_data_error @[el2_swerv.scala 417:39] - dec.io.lsu_nonblock_load_data_tag <= lsu.io.lsu_nonblock_load_data_tag @[el2_swerv.scala 418:37] - dec.io.lsu_nonblock_load_data <= lsu.io.lsu_nonblock_load_data @[el2_swerv.scala 419:33] - dec.io.lsu_pmu_bus_trxn <= lsu.io.lsu_pmu_bus_trxn @[el2_swerv.scala 420:27] - dec.io.lsu_pmu_bus_misaligned <= lsu.io.lsu_pmu_bus_misaligned @[el2_swerv.scala 421:33] - dec.io.lsu_pmu_bus_error <= lsu.io.lsu_pmu_bus_error @[el2_swerv.scala 422:28] - dec.io.lsu_pmu_bus_busy <= lsu.io.lsu_pmu_bus_busy @[el2_swerv.scala 423:27] - dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[el2_swerv.scala 424:31] - dec.io.lsu_pmu_load_external_m <= lsu.io.lsu_pmu_load_external_m @[el2_swerv.scala 425:34] - dec.io.lsu_pmu_store_external_m <= lsu.io.lsu_pmu_store_external_m @[el2_swerv.scala 426:35] - dec.io.dma_pmu_dccm_read <= dma_ctrl.io.dma_pmu_dccm_read @[el2_swerv.scala 427:28] - dec.io.dma_pmu_dccm_write <= dma_ctrl.io.dma_pmu_dccm_write @[el2_swerv.scala 428:29] - dec.io.dma_pmu_any_read <= dma_ctrl.io.dma_pmu_any_read @[el2_swerv.scala 429:27] - dec.io.dma_pmu_any_write <= dma_ctrl.io.dma_pmu_any_write @[el2_swerv.scala 430:28] - dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[el2_swerv.scala 431:23] - dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[el2_swerv.scala 432:24] - dec.io.ifu_pmu_instr_aligned <= ifu.io.ifu_pmu_instr_aligned @[el2_swerv.scala 433:32] - dec.io.ifu_pmu_fetch_stall <= ifu.io.ifu_pmu_fetch_stall @[el2_swerv.scala 434:30] - dec.io.ifu_pmu_ic_miss <= ifu.io.ifu_pmu_ic_miss @[el2_swerv.scala 435:26] - dec.io.ifu_pmu_ic_hit <= ifu.io.ifu_pmu_ic_hit @[el2_swerv.scala 436:25] - dec.io.ifu_pmu_bus_error <= ifu.io.ifu_pmu_bus_error @[el2_swerv.scala 437:28] - dec.io.ifu_pmu_bus_busy <= ifu.io.ifu_pmu_bus_busy @[el2_swerv.scala 438:27] - dec.io.ifu_pmu_bus_trxn <= ifu.io.ifu_pmu_bus_trxn @[el2_swerv.scala 439:27] - dec.io.ifu_ic_error_start <= ifu.io.ifu_ic_error_start @[el2_swerv.scala 440:29] - dec.io.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_iccm_rd_ecc_single_err @[el2_swerv.scala 441:37] - dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[el2_swerv.scala 442:30] - dec.io.dbg_cmd_valid <= dbg.io.dbg_cmd_valid @[el2_swerv.scala 443:24] - dec.io.dbg_cmd_write <= dbg.io.dbg_cmd_write @[el2_swerv.scala 444:24] - dec.io.dbg_cmd_type <= dbg.io.dbg_cmd_type @[el2_swerv.scala 445:23] - dec.io.dbg_cmd_addr <= dbg.io.dbg_cmd_addr @[el2_swerv.scala 446:23] - dec.io.dbg_cmd_wrdata <= dbg.io.dbg_cmd_wrdata @[el2_swerv.scala 447:25] - dec.io.ifu_i0_icaf <= ifu.io.ifu_i0_icaf @[el2_swerv.scala 448:22] - dec.io.ifu_i0_icaf_type <= ifu.io.ifu_i0_icaf_type @[el2_swerv.scala 449:27] - dec.io.ifu_i0_icaf_f1 <= ifu.io.ifu_i0_icaf_f1 @[el2_swerv.scala 450:25] - dec.io.ifu_i0_dbecc <= ifu.io.ifu_i0_dbecc @[el2_swerv.scala 451:23] - dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[el2_swerv.scala 452:23] - dec.io.i0_brp.bits.ret <= ifu.io.i0_brp.bits.ret @[el2_swerv.scala 453:17] - dec.io.i0_brp.bits.way <= ifu.io.i0_brp.bits.way @[el2_swerv.scala 453:17] - dec.io.i0_brp.bits.prett <= ifu.io.i0_brp.bits.prett @[el2_swerv.scala 453:17] - dec.io.i0_brp.bits.bank <= ifu.io.i0_brp.bits.bank @[el2_swerv.scala 453:17] - dec.io.i0_brp.bits.br_start_error <= ifu.io.i0_brp.bits.br_start_error @[el2_swerv.scala 453:17] - dec.io.i0_brp.bits.br_error <= ifu.io.i0_brp.bits.br_error @[el2_swerv.scala 453:17] - dec.io.i0_brp.bits.hist <= ifu.io.i0_brp.bits.hist @[el2_swerv.scala 453:17] - dec.io.i0_brp.bits.toffset <= ifu.io.i0_brp.bits.toffset @[el2_swerv.scala 453:17] - dec.io.i0_brp.valid <= ifu.io.i0_brp.valid @[el2_swerv.scala 453:17] - dec.io.ifu_i0_bp_index <= ifu.io.ifu_i0_bp_index @[el2_swerv.scala 454:26] - dec.io.ifu_i0_bp_fghr <= ifu.io.ifu_i0_bp_fghr @[el2_swerv.scala 455:25] - dec.io.ifu_i0_bp_btag <= ifu.io.ifu_i0_bp_btag @[el2_swerv.scala 456:25] - dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[el2_swerv.scala 457:26] - dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[el2_swerv.scala 457:26] - dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[el2_swerv.scala 457:26] - dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[el2_swerv.scala 457:26] - dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[el2_swerv.scala 457:26] - dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[el2_swerv.scala 457:26] - dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[el2_swerv.scala 458:36] - dec.io.lsu_imprecise_error_load_any <= lsu.io.lsu_imprecise_error_load_any @[el2_swerv.scala 459:39] - dec.io.lsu_imprecise_error_store_any <= lsu.io.lsu_imprecise_error_store_any @[el2_swerv.scala 460:40] - dec.io.lsu_imprecise_error_addr_any <= lsu.io.lsu_imprecise_error_addr_any @[el2_swerv.scala 461:39] - dec.io.exu_div_result <= exu.io.exu_div_result @[el2_swerv.scala 462:25] - dec.io.exu_div_wren <= exu.io.exu_div_wren @[el2_swerv.scala 463:23] - dec.io.exu_csr_rs1_x <= exu.io.exu_csr_rs1_x @[el2_swerv.scala 464:24] - dec.io.lsu_result_m <= lsu.io.lsu_result_m @[el2_swerv.scala 465:23] - dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[el2_swerv.scala 466:28] - dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[el2_swerv.scala 467:29] - dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[el2_swerv.scala 468:30] - dec.io.dma_dccm_stall_any <= dma_ctrl.io.dma_dccm_stall_any @[el2_swerv.scala 469:29] - dec.io.dma_iccm_stall_any <= dma_ctrl.io.dma_iccm_stall_any @[el2_swerv.scala 470:29] - dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[el2_swerv.scala 471:28] - dec.io.exu_flush_final <= exu.io.exu_flush_final @[el2_swerv.scala 472:26] - dec.io.exu_npc_r <= exu.io.exu_npc_r @[el2_swerv.scala 473:20] - dec.io.exu_i0_result_x <= exu.io.exu_i0_result_x @[el2_swerv.scala 474:26] - dec.io.ifu_i0_valid <= ifu.io.ifu_i0_valid @[el2_swerv.scala 475:23] - dec.io.ifu_i0_instr <= ifu.io.ifu_i0_instr @[el2_swerv.scala 476:23] - dec.io.ifu_i0_pc <= ifu.io.ifu_i0_pc @[el2_swerv.scala 477:20] - dec.io.ifu_i0_pc4 <= ifu.io.ifu_i0_pc4 @[el2_swerv.scala 478:21] - dec.io.exu_i0_pc_x <= exu.io.exu_i0_pc_x @[el2_swerv.scala 479:22] - dec.io.mexintpend <= pic_ctl_inst.io.mexintpend @[el2_swerv.scala 480:21] - dec.io.soft_int <= io.soft_int @[el2_swerv.scala 481:19] - dec.io.pic_claimid <= pic_ctl_inst.io.claimid @[el2_swerv.scala 482:22] - dec.io.pic_pl <= pic_ctl_inst.io.pl @[el2_swerv.scala 483:17] - dec.io.mhwakeup <= pic_ctl_inst.io.mhwakeup @[el2_swerv.scala 484:19] - dec.io.ifu_ic_debug_rd_data <= ifu.io.ifu_ic_debug_rd_data @[el2_swerv.scala 485:31] - dec.io.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_ic_debug_rd_data_valid @[el2_swerv.scala 486:37] - dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[el2_swerv.scala 487:23] - dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[el2_swerv.scala 488:25] - dec.io.ifu_miss_state_idle <= ifu.io.ifu_miss_state_idle @[el2_swerv.scala 489:30] - dec.io.exu_i0_br_hist_r <= exu.io.exu_i0_br_hist_r @[el2_swerv.scala 490:27] - dec.io.exu_i0_br_error_r <= exu.io.exu_i0_br_error_r @[el2_swerv.scala 491:28] - dec.io.exu_i0_br_start_error_r <= exu.io.exu_i0_br_start_error_r @[el2_swerv.scala 492:34] - dec.io.exu_i0_br_valid_r <= exu.io.exu_i0_br_valid_r @[el2_swerv.scala 493:28] - dec.io.exu_i0_br_mp_r <= exu.io.exu_i0_br_mp_r @[el2_swerv.scala 494:25] - dec.io.exu_i0_br_middle_r <= exu.io.exu_i0_br_middle_r @[el2_swerv.scala 495:29] - dec.io.exu_i0_br_way_r <= exu.io.exu_i0_br_way_r @[el2_swerv.scala 496:26] - dec.io.ifu_i0_cinst <= ifu.io.ifu_i0_cinst @[el2_swerv.scala 497:23] - dec.io.timer_int <= io.timer_int @[el2_swerv.scala 498:20] - dec.io.scan_mode <= io.scan_mode @[el2_swerv.scala 499:20] - exu.reset <= io.core_rst_l @[el2_swerv.scala 502:13] - exu.io.scan_mode <= io.scan_mode @[el2_swerv.scala 503:20] - exu.io.dec_data_en <= dec.io.dec_data_en @[el2_swerv.scala 504:22] - exu.io.dec_ctl_en <= dec.io.dec_ctl_en @[el2_swerv.scala 505:21] - exu.io.dbg_cmd_wrdata <= dbg.io.dbg_cmd_wrdata @[el2_swerv.scala 506:25] - exu.io.i0_ap.csr_imm <= dec.io.i0_ap.csr_imm @[el2_swerv.scala 507:16] - exu.io.i0_ap.csr_write <= dec.io.i0_ap.csr_write @[el2_swerv.scala 507:16] - exu.io.i0_ap.predict_nt <= dec.io.i0_ap.predict_nt @[el2_swerv.scala 507:16] - exu.io.i0_ap.predict_t <= dec.io.i0_ap.predict_t @[el2_swerv.scala 507:16] - exu.io.i0_ap.jal <= dec.io.i0_ap.jal @[el2_swerv.scala 507:16] - exu.io.i0_ap.unsign <= dec.io.i0_ap.unsign @[el2_swerv.scala 507:16] - exu.io.i0_ap.slt <= dec.io.i0_ap.slt @[el2_swerv.scala 507:16] - exu.io.i0_ap.sub <= dec.io.i0_ap.sub @[el2_swerv.scala 507:16] - exu.io.i0_ap.add <= dec.io.i0_ap.add @[el2_swerv.scala 507:16] - exu.io.i0_ap.bge <= dec.io.i0_ap.bge @[el2_swerv.scala 507:16] - exu.io.i0_ap.blt <= dec.io.i0_ap.blt @[el2_swerv.scala 507:16] - exu.io.i0_ap.bne <= dec.io.i0_ap.bne @[el2_swerv.scala 507:16] - exu.io.i0_ap.beq <= dec.io.i0_ap.beq @[el2_swerv.scala 507:16] - exu.io.i0_ap.sra <= dec.io.i0_ap.sra @[el2_swerv.scala 507:16] - exu.io.i0_ap.srl <= dec.io.i0_ap.srl @[el2_swerv.scala 507:16] - exu.io.i0_ap.sll <= dec.io.i0_ap.sll @[el2_swerv.scala 507:16] - exu.io.i0_ap.lxor <= dec.io.i0_ap.lxor @[el2_swerv.scala 507:16] - exu.io.i0_ap.lor <= dec.io.i0_ap.lor @[el2_swerv.scala 507:16] - exu.io.i0_ap.land <= dec.io.i0_ap.land @[el2_swerv.scala 507:16] - exu.io.dec_debug_wdata_rs1_d <= dec.io.dec_debug_wdata_rs1_d @[el2_swerv.scala 508:32] - exu.io.dec_i0_predict_p_d.bits.way <= dec.io.dec_i0_predict_p_d.bits.way @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.pja <= dec.io.dec_i0_predict_p_d.bits.pja @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.pret <= dec.io.dec_i0_predict_p_d.bits.pret @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_i0_predict_p_d.bits.pcall @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.prett <= dec.io.dec_i0_predict_p_d.bits.prett @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_i0_predict_p_d.bits.br_start_error @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_i0_predict_p_d.bits.br_error @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_i0_predict_p_d.bits.toffset @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.hist <= dec.io.dec_i0_predict_p_d.bits.hist @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_i0_predict_p_d.bits.pc4 @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_i0_predict_p_d.bits.boffset @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_i0_predict_p_d.bits.ataken @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.bits.misp <= dec.io.dec_i0_predict_p_d.bits.misp @[el2_swerv.scala 509:29] - exu.io.dec_i0_predict_p_d.valid <= dec.io.dec_i0_predict_p_d.valid @[el2_swerv.scala 509:29] - exu.io.i0_predict_fghr_d <= dec.io.i0_predict_fghr_d @[el2_swerv.scala 510:28] - exu.io.i0_predict_index_d <= dec.io.i0_predict_index_d @[el2_swerv.scala 511:29] - exu.io.i0_predict_btag_d <= dec.io.i0_predict_btag_d @[el2_swerv.scala 512:28] - exu.io.dec_i0_rs1_en_d <= dec.io.dec_i0_rs1_en_d @[el2_swerv.scala 513:26] - exu.io.dec_i0_rs2_en_d <= dec.io.dec_i0_rs2_en_d @[el2_swerv.scala 514:26] - exu.io.gpr_i0_rs1_d <= dec.io.gpr_i0_rs1_d @[el2_swerv.scala 515:23] - exu.io.gpr_i0_rs2_d <= dec.io.gpr_i0_rs2_d @[el2_swerv.scala 516:23] - exu.io.dec_i0_immed_d <= dec.io.dec_i0_immed_d @[el2_swerv.scala 517:25] - exu.io.dec_i0_rs1_bypass_data_d <= dec.io.dec_i0_rs1_bypass_data_d @[el2_swerv.scala 518:35] - exu.io.dec_i0_rs2_bypass_data_d <= dec.io.dec_i0_rs2_bypass_data_d @[el2_swerv.scala 519:35] - exu.io.dec_i0_br_immed_d <= dec.io.dec_i0_br_immed_d @[el2_swerv.scala 520:28] - exu.io.dec_i0_alu_decode_d <= dec.io.dec_i0_alu_decode_d @[el2_swerv.scala 521:30] - exu.io.dec_i0_select_pc_d <= dec.io.dec_i0_select_pc_d @[el2_swerv.scala 522:29] - exu.io.dec_i0_pc_d <= dec.io.dec_i0_pc_d @[el2_swerv.scala 523:22] - exu.io.dec_i0_rs1_bypass_en_d <= dec.io.dec_i0_rs1_bypass_en_d @[el2_swerv.scala 524:33] - exu.io.dec_i0_rs2_bypass_en_d <= dec.io.dec_i0_rs2_bypass_en_d @[el2_swerv.scala 525:33] - exu.io.dec_csr_ren_d <= dec.io.dec_csr_ren_d @[el2_swerv.scala 526:24] - exu.io.mul_p.bits.bfp <= dec.io.mul_p.bits.bfp @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.crc32c_w <= dec.io.mul_p.bits.crc32c_w @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.crc32c_h <= dec.io.mul_p.bits.crc32c_h @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.crc32c_b <= dec.io.mul_p.bits.crc32c_b @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.crc32_w <= dec.io.mul_p.bits.crc32_w @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.crc32_h <= dec.io.mul_p.bits.crc32_h @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.crc32_b <= dec.io.mul_p.bits.crc32_b @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.unshfl <= dec.io.mul_p.bits.unshfl @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.shfl <= dec.io.mul_p.bits.shfl @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.grev <= dec.io.mul_p.bits.grev @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.clmulr <= dec.io.mul_p.bits.clmulr @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.clmulh <= dec.io.mul_p.bits.clmulh @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.clmul <= dec.io.mul_p.bits.clmul @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.bdep <= dec.io.mul_p.bits.bdep @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.bext <= dec.io.mul_p.bits.bext @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.low <= dec.io.mul_p.bits.low @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.rs2_sign <= dec.io.mul_p.bits.rs2_sign @[el2_swerv.scala 527:16] - exu.io.mul_p.bits.rs1_sign <= dec.io.mul_p.bits.rs1_sign @[el2_swerv.scala 527:16] - exu.io.mul_p.valid <= dec.io.mul_p.valid @[el2_swerv.scala 527:16] - exu.io.div_p.bits.rem <= dec.io.div_p.bits.rem @[el2_swerv.scala 528:16] - exu.io.div_p.bits.unsign <= dec.io.div_p.bits.unsign @[el2_swerv.scala 528:16] - exu.io.div_p.valid <= dec.io.div_p.valid @[el2_swerv.scala 528:16] - exu.io.dec_div_cancel <= dec.io.dec_div_cancel @[el2_swerv.scala 529:25] - exu.io.pred_correct_npc_x <= dec.io.pred_correct_npc_x @[el2_swerv.scala 530:29] - exu.io.dec_tlu_flush_lower_r <= dec.io.dec_tlu_flush_lower_r @[el2_swerv.scala 531:32] - exu.io.dec_tlu_flush_path_r <= dec.io.dec_tlu_flush_path_r @[el2_swerv.scala 532:31] - exu.io.dec_extint_stall <= dec.io.dec_extint_stall @[el2_swerv.scala 533:27] - exu.io.dec_tlu_meihap <= dec.io.dec_tlu_meihap @[el2_swerv.scala 534:25] - lsu.reset <= io.core_rst_l @[el2_swerv.scala 538:13] - lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[el2_swerv.scala 539:23] - lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_tlu_flush_lower_r @[el2_swerv.scala 540:32] - lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[el2_swerv.scala 541:35] - lsu.io.dec_tlu_force_halt <= dec.io.dec_tlu_force_halt @[el2_swerv.scala 542:29] - lsu.io.dec_tlu_external_ldfwd_disable <= dec.io.dec_tlu_external_ldfwd_disable @[el2_swerv.scala 543:41] - lsu.io.dec_tlu_wb_coalescing_disable <= dec.io.dec_tlu_wb_coalescing_disable @[el2_swerv.scala 544:40] - lsu.io.dec_tlu_sideeffect_posted_disable <= dec.io.dec_tlu_sideeffect_posted_disable @[el2_swerv.scala 545:44] - lsu.io.dec_tlu_core_ecc_disable <= dec.io.dec_tlu_core_ecc_disable @[el2_swerv.scala 546:35] - lsu.io.exu_lsu_rs1_d <= exu.io.exu_lsu_rs1_d @[el2_swerv.scala 547:24] - lsu.io.exu_lsu_rs2_d <= exu.io.exu_lsu_rs2_d @[el2_swerv.scala 548:24] - lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[el2_swerv.scala 549:27] - lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[el2_swerv.scala 550:16] - lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[el2_swerv.scala 550:16] - lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[el2_swerv.scala 550:16] - lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[el2_swerv.scala 551:30] - lsu.io.dec_tlu_mrac_ff <= dec.io.dec_tlu_mrac_ff @[el2_swerv.scala 552:26] - lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[0].match_ <= dec.io.trigger_pkt_any[0].match_ @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[1].match_ <= dec.io.trigger_pkt_any[1].match_ @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[2].match_ <= dec.io.trigger_pkt_any[2].match_ @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[3].match_ <= dec.io.trigger_pkt_any[3].match_ @[el2_swerv.scala 553:26] - lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[el2_swerv.scala 553:26] - lsu.io.dccm_rd_data_lo <= io.dccm_rd_data_lo @[el2_swerv.scala 554:26] - lsu.io.dccm_rd_data_hi <= io.dccm_rd_data_hi @[el2_swerv.scala 555:26] - node _T_13 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_awready) @[el2_swerv.scala 556:32] - lsu.io.lsu_axi_awready <= _T_13 @[el2_swerv.scala 556:26] - node _T_14 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_wready) @[el2_swerv.scala 557:32] - lsu.io.lsu_axi_wready <= _T_14 @[el2_swerv.scala 557:25] - node _T_15 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_bvalid) @[el2_swerv.scala 558:32] - lsu.io.lsu_axi_bvalid <= _T_15 @[el2_swerv.scala 558:25] - node _T_16 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_bresp) @[el2_swerv.scala 559:31] - lsu.io.lsu_axi_bresp <= _T_16 @[el2_swerv.scala 559:24] - node _T_17 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_bid) @[el2_swerv.scala 560:29] - lsu.io.lsu_axi_bid <= _T_17 @[el2_swerv.scala 560:22] - node _T_18 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_arready) @[el2_swerv.scala 561:33] - lsu.io.lsu_axi_arready <= _T_18 @[el2_swerv.scala 561:26] - node _T_19 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rvalid) @[el2_swerv.scala 562:32] - lsu.io.lsu_axi_rvalid <= _T_19 @[el2_swerv.scala 562:25] - node _T_20 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rid) @[el2_swerv.scala 563:29] - lsu.io.lsu_axi_rid <= _T_20 @[el2_swerv.scala 563:22] - node _T_21 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rdata) @[el2_swerv.scala 564:31] - lsu.io.lsu_axi_rdata <= _T_21 @[el2_swerv.scala 564:24] - node _T_22 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rresp) @[el2_swerv.scala 565:31] - lsu.io.lsu_axi_rresp <= _T_22 @[el2_swerv.scala 565:24] - node _T_23 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rlast) @[el2_swerv.scala 566:31] - lsu.io.lsu_axi_rlast <= _T_23 @[el2_swerv.scala 566:24] - lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[el2_swerv.scala 567:25] - lsu.io.dma_dccm_req <= dma_ctrl.io.dma_dccm_req @[el2_swerv.scala 568:23] - lsu.io.dma_mem_tag <= dma_ctrl.io.dma_mem_tag @[el2_swerv.scala 569:22] - lsu.io.dma_mem_addr <= dma_ctrl.io.dma_mem_addr @[el2_swerv.scala 570:23] - lsu.io.dma_mem_sz <= dma_ctrl.io.dma_mem_sz @[el2_swerv.scala 571:21] - lsu.io.dma_mem_write <= dma_ctrl.io.dma_mem_write @[el2_swerv.scala 572:24] - lsu.io.dma_mem_wdata <= dma_ctrl.io.dma_mem_wdata @[el2_swerv.scala 573:24] - lsu.io.scan_mode <= io.scan_mode @[el2_swerv.scala 574:20] - lsu.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 575:19] - dbg.reset <= io.core_rst_l @[el2_swerv.scala 578:13] - node _T_24 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[el2_swerv.scala 579:32] - dbg.io.core_dbg_rddata <= _T_24 @[el2_swerv.scala 579:26] - node _T_25 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[el2_swerv.scala 580:60] - dbg.io.core_dbg_cmd_done <= _T_25 @[el2_swerv.scala 580:28] - node _T_26 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[el2_swerv.scala 581:60] - dbg.io.core_dbg_cmd_fail <= _T_26 @[el2_swerv.scala 581:28] - dbg.io.dma_dbg_ready <= dma_ctrl.io.dma_dbg_ready @[el2_swerv.scala 582:24] - dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[el2_swerv.scala 583:29] - dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[el2_swerv.scala 584:29] - dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[el2_swerv.scala 585:34] - dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[el2_swerv.scala 586:29] - dbg.io.dmi_reg_en <= io.dmi_reg_en @[el2_swerv.scala 587:21] - dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[el2_swerv.scala 588:23] - dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[el2_swerv.scala 589:24] - dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[el2_swerv.scala 590:24] - dbg.io.sb_axi_awready <= io.sb_axi_awready @[el2_swerv.scala 591:25] - dbg.io.sb_axi_wready <= io.sb_axi_wready @[el2_swerv.scala 592:24] - dbg.io.sb_axi_bvalid <= io.sb_axi_bvalid @[el2_swerv.scala 593:24] - dbg.io.sb_axi_bresp <= io.sb_axi_bresp @[el2_swerv.scala 594:23] - dbg.io.sb_axi_arready <= io.sb_axi_arready @[el2_swerv.scala 595:25] - dbg.io.sb_axi_rvalid <= io.sb_axi_rvalid @[el2_swerv.scala 596:24] - dbg.io.sb_axi_rdata <= io.sb_axi_rdata @[el2_swerv.scala 597:23] - dbg.io.sb_axi_rresp <= io.sb_axi_rresp @[el2_swerv.scala 598:23] - dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[el2_swerv.scala 599:25] - dbg.io.dbg_rst_l <= io.dbg_rst_l @[el2_swerv.scala 600:20] - dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[el2_swerv.scala 601:23] - dbg.io.scan_mode <= io.scan_mode @[el2_swerv.scala 602:20] - dma_ctrl.reset <= io.core_rst_l @[el2_swerv.scala 606:18] - dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 607:24] - dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[el2_swerv.scala 608:30] - dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[el2_swerv.scala 609:28] - dma_ctrl.io.scan_mode <= io.scan_mode @[el2_swerv.scala 610:25] - dma_ctrl.io.dbg_cmd_addr <= dbg.io.dbg_cmd_addr @[el2_swerv.scala 611:28] - dma_ctrl.io.dbg_cmd_wrdata <= dbg.io.dbg_cmd_wrdata @[el2_swerv.scala 612:30] - dma_ctrl.io.dbg_cmd_valid <= dbg.io.dbg_cmd_valid @[el2_swerv.scala 613:29] - dma_ctrl.io.dbg_cmd_write <= dbg.io.dbg_cmd_write @[el2_swerv.scala 614:29] - dma_ctrl.io.dbg_cmd_type <= dbg.io.dbg_cmd_type @[el2_swerv.scala 615:28] - dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[el2_swerv.scala 616:28] - dma_ctrl.io.dbg_dma_bubble <= dbg.io.dbg_dma_bubble @[el2_swerv.scala 617:30] - dma_ctrl.io.dccm_dma_rvalid <= lsu.io.dccm_dma_rvalid @[el2_swerv.scala 618:31] - dma_ctrl.io.dccm_dma_ecc_error <= lsu.io.dccm_dma_ecc_error @[el2_swerv.scala 619:34] - dma_ctrl.io.dccm_dma_rtag <= lsu.io.dccm_dma_rtag @[el2_swerv.scala 620:29] - dma_ctrl.io.dccm_dma_rdata <= lsu.io.dccm_dma_rdata @[el2_swerv.scala 621:30] - dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[el2_swerv.scala 622:31] - dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[el2_swerv.scala 623:29] - dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[el2_swerv.scala 624:30] - dma_ctrl.io.dccm_ready <= lsu.io.dccm_ready @[el2_swerv.scala 625:26] - dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[el2_swerv.scala 626:26] - dma_ctrl.io.dec_tlu_dma_qos_prty <= dec.io.dec_tlu_dma_qos_prty @[el2_swerv.scala 627:36] - dma_ctrl.io.dma_axi_awvalid <= io.dma_axi_awvalid @[el2_swerv.scala 628:31] - dma_ctrl.io.dma_axi_awid <= io.dma_axi_awid @[el2_swerv.scala 629:28] - dma_ctrl.io.dma_axi_awaddr <= io.dma_axi_awaddr @[el2_swerv.scala 630:30] - dma_ctrl.io.dma_axi_awsize <= io.dma_axi_awsize @[el2_swerv.scala 631:30] - dma_ctrl.io.dma_axi_wvalid <= io.dma_axi_wvalid @[el2_swerv.scala 632:30] - dma_ctrl.io.dma_axi_wdata <= io.dma_axi_wdata @[el2_swerv.scala 633:29] - dma_ctrl.io.dma_axi_wstrb <= io.dma_axi_wstrb @[el2_swerv.scala 634:29] - dma_ctrl.io.dma_axi_bready <= io.dma_axi_bready @[el2_swerv.scala 635:30] - dma_ctrl.io.dma_axi_arvalid <= io.dma_axi_arvalid @[el2_swerv.scala 636:31] - dma_ctrl.io.dma_axi_arid <= io.dma_axi_arid @[el2_swerv.scala 637:28] - dma_ctrl.io.dma_axi_araddr <= io.dma_axi_araddr @[el2_swerv.scala 638:30] - dma_ctrl.io.dma_axi_arsize <= io.dma_axi_arsize @[el2_swerv.scala 639:30] - dma_ctrl.io.dma_axi_rready <= io.dma_axi_rready @[el2_swerv.scala 640:30] - dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[el2_swerv.scala 641:34] - pic_ctl_inst.io.scan_mode <= io.scan_mode @[el2_swerv.scala 645:29] - pic_ctl_inst.reset <= io.core_rst_l @[el2_swerv.scala 646:22] - pic_ctl_inst.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 647:28] - pic_ctl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[el2_swerv.scala 648:30] - pic_ctl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[el2_swerv.scala 649:32] - pic_ctl_inst.io.extintsrc_req <= io.extintsrc_req @[el2_swerv.scala 650:33] - pic_ctl_inst.io.picm_rdaddr <= lsu.io.picm_rdaddr @[el2_swerv.scala 651:31] - pic_ctl_inst.io.picm_wraddr <= lsu.io.picm_wraddr @[el2_swerv.scala 652:31] - pic_ctl_inst.io.picm_wr_data <= lsu.io.picm_wr_data @[el2_swerv.scala 653:32] - pic_ctl_inst.io.picm_wren <= lsu.io.picm_wren @[el2_swerv.scala 654:29] - pic_ctl_inst.io.picm_rden <= lsu.io.picm_rden @[el2_swerv.scala 655:29] - pic_ctl_inst.io.picm_mken <= lsu.io.picm_mken @[el2_swerv.scala 656:29] - pic_ctl_inst.io.meicurpl <= dec.io.dec_tlu_meicurpl @[el2_swerv.scala 657:28] - pic_ctl_inst.io.meipt <= dec.io.dec_tlu_meipt @[el2_swerv.scala 658:25] - lsu.io.picm_rd_data <= pic_ctl_inst.io.picm_rd_data @[el2_swerv.scala 659:23] - io.trace_rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[el2_swerv.scala 665:25] - io.trace_rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[el2_swerv.scala 666:28] - io.trace_rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[el2_swerv.scala 667:26] - io.trace_rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[el2_swerv.scala 668:30] - io.trace_rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[el2_swerv.scala 669:27] - io.trace_rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[el2_swerv.scala 670:30] - io.trace_rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[el2_swerv.scala 671:25] - io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[el2_swerv.scala 675:24] - io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[el2_swerv.scala 676:23] - io.dec_tlu_core_ecc_disable <= dec.io.dec_tlu_core_ecc_disable @[el2_swerv.scala 677:31] - io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[el2_swerv.scala 678:21] - io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[el2_swerv.scala 679:24] - io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[el2_swerv.scala 680:20] - io.o_debug_mode_status <= dec.io.o_debug_mode_status @[el2_swerv.scala 681:26] - io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[el2_swerv.scala 682:25] - io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[el2_swerv.scala 683:24] - io.debug_brkpt_status <= dec.io.debug_brkpt_status @[el2_swerv.scala 684:25] - io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[el2_swerv.scala 685:23] - io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[el2_swerv.scala 686:23] - io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[el2_swerv.scala 687:23] - io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[el2_swerv.scala 688:23] - io.dccm_wren <= lsu.io.dccm_wren @[el2_swerv.scala 690:16] - io.dccm_rden <= lsu.io.dccm_rden @[el2_swerv.scala 691:16] - io.dccm_wr_addr_lo <= lsu.io.dccm_wr_addr_lo @[el2_swerv.scala 692:22] - io.dccm_wr_addr_hi <= lsu.io.dccm_wr_addr_hi @[el2_swerv.scala 693:22] - io.dccm_rd_addr_lo <= lsu.io.dccm_rd_addr_lo @[el2_swerv.scala 694:22] - io.dccm_rd_addr_hi <= lsu.io.dccm_rd_addr_hi @[el2_swerv.scala 695:22] - io.dccm_wr_data_lo <= lsu.io.dccm_wr_data_lo @[el2_swerv.scala 696:22] - io.dccm_wr_data_hi <= lsu.io.dccm_wr_data_hi @[el2_swerv.scala 697:22] - io.iccm_rw_addr <= ifu.io.iccm_rw_addr @[el2_swerv.scala 699:19] - io.iccm_wren <= ifu.io.iccm_wren @[el2_swerv.scala 700:16] - io.iccm_rden <= ifu.io.iccm_rden @[el2_swerv.scala 701:16] - io.iccm_wr_size <= ifu.io.iccm_wr_size @[el2_swerv.scala 702:19] - io.iccm_wr_data <= ifu.io.iccm_wr_data @[el2_swerv.scala 703:19] - io.iccm_buf_correct_ecc <= ifu.io.iccm_buf_correct_ecc @[el2_swerv.scala 704:27] - io.iccm_correction_state <= ifu.io.iccm_correction_state @[el2_swerv.scala 705:28] - io.ic_rw_addr <= ifu.io.ic_rw_addr @[el2_swerv.scala 706:17] - io.ic_tag_valid <= ifu.io.ic_tag_valid @[el2_swerv.scala 707:19] - io.ic_wr_en <= ifu.io.ic_wr_en @[el2_swerv.scala 708:15] - io.ic_rd_en <= ifu.io.ic_rd_en @[el2_swerv.scala 709:15] - io.ic_wr_data[0] <= ifu.io.ic_wr_data[0] @[el2_swerv.scala 710:17] - io.ic_wr_data[1] <= ifu.io.ic_wr_data[1] @[el2_swerv.scala 710:17] - io.ic_debug_wr_data <= ifu.io.ic_debug_wr_data @[el2_swerv.scala 711:23] - io.ic_premux_data <= ifu.io.ic_premux_data @[el2_swerv.scala 712:21] - io.ic_sel_premux_data <= ifu.io.ic_sel_premux_data @[el2_swerv.scala 713:25] - io.ic_debug_addr <= ifu.io.ic_debug_addr @[el2_swerv.scala 714:20] - io.ic_debug_rd_en <= ifu.io.ic_debug_rd_en @[el2_swerv.scala 715:21] - io.ic_debug_wr_en <= ifu.io.ic_debug_wr_en @[el2_swerv.scala 716:21] - io.ic_debug_tag_array <= ifu.io.ic_debug_tag_array @[el2_swerv.scala 717:25] - io.ic_debug_way <= ifu.io.ic_debug_way @[el2_swerv.scala 718:19] - io.lsu_axi_awvalid <= lsu.io.lsu_axi_awvalid @[el2_swerv.scala 721:22] - io.lsu_axi_awid <= lsu.io.lsu_axi_awid @[el2_swerv.scala 722:19] - io.lsu_axi_awaddr <= lsu.io.lsu_axi_awaddr @[el2_swerv.scala 723:21] - io.lsu_axi_awregion <= lsu.io.lsu_axi_awregion @[el2_swerv.scala 724:23] - io.lsu_axi_awlen <= lsu.io.lsu_axi_awlen @[el2_swerv.scala 725:20] - io.lsu_axi_awsize <= lsu.io.lsu_axi_awsize @[el2_swerv.scala 726:21] - io.lsu_axi_awburst <= lsu.io.lsu_axi_awburst @[el2_swerv.scala 727:22] - io.lsu_axi_awlock <= lsu.io.lsu_axi_awlock @[el2_swerv.scala 728:21] - io.lsu_axi_awcache <= lsu.io.lsu_axi_awcache @[el2_swerv.scala 729:22] - io.lsu_axi_awprot <= lsu.io.lsu_axi_awprot @[el2_swerv.scala 730:21] - io.lsu_axi_awqos <= lsu.io.lsu_axi_awqos @[el2_swerv.scala 731:20] - io.lsu_axi_wvalid <= lsu.io.lsu_axi_wvalid @[el2_swerv.scala 732:21] - io.lsu_axi_wdata <= lsu.io.lsu_axi_wdata @[el2_swerv.scala 733:20] - io.lsu_axi_wstrb <= lsu.io.lsu_axi_wstrb @[el2_swerv.scala 734:20] - io.lsu_axi_wlast <= lsu.io.lsu_axi_wlast @[el2_swerv.scala 735:20] - io.lsu_axi_bready <= lsu.io.lsu_axi_bready @[el2_swerv.scala 736:21] - io.lsu_axi_arvalid <= lsu.io.lsu_axi_arvalid @[el2_swerv.scala 737:22] - io.lsu_axi_arid <= lsu.io.lsu_axi_arid @[el2_swerv.scala 738:19] - io.lsu_axi_araddr <= lsu.io.lsu_axi_araddr @[el2_swerv.scala 739:21] - io.lsu_axi_arregion <= lsu.io.lsu_axi_arregion @[el2_swerv.scala 740:23] - io.lsu_axi_arlen <= lsu.io.lsu_axi_arlen @[el2_swerv.scala 741:20] - io.lsu_axi_arsize <= lsu.io.lsu_axi_arsize @[el2_swerv.scala 742:21] - io.lsu_axi_arburst <= lsu.io.lsu_axi_arburst @[el2_swerv.scala 743:22] - io.lsu_axi_arlock <= lsu.io.lsu_axi_arlock @[el2_swerv.scala 744:21] - io.lsu_axi_arcache <= lsu.io.lsu_axi_arcache @[el2_swerv.scala 745:22] - io.lsu_axi_arprot <= lsu.io.lsu_axi_arprot @[el2_swerv.scala 746:21] - io.lsu_axi_arqos <= lsu.io.lsu_axi_arqos @[el2_swerv.scala 747:20] - io.lsu_axi_rready <= lsu.io.lsu_axi_rready @[el2_swerv.scala 748:21] - io.ifu_axi_awvalid <= ifu.io.ifu_axi_awvalid @[el2_swerv.scala 751:22] - io.ifu_axi_awid <= ifu.io.ifu_axi_awid @[el2_swerv.scala 752:19] - io.ifu_axi_awaddr <= ifu.io.ifu_axi_awaddr @[el2_swerv.scala 753:21] - io.ifu_axi_awregion <= ifu.io.ifu_axi_awregion @[el2_swerv.scala 754:23] - io.ifu_axi_awlen <= ifu.io.ifu_axi_awlen @[el2_swerv.scala 755:20] - io.ifu_axi_awsize <= ifu.io.ifu_axi_awsize @[el2_swerv.scala 756:21] - io.ifu_axi_awburst <= ifu.io.ifu_axi_awburst @[el2_swerv.scala 757:22] - io.ifu_axi_awlock <= ifu.io.ifu_axi_awlock @[el2_swerv.scala 758:21] - io.ifu_axi_awcache <= ifu.io.ifu_axi_awcache @[el2_swerv.scala 759:22] - io.ifu_axi_awprot <= ifu.io.ifu_axi_awprot @[el2_swerv.scala 760:21] - io.ifu_axi_awqos <= ifu.io.ifu_axi_awqos @[el2_swerv.scala 761:20] - io.ifu_axi_wvalid <= ifu.io.ifu_axi_wvalid @[el2_swerv.scala 762:21] - io.ifu_axi_wdata <= ifu.io.ifu_axi_wdata @[el2_swerv.scala 763:20] - io.ifu_axi_wstrb <= ifu.io.ifu_axi_wstrb @[el2_swerv.scala 764:20] - io.ifu_axi_wlast <= ifu.io.ifu_axi_wlast @[el2_swerv.scala 765:20] - io.ifu_axi_bready <= ifu.io.ifu_axi_bready @[el2_swerv.scala 766:21] - io.ifu_axi_arvalid <= ifu.io.ifu_axi_arvalid @[el2_swerv.scala 767:22] - io.ifu_axi_arid <= ifu.io.ifu_axi_arid @[el2_swerv.scala 768:19] - io.ifu_axi_araddr <= ifu.io.ifu_axi_araddr @[el2_swerv.scala 769:21] - io.ifu_axi_arregion <= ifu.io.ifu_axi_arregion @[el2_swerv.scala 770:23] - io.ifu_axi_arlen <= ifu.io.ifu_axi_arlen @[el2_swerv.scala 771:20] - io.ifu_axi_arsize <= ifu.io.ifu_axi_arsize @[el2_swerv.scala 772:21] - io.ifu_axi_arburst <= ifu.io.ifu_axi_arburst @[el2_swerv.scala 773:22] - io.ifu_axi_arlock <= ifu.io.ifu_axi_arlock @[el2_swerv.scala 774:21] - io.ifu_axi_arcache <= ifu.io.ifu_axi_arcache @[el2_swerv.scala 775:22] - io.ifu_axi_arprot <= ifu.io.ifu_axi_arprot @[el2_swerv.scala 776:21] - io.ifu_axi_arqos <= ifu.io.ifu_axi_arqos @[el2_swerv.scala 777:20] - io.ifu_axi_rready <= ifu.io.ifu_axi_rready @[el2_swerv.scala 778:21] - io.sb_axi_awvalid <= dbg.io.sb_axi_awvalid @[el2_swerv.scala 782:21] - io.sb_axi_awid <= dbg.io.sb_axi_awid @[el2_swerv.scala 783:18] - io.sb_axi_awaddr <= dbg.io.sb_axi_awaddr @[el2_swerv.scala 784:20] - io.sb_axi_awregion <= dbg.io.sb_axi_awregion @[el2_swerv.scala 785:22] - io.sb_axi_awlen <= dbg.io.sb_axi_awlen @[el2_swerv.scala 786:19] - io.sb_axi_awsize <= dbg.io.sb_axi_awsize @[el2_swerv.scala 787:20] - io.sb_axi_awburst <= dbg.io.sb_axi_awburst @[el2_swerv.scala 788:21] - io.sb_axi_awlock <= dbg.io.sb_axi_awlock @[el2_swerv.scala 789:20] - io.sb_axi_awcache <= dbg.io.sb_axi_awcache @[el2_swerv.scala 790:21] - io.sb_axi_awprot <= dbg.io.sb_axi_awprot @[el2_swerv.scala 791:20] - io.sb_axi_awqos <= dbg.io.sb_axi_awqos @[el2_swerv.scala 792:19] - io.sb_axi_wvalid <= dbg.io.sb_axi_wvalid @[el2_swerv.scala 793:20] - io.sb_axi_wdata <= dbg.io.sb_axi_wdata @[el2_swerv.scala 794:19] - io.sb_axi_wstrb <= dbg.io.sb_axi_wstrb @[el2_swerv.scala 795:19] - io.sb_axi_wlast <= dbg.io.sb_axi_wlast @[el2_swerv.scala 796:19] - io.sb_axi_bready <= dbg.io.sb_axi_bready @[el2_swerv.scala 797:20] - io.sb_axi_arvalid <= dbg.io.sb_axi_arvalid @[el2_swerv.scala 798:21] - io.sb_axi_arid <= dbg.io.sb_axi_arid @[el2_swerv.scala 799:18] - io.sb_axi_araddr <= dbg.io.sb_axi_araddr @[el2_swerv.scala 800:20] - io.sb_axi_arregion <= dbg.io.sb_axi_arregion @[el2_swerv.scala 801:22] - io.sb_axi_arlen <= dbg.io.sb_axi_arlen @[el2_swerv.scala 802:19] - io.sb_axi_arsize <= dbg.io.sb_axi_arsize @[el2_swerv.scala 803:20] - io.sb_axi_arburst <= dbg.io.sb_axi_arburst @[el2_swerv.scala 804:21] - io.sb_axi_arlock <= dbg.io.sb_axi_arlock @[el2_swerv.scala 805:20] - io.sb_axi_arcache <= dbg.io.sb_axi_arcache @[el2_swerv.scala 806:21] - io.sb_axi_arprot <= dbg.io.sb_axi_arprot @[el2_swerv.scala 807:20] - io.sb_axi_arqos <= dbg.io.sb_axi_arqos @[el2_swerv.scala 808:19] - io.sb_axi_rready <= dbg.io.sb_axi_rready @[el2_swerv.scala 809:20] - io.dma_axi_awready <= dma_ctrl.io.dma_axi_awready @[el2_swerv.scala 812:22] - io.dma_axi_wready <= dma_ctrl.io.dma_axi_wready @[el2_swerv.scala 813:21] - io.dma_axi_bvalid <= dma_ctrl.io.dma_axi_bvalid @[el2_swerv.scala 814:21] - io.dma_axi_bresp <= dma_ctrl.io.dma_axi_bresp @[el2_swerv.scala 815:20] - io.dma_axi_bid <= dma_ctrl.io.dma_axi_bid @[el2_swerv.scala 816:18] - io.dma_axi_arready <= dma_ctrl.io.dma_axi_arready @[el2_swerv.scala 817:22] - io.dma_axi_rvalid <= dma_ctrl.io.dma_axi_rvalid @[el2_swerv.scala 818:21] - io.dma_axi_rid <= dma_ctrl.io.dma_axi_rid @[el2_swerv.scala 819:18] - io.dma_axi_rdata <= dma_ctrl.io.dma_axi_rdata @[el2_swerv.scala 820:20] - io.dma_axi_rresp <= dma_ctrl.io.dma_axi_rresp @[el2_swerv.scala 821:20] - io.dma_axi_rlast <= dma_ctrl.io.dma_axi_rlast @[el2_swerv.scala 822:20] - io.hburst <= UInt<1>("h00") @[el2_swerv.scala 825:13] - io.hmastlock <= UInt<1>("h00") @[el2_swerv.scala 826:16] - io.hprot <= UInt<1>("h00") @[el2_swerv.scala 827:12] - io.hsize <= UInt<1>("h00") @[el2_swerv.scala 828:12] - io.htrans <= UInt<1>("h00") @[el2_swerv.scala 829:13] - io.hwrite <= UInt<1>("h00") @[el2_swerv.scala 830:13] - io.haddr <= UInt<1>("h00") @[el2_swerv.scala 831:12] - io.lsu_haddr <= UInt<1>("h00") @[el2_swerv.scala 833:16] - io.lsu_hburst <= UInt<1>("h00") @[el2_swerv.scala 834:17] - io.lsu_hmastlock <= UInt<1>("h00") @[el2_swerv.scala 835:20] - io.lsu_hprot <= UInt<1>("h00") @[el2_swerv.scala 836:16] - io.lsu_hsize <= UInt<1>("h00") @[el2_swerv.scala 837:16] - io.lsu_htrans <= UInt<1>("h00") @[el2_swerv.scala 838:17] - io.lsu_hwrite <= UInt<1>("h00") @[el2_swerv.scala 839:17] - io.lsu_hwdata <= UInt<1>("h00") @[el2_swerv.scala 840:17] - io.sb_haddr <= UInt<1>("h00") @[el2_swerv.scala 843:15] - io.sb_hburst <= UInt<1>("h00") @[el2_swerv.scala 844:16] - io.sb_hmastlock <= UInt<1>("h00") @[el2_swerv.scala 845:19] - io.sb_hprot <= UInt<1>("h00") @[el2_swerv.scala 846:15] - io.sb_hsize <= UInt<1>("h00") @[el2_swerv.scala 847:15] - io.sb_htrans <= UInt<1>("h00") @[el2_swerv.scala 848:16] - io.sb_hwrite <= UInt<1>("h00") @[el2_swerv.scala 849:16] - io.sb_hwdata <= UInt<1>("h00") @[el2_swerv.scala 850:16] - io.dma_hrdata <= UInt<1>("h00") @[el2_swerv.scala 852:17] - io.dma_hreadyout <= UInt<1>("h00") @[el2_swerv.scala 853:20] - io.dma_hresp <= UInt<1>("h00") @[el2_swerv.scala 854:16] - io.ifu_axi_wready <= UInt<1>("h00") @[el2_swerv.scala 856:21] - io.dma_hresp <= UInt<1>("h00") @[el2_swerv.scala 858:16] - io.dmi_reg_rdata <= UInt<1>("h00") @[el2_swerv.scala 860:20] + node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[el2_swerv.scala 336:56] + node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[el2_swerv.scala 337:56] + node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[el2_swerv.scala 338:28] + ifu.reset <= io.core_rst_l @[el2_swerv.scala 344:13] + ifu.io.scan_mode <= io.scan_mode @[el2_swerv.scala 345:20] + ifu.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 346:19] + ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[el2_swerv.scala 347:21] + ifu.io.iccm_rd_data_ecc <= io.iccm_rd_data_ecc @[el2_swerv.scala 348:27] + ifu.io.dec_i0_decode_d <= dec.io.dec_i0_decode_d @[el2_swerv.scala 349:26] + ifu.io.exu_flush_final <= dec.io.exu_flush_final @[el2_swerv.scala 350:26] + ifu.io.dec_tlu_i0_commit_cmt <= dec.io.dec_tlu_i0_commit_cmt @[el2_swerv.scala 351:32] + ifu.io.dec_tlu_flush_err_wb <= dec.io.dec_tlu_flush_err_r @[el2_swerv.scala 352:31] + ifu.io.dec_tlu_flush_noredir_wb <= dec.io.dec_tlu_flush_noredir_r @[el2_swerv.scala 353:35] + ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[el2_swerv.scala 354:31] + ifu.io.dec_tlu_mrac_ff <= dec.io.dec_tlu_mrac_ff @[el2_swerv.scala 355:26] + ifu.io.dec_tlu_fence_i_wb <= dec.io.dec_tlu_fence_i_r @[el2_swerv.scala 356:29] + ifu.io.dec_tlu_flush_leak_one_wb <= dec.io.dec_tlu_flush_leak_one_r @[el2_swerv.scala 357:36] + ifu.io.dec_tlu_bpred_disable <= dec.io.dec_tlu_bpred_disable @[el2_swerv.scala 358:32] + ifu.io.dec_tlu_core_ecc_disable <= dec.io.dec_tlu_core_ecc_disable @[el2_swerv.scala 359:35] + ifu.io.dec_tlu_force_halt <= dec.io.dec_tlu_force_halt @[el2_swerv.scala 360:29] + node _T_7 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_arready) @[el2_swerv.scala 361:32] + ifu.io.ifu_axi_arready <= _T_7 @[el2_swerv.scala 361:26] + node _T_8 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_rvalid) @[el2_swerv.scala 362:31] + ifu.io.ifu_axi_rvalid <= _T_8 @[el2_swerv.scala 362:25] + node _T_9 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_rid) @[el2_swerv.scala 363:28] + ifu.io.ifu_axi_rid <= _T_9 @[el2_swerv.scala 363:22] + node _T_10 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_rdata) @[el2_swerv.scala 364:30] + ifu.io.ifu_axi_rdata <= _T_10 @[el2_swerv.scala 364:24] + node _T_11 = mux(UInt<1>("h00"), UInt<1>("h00"), io.ifu_axi_rresp) @[el2_swerv.scala 365:30] + ifu.io.ifu_axi_rresp <= _T_11 @[el2_swerv.scala 365:24] + ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_swerv.scala 366:25] + ifu.io.dma_iccm_req <= dma_ctrl.io.dma_iccm_req @[el2_swerv.scala 367:23] + ifu.io.dma_mem_addr <= dma_ctrl.io.dma_mem_addr @[el2_swerv.scala 368:23] + ifu.io.dma_mem_sz <= dma_ctrl.io.dma_mem_sz @[el2_swerv.scala 369:21] + ifu.io.dma_mem_write <= dma_ctrl.io.dma_mem_write @[el2_swerv.scala 370:24] + ifu.io.dma_mem_wdata <= dma_ctrl.io.dma_mem_wdata @[el2_swerv.scala 371:24] + ifu.io.dma_mem_tag <= dma_ctrl.io.dma_mem_tag @[el2_swerv.scala 372:22] + ifu.io.dma_iccm_stall_any <= dma_ctrl.io.dma_iccm_stall_any @[el2_swerv.scala 373:29] + ifu.io.ic_rd_data <= io.ic_rd_data @[el2_swerv.scala 374:21] + ifu.io.ic_debug_rd_data <= io.ic_debug_rd_data @[el2_swerv.scala 375:27] + ifu.io.ictag_debug_rd_data <= io.ictag_debug_rd_data @[el2_swerv.scala 376:30] + ifu.io.ic_eccerr <= io.ic_eccerr @[el2_swerv.scala 377:20] + ifu.io.ic_parerr <= io.ic_parerr @[el2_swerv.scala 378:20] + ifu.io.ic_rd_hit <= io.ic_rd_hit @[el2_swerv.scala 379:20] + ifu.io.ic_tag_perr <= io.ic_tag_perr @[el2_swerv.scala 380:22] + ifu.io.iccm_rd_data <= io.iccm_rd_data @[el2_swerv.scala 381:23] + ifu.io.exu_mp_pkt.bits.way <= exu.io.exu_mp_pkt.bits.way @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.pja <= exu.io.exu_mp_pkt.bits.pja @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.pret <= exu.io.exu_mp_pkt.bits.pret @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.pcall <= exu.io.exu_mp_pkt.bits.pcall @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.prett <= exu.io.exu_mp_pkt.bits.prett @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.br_start_error <= exu.io.exu_mp_pkt.bits.br_start_error @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.br_error <= exu.io.exu_mp_pkt.bits.br_error @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.toffset <= exu.io.exu_mp_pkt.bits.toffset @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.hist <= exu.io.exu_mp_pkt.bits.hist @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.pc4 <= exu.io.exu_mp_pkt.bits.pc4 @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.boffset <= exu.io.exu_mp_pkt.bits.boffset @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.ataken <= exu.io.exu_mp_pkt.bits.ataken @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.bits.misp <= exu.io.exu_mp_pkt.bits.misp @[el2_swerv.scala 382:21] + ifu.io.exu_mp_pkt.valid <= exu.io.exu_mp_pkt.valid @[el2_swerv.scala 382:21] + ifu.io.exu_mp_eghr <= exu.io.exu_mp_eghr @[el2_swerv.scala 383:22] + ifu.io.exu_mp_fghr <= exu.io.exu_mp_fghr @[el2_swerv.scala 384:22] + ifu.io.exu_mp_index <= exu.io.exu_mp_index @[el2_swerv.scala 385:23] + ifu.io.exu_mp_btag <= exu.io.exu_mp_btag @[el2_swerv.scala 386:22] + ifu.io.dec_tlu_br0_r_pkt.middle <= dec.io.dec_tlu_br0_r_pkt.middle @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.way <= dec.io.dec_tlu_br0_r_pkt.way @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.br_start_error <= dec.io.dec_tlu_br0_r_pkt.br_start_error @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.br_error <= dec.io.dec_tlu_br0_r_pkt.br_error @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.hist <= dec.io.dec_tlu_br0_r_pkt.hist @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.valid <= dec.io.dec_tlu_br0_r_pkt.valid @[el2_swerv.scala 387:28] + ifu.io.exu_i0_br_fghr_r <= exu.io.exu_i0_br_fghr_r @[el2_swerv.scala 388:27] + ifu.io.exu_i0_br_index_r <= exu.io.exu_i0_br_index_r @[el2_swerv.scala 389:28] + ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_tlu_flush_lower_r @[el2_swerv.scala 390:33] + ifu.io.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_swerv.scala 391:30] + ifu.io.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_swerv.scala 391:30] + ifu.io.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_swerv.scala 391:30] + ifu.io.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_swerv.scala 391:30] + dec.reset <= io.core_rst_l @[el2_swerv.scala 394:13] + dec.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 395:19] + dec.io.active_clk <= rvclkhdr_1.io.l1clk @[el2_swerv.scala 396:21] + dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[el2_swerv.scala 397:32] + dec.io.rst_vec <= io.rst_vec @[el2_swerv.scala 398:18] + dec.io.nmi_int <= io.nmi_int @[el2_swerv.scala 399:18] + dec.io.nmi_vec <= io.nmi_vec @[el2_swerv.scala 400:18] + dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[el2_swerv.scala 401:25] + dec.io.i_cpu_run_req <= io.i_cpu_run_req @[el2_swerv.scala 402:24] + dec.io.core_id <= io.core_id @[el2_swerv.scala 403:18] + dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[el2_swerv.scala 404:29] + dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[el2_swerv.scala 405:28] + dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[el2_swerv.scala 406:28] + dec.io.exu_pmu_i0_br_misp <= exu.io.exu_pmu_i0_br_misp @[el2_swerv.scala 407:29] + dec.io.exu_pmu_i0_br_ataken <= exu.io.exu_pmu_i0_br_ataken @[el2_swerv.scala 408:31] + dec.io.exu_pmu_i0_pc4 <= exu.io.exu_pmu_i0_pc4 @[el2_swerv.scala 409:25] + dec.io.lsu_nonblock_load_valid_m <= lsu.io.lsu_nonblock_load_valid_m @[el2_swerv.scala 410:36] + dec.io.lsu_nonblock_load_tag_m <= lsu.io.lsu_nonblock_load_tag_m @[el2_swerv.scala 411:34] + dec.io.lsu_nonblock_load_inv_r <= lsu.io.lsu_nonblock_load_inv_r @[el2_swerv.scala 412:34] + dec.io.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_nonblock_load_inv_tag_r @[el2_swerv.scala 413:38] + dec.io.lsu_nonblock_load_data_valid <= lsu.io.lsu_nonblock_load_data_valid @[el2_swerv.scala 414:39] + dec.io.lsu_nonblock_load_data_error <= lsu.io.lsu_nonblock_load_data_error @[el2_swerv.scala 415:39] + dec.io.lsu_nonblock_load_data_tag <= lsu.io.lsu_nonblock_load_data_tag @[el2_swerv.scala 416:37] + dec.io.lsu_nonblock_load_data <= lsu.io.lsu_nonblock_load_data @[el2_swerv.scala 417:33] + dec.io.lsu_pmu_bus_trxn <= lsu.io.lsu_pmu_bus_trxn @[el2_swerv.scala 418:27] + dec.io.lsu_pmu_bus_misaligned <= lsu.io.lsu_pmu_bus_misaligned @[el2_swerv.scala 419:33] + dec.io.lsu_pmu_bus_error <= lsu.io.lsu_pmu_bus_error @[el2_swerv.scala 420:28] + dec.io.lsu_pmu_bus_busy <= lsu.io.lsu_pmu_bus_busy @[el2_swerv.scala 421:27] + dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[el2_swerv.scala 422:31] + dec.io.lsu_pmu_load_external_m <= lsu.io.lsu_pmu_load_external_m @[el2_swerv.scala 423:34] + dec.io.lsu_pmu_store_external_m <= lsu.io.lsu_pmu_store_external_m @[el2_swerv.scala 424:35] + dec.io.dma_pmu_dccm_read <= dma_ctrl.io.dma_pmu_dccm_read @[el2_swerv.scala 425:28] + dec.io.dma_pmu_dccm_write <= dma_ctrl.io.dma_pmu_dccm_write @[el2_swerv.scala 426:29] + dec.io.dma_pmu_any_read <= dma_ctrl.io.dma_pmu_any_read @[el2_swerv.scala 427:27] + dec.io.dma_pmu_any_write <= dma_ctrl.io.dma_pmu_any_write @[el2_swerv.scala 428:28] + dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[el2_swerv.scala 429:23] + dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[el2_swerv.scala 430:24] + dec.io.ifu_pmu_instr_aligned <= ifu.io.ifu_pmu_instr_aligned @[el2_swerv.scala 431:32] + dec.io.ifu_pmu_fetch_stall <= ifu.io.ifu_pmu_fetch_stall @[el2_swerv.scala 432:30] + dec.io.ifu_pmu_ic_miss <= ifu.io.ifu_pmu_ic_miss @[el2_swerv.scala 433:26] + dec.io.ifu_pmu_ic_hit <= ifu.io.ifu_pmu_ic_hit @[el2_swerv.scala 434:25] + dec.io.ifu_pmu_bus_error <= ifu.io.ifu_pmu_bus_error @[el2_swerv.scala 435:28] + dec.io.ifu_pmu_bus_busy <= ifu.io.ifu_pmu_bus_busy @[el2_swerv.scala 436:27] + dec.io.ifu_pmu_bus_trxn <= ifu.io.ifu_pmu_bus_trxn @[el2_swerv.scala 437:27] + dec.io.ifu_ic_error_start <= ifu.io.ifu_ic_error_start @[el2_swerv.scala 438:29] + dec.io.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_iccm_rd_ecc_single_err @[el2_swerv.scala 439:37] + dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[el2_swerv.scala 440:30] + dec.io.dbg_cmd_valid <= dbg.io.dbg_cmd_valid @[el2_swerv.scala 441:24] + dec.io.dbg_cmd_write <= dbg.io.dbg_cmd_write @[el2_swerv.scala 442:24] + dec.io.dbg_cmd_type <= dbg.io.dbg_cmd_type @[el2_swerv.scala 443:23] + dec.io.dbg_cmd_addr <= dbg.io.dbg_cmd_addr @[el2_swerv.scala 444:23] + dec.io.dbg_cmd_wrdata <= dbg.io.dbg_cmd_wrdata @[el2_swerv.scala 445:25] + dec.io.ifu_i0_icaf <= ifu.io.ifu_i0_icaf @[el2_swerv.scala 446:22] + dec.io.ifu_i0_icaf_type <= ifu.io.ifu_i0_icaf_type @[el2_swerv.scala 447:27] + dec.io.ifu_i0_icaf_f1 <= ifu.io.ifu_i0_icaf_f1 @[el2_swerv.scala 448:25] + dec.io.ifu_i0_dbecc <= ifu.io.ifu_i0_dbecc @[el2_swerv.scala 449:23] + dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[el2_swerv.scala 450:23] + dec.io.i0_brp.ret <= ifu.io.i0_brp.ret @[el2_swerv.scala 451:17] + dec.io.i0_brp.way <= ifu.io.i0_brp.way @[el2_swerv.scala 451:17] + dec.io.i0_brp.prett <= ifu.io.i0_brp.prett @[el2_swerv.scala 451:17] + dec.io.i0_brp.bank <= ifu.io.i0_brp.bank @[el2_swerv.scala 451:17] + dec.io.i0_brp.br_start_error <= ifu.io.i0_brp.br_start_error @[el2_swerv.scala 451:17] + dec.io.i0_brp.br_error <= ifu.io.i0_brp.br_error @[el2_swerv.scala 451:17] + dec.io.i0_brp.hist <= ifu.io.i0_brp.hist @[el2_swerv.scala 451:17] + dec.io.i0_brp.toffset <= ifu.io.i0_brp.toffset @[el2_swerv.scala 451:17] + dec.io.i0_brp.valid <= ifu.io.i0_brp.valid @[el2_swerv.scala 451:17] + dec.io.ifu_i0_bp_index <= ifu.io.ifu_i0_bp_index @[el2_swerv.scala 452:26] + dec.io.ifu_i0_bp_fghr <= ifu.io.ifu_i0_bp_fghr @[el2_swerv.scala 453:25] + dec.io.ifu_i0_bp_btag <= ifu.io.ifu_i0_bp_btag @[el2_swerv.scala 454:25] + dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[el2_swerv.scala 455:26] + dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[el2_swerv.scala 455:26] + dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[el2_swerv.scala 455:26] + dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[el2_swerv.scala 455:26] + dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[el2_swerv.scala 455:26] + dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[el2_swerv.scala 455:26] + dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[el2_swerv.scala 456:36] + dec.io.lsu_imprecise_error_load_any <= lsu.io.lsu_imprecise_error_load_any @[el2_swerv.scala 457:39] + dec.io.lsu_imprecise_error_store_any <= lsu.io.lsu_imprecise_error_store_any @[el2_swerv.scala 458:40] + dec.io.lsu_imprecise_error_addr_any <= lsu.io.lsu_imprecise_error_addr_any @[el2_swerv.scala 459:39] + dec.io.exu_div_result <= exu.io.exu_div_result @[el2_swerv.scala 460:25] + dec.io.exu_div_wren <= exu.io.exu_div_wren @[el2_swerv.scala 461:23] + dec.io.exu_csr_rs1_x <= exu.io.exu_csr_rs1_x @[el2_swerv.scala 462:24] + dec.io.lsu_result_m <= lsu.io.lsu_result_m @[el2_swerv.scala 463:23] + dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[el2_swerv.scala 464:28] + dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[el2_swerv.scala 465:29] + dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[el2_swerv.scala 466:30] + dec.io.dma_dccm_stall_any <= dma_ctrl.io.dma_dccm_stall_any @[el2_swerv.scala 467:29] + dec.io.dma_iccm_stall_any <= dma_ctrl.io.dma_iccm_stall_any @[el2_swerv.scala 468:29] + dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[el2_swerv.scala 469:28] + dec.io.exu_flush_final <= exu.io.exu_flush_final @[el2_swerv.scala 470:26] + dec.io.exu_npc_r <= exu.io.exu_npc_r @[el2_swerv.scala 471:20] + dec.io.exu_i0_result_x <= exu.io.exu_i0_result_x @[el2_swerv.scala 472:26] + dec.io.ifu_i0_valid <= ifu.io.ifu_i0_valid @[el2_swerv.scala 473:23] + dec.io.ifu_i0_instr <= ifu.io.ifu_i0_instr @[el2_swerv.scala 474:23] + dec.io.ifu_i0_pc <= ifu.io.ifu_i0_pc @[el2_swerv.scala 475:20] + dec.io.ifu_i0_pc4 <= ifu.io.ifu_i0_pc4 @[el2_swerv.scala 476:21] + dec.io.exu_i0_pc_x <= exu.io.exu_i0_pc_x @[el2_swerv.scala 477:22] + dec.io.mexintpend <= pic_ctrl_inst.io.mexintpend @[el2_swerv.scala 478:21] + dec.io.soft_int <= io.soft_int @[el2_swerv.scala 479:19] + dec.io.pic_claimid <= pic_ctrl_inst.io.claimid @[el2_swerv.scala 480:22] + dec.io.pic_pl <= pic_ctrl_inst.io.pl @[el2_swerv.scala 481:17] + dec.io.mhwakeup <= pic_ctrl_inst.io.mhwakeup @[el2_swerv.scala 482:19] + dec.io.ifu_ic_debug_rd_data <= ifu.io.ifu_ic_debug_rd_data @[el2_swerv.scala 483:31] + dec.io.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_ic_debug_rd_data_valid @[el2_swerv.scala 484:37] + dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[el2_swerv.scala 485:23] + dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[el2_swerv.scala 486:25] + dec.io.ifu_miss_state_idle <= ifu.io.ifu_miss_state_idle @[el2_swerv.scala 487:30] + dec.io.exu_i0_br_hist_r <= exu.io.exu_i0_br_hist_r @[el2_swerv.scala 488:27] + dec.io.exu_i0_br_error_r <= exu.io.exu_i0_br_error_r @[el2_swerv.scala 489:28] + dec.io.exu_i0_br_start_error_r <= exu.io.exu_i0_br_start_error_r @[el2_swerv.scala 490:34] + dec.io.exu_i0_br_valid_r <= exu.io.exu_i0_br_valid_r @[el2_swerv.scala 491:28] + dec.io.exu_i0_br_mp_r <= exu.io.exu_i0_br_mp_r @[el2_swerv.scala 492:25] + dec.io.exu_i0_br_middle_r <= exu.io.exu_i0_br_middle_r @[el2_swerv.scala 493:29] + dec.io.exu_i0_br_way_r <= exu.io.exu_i0_br_way_r @[el2_swerv.scala 494:26] + dec.io.ifu_i0_cinst <= ifu.io.ifu_i0_cinst @[el2_swerv.scala 495:23] + dec.io.timer_int <= io.timer_int @[el2_swerv.scala 496:20] + dec.io.scan_mode <= io.scan_mode @[el2_swerv.scala 497:20] + exu.reset <= io.core_rst_l @[el2_swerv.scala 500:13] + exu.io.scan_mode <= io.scan_mode @[el2_swerv.scala 501:20] + exu.io.dec_data_en <= dec.io.dec_data_en @[el2_swerv.scala 502:22] + exu.io.dec_ctl_en <= dec.io.dec_ctl_en @[el2_swerv.scala 503:21] + exu.io.dbg_cmd_wrdata <= dbg.io.dbg_cmd_wrdata @[el2_swerv.scala 504:25] + exu.io.i0_ap.csr_imm <= dec.io.i0_ap.csr_imm @[el2_swerv.scala 505:16] + exu.io.i0_ap.csr_write <= dec.io.i0_ap.csr_write @[el2_swerv.scala 505:16] + exu.io.i0_ap.predict_nt <= dec.io.i0_ap.predict_nt @[el2_swerv.scala 505:16] + exu.io.i0_ap.predict_t <= dec.io.i0_ap.predict_t @[el2_swerv.scala 505:16] + exu.io.i0_ap.jal <= dec.io.i0_ap.jal @[el2_swerv.scala 505:16] + exu.io.i0_ap.unsign <= dec.io.i0_ap.unsign @[el2_swerv.scala 505:16] + exu.io.i0_ap.slt <= dec.io.i0_ap.slt @[el2_swerv.scala 505:16] + exu.io.i0_ap.sub <= dec.io.i0_ap.sub @[el2_swerv.scala 505:16] + exu.io.i0_ap.add <= dec.io.i0_ap.add @[el2_swerv.scala 505:16] + exu.io.i0_ap.bge <= dec.io.i0_ap.bge @[el2_swerv.scala 505:16] + exu.io.i0_ap.blt <= dec.io.i0_ap.blt @[el2_swerv.scala 505:16] + exu.io.i0_ap.bne <= dec.io.i0_ap.bne @[el2_swerv.scala 505:16] + exu.io.i0_ap.beq <= dec.io.i0_ap.beq @[el2_swerv.scala 505:16] + exu.io.i0_ap.sra <= dec.io.i0_ap.sra @[el2_swerv.scala 505:16] + exu.io.i0_ap.srl <= dec.io.i0_ap.srl @[el2_swerv.scala 505:16] + exu.io.i0_ap.sll <= dec.io.i0_ap.sll @[el2_swerv.scala 505:16] + exu.io.i0_ap.lxor <= dec.io.i0_ap.lxor @[el2_swerv.scala 505:16] + exu.io.i0_ap.lor <= dec.io.i0_ap.lor @[el2_swerv.scala 505:16] + exu.io.i0_ap.land <= dec.io.i0_ap.land @[el2_swerv.scala 505:16] + exu.io.dec_debug_wdata_rs1_d <= dec.io.dec_debug_wdata_rs1_d @[el2_swerv.scala 506:32] + exu.io.dec_i0_predict_p_d.bits.way <= dec.io.dec_i0_predict_p_d.bits.way @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.pja <= dec.io.dec_i0_predict_p_d.bits.pja @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.pret <= dec.io.dec_i0_predict_p_d.bits.pret @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_i0_predict_p_d.bits.pcall @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.prett <= dec.io.dec_i0_predict_p_d.bits.prett @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_i0_predict_p_d.bits.br_start_error @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_i0_predict_p_d.bits.br_error @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_i0_predict_p_d.bits.toffset @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.hist <= dec.io.dec_i0_predict_p_d.bits.hist @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_i0_predict_p_d.bits.pc4 @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_i0_predict_p_d.bits.boffset @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_i0_predict_p_d.bits.ataken @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.bits.misp <= dec.io.dec_i0_predict_p_d.bits.misp @[el2_swerv.scala 507:29] + exu.io.dec_i0_predict_p_d.valid <= dec.io.dec_i0_predict_p_d.valid @[el2_swerv.scala 507:29] + exu.io.i0_predict_fghr_d <= dec.io.i0_predict_fghr_d @[el2_swerv.scala 508:28] + exu.io.i0_predict_index_d <= dec.io.i0_predict_index_d @[el2_swerv.scala 509:29] + exu.io.i0_predict_btag_d <= dec.io.i0_predict_btag_d @[el2_swerv.scala 510:28] + exu.io.dec_i0_rs1_en_d <= dec.io.dec_i0_rs1_en_d @[el2_swerv.scala 511:26] + exu.io.dec_i0_rs2_en_d <= dec.io.dec_i0_rs2_en_d @[el2_swerv.scala 512:26] + exu.io.gpr_i0_rs1_d <= dec.io.gpr_i0_rs1_d @[el2_swerv.scala 513:23] + exu.io.gpr_i0_rs2_d <= dec.io.gpr_i0_rs2_d @[el2_swerv.scala 514:23] + exu.io.dec_i0_immed_d <= dec.io.dec_i0_immed_d @[el2_swerv.scala 515:25] + exu.io.dec_i0_rs1_bypass_data_d <= dec.io.dec_i0_rs1_bypass_data_d @[el2_swerv.scala 516:35] + exu.io.dec_i0_rs2_bypass_data_d <= dec.io.dec_i0_rs2_bypass_data_d @[el2_swerv.scala 517:35] + exu.io.dec_i0_br_immed_d <= dec.io.dec_i0_br_immed_d @[el2_swerv.scala 518:28] + exu.io.dec_i0_alu_decode_d <= dec.io.dec_i0_alu_decode_d @[el2_swerv.scala 519:30] + exu.io.dec_i0_select_pc_d <= dec.io.dec_i0_select_pc_d @[el2_swerv.scala 520:29] + exu.io.dec_i0_pc_d <= dec.io.dec_i0_pc_d @[el2_swerv.scala 521:22] + exu.io.dec_i0_rs1_bypass_en_d <= dec.io.dec_i0_rs1_bypass_en_d @[el2_swerv.scala 522:33] + exu.io.dec_i0_rs2_bypass_en_d <= dec.io.dec_i0_rs2_bypass_en_d @[el2_swerv.scala 523:33] + exu.io.dec_csr_ren_d <= dec.io.dec_csr_ren_d @[el2_swerv.scala 524:24] + exu.io.mul_p.bits.bfp <= dec.io.mul_p.bits.bfp @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.crc32c_w <= dec.io.mul_p.bits.crc32c_w @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.crc32c_h <= dec.io.mul_p.bits.crc32c_h @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.crc32c_b <= dec.io.mul_p.bits.crc32c_b @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.crc32_w <= dec.io.mul_p.bits.crc32_w @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.crc32_h <= dec.io.mul_p.bits.crc32_h @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.crc32_b <= dec.io.mul_p.bits.crc32_b @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.unshfl <= dec.io.mul_p.bits.unshfl @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.shfl <= dec.io.mul_p.bits.shfl @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.grev <= dec.io.mul_p.bits.grev @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.clmulr <= dec.io.mul_p.bits.clmulr @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.clmulh <= dec.io.mul_p.bits.clmulh @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.clmul <= dec.io.mul_p.bits.clmul @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.bdep <= dec.io.mul_p.bits.bdep @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.bext <= dec.io.mul_p.bits.bext @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.low <= dec.io.mul_p.bits.low @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.rs2_sign <= dec.io.mul_p.bits.rs2_sign @[el2_swerv.scala 525:16] + exu.io.mul_p.bits.rs1_sign <= dec.io.mul_p.bits.rs1_sign @[el2_swerv.scala 525:16] + exu.io.mul_p.valid <= dec.io.mul_p.valid @[el2_swerv.scala 525:16] + exu.io.div_p.bits.rem <= dec.io.div_p.bits.rem @[el2_swerv.scala 526:16] + exu.io.div_p.bits.unsign <= dec.io.div_p.bits.unsign @[el2_swerv.scala 526:16] + exu.io.div_p.valid <= dec.io.div_p.valid @[el2_swerv.scala 526:16] + exu.io.dec_div_cancel <= dec.io.dec_div_cancel @[el2_swerv.scala 527:25] + exu.io.pred_correct_npc_x <= dec.io.pred_correct_npc_x @[el2_swerv.scala 528:29] + exu.io.dec_tlu_flush_lower_r <= dec.io.dec_tlu_flush_lower_r @[el2_swerv.scala 529:32] + exu.io.dec_tlu_flush_path_r <= dec.io.dec_tlu_flush_path_r @[el2_swerv.scala 530:31] + exu.io.dec_extint_stall <= dec.io.dec_extint_stall @[el2_swerv.scala 531:27] + exu.io.dec_tlu_meihap <= dec.io.dec_tlu_meihap @[el2_swerv.scala 532:25] + lsu.reset <= io.core_rst_l @[el2_swerv.scala 536:13] + lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[el2_swerv.scala 537:23] + lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_tlu_flush_lower_r @[el2_swerv.scala 538:32] + lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[el2_swerv.scala 539:35] + lsu.io.dec_tlu_force_halt <= dec.io.dec_tlu_force_halt @[el2_swerv.scala 540:29] + lsu.io.dec_tlu_external_ldfwd_disable <= dec.io.dec_tlu_external_ldfwd_disable @[el2_swerv.scala 541:41] + lsu.io.dec_tlu_wb_coalescing_disable <= dec.io.dec_tlu_wb_coalescing_disable @[el2_swerv.scala 542:40] + lsu.io.dec_tlu_sideeffect_posted_disable <= dec.io.dec_tlu_sideeffect_posted_disable @[el2_swerv.scala 543:44] + lsu.io.dec_tlu_core_ecc_disable <= dec.io.dec_tlu_core_ecc_disable @[el2_swerv.scala 544:35] + lsu.io.exu_lsu_rs1_d <= exu.io.exu_lsu_rs1_d @[el2_swerv.scala 545:24] + lsu.io.exu_lsu_rs2_d <= exu.io.exu_lsu_rs2_d @[el2_swerv.scala 546:24] + lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[el2_swerv.scala 547:27] + lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[el2_swerv.scala 548:16] + lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[el2_swerv.scala 548:16] + lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[el2_swerv.scala 548:16] + lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[el2_swerv.scala 549:30] + lsu.io.dec_tlu_mrac_ff <= dec.io.dec_tlu_mrac_ff @[el2_swerv.scala 550:26] + lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[el2_swerv.scala 551:26] + lsu.io.dccm_rd_data_lo <= io.dccm_rd_data_lo @[el2_swerv.scala 552:26] + lsu.io.dccm_rd_data_hi <= io.dccm_rd_data_hi @[el2_swerv.scala 553:26] + node _T_12 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_awready) @[el2_swerv.scala 554:32] + lsu.io.lsu_axi_awready <= _T_12 @[el2_swerv.scala 554:26] + node _T_13 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_wready) @[el2_swerv.scala 555:32] + lsu.io.lsu_axi_wready <= _T_13 @[el2_swerv.scala 555:25] + node _T_14 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_bvalid) @[el2_swerv.scala 556:32] + lsu.io.lsu_axi_bvalid <= _T_14 @[el2_swerv.scala 556:25] + node _T_15 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_bresp) @[el2_swerv.scala 557:31] + lsu.io.lsu_axi_bresp <= _T_15 @[el2_swerv.scala 557:24] + node _T_16 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_bid) @[el2_swerv.scala 558:29] + lsu.io.lsu_axi_bid <= _T_16 @[el2_swerv.scala 558:22] + node _T_17 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_arready) @[el2_swerv.scala 559:33] + lsu.io.lsu_axi_arready <= _T_17 @[el2_swerv.scala 559:26] + node _T_18 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rvalid) @[el2_swerv.scala 560:32] + lsu.io.lsu_axi_rvalid <= _T_18 @[el2_swerv.scala 560:25] + node _T_19 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rid) @[el2_swerv.scala 561:29] + lsu.io.lsu_axi_rid <= _T_19 @[el2_swerv.scala 561:22] + node _T_20 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rdata) @[el2_swerv.scala 562:31] + lsu.io.lsu_axi_rdata <= _T_20 @[el2_swerv.scala 562:24] + node _T_21 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rresp) @[el2_swerv.scala 563:31] + lsu.io.lsu_axi_rresp <= _T_21 @[el2_swerv.scala 563:24] + node _T_22 = mux(UInt<1>("h00"), UInt<1>("h00"), io.lsu_axi_rlast) @[el2_swerv.scala 564:31] + lsu.io.lsu_axi_rlast <= _T_22 @[el2_swerv.scala 564:24] + lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[el2_swerv.scala 565:25] + lsu.io.dma_dccm_req <= dma_ctrl.io.dma_dccm_req @[el2_swerv.scala 566:23] + lsu.io.dma_mem_tag <= dma_ctrl.io.dma_mem_tag @[el2_swerv.scala 567:22] + lsu.io.dma_mem_addr <= dma_ctrl.io.dma_mem_addr @[el2_swerv.scala 568:23] + lsu.io.dma_mem_sz <= dma_ctrl.io.dma_mem_sz @[el2_swerv.scala 569:21] + lsu.io.dma_mem_write <= dma_ctrl.io.dma_mem_write @[el2_swerv.scala 570:24] + lsu.io.dma_mem_wdata <= dma_ctrl.io.dma_mem_wdata @[el2_swerv.scala 571:24] + lsu.io.scan_mode <= io.scan_mode @[el2_swerv.scala 572:20] + lsu.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 573:19] + dbg.reset <= io.core_rst_l @[el2_swerv.scala 576:13] + node _T_23 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[el2_swerv.scala 577:32] + dbg.io.core_dbg_rddata <= _T_23 @[el2_swerv.scala 577:26] + node _T_24 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[el2_swerv.scala 578:60] + dbg.io.core_dbg_cmd_done <= _T_24 @[el2_swerv.scala 578:28] + node _T_25 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[el2_swerv.scala 579:60] + dbg.io.core_dbg_cmd_fail <= _T_25 @[el2_swerv.scala 579:28] + dbg.io.dma_dbg_ready <= dma_ctrl.io.dma_dbg_ready @[el2_swerv.scala 580:24] + dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[el2_swerv.scala 581:29] + dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[el2_swerv.scala 582:29] + dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[el2_swerv.scala 583:34] + dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[el2_swerv.scala 584:29] + dbg.io.dmi_reg_en <= io.dmi_reg_en @[el2_swerv.scala 585:21] + dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[el2_swerv.scala 586:23] + dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[el2_swerv.scala 587:24] + dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[el2_swerv.scala 588:24] + dbg.io.sb_axi_awready <= io.sb_axi_awready @[el2_swerv.scala 589:25] + dbg.io.sb_axi_wready <= io.sb_axi_wready @[el2_swerv.scala 590:24] + dbg.io.sb_axi_bvalid <= io.sb_axi_bvalid @[el2_swerv.scala 591:24] + dbg.io.sb_axi_bresp <= io.sb_axi_bresp @[el2_swerv.scala 592:23] + dbg.io.sb_axi_arready <= io.sb_axi_arready @[el2_swerv.scala 593:25] + dbg.io.sb_axi_rvalid <= io.sb_axi_rvalid @[el2_swerv.scala 594:24] + dbg.io.sb_axi_rdata <= io.sb_axi_rdata @[el2_swerv.scala 595:23] + dbg.io.sb_axi_rresp <= io.sb_axi_rresp @[el2_swerv.scala 596:23] + dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[el2_swerv.scala 597:25] + node _T_26 = asUInt(io.dbg_rst_l) @[el2_swerv.scala 598:42] + dbg.io.dbg_rst_l <= _T_26 @[el2_swerv.scala 598:20] + dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[el2_swerv.scala 599:23] + dbg.io.scan_mode <= io.scan_mode @[el2_swerv.scala 600:20] + dma_ctrl.reset <= io.core_rst_l @[el2_swerv.scala 604:18] + dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 605:24] + dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[el2_swerv.scala 606:30] + dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[el2_swerv.scala 607:28] + dma_ctrl.io.scan_mode <= io.scan_mode @[el2_swerv.scala 608:25] + dma_ctrl.io.dbg_cmd_addr <= dbg.io.dbg_cmd_addr @[el2_swerv.scala 609:28] + dma_ctrl.io.dbg_cmd_wrdata <= dbg.io.dbg_cmd_wrdata @[el2_swerv.scala 610:30] + dma_ctrl.io.dbg_cmd_valid <= dbg.io.dbg_cmd_valid @[el2_swerv.scala 611:29] + dma_ctrl.io.dbg_cmd_write <= dbg.io.dbg_cmd_write @[el2_swerv.scala 612:29] + dma_ctrl.io.dbg_cmd_type <= dbg.io.dbg_cmd_type @[el2_swerv.scala 613:28] + dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[el2_swerv.scala 614:28] + dma_ctrl.io.dbg_dma_bubble <= dbg.io.dbg_dma_bubble @[el2_swerv.scala 615:30] + dma_ctrl.io.dccm_dma_rvalid <= lsu.io.dccm_dma_rvalid @[el2_swerv.scala 616:31] + dma_ctrl.io.dccm_dma_ecc_error <= lsu.io.dccm_dma_ecc_error @[el2_swerv.scala 617:34] + dma_ctrl.io.dccm_dma_rtag <= lsu.io.dccm_dma_rtag @[el2_swerv.scala 618:29] + dma_ctrl.io.dccm_dma_rdata <= lsu.io.dccm_dma_rdata @[el2_swerv.scala 619:30] + dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[el2_swerv.scala 620:31] + dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[el2_swerv.scala 621:29] + dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[el2_swerv.scala 622:30] + dma_ctrl.io.dccm_ready <= lsu.io.dccm_ready @[el2_swerv.scala 623:26] + dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[el2_swerv.scala 624:26] + dma_ctrl.io.dec_tlu_dma_qos_prty <= dec.io.dec_tlu_dma_qos_prty @[el2_swerv.scala 625:36] + dma_ctrl.io.dma_axi_awvalid <= io.dma_axi_awvalid @[el2_swerv.scala 626:31] + dma_ctrl.io.dma_axi_awid <= io.dma_axi_awid @[el2_swerv.scala 627:28] + dma_ctrl.io.dma_axi_awaddr <= io.dma_axi_awaddr @[el2_swerv.scala 628:30] + dma_ctrl.io.dma_axi_awsize <= io.dma_axi_awsize @[el2_swerv.scala 629:30] + dma_ctrl.io.dma_axi_wvalid <= io.dma_axi_wvalid @[el2_swerv.scala 630:30] + dma_ctrl.io.dma_axi_wdata <= io.dma_axi_wdata @[el2_swerv.scala 631:29] + dma_ctrl.io.dma_axi_wstrb <= io.dma_axi_wstrb @[el2_swerv.scala 632:29] + dma_ctrl.io.dma_axi_bready <= io.dma_axi_bready @[el2_swerv.scala 633:30] + dma_ctrl.io.dma_axi_arvalid <= io.dma_axi_arvalid @[el2_swerv.scala 634:31] + dma_ctrl.io.dma_axi_arid <= io.dma_axi_arid @[el2_swerv.scala 635:28] + dma_ctrl.io.dma_axi_araddr <= io.dma_axi_araddr @[el2_swerv.scala 636:30] + dma_ctrl.io.dma_axi_arsize <= io.dma_axi_arsize @[el2_swerv.scala 637:30] + dma_ctrl.io.dma_axi_rready <= io.dma_axi_rready @[el2_swerv.scala 638:30] + dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[el2_swerv.scala 639:34] + pic_ctrl_inst.io.scan_mode <= io.scan_mode @[el2_swerv.scala 643:30] + pic_ctrl_inst.reset <= io.core_rst_l @[el2_swerv.scala 644:23] + pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[el2_swerv.scala 645:29] + pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[el2_swerv.scala 646:31] + pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[el2_swerv.scala 647:33] + pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[el2_swerv.scala 648:34] + pic_ctrl_inst.io.picm_rdaddr <= lsu.io.picm_rdaddr @[el2_swerv.scala 649:32] + pic_ctrl_inst.io.picm_wraddr <= lsu.io.picm_wraddr @[el2_swerv.scala 650:32] + pic_ctrl_inst.io.picm_wr_data <= lsu.io.picm_wr_data @[el2_swerv.scala 651:33] + pic_ctrl_inst.io.picm_wren <= lsu.io.picm_wren @[el2_swerv.scala 652:30] + pic_ctrl_inst.io.picm_rden <= lsu.io.picm_rden @[el2_swerv.scala 653:30] + pic_ctrl_inst.io.picm_mken <= lsu.io.picm_mken @[el2_swerv.scala 654:30] + pic_ctrl_inst.io.meicurpl <= dec.io.dec_tlu_meicurpl @[el2_swerv.scala 655:29] + pic_ctrl_inst.io.meipt <= dec.io.dec_tlu_meipt @[el2_swerv.scala 656:26] + lsu.io.picm_rd_data <= pic_ctrl_inst.io.picm_rd_data @[el2_swerv.scala 657:23] + io.trace_rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[el2_swerv.scala 663:25] + io.trace_rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[el2_swerv.scala 664:28] + io.trace_rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[el2_swerv.scala 665:26] + io.trace_rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[el2_swerv.scala 666:30] + io.trace_rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[el2_swerv.scala 667:27] + io.trace_rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[el2_swerv.scala 668:30] + io.trace_rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[el2_swerv.scala 669:25] + io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[el2_swerv.scala 673:24] + io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[el2_swerv.scala 674:23] + io.dec_tlu_core_ecc_disable <= dec.io.dec_tlu_core_ecc_disable @[el2_swerv.scala 675:31] + io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[el2_swerv.scala 676:21] + io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[el2_swerv.scala 677:24] + io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[el2_swerv.scala 678:20] + io.o_debug_mode_status <= dec.io.o_debug_mode_status @[el2_swerv.scala 679:26] + io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[el2_swerv.scala 680:25] + io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[el2_swerv.scala 681:24] + io.debug_brkpt_status <= dec.io.debug_brkpt_status @[el2_swerv.scala 682:25] + io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[el2_swerv.scala 683:23] + io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[el2_swerv.scala 684:23] + io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[el2_swerv.scala 685:23] + io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[el2_swerv.scala 686:23] + io.dccm_wren <= lsu.io.dccm_wren @[el2_swerv.scala 688:16] + io.dccm_rden <= lsu.io.dccm_rden @[el2_swerv.scala 689:16] + io.dccm_wr_addr_lo <= lsu.io.dccm_wr_addr_lo @[el2_swerv.scala 690:22] + io.dccm_wr_addr_hi <= lsu.io.dccm_wr_addr_hi @[el2_swerv.scala 691:22] + io.dccm_rd_addr_lo <= lsu.io.dccm_rd_addr_lo @[el2_swerv.scala 692:22] + io.dccm_rd_addr_hi <= lsu.io.dccm_rd_addr_hi @[el2_swerv.scala 693:22] + io.dccm_wr_data_lo <= lsu.io.dccm_wr_data_lo @[el2_swerv.scala 694:22] + io.dccm_wr_data_hi <= lsu.io.dccm_wr_data_hi @[el2_swerv.scala 695:22] + io.iccm_rw_addr <= ifu.io.iccm_rw_addr @[el2_swerv.scala 697:19] + io.iccm_wren <= ifu.io.iccm_wren @[el2_swerv.scala 698:16] + io.iccm_rden <= ifu.io.iccm_rden @[el2_swerv.scala 699:16] + io.iccm_wr_size <= ifu.io.iccm_wr_size @[el2_swerv.scala 700:19] + io.iccm_wr_data <= ifu.io.iccm_wr_data @[el2_swerv.scala 701:19] + io.iccm_buf_correct_ecc <= ifu.io.iccm_buf_correct_ecc @[el2_swerv.scala 702:27] + io.iccm_correction_state <= ifu.io.iccm_correction_state @[el2_swerv.scala 703:28] + io.ic_rw_addr <= ifu.io.ic_rw_addr @[el2_swerv.scala 704:17] + io.ic_tag_valid <= ifu.io.ic_tag_valid @[el2_swerv.scala 705:19] + io.ic_wr_en <= ifu.io.ic_wr_en @[el2_swerv.scala 706:15] + io.ic_rd_en <= ifu.io.ic_rd_en @[el2_swerv.scala 707:15] + io.ic_wr_data[0] <= ifu.io.ic_wr_data[0] @[el2_swerv.scala 708:17] + io.ic_wr_data[1] <= ifu.io.ic_wr_data[1] @[el2_swerv.scala 708:17] + io.ic_debug_wr_data <= ifu.io.ic_debug_wr_data @[el2_swerv.scala 709:23] + io.ic_premux_data <= ifu.io.ic_premux_data @[el2_swerv.scala 710:21] + io.ic_sel_premux_data <= ifu.io.ic_sel_premux_data @[el2_swerv.scala 711:25] + io.ic_debug_addr <= ifu.io.ic_debug_addr @[el2_swerv.scala 712:20] + io.ic_debug_rd_en <= ifu.io.ic_debug_rd_en @[el2_swerv.scala 713:21] + io.ic_debug_wr_en <= ifu.io.ic_debug_wr_en @[el2_swerv.scala 714:21] + io.ic_debug_tag_array <= ifu.io.ic_debug_tag_array @[el2_swerv.scala 715:25] + io.ic_debug_way <= ifu.io.ic_debug_way @[el2_swerv.scala 716:19] + io.lsu_axi_awvalid <= lsu.io.lsu_axi_awvalid @[el2_swerv.scala 719:22] + io.lsu_axi_awid <= lsu.io.lsu_axi_awid @[el2_swerv.scala 720:19] + io.lsu_axi_awaddr <= lsu.io.lsu_axi_awaddr @[el2_swerv.scala 721:21] + io.lsu_axi_awregion <= lsu.io.lsu_axi_awregion @[el2_swerv.scala 722:23] + io.lsu_axi_awlen <= lsu.io.lsu_axi_awlen @[el2_swerv.scala 723:20] + io.lsu_axi_awsize <= lsu.io.lsu_axi_awsize @[el2_swerv.scala 724:21] + io.lsu_axi_awburst <= lsu.io.lsu_axi_awburst @[el2_swerv.scala 725:22] + io.lsu_axi_awlock <= lsu.io.lsu_axi_awlock @[el2_swerv.scala 726:21] + io.lsu_axi_awcache <= lsu.io.lsu_axi_awcache @[el2_swerv.scala 727:22] + io.lsu_axi_awprot <= lsu.io.lsu_axi_awprot @[el2_swerv.scala 728:21] + io.lsu_axi_awqos <= lsu.io.lsu_axi_awqos @[el2_swerv.scala 729:20] + io.lsu_axi_wvalid <= lsu.io.lsu_axi_wvalid @[el2_swerv.scala 730:21] + io.lsu_axi_wdata <= lsu.io.lsu_axi_wdata @[el2_swerv.scala 731:20] + io.lsu_axi_wstrb <= lsu.io.lsu_axi_wstrb @[el2_swerv.scala 732:20] + io.lsu_axi_wlast <= lsu.io.lsu_axi_wlast @[el2_swerv.scala 733:20] + io.lsu_axi_bready <= lsu.io.lsu_axi_bready @[el2_swerv.scala 734:21] + io.lsu_axi_arvalid <= lsu.io.lsu_axi_arvalid @[el2_swerv.scala 735:22] + io.lsu_axi_arid <= lsu.io.lsu_axi_arid @[el2_swerv.scala 736:19] + io.lsu_axi_araddr <= lsu.io.lsu_axi_araddr @[el2_swerv.scala 737:21] + io.lsu_axi_arregion <= lsu.io.lsu_axi_arregion @[el2_swerv.scala 738:23] + io.lsu_axi_arlen <= lsu.io.lsu_axi_arlen @[el2_swerv.scala 739:20] + io.lsu_axi_arsize <= lsu.io.lsu_axi_arsize @[el2_swerv.scala 740:21] + io.lsu_axi_arburst <= lsu.io.lsu_axi_arburst @[el2_swerv.scala 741:22] + io.lsu_axi_arlock <= lsu.io.lsu_axi_arlock @[el2_swerv.scala 742:21] + io.lsu_axi_arcache <= lsu.io.lsu_axi_arcache @[el2_swerv.scala 743:22] + io.lsu_axi_arprot <= lsu.io.lsu_axi_arprot @[el2_swerv.scala 744:21] + io.lsu_axi_arqos <= lsu.io.lsu_axi_arqos @[el2_swerv.scala 745:20] + io.lsu_axi_rready <= lsu.io.lsu_axi_rready @[el2_swerv.scala 746:21] + io.ifu_axi_awvalid <= ifu.io.ifu_axi_awvalid @[el2_swerv.scala 749:22] + io.ifu_axi_awid <= ifu.io.ifu_axi_awid @[el2_swerv.scala 750:19] + io.ifu_axi_awaddr <= ifu.io.ifu_axi_awaddr @[el2_swerv.scala 751:21] + io.ifu_axi_awregion <= ifu.io.ifu_axi_awregion @[el2_swerv.scala 752:23] + io.ifu_axi_awlen <= ifu.io.ifu_axi_awlen @[el2_swerv.scala 753:20] + io.ifu_axi_awsize <= ifu.io.ifu_axi_awsize @[el2_swerv.scala 754:21] + io.ifu_axi_awburst <= ifu.io.ifu_axi_awburst @[el2_swerv.scala 755:22] + io.ifu_axi_awlock <= ifu.io.ifu_axi_awlock @[el2_swerv.scala 756:21] + io.ifu_axi_awcache <= ifu.io.ifu_axi_awcache @[el2_swerv.scala 757:22] + io.ifu_axi_awprot <= ifu.io.ifu_axi_awprot @[el2_swerv.scala 758:21] + io.ifu_axi_awqos <= ifu.io.ifu_axi_awqos @[el2_swerv.scala 759:20] + io.ifu_axi_wvalid <= ifu.io.ifu_axi_wvalid @[el2_swerv.scala 760:21] + io.ifu_axi_wdata <= ifu.io.ifu_axi_wdata @[el2_swerv.scala 761:20] + io.ifu_axi_wstrb <= ifu.io.ifu_axi_wstrb @[el2_swerv.scala 762:20] + io.ifu_axi_wlast <= ifu.io.ifu_axi_wlast @[el2_swerv.scala 763:20] + io.ifu_axi_bready <= ifu.io.ifu_axi_bready @[el2_swerv.scala 764:21] + io.ifu_axi_arvalid <= ifu.io.ifu_axi_arvalid @[el2_swerv.scala 765:22] + io.ifu_axi_arid <= ifu.io.ifu_axi_arid @[el2_swerv.scala 766:19] + io.ifu_axi_araddr <= ifu.io.ifu_axi_araddr @[el2_swerv.scala 767:21] + io.ifu_axi_arregion <= ifu.io.ifu_axi_arregion @[el2_swerv.scala 768:23] + io.ifu_axi_arlen <= ifu.io.ifu_axi_arlen @[el2_swerv.scala 769:20] + io.ifu_axi_arsize <= ifu.io.ifu_axi_arsize @[el2_swerv.scala 770:21] + io.ifu_axi_arburst <= ifu.io.ifu_axi_arburst @[el2_swerv.scala 771:22] + io.ifu_axi_arlock <= ifu.io.ifu_axi_arlock @[el2_swerv.scala 772:21] + io.ifu_axi_arcache <= ifu.io.ifu_axi_arcache @[el2_swerv.scala 773:22] + io.ifu_axi_arprot <= ifu.io.ifu_axi_arprot @[el2_swerv.scala 774:21] + io.ifu_axi_arqos <= ifu.io.ifu_axi_arqos @[el2_swerv.scala 775:20] + io.ifu_axi_rready <= ifu.io.ifu_axi_rready @[el2_swerv.scala 776:21] + io.sb_axi_awvalid <= dbg.io.sb_axi_awvalid @[el2_swerv.scala 780:21] + io.sb_axi_awid <= dbg.io.sb_axi_awid @[el2_swerv.scala 781:18] + io.sb_axi_awaddr <= dbg.io.sb_axi_awaddr @[el2_swerv.scala 782:20] + io.sb_axi_awregion <= dbg.io.sb_axi_awregion @[el2_swerv.scala 783:22] + io.sb_axi_awlen <= dbg.io.sb_axi_awlen @[el2_swerv.scala 784:19] + io.sb_axi_awsize <= dbg.io.sb_axi_awsize @[el2_swerv.scala 785:20] + io.sb_axi_awburst <= dbg.io.sb_axi_awburst @[el2_swerv.scala 786:21] + io.sb_axi_awlock <= dbg.io.sb_axi_awlock @[el2_swerv.scala 787:20] + io.sb_axi_awcache <= dbg.io.sb_axi_awcache @[el2_swerv.scala 788:21] + io.sb_axi_awprot <= dbg.io.sb_axi_awprot @[el2_swerv.scala 789:20] + io.sb_axi_awqos <= dbg.io.sb_axi_awqos @[el2_swerv.scala 790:19] + io.sb_axi_wvalid <= dbg.io.sb_axi_wvalid @[el2_swerv.scala 791:20] + io.sb_axi_wdata <= dbg.io.sb_axi_wdata @[el2_swerv.scala 792:19] + io.sb_axi_wstrb <= dbg.io.sb_axi_wstrb @[el2_swerv.scala 793:19] + io.sb_axi_wlast <= dbg.io.sb_axi_wlast @[el2_swerv.scala 794:19] + io.sb_axi_bready <= dbg.io.sb_axi_bready @[el2_swerv.scala 795:20] + io.sb_axi_arvalid <= dbg.io.sb_axi_arvalid @[el2_swerv.scala 796:21] + io.sb_axi_arid <= dbg.io.sb_axi_arid @[el2_swerv.scala 797:18] + io.sb_axi_araddr <= dbg.io.sb_axi_araddr @[el2_swerv.scala 798:20] + io.sb_axi_arregion <= dbg.io.sb_axi_arregion @[el2_swerv.scala 799:22] + io.sb_axi_arlen <= dbg.io.sb_axi_arlen @[el2_swerv.scala 800:19] + io.sb_axi_arsize <= dbg.io.sb_axi_arsize @[el2_swerv.scala 801:20] + io.sb_axi_arburst <= dbg.io.sb_axi_arburst @[el2_swerv.scala 802:21] + io.sb_axi_arlock <= dbg.io.sb_axi_arlock @[el2_swerv.scala 803:20] + io.sb_axi_arcache <= dbg.io.sb_axi_arcache @[el2_swerv.scala 804:21] + io.sb_axi_arprot <= dbg.io.sb_axi_arprot @[el2_swerv.scala 805:20] + io.sb_axi_arqos <= dbg.io.sb_axi_arqos @[el2_swerv.scala 806:19] + io.sb_axi_rready <= dbg.io.sb_axi_rready @[el2_swerv.scala 807:20] + io.dma_axi_awready <= dma_ctrl.io.dma_axi_awready @[el2_swerv.scala 810:22] + io.dma_axi_wready <= dma_ctrl.io.dma_axi_wready @[el2_swerv.scala 811:21] + io.dma_axi_bvalid <= dma_ctrl.io.dma_axi_bvalid @[el2_swerv.scala 812:21] + io.dma_axi_bresp <= dma_ctrl.io.dma_axi_bresp @[el2_swerv.scala 813:20] + io.dma_axi_bid <= dma_ctrl.io.dma_axi_bid @[el2_swerv.scala 814:18] + io.dma_axi_arready <= dma_ctrl.io.dma_axi_arready @[el2_swerv.scala 815:22] + io.dma_axi_rvalid <= dma_ctrl.io.dma_axi_rvalid @[el2_swerv.scala 816:21] + io.dma_axi_rid <= dma_ctrl.io.dma_axi_rid @[el2_swerv.scala 817:18] + io.dma_axi_rdata <= dma_ctrl.io.dma_axi_rdata @[el2_swerv.scala 818:20] + io.dma_axi_rresp <= dma_ctrl.io.dma_axi_rresp @[el2_swerv.scala 819:20] + io.dma_axi_rlast <= dma_ctrl.io.dma_axi_rlast @[el2_swerv.scala 820:20] + io.hburst <= UInt<1>("h00") @[el2_swerv.scala 823:13] + io.hmastlock <= UInt<1>("h00") @[el2_swerv.scala 824:16] + io.hprot <= UInt<1>("h00") @[el2_swerv.scala 825:12] + io.hsize <= UInt<1>("h00") @[el2_swerv.scala 826:12] + io.htrans <= UInt<1>("h00") @[el2_swerv.scala 827:13] + io.hwrite <= UInt<1>("h00") @[el2_swerv.scala 828:13] + io.haddr <= UInt<1>("h00") @[el2_swerv.scala 829:12] + io.lsu_haddr <= UInt<1>("h00") @[el2_swerv.scala 831:16] + io.lsu_hburst <= UInt<1>("h00") @[el2_swerv.scala 832:17] + io.lsu_hmastlock <= UInt<1>("h00") @[el2_swerv.scala 833:20] + io.lsu_hprot <= UInt<1>("h00") @[el2_swerv.scala 834:16] + io.lsu_hsize <= UInt<1>("h00") @[el2_swerv.scala 835:16] + io.lsu_htrans <= UInt<1>("h00") @[el2_swerv.scala 836:17] + io.lsu_hwrite <= UInt<1>("h00") @[el2_swerv.scala 837:17] + io.lsu_hwdata <= UInt<1>("h00") @[el2_swerv.scala 838:17] + io.sb_haddr <= UInt<1>("h00") @[el2_swerv.scala 841:15] + io.sb_hburst <= UInt<1>("h00") @[el2_swerv.scala 842:16] + io.sb_hmastlock <= UInt<1>("h00") @[el2_swerv.scala 843:19] + io.sb_hprot <= UInt<1>("h00") @[el2_swerv.scala 844:15] + io.sb_hsize <= UInt<1>("h00") @[el2_swerv.scala 845:15] + io.sb_htrans <= UInt<1>("h00") @[el2_swerv.scala 846:16] + io.sb_hwrite <= UInt<1>("h00") @[el2_swerv.scala 847:16] + io.sb_hwdata <= UInt<1>("h00") @[el2_swerv.scala 848:16] + io.dma_hrdata <= UInt<1>("h00") @[el2_swerv.scala 850:17] + io.dma_hreadyout <= UInt<1>("h00") @[el2_swerv.scala 851:20] + io.dma_hresp <= UInt<1>("h00") @[el2_swerv.scala 852:16] + io.dma_hresp <= UInt<1>("h00") @[el2_swerv.scala 856:16] + io.dmi_reg_rdata <= UInt<1>("h00") @[el2_swerv.scala 858:20] diff --git a/el2_swerv.v b/el2_swerv.v index 50665b0e..a2f421e7 100644 --- a/el2_swerv.v +++ b/el2_swerv.v @@ -11814,11 +11814,11 @@ module el2_ifu_bp_ctl( input [30:0] io_ifc_fetch_addr_f, input io_ifc_fetch_req_f, input io_dec_tlu_br0_r_pkt_valid, - input [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - input io_dec_tlu_br0_r_pkt_bits_br_error, - input io_dec_tlu_br0_r_pkt_bits_br_start_error, - input io_dec_tlu_br0_r_pkt_bits_way, - input io_dec_tlu_br0_r_pkt_bits_middle, + input [1:0] io_dec_tlu_br0_r_pkt_hist, + input io_dec_tlu_br0_r_pkt_br_error, + input io_dec_tlu_br0_r_pkt_br_start_error, + input io_dec_tlu_br0_r_pkt_way, + input io_dec_tlu_br0_r_pkt_middle, input [7:0] io_exu_i0_br_fghr_r, input [7:0] io_exu_i0_br_index_r, input io_dec_tlu_flush_lower_wb, @@ -11826,6 +11826,7 @@ module el2_ifu_bp_ctl( input io_dec_tlu_bpred_disable, input io_exu_mp_pkt_bits_misp, input io_exu_mp_pkt_bits_ataken, + input io_exu_mp_pkt_bits_boffset, input io_exu_mp_pkt_bits_pc4, input [1:0] io_exu_mp_pkt_bits_hist, input [11:0] io_exu_mp_pkt_bits_toffset, @@ -15114,7 +15115,7 @@ module el2_ifu_bp_ctl( wire leak_one_f = _T_40 | _T_41; // @[el2_ifu_bp_ctl.scala 135:76] wire _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 72:51] wire exu_mp_valid = io_exu_mp_pkt_bits_misp & _T; // @[el2_ifu_bp_ctl.scala 72:49] - wire dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_bits_br_start_error | io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu_bp_ctl.scala 94:50] + wire dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_br_start_error | io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu_bp_ctl.scala 94:50] wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 191:47] wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 191:85] wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_bp_ctl.scala 102:51] @@ -21041,18 +21042,19 @@ module el2_ifu_bp_ctl( wire _T_531 = io_exu_mp_pkt_bits_pcall | io_exu_mp_pkt_bits_pja; // @[el2_ifu_bp_ctl.scala 396:89] wire _T_532 = io_exu_mp_pkt_bits_pret | io_exu_mp_pkt_bits_pja; // @[el2_ifu_bp_ctl.scala 396:113] wire [2:0] _T_534 = {_T_531,_T_532,btb_valid}; // @[Cat.scala 29:58] - wire [18:0] _T_537 = {io_exu_mp_btag,io_exu_mp_pkt_bits_toffset,io_exu_mp_pkt_bits_pc4,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_537 = {io_exu_mp_btag,io_exu_mp_pkt_bits_toffset,io_exu_mp_pkt_bits_pc4,io_exu_mp_pkt_bits_boffset}; // @[Cat.scala 29:58] wire exu_mp_valid_write = exu_mp_valid & io_exu_mp_pkt_bits_ataken; // @[el2_ifu_bp_ctl.scala 397:41] wire _T_539 = _T_175 & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 400:39] wire _T_541 = _T_539 & _T_530; // @[el2_ifu_bp_ctl.scala 400:60] - wire _T_542 = ~io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu_bp_ctl.scala 400:87] + wire _T_542 = ~io_dec_tlu_br0_r_pkt_way; // @[el2_ifu_bp_ctl.scala 400:87] wire _T_543 = _T_542 & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 400:104] wire btb_wr_en_way0 = _T_541 | _T_543; // @[el2_ifu_bp_ctl.scala 400:83] wire _T_544 = io_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 401:36] wire _T_546 = _T_544 & _T_530; // @[el2_ifu_bp_ctl.scala 401:57] - wire _T_547 = io_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98] + wire _T_547 = io_dec_tlu_br0_r_pkt_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98] wire btb_wr_en_way1 = _T_546 | _T_547; // @[el2_ifu_bp_ctl.scala 401:80] wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_i0_br_index_r : io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 404:24] + wire middle_of_bank = io_exu_mp_pkt_bits_pc4 ^ io_exu_mp_pkt_bits_boffset; // @[el2_ifu_bp_ctl.scala 405:35] wire _T_549 = ~io_exu_mp_pkt_bits_pcall; // @[el2_ifu_bp_ctl.scala 408:43] wire _T_550 = exu_mp_valid & _T_549; // @[el2_ifu_bp_ctl.scala 408:41] wire _T_551 = ~io_exu_mp_pkt_bits_pret; // @[el2_ifu_bp_ctl.scala 408:58] @@ -21060,12 +21062,12 @@ module el2_ifu_bp_ctl( wire _T_553 = ~io_exu_mp_pkt_bits_pja; // @[el2_ifu_bp_ctl.scala 408:72] wire _T_554 = _T_552 & _T_553; // @[el2_ifu_bp_ctl.scala 408:70] wire [1:0] _T_556 = _T_554 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_557 = ~io_exu_mp_pkt_bits_pc4; // @[el2_ifu_bp_ctl.scala 408:106] - wire [1:0] _T_558 = {io_exu_mp_pkt_bits_pc4,_T_557}; // @[Cat.scala 29:58] + wire _T_557 = ~middle_of_bank; // @[el2_ifu_bp_ctl.scala 408:106] + wire [1:0] _T_558 = {middle_of_bank,_T_557}; // @[Cat.scala 29:58] wire [1:0] bht_wr_en0 = _T_556 & _T_558; // @[el2_ifu_bp_ctl.scala 408:84] wire [1:0] _T_560 = io_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_561 = ~io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu_bp_ctl.scala 409:75] - wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_bits_middle,_T_561}; // @[Cat.scala 29:58] + wire _T_561 = ~io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu_bp_ctl.scala 409:75] + wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_middle,_T_561}; // @[Cat.scala 29:58] wire [1:0] bht_wr_en2 = _T_560 & _T_562; // @[el2_ifu_bp_ctl.scala 409:46] wire [9:0] _T_563 = {io_exu_mp_index,2'h0}; // @[Cat.scala 29:58] wire [7:0] mp_hashed = _T_563[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 196:35] @@ -35092,7 +35094,7 @@ end // initial if (reset) begin dec_tlu_way_wb_f <= 1'h0; end else begin - dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_bits_way; + dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_way; end end always @(posedge rvclkhdr_266_io_l1clk or posedge reset) begin @@ -36899,7 +36901,7 @@ end // initial bht_bank_rd_data_out_1_0 <= 2'h0; end else if (bht_bank_sel_1_0_0) begin if (_T_8869) begin - bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_0 <= io_exu_mp_pkt_bits_hist; end @@ -36910,7 +36912,7 @@ end // initial bht_bank_rd_data_out_1_1 <= 2'h0; end else if (bht_bank_sel_1_0_1) begin if (_T_8878) begin - bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_1 <= io_exu_mp_pkt_bits_hist; end @@ -36921,7 +36923,7 @@ end // initial bht_bank_rd_data_out_1_2 <= 2'h0; end else if (bht_bank_sel_1_0_2) begin if (_T_8887) begin - bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_2 <= io_exu_mp_pkt_bits_hist; end @@ -36932,7 +36934,7 @@ end // initial bht_bank_rd_data_out_1_3 <= 2'h0; end else if (bht_bank_sel_1_0_3) begin if (_T_8896) begin - bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_3 <= io_exu_mp_pkt_bits_hist; end @@ -36943,7 +36945,7 @@ end // initial bht_bank_rd_data_out_1_4 <= 2'h0; end else if (bht_bank_sel_1_0_4) begin if (_T_8905) begin - bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_4 <= io_exu_mp_pkt_bits_hist; end @@ -36954,7 +36956,7 @@ end // initial bht_bank_rd_data_out_1_5 <= 2'h0; end else if (bht_bank_sel_1_0_5) begin if (_T_8914) begin - bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_5 <= io_exu_mp_pkt_bits_hist; end @@ -36965,7 +36967,7 @@ end // initial bht_bank_rd_data_out_1_6 <= 2'h0; end else if (bht_bank_sel_1_0_6) begin if (_T_8923) begin - bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_6 <= io_exu_mp_pkt_bits_hist; end @@ -36976,7 +36978,7 @@ end // initial bht_bank_rd_data_out_1_7 <= 2'h0; end else if (bht_bank_sel_1_0_7) begin if (_T_8932) begin - bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_7 <= io_exu_mp_pkt_bits_hist; end @@ -36987,7 +36989,7 @@ end // initial bht_bank_rd_data_out_1_8 <= 2'h0; end else if (bht_bank_sel_1_0_8) begin if (_T_8941) begin - bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_8 <= io_exu_mp_pkt_bits_hist; end @@ -36998,7 +37000,7 @@ end // initial bht_bank_rd_data_out_1_9 <= 2'h0; end else if (bht_bank_sel_1_0_9) begin if (_T_8950) begin - bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_9 <= io_exu_mp_pkt_bits_hist; end @@ -37009,7 +37011,7 @@ end // initial bht_bank_rd_data_out_1_10 <= 2'h0; end else if (bht_bank_sel_1_0_10) begin if (_T_8959) begin - bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_10 <= io_exu_mp_pkt_bits_hist; end @@ -37020,7 +37022,7 @@ end // initial bht_bank_rd_data_out_1_11 <= 2'h0; end else if (bht_bank_sel_1_0_11) begin if (_T_8968) begin - bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_11 <= io_exu_mp_pkt_bits_hist; end @@ -37031,7 +37033,7 @@ end // initial bht_bank_rd_data_out_1_12 <= 2'h0; end else if (bht_bank_sel_1_0_12) begin if (_T_8977) begin - bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_12 <= io_exu_mp_pkt_bits_hist; end @@ -37042,7 +37044,7 @@ end // initial bht_bank_rd_data_out_1_13 <= 2'h0; end else if (bht_bank_sel_1_0_13) begin if (_T_8986) begin - bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_13 <= io_exu_mp_pkt_bits_hist; end @@ -37053,7 +37055,7 @@ end // initial bht_bank_rd_data_out_1_14 <= 2'h0; end else if (bht_bank_sel_1_0_14) begin if (_T_8995) begin - bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_14 <= io_exu_mp_pkt_bits_hist; end @@ -37064,7 +37066,7 @@ end // initial bht_bank_rd_data_out_1_15 <= 2'h0; end else if (bht_bank_sel_1_0_15) begin if (_T_9004) begin - bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_15 <= io_exu_mp_pkt_bits_hist; end @@ -37075,7 +37077,7 @@ end // initial bht_bank_rd_data_out_1_16 <= 2'h0; end else if (bht_bank_sel_1_1_0) begin if (_T_9013) begin - bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_16 <= io_exu_mp_pkt_bits_hist; end @@ -37086,7 +37088,7 @@ end // initial bht_bank_rd_data_out_1_17 <= 2'h0; end else if (bht_bank_sel_1_1_1) begin if (_T_9022) begin - bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_17 <= io_exu_mp_pkt_bits_hist; end @@ -37097,7 +37099,7 @@ end // initial bht_bank_rd_data_out_1_18 <= 2'h0; end else if (bht_bank_sel_1_1_2) begin if (_T_9031) begin - bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_18 <= io_exu_mp_pkt_bits_hist; end @@ -37108,7 +37110,7 @@ end // initial bht_bank_rd_data_out_1_19 <= 2'h0; end else if (bht_bank_sel_1_1_3) begin if (_T_9040) begin - bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_19 <= io_exu_mp_pkt_bits_hist; end @@ -37119,7 +37121,7 @@ end // initial bht_bank_rd_data_out_1_20 <= 2'h0; end else if (bht_bank_sel_1_1_4) begin if (_T_9049) begin - bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_20 <= io_exu_mp_pkt_bits_hist; end @@ -37130,7 +37132,7 @@ end // initial bht_bank_rd_data_out_1_21 <= 2'h0; end else if (bht_bank_sel_1_1_5) begin if (_T_9058) begin - bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_21 <= io_exu_mp_pkt_bits_hist; end @@ -37141,7 +37143,7 @@ end // initial bht_bank_rd_data_out_1_22 <= 2'h0; end else if (bht_bank_sel_1_1_6) begin if (_T_9067) begin - bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_22 <= io_exu_mp_pkt_bits_hist; end @@ -37152,7 +37154,7 @@ end // initial bht_bank_rd_data_out_1_23 <= 2'h0; end else if (bht_bank_sel_1_1_7) begin if (_T_9076) begin - bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_23 <= io_exu_mp_pkt_bits_hist; end @@ -37163,7 +37165,7 @@ end // initial bht_bank_rd_data_out_1_24 <= 2'h0; end else if (bht_bank_sel_1_1_8) begin if (_T_9085) begin - bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_24 <= io_exu_mp_pkt_bits_hist; end @@ -37174,7 +37176,7 @@ end // initial bht_bank_rd_data_out_1_25 <= 2'h0; end else if (bht_bank_sel_1_1_9) begin if (_T_9094) begin - bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_25 <= io_exu_mp_pkt_bits_hist; end @@ -37185,7 +37187,7 @@ end // initial bht_bank_rd_data_out_1_26 <= 2'h0; end else if (bht_bank_sel_1_1_10) begin if (_T_9103) begin - bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_26 <= io_exu_mp_pkt_bits_hist; end @@ -37196,7 +37198,7 @@ end // initial bht_bank_rd_data_out_1_27 <= 2'h0; end else if (bht_bank_sel_1_1_11) begin if (_T_9112) begin - bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_27 <= io_exu_mp_pkt_bits_hist; end @@ -37207,7 +37209,7 @@ end // initial bht_bank_rd_data_out_1_28 <= 2'h0; end else if (bht_bank_sel_1_1_12) begin if (_T_9121) begin - bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_28 <= io_exu_mp_pkt_bits_hist; end @@ -37218,7 +37220,7 @@ end // initial bht_bank_rd_data_out_1_29 <= 2'h0; end else if (bht_bank_sel_1_1_13) begin if (_T_9130) begin - bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_29 <= io_exu_mp_pkt_bits_hist; end @@ -37229,7 +37231,7 @@ end // initial bht_bank_rd_data_out_1_30 <= 2'h0; end else if (bht_bank_sel_1_1_14) begin if (_T_9139) begin - bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_30 <= io_exu_mp_pkt_bits_hist; end @@ -37240,7 +37242,7 @@ end // initial bht_bank_rd_data_out_1_31 <= 2'h0; end else if (bht_bank_sel_1_1_15) begin if (_T_9148) begin - bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_31 <= io_exu_mp_pkt_bits_hist; end @@ -37251,7 +37253,7 @@ end // initial bht_bank_rd_data_out_1_32 <= 2'h0; end else if (bht_bank_sel_1_2_0) begin if (_T_9157) begin - bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_32 <= io_exu_mp_pkt_bits_hist; end @@ -37262,7 +37264,7 @@ end // initial bht_bank_rd_data_out_1_33 <= 2'h0; end else if (bht_bank_sel_1_2_1) begin if (_T_9166) begin - bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_33 <= io_exu_mp_pkt_bits_hist; end @@ -37273,7 +37275,7 @@ end // initial bht_bank_rd_data_out_1_34 <= 2'h0; end else if (bht_bank_sel_1_2_2) begin if (_T_9175) begin - bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_34 <= io_exu_mp_pkt_bits_hist; end @@ -37284,7 +37286,7 @@ end // initial bht_bank_rd_data_out_1_35 <= 2'h0; end else if (bht_bank_sel_1_2_3) begin if (_T_9184) begin - bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_35 <= io_exu_mp_pkt_bits_hist; end @@ -37295,7 +37297,7 @@ end // initial bht_bank_rd_data_out_1_36 <= 2'h0; end else if (bht_bank_sel_1_2_4) begin if (_T_9193) begin - bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_36 <= io_exu_mp_pkt_bits_hist; end @@ -37306,7 +37308,7 @@ end // initial bht_bank_rd_data_out_1_37 <= 2'h0; end else if (bht_bank_sel_1_2_5) begin if (_T_9202) begin - bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_37 <= io_exu_mp_pkt_bits_hist; end @@ -37317,7 +37319,7 @@ end // initial bht_bank_rd_data_out_1_38 <= 2'h0; end else if (bht_bank_sel_1_2_6) begin if (_T_9211) begin - bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_38 <= io_exu_mp_pkt_bits_hist; end @@ -37328,7 +37330,7 @@ end // initial bht_bank_rd_data_out_1_39 <= 2'h0; end else if (bht_bank_sel_1_2_7) begin if (_T_9220) begin - bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_39 <= io_exu_mp_pkt_bits_hist; end @@ -37339,7 +37341,7 @@ end // initial bht_bank_rd_data_out_1_40 <= 2'h0; end else if (bht_bank_sel_1_2_8) begin if (_T_9229) begin - bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_40 <= io_exu_mp_pkt_bits_hist; end @@ -37350,7 +37352,7 @@ end // initial bht_bank_rd_data_out_1_41 <= 2'h0; end else if (bht_bank_sel_1_2_9) begin if (_T_9238) begin - bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_41 <= io_exu_mp_pkt_bits_hist; end @@ -37361,7 +37363,7 @@ end // initial bht_bank_rd_data_out_1_42 <= 2'h0; end else if (bht_bank_sel_1_2_10) begin if (_T_9247) begin - bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_42 <= io_exu_mp_pkt_bits_hist; end @@ -37372,7 +37374,7 @@ end // initial bht_bank_rd_data_out_1_43 <= 2'h0; end else if (bht_bank_sel_1_2_11) begin if (_T_9256) begin - bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_43 <= io_exu_mp_pkt_bits_hist; end @@ -37383,7 +37385,7 @@ end // initial bht_bank_rd_data_out_1_44 <= 2'h0; end else if (bht_bank_sel_1_2_12) begin if (_T_9265) begin - bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_44 <= io_exu_mp_pkt_bits_hist; end @@ -37394,7 +37396,7 @@ end // initial bht_bank_rd_data_out_1_45 <= 2'h0; end else if (bht_bank_sel_1_2_13) begin if (_T_9274) begin - bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_45 <= io_exu_mp_pkt_bits_hist; end @@ -37405,7 +37407,7 @@ end // initial bht_bank_rd_data_out_1_46 <= 2'h0; end else if (bht_bank_sel_1_2_14) begin if (_T_9283) begin - bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_46 <= io_exu_mp_pkt_bits_hist; end @@ -37416,7 +37418,7 @@ end // initial bht_bank_rd_data_out_1_47 <= 2'h0; end else if (bht_bank_sel_1_2_15) begin if (_T_9292) begin - bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_47 <= io_exu_mp_pkt_bits_hist; end @@ -37427,7 +37429,7 @@ end // initial bht_bank_rd_data_out_1_48 <= 2'h0; end else if (bht_bank_sel_1_3_0) begin if (_T_9301) begin - bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_48 <= io_exu_mp_pkt_bits_hist; end @@ -37438,7 +37440,7 @@ end // initial bht_bank_rd_data_out_1_49 <= 2'h0; end else if (bht_bank_sel_1_3_1) begin if (_T_9310) begin - bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_49 <= io_exu_mp_pkt_bits_hist; end @@ -37449,7 +37451,7 @@ end // initial bht_bank_rd_data_out_1_50 <= 2'h0; end else if (bht_bank_sel_1_3_2) begin if (_T_9319) begin - bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_50 <= io_exu_mp_pkt_bits_hist; end @@ -37460,7 +37462,7 @@ end // initial bht_bank_rd_data_out_1_51 <= 2'h0; end else if (bht_bank_sel_1_3_3) begin if (_T_9328) begin - bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_51 <= io_exu_mp_pkt_bits_hist; end @@ -37471,7 +37473,7 @@ end // initial bht_bank_rd_data_out_1_52 <= 2'h0; end else if (bht_bank_sel_1_3_4) begin if (_T_9337) begin - bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_52 <= io_exu_mp_pkt_bits_hist; end @@ -37482,7 +37484,7 @@ end // initial bht_bank_rd_data_out_1_53 <= 2'h0; end else if (bht_bank_sel_1_3_5) begin if (_T_9346) begin - bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_53 <= io_exu_mp_pkt_bits_hist; end @@ -37493,7 +37495,7 @@ end // initial bht_bank_rd_data_out_1_54 <= 2'h0; end else if (bht_bank_sel_1_3_6) begin if (_T_9355) begin - bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_54 <= io_exu_mp_pkt_bits_hist; end @@ -37504,7 +37506,7 @@ end // initial bht_bank_rd_data_out_1_55 <= 2'h0; end else if (bht_bank_sel_1_3_7) begin if (_T_9364) begin - bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_55 <= io_exu_mp_pkt_bits_hist; end @@ -37515,7 +37517,7 @@ end // initial bht_bank_rd_data_out_1_56 <= 2'h0; end else if (bht_bank_sel_1_3_8) begin if (_T_9373) begin - bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_56 <= io_exu_mp_pkt_bits_hist; end @@ -37526,7 +37528,7 @@ end // initial bht_bank_rd_data_out_1_57 <= 2'h0; end else if (bht_bank_sel_1_3_9) begin if (_T_9382) begin - bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_57 <= io_exu_mp_pkt_bits_hist; end @@ -37537,7 +37539,7 @@ end // initial bht_bank_rd_data_out_1_58 <= 2'h0; end else if (bht_bank_sel_1_3_10) begin if (_T_9391) begin - bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_58 <= io_exu_mp_pkt_bits_hist; end @@ -37548,7 +37550,7 @@ end // initial bht_bank_rd_data_out_1_59 <= 2'h0; end else if (bht_bank_sel_1_3_11) begin if (_T_9400) begin - bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_59 <= io_exu_mp_pkt_bits_hist; end @@ -37559,7 +37561,7 @@ end // initial bht_bank_rd_data_out_1_60 <= 2'h0; end else if (bht_bank_sel_1_3_12) begin if (_T_9409) begin - bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_60 <= io_exu_mp_pkt_bits_hist; end @@ -37570,7 +37572,7 @@ end // initial bht_bank_rd_data_out_1_61 <= 2'h0; end else if (bht_bank_sel_1_3_13) begin if (_T_9418) begin - bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_61 <= io_exu_mp_pkt_bits_hist; end @@ -37581,7 +37583,7 @@ end // initial bht_bank_rd_data_out_1_62 <= 2'h0; end else if (bht_bank_sel_1_3_14) begin if (_T_9427) begin - bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_62 <= io_exu_mp_pkt_bits_hist; end @@ -37592,7 +37594,7 @@ end // initial bht_bank_rd_data_out_1_63 <= 2'h0; end else if (bht_bank_sel_1_3_15) begin if (_T_9436) begin - bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_63 <= io_exu_mp_pkt_bits_hist; end @@ -37603,7 +37605,7 @@ end // initial bht_bank_rd_data_out_1_64 <= 2'h0; end else if (bht_bank_sel_1_4_0) begin if (_T_9445) begin - bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_64 <= io_exu_mp_pkt_bits_hist; end @@ -37614,7 +37616,7 @@ end // initial bht_bank_rd_data_out_1_65 <= 2'h0; end else if (bht_bank_sel_1_4_1) begin if (_T_9454) begin - bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_65 <= io_exu_mp_pkt_bits_hist; end @@ -37625,7 +37627,7 @@ end // initial bht_bank_rd_data_out_1_66 <= 2'h0; end else if (bht_bank_sel_1_4_2) begin if (_T_9463) begin - bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_66 <= io_exu_mp_pkt_bits_hist; end @@ -37636,7 +37638,7 @@ end // initial bht_bank_rd_data_out_1_67 <= 2'h0; end else if (bht_bank_sel_1_4_3) begin if (_T_9472) begin - bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_67 <= io_exu_mp_pkt_bits_hist; end @@ -37647,7 +37649,7 @@ end // initial bht_bank_rd_data_out_1_68 <= 2'h0; end else if (bht_bank_sel_1_4_4) begin if (_T_9481) begin - bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_68 <= io_exu_mp_pkt_bits_hist; end @@ -37658,7 +37660,7 @@ end // initial bht_bank_rd_data_out_1_69 <= 2'h0; end else if (bht_bank_sel_1_4_5) begin if (_T_9490) begin - bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_69 <= io_exu_mp_pkt_bits_hist; end @@ -37669,7 +37671,7 @@ end // initial bht_bank_rd_data_out_1_70 <= 2'h0; end else if (bht_bank_sel_1_4_6) begin if (_T_9499) begin - bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_70 <= io_exu_mp_pkt_bits_hist; end @@ -37680,7 +37682,7 @@ end // initial bht_bank_rd_data_out_1_71 <= 2'h0; end else if (bht_bank_sel_1_4_7) begin if (_T_9508) begin - bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_71 <= io_exu_mp_pkt_bits_hist; end @@ -37691,7 +37693,7 @@ end // initial bht_bank_rd_data_out_1_72 <= 2'h0; end else if (bht_bank_sel_1_4_8) begin if (_T_9517) begin - bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_72 <= io_exu_mp_pkt_bits_hist; end @@ -37702,7 +37704,7 @@ end // initial bht_bank_rd_data_out_1_73 <= 2'h0; end else if (bht_bank_sel_1_4_9) begin if (_T_9526) begin - bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_73 <= io_exu_mp_pkt_bits_hist; end @@ -37713,7 +37715,7 @@ end // initial bht_bank_rd_data_out_1_74 <= 2'h0; end else if (bht_bank_sel_1_4_10) begin if (_T_9535) begin - bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_74 <= io_exu_mp_pkt_bits_hist; end @@ -37724,7 +37726,7 @@ end // initial bht_bank_rd_data_out_1_75 <= 2'h0; end else if (bht_bank_sel_1_4_11) begin if (_T_9544) begin - bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_75 <= io_exu_mp_pkt_bits_hist; end @@ -37735,7 +37737,7 @@ end // initial bht_bank_rd_data_out_1_76 <= 2'h0; end else if (bht_bank_sel_1_4_12) begin if (_T_9553) begin - bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_76 <= io_exu_mp_pkt_bits_hist; end @@ -37746,7 +37748,7 @@ end // initial bht_bank_rd_data_out_1_77 <= 2'h0; end else if (bht_bank_sel_1_4_13) begin if (_T_9562) begin - bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_77 <= io_exu_mp_pkt_bits_hist; end @@ -37757,7 +37759,7 @@ end // initial bht_bank_rd_data_out_1_78 <= 2'h0; end else if (bht_bank_sel_1_4_14) begin if (_T_9571) begin - bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_78 <= io_exu_mp_pkt_bits_hist; end @@ -37768,7 +37770,7 @@ end // initial bht_bank_rd_data_out_1_79 <= 2'h0; end else if (bht_bank_sel_1_4_15) begin if (_T_9580) begin - bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_79 <= io_exu_mp_pkt_bits_hist; end @@ -37779,7 +37781,7 @@ end // initial bht_bank_rd_data_out_1_80 <= 2'h0; end else if (bht_bank_sel_1_5_0) begin if (_T_9589) begin - bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_80 <= io_exu_mp_pkt_bits_hist; end @@ -37790,7 +37792,7 @@ end // initial bht_bank_rd_data_out_1_81 <= 2'h0; end else if (bht_bank_sel_1_5_1) begin if (_T_9598) begin - bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_81 <= io_exu_mp_pkt_bits_hist; end @@ -37801,7 +37803,7 @@ end // initial bht_bank_rd_data_out_1_82 <= 2'h0; end else if (bht_bank_sel_1_5_2) begin if (_T_9607) begin - bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_82 <= io_exu_mp_pkt_bits_hist; end @@ -37812,7 +37814,7 @@ end // initial bht_bank_rd_data_out_1_83 <= 2'h0; end else if (bht_bank_sel_1_5_3) begin if (_T_9616) begin - bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_83 <= io_exu_mp_pkt_bits_hist; end @@ -37823,7 +37825,7 @@ end // initial bht_bank_rd_data_out_1_84 <= 2'h0; end else if (bht_bank_sel_1_5_4) begin if (_T_9625) begin - bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_84 <= io_exu_mp_pkt_bits_hist; end @@ -37834,7 +37836,7 @@ end // initial bht_bank_rd_data_out_1_85 <= 2'h0; end else if (bht_bank_sel_1_5_5) begin if (_T_9634) begin - bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_85 <= io_exu_mp_pkt_bits_hist; end @@ -37845,7 +37847,7 @@ end // initial bht_bank_rd_data_out_1_86 <= 2'h0; end else if (bht_bank_sel_1_5_6) begin if (_T_9643) begin - bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_86 <= io_exu_mp_pkt_bits_hist; end @@ -37856,7 +37858,7 @@ end // initial bht_bank_rd_data_out_1_87 <= 2'h0; end else if (bht_bank_sel_1_5_7) begin if (_T_9652) begin - bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_87 <= io_exu_mp_pkt_bits_hist; end @@ -37867,7 +37869,7 @@ end // initial bht_bank_rd_data_out_1_88 <= 2'h0; end else if (bht_bank_sel_1_5_8) begin if (_T_9661) begin - bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_88 <= io_exu_mp_pkt_bits_hist; end @@ -37878,7 +37880,7 @@ end // initial bht_bank_rd_data_out_1_89 <= 2'h0; end else if (bht_bank_sel_1_5_9) begin if (_T_9670) begin - bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_89 <= io_exu_mp_pkt_bits_hist; end @@ -37889,7 +37891,7 @@ end // initial bht_bank_rd_data_out_1_90 <= 2'h0; end else if (bht_bank_sel_1_5_10) begin if (_T_9679) begin - bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_90 <= io_exu_mp_pkt_bits_hist; end @@ -37900,7 +37902,7 @@ end // initial bht_bank_rd_data_out_1_91 <= 2'h0; end else if (bht_bank_sel_1_5_11) begin if (_T_9688) begin - bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_91 <= io_exu_mp_pkt_bits_hist; end @@ -37911,7 +37913,7 @@ end // initial bht_bank_rd_data_out_1_92 <= 2'h0; end else if (bht_bank_sel_1_5_12) begin if (_T_9697) begin - bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_92 <= io_exu_mp_pkt_bits_hist; end @@ -37922,7 +37924,7 @@ end // initial bht_bank_rd_data_out_1_93 <= 2'h0; end else if (bht_bank_sel_1_5_13) begin if (_T_9706) begin - bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_93 <= io_exu_mp_pkt_bits_hist; end @@ -37933,7 +37935,7 @@ end // initial bht_bank_rd_data_out_1_94 <= 2'h0; end else if (bht_bank_sel_1_5_14) begin if (_T_9715) begin - bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_94 <= io_exu_mp_pkt_bits_hist; end @@ -37944,7 +37946,7 @@ end // initial bht_bank_rd_data_out_1_95 <= 2'h0; end else if (bht_bank_sel_1_5_15) begin if (_T_9724) begin - bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_95 <= io_exu_mp_pkt_bits_hist; end @@ -37955,7 +37957,7 @@ end // initial bht_bank_rd_data_out_1_96 <= 2'h0; end else if (bht_bank_sel_1_6_0) begin if (_T_9733) begin - bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_96 <= io_exu_mp_pkt_bits_hist; end @@ -37966,7 +37968,7 @@ end // initial bht_bank_rd_data_out_1_97 <= 2'h0; end else if (bht_bank_sel_1_6_1) begin if (_T_9742) begin - bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_97 <= io_exu_mp_pkt_bits_hist; end @@ -37977,7 +37979,7 @@ end // initial bht_bank_rd_data_out_1_98 <= 2'h0; end else if (bht_bank_sel_1_6_2) begin if (_T_9751) begin - bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_98 <= io_exu_mp_pkt_bits_hist; end @@ -37988,7 +37990,7 @@ end // initial bht_bank_rd_data_out_1_99 <= 2'h0; end else if (bht_bank_sel_1_6_3) begin if (_T_9760) begin - bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_99 <= io_exu_mp_pkt_bits_hist; end @@ -37999,7 +38001,7 @@ end // initial bht_bank_rd_data_out_1_100 <= 2'h0; end else if (bht_bank_sel_1_6_4) begin if (_T_9769) begin - bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_100 <= io_exu_mp_pkt_bits_hist; end @@ -38010,7 +38012,7 @@ end // initial bht_bank_rd_data_out_1_101 <= 2'h0; end else if (bht_bank_sel_1_6_5) begin if (_T_9778) begin - bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_101 <= io_exu_mp_pkt_bits_hist; end @@ -38021,7 +38023,7 @@ end // initial bht_bank_rd_data_out_1_102 <= 2'h0; end else if (bht_bank_sel_1_6_6) begin if (_T_9787) begin - bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_102 <= io_exu_mp_pkt_bits_hist; end @@ -38032,7 +38034,7 @@ end // initial bht_bank_rd_data_out_1_103 <= 2'h0; end else if (bht_bank_sel_1_6_7) begin if (_T_9796) begin - bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_103 <= io_exu_mp_pkt_bits_hist; end @@ -38043,7 +38045,7 @@ end // initial bht_bank_rd_data_out_1_104 <= 2'h0; end else if (bht_bank_sel_1_6_8) begin if (_T_9805) begin - bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_104 <= io_exu_mp_pkt_bits_hist; end @@ -38054,7 +38056,7 @@ end // initial bht_bank_rd_data_out_1_105 <= 2'h0; end else if (bht_bank_sel_1_6_9) begin if (_T_9814) begin - bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_105 <= io_exu_mp_pkt_bits_hist; end @@ -38065,7 +38067,7 @@ end // initial bht_bank_rd_data_out_1_106 <= 2'h0; end else if (bht_bank_sel_1_6_10) begin if (_T_9823) begin - bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_106 <= io_exu_mp_pkt_bits_hist; end @@ -38076,7 +38078,7 @@ end // initial bht_bank_rd_data_out_1_107 <= 2'h0; end else if (bht_bank_sel_1_6_11) begin if (_T_9832) begin - bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_107 <= io_exu_mp_pkt_bits_hist; end @@ -38087,7 +38089,7 @@ end // initial bht_bank_rd_data_out_1_108 <= 2'h0; end else if (bht_bank_sel_1_6_12) begin if (_T_9841) begin - bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_108 <= io_exu_mp_pkt_bits_hist; end @@ -38098,7 +38100,7 @@ end // initial bht_bank_rd_data_out_1_109 <= 2'h0; end else if (bht_bank_sel_1_6_13) begin if (_T_9850) begin - bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_109 <= io_exu_mp_pkt_bits_hist; end @@ -38109,7 +38111,7 @@ end // initial bht_bank_rd_data_out_1_110 <= 2'h0; end else if (bht_bank_sel_1_6_14) begin if (_T_9859) begin - bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_110 <= io_exu_mp_pkt_bits_hist; end @@ -38120,7 +38122,7 @@ end // initial bht_bank_rd_data_out_1_111 <= 2'h0; end else if (bht_bank_sel_1_6_15) begin if (_T_9868) begin - bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_111 <= io_exu_mp_pkt_bits_hist; end @@ -38131,7 +38133,7 @@ end // initial bht_bank_rd_data_out_1_112 <= 2'h0; end else if (bht_bank_sel_1_7_0) begin if (_T_9877) begin - bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_112 <= io_exu_mp_pkt_bits_hist; end @@ -38142,7 +38144,7 @@ end // initial bht_bank_rd_data_out_1_113 <= 2'h0; end else if (bht_bank_sel_1_7_1) begin if (_T_9886) begin - bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_113 <= io_exu_mp_pkt_bits_hist; end @@ -38153,7 +38155,7 @@ end // initial bht_bank_rd_data_out_1_114 <= 2'h0; end else if (bht_bank_sel_1_7_2) begin if (_T_9895) begin - bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_114 <= io_exu_mp_pkt_bits_hist; end @@ -38164,7 +38166,7 @@ end // initial bht_bank_rd_data_out_1_115 <= 2'h0; end else if (bht_bank_sel_1_7_3) begin if (_T_9904) begin - bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_115 <= io_exu_mp_pkt_bits_hist; end @@ -38175,7 +38177,7 @@ end // initial bht_bank_rd_data_out_1_116 <= 2'h0; end else if (bht_bank_sel_1_7_4) begin if (_T_9913) begin - bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_116 <= io_exu_mp_pkt_bits_hist; end @@ -38186,7 +38188,7 @@ end // initial bht_bank_rd_data_out_1_117 <= 2'h0; end else if (bht_bank_sel_1_7_5) begin if (_T_9922) begin - bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_117 <= io_exu_mp_pkt_bits_hist; end @@ -38197,7 +38199,7 @@ end // initial bht_bank_rd_data_out_1_118 <= 2'h0; end else if (bht_bank_sel_1_7_6) begin if (_T_9931) begin - bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_118 <= io_exu_mp_pkt_bits_hist; end @@ -38208,7 +38210,7 @@ end // initial bht_bank_rd_data_out_1_119 <= 2'h0; end else if (bht_bank_sel_1_7_7) begin if (_T_9940) begin - bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_119 <= io_exu_mp_pkt_bits_hist; end @@ -38219,7 +38221,7 @@ end // initial bht_bank_rd_data_out_1_120 <= 2'h0; end else if (bht_bank_sel_1_7_8) begin if (_T_9949) begin - bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_120 <= io_exu_mp_pkt_bits_hist; end @@ -38230,7 +38232,7 @@ end // initial bht_bank_rd_data_out_1_121 <= 2'h0; end else if (bht_bank_sel_1_7_9) begin if (_T_9958) begin - bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_121 <= io_exu_mp_pkt_bits_hist; end @@ -38241,7 +38243,7 @@ end // initial bht_bank_rd_data_out_1_122 <= 2'h0; end else if (bht_bank_sel_1_7_10) begin if (_T_9967) begin - bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_122 <= io_exu_mp_pkt_bits_hist; end @@ -38252,7 +38254,7 @@ end // initial bht_bank_rd_data_out_1_123 <= 2'h0; end else if (bht_bank_sel_1_7_11) begin if (_T_9976) begin - bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_123 <= io_exu_mp_pkt_bits_hist; end @@ -38263,7 +38265,7 @@ end // initial bht_bank_rd_data_out_1_124 <= 2'h0; end else if (bht_bank_sel_1_7_12) begin if (_T_9985) begin - bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_124 <= io_exu_mp_pkt_bits_hist; end @@ -38274,7 +38276,7 @@ end // initial bht_bank_rd_data_out_1_125 <= 2'h0; end else if (bht_bank_sel_1_7_13) begin if (_T_9994) begin - bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_125 <= io_exu_mp_pkt_bits_hist; end @@ -38285,7 +38287,7 @@ end // initial bht_bank_rd_data_out_1_126 <= 2'h0; end else if (bht_bank_sel_1_7_14) begin if (_T_10003) begin - bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_126 <= io_exu_mp_pkt_bits_hist; end @@ -38296,7 +38298,7 @@ end // initial bht_bank_rd_data_out_1_127 <= 2'h0; end else if (bht_bank_sel_1_7_15) begin if (_T_10012) begin - bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_127 <= io_exu_mp_pkt_bits_hist; end @@ -38307,7 +38309,7 @@ end // initial bht_bank_rd_data_out_1_128 <= 2'h0; end else if (bht_bank_sel_1_8_0) begin if (_T_10021) begin - bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_128 <= io_exu_mp_pkt_bits_hist; end @@ -38318,7 +38320,7 @@ end // initial bht_bank_rd_data_out_1_129 <= 2'h0; end else if (bht_bank_sel_1_8_1) begin if (_T_10030) begin - bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_129 <= io_exu_mp_pkt_bits_hist; end @@ -38329,7 +38331,7 @@ end // initial bht_bank_rd_data_out_1_130 <= 2'h0; end else if (bht_bank_sel_1_8_2) begin if (_T_10039) begin - bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_130 <= io_exu_mp_pkt_bits_hist; end @@ -38340,7 +38342,7 @@ end // initial bht_bank_rd_data_out_1_131 <= 2'h0; end else if (bht_bank_sel_1_8_3) begin if (_T_10048) begin - bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_131 <= io_exu_mp_pkt_bits_hist; end @@ -38351,7 +38353,7 @@ end // initial bht_bank_rd_data_out_1_132 <= 2'h0; end else if (bht_bank_sel_1_8_4) begin if (_T_10057) begin - bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_132 <= io_exu_mp_pkt_bits_hist; end @@ -38362,7 +38364,7 @@ end // initial bht_bank_rd_data_out_1_133 <= 2'h0; end else if (bht_bank_sel_1_8_5) begin if (_T_10066) begin - bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_133 <= io_exu_mp_pkt_bits_hist; end @@ -38373,7 +38375,7 @@ end // initial bht_bank_rd_data_out_1_134 <= 2'h0; end else if (bht_bank_sel_1_8_6) begin if (_T_10075) begin - bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_134 <= io_exu_mp_pkt_bits_hist; end @@ -38384,7 +38386,7 @@ end // initial bht_bank_rd_data_out_1_135 <= 2'h0; end else if (bht_bank_sel_1_8_7) begin if (_T_10084) begin - bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_135 <= io_exu_mp_pkt_bits_hist; end @@ -38395,7 +38397,7 @@ end // initial bht_bank_rd_data_out_1_136 <= 2'h0; end else if (bht_bank_sel_1_8_8) begin if (_T_10093) begin - bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_136 <= io_exu_mp_pkt_bits_hist; end @@ -38406,7 +38408,7 @@ end // initial bht_bank_rd_data_out_1_137 <= 2'h0; end else if (bht_bank_sel_1_8_9) begin if (_T_10102) begin - bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_137 <= io_exu_mp_pkt_bits_hist; end @@ -38417,7 +38419,7 @@ end // initial bht_bank_rd_data_out_1_138 <= 2'h0; end else if (bht_bank_sel_1_8_10) begin if (_T_10111) begin - bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_138 <= io_exu_mp_pkt_bits_hist; end @@ -38428,7 +38430,7 @@ end // initial bht_bank_rd_data_out_1_139 <= 2'h0; end else if (bht_bank_sel_1_8_11) begin if (_T_10120) begin - bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_139 <= io_exu_mp_pkt_bits_hist; end @@ -38439,7 +38441,7 @@ end // initial bht_bank_rd_data_out_1_140 <= 2'h0; end else if (bht_bank_sel_1_8_12) begin if (_T_10129) begin - bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_140 <= io_exu_mp_pkt_bits_hist; end @@ -38450,7 +38452,7 @@ end // initial bht_bank_rd_data_out_1_141 <= 2'h0; end else if (bht_bank_sel_1_8_13) begin if (_T_10138) begin - bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_141 <= io_exu_mp_pkt_bits_hist; end @@ -38461,7 +38463,7 @@ end // initial bht_bank_rd_data_out_1_142 <= 2'h0; end else if (bht_bank_sel_1_8_14) begin if (_T_10147) begin - bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_142 <= io_exu_mp_pkt_bits_hist; end @@ -38472,7 +38474,7 @@ end // initial bht_bank_rd_data_out_1_143 <= 2'h0; end else if (bht_bank_sel_1_8_15) begin if (_T_10156) begin - bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_143 <= io_exu_mp_pkt_bits_hist; end @@ -38483,7 +38485,7 @@ end // initial bht_bank_rd_data_out_1_144 <= 2'h0; end else if (bht_bank_sel_1_9_0) begin if (_T_10165) begin - bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_144 <= io_exu_mp_pkt_bits_hist; end @@ -38494,7 +38496,7 @@ end // initial bht_bank_rd_data_out_1_145 <= 2'h0; end else if (bht_bank_sel_1_9_1) begin if (_T_10174) begin - bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_145 <= io_exu_mp_pkt_bits_hist; end @@ -38505,7 +38507,7 @@ end // initial bht_bank_rd_data_out_1_146 <= 2'h0; end else if (bht_bank_sel_1_9_2) begin if (_T_10183) begin - bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_146 <= io_exu_mp_pkt_bits_hist; end @@ -38516,7 +38518,7 @@ end // initial bht_bank_rd_data_out_1_147 <= 2'h0; end else if (bht_bank_sel_1_9_3) begin if (_T_10192) begin - bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_147 <= io_exu_mp_pkt_bits_hist; end @@ -38527,7 +38529,7 @@ end // initial bht_bank_rd_data_out_1_148 <= 2'h0; end else if (bht_bank_sel_1_9_4) begin if (_T_10201) begin - bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_148 <= io_exu_mp_pkt_bits_hist; end @@ -38538,7 +38540,7 @@ end // initial bht_bank_rd_data_out_1_149 <= 2'h0; end else if (bht_bank_sel_1_9_5) begin if (_T_10210) begin - bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_149 <= io_exu_mp_pkt_bits_hist; end @@ -38549,7 +38551,7 @@ end // initial bht_bank_rd_data_out_1_150 <= 2'h0; end else if (bht_bank_sel_1_9_6) begin if (_T_10219) begin - bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_150 <= io_exu_mp_pkt_bits_hist; end @@ -38560,7 +38562,7 @@ end // initial bht_bank_rd_data_out_1_151 <= 2'h0; end else if (bht_bank_sel_1_9_7) begin if (_T_10228) begin - bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_151 <= io_exu_mp_pkt_bits_hist; end @@ -38571,7 +38573,7 @@ end // initial bht_bank_rd_data_out_1_152 <= 2'h0; end else if (bht_bank_sel_1_9_8) begin if (_T_10237) begin - bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_152 <= io_exu_mp_pkt_bits_hist; end @@ -38582,7 +38584,7 @@ end // initial bht_bank_rd_data_out_1_153 <= 2'h0; end else if (bht_bank_sel_1_9_9) begin if (_T_10246) begin - bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_153 <= io_exu_mp_pkt_bits_hist; end @@ -38593,7 +38595,7 @@ end // initial bht_bank_rd_data_out_1_154 <= 2'h0; end else if (bht_bank_sel_1_9_10) begin if (_T_10255) begin - bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_154 <= io_exu_mp_pkt_bits_hist; end @@ -38604,7 +38606,7 @@ end // initial bht_bank_rd_data_out_1_155 <= 2'h0; end else if (bht_bank_sel_1_9_11) begin if (_T_10264) begin - bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_155 <= io_exu_mp_pkt_bits_hist; end @@ -38615,7 +38617,7 @@ end // initial bht_bank_rd_data_out_1_156 <= 2'h0; end else if (bht_bank_sel_1_9_12) begin if (_T_10273) begin - bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_156 <= io_exu_mp_pkt_bits_hist; end @@ -38626,7 +38628,7 @@ end // initial bht_bank_rd_data_out_1_157 <= 2'h0; end else if (bht_bank_sel_1_9_13) begin if (_T_10282) begin - bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_157 <= io_exu_mp_pkt_bits_hist; end @@ -38637,7 +38639,7 @@ end // initial bht_bank_rd_data_out_1_158 <= 2'h0; end else if (bht_bank_sel_1_9_14) begin if (_T_10291) begin - bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_158 <= io_exu_mp_pkt_bits_hist; end @@ -38648,7 +38650,7 @@ end // initial bht_bank_rd_data_out_1_159 <= 2'h0; end else if (bht_bank_sel_1_9_15) begin if (_T_10300) begin - bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_159 <= io_exu_mp_pkt_bits_hist; end @@ -38659,7 +38661,7 @@ end // initial bht_bank_rd_data_out_1_160 <= 2'h0; end else if (bht_bank_sel_1_10_0) begin if (_T_10309) begin - bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_160 <= io_exu_mp_pkt_bits_hist; end @@ -38670,7 +38672,7 @@ end // initial bht_bank_rd_data_out_1_161 <= 2'h0; end else if (bht_bank_sel_1_10_1) begin if (_T_10318) begin - bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_161 <= io_exu_mp_pkt_bits_hist; end @@ -38681,7 +38683,7 @@ end // initial bht_bank_rd_data_out_1_162 <= 2'h0; end else if (bht_bank_sel_1_10_2) begin if (_T_10327) begin - bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_162 <= io_exu_mp_pkt_bits_hist; end @@ -38692,7 +38694,7 @@ end // initial bht_bank_rd_data_out_1_163 <= 2'h0; end else if (bht_bank_sel_1_10_3) begin if (_T_10336) begin - bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_163 <= io_exu_mp_pkt_bits_hist; end @@ -38703,7 +38705,7 @@ end // initial bht_bank_rd_data_out_1_164 <= 2'h0; end else if (bht_bank_sel_1_10_4) begin if (_T_10345) begin - bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_164 <= io_exu_mp_pkt_bits_hist; end @@ -38714,7 +38716,7 @@ end // initial bht_bank_rd_data_out_1_165 <= 2'h0; end else if (bht_bank_sel_1_10_5) begin if (_T_10354) begin - bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_165 <= io_exu_mp_pkt_bits_hist; end @@ -38725,7 +38727,7 @@ end // initial bht_bank_rd_data_out_1_166 <= 2'h0; end else if (bht_bank_sel_1_10_6) begin if (_T_10363) begin - bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_166 <= io_exu_mp_pkt_bits_hist; end @@ -38736,7 +38738,7 @@ end // initial bht_bank_rd_data_out_1_167 <= 2'h0; end else if (bht_bank_sel_1_10_7) begin if (_T_10372) begin - bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_167 <= io_exu_mp_pkt_bits_hist; end @@ -38747,7 +38749,7 @@ end // initial bht_bank_rd_data_out_1_168 <= 2'h0; end else if (bht_bank_sel_1_10_8) begin if (_T_10381) begin - bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_168 <= io_exu_mp_pkt_bits_hist; end @@ -38758,7 +38760,7 @@ end // initial bht_bank_rd_data_out_1_169 <= 2'h0; end else if (bht_bank_sel_1_10_9) begin if (_T_10390) begin - bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_169 <= io_exu_mp_pkt_bits_hist; end @@ -38769,7 +38771,7 @@ end // initial bht_bank_rd_data_out_1_170 <= 2'h0; end else if (bht_bank_sel_1_10_10) begin if (_T_10399) begin - bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_170 <= io_exu_mp_pkt_bits_hist; end @@ -38780,7 +38782,7 @@ end // initial bht_bank_rd_data_out_1_171 <= 2'h0; end else if (bht_bank_sel_1_10_11) begin if (_T_10408) begin - bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_171 <= io_exu_mp_pkt_bits_hist; end @@ -38791,7 +38793,7 @@ end // initial bht_bank_rd_data_out_1_172 <= 2'h0; end else if (bht_bank_sel_1_10_12) begin if (_T_10417) begin - bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_172 <= io_exu_mp_pkt_bits_hist; end @@ -38802,7 +38804,7 @@ end // initial bht_bank_rd_data_out_1_173 <= 2'h0; end else if (bht_bank_sel_1_10_13) begin if (_T_10426) begin - bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_173 <= io_exu_mp_pkt_bits_hist; end @@ -38813,7 +38815,7 @@ end // initial bht_bank_rd_data_out_1_174 <= 2'h0; end else if (bht_bank_sel_1_10_14) begin if (_T_10435) begin - bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_174 <= io_exu_mp_pkt_bits_hist; end @@ -38824,7 +38826,7 @@ end // initial bht_bank_rd_data_out_1_175 <= 2'h0; end else if (bht_bank_sel_1_10_15) begin if (_T_10444) begin - bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_175 <= io_exu_mp_pkt_bits_hist; end @@ -38835,7 +38837,7 @@ end // initial bht_bank_rd_data_out_1_176 <= 2'h0; end else if (bht_bank_sel_1_11_0) begin if (_T_10453) begin - bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_176 <= io_exu_mp_pkt_bits_hist; end @@ -38846,7 +38848,7 @@ end // initial bht_bank_rd_data_out_1_177 <= 2'h0; end else if (bht_bank_sel_1_11_1) begin if (_T_10462) begin - bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_177 <= io_exu_mp_pkt_bits_hist; end @@ -38857,7 +38859,7 @@ end // initial bht_bank_rd_data_out_1_178 <= 2'h0; end else if (bht_bank_sel_1_11_2) begin if (_T_10471) begin - bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_178 <= io_exu_mp_pkt_bits_hist; end @@ -38868,7 +38870,7 @@ end // initial bht_bank_rd_data_out_1_179 <= 2'h0; end else if (bht_bank_sel_1_11_3) begin if (_T_10480) begin - bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_179 <= io_exu_mp_pkt_bits_hist; end @@ -38879,7 +38881,7 @@ end // initial bht_bank_rd_data_out_1_180 <= 2'h0; end else if (bht_bank_sel_1_11_4) begin if (_T_10489) begin - bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_180 <= io_exu_mp_pkt_bits_hist; end @@ -38890,7 +38892,7 @@ end // initial bht_bank_rd_data_out_1_181 <= 2'h0; end else if (bht_bank_sel_1_11_5) begin if (_T_10498) begin - bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_181 <= io_exu_mp_pkt_bits_hist; end @@ -38901,7 +38903,7 @@ end // initial bht_bank_rd_data_out_1_182 <= 2'h0; end else if (bht_bank_sel_1_11_6) begin if (_T_10507) begin - bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_182 <= io_exu_mp_pkt_bits_hist; end @@ -38912,7 +38914,7 @@ end // initial bht_bank_rd_data_out_1_183 <= 2'h0; end else if (bht_bank_sel_1_11_7) begin if (_T_10516) begin - bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_183 <= io_exu_mp_pkt_bits_hist; end @@ -38923,7 +38925,7 @@ end // initial bht_bank_rd_data_out_1_184 <= 2'h0; end else if (bht_bank_sel_1_11_8) begin if (_T_10525) begin - bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_184 <= io_exu_mp_pkt_bits_hist; end @@ -38934,7 +38936,7 @@ end // initial bht_bank_rd_data_out_1_185 <= 2'h0; end else if (bht_bank_sel_1_11_9) begin if (_T_10534) begin - bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_185 <= io_exu_mp_pkt_bits_hist; end @@ -38945,7 +38947,7 @@ end // initial bht_bank_rd_data_out_1_186 <= 2'h0; end else if (bht_bank_sel_1_11_10) begin if (_T_10543) begin - bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_186 <= io_exu_mp_pkt_bits_hist; end @@ -38956,7 +38958,7 @@ end // initial bht_bank_rd_data_out_1_187 <= 2'h0; end else if (bht_bank_sel_1_11_11) begin if (_T_10552) begin - bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_187 <= io_exu_mp_pkt_bits_hist; end @@ -38967,7 +38969,7 @@ end // initial bht_bank_rd_data_out_1_188 <= 2'h0; end else if (bht_bank_sel_1_11_12) begin if (_T_10561) begin - bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_188 <= io_exu_mp_pkt_bits_hist; end @@ -38978,7 +38980,7 @@ end // initial bht_bank_rd_data_out_1_189 <= 2'h0; end else if (bht_bank_sel_1_11_13) begin if (_T_10570) begin - bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_189 <= io_exu_mp_pkt_bits_hist; end @@ -38989,7 +38991,7 @@ end // initial bht_bank_rd_data_out_1_190 <= 2'h0; end else if (bht_bank_sel_1_11_14) begin if (_T_10579) begin - bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_190 <= io_exu_mp_pkt_bits_hist; end @@ -39000,7 +39002,7 @@ end // initial bht_bank_rd_data_out_1_191 <= 2'h0; end else if (bht_bank_sel_1_11_15) begin if (_T_10588) begin - bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_191 <= io_exu_mp_pkt_bits_hist; end @@ -39011,7 +39013,7 @@ end // initial bht_bank_rd_data_out_1_192 <= 2'h0; end else if (bht_bank_sel_1_12_0) begin if (_T_10597) begin - bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_192 <= io_exu_mp_pkt_bits_hist; end @@ -39022,7 +39024,7 @@ end // initial bht_bank_rd_data_out_1_193 <= 2'h0; end else if (bht_bank_sel_1_12_1) begin if (_T_10606) begin - bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_193 <= io_exu_mp_pkt_bits_hist; end @@ -39033,7 +39035,7 @@ end // initial bht_bank_rd_data_out_1_194 <= 2'h0; end else if (bht_bank_sel_1_12_2) begin if (_T_10615) begin - bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_194 <= io_exu_mp_pkt_bits_hist; end @@ -39044,7 +39046,7 @@ end // initial bht_bank_rd_data_out_1_195 <= 2'h0; end else if (bht_bank_sel_1_12_3) begin if (_T_10624) begin - bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_195 <= io_exu_mp_pkt_bits_hist; end @@ -39055,7 +39057,7 @@ end // initial bht_bank_rd_data_out_1_196 <= 2'h0; end else if (bht_bank_sel_1_12_4) begin if (_T_10633) begin - bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_196 <= io_exu_mp_pkt_bits_hist; end @@ -39066,7 +39068,7 @@ end // initial bht_bank_rd_data_out_1_197 <= 2'h0; end else if (bht_bank_sel_1_12_5) begin if (_T_10642) begin - bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_197 <= io_exu_mp_pkt_bits_hist; end @@ -39077,7 +39079,7 @@ end // initial bht_bank_rd_data_out_1_198 <= 2'h0; end else if (bht_bank_sel_1_12_6) begin if (_T_10651) begin - bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_198 <= io_exu_mp_pkt_bits_hist; end @@ -39088,7 +39090,7 @@ end // initial bht_bank_rd_data_out_1_199 <= 2'h0; end else if (bht_bank_sel_1_12_7) begin if (_T_10660) begin - bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_199 <= io_exu_mp_pkt_bits_hist; end @@ -39099,7 +39101,7 @@ end // initial bht_bank_rd_data_out_1_200 <= 2'h0; end else if (bht_bank_sel_1_12_8) begin if (_T_10669) begin - bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_200 <= io_exu_mp_pkt_bits_hist; end @@ -39110,7 +39112,7 @@ end // initial bht_bank_rd_data_out_1_201 <= 2'h0; end else if (bht_bank_sel_1_12_9) begin if (_T_10678) begin - bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_201 <= io_exu_mp_pkt_bits_hist; end @@ -39121,7 +39123,7 @@ end // initial bht_bank_rd_data_out_1_202 <= 2'h0; end else if (bht_bank_sel_1_12_10) begin if (_T_10687) begin - bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_202 <= io_exu_mp_pkt_bits_hist; end @@ -39132,7 +39134,7 @@ end // initial bht_bank_rd_data_out_1_203 <= 2'h0; end else if (bht_bank_sel_1_12_11) begin if (_T_10696) begin - bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_203 <= io_exu_mp_pkt_bits_hist; end @@ -39143,7 +39145,7 @@ end // initial bht_bank_rd_data_out_1_204 <= 2'h0; end else if (bht_bank_sel_1_12_12) begin if (_T_10705) begin - bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_204 <= io_exu_mp_pkt_bits_hist; end @@ -39154,7 +39156,7 @@ end // initial bht_bank_rd_data_out_1_205 <= 2'h0; end else if (bht_bank_sel_1_12_13) begin if (_T_10714) begin - bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_205 <= io_exu_mp_pkt_bits_hist; end @@ -39165,7 +39167,7 @@ end // initial bht_bank_rd_data_out_1_206 <= 2'h0; end else if (bht_bank_sel_1_12_14) begin if (_T_10723) begin - bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_206 <= io_exu_mp_pkt_bits_hist; end @@ -39176,7 +39178,7 @@ end // initial bht_bank_rd_data_out_1_207 <= 2'h0; end else if (bht_bank_sel_1_12_15) begin if (_T_10732) begin - bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_207 <= io_exu_mp_pkt_bits_hist; end @@ -39187,7 +39189,7 @@ end // initial bht_bank_rd_data_out_1_208 <= 2'h0; end else if (bht_bank_sel_1_13_0) begin if (_T_10741) begin - bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_208 <= io_exu_mp_pkt_bits_hist; end @@ -39198,7 +39200,7 @@ end // initial bht_bank_rd_data_out_1_209 <= 2'h0; end else if (bht_bank_sel_1_13_1) begin if (_T_10750) begin - bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_209 <= io_exu_mp_pkt_bits_hist; end @@ -39209,7 +39211,7 @@ end // initial bht_bank_rd_data_out_1_210 <= 2'h0; end else if (bht_bank_sel_1_13_2) begin if (_T_10759) begin - bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_210 <= io_exu_mp_pkt_bits_hist; end @@ -39220,7 +39222,7 @@ end // initial bht_bank_rd_data_out_1_211 <= 2'h0; end else if (bht_bank_sel_1_13_3) begin if (_T_10768) begin - bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_211 <= io_exu_mp_pkt_bits_hist; end @@ -39231,7 +39233,7 @@ end // initial bht_bank_rd_data_out_1_212 <= 2'h0; end else if (bht_bank_sel_1_13_4) begin if (_T_10777) begin - bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_212 <= io_exu_mp_pkt_bits_hist; end @@ -39242,7 +39244,7 @@ end // initial bht_bank_rd_data_out_1_213 <= 2'h0; end else if (bht_bank_sel_1_13_5) begin if (_T_10786) begin - bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_213 <= io_exu_mp_pkt_bits_hist; end @@ -39253,7 +39255,7 @@ end // initial bht_bank_rd_data_out_1_214 <= 2'h0; end else if (bht_bank_sel_1_13_6) begin if (_T_10795) begin - bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_214 <= io_exu_mp_pkt_bits_hist; end @@ -39264,7 +39266,7 @@ end // initial bht_bank_rd_data_out_1_215 <= 2'h0; end else if (bht_bank_sel_1_13_7) begin if (_T_10804) begin - bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_215 <= io_exu_mp_pkt_bits_hist; end @@ -39275,7 +39277,7 @@ end // initial bht_bank_rd_data_out_1_216 <= 2'h0; end else if (bht_bank_sel_1_13_8) begin if (_T_10813) begin - bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_216 <= io_exu_mp_pkt_bits_hist; end @@ -39286,7 +39288,7 @@ end // initial bht_bank_rd_data_out_1_217 <= 2'h0; end else if (bht_bank_sel_1_13_9) begin if (_T_10822) begin - bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_217 <= io_exu_mp_pkt_bits_hist; end @@ -39297,7 +39299,7 @@ end // initial bht_bank_rd_data_out_1_218 <= 2'h0; end else if (bht_bank_sel_1_13_10) begin if (_T_10831) begin - bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_218 <= io_exu_mp_pkt_bits_hist; end @@ -39308,7 +39310,7 @@ end // initial bht_bank_rd_data_out_1_219 <= 2'h0; end else if (bht_bank_sel_1_13_11) begin if (_T_10840) begin - bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_219 <= io_exu_mp_pkt_bits_hist; end @@ -39319,7 +39321,7 @@ end // initial bht_bank_rd_data_out_1_220 <= 2'h0; end else if (bht_bank_sel_1_13_12) begin if (_T_10849) begin - bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_220 <= io_exu_mp_pkt_bits_hist; end @@ -39330,7 +39332,7 @@ end // initial bht_bank_rd_data_out_1_221 <= 2'h0; end else if (bht_bank_sel_1_13_13) begin if (_T_10858) begin - bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_221 <= io_exu_mp_pkt_bits_hist; end @@ -39341,7 +39343,7 @@ end // initial bht_bank_rd_data_out_1_222 <= 2'h0; end else if (bht_bank_sel_1_13_14) begin if (_T_10867) begin - bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_222 <= io_exu_mp_pkt_bits_hist; end @@ -39352,7 +39354,7 @@ end // initial bht_bank_rd_data_out_1_223 <= 2'h0; end else if (bht_bank_sel_1_13_15) begin if (_T_10876) begin - bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_223 <= io_exu_mp_pkt_bits_hist; end @@ -39363,7 +39365,7 @@ end // initial bht_bank_rd_data_out_1_224 <= 2'h0; end else if (bht_bank_sel_1_14_0) begin if (_T_10885) begin - bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_224 <= io_exu_mp_pkt_bits_hist; end @@ -39374,7 +39376,7 @@ end // initial bht_bank_rd_data_out_1_225 <= 2'h0; end else if (bht_bank_sel_1_14_1) begin if (_T_10894) begin - bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_225 <= io_exu_mp_pkt_bits_hist; end @@ -39385,7 +39387,7 @@ end // initial bht_bank_rd_data_out_1_226 <= 2'h0; end else if (bht_bank_sel_1_14_2) begin if (_T_10903) begin - bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_226 <= io_exu_mp_pkt_bits_hist; end @@ -39396,7 +39398,7 @@ end // initial bht_bank_rd_data_out_1_227 <= 2'h0; end else if (bht_bank_sel_1_14_3) begin if (_T_10912) begin - bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_227 <= io_exu_mp_pkt_bits_hist; end @@ -39407,7 +39409,7 @@ end // initial bht_bank_rd_data_out_1_228 <= 2'h0; end else if (bht_bank_sel_1_14_4) begin if (_T_10921) begin - bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_228 <= io_exu_mp_pkt_bits_hist; end @@ -39418,7 +39420,7 @@ end // initial bht_bank_rd_data_out_1_229 <= 2'h0; end else if (bht_bank_sel_1_14_5) begin if (_T_10930) begin - bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_229 <= io_exu_mp_pkt_bits_hist; end @@ -39429,7 +39431,7 @@ end // initial bht_bank_rd_data_out_1_230 <= 2'h0; end else if (bht_bank_sel_1_14_6) begin if (_T_10939) begin - bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_230 <= io_exu_mp_pkt_bits_hist; end @@ -39440,7 +39442,7 @@ end // initial bht_bank_rd_data_out_1_231 <= 2'h0; end else if (bht_bank_sel_1_14_7) begin if (_T_10948) begin - bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_231 <= io_exu_mp_pkt_bits_hist; end @@ -39451,7 +39453,7 @@ end // initial bht_bank_rd_data_out_1_232 <= 2'h0; end else if (bht_bank_sel_1_14_8) begin if (_T_10957) begin - bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_232 <= io_exu_mp_pkt_bits_hist; end @@ -39462,7 +39464,7 @@ end // initial bht_bank_rd_data_out_1_233 <= 2'h0; end else if (bht_bank_sel_1_14_9) begin if (_T_10966) begin - bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_233 <= io_exu_mp_pkt_bits_hist; end @@ -39473,7 +39475,7 @@ end // initial bht_bank_rd_data_out_1_234 <= 2'h0; end else if (bht_bank_sel_1_14_10) begin if (_T_10975) begin - bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_234 <= io_exu_mp_pkt_bits_hist; end @@ -39484,7 +39486,7 @@ end // initial bht_bank_rd_data_out_1_235 <= 2'h0; end else if (bht_bank_sel_1_14_11) begin if (_T_10984) begin - bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_235 <= io_exu_mp_pkt_bits_hist; end @@ -39495,7 +39497,7 @@ end // initial bht_bank_rd_data_out_1_236 <= 2'h0; end else if (bht_bank_sel_1_14_12) begin if (_T_10993) begin - bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_236 <= io_exu_mp_pkt_bits_hist; end @@ -39506,7 +39508,7 @@ end // initial bht_bank_rd_data_out_1_237 <= 2'h0; end else if (bht_bank_sel_1_14_13) begin if (_T_11002) begin - bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_237 <= io_exu_mp_pkt_bits_hist; end @@ -39517,7 +39519,7 @@ end // initial bht_bank_rd_data_out_1_238 <= 2'h0; end else if (bht_bank_sel_1_14_14) begin if (_T_11011) begin - bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_238 <= io_exu_mp_pkt_bits_hist; end @@ -39528,7 +39530,7 @@ end // initial bht_bank_rd_data_out_1_239 <= 2'h0; end else if (bht_bank_sel_1_14_15) begin if (_T_11020) begin - bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_239 <= io_exu_mp_pkt_bits_hist; end @@ -39539,7 +39541,7 @@ end // initial bht_bank_rd_data_out_1_240 <= 2'h0; end else if (bht_bank_sel_1_15_0) begin if (_T_11029) begin - bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_240 <= io_exu_mp_pkt_bits_hist; end @@ -39550,7 +39552,7 @@ end // initial bht_bank_rd_data_out_1_241 <= 2'h0; end else if (bht_bank_sel_1_15_1) begin if (_T_11038) begin - bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_241 <= io_exu_mp_pkt_bits_hist; end @@ -39561,7 +39563,7 @@ end // initial bht_bank_rd_data_out_1_242 <= 2'h0; end else if (bht_bank_sel_1_15_2) begin if (_T_11047) begin - bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_242 <= io_exu_mp_pkt_bits_hist; end @@ -39572,7 +39574,7 @@ end // initial bht_bank_rd_data_out_1_243 <= 2'h0; end else if (bht_bank_sel_1_15_3) begin if (_T_11056) begin - bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_243 <= io_exu_mp_pkt_bits_hist; end @@ -39583,7 +39585,7 @@ end // initial bht_bank_rd_data_out_1_244 <= 2'h0; end else if (bht_bank_sel_1_15_4) begin if (_T_11065) begin - bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_244 <= io_exu_mp_pkt_bits_hist; end @@ -39594,7 +39596,7 @@ end // initial bht_bank_rd_data_out_1_245 <= 2'h0; end else if (bht_bank_sel_1_15_5) begin if (_T_11074) begin - bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_245 <= io_exu_mp_pkt_bits_hist; end @@ -39605,7 +39607,7 @@ end // initial bht_bank_rd_data_out_1_246 <= 2'h0; end else if (bht_bank_sel_1_15_6) begin if (_T_11083) begin - bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_246 <= io_exu_mp_pkt_bits_hist; end @@ -39616,7 +39618,7 @@ end // initial bht_bank_rd_data_out_1_247 <= 2'h0; end else if (bht_bank_sel_1_15_7) begin if (_T_11092) begin - bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_247 <= io_exu_mp_pkt_bits_hist; end @@ -39627,7 +39629,7 @@ end // initial bht_bank_rd_data_out_1_248 <= 2'h0; end else if (bht_bank_sel_1_15_8) begin if (_T_11101) begin - bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_248 <= io_exu_mp_pkt_bits_hist; end @@ -39638,7 +39640,7 @@ end // initial bht_bank_rd_data_out_1_249 <= 2'h0; end else if (bht_bank_sel_1_15_9) begin if (_T_11110) begin - bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_249 <= io_exu_mp_pkt_bits_hist; end @@ -39649,7 +39651,7 @@ end // initial bht_bank_rd_data_out_1_250 <= 2'h0; end else if (bht_bank_sel_1_15_10) begin if (_T_11119) begin - bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_250 <= io_exu_mp_pkt_bits_hist; end @@ -39660,7 +39662,7 @@ end // initial bht_bank_rd_data_out_1_251 <= 2'h0; end else if (bht_bank_sel_1_15_11) begin if (_T_11128) begin - bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_251 <= io_exu_mp_pkt_bits_hist; end @@ -39671,7 +39673,7 @@ end // initial bht_bank_rd_data_out_1_252 <= 2'h0; end else if (bht_bank_sel_1_15_12) begin if (_T_11137) begin - bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_252 <= io_exu_mp_pkt_bits_hist; end @@ -39682,7 +39684,7 @@ end // initial bht_bank_rd_data_out_1_253 <= 2'h0; end else if (bht_bank_sel_1_15_13) begin if (_T_11146) begin - bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_253 <= io_exu_mp_pkt_bits_hist; end @@ -39693,7 +39695,7 @@ end // initial bht_bank_rd_data_out_1_254 <= 2'h0; end else if (bht_bank_sel_1_15_14) begin if (_T_11155) begin - bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_254 <= io_exu_mp_pkt_bits_hist; end @@ -39704,7 +39706,7 @@ end // initial bht_bank_rd_data_out_1_255 <= 2'h0; end else if (bht_bank_sel_1_15_15) begin if (_T_11164) begin - bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_255 <= io_exu_mp_pkt_bits_hist; end @@ -39715,7 +39717,7 @@ end // initial bht_bank_rd_data_out_0_0 <= 2'h0; end else if (bht_bank_sel_0_0_0) begin if (_T_6565) begin - bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_0 <= io_exu_mp_pkt_bits_hist; end @@ -39726,7 +39728,7 @@ end // initial bht_bank_rd_data_out_0_1 <= 2'h0; end else if (bht_bank_sel_0_0_1) begin if (_T_6574) begin - bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_1 <= io_exu_mp_pkt_bits_hist; end @@ -39737,7 +39739,7 @@ end // initial bht_bank_rd_data_out_0_2 <= 2'h0; end else if (bht_bank_sel_0_0_2) begin if (_T_6583) begin - bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_2 <= io_exu_mp_pkt_bits_hist; end @@ -39748,7 +39750,7 @@ end // initial bht_bank_rd_data_out_0_3 <= 2'h0; end else if (bht_bank_sel_0_0_3) begin if (_T_6592) begin - bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_3 <= io_exu_mp_pkt_bits_hist; end @@ -39759,7 +39761,7 @@ end // initial bht_bank_rd_data_out_0_4 <= 2'h0; end else if (bht_bank_sel_0_0_4) begin if (_T_6601) begin - bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_4 <= io_exu_mp_pkt_bits_hist; end @@ -39770,7 +39772,7 @@ end // initial bht_bank_rd_data_out_0_5 <= 2'h0; end else if (bht_bank_sel_0_0_5) begin if (_T_6610) begin - bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_5 <= io_exu_mp_pkt_bits_hist; end @@ -39781,7 +39783,7 @@ end // initial bht_bank_rd_data_out_0_6 <= 2'h0; end else if (bht_bank_sel_0_0_6) begin if (_T_6619) begin - bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_6 <= io_exu_mp_pkt_bits_hist; end @@ -39792,7 +39794,7 @@ end // initial bht_bank_rd_data_out_0_7 <= 2'h0; end else if (bht_bank_sel_0_0_7) begin if (_T_6628) begin - bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_7 <= io_exu_mp_pkt_bits_hist; end @@ -39803,7 +39805,7 @@ end // initial bht_bank_rd_data_out_0_8 <= 2'h0; end else if (bht_bank_sel_0_0_8) begin if (_T_6637) begin - bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_8 <= io_exu_mp_pkt_bits_hist; end @@ -39814,7 +39816,7 @@ end // initial bht_bank_rd_data_out_0_9 <= 2'h0; end else if (bht_bank_sel_0_0_9) begin if (_T_6646) begin - bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_9 <= io_exu_mp_pkt_bits_hist; end @@ -39825,7 +39827,7 @@ end // initial bht_bank_rd_data_out_0_10 <= 2'h0; end else if (bht_bank_sel_0_0_10) begin if (_T_6655) begin - bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_10 <= io_exu_mp_pkt_bits_hist; end @@ -39836,7 +39838,7 @@ end // initial bht_bank_rd_data_out_0_11 <= 2'h0; end else if (bht_bank_sel_0_0_11) begin if (_T_6664) begin - bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_11 <= io_exu_mp_pkt_bits_hist; end @@ -39847,7 +39849,7 @@ end // initial bht_bank_rd_data_out_0_12 <= 2'h0; end else if (bht_bank_sel_0_0_12) begin if (_T_6673) begin - bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_12 <= io_exu_mp_pkt_bits_hist; end @@ -39858,7 +39860,7 @@ end // initial bht_bank_rd_data_out_0_13 <= 2'h0; end else if (bht_bank_sel_0_0_13) begin if (_T_6682) begin - bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_13 <= io_exu_mp_pkt_bits_hist; end @@ -39869,7 +39871,7 @@ end // initial bht_bank_rd_data_out_0_14 <= 2'h0; end else if (bht_bank_sel_0_0_14) begin if (_T_6691) begin - bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_14 <= io_exu_mp_pkt_bits_hist; end @@ -39880,7 +39882,7 @@ end // initial bht_bank_rd_data_out_0_15 <= 2'h0; end else if (bht_bank_sel_0_0_15) begin if (_T_6700) begin - bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_15 <= io_exu_mp_pkt_bits_hist; end @@ -39891,7 +39893,7 @@ end // initial bht_bank_rd_data_out_0_16 <= 2'h0; end else if (bht_bank_sel_0_1_0) begin if (_T_6709) begin - bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_16 <= io_exu_mp_pkt_bits_hist; end @@ -39902,7 +39904,7 @@ end // initial bht_bank_rd_data_out_0_17 <= 2'h0; end else if (bht_bank_sel_0_1_1) begin if (_T_6718) begin - bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_17 <= io_exu_mp_pkt_bits_hist; end @@ -39913,7 +39915,7 @@ end // initial bht_bank_rd_data_out_0_18 <= 2'h0; end else if (bht_bank_sel_0_1_2) begin if (_T_6727) begin - bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_18 <= io_exu_mp_pkt_bits_hist; end @@ -39924,7 +39926,7 @@ end // initial bht_bank_rd_data_out_0_19 <= 2'h0; end else if (bht_bank_sel_0_1_3) begin if (_T_6736) begin - bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_19 <= io_exu_mp_pkt_bits_hist; end @@ -39935,7 +39937,7 @@ end // initial bht_bank_rd_data_out_0_20 <= 2'h0; end else if (bht_bank_sel_0_1_4) begin if (_T_6745) begin - bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_20 <= io_exu_mp_pkt_bits_hist; end @@ -39946,7 +39948,7 @@ end // initial bht_bank_rd_data_out_0_21 <= 2'h0; end else if (bht_bank_sel_0_1_5) begin if (_T_6754) begin - bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_21 <= io_exu_mp_pkt_bits_hist; end @@ -39957,7 +39959,7 @@ end // initial bht_bank_rd_data_out_0_22 <= 2'h0; end else if (bht_bank_sel_0_1_6) begin if (_T_6763) begin - bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_22 <= io_exu_mp_pkt_bits_hist; end @@ -39968,7 +39970,7 @@ end // initial bht_bank_rd_data_out_0_23 <= 2'h0; end else if (bht_bank_sel_0_1_7) begin if (_T_6772) begin - bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_23 <= io_exu_mp_pkt_bits_hist; end @@ -39979,7 +39981,7 @@ end // initial bht_bank_rd_data_out_0_24 <= 2'h0; end else if (bht_bank_sel_0_1_8) begin if (_T_6781) begin - bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_24 <= io_exu_mp_pkt_bits_hist; end @@ -39990,7 +39992,7 @@ end // initial bht_bank_rd_data_out_0_25 <= 2'h0; end else if (bht_bank_sel_0_1_9) begin if (_T_6790) begin - bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_25 <= io_exu_mp_pkt_bits_hist; end @@ -40001,7 +40003,7 @@ end // initial bht_bank_rd_data_out_0_26 <= 2'h0; end else if (bht_bank_sel_0_1_10) begin if (_T_6799) begin - bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_26 <= io_exu_mp_pkt_bits_hist; end @@ -40012,7 +40014,7 @@ end // initial bht_bank_rd_data_out_0_27 <= 2'h0; end else if (bht_bank_sel_0_1_11) begin if (_T_6808) begin - bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_27 <= io_exu_mp_pkt_bits_hist; end @@ -40023,7 +40025,7 @@ end // initial bht_bank_rd_data_out_0_28 <= 2'h0; end else if (bht_bank_sel_0_1_12) begin if (_T_6817) begin - bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_28 <= io_exu_mp_pkt_bits_hist; end @@ -40034,7 +40036,7 @@ end // initial bht_bank_rd_data_out_0_29 <= 2'h0; end else if (bht_bank_sel_0_1_13) begin if (_T_6826) begin - bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_29 <= io_exu_mp_pkt_bits_hist; end @@ -40045,7 +40047,7 @@ end // initial bht_bank_rd_data_out_0_30 <= 2'h0; end else if (bht_bank_sel_0_1_14) begin if (_T_6835) begin - bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_30 <= io_exu_mp_pkt_bits_hist; end @@ -40056,7 +40058,7 @@ end // initial bht_bank_rd_data_out_0_31 <= 2'h0; end else if (bht_bank_sel_0_1_15) begin if (_T_6844) begin - bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_31 <= io_exu_mp_pkt_bits_hist; end @@ -40067,7 +40069,7 @@ end // initial bht_bank_rd_data_out_0_32 <= 2'h0; end else if (bht_bank_sel_0_2_0) begin if (_T_6853) begin - bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_32 <= io_exu_mp_pkt_bits_hist; end @@ -40078,7 +40080,7 @@ end // initial bht_bank_rd_data_out_0_33 <= 2'h0; end else if (bht_bank_sel_0_2_1) begin if (_T_6862) begin - bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_33 <= io_exu_mp_pkt_bits_hist; end @@ -40089,7 +40091,7 @@ end // initial bht_bank_rd_data_out_0_34 <= 2'h0; end else if (bht_bank_sel_0_2_2) begin if (_T_6871) begin - bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_34 <= io_exu_mp_pkt_bits_hist; end @@ -40100,7 +40102,7 @@ end // initial bht_bank_rd_data_out_0_35 <= 2'h0; end else if (bht_bank_sel_0_2_3) begin if (_T_6880) begin - bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_35 <= io_exu_mp_pkt_bits_hist; end @@ -40111,7 +40113,7 @@ end // initial bht_bank_rd_data_out_0_36 <= 2'h0; end else if (bht_bank_sel_0_2_4) begin if (_T_6889) begin - bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_36 <= io_exu_mp_pkt_bits_hist; end @@ -40122,7 +40124,7 @@ end // initial bht_bank_rd_data_out_0_37 <= 2'h0; end else if (bht_bank_sel_0_2_5) begin if (_T_6898) begin - bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_37 <= io_exu_mp_pkt_bits_hist; end @@ -40133,7 +40135,7 @@ end // initial bht_bank_rd_data_out_0_38 <= 2'h0; end else if (bht_bank_sel_0_2_6) begin if (_T_6907) begin - bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_38 <= io_exu_mp_pkt_bits_hist; end @@ -40144,7 +40146,7 @@ end // initial bht_bank_rd_data_out_0_39 <= 2'h0; end else if (bht_bank_sel_0_2_7) begin if (_T_6916) begin - bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_39 <= io_exu_mp_pkt_bits_hist; end @@ -40155,7 +40157,7 @@ end // initial bht_bank_rd_data_out_0_40 <= 2'h0; end else if (bht_bank_sel_0_2_8) begin if (_T_6925) begin - bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_40 <= io_exu_mp_pkt_bits_hist; end @@ -40166,7 +40168,7 @@ end // initial bht_bank_rd_data_out_0_41 <= 2'h0; end else if (bht_bank_sel_0_2_9) begin if (_T_6934) begin - bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_41 <= io_exu_mp_pkt_bits_hist; end @@ -40177,7 +40179,7 @@ end // initial bht_bank_rd_data_out_0_42 <= 2'h0; end else if (bht_bank_sel_0_2_10) begin if (_T_6943) begin - bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_42 <= io_exu_mp_pkt_bits_hist; end @@ -40188,7 +40190,7 @@ end // initial bht_bank_rd_data_out_0_43 <= 2'h0; end else if (bht_bank_sel_0_2_11) begin if (_T_6952) begin - bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_43 <= io_exu_mp_pkt_bits_hist; end @@ -40199,7 +40201,7 @@ end // initial bht_bank_rd_data_out_0_44 <= 2'h0; end else if (bht_bank_sel_0_2_12) begin if (_T_6961) begin - bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_44 <= io_exu_mp_pkt_bits_hist; end @@ -40210,7 +40212,7 @@ end // initial bht_bank_rd_data_out_0_45 <= 2'h0; end else if (bht_bank_sel_0_2_13) begin if (_T_6970) begin - bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_45 <= io_exu_mp_pkt_bits_hist; end @@ -40221,7 +40223,7 @@ end // initial bht_bank_rd_data_out_0_46 <= 2'h0; end else if (bht_bank_sel_0_2_14) begin if (_T_6979) begin - bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_46 <= io_exu_mp_pkt_bits_hist; end @@ -40232,7 +40234,7 @@ end // initial bht_bank_rd_data_out_0_47 <= 2'h0; end else if (bht_bank_sel_0_2_15) begin if (_T_6988) begin - bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_47 <= io_exu_mp_pkt_bits_hist; end @@ -40243,7 +40245,7 @@ end // initial bht_bank_rd_data_out_0_48 <= 2'h0; end else if (bht_bank_sel_0_3_0) begin if (_T_6997) begin - bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_48 <= io_exu_mp_pkt_bits_hist; end @@ -40254,7 +40256,7 @@ end // initial bht_bank_rd_data_out_0_49 <= 2'h0; end else if (bht_bank_sel_0_3_1) begin if (_T_7006) begin - bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_49 <= io_exu_mp_pkt_bits_hist; end @@ -40265,7 +40267,7 @@ end // initial bht_bank_rd_data_out_0_50 <= 2'h0; end else if (bht_bank_sel_0_3_2) begin if (_T_7015) begin - bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_50 <= io_exu_mp_pkt_bits_hist; end @@ -40276,7 +40278,7 @@ end // initial bht_bank_rd_data_out_0_51 <= 2'h0; end else if (bht_bank_sel_0_3_3) begin if (_T_7024) begin - bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_51 <= io_exu_mp_pkt_bits_hist; end @@ -40287,7 +40289,7 @@ end // initial bht_bank_rd_data_out_0_52 <= 2'h0; end else if (bht_bank_sel_0_3_4) begin if (_T_7033) begin - bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_52 <= io_exu_mp_pkt_bits_hist; end @@ -40298,7 +40300,7 @@ end // initial bht_bank_rd_data_out_0_53 <= 2'h0; end else if (bht_bank_sel_0_3_5) begin if (_T_7042) begin - bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_53 <= io_exu_mp_pkt_bits_hist; end @@ -40309,7 +40311,7 @@ end // initial bht_bank_rd_data_out_0_54 <= 2'h0; end else if (bht_bank_sel_0_3_6) begin if (_T_7051) begin - bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_54 <= io_exu_mp_pkt_bits_hist; end @@ -40320,7 +40322,7 @@ end // initial bht_bank_rd_data_out_0_55 <= 2'h0; end else if (bht_bank_sel_0_3_7) begin if (_T_7060) begin - bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_55 <= io_exu_mp_pkt_bits_hist; end @@ -40331,7 +40333,7 @@ end // initial bht_bank_rd_data_out_0_56 <= 2'h0; end else if (bht_bank_sel_0_3_8) begin if (_T_7069) begin - bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_56 <= io_exu_mp_pkt_bits_hist; end @@ -40342,7 +40344,7 @@ end // initial bht_bank_rd_data_out_0_57 <= 2'h0; end else if (bht_bank_sel_0_3_9) begin if (_T_7078) begin - bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_57 <= io_exu_mp_pkt_bits_hist; end @@ -40353,7 +40355,7 @@ end // initial bht_bank_rd_data_out_0_58 <= 2'h0; end else if (bht_bank_sel_0_3_10) begin if (_T_7087) begin - bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_58 <= io_exu_mp_pkt_bits_hist; end @@ -40364,7 +40366,7 @@ end // initial bht_bank_rd_data_out_0_59 <= 2'h0; end else if (bht_bank_sel_0_3_11) begin if (_T_7096) begin - bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_59 <= io_exu_mp_pkt_bits_hist; end @@ -40375,7 +40377,7 @@ end // initial bht_bank_rd_data_out_0_60 <= 2'h0; end else if (bht_bank_sel_0_3_12) begin if (_T_7105) begin - bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_60 <= io_exu_mp_pkt_bits_hist; end @@ -40386,7 +40388,7 @@ end // initial bht_bank_rd_data_out_0_61 <= 2'h0; end else if (bht_bank_sel_0_3_13) begin if (_T_7114) begin - bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_61 <= io_exu_mp_pkt_bits_hist; end @@ -40397,7 +40399,7 @@ end // initial bht_bank_rd_data_out_0_62 <= 2'h0; end else if (bht_bank_sel_0_3_14) begin if (_T_7123) begin - bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_62 <= io_exu_mp_pkt_bits_hist; end @@ -40408,7 +40410,7 @@ end // initial bht_bank_rd_data_out_0_63 <= 2'h0; end else if (bht_bank_sel_0_3_15) begin if (_T_7132) begin - bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_63 <= io_exu_mp_pkt_bits_hist; end @@ -40419,7 +40421,7 @@ end // initial bht_bank_rd_data_out_0_64 <= 2'h0; end else if (bht_bank_sel_0_4_0) begin if (_T_7141) begin - bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_64 <= io_exu_mp_pkt_bits_hist; end @@ -40430,7 +40432,7 @@ end // initial bht_bank_rd_data_out_0_65 <= 2'h0; end else if (bht_bank_sel_0_4_1) begin if (_T_7150) begin - bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_65 <= io_exu_mp_pkt_bits_hist; end @@ -40441,7 +40443,7 @@ end // initial bht_bank_rd_data_out_0_66 <= 2'h0; end else if (bht_bank_sel_0_4_2) begin if (_T_7159) begin - bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_66 <= io_exu_mp_pkt_bits_hist; end @@ -40452,7 +40454,7 @@ end // initial bht_bank_rd_data_out_0_67 <= 2'h0; end else if (bht_bank_sel_0_4_3) begin if (_T_7168) begin - bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_67 <= io_exu_mp_pkt_bits_hist; end @@ -40463,7 +40465,7 @@ end // initial bht_bank_rd_data_out_0_68 <= 2'h0; end else if (bht_bank_sel_0_4_4) begin if (_T_7177) begin - bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_68 <= io_exu_mp_pkt_bits_hist; end @@ -40474,7 +40476,7 @@ end // initial bht_bank_rd_data_out_0_69 <= 2'h0; end else if (bht_bank_sel_0_4_5) begin if (_T_7186) begin - bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_69 <= io_exu_mp_pkt_bits_hist; end @@ -40485,7 +40487,7 @@ end // initial bht_bank_rd_data_out_0_70 <= 2'h0; end else if (bht_bank_sel_0_4_6) begin if (_T_7195) begin - bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_70 <= io_exu_mp_pkt_bits_hist; end @@ -40496,7 +40498,7 @@ end // initial bht_bank_rd_data_out_0_71 <= 2'h0; end else if (bht_bank_sel_0_4_7) begin if (_T_7204) begin - bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_71 <= io_exu_mp_pkt_bits_hist; end @@ -40507,7 +40509,7 @@ end // initial bht_bank_rd_data_out_0_72 <= 2'h0; end else if (bht_bank_sel_0_4_8) begin if (_T_7213) begin - bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_72 <= io_exu_mp_pkt_bits_hist; end @@ -40518,7 +40520,7 @@ end // initial bht_bank_rd_data_out_0_73 <= 2'h0; end else if (bht_bank_sel_0_4_9) begin if (_T_7222) begin - bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_73 <= io_exu_mp_pkt_bits_hist; end @@ -40529,7 +40531,7 @@ end // initial bht_bank_rd_data_out_0_74 <= 2'h0; end else if (bht_bank_sel_0_4_10) begin if (_T_7231) begin - bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_74 <= io_exu_mp_pkt_bits_hist; end @@ -40540,7 +40542,7 @@ end // initial bht_bank_rd_data_out_0_75 <= 2'h0; end else if (bht_bank_sel_0_4_11) begin if (_T_7240) begin - bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_75 <= io_exu_mp_pkt_bits_hist; end @@ -40551,7 +40553,7 @@ end // initial bht_bank_rd_data_out_0_76 <= 2'h0; end else if (bht_bank_sel_0_4_12) begin if (_T_7249) begin - bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_76 <= io_exu_mp_pkt_bits_hist; end @@ -40562,7 +40564,7 @@ end // initial bht_bank_rd_data_out_0_77 <= 2'h0; end else if (bht_bank_sel_0_4_13) begin if (_T_7258) begin - bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_77 <= io_exu_mp_pkt_bits_hist; end @@ -40573,7 +40575,7 @@ end // initial bht_bank_rd_data_out_0_78 <= 2'h0; end else if (bht_bank_sel_0_4_14) begin if (_T_7267) begin - bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_78 <= io_exu_mp_pkt_bits_hist; end @@ -40584,7 +40586,7 @@ end // initial bht_bank_rd_data_out_0_79 <= 2'h0; end else if (bht_bank_sel_0_4_15) begin if (_T_7276) begin - bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_79 <= io_exu_mp_pkt_bits_hist; end @@ -40595,7 +40597,7 @@ end // initial bht_bank_rd_data_out_0_80 <= 2'h0; end else if (bht_bank_sel_0_5_0) begin if (_T_7285) begin - bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_80 <= io_exu_mp_pkt_bits_hist; end @@ -40606,7 +40608,7 @@ end // initial bht_bank_rd_data_out_0_81 <= 2'h0; end else if (bht_bank_sel_0_5_1) begin if (_T_7294) begin - bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_81 <= io_exu_mp_pkt_bits_hist; end @@ -40617,7 +40619,7 @@ end // initial bht_bank_rd_data_out_0_82 <= 2'h0; end else if (bht_bank_sel_0_5_2) begin if (_T_7303) begin - bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_82 <= io_exu_mp_pkt_bits_hist; end @@ -40628,7 +40630,7 @@ end // initial bht_bank_rd_data_out_0_83 <= 2'h0; end else if (bht_bank_sel_0_5_3) begin if (_T_7312) begin - bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_83 <= io_exu_mp_pkt_bits_hist; end @@ -40639,7 +40641,7 @@ end // initial bht_bank_rd_data_out_0_84 <= 2'h0; end else if (bht_bank_sel_0_5_4) begin if (_T_7321) begin - bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_84 <= io_exu_mp_pkt_bits_hist; end @@ -40650,7 +40652,7 @@ end // initial bht_bank_rd_data_out_0_85 <= 2'h0; end else if (bht_bank_sel_0_5_5) begin if (_T_7330) begin - bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_85 <= io_exu_mp_pkt_bits_hist; end @@ -40661,7 +40663,7 @@ end // initial bht_bank_rd_data_out_0_86 <= 2'h0; end else if (bht_bank_sel_0_5_6) begin if (_T_7339) begin - bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_86 <= io_exu_mp_pkt_bits_hist; end @@ -40672,7 +40674,7 @@ end // initial bht_bank_rd_data_out_0_87 <= 2'h0; end else if (bht_bank_sel_0_5_7) begin if (_T_7348) begin - bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_87 <= io_exu_mp_pkt_bits_hist; end @@ -40683,7 +40685,7 @@ end // initial bht_bank_rd_data_out_0_88 <= 2'h0; end else if (bht_bank_sel_0_5_8) begin if (_T_7357) begin - bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_88 <= io_exu_mp_pkt_bits_hist; end @@ -40694,7 +40696,7 @@ end // initial bht_bank_rd_data_out_0_89 <= 2'h0; end else if (bht_bank_sel_0_5_9) begin if (_T_7366) begin - bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_89 <= io_exu_mp_pkt_bits_hist; end @@ -40705,7 +40707,7 @@ end // initial bht_bank_rd_data_out_0_90 <= 2'h0; end else if (bht_bank_sel_0_5_10) begin if (_T_7375) begin - bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_90 <= io_exu_mp_pkt_bits_hist; end @@ -40716,7 +40718,7 @@ end // initial bht_bank_rd_data_out_0_91 <= 2'h0; end else if (bht_bank_sel_0_5_11) begin if (_T_7384) begin - bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_91 <= io_exu_mp_pkt_bits_hist; end @@ -40727,7 +40729,7 @@ end // initial bht_bank_rd_data_out_0_92 <= 2'h0; end else if (bht_bank_sel_0_5_12) begin if (_T_7393) begin - bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_92 <= io_exu_mp_pkt_bits_hist; end @@ -40738,7 +40740,7 @@ end // initial bht_bank_rd_data_out_0_93 <= 2'h0; end else if (bht_bank_sel_0_5_13) begin if (_T_7402) begin - bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_93 <= io_exu_mp_pkt_bits_hist; end @@ -40749,7 +40751,7 @@ end // initial bht_bank_rd_data_out_0_94 <= 2'h0; end else if (bht_bank_sel_0_5_14) begin if (_T_7411) begin - bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_94 <= io_exu_mp_pkt_bits_hist; end @@ -40760,7 +40762,7 @@ end // initial bht_bank_rd_data_out_0_95 <= 2'h0; end else if (bht_bank_sel_0_5_15) begin if (_T_7420) begin - bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_95 <= io_exu_mp_pkt_bits_hist; end @@ -40771,7 +40773,7 @@ end // initial bht_bank_rd_data_out_0_96 <= 2'h0; end else if (bht_bank_sel_0_6_0) begin if (_T_7429) begin - bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_96 <= io_exu_mp_pkt_bits_hist; end @@ -40782,7 +40784,7 @@ end // initial bht_bank_rd_data_out_0_97 <= 2'h0; end else if (bht_bank_sel_0_6_1) begin if (_T_7438) begin - bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_97 <= io_exu_mp_pkt_bits_hist; end @@ -40793,7 +40795,7 @@ end // initial bht_bank_rd_data_out_0_98 <= 2'h0; end else if (bht_bank_sel_0_6_2) begin if (_T_7447) begin - bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_98 <= io_exu_mp_pkt_bits_hist; end @@ -40804,7 +40806,7 @@ end // initial bht_bank_rd_data_out_0_99 <= 2'h0; end else if (bht_bank_sel_0_6_3) begin if (_T_7456) begin - bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_99 <= io_exu_mp_pkt_bits_hist; end @@ -40815,7 +40817,7 @@ end // initial bht_bank_rd_data_out_0_100 <= 2'h0; end else if (bht_bank_sel_0_6_4) begin if (_T_7465) begin - bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_100 <= io_exu_mp_pkt_bits_hist; end @@ -40826,7 +40828,7 @@ end // initial bht_bank_rd_data_out_0_101 <= 2'h0; end else if (bht_bank_sel_0_6_5) begin if (_T_7474) begin - bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_101 <= io_exu_mp_pkt_bits_hist; end @@ -40837,7 +40839,7 @@ end // initial bht_bank_rd_data_out_0_102 <= 2'h0; end else if (bht_bank_sel_0_6_6) begin if (_T_7483) begin - bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_102 <= io_exu_mp_pkt_bits_hist; end @@ -40848,7 +40850,7 @@ end // initial bht_bank_rd_data_out_0_103 <= 2'h0; end else if (bht_bank_sel_0_6_7) begin if (_T_7492) begin - bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_103 <= io_exu_mp_pkt_bits_hist; end @@ -40859,7 +40861,7 @@ end // initial bht_bank_rd_data_out_0_104 <= 2'h0; end else if (bht_bank_sel_0_6_8) begin if (_T_7501) begin - bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_104 <= io_exu_mp_pkt_bits_hist; end @@ -40870,7 +40872,7 @@ end // initial bht_bank_rd_data_out_0_105 <= 2'h0; end else if (bht_bank_sel_0_6_9) begin if (_T_7510) begin - bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_105 <= io_exu_mp_pkt_bits_hist; end @@ -40881,7 +40883,7 @@ end // initial bht_bank_rd_data_out_0_106 <= 2'h0; end else if (bht_bank_sel_0_6_10) begin if (_T_7519) begin - bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_106 <= io_exu_mp_pkt_bits_hist; end @@ -40892,7 +40894,7 @@ end // initial bht_bank_rd_data_out_0_107 <= 2'h0; end else if (bht_bank_sel_0_6_11) begin if (_T_7528) begin - bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_107 <= io_exu_mp_pkt_bits_hist; end @@ -40903,7 +40905,7 @@ end // initial bht_bank_rd_data_out_0_108 <= 2'h0; end else if (bht_bank_sel_0_6_12) begin if (_T_7537) begin - bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_108 <= io_exu_mp_pkt_bits_hist; end @@ -40914,7 +40916,7 @@ end // initial bht_bank_rd_data_out_0_109 <= 2'h0; end else if (bht_bank_sel_0_6_13) begin if (_T_7546) begin - bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_109 <= io_exu_mp_pkt_bits_hist; end @@ -40925,7 +40927,7 @@ end // initial bht_bank_rd_data_out_0_110 <= 2'h0; end else if (bht_bank_sel_0_6_14) begin if (_T_7555) begin - bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_110 <= io_exu_mp_pkt_bits_hist; end @@ -40936,7 +40938,7 @@ end // initial bht_bank_rd_data_out_0_111 <= 2'h0; end else if (bht_bank_sel_0_6_15) begin if (_T_7564) begin - bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_111 <= io_exu_mp_pkt_bits_hist; end @@ -40947,7 +40949,7 @@ end // initial bht_bank_rd_data_out_0_112 <= 2'h0; end else if (bht_bank_sel_0_7_0) begin if (_T_7573) begin - bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_112 <= io_exu_mp_pkt_bits_hist; end @@ -40958,7 +40960,7 @@ end // initial bht_bank_rd_data_out_0_113 <= 2'h0; end else if (bht_bank_sel_0_7_1) begin if (_T_7582) begin - bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_113 <= io_exu_mp_pkt_bits_hist; end @@ -40969,7 +40971,7 @@ end // initial bht_bank_rd_data_out_0_114 <= 2'h0; end else if (bht_bank_sel_0_7_2) begin if (_T_7591) begin - bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_114 <= io_exu_mp_pkt_bits_hist; end @@ -40980,7 +40982,7 @@ end // initial bht_bank_rd_data_out_0_115 <= 2'h0; end else if (bht_bank_sel_0_7_3) begin if (_T_7600) begin - bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_115 <= io_exu_mp_pkt_bits_hist; end @@ -40991,7 +40993,7 @@ end // initial bht_bank_rd_data_out_0_116 <= 2'h0; end else if (bht_bank_sel_0_7_4) begin if (_T_7609) begin - bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_116 <= io_exu_mp_pkt_bits_hist; end @@ -41002,7 +41004,7 @@ end // initial bht_bank_rd_data_out_0_117 <= 2'h0; end else if (bht_bank_sel_0_7_5) begin if (_T_7618) begin - bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_117 <= io_exu_mp_pkt_bits_hist; end @@ -41013,7 +41015,7 @@ end // initial bht_bank_rd_data_out_0_118 <= 2'h0; end else if (bht_bank_sel_0_7_6) begin if (_T_7627) begin - bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_118 <= io_exu_mp_pkt_bits_hist; end @@ -41024,7 +41026,7 @@ end // initial bht_bank_rd_data_out_0_119 <= 2'h0; end else if (bht_bank_sel_0_7_7) begin if (_T_7636) begin - bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_119 <= io_exu_mp_pkt_bits_hist; end @@ -41035,7 +41037,7 @@ end // initial bht_bank_rd_data_out_0_120 <= 2'h0; end else if (bht_bank_sel_0_7_8) begin if (_T_7645) begin - bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_120 <= io_exu_mp_pkt_bits_hist; end @@ -41046,7 +41048,7 @@ end // initial bht_bank_rd_data_out_0_121 <= 2'h0; end else if (bht_bank_sel_0_7_9) begin if (_T_7654) begin - bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_121 <= io_exu_mp_pkt_bits_hist; end @@ -41057,7 +41059,7 @@ end // initial bht_bank_rd_data_out_0_122 <= 2'h0; end else if (bht_bank_sel_0_7_10) begin if (_T_7663) begin - bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_122 <= io_exu_mp_pkt_bits_hist; end @@ -41068,7 +41070,7 @@ end // initial bht_bank_rd_data_out_0_123 <= 2'h0; end else if (bht_bank_sel_0_7_11) begin if (_T_7672) begin - bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_123 <= io_exu_mp_pkt_bits_hist; end @@ -41079,7 +41081,7 @@ end // initial bht_bank_rd_data_out_0_124 <= 2'h0; end else if (bht_bank_sel_0_7_12) begin if (_T_7681) begin - bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_124 <= io_exu_mp_pkt_bits_hist; end @@ -41090,7 +41092,7 @@ end // initial bht_bank_rd_data_out_0_125 <= 2'h0; end else if (bht_bank_sel_0_7_13) begin if (_T_7690) begin - bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_125 <= io_exu_mp_pkt_bits_hist; end @@ -41101,7 +41103,7 @@ end // initial bht_bank_rd_data_out_0_126 <= 2'h0; end else if (bht_bank_sel_0_7_14) begin if (_T_7699) begin - bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_126 <= io_exu_mp_pkt_bits_hist; end @@ -41112,7 +41114,7 @@ end // initial bht_bank_rd_data_out_0_127 <= 2'h0; end else if (bht_bank_sel_0_7_15) begin if (_T_7708) begin - bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_127 <= io_exu_mp_pkt_bits_hist; end @@ -41123,7 +41125,7 @@ end // initial bht_bank_rd_data_out_0_128 <= 2'h0; end else if (bht_bank_sel_0_8_0) begin if (_T_7717) begin - bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_128 <= io_exu_mp_pkt_bits_hist; end @@ -41134,7 +41136,7 @@ end // initial bht_bank_rd_data_out_0_129 <= 2'h0; end else if (bht_bank_sel_0_8_1) begin if (_T_7726) begin - bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_129 <= io_exu_mp_pkt_bits_hist; end @@ -41145,7 +41147,7 @@ end // initial bht_bank_rd_data_out_0_130 <= 2'h0; end else if (bht_bank_sel_0_8_2) begin if (_T_7735) begin - bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_130 <= io_exu_mp_pkt_bits_hist; end @@ -41156,7 +41158,7 @@ end // initial bht_bank_rd_data_out_0_131 <= 2'h0; end else if (bht_bank_sel_0_8_3) begin if (_T_7744) begin - bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_131 <= io_exu_mp_pkt_bits_hist; end @@ -41167,7 +41169,7 @@ end // initial bht_bank_rd_data_out_0_132 <= 2'h0; end else if (bht_bank_sel_0_8_4) begin if (_T_7753) begin - bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_132 <= io_exu_mp_pkt_bits_hist; end @@ -41178,7 +41180,7 @@ end // initial bht_bank_rd_data_out_0_133 <= 2'h0; end else if (bht_bank_sel_0_8_5) begin if (_T_7762) begin - bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_133 <= io_exu_mp_pkt_bits_hist; end @@ -41189,7 +41191,7 @@ end // initial bht_bank_rd_data_out_0_134 <= 2'h0; end else if (bht_bank_sel_0_8_6) begin if (_T_7771) begin - bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_134 <= io_exu_mp_pkt_bits_hist; end @@ -41200,7 +41202,7 @@ end // initial bht_bank_rd_data_out_0_135 <= 2'h0; end else if (bht_bank_sel_0_8_7) begin if (_T_7780) begin - bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_135 <= io_exu_mp_pkt_bits_hist; end @@ -41211,7 +41213,7 @@ end // initial bht_bank_rd_data_out_0_136 <= 2'h0; end else if (bht_bank_sel_0_8_8) begin if (_T_7789) begin - bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_136 <= io_exu_mp_pkt_bits_hist; end @@ -41222,7 +41224,7 @@ end // initial bht_bank_rd_data_out_0_137 <= 2'h0; end else if (bht_bank_sel_0_8_9) begin if (_T_7798) begin - bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_137 <= io_exu_mp_pkt_bits_hist; end @@ -41233,7 +41235,7 @@ end // initial bht_bank_rd_data_out_0_138 <= 2'h0; end else if (bht_bank_sel_0_8_10) begin if (_T_7807) begin - bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_138 <= io_exu_mp_pkt_bits_hist; end @@ -41244,7 +41246,7 @@ end // initial bht_bank_rd_data_out_0_139 <= 2'h0; end else if (bht_bank_sel_0_8_11) begin if (_T_7816) begin - bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_139 <= io_exu_mp_pkt_bits_hist; end @@ -41255,7 +41257,7 @@ end // initial bht_bank_rd_data_out_0_140 <= 2'h0; end else if (bht_bank_sel_0_8_12) begin if (_T_7825) begin - bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_140 <= io_exu_mp_pkt_bits_hist; end @@ -41266,7 +41268,7 @@ end // initial bht_bank_rd_data_out_0_141 <= 2'h0; end else if (bht_bank_sel_0_8_13) begin if (_T_7834) begin - bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_141 <= io_exu_mp_pkt_bits_hist; end @@ -41277,7 +41279,7 @@ end // initial bht_bank_rd_data_out_0_142 <= 2'h0; end else if (bht_bank_sel_0_8_14) begin if (_T_7843) begin - bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_142 <= io_exu_mp_pkt_bits_hist; end @@ -41288,7 +41290,7 @@ end // initial bht_bank_rd_data_out_0_143 <= 2'h0; end else if (bht_bank_sel_0_8_15) begin if (_T_7852) begin - bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_143 <= io_exu_mp_pkt_bits_hist; end @@ -41299,7 +41301,7 @@ end // initial bht_bank_rd_data_out_0_144 <= 2'h0; end else if (bht_bank_sel_0_9_0) begin if (_T_7861) begin - bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_144 <= io_exu_mp_pkt_bits_hist; end @@ -41310,7 +41312,7 @@ end // initial bht_bank_rd_data_out_0_145 <= 2'h0; end else if (bht_bank_sel_0_9_1) begin if (_T_7870) begin - bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_145 <= io_exu_mp_pkt_bits_hist; end @@ -41321,7 +41323,7 @@ end // initial bht_bank_rd_data_out_0_146 <= 2'h0; end else if (bht_bank_sel_0_9_2) begin if (_T_7879) begin - bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_146 <= io_exu_mp_pkt_bits_hist; end @@ -41332,7 +41334,7 @@ end // initial bht_bank_rd_data_out_0_147 <= 2'h0; end else if (bht_bank_sel_0_9_3) begin if (_T_7888) begin - bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_147 <= io_exu_mp_pkt_bits_hist; end @@ -41343,7 +41345,7 @@ end // initial bht_bank_rd_data_out_0_148 <= 2'h0; end else if (bht_bank_sel_0_9_4) begin if (_T_7897) begin - bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_148 <= io_exu_mp_pkt_bits_hist; end @@ -41354,7 +41356,7 @@ end // initial bht_bank_rd_data_out_0_149 <= 2'h0; end else if (bht_bank_sel_0_9_5) begin if (_T_7906) begin - bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_149 <= io_exu_mp_pkt_bits_hist; end @@ -41365,7 +41367,7 @@ end // initial bht_bank_rd_data_out_0_150 <= 2'h0; end else if (bht_bank_sel_0_9_6) begin if (_T_7915) begin - bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_150 <= io_exu_mp_pkt_bits_hist; end @@ -41376,7 +41378,7 @@ end // initial bht_bank_rd_data_out_0_151 <= 2'h0; end else if (bht_bank_sel_0_9_7) begin if (_T_7924) begin - bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_151 <= io_exu_mp_pkt_bits_hist; end @@ -41387,7 +41389,7 @@ end // initial bht_bank_rd_data_out_0_152 <= 2'h0; end else if (bht_bank_sel_0_9_8) begin if (_T_7933) begin - bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_152 <= io_exu_mp_pkt_bits_hist; end @@ -41398,7 +41400,7 @@ end // initial bht_bank_rd_data_out_0_153 <= 2'h0; end else if (bht_bank_sel_0_9_9) begin if (_T_7942) begin - bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_153 <= io_exu_mp_pkt_bits_hist; end @@ -41409,7 +41411,7 @@ end // initial bht_bank_rd_data_out_0_154 <= 2'h0; end else if (bht_bank_sel_0_9_10) begin if (_T_7951) begin - bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_154 <= io_exu_mp_pkt_bits_hist; end @@ -41420,7 +41422,7 @@ end // initial bht_bank_rd_data_out_0_155 <= 2'h0; end else if (bht_bank_sel_0_9_11) begin if (_T_7960) begin - bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_155 <= io_exu_mp_pkt_bits_hist; end @@ -41431,7 +41433,7 @@ end // initial bht_bank_rd_data_out_0_156 <= 2'h0; end else if (bht_bank_sel_0_9_12) begin if (_T_7969) begin - bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_156 <= io_exu_mp_pkt_bits_hist; end @@ -41442,7 +41444,7 @@ end // initial bht_bank_rd_data_out_0_157 <= 2'h0; end else if (bht_bank_sel_0_9_13) begin if (_T_7978) begin - bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_157 <= io_exu_mp_pkt_bits_hist; end @@ -41453,7 +41455,7 @@ end // initial bht_bank_rd_data_out_0_158 <= 2'h0; end else if (bht_bank_sel_0_9_14) begin if (_T_7987) begin - bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_158 <= io_exu_mp_pkt_bits_hist; end @@ -41464,7 +41466,7 @@ end // initial bht_bank_rd_data_out_0_159 <= 2'h0; end else if (bht_bank_sel_0_9_15) begin if (_T_7996) begin - bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_159 <= io_exu_mp_pkt_bits_hist; end @@ -41475,7 +41477,7 @@ end // initial bht_bank_rd_data_out_0_160 <= 2'h0; end else if (bht_bank_sel_0_10_0) begin if (_T_8005) begin - bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_160 <= io_exu_mp_pkt_bits_hist; end @@ -41486,7 +41488,7 @@ end // initial bht_bank_rd_data_out_0_161 <= 2'h0; end else if (bht_bank_sel_0_10_1) begin if (_T_8014) begin - bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_161 <= io_exu_mp_pkt_bits_hist; end @@ -41497,7 +41499,7 @@ end // initial bht_bank_rd_data_out_0_162 <= 2'h0; end else if (bht_bank_sel_0_10_2) begin if (_T_8023) begin - bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_162 <= io_exu_mp_pkt_bits_hist; end @@ -41508,7 +41510,7 @@ end // initial bht_bank_rd_data_out_0_163 <= 2'h0; end else if (bht_bank_sel_0_10_3) begin if (_T_8032) begin - bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_163 <= io_exu_mp_pkt_bits_hist; end @@ -41519,7 +41521,7 @@ end // initial bht_bank_rd_data_out_0_164 <= 2'h0; end else if (bht_bank_sel_0_10_4) begin if (_T_8041) begin - bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_164 <= io_exu_mp_pkt_bits_hist; end @@ -41530,7 +41532,7 @@ end // initial bht_bank_rd_data_out_0_165 <= 2'h0; end else if (bht_bank_sel_0_10_5) begin if (_T_8050) begin - bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_165 <= io_exu_mp_pkt_bits_hist; end @@ -41541,7 +41543,7 @@ end // initial bht_bank_rd_data_out_0_166 <= 2'h0; end else if (bht_bank_sel_0_10_6) begin if (_T_8059) begin - bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_166 <= io_exu_mp_pkt_bits_hist; end @@ -41552,7 +41554,7 @@ end // initial bht_bank_rd_data_out_0_167 <= 2'h0; end else if (bht_bank_sel_0_10_7) begin if (_T_8068) begin - bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_167 <= io_exu_mp_pkt_bits_hist; end @@ -41563,7 +41565,7 @@ end // initial bht_bank_rd_data_out_0_168 <= 2'h0; end else if (bht_bank_sel_0_10_8) begin if (_T_8077) begin - bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_168 <= io_exu_mp_pkt_bits_hist; end @@ -41574,7 +41576,7 @@ end // initial bht_bank_rd_data_out_0_169 <= 2'h0; end else if (bht_bank_sel_0_10_9) begin if (_T_8086) begin - bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_169 <= io_exu_mp_pkt_bits_hist; end @@ -41585,7 +41587,7 @@ end // initial bht_bank_rd_data_out_0_170 <= 2'h0; end else if (bht_bank_sel_0_10_10) begin if (_T_8095) begin - bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_170 <= io_exu_mp_pkt_bits_hist; end @@ -41596,7 +41598,7 @@ end // initial bht_bank_rd_data_out_0_171 <= 2'h0; end else if (bht_bank_sel_0_10_11) begin if (_T_8104) begin - bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_171 <= io_exu_mp_pkt_bits_hist; end @@ -41607,7 +41609,7 @@ end // initial bht_bank_rd_data_out_0_172 <= 2'h0; end else if (bht_bank_sel_0_10_12) begin if (_T_8113) begin - bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_172 <= io_exu_mp_pkt_bits_hist; end @@ -41618,7 +41620,7 @@ end // initial bht_bank_rd_data_out_0_173 <= 2'h0; end else if (bht_bank_sel_0_10_13) begin if (_T_8122) begin - bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_173 <= io_exu_mp_pkt_bits_hist; end @@ -41629,7 +41631,7 @@ end // initial bht_bank_rd_data_out_0_174 <= 2'h0; end else if (bht_bank_sel_0_10_14) begin if (_T_8131) begin - bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_174 <= io_exu_mp_pkt_bits_hist; end @@ -41640,7 +41642,7 @@ end // initial bht_bank_rd_data_out_0_175 <= 2'h0; end else if (bht_bank_sel_0_10_15) begin if (_T_8140) begin - bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_175 <= io_exu_mp_pkt_bits_hist; end @@ -41651,7 +41653,7 @@ end // initial bht_bank_rd_data_out_0_176 <= 2'h0; end else if (bht_bank_sel_0_11_0) begin if (_T_8149) begin - bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_176 <= io_exu_mp_pkt_bits_hist; end @@ -41662,7 +41664,7 @@ end // initial bht_bank_rd_data_out_0_177 <= 2'h0; end else if (bht_bank_sel_0_11_1) begin if (_T_8158) begin - bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_177 <= io_exu_mp_pkt_bits_hist; end @@ -41673,7 +41675,7 @@ end // initial bht_bank_rd_data_out_0_178 <= 2'h0; end else if (bht_bank_sel_0_11_2) begin if (_T_8167) begin - bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_178 <= io_exu_mp_pkt_bits_hist; end @@ -41684,7 +41686,7 @@ end // initial bht_bank_rd_data_out_0_179 <= 2'h0; end else if (bht_bank_sel_0_11_3) begin if (_T_8176) begin - bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_179 <= io_exu_mp_pkt_bits_hist; end @@ -41695,7 +41697,7 @@ end // initial bht_bank_rd_data_out_0_180 <= 2'h0; end else if (bht_bank_sel_0_11_4) begin if (_T_8185) begin - bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_180 <= io_exu_mp_pkt_bits_hist; end @@ -41706,7 +41708,7 @@ end // initial bht_bank_rd_data_out_0_181 <= 2'h0; end else if (bht_bank_sel_0_11_5) begin if (_T_8194) begin - bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_181 <= io_exu_mp_pkt_bits_hist; end @@ -41717,7 +41719,7 @@ end // initial bht_bank_rd_data_out_0_182 <= 2'h0; end else if (bht_bank_sel_0_11_6) begin if (_T_8203) begin - bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_182 <= io_exu_mp_pkt_bits_hist; end @@ -41728,7 +41730,7 @@ end // initial bht_bank_rd_data_out_0_183 <= 2'h0; end else if (bht_bank_sel_0_11_7) begin if (_T_8212) begin - bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_183 <= io_exu_mp_pkt_bits_hist; end @@ -41739,7 +41741,7 @@ end // initial bht_bank_rd_data_out_0_184 <= 2'h0; end else if (bht_bank_sel_0_11_8) begin if (_T_8221) begin - bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_184 <= io_exu_mp_pkt_bits_hist; end @@ -41750,7 +41752,7 @@ end // initial bht_bank_rd_data_out_0_185 <= 2'h0; end else if (bht_bank_sel_0_11_9) begin if (_T_8230) begin - bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_185 <= io_exu_mp_pkt_bits_hist; end @@ -41761,7 +41763,7 @@ end // initial bht_bank_rd_data_out_0_186 <= 2'h0; end else if (bht_bank_sel_0_11_10) begin if (_T_8239) begin - bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_186 <= io_exu_mp_pkt_bits_hist; end @@ -41772,7 +41774,7 @@ end // initial bht_bank_rd_data_out_0_187 <= 2'h0; end else if (bht_bank_sel_0_11_11) begin if (_T_8248) begin - bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_187 <= io_exu_mp_pkt_bits_hist; end @@ -41783,7 +41785,7 @@ end // initial bht_bank_rd_data_out_0_188 <= 2'h0; end else if (bht_bank_sel_0_11_12) begin if (_T_8257) begin - bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_188 <= io_exu_mp_pkt_bits_hist; end @@ -41794,7 +41796,7 @@ end // initial bht_bank_rd_data_out_0_189 <= 2'h0; end else if (bht_bank_sel_0_11_13) begin if (_T_8266) begin - bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_189 <= io_exu_mp_pkt_bits_hist; end @@ -41805,7 +41807,7 @@ end // initial bht_bank_rd_data_out_0_190 <= 2'h0; end else if (bht_bank_sel_0_11_14) begin if (_T_8275) begin - bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_190 <= io_exu_mp_pkt_bits_hist; end @@ -41816,7 +41818,7 @@ end // initial bht_bank_rd_data_out_0_191 <= 2'h0; end else if (bht_bank_sel_0_11_15) begin if (_T_8284) begin - bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_191 <= io_exu_mp_pkt_bits_hist; end @@ -41827,7 +41829,7 @@ end // initial bht_bank_rd_data_out_0_192 <= 2'h0; end else if (bht_bank_sel_0_12_0) begin if (_T_8293) begin - bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_192 <= io_exu_mp_pkt_bits_hist; end @@ -41838,7 +41840,7 @@ end // initial bht_bank_rd_data_out_0_193 <= 2'h0; end else if (bht_bank_sel_0_12_1) begin if (_T_8302) begin - bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_193 <= io_exu_mp_pkt_bits_hist; end @@ -41849,7 +41851,7 @@ end // initial bht_bank_rd_data_out_0_194 <= 2'h0; end else if (bht_bank_sel_0_12_2) begin if (_T_8311) begin - bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_194 <= io_exu_mp_pkt_bits_hist; end @@ -41860,7 +41862,7 @@ end // initial bht_bank_rd_data_out_0_195 <= 2'h0; end else if (bht_bank_sel_0_12_3) begin if (_T_8320) begin - bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_195 <= io_exu_mp_pkt_bits_hist; end @@ -41871,7 +41873,7 @@ end // initial bht_bank_rd_data_out_0_196 <= 2'h0; end else if (bht_bank_sel_0_12_4) begin if (_T_8329) begin - bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_196 <= io_exu_mp_pkt_bits_hist; end @@ -41882,7 +41884,7 @@ end // initial bht_bank_rd_data_out_0_197 <= 2'h0; end else if (bht_bank_sel_0_12_5) begin if (_T_8338) begin - bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_197 <= io_exu_mp_pkt_bits_hist; end @@ -41893,7 +41895,7 @@ end // initial bht_bank_rd_data_out_0_198 <= 2'h0; end else if (bht_bank_sel_0_12_6) begin if (_T_8347) begin - bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_198 <= io_exu_mp_pkt_bits_hist; end @@ -41904,7 +41906,7 @@ end // initial bht_bank_rd_data_out_0_199 <= 2'h0; end else if (bht_bank_sel_0_12_7) begin if (_T_8356) begin - bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_199 <= io_exu_mp_pkt_bits_hist; end @@ -41915,7 +41917,7 @@ end // initial bht_bank_rd_data_out_0_200 <= 2'h0; end else if (bht_bank_sel_0_12_8) begin if (_T_8365) begin - bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_200 <= io_exu_mp_pkt_bits_hist; end @@ -41926,7 +41928,7 @@ end // initial bht_bank_rd_data_out_0_201 <= 2'h0; end else if (bht_bank_sel_0_12_9) begin if (_T_8374) begin - bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_201 <= io_exu_mp_pkt_bits_hist; end @@ -41937,7 +41939,7 @@ end // initial bht_bank_rd_data_out_0_202 <= 2'h0; end else if (bht_bank_sel_0_12_10) begin if (_T_8383) begin - bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_202 <= io_exu_mp_pkt_bits_hist; end @@ -41948,7 +41950,7 @@ end // initial bht_bank_rd_data_out_0_203 <= 2'h0; end else if (bht_bank_sel_0_12_11) begin if (_T_8392) begin - bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_203 <= io_exu_mp_pkt_bits_hist; end @@ -41959,7 +41961,7 @@ end // initial bht_bank_rd_data_out_0_204 <= 2'h0; end else if (bht_bank_sel_0_12_12) begin if (_T_8401) begin - bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_204 <= io_exu_mp_pkt_bits_hist; end @@ -41970,7 +41972,7 @@ end // initial bht_bank_rd_data_out_0_205 <= 2'h0; end else if (bht_bank_sel_0_12_13) begin if (_T_8410) begin - bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_205 <= io_exu_mp_pkt_bits_hist; end @@ -41981,7 +41983,7 @@ end // initial bht_bank_rd_data_out_0_206 <= 2'h0; end else if (bht_bank_sel_0_12_14) begin if (_T_8419) begin - bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_206 <= io_exu_mp_pkt_bits_hist; end @@ -41992,7 +41994,7 @@ end // initial bht_bank_rd_data_out_0_207 <= 2'h0; end else if (bht_bank_sel_0_12_15) begin if (_T_8428) begin - bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_207 <= io_exu_mp_pkt_bits_hist; end @@ -42003,7 +42005,7 @@ end // initial bht_bank_rd_data_out_0_208 <= 2'h0; end else if (bht_bank_sel_0_13_0) begin if (_T_8437) begin - bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_208 <= io_exu_mp_pkt_bits_hist; end @@ -42014,7 +42016,7 @@ end // initial bht_bank_rd_data_out_0_209 <= 2'h0; end else if (bht_bank_sel_0_13_1) begin if (_T_8446) begin - bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_209 <= io_exu_mp_pkt_bits_hist; end @@ -42025,7 +42027,7 @@ end // initial bht_bank_rd_data_out_0_210 <= 2'h0; end else if (bht_bank_sel_0_13_2) begin if (_T_8455) begin - bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_210 <= io_exu_mp_pkt_bits_hist; end @@ -42036,7 +42038,7 @@ end // initial bht_bank_rd_data_out_0_211 <= 2'h0; end else if (bht_bank_sel_0_13_3) begin if (_T_8464) begin - bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_211 <= io_exu_mp_pkt_bits_hist; end @@ -42047,7 +42049,7 @@ end // initial bht_bank_rd_data_out_0_212 <= 2'h0; end else if (bht_bank_sel_0_13_4) begin if (_T_8473) begin - bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_212 <= io_exu_mp_pkt_bits_hist; end @@ -42058,7 +42060,7 @@ end // initial bht_bank_rd_data_out_0_213 <= 2'h0; end else if (bht_bank_sel_0_13_5) begin if (_T_8482) begin - bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_213 <= io_exu_mp_pkt_bits_hist; end @@ -42069,7 +42071,7 @@ end // initial bht_bank_rd_data_out_0_214 <= 2'h0; end else if (bht_bank_sel_0_13_6) begin if (_T_8491) begin - bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_214 <= io_exu_mp_pkt_bits_hist; end @@ -42080,7 +42082,7 @@ end // initial bht_bank_rd_data_out_0_215 <= 2'h0; end else if (bht_bank_sel_0_13_7) begin if (_T_8500) begin - bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_215 <= io_exu_mp_pkt_bits_hist; end @@ -42091,7 +42093,7 @@ end // initial bht_bank_rd_data_out_0_216 <= 2'h0; end else if (bht_bank_sel_0_13_8) begin if (_T_8509) begin - bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_216 <= io_exu_mp_pkt_bits_hist; end @@ -42102,7 +42104,7 @@ end // initial bht_bank_rd_data_out_0_217 <= 2'h0; end else if (bht_bank_sel_0_13_9) begin if (_T_8518) begin - bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_217 <= io_exu_mp_pkt_bits_hist; end @@ -42113,7 +42115,7 @@ end // initial bht_bank_rd_data_out_0_218 <= 2'h0; end else if (bht_bank_sel_0_13_10) begin if (_T_8527) begin - bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_218 <= io_exu_mp_pkt_bits_hist; end @@ -42124,7 +42126,7 @@ end // initial bht_bank_rd_data_out_0_219 <= 2'h0; end else if (bht_bank_sel_0_13_11) begin if (_T_8536) begin - bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_219 <= io_exu_mp_pkt_bits_hist; end @@ -42135,7 +42137,7 @@ end // initial bht_bank_rd_data_out_0_220 <= 2'h0; end else if (bht_bank_sel_0_13_12) begin if (_T_8545) begin - bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_220 <= io_exu_mp_pkt_bits_hist; end @@ -42146,7 +42148,7 @@ end // initial bht_bank_rd_data_out_0_221 <= 2'h0; end else if (bht_bank_sel_0_13_13) begin if (_T_8554) begin - bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_221 <= io_exu_mp_pkt_bits_hist; end @@ -42157,7 +42159,7 @@ end // initial bht_bank_rd_data_out_0_222 <= 2'h0; end else if (bht_bank_sel_0_13_14) begin if (_T_8563) begin - bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_222 <= io_exu_mp_pkt_bits_hist; end @@ -42168,7 +42170,7 @@ end // initial bht_bank_rd_data_out_0_223 <= 2'h0; end else if (bht_bank_sel_0_13_15) begin if (_T_8572) begin - bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_223 <= io_exu_mp_pkt_bits_hist; end @@ -42179,7 +42181,7 @@ end // initial bht_bank_rd_data_out_0_224 <= 2'h0; end else if (bht_bank_sel_0_14_0) begin if (_T_8581) begin - bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_224 <= io_exu_mp_pkt_bits_hist; end @@ -42190,7 +42192,7 @@ end // initial bht_bank_rd_data_out_0_225 <= 2'h0; end else if (bht_bank_sel_0_14_1) begin if (_T_8590) begin - bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_225 <= io_exu_mp_pkt_bits_hist; end @@ -42201,7 +42203,7 @@ end // initial bht_bank_rd_data_out_0_226 <= 2'h0; end else if (bht_bank_sel_0_14_2) begin if (_T_8599) begin - bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_226 <= io_exu_mp_pkt_bits_hist; end @@ -42212,7 +42214,7 @@ end // initial bht_bank_rd_data_out_0_227 <= 2'h0; end else if (bht_bank_sel_0_14_3) begin if (_T_8608) begin - bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_227 <= io_exu_mp_pkt_bits_hist; end @@ -42223,7 +42225,7 @@ end // initial bht_bank_rd_data_out_0_228 <= 2'h0; end else if (bht_bank_sel_0_14_4) begin if (_T_8617) begin - bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_228 <= io_exu_mp_pkt_bits_hist; end @@ -42234,7 +42236,7 @@ end // initial bht_bank_rd_data_out_0_229 <= 2'h0; end else if (bht_bank_sel_0_14_5) begin if (_T_8626) begin - bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_229 <= io_exu_mp_pkt_bits_hist; end @@ -42245,7 +42247,7 @@ end // initial bht_bank_rd_data_out_0_230 <= 2'h0; end else if (bht_bank_sel_0_14_6) begin if (_T_8635) begin - bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_230 <= io_exu_mp_pkt_bits_hist; end @@ -42256,7 +42258,7 @@ end // initial bht_bank_rd_data_out_0_231 <= 2'h0; end else if (bht_bank_sel_0_14_7) begin if (_T_8644) begin - bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_231 <= io_exu_mp_pkt_bits_hist; end @@ -42267,7 +42269,7 @@ end // initial bht_bank_rd_data_out_0_232 <= 2'h0; end else if (bht_bank_sel_0_14_8) begin if (_T_8653) begin - bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_232 <= io_exu_mp_pkt_bits_hist; end @@ -42278,7 +42280,7 @@ end // initial bht_bank_rd_data_out_0_233 <= 2'h0; end else if (bht_bank_sel_0_14_9) begin if (_T_8662) begin - bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_233 <= io_exu_mp_pkt_bits_hist; end @@ -42289,7 +42291,7 @@ end // initial bht_bank_rd_data_out_0_234 <= 2'h0; end else if (bht_bank_sel_0_14_10) begin if (_T_8671) begin - bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_234 <= io_exu_mp_pkt_bits_hist; end @@ -42300,7 +42302,7 @@ end // initial bht_bank_rd_data_out_0_235 <= 2'h0; end else if (bht_bank_sel_0_14_11) begin if (_T_8680) begin - bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_235 <= io_exu_mp_pkt_bits_hist; end @@ -42311,7 +42313,7 @@ end // initial bht_bank_rd_data_out_0_236 <= 2'h0; end else if (bht_bank_sel_0_14_12) begin if (_T_8689) begin - bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_236 <= io_exu_mp_pkt_bits_hist; end @@ -42322,7 +42324,7 @@ end // initial bht_bank_rd_data_out_0_237 <= 2'h0; end else if (bht_bank_sel_0_14_13) begin if (_T_8698) begin - bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_237 <= io_exu_mp_pkt_bits_hist; end @@ -42333,7 +42335,7 @@ end // initial bht_bank_rd_data_out_0_238 <= 2'h0; end else if (bht_bank_sel_0_14_14) begin if (_T_8707) begin - bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_238 <= io_exu_mp_pkt_bits_hist; end @@ -42344,7 +42346,7 @@ end // initial bht_bank_rd_data_out_0_239 <= 2'h0; end else if (bht_bank_sel_0_14_15) begin if (_T_8716) begin - bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_239 <= io_exu_mp_pkt_bits_hist; end @@ -42355,7 +42357,7 @@ end // initial bht_bank_rd_data_out_0_240 <= 2'h0; end else if (bht_bank_sel_0_15_0) begin if (_T_8725) begin - bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_240 <= io_exu_mp_pkt_bits_hist; end @@ -42366,7 +42368,7 @@ end // initial bht_bank_rd_data_out_0_241 <= 2'h0; end else if (bht_bank_sel_0_15_1) begin if (_T_8734) begin - bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_241 <= io_exu_mp_pkt_bits_hist; end @@ -42377,7 +42379,7 @@ end // initial bht_bank_rd_data_out_0_242 <= 2'h0; end else if (bht_bank_sel_0_15_2) begin if (_T_8743) begin - bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_242 <= io_exu_mp_pkt_bits_hist; end @@ -42388,7 +42390,7 @@ end // initial bht_bank_rd_data_out_0_243 <= 2'h0; end else if (bht_bank_sel_0_15_3) begin if (_T_8752) begin - bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_243 <= io_exu_mp_pkt_bits_hist; end @@ -42399,7 +42401,7 @@ end // initial bht_bank_rd_data_out_0_244 <= 2'h0; end else if (bht_bank_sel_0_15_4) begin if (_T_8761) begin - bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_244 <= io_exu_mp_pkt_bits_hist; end @@ -42410,7 +42412,7 @@ end // initial bht_bank_rd_data_out_0_245 <= 2'h0; end else if (bht_bank_sel_0_15_5) begin if (_T_8770) begin - bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_245 <= io_exu_mp_pkt_bits_hist; end @@ -42421,7 +42423,7 @@ end // initial bht_bank_rd_data_out_0_246 <= 2'h0; end else if (bht_bank_sel_0_15_6) begin if (_T_8779) begin - bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_246 <= io_exu_mp_pkt_bits_hist; end @@ -42432,7 +42434,7 @@ end // initial bht_bank_rd_data_out_0_247 <= 2'h0; end else if (bht_bank_sel_0_15_7) begin if (_T_8788) begin - bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_247 <= io_exu_mp_pkt_bits_hist; end @@ -42443,7 +42445,7 @@ end // initial bht_bank_rd_data_out_0_248 <= 2'h0; end else if (bht_bank_sel_0_15_8) begin if (_T_8797) begin - bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_248 <= io_exu_mp_pkt_bits_hist; end @@ -42454,7 +42456,7 @@ end // initial bht_bank_rd_data_out_0_249 <= 2'h0; end else if (bht_bank_sel_0_15_9) begin if (_T_8806) begin - bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_249 <= io_exu_mp_pkt_bits_hist; end @@ -42465,7 +42467,7 @@ end // initial bht_bank_rd_data_out_0_250 <= 2'h0; end else if (bht_bank_sel_0_15_10) begin if (_T_8815) begin - bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_250 <= io_exu_mp_pkt_bits_hist; end @@ -42476,7 +42478,7 @@ end // initial bht_bank_rd_data_out_0_251 <= 2'h0; end else if (bht_bank_sel_0_15_11) begin if (_T_8824) begin - bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_251 <= io_exu_mp_pkt_bits_hist; end @@ -42487,7 +42489,7 @@ end // initial bht_bank_rd_data_out_0_252 <= 2'h0; end else if (bht_bank_sel_0_15_12) begin if (_T_8833) begin - bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_252 <= io_exu_mp_pkt_bits_hist; end @@ -42498,7 +42500,7 @@ end // initial bht_bank_rd_data_out_0_253 <= 2'h0; end else if (bht_bank_sel_0_15_13) begin if (_T_8842) begin - bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_253 <= io_exu_mp_pkt_bits_hist; end @@ -42509,7 +42511,7 @@ end // initial bht_bank_rd_data_out_0_254 <= 2'h0; end else if (bht_bank_sel_0_15_14) begin if (_T_8851) begin - bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_254 <= io_exu_mp_pkt_bits_hist; end @@ -42520,7 +42522,7 @@ end // initial bht_bank_rd_data_out_0_255 <= 2'h0; end else if (bht_bank_sel_0_15_15) begin if (_T_8860) begin - bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_255 <= io_exu_mp_pkt_bits_hist; end @@ -43150,6 +43152,7 @@ module el2_ifu_aln_ctl( output io_ifu_i0_dbecc, output [31:0] io_ifu_i0_instr, output [30:0] io_ifu_i0_pc, + output io_ifu_i0_pc4, output io_ifu_fb_consume1, output io_ifu_fb_consume2, output [7:0] io_ifu_i0_bp_index, @@ -43158,13 +43161,13 @@ module el2_ifu_aln_ctl( output io_ifu_pmu_instr_aligned, output [15:0] io_ifu_i0_cinst, output io_i0_brp_valid, - output [11:0] io_i0_brp_bits_toffset, - output [1:0] io_i0_brp_bits_hist, - output io_i0_brp_bits_br_error, - output io_i0_brp_bits_br_start_error, - output [30:0] io_i0_brp_bits_prett, - output io_i0_brp_bits_way, - output io_i0_brp_bits_ret + output [11:0] io_i0_brp_toffset, + output [1:0] io_i0_brp_hist, + output io_i0_brp_br_error, + output io_i0_brp_br_start_error, + output [30:0] io_i0_brp_prett, + output io_i0_brp_way, + output io_i0_brp_ret ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -43603,24 +43606,24 @@ module el2_ifu_aln_ctl( wire _T_721 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 378:58] wire _T_722 = _T_719 | _T_721; // @[el2_ifu_aln_ctl.scala 378:47] wire _T_726 = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:100] - wire _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:34] - wire _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:60] + wire _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:29] + wire _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:55] wire _T_734 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 382:29] wire _T_736 = first4B & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 382:55] wire i0_brp_pc4 = _T_734 | _T_736; // @[el2_ifu_aln_ctl.scala 382:44] - wire _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:38] - wire _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:39] - wire _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:67] - wire _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:56] + wire _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:33] + wire _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:34] + wire _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:62] + wire _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:51] wire _T_749 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 387:14] wire _T_751 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42] wire _T_752 = _T_749 | _T_751; // @[el2_ifu_aln_ctl.scala 387:31] wire i0_ends_f1 = first4B & _T_515; // @[el2_ifu_aln_ctl.scala 389:28] - wire _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:47] - wire _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:61] - wire _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:94] - wire _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:92] - wire _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:106] + wire _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42] + wire _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:56] + wire _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89] + wire _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:87] + wire _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:101] rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -43704,6 +43707,7 @@ module el2_ifu_aln_ctl( assign io_ifu_i0_dbecc = _T_690 | _T_691; // @[el2_ifu_aln_ctl.scala 51:19 el2_ifu_aln_ctl.scala 362:19] assign io_ifu_i0_instr = _T_696 | _T_697; // @[el2_ifu_aln_ctl.scala 52:19 el2_ifu_aln_ctl.scala 368:19] assign io_ifu_i0_pc = f0pc; // @[el2_ifu_aln_ctl.scala 53:16 el2_ifu_aln_ctl.scala 340:16] + assign io_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 54:17 el2_ifu_aln_ctl.scala 344:17] assign io_ifu_fb_consume1 = _T_312 & _T_1; // @[el2_ifu_aln_ctl.scala 55:22 el2_ifu_aln_ctl.scala 258:22] assign io_ifu_fb_consume2 = _T_315 & _T_1; // @[el2_ifu_aln_ctl.scala 56:22 el2_ifu_aln_ctl.scala 259:22] assign io_ifu_i0_bp_index = _T_738 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 57:22 el2_ifu_aln_ctl.scala 400:22] @@ -43712,13 +43716,13 @@ module el2_ifu_aln_ctl( assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_785; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28] assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 61:19 el2_ifu_aln_ctl.scala 346:19] assign io_i0_brp_valid = _T_722 | _T_726; // @[el2_ifu_aln_ctl.scala 378:19] - assign io_i0_brp_bits_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:26] - assign io_i0_brp_bits_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:23] - assign io_i0_brp_bits_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:27] - assign io_i0_brp_bits_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:34] - assign io_i0_brp_bits_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:24] - assign io_i0_brp_bits_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:22] - assign io_i0_brp_bits_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:22] + assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:21] + assign io_i0_brp_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:18] + assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22] + assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29] + assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19] + assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17] + assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_en = _T_354 | _T_358; // @[el2_lib.scala 511:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] @@ -44441,20 +44445,22 @@ module el2_ifu( output io_iccm_dma_sb_error, output [31:0] io_ifu_i0_instr, output [30:0] io_ifu_i0_pc, + output io_ifu_i0_pc4, output io_ifu_miss_state_idle, output io_i0_brp_valid, - output [11:0] io_i0_brp_bits_toffset, - output [1:0] io_i0_brp_bits_hist, - output io_i0_brp_bits_br_error, - output io_i0_brp_bits_br_start_error, - output [30:0] io_i0_brp_bits_prett, - output io_i0_brp_bits_way, - output io_i0_brp_bits_ret, + output [11:0] io_i0_brp_toffset, + output [1:0] io_i0_brp_hist, + output io_i0_brp_br_error, + output io_i0_brp_br_start_error, + output [30:0] io_i0_brp_prett, + output io_i0_brp_way, + output io_i0_brp_ret, output [7:0] io_ifu_i0_bp_index, output [7:0] io_ifu_i0_bp_fghr, output [4:0] io_ifu_i0_bp_btag, input io_exu_mp_pkt_bits_misp, input io_exu_mp_pkt_bits_ataken, + input io_exu_mp_pkt_bits_boffset, input io_exu_mp_pkt_bits_pc4, input [1:0] io_exu_mp_pkt_bits_hist, input [11:0] io_exu_mp_pkt_bits_toffset, @@ -44467,11 +44473,11 @@ module el2_ifu( input [7:0] io_exu_mp_index, input [4:0] io_exu_mp_btag, input io_dec_tlu_br0_r_pkt_valid, - input [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - input io_dec_tlu_br0_r_pkt_bits_br_error, - input io_dec_tlu_br0_r_pkt_bits_br_start_error, - input io_dec_tlu_br0_r_pkt_bits_way, - input io_dec_tlu_br0_r_pkt_bits_middle, + input [1:0] io_dec_tlu_br0_r_pkt_hist, + input io_dec_tlu_br0_r_pkt_br_error, + input io_dec_tlu_br0_r_pkt_br_start_error, + input io_dec_tlu_br0_r_pkt_way, + input io_dec_tlu_br0_r_pkt_middle, input [7:0] io_exu_i0_br_fghr_r, input [7:0] io_exu_i0_br_index_r, input io_dec_tlu_flush_lower_wb, @@ -44590,11 +44596,11 @@ module el2_ifu( wire [30:0] bp_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 147:25] - wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 147:25] + wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 147:25] wire [7:0] bp_ctl_ch_io_exu_i0_br_fghr_r; // @[el2_ifu.scala 147:25] wire [7:0] bp_ctl_ch_io_exu_i0_br_index_r; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 147:25] @@ -44602,6 +44608,7 @@ module el2_ifu( wire bp_ctl_ch_io_dec_tlu_bpred_disable; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_exu_mp_pkt_bits_misp; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_exu_mp_pkt_bits_ataken; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_exu_mp_pkt_bits_boffset; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_exu_mp_pkt_bits_pc4; // @[el2_ifu.scala 147:25] wire [1:0] bp_ctl_ch_io_exu_mp_pkt_bits_hist; // @[el2_ifu.scala 147:25] wire [11:0] bp_ctl_ch_io_exu_mp_pkt_bits_toffset; // @[el2_ifu.scala 147:25] @@ -44655,6 +44662,7 @@ module el2_ifu( wire aln_ctl_ch_io_ifu_i0_dbecc; // @[el2_ifu.scala 148:26] wire [31:0] aln_ctl_ch_io_ifu_i0_instr; // @[el2_ifu.scala 148:26] wire [30:0] aln_ctl_ch_io_ifu_i0_pc; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 148:26] wire aln_ctl_ch_io_ifu_fb_consume1; // @[el2_ifu.scala 148:26] wire aln_ctl_ch_io_ifu_fb_consume2; // @[el2_ifu.scala 148:26] wire [7:0] aln_ctl_ch_io_ifu_i0_bp_index; // @[el2_ifu.scala 148:26] @@ -44663,13 +44671,13 @@ module el2_ifu( wire aln_ctl_ch_io_ifu_pmu_instr_aligned; // @[el2_ifu.scala 148:26] wire [15:0] aln_ctl_ch_io_ifu_i0_cinst; // @[el2_ifu.scala 148:26] wire aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 148:26] - wire [11:0] aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 148:26] - wire [1:0] aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 148:26] - wire [30:0] aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 148:26] + wire [11:0] aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 148:26] + wire [1:0] aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 148:26] + wire [30:0] aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 148:26] wire ifc_ctl_ch_clock; // @[el2_ifu.scala 149:26] wire ifc_ctl_ch_reset; // @[el2_ifu.scala 149:26] wire ifc_ctl_ch_io_free_clk; // @[el2_ifu.scala 149:26] @@ -44806,11 +44814,11 @@ module el2_ifu( .io_ifc_fetch_addr_f(bp_ctl_ch_io_ifc_fetch_addr_f), .io_ifc_fetch_req_f(bp_ctl_ch_io_ifc_fetch_req_f), .io_dec_tlu_br0_r_pkt_valid(bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle), .io_exu_i0_br_fghr_r(bp_ctl_ch_io_exu_i0_br_fghr_r), .io_exu_i0_br_index_r(bp_ctl_ch_io_exu_i0_br_index_r), .io_dec_tlu_flush_lower_wb(bp_ctl_ch_io_dec_tlu_flush_lower_wb), @@ -44818,6 +44826,7 @@ module el2_ifu( .io_dec_tlu_bpred_disable(bp_ctl_ch_io_dec_tlu_bpred_disable), .io_exu_mp_pkt_bits_misp(bp_ctl_ch_io_exu_mp_pkt_bits_misp), .io_exu_mp_pkt_bits_ataken(bp_ctl_ch_io_exu_mp_pkt_bits_ataken), + .io_exu_mp_pkt_bits_boffset(bp_ctl_ch_io_exu_mp_pkt_bits_boffset), .io_exu_mp_pkt_bits_pc4(bp_ctl_ch_io_exu_mp_pkt_bits_pc4), .io_exu_mp_pkt_bits_hist(bp_ctl_ch_io_exu_mp_pkt_bits_hist), .io_exu_mp_pkt_bits_toffset(bp_ctl_ch_io_exu_mp_pkt_bits_toffset), @@ -44873,6 +44882,7 @@ module el2_ifu( .io_ifu_i0_dbecc(aln_ctl_ch_io_ifu_i0_dbecc), .io_ifu_i0_instr(aln_ctl_ch_io_ifu_i0_instr), .io_ifu_i0_pc(aln_ctl_ch_io_ifu_i0_pc), + .io_ifu_i0_pc4(aln_ctl_ch_io_ifu_i0_pc4), .io_ifu_fb_consume1(aln_ctl_ch_io_ifu_fb_consume1), .io_ifu_fb_consume2(aln_ctl_ch_io_ifu_fb_consume2), .io_ifu_i0_bp_index(aln_ctl_ch_io_ifu_i0_bp_index), @@ -44881,13 +44891,13 @@ module el2_ifu( .io_ifu_pmu_instr_aligned(aln_ctl_ch_io_ifu_pmu_instr_aligned), .io_ifu_i0_cinst(aln_ctl_ch_io_ifu_i0_cinst), .io_i0_brp_valid(aln_ctl_ch_io_i0_brp_valid), - .io_i0_brp_bits_toffset(aln_ctl_ch_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(aln_ctl_ch_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(aln_ctl_ch_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(aln_ctl_ch_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_prett(aln_ctl_ch_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(aln_ctl_ch_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(aln_ctl_ch_io_i0_brp_bits_ret) + .io_i0_brp_toffset(aln_ctl_ch_io_i0_brp_toffset), + .io_i0_brp_hist(aln_ctl_ch_io_i0_brp_hist), + .io_i0_brp_br_error(aln_ctl_ch_io_i0_brp_br_error), + .io_i0_brp_br_start_error(aln_ctl_ch_io_i0_brp_br_start_error), + .io_i0_brp_prett(aln_ctl_ch_io_i0_brp_prett), + .io_i0_brp_way(aln_ctl_ch_io_i0_brp_way), + .io_i0_brp_ret(aln_ctl_ch_io_i0_brp_ret) ); el2_ifu_ifc_ctl ifc_ctl_ch ( // @[el2_ifu.scala 149:26] .clock(ifc_ctl_ch_clock), @@ -44965,15 +44975,16 @@ module el2_ifu( assign io_iccm_dma_sb_error = mem_ctl_ch_io_iccm_dma_sb_error; // @[el2_ifu.scala 325:24] assign io_ifu_i0_instr = aln_ctl_ch_io_ifu_i0_instr; // @[el2_ifu.scala 326:19] assign io_ifu_i0_pc = aln_ctl_ch_io_ifu_i0_pc; // @[el2_ifu.scala 327:16] + assign io_ifu_i0_pc4 = aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 328:17] assign io_ifu_miss_state_idle = mem_ctl_ch_io_ifu_miss_state_idle; // @[el2_ifu.scala 329:26] assign io_i0_brp_valid = aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_toffset = aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_hist = aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_br_error = aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_br_start_error = aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_prett = aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_way = aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_ret = aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 331:13] + assign io_i0_brp_toffset = aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 331:13] + assign io_i0_brp_hist = aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 331:13] + assign io_i0_brp_br_error = aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 331:13] + assign io_i0_brp_br_start_error = aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 331:13] + assign io_i0_brp_prett = aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 331:13] + assign io_i0_brp_way = aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 331:13] + assign io_i0_brp_ret = aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 331:13] assign io_ifu_i0_bp_index = aln_ctl_ch_io_ifu_i0_bp_index; // @[el2_ifu.scala 332:22] assign io_ifu_i0_bp_fghr = aln_ctl_ch_io_ifu_i0_bp_fghr; // @[el2_ifu.scala 333:21] assign io_ifu_i0_bp_btag = aln_ctl_ch_io_ifu_i0_bp_btag; // @[el2_ifu.scala 334:21] @@ -45034,11 +45045,11 @@ module el2_ifu( assign bp_ctl_ch_io_ifc_fetch_addr_f = ifc_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 196:33] assign bp_ctl_ch_io_ifc_fetch_req_f = ifc_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 197:32] assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid = io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist = io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error = io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error = io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way = io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle = io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist = io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error = io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error = io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_way = io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle = io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 198:34] assign bp_ctl_ch_io_exu_i0_br_fghr_r = io_exu_i0_br_fghr_r; // @[el2_ifu.scala 199:33] assign bp_ctl_ch_io_exu_i0_br_index_r = io_exu_i0_br_index_r; // @[el2_ifu.scala 200:34] assign bp_ctl_ch_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 201:39] @@ -45046,6 +45057,7 @@ module el2_ifu( assign bp_ctl_ch_io_dec_tlu_bpred_disable = io_dec_tlu_bpred_disable; // @[el2_ifu.scala 203:38] assign bp_ctl_ch_io_exu_mp_pkt_bits_misp = io_exu_mp_pkt_bits_misp; // @[el2_ifu.scala 204:27] assign bp_ctl_ch_io_exu_mp_pkt_bits_ataken = io_exu_mp_pkt_bits_ataken; // @[el2_ifu.scala 204:27] + assign bp_ctl_ch_io_exu_mp_pkt_bits_boffset = io_exu_mp_pkt_bits_boffset; // @[el2_ifu.scala 204:27] assign bp_ctl_ch_io_exu_mp_pkt_bits_pc4 = io_exu_mp_pkt_bits_pc4; // @[el2_ifu.scala 204:27] assign bp_ctl_ch_io_exu_mp_pkt_bits_hist = io_exu_mp_pkt_bits_hist; // @[el2_ifu.scala 204:27] assign bp_ctl_ch_io_exu_mp_pkt_bits_toffset = io_exu_mp_pkt_bits_toffset; // @[el2_ifu.scala 204:27] @@ -45106,16 +45118,17 @@ module el2_dec_ib_ctl( input [1:0] io_dbg_cmd_type, input [31:0] io_dbg_cmd_addr, input io_i0_brp_valid, - input [11:0] io_i0_brp_bits_toffset, - input [1:0] io_i0_brp_bits_hist, - input io_i0_brp_bits_br_error, - input io_i0_brp_bits_br_start_error, - input [30:0] io_i0_brp_bits_prett, - input io_i0_brp_bits_way, - input io_i0_brp_bits_ret, + input [11:0] io_i0_brp_toffset, + input [1:0] io_i0_brp_hist, + input io_i0_brp_br_error, + input io_i0_brp_br_start_error, + input [30:0] io_i0_brp_prett, + input io_i0_brp_way, + input io_i0_brp_ret, input [7:0] io_ifu_i0_bp_index, input [7:0] io_ifu_i0_bp_fghr, input [4:0] io_ifu_i0_bp_btag, + input io_ifu_i0_pc4, input io_ifu_i0_valid, input io_ifu_i0_icaf, input [1:0] io_ifu_i0_icaf_type, @@ -45127,14 +45140,15 @@ module el2_dec_ib_ctl( output [1:0] io_dec_i0_icaf_type_d, output [31:0] io_dec_i0_instr_d, output [30:0] io_dec_i0_pc_d, + output io_dec_i0_pc4_d, output io_dec_i0_brp_valid, - output [11:0] io_dec_i0_brp_bits_toffset, - output [1:0] io_dec_i0_brp_bits_hist, - output io_dec_i0_brp_bits_br_error, - output io_dec_i0_brp_bits_br_start_error, - output [30:0] io_dec_i0_brp_bits_prett, - output io_dec_i0_brp_bits_way, - output io_dec_i0_brp_bits_ret, + output [11:0] io_dec_i0_brp_toffset, + output [1:0] io_dec_i0_brp_hist, + output io_dec_i0_brp_br_error, + output io_dec_i0_brp_br_start_error, + output [30:0] io_dec_i0_brp_prett, + output io_dec_i0_brp_way, + output io_dec_i0_brp_ret, output [7:0] io_dec_i0_bp_index, output [7:0] io_dec_i0_bp_fghr, output [4:0] io_dec_i0_bp_btag, @@ -45144,51 +45158,55 @@ module el2_dec_ib_ctl( output io_dec_debug_wdata_rs1_d, output io_dec_debug_fence_d ); - wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 66:60] - wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 66:41] - wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 67:38] - wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 67:36] - wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 68:36] - wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 70:55] - wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 70:37] - wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 71:37] - wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 72:55] - wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 72:37] - wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 73:37] - wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 75:40] - wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 76:40] + wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 31:60] + wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 31:41] + wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 32:38] + wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 32:36] + wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 33:36] + wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 35:55] + wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 35:37] + wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 36:37] + wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 37:55] + wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 37:37] + wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 38:37] + wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 40:40] + wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 41:40] wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58] - wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58] - wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58] - wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58] + wire [13:0] _T_12 = {3'h6,dreg,6'h33}; // @[Cat.scala 29:58] + wire [25:0] _T_14 = {dcsr,14'h2073}; // @[Cat.scala 29:58] + wire [24:0] _T_16 = {dcsr,13'h1073}; // @[Cat.scala 29:58] wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] - wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] - wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72] - wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 89:51] - assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 91:22] - assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 48:31] - assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 92:22] - assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 46:31] - assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 50:31] - assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 51:31] - assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 52:31] - assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 45:31] - assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 43:31] - assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 44:31] - assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 86:28] - assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 89:24] + wire [13:0] _T_18 = debug_write_gpr ? _T_12 : 14'h0; // @[Mux.scala 27:72] + wire [25:0] _T_19 = debug_read_csr ? _T_14 : 26'h0; // @[Mux.scala 27:72] + wire [24:0] _T_20 = debug_write_csr ? _T_16 : 25'h0; // @[Mux.scala 27:72] + wire [31:0] _GEN_0 = {{18'd0}, _T_18}; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_17 | _GEN_0; // @[Mux.scala 27:72] + wire [31:0] _GEN_1 = {{6'd0}, _T_19}; // @[Mux.scala 27:72] + wire [31:0] _T_22 = _T_21 | _GEN_1; // @[Mux.scala 27:72] + wire [31:0] _GEN_2 = {{7'd0}, _T_20}; // @[Mux.scala 27:72] + wire [31:0] ib0_debug_in = _T_22 | _GEN_2; // @[Mux.scala 27:72] + wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 54:51] + assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 56:22] + assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 13:31] + assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 57:22] + assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31] + assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31] + assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31] + assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31] + assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31] + assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 10:31] + assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 8:31] + assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 9:31] + assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 51:28] + assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 54:24] endmodule module el2_dec_dec_ctl( input [31:0] io_ins, @@ -45199,6 +45217,7 @@ module el2_dec_dec_ctl( output io_out_rd, output io_out_shimm5, output io_out_imm20, + output io_out_pc, output io_out_load, output io_out_store, output io_out_lsu, @@ -45242,653 +45261,661 @@ module el2_dec_dec_ctl( output io_out_pm_alu, output io_out_legal ); - wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 72:27] - wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 72:42] - wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:53] - wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 72:39] - wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 72:68] - wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:78] - wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 73:51] - wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 73:51] - wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 73:90] - wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 73:90] - wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 73:55] - wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 74:37] - wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 74:37] - wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 73:94] - wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 74:76] - wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 74:76] - wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 74:41] - wire _T_45 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_49 = _T_45 & io_ins[13]; // @[el2_dec_dec_ctl.scala 75:38] - wire _T_50 = _T_49 & _T_18; // @[el2_dec_dec_ctl.scala 75:38] - wire _T_51 = _T_43 | _T_50; // @[el2_dec_dec_ctl.scala 74:80] - wire _T_57 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 75:76] - wire _T_58 = _T_57 & _T_18; // @[el2_dec_dec_ctl.scala 75:76] - wire _T_59 = _T_51 | _T_58; // @[el2_dec_dec_ctl.scala 75:42] - wire _T_64 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 76:37] - wire _T_65 = _T_64 & _T_18; // @[el2_dec_dec_ctl.scala 76:37] - wire _T_66 = _T_59 | _T_65; // @[el2_dec_dec_ctl.scala 75:80] - wire _T_72 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 76:75] - wire _T_73 = _T_72 & _T_18; // @[el2_dec_dec_ctl.scala 76:75] - wire _T_74 = _T_66 | _T_73; // @[el2_dec_dec_ctl.scala 76:41] - wire _T_79 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 77:37] - wire _T_80 = _T_79 & _T_18; // @[el2_dec_dec_ctl.scala 77:37] - wire _T_81 = _T_74 | _T_80; // @[el2_dec_dec_ctl.scala 76:79] - wire _T_87 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 77:75] - wire _T_88 = _T_87 & _T_18; // @[el2_dec_dec_ctl.scala 77:75] - wire _T_89 = _T_81 | _T_88; // @[el2_dec_dec_ctl.scala 77:41] - wire _T_94 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 78:37] - wire _T_95 = _T_94 & _T_18; // @[el2_dec_dec_ctl.scala 78:37] - wire _T_96 = _T_89 | _T_95; // @[el2_dec_dec_ctl.scala 77:79] - wire _T_98 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_100 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_101 = _T_98 & _T_100; // @[el2_dec_dec_ctl.scala 78:71] - wire _T_102 = _T_96 | _T_101; // @[el2_dec_dec_ctl.scala 78:41] - wire _T_104 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_107 = _T_104 & _T_18; // @[el2_dec_dec_ctl.scala 78:106] - wire _T_114 = io_ins[5] & _T_98; // @[el2_dec_dec_ctl.scala 79:48] - wire _T_115 = _T_114 & _T_18; // @[el2_dec_dec_ctl.scala 79:48] - wire _T_121 = _T_104 & io_ins[5]; // @[el2_dec_dec_ctl.scala 79:85] - wire _T_122 = _T_121 & _T_18; // @[el2_dec_dec_ctl.scala 79:85] - wire _T_130 = _T_101 & io_ins[2]; // @[el2_dec_dec_ctl.scala 80:50] - wire _T_137 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 80:90] - wire _T_138 = _T_137 & io_ins[4]; // @[el2_dec_dec_ctl.scala 80:90] - wire _T_139 = _T_138 & _T_18; // @[el2_dec_dec_ctl.scala 80:90] - wire _T_140 = _T_130 | _T_139; // @[el2_dec_dec_ctl.scala 80:54] - wire _T_144 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_147 = _T_16 & _T_144; // @[el2_dec_dec_ctl.scala 81:40] - wire _T_148 = _T_147 & io_ins[6]; // @[el2_dec_dec_ctl.scala 81:40] - wire _T_149 = _T_148 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:40] - wire _T_150 = _T_140 | _T_149; // @[el2_dec_dec_ctl.scala 80:94] - wire _T_158 = _T_144 & _T_9; // @[el2_dec_dec_ctl.scala 81:81] - wire _T_159 = _T_158 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:81] - wire _T_160 = _T_159 & _T_18; // @[el2_dec_dec_ctl.scala 81:81] - wire _T_166 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 82:28] - wire _T_169 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 82:55] - wire _T_170 = _T_166 | _T_169; // @[el2_dec_dec_ctl.scala 82:42] - wire _T_181 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 83:58] - wire _T_182 = _T_181 & _T_9; // @[el2_dec_dec_ctl.scala 83:58] - wire _T_183 = _T_182 & io_ins[4]; // @[el2_dec_dec_ctl.scala 83:58] - wire _T_187 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 84:29] - wire _T_190 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 84:53] - wire _T_196 = _T_9 & _T_100; // @[el2_dec_dec_ctl.scala 85:28] - wire _T_198 = _T_196 & io_ins[2]; // @[el2_dec_dec_ctl.scala 85:41] - wire _T_209 = _T_9 & _T_98; // @[el2_dec_dec_ctl.scala 86:50] - wire _T_224 = _T_104 & _T_98; // @[el2_dec_dec_ctl.scala 88:49] - wire _T_236 = _T_19 & _T_144; // @[el2_dec_dec_ctl.scala 89:57] - wire _T_237 = _T_236 & _T_9; // @[el2_dec_dec_ctl.scala 89:57] - wire _T_238 = _T_237 & io_ins[4]; // @[el2_dec_dec_ctl.scala 89:57] - wire _T_246 = _T_238 | _T_198; // @[el2_dec_dec_ctl.scala 89:61] - wire _T_248 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_262 = _T_248 & _T_4; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_263 = _T_262 & _T_14; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_264 = _T_263 & _T_16; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_265 = _T_264 & _T_144; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_266 = _T_265 & _T_104; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_267 = _T_266 & io_ins[4]; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_268 = _T_267 & _T_18; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_279 = io_ins[30] & _T_144; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_280 = _T_279 & _T_104; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_281 = _T_280 & io_ins[5]; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_282 = _T_281 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_283 = _T_282 & _T_18; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_294 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_295 = _T_294 & io_ins[13]; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_296 = _T_295 & _T_104; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_297 = _T_296 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_298 = _T_297 & _T_18; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_299 = _T_283 | _T_298; // @[el2_dec_dec_ctl.scala 91:61] - wire _T_308 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_309 = _T_308 & _T_9; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_310 = _T_309 & io_ins[4]; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_311 = _T_310 & _T_18; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_312 = _T_299 | _T_311; // @[el2_dec_dec_ctl.scala 91:109] - wire _T_318 = io_ins[6] & _T_98; // @[el2_dec_dec_ctl.scala 92:80] - wire _T_319 = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 92:80] - wire _T_328 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_329 = _T_328 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_330 = _T_329 & _T_9; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_331 = _T_330 & _T_18; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_341 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_342 = _T_341 & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_343 = _T_342 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_344 = _T_343 & _T_104; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_345 = _T_344 & _T_18; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_350 = _T_104 & io_ins[3]; // @[el2_dec_dec_ctl.scala 94:45] - wire _T_363 = _T_342 & _T_144; // @[el2_dec_dec_ctl.scala 94:94] - wire _T_364 = _T_363 & _T_104; // @[el2_dec_dec_ctl.scala 94:94] - wire _T_365 = _T_364 & _T_18; // @[el2_dec_dec_ctl.scala 94:94] - wire _T_366 = _T_350 | _T_365; // @[el2_dec_dec_ctl.scala 94:49] - wire _T_370 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 95:34] - wire _T_371 = _T_370 & io_ins[2]; // @[el2_dec_dec_ctl.scala 95:34] - wire _T_372 = _T_366 | _T_371; // @[el2_dec_dec_ctl.scala 94:98] - wire _T_382 = _T_372 | _T_149; // @[el2_dec_dec_ctl.scala 95:38] - wire _T_392 = _T_328 & _T_144; // @[el2_dec_dec_ctl.scala 96:44] - wire _T_393 = _T_392 & _T_9; // @[el2_dec_dec_ctl.scala 96:44] - wire _T_394 = _T_393 & _T_18; // @[el2_dec_dec_ctl.scala 96:44] - wire _T_407 = _T_341 & _T_16; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_408 = _T_407 & _T_144; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_409 = _T_408 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_410 = _T_409 & _T_18; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_421 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_422 = _T_421 & _T_144; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_423 = _T_422 & _T_9; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_424 = _T_423 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_425 = _T_424 & _T_18; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_440 = _T_294 & _T_16; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_441 = _T_440 & io_ins[12]; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_442 = _T_441 & _T_104; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_443 = _T_442 & io_ins[4]; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_454 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_455 = _T_454 & io_ins[12]; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_456 = _T_455 & _T_104; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_457 = _T_456 & io_ins[4]; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_473 = _T_262 & io_ins[14]; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_474 = _T_473 & _T_16; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_475 = _T_474 & io_ins[12]; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_476 = _T_475 & _T_104; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_477 = _T_476 & io_ins[4]; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_492 = _T_295 & io_ins[12]; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_493 = _T_492 & _T_104; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_494 = _T_493 & io_ins[4]; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_495 = _T_494 & _T_18; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_518 = _T_308 & io_ins[12]; // @[el2_dec_dec_ctl.scala 102:59] - wire _T_519 = _T_518 & _T_9; // @[el2_dec_dec_ctl.scala 102:59] - wire _T_520 = _T_519 & _T_18; // @[el2_dec_dec_ctl.scala 102:59] - wire _T_527 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 102:99] - wire _T_528 = _T_527 & _T_98; // @[el2_dec_dec_ctl.scala 102:99] - wire _T_529 = _T_528 & _T_18; // @[el2_dec_dec_ctl.scala 102:99] - wire _T_530 = _T_520 | _T_529; // @[el2_dec_dec_ctl.scala 102:63] - wire _T_536 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 103:37] - wire _T_537 = _T_536 & _T_98; // @[el2_dec_dec_ctl.scala 103:37] - wire _T_538 = _T_530 | _T_537; // @[el2_dec_dec_ctl.scala 102:103] - wire _T_553 = _T_493 & _T_18; // @[el2_dec_dec_ctl.scala 103:86] - wire _T_554 = _T_538 | _T_553; // @[el2_dec_dec_ctl.scala 103:41] - wire _T_563 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_564 = _T_563 & io_ins[12]; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_565 = _T_564 & _T_104; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_566 = _T_565 & io_ins[5]; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_567 = _T_566 & _T_18; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_585 = _T_14 & _T_144; // @[el2_dec_dec_ctl.scala 106:56] - wire _T_586 = _T_585 & io_ins[6]; // @[el2_dec_dec_ctl.scala 106:56] - wire _T_587 = _T_586 & _T_98; // @[el2_dec_dec_ctl.scala 106:56] - wire _T_597 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 107:55] - wire _T_598 = _T_597 & io_ins[6]; // @[el2_dec_dec_ctl.scala 107:55] - wire _T_599 = _T_598 & _T_98; // @[el2_dec_dec_ctl.scala 107:55] - wire _T_608 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 108:54] - wire _T_609 = _T_608 & io_ins[5]; // @[el2_dec_dec_ctl.scala 108:54] - wire _T_610 = _T_609 & _T_98; // @[el2_dec_dec_ctl.scala 108:54] - wire _T_620 = io_ins[14] & _T_144; // @[el2_dec_dec_ctl.scala 109:55] - wire _T_621 = _T_620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 109:55] - wire _T_622 = _T_621 & _T_98; // @[el2_dec_dec_ctl.scala 109:55] - wire _T_638 = _T_147 & _T_104; // @[el2_dec_dec_ctl.scala 111:56] - wire _T_639 = _T_638 & _T_98; // @[el2_dec_dec_ctl.scala 111:56] - wire _T_648 = io_ins[12] & _T_104; // @[el2_dec_dec_ctl.scala 112:53] - wire _T_649 = _T_648 & _T_98; // @[el2_dec_dec_ctl.scala 112:53] - wire _T_656 = io_ins[13] & _T_104; // @[el2_dec_dec_ctl.scala 113:50] - wire _T_662 = _T_527 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:52] - wire _T_666 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 114:87] - wire _T_667 = _T_666 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:87] - wire _T_668 = _T_662 | _T_667; // @[el2_dec_dec_ctl.scala 114:56] - wire _T_672 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:34] - wire _T_673 = _T_672 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:34] - wire _T_674 = _T_668 | _T_673; // @[el2_dec_dec_ctl.scala 114:91] - wire _T_678 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:69] - wire _T_679 = _T_678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:69] - wire _T_680 = _T_674 | _T_679; // @[el2_dec_dec_ctl.scala 115:38] - wire _T_684 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:105] - wire _T_685 = _T_684 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:105] - wire _T_686 = _T_680 | _T_685; // @[el2_dec_dec_ctl.scala 115:73] - wire _T_690 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 116:35] - wire _T_691 = _T_690 & io_ins[4]; // @[el2_dec_dec_ctl.scala 116:35] - wire _T_699 = _T_94 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:57] - wire _T_700 = _T_699 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:57] - wire _T_701 = _T_700 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:57] - wire _T_708 = _T_79 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:99] - wire _T_709 = _T_708 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:99] - wire _T_710 = _T_709 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:99] - wire _T_711 = _T_701 | _T_710; // @[el2_dec_dec_ctl.scala 117:61] - wire _T_718 = _T_64 & io_ins[12]; // @[el2_dec_dec_ctl.scala 118:41] - wire _T_719 = _T_718 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:41] - wire _T_720 = _T_719 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:41] - wire _T_721 = _T_711 | _T_720; // @[el2_dec_dec_ctl.scala 117:103] - wire _T_727 = io_ins[18] & _T_144; // @[el2_dec_dec_ctl.scala 118:81] - wire _T_728 = _T_727 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:81] - wire _T_729 = _T_728 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:81] - wire _T_730 = _T_721 | _T_729; // @[el2_dec_dec_ctl.scala 118:45] - wire _T_736 = io_ins[19] & _T_144; // @[el2_dec_dec_ctl.scala 119:39] - wire _T_737 = _T_736 & io_ins[6]; // @[el2_dec_dec_ctl.scala 119:39] - wire _T_738 = _T_737 & io_ins[4]; // @[el2_dec_dec_ctl.scala 119:39] - wire _T_746 = _T_181 & io_ins[6]; // @[el2_dec_dec_ctl.scala 120:57] - wire _T_754 = _T_421 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:55] - wire _T_755 = _T_754 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:55] - wire _T_760 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 121:94] - wire _T_761 = _T_760 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:94] - wire _T_762 = _T_761 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:94] - wire _T_763 = _T_755 | _T_762; // @[el2_dec_dec_ctl.scala 121:59] - wire _T_768 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:38] - wire _T_769 = _T_768 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:38] - wire _T_770 = _T_769 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:38] - wire _T_771 = _T_763 | _T_770; // @[el2_dec_dec_ctl.scala 121:98] - wire _T_776 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:77] - wire _T_777 = _T_776 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:77] - wire _T_778 = _T_777 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:77] - wire _T_779 = _T_771 | _T_778; // @[el2_dec_dec_ctl.scala 122:42] - wire _T_784 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:38] - wire _T_785 = _T_784 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:38] - wire _T_786 = _T_785 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:38] - wire _T_787 = _T_779 | _T_786; // @[el2_dec_dec_ctl.scala 122:81] - wire _T_792 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:77] - wire _T_793 = _T_792 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:77] - wire _T_794 = _T_793 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:77] - wire _T_801 = io_ins[15] & _T_144; // @[el2_dec_dec_ctl.scala 124:55] - wire _T_802 = _T_801 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:55] - wire _T_803 = _T_802 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:55] - wire _T_809 = io_ins[16] & _T_144; // @[el2_dec_dec_ctl.scala 124:95] - wire _T_810 = _T_809 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:95] - wire _T_811 = _T_810 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:95] - wire _T_812 = _T_803 | _T_811; // @[el2_dec_dec_ctl.scala 124:59] - wire _T_818 = io_ins[17] & _T_144; // @[el2_dec_dec_ctl.scala 125:39] - wire _T_819 = _T_818 & io_ins[6]; // @[el2_dec_dec_ctl.scala 125:39] - wire _T_820 = _T_819 & io_ins[4]; // @[el2_dec_dec_ctl.scala 125:39] - wire _T_821 = _T_812 | _T_820; // @[el2_dec_dec_ctl.scala 124:99] - wire _T_830 = _T_821 | _T_729; // @[el2_dec_dec_ctl.scala 125:43] - wire _T_841 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_849 = _T_841 & io_ins[20]; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_850 = _T_849 & _T_16; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_851 = _T_850 & _T_144; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_852 = _T_851 & io_ins[6]; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_855 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_857 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_864 = _T_855 & _T_857; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_865 = _T_864 & _T_16; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_866 = _T_865 & _T_144; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_867 = _T_866 & io_ins[6]; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_876 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 129:56] - wire _T_877 = _T_876 & _T_144; // @[el2_dec_dec_ctl.scala 129:56] - wire _T_878 = _T_877 & io_ins[6]; // @[el2_dec_dec_ctl.scala 129:56] - wire _T_889 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_890 = _T_889 & _T_104; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_891 = _T_890 & io_ins[5]; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_892 = _T_891 & io_ins[4]; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_907 = _T_889 & io_ins[13]; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_908 = _T_907 & _T_144; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_909 = _T_908 & _T_104; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_910 = _T_909 & io_ins[5]; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_911 = _T_910 & io_ins[4]; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_912 = _T_911 & _T_18; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_925 = _T_889 & _T_16; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_926 = _T_925 & io_ins[12]; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_927 = _T_926 & _T_104; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_928 = _T_927 & io_ins[4]; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_929 = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_961 = _T_925 & _T_144; // @[el2_dec_dec_ctl.scala 134:62] - wire _T_962 = _T_961 & io_ins[5]; // @[el2_dec_dec_ctl.scala 134:62] - wire _T_963 = _T_962 & io_ins[4]; // @[el2_dec_dec_ctl.scala 134:62] - wire _T_973 = _T_563 & _T_104; // @[el2_dec_dec_ctl.scala 135:54] - wire _T_974 = _T_973 & io_ins[5]; // @[el2_dec_dec_ctl.scala 135:54] - wire _T_985 = _T_563 & io_ins[13]; // @[el2_dec_dec_ctl.scala 136:57] - wire _T_986 = _T_985 & _T_104; // @[el2_dec_dec_ctl.scala 136:57] - wire _T_987 = _T_986 & io_ins[5]; // @[el2_dec_dec_ctl.scala 136:57] - wire _T_992 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:47] - wire _T_997 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 138:52] - wire _T_998 = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:52] - wire _T_1006 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1007 = _T_1006 & _T_16; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1008 = _T_1007 & _T_144; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1009 = _T_1008 & io_ins[4]; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1013 = _T_1009 | _T_190; // @[el2_dec_dec_ctl.scala 139:63] - wire _T_1019 = _T_4 & _T_104; // @[el2_dec_dec_ctl.scala 140:37] - wire _T_1020 = _T_1019 & io_ins[4]; // @[el2_dec_dec_ctl.scala 140:37] - wire _T_1021 = _T_1013 | _T_1020; // @[el2_dec_dec_ctl.scala 139:96] - wire _T_1037 = _T_87 & io_ins[6]; // @[el2_dec_dec_ctl.scala 141:88] - wire _T_1038 = _T_1037 & io_ins[4]; // @[el2_dec_dec_ctl.scala 141:88] - wire _T_1039 = _T_992 | _T_1038; // @[el2_dec_dec_ctl.scala 141:53] - wire _T_1046 = _T_72 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:38] - wire _T_1047 = _T_1046 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:38] - wire _T_1048 = _T_1039 | _T_1047; // @[el2_dec_dec_ctl.scala 141:92] - wire _T_1055 = _T_57 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:77] - wire _T_1056 = _T_1055 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:77] - wire _T_1057 = _T_1048 | _T_1056; // @[el2_dec_dec_ctl.scala 142:42] - wire _T_1066 = _T_1057 | _T_1056; // @[el2_dec_dec_ctl.scala 142:81] - wire _T_1073 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 143:78] - wire _T_1074 = _T_1073 & io_ins[4]; // @[el2_dec_dec_ctl.scala 143:78] - wire _T_1075 = _T_1066 | _T_1074; // @[el2_dec_dec_ctl.scala 143:42] - wire _T_1082 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:39] - wire _T_1083 = _T_1082 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:39] - wire _T_1084 = _T_1075 | _T_1083; // @[el2_dec_dec_ctl.scala 143:82] - wire _T_1090 = _T_94 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:78] - wire _T_1091 = _T_1090 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:78] - wire _T_1092 = _T_1084 | _T_1091; // @[el2_dec_dec_ctl.scala 144:43] - wire _T_1098 = _T_79 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:38] - wire _T_1099 = _T_1098 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:38] - wire _T_1100 = _T_1092 | _T_1099; // @[el2_dec_dec_ctl.scala 144:82] - wire _T_1106 = _T_64 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:77] - wire _T_1107 = _T_1106 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:77] - wire _T_1108 = _T_1100 | _T_1107; // @[el2_dec_dec_ctl.scala 145:42] - wire _T_1113 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 146:38] - wire _T_1114 = _T_1113 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:38] - wire _T_1115 = _T_1114 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:38] - wire _T_1116 = _T_1108 | _T_1115; // @[el2_dec_dec_ctl.scala 145:81] - wire _T_1122 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:77] - wire _T_1123 = _T_1122 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:77] - wire _T_1139 = _T_841 & _T_16; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1140 = _T_1139 & _T_144; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1141 = _T_1140 & io_ins[6]; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1142 = _T_1141 & io_ins[4]; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1143 = _T_998 | _T_1142; // @[el2_dec_dec_ctl.scala 147:57] - wire _T_1152 = _T_1143 | _T_1038; // @[el2_dec_dec_ctl.scala 147:102] - wire _T_1161 = _T_1152 | _T_1047; // @[el2_dec_dec_ctl.scala 148:42] - wire _T_1170 = _T_1161 | _T_1056; // @[el2_dec_dec_ctl.scala 148:81] - wire _T_1179 = _T_1170 | _T_1074; // @[el2_dec_dec_ctl.scala 149:42] - wire _T_1188 = _T_1179 | _T_1083; // @[el2_dec_dec_ctl.scala 149:82] - wire _T_1196 = _T_1188 | _T_1091; // @[el2_dec_dec_ctl.scala 150:43] - wire _T_1204 = _T_1196 | _T_1099; // @[el2_dec_dec_ctl.scala 150:82] - wire _T_1212 = _T_1204 | _T_1107; // @[el2_dec_dec_ctl.scala 151:42] - wire _T_1220 = _T_1212 | _T_1115; // @[el2_dec_dec_ctl.scala 151:81] - wire _T_1230 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1236 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1238 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1242 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1244 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1251 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1255 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1257 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1259 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1263 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1265 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1267 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1269 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1271 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1281 = ~io_ins[0]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1282 = _T_1230 & _T_248; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1283 = _T_1282 & io_ins[29]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1284 = _T_1283 & io_ins[28]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1285 = _T_1284 & _T_1236; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1286 = _T_1285 & _T_1238; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1287 = _T_1286 & _T_4; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1288 = _T_1287 & _T_1242; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1289 = _T_1288 & _T_1244; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1290 = _T_1289 & _T_841; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1291 = _T_1290 & io_ins[21]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1292 = _T_1291 & _T_857; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1293 = _T_1292 & _T_1251; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1294 = _T_1293 & _T_45; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1295 = _T_1294 & _T_1255; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1296 = _T_1295 & _T_1257; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1297 = _T_1296 & _T_1259; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1298 = _T_1297 & _T_14; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1299 = _T_1298 & _T_1263; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1300 = _T_1299 & _T_1265; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1301 = _T_1300 & _T_1267; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1302 = _T_1301 & _T_1269; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1303 = _T_1302 & _T_1271; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1304 = _T_1303 & io_ins[6]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1305 = _T_1304 & io_ins[5]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1306 = _T_1305 & io_ins[4]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1307 = _T_1306 & _T_100; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1308 = _T_1307 & _T_18; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1309 = _T_1308 & io_ins[1]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1310 = _T_1309 & _T_1281; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1316 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1365 = _T_1282 & _T_1316; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1366 = _T_1365 & io_ins[28]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1367 = _T_1366 & _T_1236; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1368 = _T_1367 & _T_1238; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1369 = _T_1368 & _T_4; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1370 = _T_1369 & _T_1242; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1371 = _T_1370 & _T_1244; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1372 = _T_1371 & io_ins[22]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1373 = _T_1372 & _T_855; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1374 = _T_1373 & io_ins[20]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1375 = _T_1374 & _T_1251; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1376 = _T_1375 & _T_45; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1377 = _T_1376 & _T_1255; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1378 = _T_1377 & _T_1257; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1379 = _T_1378 & _T_1259; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1380 = _T_1379 & _T_14; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1381 = _T_1380 & _T_1263; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1382 = _T_1381 & _T_1265; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1383 = _T_1382 & _T_1267; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1384 = _T_1383 & _T_1269; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1385 = _T_1384 & _T_1271; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1386 = _T_1385 & io_ins[6]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1387 = _T_1386 & io_ins[5]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1388 = _T_1387 & io_ins[4]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1389 = _T_1388 & _T_100; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1390 = _T_1389 & _T_18; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1391 = _T_1390 & io_ins[1]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1392 = _T_1391 & _T_1281; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1393 = _T_1310 | _T_1392; // @[el2_dec_dec_ctl.scala 153:148] - wire _T_1401 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1449 = _T_1365 & _T_1401; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1450 = _T_1449 & _T_1236; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1451 = _T_1450 & _T_1238; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1452 = _T_1451 & _T_4; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1453 = _T_1452 & _T_1242; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1454 = _T_1453 & _T_1244; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1455 = _T_1454 & _T_841; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1456 = _T_1455 & _T_855; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1457 = _T_1456 & _T_1251; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1458 = _T_1457 & _T_45; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1459 = _T_1458 & _T_1255; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1460 = _T_1459 & _T_1257; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1461 = _T_1460 & _T_1259; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1462 = _T_1461 & _T_14; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1463 = _T_1462 & _T_1263; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1464 = _T_1463 & _T_1265; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1465 = _T_1464 & _T_1267; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1466 = _T_1465 & _T_1269; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1467 = _T_1466 & _T_1271; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1468 = _T_1467 & io_ins[5]; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1469 = _T_1468 & io_ins[4]; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1470 = _T_1469 & _T_100; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1471 = _T_1470 & _T_18; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1472 = _T_1471 & io_ins[1]; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1473 = _T_1472 & _T_1281; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1474 = _T_1393 | _T_1473; // @[el2_dec_dec_ctl.scala 154:134] - wire _T_1503 = _T_1452 & _T_104; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1504 = _T_1503 & io_ins[4]; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1505 = _T_1504 & _T_100; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1506 = _T_1505 & io_ins[1]; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1507 = _T_1506 & _T_1281; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1508 = _T_1474 | _T_1507; // @[el2_dec_dec_ctl.scala 155:131] - wire _T_1536 = _T_1230 & _T_1316; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1537 = _T_1536 & _T_1401; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1538 = _T_1537 & _T_1236; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1539 = _T_1538 & _T_1238; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1540 = _T_1539 & _T_4; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1541 = _T_1540 & _T_14; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1542 = _T_1541 & _T_16; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1543 = _T_1542 & _T_144; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1544 = _T_1543 & _T_104; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1545 = _T_1544 & _T_100; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1546 = _T_1545 & _T_18; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1547 = _T_1546 & io_ins[1]; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1548 = _T_1547 & _T_1281; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1549 = _T_1508 | _T_1548; // @[el2_dec_dec_ctl.scala 156:72] - wire _T_1579 = _T_1540 & io_ins[14]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1580 = _T_1579 & _T_16; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1581 = _T_1580 & io_ins[12]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1582 = _T_1581 & _T_104; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1583 = _T_1582 & io_ins[4]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1584 = _T_1583 & _T_100; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1585 = _T_1584 & io_ins[1]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1586 = _T_1585 & _T_1281; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1587 = _T_1549 | _T_1586; // @[el2_dec_dec_ctl.scala 157:81] - wire _T_1614 = _T_1451 & _T_104; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1615 = _T_1614 & io_ins[5]; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1616 = _T_1615 & io_ins[4]; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1617 = _T_1616 & _T_100; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1618 = _T_1617 & io_ins[1]; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1619 = _T_1618 & _T_1281; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1620 = _T_1587 | _T_1619; // @[el2_dec_dec_ctl.scala 158:78] - wire _T_1638 = _T_236 & io_ins[6]; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1640 = _T_1639 & _T_98; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1641 = _T_1640 & _T_100; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1642 = _T_1641 & io_ins[1]; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1643 = _T_1642 & _T_1281; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1644 = _T_1620 | _T_1643; // @[el2_dec_dec_ctl.scala 159:70] - wire _T_1657 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1658 = _T_1657 & io_ins[5]; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1659 = _T_1658 & _T_98; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1660 = _T_1659 & _T_100; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1661 = _T_1660 & _T_18; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1662 = _T_1661 & io_ins[1]; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1663 = _T_1662 & _T_1281; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1664 = _T_1644 | _T_1663; // @[el2_dec_dec_ctl.scala 160:58] - wire _T_1677 = _T_144 & _T_104; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1678 = _T_1677 & _T_9; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1679 = _T_1678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1680 = _T_1679 & _T_100; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1681 = _T_1680 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1682 = _T_1681 & _T_1281; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1683 = _T_1664 | _T_1682; // @[el2_dec_dec_ctl.scala 161:52] - wire _T_1699 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1700 = _T_1699 & _T_98; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1701 = _T_1700 & _T_100; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1702 = _T_1701 & _T_18; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1703 = _T_1702 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1704 = _T_1703 & _T_1281; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1705 = _T_1683 | _T_1704; // @[el2_dec_dec_ctl.scala 162:51] - wire _T_1717 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1718 = _T_1717 & io_ins[5]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1719 = _T_1718 & io_ins[4]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1720 = _T_1719 & _T_100; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1721 = _T_1720 & _T_18; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1722 = _T_1721 & io_ins[1]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1723 = _T_1722 & _T_1281; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1724 = _T_1705 | _T_1723; // @[el2_dec_dec_ctl.scala 162:103] - wire _T_1796 = _T_1456 & _T_857; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1797 = _T_1796 & _T_1251; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1798 = _T_1797 & _T_45; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1799 = _T_1798 & _T_1255; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1800 = _T_1799 & _T_1257; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1801 = _T_1800 & _T_1259; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1802 = _T_1801 & _T_14; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1803 = _T_1802 & _T_16; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1804 = _T_1803 & _T_144; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1805 = _T_1804 & _T_1263; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1806 = _T_1805 & _T_1265; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1807 = _T_1806 & _T_1267; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1808 = _T_1807 & _T_1269; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1809 = _T_1808 & _T_1271; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1810 = _T_1809 & _T_104; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1811 = _T_1810 & _T_9; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1812 = _T_1811 & _T_98; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1813 = _T_1812 & io_ins[3]; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1814 = _T_1813 & io_ins[2]; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1815 = _T_1814 & io_ins[1]; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1816 = _T_1815 & _T_1281; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1817 = _T_1724 | _T_1816; // @[el2_dec_dec_ctl.scala 163:51] - wire _T_1866 = _T_1449 & _T_1251; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1867 = _T_1866 & _T_45; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1868 = _T_1867 & _T_1255; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1869 = _T_1868 & _T_1257; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1870 = _T_1869 & _T_1259; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1871 = _T_1870 & _T_14; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1872 = _T_1871 & _T_16; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1873 = _T_1872 & _T_144; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1874 = _T_1873 & _T_1263; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1875 = _T_1874 & _T_1265; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1876 = _T_1875 & _T_1267; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1877 = _T_1876 & _T_1269; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1878 = _T_1877 & _T_1271; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1879 = _T_1878 & _T_104; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1880 = _T_1879 & _T_9; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1881 = _T_1880 & _T_98; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1882 = _T_1881 & io_ins[3]; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1883 = _T_1882 & io_ins[2]; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1884 = _T_1883 & io_ins[1]; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1885 = _T_1884 & _T_1281; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1886 = _T_1817 | _T_1885; // @[el2_dec_dec_ctl.scala 164:146] - wire _T_1902 = _T_16 & _T_104; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1903 = _T_1902 & _T_9; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1904 = _T_1903 & _T_98; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1905 = _T_1904 & _T_100; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1906 = _T_1905 & _T_18; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1907 = _T_1906 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1908 = _T_1907 & _T_1281; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1909 = _T_1886 | _T_1908; // @[el2_dec_dec_ctl.scala 165:114] - wire _T_1919 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1920 = _T_1919 & _T_98; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1921 = _T_1920 & io_ins[3]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1922 = _T_1921 & io_ins[2]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1923 = _T_1922 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1924 = _T_1923 & _T_1281; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1925 = _T_1909 | _T_1924; // @[el2_dec_dec_ctl.scala 166:55] - wire _T_1938 = _T_656 & _T_9; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1939 = _T_1938 & io_ins[4]; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1940 = _T_1939 & _T_100; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1941 = _T_1940 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1942 = _T_1941 & _T_1281; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1943 = _T_1925 | _T_1942; // @[el2_dec_dec_ctl.scala 166:99] - wire _T_1960 = _T_585 & _T_104; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1961 = _T_1960 & _T_98; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1962 = _T_1961 & _T_100; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1963 = _T_1962 & _T_18; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50] - wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43] - assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14] - assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14] - assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14] - assign io_out_imm12 = _T_150 | _T_160; // @[el2_dec_dec_ctl.scala 80:16] - assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13] - assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17] - assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16] - assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15] - assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16] - assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14] - assign io_out_add = _T_246 | _T_268; // @[el2_dec_dec_ctl.scala 89:14] - assign io_out_sub = _T_312 | _T_319; // @[el2_dec_dec_ctl.scala 91:14] - assign io_out_land = _T_331 | _T_345; // @[el2_dec_dec_ctl.scala 93:15] - assign io_out_lor = _T_382 | _T_394; // @[el2_dec_dec_ctl.scala 94:14] - assign io_out_lxor = _T_410 | _T_425; // @[el2_dec_dec_ctl.scala 97:15] - assign io_out_sll = _T_443 & _T_18; // @[el2_dec_dec_ctl.scala 98:14] - assign io_out_sra = _T_457 & _T_18; // @[el2_dec_dec_ctl.scala 99:14] - assign io_out_srl = _T_477 & _T_18; // @[el2_dec_dec_ctl.scala 100:14] - assign io_out_slt = _T_495 | _T_311; // @[el2_dec_dec_ctl.scala 101:14] - assign io_out_unsign = _T_554 | _T_567; // @[el2_dec_dec_ctl.scala 102:17] - assign io_out_condbr = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 105:17] - assign io_out_beq = _T_587 & _T_18; // @[el2_dec_dec_ctl.scala 106:14] - assign io_out_bne = _T_599 & _T_18; // @[el2_dec_dec_ctl.scala 107:14] - assign io_out_bge = _T_610 & _T_18; // @[el2_dec_dec_ctl.scala 108:14] - assign io_out_blt = _T_622 & _T_18; // @[el2_dec_dec_ctl.scala 109:14] - assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 110:14] - assign io_out_by = _T_639 & _T_18; // @[el2_dec_dec_ctl.scala 111:13] - assign io_out_half = _T_649 & _T_18; // @[el2_dec_dec_ctl.scala 112:15] - assign io_out_word = _T_656 & _T_98; // @[el2_dec_dec_ctl.scala 113:15] - assign io_out_csr_read = _T_686 | _T_691; // @[el2_dec_dec_ctl.scala 114:19] - assign io_out_csr_clr = _T_730 | _T_738; // @[el2_dec_dec_ctl.scala 117:18] - assign io_out_csr_set = _T_830 | _T_738; // @[el2_dec_dec_ctl.scala 124:18] - assign io_out_csr_write = _T_746 & io_ins[4]; // @[el2_dec_dec_ctl.scala 120:20] - assign io_out_csr_imm = _T_787 | _T_794; // @[el2_dec_dec_ctl.scala 121:18] - assign io_out_presync = _T_1116 | _T_1123; // @[el2_dec_dec_ctl.scala 141:18] - assign io_out_postsync = _T_1220 | _T_1123; // @[el2_dec_dec_ctl.scala 147:19] - assign io_out_ebreak = _T_852 & io_ins[4]; // @[el2_dec_dec_ctl.scala 127:17] - assign io_out_ecall = _T_867 & io_ins[4]; // @[el2_dec_dec_ctl.scala 128:16] - assign io_out_mret = _T_878 & io_ins[4]; // @[el2_dec_dec_ctl.scala 129:15] - assign io_out_mul = _T_892 & _T_18; // @[el2_dec_dec_ctl.scala 130:14] - assign io_out_rs1_sign = _T_912 | _T_929; // @[el2_dec_dec_ctl.scala 131:19] - assign io_out_rs2_sign = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 133:19] - assign io_out_low = _T_963 & _T_18; // @[el2_dec_dec_ctl.scala 134:14] - assign io_out_div = _T_974 & _T_18; // @[el2_dec_dec_ctl.scala 135:14] - assign io_out_rem = _T_987 & _T_18; // @[el2_dec_dec_ctl.scala 136:14] - assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16] - assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18] - assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17] - assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16] + wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 20:27] + wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 20:42] + wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:53] + wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 20:39] + wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 20:68] + wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:78] + wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 21:43] + wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 21:70] + wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 22:29] + wire _T_48 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_49 = _T_48 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_50 = _T_43 | _T_49; // @[el2_dec_dec_ctl.scala 22:56] + wire _T_56 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_57 = _T_56 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_58 = _T_50 | _T_57; // @[el2_dec_dec_ctl.scala 23:29] + wire _T_63 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_64 = _T_63 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_65 = _T_58 | _T_64; // @[el2_dec_dec_ctl.scala 23:55] + wire _T_71 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_72 = _T_71 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_73 = _T_65 | _T_72; // @[el2_dec_dec_ctl.scala 24:29] + wire _T_78 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_79 = _T_78 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_80 = _T_73 | _T_79; // @[el2_dec_dec_ctl.scala 24:55] + wire _T_86 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_87 = _T_86 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_88 = _T_80 | _T_87; // @[el2_dec_dec_ctl.scala 25:29] + wire _T_93 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_94 = _T_93 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_95 = _T_88 | _T_94; // @[el2_dec_dec_ctl.scala 25:55] + wire _T_97 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_99 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_100 = _T_97 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_101 = _T_95 | _T_100; // @[el2_dec_dec_ctl.scala 26:29] + wire _T_103 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_106 = _T_103 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_113 = io_ins[5] & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_114 = _T_113 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_120 = _T_103 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_121 = _T_120 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_129 = _T_100 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_136 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_137 = _T_136 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_138 = _T_137 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_139 = _T_129 | _T_138; // @[el2_dec_dec_ctl.scala 28:42] + wire _T_143 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_146 = _T_16 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_147 = _T_146 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_148 = _T_147 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_149 = _T_139 | _T_148; // @[el2_dec_dec_ctl.scala 28:70] + wire _T_157 = _T_143 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_158 = _T_157 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_159 = _T_158 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_165 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 30:28] + wire _T_168 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 30:55] + wire _T_169 = _T_165 | _T_168; // @[el2_dec_dec_ctl.scala 30:42] + wire _T_180 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_181 = _T_180 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_182 = _T_181 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_186 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 32:29] + wire _T_189 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 32:53] + wire _T_195 = _T_9 & _T_99; // @[el2_dec_dec_ctl.scala 33:28] + wire _T_197 = _T_195 & io_ins[2]; // @[el2_dec_dec_ctl.scala 33:41] + wire _T_208 = _T_9 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_223 = _T_103 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_235 = _T_19 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_236 = _T_235 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_237 = _T_236 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_245 = _T_237 | _T_197; // @[el2_dec_dec_ctl.scala 37:49] + wire _T_247 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_261 = _T_247 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_262 = _T_261 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_263 = _T_262 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_264 = _T_263 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_265 = _T_264 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_266 = _T_265 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_267 = _T_266 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_278 = io_ins[30] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_279 = _T_278 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_280 = _T_279 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_281 = _T_280 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_282 = _T_281 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_293 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_294 = _T_293 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_295 = _T_294 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_296 = _T_295 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_297 = _T_296 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_298 = _T_282 | _T_297; // @[el2_dec_dec_ctl.scala 39:49] + wire _T_307 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_308 = _T_307 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_309 = _T_308 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_310 = _T_309 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_311 = _T_298 | _T_310; // @[el2_dec_dec_ctl.scala 39:85] + wire _T_317 = io_ins[6] & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_318 = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_327 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_328 = _T_327 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_329 = _T_328 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_330 = _T_329 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_340 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_341 = _T_340 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_342 = _T_341 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_343 = _T_342 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_344 = _T_343 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_349 = _T_103 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_362 = _T_341 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_363 = _T_362 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_364 = _T_363 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_365 = _T_349 | _T_364; // @[el2_dec_dec_ctl.scala 42:37] + wire _T_369 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_370 = _T_369 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_371 = _T_365 | _T_370; // @[el2_dec_dec_ctl.scala 42:74] + wire _T_381 = _T_371 | _T_148; // @[el2_dec_dec_ctl.scala 43:26] + wire _T_391 = _T_327 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_392 = _T_391 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_393 = _T_392 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_406 = _T_340 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_407 = _T_406 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_408 = _T_407 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_409 = _T_408 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_420 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_421 = _T_420 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_422 = _T_421 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_423 = _T_422 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_424 = _T_423 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_439 = _T_293 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_440 = _T_439 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_441 = _T_440 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_442 = _T_441 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_453 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_454 = _T_453 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_455 = _T_454 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_456 = _T_455 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_472 = _T_261 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_473 = _T_472 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_474 = _T_473 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_475 = _T_474 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_476 = _T_475 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_515 = _T_307 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_516 = _T_515 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_517 = _T_516 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_524 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_525 = _T_524 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_526 = _T_525 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_527 = _T_517 | _T_526; // @[el2_dec_dec_ctl.scala 50:51] + wire _T_533 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_534 = _T_533 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_535 = _T_527 | _T_534; // @[el2_dec_dec_ctl.scala 50:79] + wire _T_548 = _T_294 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_549 = _T_548 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_550 = _T_549 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_551 = _T_535 | _T_550; // @[el2_dec_dec_ctl.scala 51:29] + wire _T_560 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_561 = _T_560 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_562 = _T_561 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_563 = _T_562 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_564 = _T_563 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_582 = _T_14 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_583 = _T_582 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_584 = _T_583 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_594 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_595 = _T_594 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_596 = _T_595 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_605 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_606 = _T_605 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_607 = _T_606 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_617 = io_ins[14] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_618 = _T_617 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_619 = _T_618 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_635 = _T_146 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_636 = _T_635 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_645 = io_ins[12] & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_646 = _T_645 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_653 = io_ins[13] & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_659 = _T_524 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_663 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_664 = _T_663 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_665 = _T_659 | _T_664; // @[el2_dec_dec_ctl.scala 62:44] + wire _T_669 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_670 = _T_669 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_671 = _T_665 | _T_670; // @[el2_dec_dec_ctl.scala 62:67] + wire _T_675 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_676 = _T_675 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_677 = _T_671 | _T_676; // @[el2_dec_dec_ctl.scala 63:26] + wire _T_681 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_682 = _T_681 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_683 = _T_677 | _T_682; // @[el2_dec_dec_ctl.scala 63:49] + wire _T_687 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_688 = _T_687 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_696 = _T_93 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_697 = _T_696 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_698 = _T_697 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_705 = _T_78 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_706 = _T_705 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_707 = _T_706 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_708 = _T_698 | _T_707; // @[el2_dec_dec_ctl.scala 65:49] + wire _T_715 = _T_63 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_716 = _T_715 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_717 = _T_716 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_718 = _T_708 | _T_717; // @[el2_dec_dec_ctl.scala 65:79] + wire _T_725 = _T_48 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_726 = _T_725 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_727 = _T_726 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_728 = _T_718 | _T_727; // @[el2_dec_dec_ctl.scala 66:33] + wire _T_735 = _T_33 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_736 = _T_735 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_737 = _T_736 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_745 = _T_180 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_753 = _T_420 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_754 = _T_753 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_759 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_760 = _T_759 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_761 = _T_760 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_762 = _T_754 | _T_761; // @[el2_dec_dec_ctl.scala 69:47] + wire _T_767 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_768 = _T_767 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_769 = _T_768 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_770 = _T_762 | _T_769; // @[el2_dec_dec_ctl.scala 69:74] + wire _T_775 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_776 = _T_775 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_777 = _T_776 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_778 = _T_770 | _T_777; // @[el2_dec_dec_ctl.scala 70:30] + wire _T_783 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_784 = _T_783 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_785 = _T_784 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_786 = _T_778 | _T_785; // @[el2_dec_dec_ctl.scala 70:57] + wire _T_791 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_792 = _T_791 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_793 = _T_792 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_800 = io_ins[15] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_801 = _T_800 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_802 = _T_801 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_808 = io_ins[16] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_809 = _T_808 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_810 = _T_809 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_811 = _T_802 | _T_810; // @[el2_dec_dec_ctl.scala 72:47] + wire _T_817 = io_ins[17] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_818 = _T_817 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_819 = _T_818 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_820 = _T_811 | _T_819; // @[el2_dec_dec_ctl.scala 72:75] + wire _T_826 = io_ins[18] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_827 = _T_826 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_828 = _T_827 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_829 = _T_820 | _T_828; // @[el2_dec_dec_ctl.scala 73:31] + wire _T_835 = io_ins[19] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_836 = _T_835 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_837 = _T_836 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_840 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_848 = _T_840 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_849 = _T_848 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_850 = _T_849 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_851 = _T_850 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_854 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_856 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_863 = _T_854 & _T_856; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_864 = _T_863 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_865 = _T_864 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_866 = _T_865 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_875 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_876 = _T_875 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_877 = _T_876 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_888 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_889 = _T_888 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_890 = _T_889 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_891 = _T_890 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_906 = _T_888 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_907 = _T_906 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_908 = _T_907 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_909 = _T_908 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_910 = _T_909 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_911 = _T_910 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_924 = _T_888 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_925 = _T_924 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_926 = _T_925 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_927 = _T_926 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_928 = _T_927 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_960 = _T_924 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_961 = _T_960 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_962 = _T_961 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_972 = _T_560 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_973 = _T_972 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_984 = _T_560 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_985 = _T_984 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_986 = _T_985 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_991 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_996 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_997 = _T_996 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1005 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1006 = _T_1005 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1007 = _T_1006 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1008 = _T_1007 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1012 = _T_1008 | _T_189; // @[el2_dec_dec_ctl.scala 87:51] + wire _T_1018 = _T_4 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1019 = _T_1018 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1020 = _T_1012 | _T_1019; // @[el2_dec_dec_ctl.scala 87:72] + wire _T_1036 = _T_86 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1037 = _T_1036 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1038 = _T_991 | _T_1037; // @[el2_dec_dec_ctl.scala 89:41] + wire _T_1045 = _T_71 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1046 = _T_1045 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1047 = _T_1038 | _T_1046; // @[el2_dec_dec_ctl.scala 89:68] + wire _T_1054 = _T_56 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1055 = _T_1054 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1056 = _T_1047 | _T_1055; // @[el2_dec_dec_ctl.scala 90:30] + wire _T_1063 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1064 = _T_1063 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1065 = _T_1056 | _T_1064; // @[el2_dec_dec_ctl.scala 90:57] + wire _T_1072 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1073 = _T_1072 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1074 = _T_1065 | _T_1073; // @[el2_dec_dec_ctl.scala 91:31] + wire _T_1080 = _T_93 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1081 = _T_1080 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1082 = _T_1074 | _T_1081; // @[el2_dec_dec_ctl.scala 91:59] + wire _T_1088 = _T_78 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1089 = _T_1088 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1090 = _T_1082 | _T_1089; // @[el2_dec_dec_ctl.scala 92:30] + wire _T_1096 = _T_63 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1097 = _T_1096 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1098 = _T_1090 | _T_1097; // @[el2_dec_dec_ctl.scala 92:57] + wire _T_1104 = _T_48 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1105 = _T_1104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1106 = _T_1098 | _T_1105; // @[el2_dec_dec_ctl.scala 93:30] + wire _T_1112 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1113 = _T_1112 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1129 = _T_840 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1130 = _T_1129 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1131 = _T_1130 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1132 = _T_1131 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1133 = _T_997 | _T_1132; // @[el2_dec_dec_ctl.scala 95:45] + wire _T_1142 = _T_1133 | _T_1037; // @[el2_dec_dec_ctl.scala 95:78] + wire _T_1151 = _T_1142 | _T_1046; // @[el2_dec_dec_ctl.scala 96:30] + wire _T_1160 = _T_1151 | _T_1055; // @[el2_dec_dec_ctl.scala 96:57] + wire _T_1169 = _T_1160 | _T_1064; // @[el2_dec_dec_ctl.scala 97:30] + wire _T_1178 = _T_1169 | _T_1073; // @[el2_dec_dec_ctl.scala 97:58] + wire _T_1186 = _T_1178 | _T_1081; // @[el2_dec_dec_ctl.scala 98:31] + wire _T_1194 = _T_1186 | _T_1089; // @[el2_dec_dec_ctl.scala 98:58] + wire _T_1202 = _T_1194 | _T_1097; // @[el2_dec_dec_ctl.scala 99:30] + wire _T_1210 = _T_1202 | _T_1105; // @[el2_dec_dec_ctl.scala 99:57] + wire _T_1220 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1226 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1228 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1232 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1234 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1241 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1243 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1245 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1247 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1249 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1253 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1255 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1257 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1259 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1261 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1271 = _T_1220 & _T_247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1272 = _T_1271 & io_ins[29]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1273 = _T_1272 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1274 = _T_1273 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1275 = _T_1274 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1276 = _T_1275 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1277 = _T_1276 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1278 = _T_1277 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1279 = _T_1278 & _T_840; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1280 = _T_1279 & io_ins[21]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1281 = _T_1280 & _T_856; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1282 = _T_1281 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1283 = _T_1282 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1284 = _T_1283 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1285 = _T_1284 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1286 = _T_1285 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1287 = _T_1286 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1288 = _T_1287 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1289 = _T_1288 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1290 = _T_1289 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1291 = _T_1290 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1292 = _T_1291 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1293 = _T_1292 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1294 = _T_1293 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1295 = _T_1294 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1296 = _T_1295 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1297 = _T_1296 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1298 = _T_1297 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1299 = _T_1298 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1305 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1353 = _T_1271 & _T_1305; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1354 = _T_1353 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1355 = _T_1354 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1356 = _T_1355 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1357 = _T_1356 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1358 = _T_1357 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1359 = _T_1358 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1360 = _T_1359 & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1361 = _T_1360 & _T_854; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1362 = _T_1361 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1363 = _T_1362 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1364 = _T_1363 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1365 = _T_1364 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1366 = _T_1365 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1367 = _T_1366 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1368 = _T_1367 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1369 = _T_1368 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1370 = _T_1369 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1371 = _T_1370 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1372 = _T_1371 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1373 = _T_1372 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1374 = _T_1373 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1375 = _T_1374 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1376 = _T_1375 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1377 = _T_1376 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1378 = _T_1377 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1379 = _T_1378 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1380 = _T_1379 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1381 = _T_1299 | _T_1380; // @[el2_dec_dec_ctl.scala 101:136] + wire _T_1389 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1436 = _T_1353 & _T_1389; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1437 = _T_1436 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1438 = _T_1437 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1439 = _T_1438 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1440 = _T_1439 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1441 = _T_1440 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1442 = _T_1441 & _T_840; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1443 = _T_1442 & _T_854; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1444 = _T_1443 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1445 = _T_1444 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1446 = _T_1445 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1447 = _T_1446 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1448 = _T_1447 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1449 = _T_1448 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1450 = _T_1449 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1451 = _T_1450 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1452 = _T_1451 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1453 = _T_1452 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1454 = _T_1453 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1455 = _T_1454 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1456 = _T_1455 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1457 = _T_1456 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1458 = _T_1457 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1459 = _T_1458 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1460 = _T_1459 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1461 = _T_1381 | _T_1460; // @[el2_dec_dec_ctl.scala 102:122] + wire _T_1489 = _T_1439 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1490 = _T_1489 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1491 = _T_1490 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1492 = _T_1491 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1493 = _T_1492 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1494 = _T_1461 | _T_1493; // @[el2_dec_dec_ctl.scala 103:119] + wire _T_1521 = _T_1220 & _T_1305; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1522 = _T_1521 & _T_1389; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1523 = _T_1522 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1524 = _T_1523 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1525 = _T_1524 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1526 = _T_1525 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1527 = _T_1526 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1528 = _T_1527 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1529 = _T_1528 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1530 = _T_1529 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1531 = _T_1530 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1532 = _T_1531 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1533 = _T_1532 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1534 = _T_1494 | _T_1533; // @[el2_dec_dec_ctl.scala 104:60] + wire _T_1563 = _T_1525 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1564 = _T_1563 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1565 = _T_1564 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1566 = _T_1565 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1567 = _T_1566 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1568 = _T_1567 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1569 = _T_1568 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1570 = _T_1569 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1571 = _T_1534 | _T_1570; // @[el2_dec_dec_ctl.scala 105:69] + wire _T_1597 = _T_1438 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1598 = _T_1597 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1599 = _T_1598 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1600 = _T_1599 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1601 = _T_1600 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1602 = _T_1601 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1603 = _T_1571 | _T_1602; // @[el2_dec_dec_ctl.scala 106:66] + wire _T_1620 = _T_235 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1621 = _T_1620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1622 = _T_1621 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1623 = _T_1622 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1624 = _T_1623 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1625 = _T_1624 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1626 = _T_1603 | _T_1625; // @[el2_dec_dec_ctl.scala 107:58] + wire _T_1638 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1640 = _T_1639 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1641 = _T_1640 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1642 = _T_1641 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1643 = _T_1642 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1644 = _T_1643 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1645 = _T_1626 | _T_1644; // @[el2_dec_dec_ctl.scala 108:46] + wire _T_1657 = _T_143 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1658 = _T_1657 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1659 = _T_1658 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1660 = _T_1659 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1661 = _T_1660 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1662 = _T_1661 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1663 = _T_1645 | _T_1662; // @[el2_dec_dec_ctl.scala 109:40] + wire _T_1678 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1679 = _T_1678 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1680 = _T_1679 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1681 = _T_1680 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1682 = _T_1681 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1683 = _T_1682 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1684 = _T_1663 | _T_1683; // @[el2_dec_dec_ctl.scala 110:39] + wire _T_1695 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1696 = _T_1695 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1697 = _T_1696 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1698 = _T_1697 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1699 = _T_1698 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1700 = _T_1699 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1701 = _T_1700 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1702 = _T_1684 | _T_1701; // @[el2_dec_dec_ctl.scala 111:43] + wire _T_1771 = _T_1443 & _T_856; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1772 = _T_1771 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1773 = _T_1772 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1774 = _T_1773 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1775 = _T_1774 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1776 = _T_1775 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1777 = _T_1776 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1778 = _T_1777 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1779 = _T_1778 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1780 = _T_1779 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1781 = _T_1780 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1782 = _T_1781 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1783 = _T_1782 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1784 = _T_1783 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1785 = _T_1784 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1786 = _T_1785 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1787 = _T_1786 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1788 = _T_1787 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1789 = _T_1788 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1790 = _T_1789 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1791 = _T_1702 | _T_1790; // @[el2_dec_dec_ctl.scala 112:39] + wire _T_1839 = _T_1436 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1840 = _T_1839 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1841 = _T_1840 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1842 = _T_1841 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1843 = _T_1842 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1844 = _T_1843 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1845 = _T_1844 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1846 = _T_1845 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1847 = _T_1846 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1848 = _T_1847 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1849 = _T_1848 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1850 = _T_1849 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1851 = _T_1850 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1852 = _T_1851 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1853 = _T_1852 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1854 = _T_1853 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1855 = _T_1854 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1856 = _T_1855 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1857 = _T_1856 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1858 = _T_1857 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1859 = _T_1791 | _T_1858; // @[el2_dec_dec_ctl.scala 113:130] + wire _T_1871 = _T_524 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1872 = _T_1871 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1873 = _T_1872 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1874 = _T_1873 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1875 = _T_1874 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1876 = _T_1875 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1877 = _T_1859 | _T_1876; // @[el2_dec_dec_ctl.scala 114:102] + wire _T_1892 = _T_16 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1893 = _T_1892 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1894 = _T_1893 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1895 = _T_1894 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1896 = _T_1895 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1897 = _T_1896 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1898 = _T_1897 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1899 = _T_1877 | _T_1898; // @[el2_dec_dec_ctl.scala 115:39] + wire _T_1908 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1909 = _T_1908 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1910 = _T_1909 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1911 = _T_1910 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1912 = _T_1911 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1913 = _T_1912 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1914 = _T_1899 | _T_1913; // @[el2_dec_dec_ctl.scala 116:43] + wire _T_1926 = _T_653 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1927 = _T_1926 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1928 = _T_1927 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1929 = _T_1928 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1930 = _T_1929 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1931 = _T_1914 | _T_1930; // @[el2_dec_dec_ctl.scala 117:35] + wire _T_1947 = _T_582 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1948 = _T_1947 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1949 = _T_1948 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1950 = _T_1949 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1951 = _T_1950 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1952 = _T_1951 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1953 = _T_1931 | _T_1952; // @[el2_dec_dec_ctl.scala 118:38] + wire _T_1962 = _T_103 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1963 = _T_1962 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1964 = _T_1963 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1965 = _T_1964 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1966 = _T_1965 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 20:14] + assign io_out_rs1 = _T_101 | _T_106; // @[el2_dec_dec_ctl.scala 21:14] + assign io_out_rs2 = _T_114 | _T_121; // @[el2_dec_dec_ctl.scala 27:14] + assign io_out_imm12 = _T_149 | _T_159; // @[el2_dec_dec_ctl.scala 28:16] + assign io_out_rd = _T_169 | io_ins[4]; // @[el2_dec_dec_ctl.scala 30:13] + assign io_out_shimm5 = _T_182 & _T_18; // @[el2_dec_dec_ctl.scala 31:17] + assign io_out_imm20 = _T_186 | _T_189; // @[el2_dec_dec_ctl.scala 32:16] + assign io_out_pc = _T_197 | _T_186; // @[el2_dec_dec_ctl.scala 33:13] + assign io_out_load = _T_208 & _T_18; // @[el2_dec_dec_ctl.scala 34:15] + assign io_out_store = _T_120 & _T_97; // @[el2_dec_dec_ctl.scala 35:16] + assign io_out_lsu = _T_223 & _T_18; // @[el2_dec_dec_ctl.scala 36:14] + assign io_out_add = _T_245 | _T_267; // @[el2_dec_dec_ctl.scala 37:14] + assign io_out_sub = _T_311 | _T_318; // @[el2_dec_dec_ctl.scala 39:14] + assign io_out_land = _T_330 | _T_344; // @[el2_dec_dec_ctl.scala 41:15] + assign io_out_lor = _T_381 | _T_393; // @[el2_dec_dec_ctl.scala 42:14] + assign io_out_lxor = _T_409 | _T_424; // @[el2_dec_dec_ctl.scala 45:15] + assign io_out_sll = _T_442 & _T_18; // @[el2_dec_dec_ctl.scala 46:14] + assign io_out_sra = _T_456 & _T_18; // @[el2_dec_dec_ctl.scala 47:14] + assign io_out_srl = _T_476 & _T_18; // @[el2_dec_dec_ctl.scala 48:14] + assign io_out_slt = _T_297 | _T_310; // @[el2_dec_dec_ctl.scala 49:14] + assign io_out_unsign = _T_551 | _T_564; // @[el2_dec_dec_ctl.scala 50:17] + assign io_out_condbr = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 53:17] + assign io_out_beq = _T_584 & _T_18; // @[el2_dec_dec_ctl.scala 54:14] + assign io_out_bne = _T_596 & _T_18; // @[el2_dec_dec_ctl.scala 55:14] + assign io_out_bge = _T_607 & _T_18; // @[el2_dec_dec_ctl.scala 56:14] + assign io_out_blt = _T_619 & _T_18; // @[el2_dec_dec_ctl.scala 57:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 58:14] + assign io_out_by = _T_636 & _T_18; // @[el2_dec_dec_ctl.scala 59:13] + assign io_out_half = _T_646 & _T_18; // @[el2_dec_dec_ctl.scala 60:15] + assign io_out_word = _T_653 & _T_97; // @[el2_dec_dec_ctl.scala 61:15] + assign io_out_csr_read = _T_683 | _T_688; // @[el2_dec_dec_ctl.scala 62:19] + assign io_out_csr_clr = _T_728 | _T_737; // @[el2_dec_dec_ctl.scala 65:18] + assign io_out_csr_set = _T_829 | _T_837; // @[el2_dec_dec_ctl.scala 72:18] + assign io_out_csr_write = _T_745 & io_ins[4]; // @[el2_dec_dec_ctl.scala 68:20] + assign io_out_csr_imm = _T_786 | _T_793; // @[el2_dec_dec_ctl.scala 69:18] + assign io_out_presync = _T_1106 | _T_1113; // @[el2_dec_dec_ctl.scala 89:18] + assign io_out_postsync = _T_1210 | _T_1113; // @[el2_dec_dec_ctl.scala 95:19] + assign io_out_ebreak = _T_851 & io_ins[4]; // @[el2_dec_dec_ctl.scala 75:17] + assign io_out_ecall = _T_866 & io_ins[4]; // @[el2_dec_dec_ctl.scala 76:16] + assign io_out_mret = _T_877 & io_ins[4]; // @[el2_dec_dec_ctl.scala 77:15] + assign io_out_mul = _T_891 & _T_18; // @[el2_dec_dec_ctl.scala 78:14] + assign io_out_rs1_sign = _T_911 | _T_928; // @[el2_dec_dec_ctl.scala 79:19] + assign io_out_rs2_sign = _T_927 & _T_18; // @[el2_dec_dec_ctl.scala 81:19] + assign io_out_low = _T_962 & _T_18; // @[el2_dec_dec_ctl.scala 82:14] + assign io_out_div = _T_973 & _T_18; // @[el2_dec_dec_ctl.scala 83:14] + assign io_out_rem = _T_986 & _T_18; // @[el2_dec_dec_ctl.scala 84:14] + assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 85:16] + assign io_out_fence_i = _T_996 & io_ins[3]; // @[el2_dec_dec_ctl.scala 86:18] + assign io_out_pm_alu = _T_1020 | _T_11; // @[el2_dec_dec_ctl.scala 87:17] + assign io_out_legal = _T_1953 | _T_1966; // @[el2_dec_dec_ctl.scala 101:16] endmodule module el2_dec_decode_ctl( input clock, @@ -45921,13 +45948,13 @@ module el2_dec_decode_ctl( input [1:0] io_dec_i0_icaf_type_d, input io_dec_i0_dbecc_d, input io_dec_i0_brp_valid, - input [11:0] io_dec_i0_brp_bits_toffset, - input [1:0] io_dec_i0_brp_bits_hist, - input io_dec_i0_brp_bits_br_error, - input io_dec_i0_brp_bits_br_start_error, - input [30:0] io_dec_i0_brp_bits_prett, - input io_dec_i0_brp_bits_way, - input io_dec_i0_brp_bits_ret, + input [11:0] io_dec_i0_brp_toffset, + input [1:0] io_dec_i0_brp_hist, + input io_dec_i0_brp_br_error, + input io_dec_i0_brp_br_start_error, + input [30:0] io_dec_i0_brp_prett, + input io_dec_i0_brp_way, + input io_dec_i0_brp_ret, input [7:0] io_dec_i0_bp_index, input [7:0] io_dec_i0_bp_fghr, input [4:0] io_dec_i0_bp_btag, @@ -45950,6 +45977,7 @@ module el2_dec_decode_ctl( input [31:0] io_lsu_result_m, input [31:0] io_lsu_result_corr_r, input io_exu_flush_final, + input [30:0] io_exu_i0_pc_x, input [31:0] io_dec_i0_instr_d, input io_dec_ib0_valid_d, input [31:0] io_exu_i0_result_x, @@ -45988,6 +46016,7 @@ module el2_dec_decode_ctl( output [4:0] io_dec_i0_waddr_r, output io_dec_i0_wen_r, output [31:0] io_dec_i0_wdata_r, + output io_dec_i0_select_pc_d, output [1:0] io_dec_i0_rs1_bypass_en_d, output [1:0] io_dec_i0_rs2_bypass_en_d, output io_lsu_p_valid, @@ -46151,65 +46180,63 @@ module el2_dec_decode_ctl( reg [31:0] _RAND_87; reg [31:0] _RAND_88; reg [31:0] _RAND_89; + reg [31:0] _RAND_90; `endif // RANDOMIZE_REG_INIT - wire data_gated_cgc_io_l1clk; // @[el2_dec_decode_ctl.scala 222:29] - wire data_gated_cgc_io_clk; // @[el2_dec_decode_ctl.scala 222:29] - wire data_gated_cgc_io_en; // @[el2_dec_decode_ctl.scala 222:29] - wire data_gated_cgc_io_scan_mode; // @[el2_dec_decode_ctl.scala 222:29] - wire [31:0] i0_dec_io_ins; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 396:22] - wire i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 396:22] - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire [31:0] i0_dec_io_ins; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 392:22] + wire i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 392:22] wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] @@ -46222,10 +46249,10 @@ module el2_dec_decode_ctl( wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 518:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 518:23] wire rvclkhdr_5_io_clk; // @[el2_lib.scala 518:23] wire rvclkhdr_5_io_en; // @[el2_lib.scala 518:23] @@ -46242,10 +46269,10 @@ module el2_dec_decode_ctl( wire rvclkhdr_8_io_clk; // @[el2_lib.scala 518:23] wire rvclkhdr_8_io_en; // @[el2_lib.scala 518:23] wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 518:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 518:23] wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] @@ -46282,554 +46309,559 @@ module el2_dec_decode_ctl( wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23] wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23] - reg tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 503:29] + wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23] + reg tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 499:55] wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 211:51] - reg tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 504:29] + reg tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 500:55] wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 212:32] wire _T_3 = _T_1 | _T_2; // @[el2_dec_decode_ctl.scala 211:73] wire _T_4 = io_dec_tlu_flush_extint ^ io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 213:32] wire _T_5 = _T_3 | _T_4; // @[el2_dec_decode_ctl.scala 212:56] - reg leak1_i1_stall; // @[el2_dec_decode_ctl.scala 404:56] - wire _T_279 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 403:73] - wire _T_280 = leak1_i1_stall & _T_279; // @[el2_dec_decode_ctl.scala 403:71] - wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_280; // @[el2_dec_decode_ctl.scala 403:53] + reg leak1_i1_stall; // @[el2_dec_decode_ctl.scala 400:56] + wire _T_280 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 399:73] + wire _T_281 = leak1_i1_stall & _T_280; // @[el2_dec_decode_ctl.scala 399:71] + wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_281; // @[el2_dec_decode_ctl.scala 399:53] wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[el2_dec_decode_ctl.scala 214:32] wire _T_7 = _T_5 | _T_6; // @[el2_dec_decode_ctl.scala 213:56] - wire _T_283 = io_dec_i0_decode_d & leak1_i1_stall; // @[el2_dec_decode_ctl.scala 406:45] - reg leak1_i0_stall; // @[el2_dec_decode_ctl.scala 407:56] - wire _T_285 = leak1_i0_stall & _T_279; // @[el2_dec_decode_ctl.scala 406:81] - wire leak1_i0_stall_in = _T_283 | _T_285; // @[el2_dec_decode_ctl.scala 406:63] + wire _T_284 = io_dec_i0_decode_d & leak1_i1_stall; // @[el2_dec_decode_ctl.scala 402:45] + reg leak1_i0_stall; // @[el2_dec_decode_ctl.scala 403:56] + wire _T_286 = leak1_i0_stall & _T_280; // @[el2_dec_decode_ctl.scala 402:81] + wire leak1_i0_stall_in = _T_284 | _T_286; // @[el2_dec_decode_ctl.scala 402:63] wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[el2_dec_decode_ctl.scala 215:32] wire _T_9 = _T_7 | _T_8; // @[el2_dec_decode_ctl.scala 214:56] - reg pause_stall; // @[el2_dec_decode_ctl.scala 501:50] - wire _T_412 = io_dec_tlu_wr_pause_r | pause_stall; // @[el2_dec_decode_ctl.scala 500:44] - wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[el2_dec_decode_ctl.scala 499:49] - wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[el2_dec_decode_ctl.scala 499:47] + reg pause_stall; // @[el2_dec_decode_ctl.scala 497:50] + wire _T_412 = io_dec_tlu_wr_pause_r | pause_stall; // @[el2_dec_decode_ctl.scala 496:44] + wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[el2_dec_decode_ctl.scala 495:49] + wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[el2_dec_decode_ctl.scala 495:47] reg [31:0] write_csr_data; // @[el2_lib.scala 514:16] - wire _T_410 = write_csr_data == 32'h0; // @[el2_dec_decode_ctl.scala 499:109] - wire _T_411 = pause_stall & _T_410; // @[el2_dec_decode_ctl.scala 499:91] - wire clear_pause = _T_409 | _T_411; // @[el2_dec_decode_ctl.scala 499:76] - wire _T_413 = ~clear_pause; // @[el2_dec_decode_ctl.scala 500:61] - wire pause_state_in = _T_412 & _T_413; // @[el2_dec_decode_ctl.scala 500:59] + wire _T_410 = write_csr_data == 32'h0; // @[el2_dec_decode_ctl.scala 495:109] + wire _T_411 = pause_stall & _T_410; // @[el2_dec_decode_ctl.scala 495:91] + wire clear_pause = _T_409 | _T_411; // @[el2_dec_decode_ctl.scala 495:76] + wire _T_413 = ~clear_pause; // @[el2_dec_decode_ctl.scala 496:61] + wire pause_state_in = _T_412 & _T_413; // @[el2_dec_decode_ctl.scala 496:59] wire _T_10 = pause_state_in ^ pause_stall; // @[el2_dec_decode_ctl.scala 216:32] wire _T_11 = _T_9 | _T_10; // @[el2_dec_decode_ctl.scala 215:56] - wire _T_17 = ~leak1_i1_stall; // @[el2_dec_decode_ctl.scala 230:62] - wire i0_brp_valid = io_dec_i0_brp_valid & _T_17; // @[el2_dec_decode_ctl.scala 230:60] - wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire [20:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] - wire _T_298 = i0_pcall_imm[20:13] == 8'hff; // @[el2_dec_decode_ctl.scala 412:79] - wire _T_300 = i0_pcall_imm[20:13] == 8'h0; // @[el2_dec_decode_ctl.scala 412:112] - wire i0_pcall_12b_offset = i0_pcall_imm[12] ? _T_298 : _T_300; // @[el2_dec_decode_ctl.scala 412:33] - wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 413:47] - wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[el2_dec_decode_ctl.scala 626:16] - wire _T_302 = i0r_rd == 5'h1; // @[el2_dec_decode_ctl.scala 413:76] - wire _T_303 = i0r_rd == 5'h5; // @[el2_dec_decode_ctl.scala 413:98] - wire _T_304 = _T_302 | _T_303; // @[el2_dec_decode_ctl.scala 413:89] - wire i0_pcall_case = _T_301 & _T_304; // @[el2_dec_decode_ctl.scala 413:65] - wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 415:38] - wire _T_19 = i0_dp_raw_condbr | i0_pcall_raw; // @[el2_dec_decode_ctl.scala 241:75] - wire _T_309 = ~_T_304; // @[el2_dec_decode_ctl.scala 414:67] - wire i0_pja_case = _T_301 & _T_309; // @[el2_dec_decode_ctl.scala 414:65] - wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 417:38] - wire _T_20 = _T_19 | i0_pja_raw; // @[el2_dec_decode_ctl.scala 241:90] - wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 421:37] - wire _T_326 = i0r_rd == 5'h0; // @[el2_dec_decode_ctl.scala 421:65] - wire _T_327 = _T_325 & _T_326; // @[el2_dec_decode_ctl.scala 421:55] - wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 624:16] - wire _T_328 = i0r_rs1 == 5'h1; // @[el2_dec_decode_ctl.scala 421:89] - wire _T_329 = i0r_rs1 == 5'h5; // @[el2_dec_decode_ctl.scala 421:111] - wire _T_330 = _T_328 | _T_329; // @[el2_dec_decode_ctl.scala 421:101] - wire i0_pret_case = _T_327 & _T_330; // @[el2_dec_decode_ctl.scala 421:79] - wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 422:32] - wire _T_21 = _T_20 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 241:103] - wire _T_22 = ~_T_21; // @[el2_dec_decode_ctl.scala 241:56] - wire i0_notbr_error = i0_brp_valid & _T_22; // @[el2_dec_decode_ctl.scala 241:54] - wire _T_30 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 246:62] - wire _T_24 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[el2_dec_decode_ctl.scala 244:47] - wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 419:41] + wire _T_18 = ~leak1_i1_stall; // @[el2_dec_decode_ctl.scala 226:62] + wire i0_brp_valid = io_dec_i0_brp_valid & _T_18; // @[el2_dec_decode_ctl.scala 226:60] + wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58] + wire _T_298 = i0_pcall_imm[19:12] == 8'hff; // @[el2_dec_decode_ctl.scala 408:79] + wire _T_300 = i0_pcall_imm[19:12] == 8'h0; // @[el2_dec_decode_ctl.scala 408:112] + wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_298 : _T_300; // @[el2_dec_decode_ctl.scala 408:33] + wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 409:47] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[el2_dec_decode_ctl.scala 622:16] + wire _T_302 = i0r_rd == 5'h1; // @[el2_dec_decode_ctl.scala 409:76] + wire _T_303 = i0r_rd == 5'h5; // @[el2_dec_decode_ctl.scala 409:98] + wire _T_304 = _T_302 | _T_303; // @[el2_dec_decode_ctl.scala 409:89] + wire i0_pcall_case = _T_301 & _T_304; // @[el2_dec_decode_ctl.scala 409:65] + wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 411:38] + wire _T_20 = i0_dp_raw_condbr | i0_pcall_raw; // @[el2_dec_decode_ctl.scala 237:75] + wire _T_309 = ~_T_304; // @[el2_dec_decode_ctl.scala 410:67] + wire i0_pja_case = _T_301 & _T_309; // @[el2_dec_decode_ctl.scala 410:65] + wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 413:38] + wire _T_21 = _T_20 | i0_pja_raw; // @[el2_dec_decode_ctl.scala 237:90] + wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 417:37] + wire _T_326 = i0r_rd == 5'h0; // @[el2_dec_decode_ctl.scala 417:65] + wire _T_327 = _T_325 & _T_326; // @[el2_dec_decode_ctl.scala 417:55] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 620:16] + wire _T_328 = i0r_rs1 == 5'h1; // @[el2_dec_decode_ctl.scala 417:89] + wire _T_329 = i0r_rs1 == 5'h5; // @[el2_dec_decode_ctl.scala 417:111] + wire _T_330 = _T_328 | _T_329; // @[el2_dec_decode_ctl.scala 417:101] + wire i0_pret_case = _T_327 & _T_330; // @[el2_dec_decode_ctl.scala 417:79] + wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 418:32] + wire _T_22 = _T_21 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 237:103] + wire _T_23 = ~_T_22; // @[el2_dec_decode_ctl.scala 237:56] + wire i0_notbr_error = i0_brp_valid & _T_23; // @[el2_dec_decode_ctl.scala 237:54] + wire _T_31 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:57] + wire _T_25 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 240:47] + wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 415:41] wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] - wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 419:26] - wire _T_25 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 244:106] - wire _T_26 = _T_24 & _T_25; // @[el2_dec_decode_ctl.scala 244:76] - wire _T_27 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 244:126] - wire i0_br_toffset_error = _T_26 & _T_27; // @[el2_dec_decode_ctl.scala 244:124] - wire _T_31 = _T_30 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 246:79] - wire _T_28 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[el2_dec_decode_ctl.scala 245:47] - wire i0_ret_error = _T_28 & _T_27; // @[el2_dec_decode_ctl.scala 245:72] - wire i0_br_error = _T_31 | i0_ret_error; // @[el2_dec_decode_ctl.scala 246:101] - wire _T_38 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[el2_dec_decode_ctl.scala 251:47] - wire i0_br_error_all = _T_38 & _T_17; // @[el2_dec_decode_ctl.scala 251:84] - wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 260:36] - wire _T_40 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 264:25] - wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_postsync = _T_40 | i0_dp_raw_postsync; // @[el2_dec_decode_ctl.scala 264:50] - wire _T_439 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[el2_dec_decode_ctl.scala 530:36] - wire debug_fence_i = io_dec_debug_fence_d & io_dbg_cmd_wrdata[0]; // @[el2_dec_decode_ctl.scala 522:48] - wire _T_440 = _T_439 | debug_fence_i; // @[el2_dec_decode_ctl.scala 530:60] - wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_write = _T_40 ? 1'h0 : i0_dp_raw_csr_write; // @[el2_dec_decode_ctl.scala 264:50] - wire _T_343 = ~io_dec_debug_fence_d; // @[el2_dec_decode_ctl.scala 461:42] - wire i0_csr_write = i0_dp_csr_write & _T_343; // @[el2_dec_decode_ctl.scala 461:40] - wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_read = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 264:50] - wire _T_347 = ~i0_dp_csr_read; // @[el2_dec_decode_ctl.scala 466:41] - wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 466:39] - wire _T_442 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[el2_dec_decode_ctl.scala 530:112] - wire _T_443 = i0_csr_write_only_d & _T_442; // @[el2_dec_decode_ctl.scala 530:99] - wire i0_postsync = _T_440 | _T_443; // @[el2_dec_decode_ctl.scala 530:76] - wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_legal = _T_40 | i0_dp_raw_legal; // @[el2_dec_decode_ctl.scala 264:50] - wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 532:34] - wire _T_444 = ~any_csr_d; // @[el2_dec_decode_ctl.scala 534:40] - wire _T_445 = _T_444 | io_dec_csr_legal_d; // @[el2_dec_decode_ctl.scala 534:51] - wire i0_legal = i0_dp_legal & _T_445; // @[el2_dec_decode_ctl.scala 534:37] - wire _T_504 = ~i0_legal; // @[el2_dec_decode_ctl.scala 574:56] - wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 574:54] - wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 574:39] - reg postsync_stall; // @[el2_dec_decode_ctl.scala 572:53] - reg x_d_valid; // @[el2_lib.scala 524:16] - wire _T_507 = postsync_stall & x_d_valid; // @[el2_dec_decode_ctl.scala 574:88] - wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 574:69] + wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 415:26] + wire _T_26 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:96] + wire _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:71] + wire _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:116] + wire i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:114] + wire _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:74] + wire _T_29 = i0_brp_valid & io_dec_i0_brp_ret; // @[el2_dec_decode_ctl.scala 241:47] + wire i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:67] + wire i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:96] + wire _T_39 = i0_br_error | io_dec_i0_brp_br_start_error; // @[el2_dec_decode_ctl.scala 247:47] + wire i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:79] + wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 256:36] + wire _T_41 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 260:25] + wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_postsync = _T_41 | i0_dp_raw_postsync; // @[el2_dec_decode_ctl.scala 260:50] + wire _T_439 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[el2_dec_decode_ctl.scala 526:36] + wire debug_fence_i = io_dec_debug_fence_d & io_dbg_cmd_wrdata[0]; // @[el2_dec_decode_ctl.scala 518:48] + wire _T_440 = _T_439 | debug_fence_i; // @[el2_dec_decode_ctl.scala 526:60] + wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_write = _T_41 ? 1'h0 : i0_dp_raw_csr_write; // @[el2_dec_decode_ctl.scala 260:50] + wire _T_343 = ~io_dec_debug_fence_d; // @[el2_dec_decode_ctl.scala 457:42] + wire i0_csr_write = i0_dp_csr_write & _T_343; // @[el2_dec_decode_ctl.scala 457:40] + wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_read = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 260:50] + wire _T_347 = ~i0_dp_csr_read; // @[el2_dec_decode_ctl.scala 462:41] + wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 462:39] + wire _T_442 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[el2_dec_decode_ctl.scala 526:112] + wire _T_443 = i0_csr_write_only_d & _T_442; // @[el2_dec_decode_ctl.scala 526:99] + wire i0_postsync = _T_440 | _T_443; // @[el2_dec_decode_ctl.scala 526:76] + wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_legal = _T_41 | i0_dp_raw_legal; // @[el2_dec_decode_ctl.scala 260:50] + wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 528:34] + wire _T_444 = ~any_csr_d; // @[el2_dec_decode_ctl.scala 530:40] + wire _T_445 = _T_444 | io_dec_csr_legal_d; // @[el2_dec_decode_ctl.scala 530:51] + wire i0_legal = i0_dp_legal & _T_445; // @[el2_dec_decode_ctl.scala 530:37] + wire _T_504 = ~i0_legal; // @[el2_dec_decode_ctl.scala 570:56] + wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54] + wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39] + reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53] + reg x_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 570:88] + wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69] wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] - reg flush_final_r; // @[el2_dec_decode_ctl.scala 620:52] + reg flush_final_r; // @[el2_dec_decode_ctl.scala 616:52] wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[el2_dec_decode_ctl.scala 218:32] wire _T_15 = _T_13 | _T_14; // @[el2_dec_decode_ctl.scala 217:56] - wire shift_illegal = io_dec_i0_decode_d & _T_504; // @[el2_dec_decode_ctl.scala 538:47] - reg illegal_lockout; // @[el2_dec_decode_ctl.scala 542:54] - wire _T_466 = shift_illegal | illegal_lockout; // @[el2_dec_decode_ctl.scala 541:40] - wire _T_467 = ~flush_final_r; // @[el2_dec_decode_ctl.scala 541:61] - wire illegal_lockout_in = _T_466 & _T_467; // @[el2_dec_decode_ctl.scala 541:59] + wire shift_illegal = io_dec_i0_decode_d & _T_504; // @[el2_dec_decode_ctl.scala 534:47] + reg illegal_lockout; // @[el2_dec_decode_ctl.scala 538:54] + wire _T_466 = shift_illegal | illegal_lockout; // @[el2_dec_decode_ctl.scala 537:40] + wire _T_467 = ~flush_final_r; // @[el2_dec_decode_ctl.scala 537:61] + wire illegal_lockout_in = _T_466 & _T_467; // @[el2_dec_decode_ctl.scala 537:59] wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32] - wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 648:46] - wire _T_32 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 247:72] - wire _T_35 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 248:94] - wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_pm_alu = _T_40 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_fence_i = _T_40 ? 1'h0 : i0_dp_raw_fence_i; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_fence = _T_40 ? 1'h0 : i0_dp_raw_fence; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_div = i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_div = _T_40 ? 1'h0 : i0_dp_raw_div; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_low = i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_mul = _T_40 ? 1'h0 : i0_dp_raw_mul; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_mret = _T_40 ? 1'h0 : i0_dp_raw_mret; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_ecall = _T_40 ? 1'h0 : i0_dp_raw_ecall; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_ebreak = _T_40 ? 1'h0 : i0_dp_raw_ebreak; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_presync = _T_40 ? 1'h0 : i0_dp_raw_presync; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_set = _T_40 ? 1'h0 : i0_dp_raw_csr_set; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_csr_clr = _T_40 ? 1'h0 : i0_dp_raw_csr_clr; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_word = i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_word = _T_40 ? 1'h0 : i0_dp_raw_word; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_half = i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_half = _T_40 ? 1'h0 : i0_dp_raw_half; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_by = i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_by = _T_40 ? 1'h0 : i0_dp_raw_by; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_jal = _T_40 ? 1'h0 : i0_dp_raw_jal; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_condbr = _T_40 ? 1'h0 : i0_dp_raw_condbr; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_land = i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_add = i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_lsu = _T_40 ? 1'h0 : i0_dp_raw_lsu; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_store = i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_store = _T_40 ? 1'h0 : i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_load = i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_load = _T_40 ? 1'h0 : i0_dp_raw_load; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_imm20 = _T_40 ? 1'h0 : i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_shimm5 = _T_40 ? 1'h0 : i0_dp_raw_shimm5; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_rd = _T_40 ? 1'h0 : i0_dp_raw_rd; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_imm12 = _T_40 ? 1'h0 : i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_rs2 = _T_40 | i0_dp_raw_rs2; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_rs1 = _T_40 | i0_dp_raw_rs1; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] - wire i0_dp_alu = _T_40 | i0_dp_raw_alu; // @[el2_dec_decode_ctl.scala 264:50] - wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 416:38] - wire _T_43 = i0_dp_condbr | i0_pcall; // @[el2_dec_decode_ctl.scala 278:38] - wire i0_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 418:38] - wire _T_44 = _T_43 | i0_pja; // @[el2_dec_decode_ctl.scala 278:49] - wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 423:32] - wire i0_predict_br = _T_44 | i0_pret; // @[el2_dec_decode_ctl.scala 278:58] - wire _T_46 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 280:55] - wire _T_47 = ~_T_46; // @[el2_dec_decode_ctl.scala 280:26] - wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 282:20] - wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 315:63] - reg [2:0] cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 351:47] - wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_93 = _GEN_123 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_94 = cam_data_reset & _T_93; // @[el2_dec_decode_ctl.scala 326:45] - reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 351:47] - wire cam_data_reset_val_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:88] - wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 330:39] - wire _T_50 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 307:78] - reg [2:0] cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_119 = _GEN_123 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_120 = cam_data_reset & _T_119; // @[el2_dec_decode_ctl.scala 326:45] - reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 351:47] - wire cam_data_reset_val_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:88] - wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 330:39] - wire _T_53 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 307:78] - wire _T_56 = cam_0_valid & _T_53; // @[el2_dec_decode_ctl.scala 307:126] - wire [1:0] _T_58 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 307:158] - reg [2:0] cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_145 = _GEN_123 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_146 = cam_data_reset & _T_145; // @[el2_dec_decode_ctl.scala 326:45] - reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 351:47] - wire cam_data_reset_val_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:88] - wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 330:39] - wire _T_59 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 307:78] - wire _T_62 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 307:126] - wire _T_65 = _T_62 & _T_59; // @[el2_dec_decode_ctl.scala 307:126] - wire [2:0] _T_67 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 307:158] - reg [2:0] cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_171 = _GEN_123 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 326:67] - wire _T_172 = cam_data_reset & _T_171; // @[el2_dec_decode_ctl.scala 326:45] - reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 351:47] - wire cam_data_reset_val_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:88] - wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 330:39] - wire _T_68 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 307:78] - wire _T_74 = _T_62 & cam_2_valid; // @[el2_dec_decode_ctl.scala 307:126] - wire _T_77 = _T_74 & _T_68; // @[el2_dec_decode_ctl.scala 307:126] - wire [3:0] _T_79 = {io_lsu_nonblock_load_valid_m, 3'h0}; // @[el2_dec_decode_ctl.scala 307:158] - wire _T_80 = _T_50 & io_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] - wire [1:0] _T_81 = _T_56 ? _T_58 : 2'h0; // @[Mux.scala 27:72] - wire [2:0] _T_82 = _T_65 ? _T_67 : 3'h0; // @[Mux.scala 27:72] - wire [3:0] _T_83 = _T_77 ? _T_79 : 4'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_127 = {{1'd0}, _T_80}; // @[Mux.scala 27:72] - wire [1:0] _T_84 = _GEN_127 | _T_81; // @[Mux.scala 27:72] - wire [2:0] _GEN_128 = {{1'd0}, _T_84}; // @[Mux.scala 27:72] - wire [2:0] _T_85 = _GEN_128 | _T_82; // @[Mux.scala 27:72] - wire [3:0] _GEN_129 = {{1'd0}, _T_85}; // @[Mux.scala 27:72] - wire [3:0] cam_wen = _GEN_129 | _T_83; // @[Mux.scala 27:72] - reg x_d_bits_i0load; // @[el2_lib.scala 524:16] - reg [4:0] x_d_bits_i0rd; // @[el2_lib.scala 524:16] - wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 318:31] - reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 656:72] + wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 644:46] + wire _T_33 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 243:72] + wire _T_36 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:89] + wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_fence_i = _T_41 ? 1'h0 : i0_dp_raw_fence_i; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_fence = _T_41 ? 1'h0 : i0_dp_raw_fence; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_div = i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_div = _T_41 ? 1'h0 : i0_dp_raw_div; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_low = i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_mul = _T_41 ? 1'h0 : i0_dp_raw_mul; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_mret = _T_41 ? 1'h0 : i0_dp_raw_mret; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_ecall = _T_41 ? 1'h0 : i0_dp_raw_ecall; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_ebreak = _T_41 ? 1'h0 : i0_dp_raw_ebreak; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_presync = _T_41 ? 1'h0 : i0_dp_raw_presync; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_set = _T_41 ? 1'h0 : i0_dp_raw_csr_set; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_csr_clr = _T_41 ? 1'h0 : i0_dp_raw_csr_clr; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_word = i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_word = _T_41 ? 1'h0 : i0_dp_raw_word; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_half = i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_half = _T_41 ? 1'h0 : i0_dp_raw_half; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_by = i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_by = _T_41 ? 1'h0 : i0_dp_raw_by; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_jal = _T_41 ? 1'h0 : i0_dp_raw_jal; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_condbr = _T_41 ? 1'h0 : i0_dp_raw_condbr; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_land = i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_add = i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_lsu = _T_41 ? 1'h0 : i0_dp_raw_lsu; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_store = i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_store = _T_41 ? 1'h0 : i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_load = i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_load = _T_41 ? 1'h0 : i0_dp_raw_load; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_imm20 = _T_41 ? 1'h0 : i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_shimm5 = _T_41 ? 1'h0 : i0_dp_raw_shimm5; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_rd = _T_41 ? 1'h0 : i0_dp_raw_rd; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_imm12 = _T_41 ? 1'h0 : i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_rs2 = _T_41 | i0_dp_raw_rs2; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_rs1 = _T_41 | i0_dp_raw_rs1; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] + wire i0_dp_alu = _T_41 | i0_dp_raw_alu; // @[el2_dec_decode_ctl.scala 260:50] + wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 412:38] + wire _T_44 = i0_dp_condbr | i0_pcall; // @[el2_dec_decode_ctl.scala 274:38] + wire i0_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 414:38] + wire _T_45 = _T_44 | i0_pja; // @[el2_dec_decode_ctl.scala 274:49] + wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 419:32] + wire i0_predict_br = _T_45 | i0_pret; // @[el2_dec_decode_ctl.scala 274:58] + wire _T_47 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:50] + wire _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26] + wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20] + wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63] + reg [2:0] cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_94 = _GEN_123 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_95 = cam_data_reset & _T_94; // @[el2_dec_decode_ctl.scala 322:45] + reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 347:47] + wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:83] + wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:39] + wire _T_51 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 303:78] + reg [2:0] cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_120 = _GEN_123 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_121 = cam_data_reset & _T_120; // @[el2_dec_decode_ctl.scala 322:45] + reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 347:47] + wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:83] + wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:39] + wire _T_54 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 303:78] + wire _T_57 = cam_0_valid & _T_54; // @[el2_dec_decode_ctl.scala 303:126] + wire [1:0] _T_59 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 303:158] + reg [2:0] cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_146 = _GEN_123 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_147 = cam_data_reset & _T_146; // @[el2_dec_decode_ctl.scala 322:45] + reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 347:47] + wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:83] + wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:39] + wire _T_60 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 303:78] + wire _T_63 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 303:126] + wire _T_66 = _T_63 & _T_60; // @[el2_dec_decode_ctl.scala 303:126] + wire [2:0] _T_68 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 303:158] + reg [2:0] cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_172 = _GEN_123 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_173 = cam_data_reset & _T_172; // @[el2_dec_decode_ctl.scala 322:45] + reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 347:47] + wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:83] + wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:39] + wire _T_69 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 303:78] + wire _T_75 = _T_63 & cam_2_valid; // @[el2_dec_decode_ctl.scala 303:126] + wire _T_78 = _T_75 & _T_69; // @[el2_dec_decode_ctl.scala 303:126] + wire [3:0] _T_80 = {io_lsu_nonblock_load_valid_m, 3'h0}; // @[el2_dec_decode_ctl.scala 303:158] + wire _T_81 = _T_51 & io_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] + wire [1:0] _T_82 = _T_57 ? _T_59 : 2'h0; // @[Mux.scala 27:72] + wire [2:0] _T_83 = _T_66 ? _T_68 : 3'h0; // @[Mux.scala 27:72] + wire [3:0] _T_84 = _T_78 ? _T_80 : 4'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_127 = {{1'd0}, _T_81}; // @[Mux.scala 27:72] + wire [1:0] _T_85 = _GEN_127 | _T_82; // @[Mux.scala 27:72] + wire [2:0] _GEN_128 = {{1'd0}, _T_85}; // @[Mux.scala 27:72] + wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72] + wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72] + wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] + reg x_d_i0load; // @[el2_lib.scala 524:16] + reg [4:0] x_d_i0rd; // @[el2_lib.scala 524:16] + wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] + reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] - wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 659:49] - wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 659:53] + wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49] + wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] - reg r_d_bits_i0load; // @[el2_lib.scala 524:16] - wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 323:56] - wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_90 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_91 = io_lsu_nonblock_load_inv_r & _T_90; // @[el2_dec_decode_ctl.scala 325:45] - wire cam_inv_reset_val_0 = _T_91 & cam_0_valid; // @[el2_dec_decode_ctl.scala 325:87] - reg r_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 691:51] - wire r_d_in_bits_i0v = r_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 691:49] - wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 699:47] - wire i0_wen_r = r_d_in_bits_i0v & _T_754; // @[el2_dec_decode_ctl.scala 699:45] - reg [4:0] r_d_bits_i0rd; // @[el2_lib.scala 524:16] - reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_102 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 338:85] - wire _T_103 = i0_wen_r & _T_102; // @[el2_dec_decode_ctl.scala 338:64] - reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_105 = _T_103 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 338:105] - wire _T_106 = cam_inv_reset_val_0 | _T_105; // @[el2_dec_decode_ctl.scala 338:44] - wire _GEN_52 = _T_106 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_55 = _T_106 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 333:28] - wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 333:28] - wire _T_109 = nonblock_load_valid_m_delay & _T_90; // @[el2_dec_decode_ctl.scala 343:44] - wire _T_111 = _T_109 & cam_0_valid; // @[el2_dec_decode_ctl.scala 343:100] - wire nonblock_load_write_0 = _T_93 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 352:71] - wire _T_116 = _GEN_130 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_117 = io_lsu_nonblock_load_inv_r & _T_116; // @[el2_dec_decode_ctl.scala 325:45] - wire cam_inv_reset_val_1 = _T_117 & cam_1_valid; // @[el2_dec_decode_ctl.scala 325:87] - reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_128 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 338:85] - wire _T_129 = i0_wen_r & _T_128; // @[el2_dec_decode_ctl.scala 338:64] - reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_131 = _T_129 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 338:105] - wire _T_132 = cam_inv_reset_val_1 | _T_131; // @[el2_dec_decode_ctl.scala 338:44] - wire _GEN_63 = _T_132 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_66 = _T_132 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 333:28] - wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 333:28] - wire _T_135 = nonblock_load_valid_m_delay & _T_116; // @[el2_dec_decode_ctl.scala 343:44] - wire _T_137 = _T_135 & cam_1_valid; // @[el2_dec_decode_ctl.scala 343:100] - wire nonblock_load_write_1 = _T_119 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 352:71] - wire _T_142 = _GEN_130 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_143 = io_lsu_nonblock_load_inv_r & _T_142; // @[el2_dec_decode_ctl.scala 325:45] - wire cam_inv_reset_val_2 = _T_143 & cam_2_valid; // @[el2_dec_decode_ctl.scala 325:87] - reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_154 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 338:85] - wire _T_155 = i0_wen_r & _T_154; // @[el2_dec_decode_ctl.scala 338:64] - reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_157 = _T_155 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 338:105] - wire _T_158 = cam_inv_reset_val_2 | _T_157; // @[el2_dec_decode_ctl.scala 338:44] - wire _GEN_74 = _T_158 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_77 = _T_158 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 333:28] - wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 333:28] - wire _T_161 = nonblock_load_valid_m_delay & _T_142; // @[el2_dec_decode_ctl.scala 343:44] - wire _T_163 = _T_161 & cam_2_valid; // @[el2_dec_decode_ctl.scala 343:100] - wire nonblock_load_write_2 = _T_145 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 352:71] - wire _T_168 = _GEN_130 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 325:66] - wire _T_169 = io_lsu_nonblock_load_inv_r & _T_168; // @[el2_dec_decode_ctl.scala 325:45] - wire cam_inv_reset_val_3 = _T_169 & cam_3_valid; // @[el2_dec_decode_ctl.scala 325:87] - reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_180 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 338:85] - wire _T_181 = i0_wen_r & _T_180; // @[el2_dec_decode_ctl.scala 338:64] - reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 351:47] - wire _T_183 = _T_181 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 338:105] - wire _T_184 = cam_inv_reset_val_3 | _T_183; // @[el2_dec_decode_ctl.scala 338:44] - wire _GEN_85 = _T_184 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_88 = _T_184 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 338:131] - wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 333:28] - wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 333:28] - wire _T_187 = nonblock_load_valid_m_delay & _T_168; // @[el2_dec_decode_ctl.scala 343:44] - wire _T_189 = _T_187 & cam_3_valid; // @[el2_dec_decode_ctl.scala 343:100] - wire nonblock_load_write_3 = _T_171 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 352:71] - wire _T_194 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 357:49] - wire nonblock_load_cancel = _T_194 & i0_wen_r; // @[el2_dec_decode_ctl.scala 357:81] - wire _T_195 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 358:95] - wire _T_196 = _T_195 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 358:95] - wire _T_197 = _T_196 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 358:95] - wire _T_199 = io_lsu_nonblock_load_data_valid & _T_197; // @[el2_dec_decode_ctl.scala 358:64] - wire _T_200 = ~nonblock_load_cancel; // @[el2_dec_decode_ctl.scala 358:109] - wire _T_202 = nonblock_load_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:54] - wire _T_203 = _T_202 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 359:66] - wire _T_204 = _T_203 & io_dec_i0_rs1_en_d; // @[el2_dec_decode_ctl.scala 359:97] - wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 625:16] - wire _T_205 = nonblock_load_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:137] - wire _T_206 = _T_205 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 359:149] - wire _T_207 = _T_206 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 359:180] - wire i0_nonblock_boundary_stall = _T_204 | _T_207; // @[el2_dec_decode_ctl.scala 359:118] - wire [4:0] _T_209 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_210 = _T_209 & cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 363:88] - wire _T_211 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 363:126] - wire _T_212 = cam_raw_0_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:159] - wire _T_213 = _T_211 & _T_212; // @[el2_dec_decode_ctl.scala 363:141] - wire _T_214 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 363:192] - wire _T_215 = cam_raw_0_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:225] - wire _T_216 = _T_214 & _T_215; // @[el2_dec_decode_ctl.scala 363:207] - wire [4:0] _T_218 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_219 = _T_218 & cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 363:88] - wire _T_220 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 363:126] - wire _T_221 = cam_raw_1_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:159] - wire _T_222 = _T_220 & _T_221; // @[el2_dec_decode_ctl.scala 363:141] - wire _T_223 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 363:192] - wire _T_224 = cam_raw_1_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:225] - wire _T_225 = _T_223 & _T_224; // @[el2_dec_decode_ctl.scala 363:207] - wire [4:0] _T_227 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_228 = _T_227 & cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 363:88] - wire _T_229 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 363:126] - wire _T_230 = cam_raw_2_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:159] - wire _T_231 = _T_229 & _T_230; // @[el2_dec_decode_ctl.scala 363:141] - wire _T_232 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 363:192] - wire _T_233 = cam_raw_2_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:225] - wire _T_234 = _T_232 & _T_233; // @[el2_dec_decode_ctl.scala 363:207] - wire [4:0] _T_236 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_237 = _T_236 & cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 363:88] - wire _T_238 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 363:126] - wire _T_239 = cam_raw_3_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:159] - wire _T_240 = _T_238 & _T_239; // @[el2_dec_decode_ctl.scala 363:141] - wire _T_241 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 363:192] - wire _T_242 = cam_raw_3_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:225] - wire _T_243 = _T_241 & _T_242; // @[el2_dec_decode_ctl.scala 363:207] - wire [4:0] _T_244 = _T_210 | _T_219; // @[el2_dec_decode_ctl.scala 364:69] - wire [4:0] _T_245 = _T_244 | _T_228; // @[el2_dec_decode_ctl.scala 364:69] - wire _T_246 = _T_213 | _T_222; // @[el2_dec_decode_ctl.scala 364:102] - wire _T_247 = _T_246 | _T_231; // @[el2_dec_decode_ctl.scala 364:102] - wire ld_stall_1 = _T_247 | _T_240; // @[el2_dec_decode_ctl.scala 364:102] - wire _T_248 = _T_216 | _T_225; // @[el2_dec_decode_ctl.scala 364:134] - wire _T_249 = _T_248 | _T_234; // @[el2_dec_decode_ctl.scala 364:134] - wire ld_stall_2 = _T_249 | _T_243; // @[el2_dec_decode_ctl.scala 364:134] - wire _T_250 = ld_stall_1 | ld_stall_2; // @[el2_dec_decode_ctl.scala 366:38] - wire i0_nonblock_load_stall = _T_250 | i0_nonblock_boundary_stall; // @[el2_dec_decode_ctl.scala 366:51] - wire _T_252 = ~i0_predict_br; // @[el2_dec_decode_ctl.scala 375:34] - wire [3:0] _T_254 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 459:36] - wire _T_255 = csr_read & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 387:16] - wire _T_257 = ~csr_read; // @[el2_dec_decode_ctl.scala 388:6] - wire _T_258 = _T_257 & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 388:16] - wire _T_260 = ~io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 389:18] - wire _T_261 = csr_read & _T_260; // @[el2_dec_decode_ctl.scala 389:16] - wire [3:0] _T_263 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] - wire [3:0] _T_264 = i0_dp_load ? 4'h2 : _T_263; // @[Mux.scala 98:16] - wire [3:0] _T_265 = i0_dp_store ? 4'h3 : _T_264; // @[Mux.scala 98:16] - wire [3:0] _T_266 = i0_dp_pm_alu ? 4'h4 : _T_265; // @[Mux.scala 98:16] - wire [3:0] _T_267 = _T_261 ? 4'h5 : _T_266; // @[Mux.scala 98:16] - wire [3:0] _T_268 = _T_258 ? 4'h6 : _T_267; // @[Mux.scala 98:16] - wire [3:0] _T_269 = _T_255 ? 4'h7 : _T_268; // @[Mux.scala 98:16] - wire [3:0] _T_270 = i0_dp_ebreak ? 4'h8 : _T_269; // @[Mux.scala 98:16] - wire [3:0] _T_271 = i0_dp_ecall ? 4'h9 : _T_270; // @[Mux.scala 98:16] - wire [3:0] _T_272 = i0_dp_fence ? 4'ha : _T_271; // @[Mux.scala 98:16] - wire [3:0] _T_273 = i0_dp_fence_i ? 4'hb : _T_272; // @[Mux.scala 98:16] - wire [3:0] _T_274 = i0_dp_mret ? 4'hc : _T_273; // @[Mux.scala 98:16] - wire [3:0] _T_275 = i0_dp_condbr ? 4'hd : _T_274; // @[Mux.scala 98:16] - wire [3:0] _T_276 = i0_dp_jal ? 4'he : _T_275; // @[Mux.scala 98:16] - reg lsu_idle; // @[el2_dec_decode_ctl.scala 400:45] - wire _T_333 = ~i0_pcall_case; // @[el2_dec_decode_ctl.scala 424:35] - wire _T_334 = i0_dp_jal & _T_333; // @[el2_dec_decode_ctl.scala 424:32] - wire _T_335 = ~i0_pja_case; // @[el2_dec_decode_ctl.scala 424:52] - wire _T_336 = _T_334 & _T_335; // @[el2_dec_decode_ctl.scala 424:50] - wire _T_337 = ~i0_pret_case; // @[el2_dec_decode_ctl.scala 424:67] - reg _T_339; // @[el2_dec_decode_ctl.scala 436:58] - wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 578:40] - wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 792:43] - reg x_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_876 = io_dec_i0_rs1_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 772:48] - wire _T_877 = x_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 772:80] - wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 772:63] - wire _T_878 = io_dec_i0_rs1_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 773:48] - wire _T_879 = r_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 773:80] - wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 773:63] - wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 779:63] - wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 779:24] - wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 792:58] + reg r_d_i0load; // @[el2_lib.scala 524:16] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 319:56] + wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_91 = _GEN_130 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45] + wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg r_d_i0v; // @[el2_lib.scala 524:16] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:41] + wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:39] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:42] + wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:40] + reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16] + reg [4:0] cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_103 = r_d_i0rd == cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 334:80] + wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64] + reg cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_106 = _T_104 & cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:95] + wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44] + wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28] + wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28] + wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44] + wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_117 = _GEN_130 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45] + wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg [4:0] cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_129 = r_d_i0rd == cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 334:80] + wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64] + reg cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_132 = _T_130 & cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:95] + wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44] + wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28] + wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28] + wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44] + wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_143 = _GEN_130 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45] + wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg [4:0] cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_155 = r_d_i0rd == cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 334:80] + wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64] + reg cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_158 = _T_156 & cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:95] + wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44] + wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28] + wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28] + wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44] + wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_169 = _GEN_130 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45] + wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg [4:0] cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_181 = r_d_i0rd == cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 334:80] + wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64] + reg cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_184 = _T_182 & cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:95] + wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44] + wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28] + wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28] + wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44] + wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_195 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:44] + wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:76] + wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95] + wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95] + wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95] + wire _T_200 = io_lsu_nonblock_load_data_valid & _T_198; // @[el2_dec_decode_ctl.scala 354:64] + wire _T_201 = ~nonblock_load_cancel; // @[el2_dec_decode_ctl.scala 354:109] + wire _T_203 = nonblock_load_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 355:54] + wire _T_204 = _T_203 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 355:66] + wire _T_205 = _T_204 & io_dec_i0_rs1_en_d; // @[el2_dec_decode_ctl.scala 355:97] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 621:16] + wire _T_206 = nonblock_load_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 355:137] + wire _T_207 = _T_206 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 355:149] + wire _T_208 = _T_207 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 355:180] + wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[el2_dec_decode_ctl.scala 355:118] + wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_211 = _T_210 & cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_213 = cam_raw_0_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_216 = cam_raw_0_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:197] + wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_220 = _T_219 & cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_222 = cam_raw_1_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_225 = cam_raw_1_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:197] + wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_229 = _T_228 & cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_231 = cam_raw_2_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_234 = cam_raw_2_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:197] + wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_238 = _T_237 & cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_240 = cam_raw_3_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_243 = cam_raw_3_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:197] + wire [4:0] _T_245 = _T_211 | _T_220; // @[el2_dec_decode_ctl.scala 360:69] + wire [4:0] _T_246 = _T_245 | _T_229; // @[el2_dec_decode_ctl.scala 360:69] + wire _T_247 = _T_214 | _T_223; // @[el2_dec_decode_ctl.scala 360:102] + wire _T_248 = _T_247 | _T_232; // @[el2_dec_decode_ctl.scala 360:102] + wire ld_stall_1 = _T_248 | _T_241; // @[el2_dec_decode_ctl.scala 360:102] + wire _T_249 = _T_217 | _T_226; // @[el2_dec_decode_ctl.scala 360:134] + wire _T_250 = _T_249 | _T_235; // @[el2_dec_decode_ctl.scala 360:134] + wire ld_stall_2 = _T_250 | _T_244; // @[el2_dec_decode_ctl.scala 360:134] + wire _T_251 = ld_stall_1 | ld_stall_2; // @[el2_dec_decode_ctl.scala 362:38] + wire i0_nonblock_load_stall = _T_251 | i0_nonblock_boundary_stall; // @[el2_dec_decode_ctl.scala 362:51] + wire _T_253 = ~i0_predict_br; // @[el2_dec_decode_ctl.scala 371:34] + wire [3:0] _T_255 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 455:36] + wire _T_256 = csr_read & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 383:16] + wire _T_258 = ~csr_read; // @[el2_dec_decode_ctl.scala 384:6] + wire _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 384:16] + wire _T_261 = ~io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 385:18] + wire _T_262 = csr_read & _T_261; // @[el2_dec_decode_ctl.scala 385:16] + wire [3:0] _T_264 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] + wire [3:0] _T_265 = i0_dp_load ? 4'h2 : _T_264; // @[Mux.scala 98:16] + wire [3:0] _T_266 = i0_dp_store ? 4'h3 : _T_265; // @[Mux.scala 98:16] + wire [3:0] _T_267 = i0_dp_pm_alu ? 4'h4 : _T_266; // @[Mux.scala 98:16] + wire [3:0] _T_268 = _T_262 ? 4'h5 : _T_267; // @[Mux.scala 98:16] + wire [3:0] _T_269 = _T_259 ? 4'h6 : _T_268; // @[Mux.scala 98:16] + wire [3:0] _T_270 = _T_256 ? 4'h7 : _T_269; // @[Mux.scala 98:16] + wire [3:0] _T_271 = i0_dp_ebreak ? 4'h8 : _T_270; // @[Mux.scala 98:16] + wire [3:0] _T_272 = i0_dp_ecall ? 4'h9 : _T_271; // @[Mux.scala 98:16] + wire [3:0] _T_273 = i0_dp_fence ? 4'ha : _T_272; // @[Mux.scala 98:16] + wire [3:0] _T_274 = i0_dp_fence_i ? 4'hb : _T_273; // @[Mux.scala 98:16] + wire [3:0] _T_275 = i0_dp_mret ? 4'hc : _T_274; // @[Mux.scala 98:16] + wire [3:0] _T_276 = i0_dp_condbr ? 4'hd : _T_275; // @[Mux.scala 98:16] + wire [3:0] _T_277 = i0_dp_jal ? 4'he : _T_276; // @[Mux.scala 98:16] + reg lsu_idle; // @[el2_dec_decode_ctl.scala 396:45] + wire _T_333 = ~i0_pcall_case; // @[el2_dec_decode_ctl.scala 420:35] + wire _T_334 = i0_dp_jal & _T_333; // @[el2_dec_decode_ctl.scala 420:32] + wire _T_335 = ~i0_pja_case; // @[el2_dec_decode_ctl.scala 420:52] + wire _T_336 = _T_334 & _T_335; // @[el2_dec_decode_ctl.scala 420:50] + wire _T_337 = ~i0_pret_case; // @[el2_dec_decode_ctl.scala 420:67] + reg _T_339; // @[el2_dec_decode_ctl.scala 432:58] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40] + wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43] + reg x_d_i0v; // @[el2_lib.scala 524:16] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 768:48] + wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:70] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:58] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 769:48] + wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:70] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:58] + wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24] + wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58] reg i0_x_c_load; // @[Reg.scala 15:16] reg i0_r_c_load; // @[Reg.scala 15:16] - wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 778:61] - wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 778:24] - wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 792:78] - wire _T_880 = io_dec_i0_rs2_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 775:48] - wire _T_881 = x_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 775:80] - wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 775:63] - wire _T_882 = io_dec_i0_rs2_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 776:48] - wire _T_883 = r_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 776:80] - wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 776:63] - wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 781:63] - wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 781:24] - wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 793:43] - wire _T_896_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 780:61] - wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 780:24] - wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 793:63] - wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 467:42] - reg r_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg r_d_valid; // @[el2_lib.scala 524:16] - wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[el2_dec_decode_ctl.scala 475:39] - reg [11:0] r_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 478:50] - wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 478:85] - wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 478:64] - wire _T_358 = _T_357 & r_d_bits_csrwen; // @[el2_dec_decode_ctl.scala 478:100] - wire _T_359 = _T_358 & r_d_valid; // @[el2_dec_decode_ctl.scala 478:118] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 478:132] - reg csr_read_x; // @[el2_dec_decode_ctl.scala 480:52] - reg csr_clr_x; // @[el2_dec_decode_ctl.scala 481:51] - reg csr_set_x; // @[el2_dec_decode_ctl.scala 482:51] - reg csr_write_x; // @[el2_dec_decode_ctl.scala 483:53] - reg csr_imm_x; // @[el2_dec_decode_ctl.scala 484:51] - wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[el2_dec_decode_ctl.scala 661:50] + wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24] + wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48] + wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:70] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:58] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:70] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:58] + wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24] + wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43] + wire _T_896_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 776:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24] + wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63] + wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42] + reg r_d_csrwen; // @[el2_lib.scala 524:16] + reg r_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 471:34] + reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:45] + wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:75] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:59] + wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 474:90] + wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:103] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:119] + reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52] + reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51] + reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51] + reg csr_write_x; // @[el2_dec_decode_ctl.scala 479:53] + reg csr_imm_x; // @[el2_dec_decode_ctl.scala 480:51] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[el2_dec_decode_ctl.scala 657:50] reg [4:0] csrimm_x; // @[el2_lib.scala 514:16] reg [31:0] csr_rddata_x; // @[el2_lib.scala 514:16] wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] - wire _T_396 = ~csr_imm_x; // @[el2_dec_decode_ctl.scala 492:5] + wire _T_396 = ~csr_imm_x; // @[el2_dec_decode_ctl.scala 488:5] wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_398 = _T_396 ? io_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] csr_mask_x = _T_397 | _T_398; // @[Mux.scala 27:72] - wire [31:0] _T_400 = ~csr_mask_x; // @[el2_dec_decode_ctl.scala 495:38] - wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[el2_dec_decode_ctl.scala 495:35] - wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[el2_dec_decode_ctl.scala 496:35] + wire [31:0] _T_400 = ~csr_mask_x; // @[el2_dec_decode_ctl.scala 491:38] + wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[el2_dec_decode_ctl.scala 491:35] + wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[el2_dec_decode_ctl.scala 492:35] wire [31:0] _T_403 = csr_clr_x ? _T_401 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_404 = csr_set_x ? _T_402 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_405 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_406 = _T_403 | _T_404; // @[Mux.scala 27:72] wire [31:0] write_csr_data_x = _T_406 | _T_405; // @[Mux.scala 27:72] - wire _T_418 = ~tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 506:44] - wire _T_419 = ~tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 506:64] - wire _T_420 = _T_418 & _T_419; // @[el2_dec_decode_ctl.scala 506:61] - wire [31:0] _T_423 = write_csr_data - 32'h1; // @[el2_dec_decode_ctl.scala 509:59] - wire _T_425 = csr_clr_x | csr_set_x; // @[el2_dec_decode_ctl.scala 511:34] - wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 511:46] - wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 511:61] - wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 511:75] - reg r_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_764 = r_d_bits_i0v & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 714:42] + wire _T_418 = ~tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 502:44] + wire _T_419 = ~tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 502:64] + wire _T_420 = _T_418 & _T_419; // @[el2_dec_decode_ctl.scala 502:61] + wire [31:0] _T_423 = write_csr_data - 32'h1; // @[el2_dec_decode_ctl.scala 505:59] + wire _T_425 = csr_clr_x | csr_set_x; // @[el2_dec_decode_ctl.scala 507:34] + wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46] + wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61] + wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75] + reg r_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 710:37] reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] - wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 714:27] - reg x_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_432 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[el2_dec_decode_ctl.scala 520:43] - reg wbd_bits_csrwonly; // @[el2_lib.scala 524:16] - wire prior_csr_write = _T_432 | wbd_bits_csrwonly; // @[el2_dec_decode_ctl.scala 520:63] - wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 523:48] - wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 524:40] - wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 527:34] - wire _T_437 = _T_436 | debug_fence_i; // @[el2_dec_decode_ctl.scala 527:57] - wire _T_438 = _T_437 | debug_fence_raw; // @[el2_dec_decode_ctl.scala 527:73] - wire i0_presync = _T_438 | io_dec_tlu_pipelining_disable; // @[el2_dec_decode_ctl.scala 527:91] + wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27] + reg x_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 516:38] + reg wbd_csrwonly; // @[el2_lib.scala 524:16] + wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 516:53] + wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48] + wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40] + wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34] + wire _T_437 = _T_436 | debug_fence_i; // @[el2_dec_decode_ctl.scala 523:57] + wire _T_438 = _T_437 | debug_fence_raw; // @[el2_dec_decode_ctl.scala 523:73] + wire i0_presync = _T_438 | io_dec_tlu_pipelining_disable; // @[el2_dec_decode_ctl.scala 523:91] wire [31:0] _T_462 = {16'h0,io_ifu_i0_cinst}; // @[Cat.scala 29:58] - wire _T_464 = ~illegal_lockout; // @[el2_dec_decode_ctl.scala 539:44] + wire _T_464 = ~illegal_lockout; // @[el2_dec_decode_ctl.scala 535:44] reg [31:0] _T_465; // @[el2_lib.scala 514:16] - wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[el2_dec_decode_ctl.scala 543:42] - wire _T_470 = i0_dp_csr_read & prior_csr_write; // @[el2_dec_decode_ctl.scala 545:40] - wire _T_471 = _T_470 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 545:59] - wire _T_472 = _T_471 | pause_stall; // @[el2_dec_decode_ctl.scala 545:81] - wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 545:95] - wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 546:20] - wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 546:45] - wire prior_inflight = x_d_valid | r_d_valid; // @[el2_dec_decode_ctl.scala 568:41] - wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[el2_dec_decode_ctl.scala 569:31] - wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 571:37] - wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 546:62] - wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 547:19] - wire _T_478 = ~lsu_idle; // @[el2_dec_decode_ctl.scala 547:36] - wire _T_479 = _T_477 & _T_478; // @[el2_dec_decode_ctl.scala 547:34] - wire _T_480 = _T_476 | _T_479; // @[el2_dec_decode_ctl.scala 546:79] - wire _T_481 = _T_480 | i0_nonblock_load_stall; // @[el2_dec_decode_ctl.scala 547:47] - wire _T_822 = io_dec_i0_rs1_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 742:49] - wire _T_823 = io_div_waddr_wb == i0r_rs1; // @[el2_dec_decode_ctl.scala 742:88] - wire _T_824 = _T_822 & _T_823; // @[el2_dec_decode_ctl.scala 742:69] - wire _T_825 = io_dec_i0_rs2_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 743:25] - wire _T_826 = io_div_waddr_wb == i0r_rs2; // @[el2_dec_decode_ctl.scala 743:64] - wire _T_827 = _T_825 & _T_826; // @[el2_dec_decode_ctl.scala 743:45] - wire i0_nonblock_div_stall = _T_824 | _T_827; // @[el2_dec_decode_ctl.scala 742:102] - wire _T_483 = _T_481 | i0_nonblock_div_stall; // @[el2_dec_decode_ctl.scala 548:21] - wire i0_block_raw_d = _T_483 | i0_div_prior_div_stall; // @[el2_dec_decode_ctl.scala 548:45] - wire _T_484 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 550:65] - wire i0_store_stall_d = i0_dp_store & _T_484; // @[el2_dec_decode_ctl.scala 550:39] - wire _T_485 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 551:63] - wire i0_load_stall_d = i0_dp_load & _T_485; // @[el2_dec_decode_ctl.scala 551:38] - wire _T_486 = i0_block_raw_d | i0_store_stall_d; // @[el2_dec_decode_ctl.scala 552:38] - wire i0_block_d = _T_486 | i0_load_stall_d; // @[el2_dec_decode_ctl.scala 552:57] - wire _T_487 = ~i0_block_d; // @[el2_dec_decode_ctl.scala 556:46] - wire _T_488 = io_dec_ib0_valid_d & _T_487; // @[el2_dec_decode_ctl.scala 556:44] - wire _T_490 = _T_488 & _T_279; // @[el2_dec_decode_ctl.scala 556:61] - wire _T_493 = ~i0_block_raw_d; // @[el2_dec_decode_ctl.scala 557:46] - wire _T_494 = io_dec_ib0_valid_d & _T_493; // @[el2_dec_decode_ctl.scala 557:44] - wire _T_496 = _T_494 & _T_279; // @[el2_dec_decode_ctl.scala 557:61] - wire i0_exudecode_d = _T_496 & _T_467; // @[el2_dec_decode_ctl.scala 557:89] - wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[el2_dec_decode_ctl.scala 558:46] - wire _T_498 = ~io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 562:51] - wire _T_517 = i0_dp_fence_i | debug_fence_i; // @[el2_dec_decode_ctl.scala 590:44] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[el2_dec_decode_ctl.scala 539:42] + wire _T_470 = i0_dp_csr_read & prior_csr_write; // @[el2_dec_decode_ctl.scala 541:40] + wire _T_471 = _T_470 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 541:59] + wire _T_472 = _T_471 | pause_stall; // @[el2_dec_decode_ctl.scala 541:81] + wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95] + wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20] + wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45] + wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 564:41] + wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37] + wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62] + wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19] + wire _T_478 = ~lsu_idle; // @[el2_dec_decode_ctl.scala 543:36] + wire _T_479 = _T_477 & _T_478; // @[el2_dec_decode_ctl.scala 543:34] + wire _T_480 = _T_476 | _T_479; // @[el2_dec_decode_ctl.scala 542:79] + wire _T_481 = _T_480 | i0_nonblock_load_stall; // @[el2_dec_decode_ctl.scala 543:47] + wire _T_822 = io_dec_i0_rs1_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 738:49] + wire _T_823 = io_div_waddr_wb == i0r_rs1; // @[el2_dec_decode_ctl.scala 738:88] + wire _T_824 = _T_822 & _T_823; // @[el2_dec_decode_ctl.scala 738:69] + wire _T_825 = io_dec_i0_rs2_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 739:25] + wire _T_826 = io_div_waddr_wb == i0r_rs2; // @[el2_dec_decode_ctl.scala 739:64] + wire _T_827 = _T_825 & _T_826; // @[el2_dec_decode_ctl.scala 739:45] + wire i0_nonblock_div_stall = _T_824 | _T_827; // @[el2_dec_decode_ctl.scala 738:102] + wire _T_483 = _T_481 | i0_nonblock_div_stall; // @[el2_dec_decode_ctl.scala 544:21] + wire i0_block_raw_d = _T_483 | i0_div_prior_div_stall; // @[el2_dec_decode_ctl.scala 544:45] + wire _T_484 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 546:65] + wire i0_store_stall_d = i0_dp_store & _T_484; // @[el2_dec_decode_ctl.scala 546:39] + wire _T_485 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 547:63] + wire i0_load_stall_d = i0_dp_load & _T_485; // @[el2_dec_decode_ctl.scala 547:38] + wire _T_486 = i0_block_raw_d | i0_store_stall_d; // @[el2_dec_decode_ctl.scala 548:38] + wire i0_block_d = _T_486 | i0_load_stall_d; // @[el2_dec_decode_ctl.scala 548:57] + wire _T_487 = ~i0_block_d; // @[el2_dec_decode_ctl.scala 552:46] + wire _T_488 = io_dec_ib0_valid_d & _T_487; // @[el2_dec_decode_ctl.scala 552:44] + wire _T_490 = _T_488 & _T_280; // @[el2_dec_decode_ctl.scala 552:61] + wire _T_493 = ~i0_block_raw_d; // @[el2_dec_decode_ctl.scala 553:46] + wire _T_494 = io_dec_ib0_valid_d & _T_493; // @[el2_dec_decode_ctl.scala 553:44] + wire _T_496 = _T_494 & _T_280; // @[el2_dec_decode_ctl.scala 553:61] + wire i0_exudecode_d = _T_496 & _T_467; // @[el2_dec_decode_ctl.scala 553:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[el2_dec_decode_ctl.scala 554:46] + wire _T_498 = ~io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 558:51] + wire _T_517 = i0_dp_fence_i | debug_fence_i; // @[el2_dec_decode_ctl.scala 586:44] wire [3:0] _T_522 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58] - wire _T_704 = |i0_pipe_en[3:2]; // @[el2_dec_decode_ctl.scala 658:49] - wire i0_x_ctl_en = _T_704 | io_clk_override; // @[el2_dec_decode_ctl.scala 658:53] + wire _T_704 = |i0_pipe_en[3:2]; // @[el2_dec_decode_ctl.scala 654:49] + wire i0_x_ctl_en = _T_704 | io_clk_override; // @[el2_dec_decode_ctl.scala 654:53] reg x_t_legal; // @[el2_lib.scala 524:16] reg x_t_icaf; // @[el2_lib.scala 524:16] reg x_t_icaf_f1; // @[el2_lib.scala 524:16] @@ -46839,7 +46871,7 @@ module el2_dec_decode_ctl( reg [3:0] x_t_pmu_i0_itype; // @[el2_lib.scala 524:16] reg x_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] wire [3:0] _T_530 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] - wire [3:0] _T_531 = ~_T_530; // @[el2_dec_decode_ctl.scala 603:39] + wire [3:0] _T_531 = ~_T_530; // @[el2_dec_decode_ctl.scala 599:39] reg r_t_legal; // @[el2_lib.scala 524:16] reg r_t_icaf; // @[el2_lib.scala 524:16] reg r_t_icaf_f1; // @[el2_lib.scala 524:16] @@ -46848,22 +46880,22 @@ module el2_dec_decode_ctl( reg [3:0] r_t_i0trigger; // @[el2_lib.scala 524:16] reg [3:0] r_t_pmu_i0_itype; // @[el2_lib.scala 524:16] reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] - reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 606:36] - reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 607:37] - reg r_d_bits_i0store; // @[el2_lib.scala 524:16] - wire _T_536 = r_d_bits_i0load | r_d_bits_i0store; // @[el2_dec_decode_ctl.scala 611:61] + reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36] + reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37] + reg r_d_i0store; // @[el2_lib.scala 524:16] + wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 607:56] wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] - wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 611:82] - wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 611:105] - reg r_d_bits_i0div; // @[el2_lib.scala 524:16] - wire _T_545 = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 617:58] - wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 628:49] - wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 629:49] - wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 630:48] - wire i0_rd_en_d = i0_dp_rd & _T_560; // @[el2_dec_decode_ctl.scala 630:37] - wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 634:38] - wire _T_561 = ~i0_dp_jal; // @[el2_dec_decode_ctl.scala 635:27] - wire i0_uiimm20 = _T_561 & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 635:38] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:72] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:95] + reg r_d_i0div; // @[el2_lib.scala 524:16] + wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 613:53] + wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49] + wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49] + wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48] + wire i0_rd_en_d = i0_dp_rd & _T_560; // @[el2_dec_decode_ctl.scala 626:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 630:38] + wire _T_561 = ~i0_dp_jal; // @[el2_dec_decode_ctl.scala 631:27] + wire i0_uiimm20 = _T_561 & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 631:38] wire [31:0] _T_563 = i0_dp_csr_read ? io_dec_csr_rddata_d : 32'h0; // @[Mux.scala 27:72] wire [9:0] _T_577 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] wire [18:0] _T_586 = {_T_577,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] @@ -46878,55 +46910,55 @@ module el2_dec_decode_ctl( wire [31:0] _T_652 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] wire [31:0] _T_687 = i0_uiimm20 ? _T_652 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_691 = _T_690 | _T_687; // @[Mux.scala 27:72] - wire _T_653 = i0_csr_write_only_d & i0_dp_csr_imm; // @[el2_dec_decode_ctl.scala 646:26] + wire _T_653 = i0_csr_write_only_d & i0_dp_csr_imm; // @[el2_dec_decode_ctl.scala 642:26] wire [31:0] _T_683 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] wire [31:0] _T_688 = _T_653 ? _T_683 : 32'h0; // @[Mux.scala 27:72] wire [31:0] i0_immed_d = _T_691 | _T_688; // @[Mux.scala 27:72] wire [31:0] _T_564 = _T_347 ? i0_immed_d : 32'h0; // @[Mux.scala 27:72] - wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 650:44] - wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 651:44] - wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 652:44] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 646:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 647:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 648:44] reg i0_x_c_mul; // @[Reg.scala 15:16] reg i0_x_c_alu; // @[Reg.scala 15:16] reg i0_r_c_mul; // @[Reg.scala 15:16] reg i0_r_c_alu; // @[Reg.scala 15:16] - wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 660:49] - wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 662:50] - reg x_d_bits_i0store; // @[el2_lib.scala 524:16] - reg x_d_bits_i0div; // @[el2_lib.scala 524:16] - reg x_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg [11:0] x_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_733 = x_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 684:47] - wire _T_737 = x_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 685:33] - wire _T_756 = ~r_d_bits_i0div; // @[el2_dec_decode_ctl.scala 700:49] - wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 700:47] - wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 700:70] - wire _T_761 = x_d_bits_i0v & x_d_bits_i0load; // @[el2_dec_decode_ctl.scala 709:47] - wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 715:52] + wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50] + reg x_d_i0store; // @[el2_lib.scala 524:16] + reg x_d_i0div; // @[el2_lib.scala 524:16] + reg x_d_csrwen; // @[el2_lib.scala 524:16] + reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:37] + wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 681:37] + wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 696:49] + wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:65] + wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 705:42] + wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52] wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] - wire _T_799 = x_d_bits_i0div & x_d_valid; // @[el2_dec_decode_ctl.scala 723:45] - wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 723:58] - wire _T_802 = x_d_bits_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 725:77] - wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 725:60] - wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 726:33] - wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 725:94] - wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 727:33] - wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 727:60] - wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 726:62] - wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 731:51] - wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 732:26] - wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 732:24] - wire _T_813 = r_d_bits_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 732:56] - wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 732:39] - wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 732:77] - wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 731:65] - wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 735:55] - wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 737:62] - wire _T_818 = io_dec_div_active & _T_817; // @[el2_dec_decode_ctl.scala 737:60] - wire _T_819 = ~nonblock_div_cancel; // @[el2_dec_decode_ctl.scala 737:81] - wire _T_820 = _T_818 & _T_819; // @[el2_dec_decode_ctl.scala 737:79] - reg _T_821; // @[el2_dec_decode_ctl.scala 739:54] + wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 719:40] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:55] + wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:69] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:57] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:30] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:86] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:30] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:57] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:59] + wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51] + wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26] + wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24] + wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:51] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:72] + wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55] + wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62] + wire _T_818 = io_dec_div_active & _T_817; // @[el2_dec_decode_ctl.scala 733:60] + wire _T_819 = ~nonblock_div_cancel; // @[el2_dec_decode_ctl.scala 733:81] + wire _T_820 = _T_818 & _T_819; // @[el2_dec_decode_ctl.scala 733:79] + reg _T_821; // @[el2_dec_decode_ctl.scala 735:54] reg [4:0] _T_830; // @[Reg.scala 27:20] reg [31:0] i0_inst_x; // @[el2_lib.scala 514:16] reg [31:0] i0_inst_r; // @[el2_lib.scala 514:16] @@ -46934,86 +46966,92 @@ module el2_dec_decode_ctl( reg [31:0] _T_837; // @[el2_lib.scala 514:16] reg [30:0] i0_pc_wb; // @[el2_lib.scala 514:16] reg [30:0] _T_840; // @[el2_lib.scala 514:16] + reg [30:0] dec_i0_pc_r; // @[el2_lib.scala 514:16] + wire [31:0] _T_842 = {io_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_843 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_846 = {{1'd0}, _T_843[12:1]}; // @[el2_lib.scala 208:31] - wire [18:0] _T_852 = 19'h0 - 19'h1; // @[el2_lib.scala 210:27] + wire [12:0] _T_846 = _T_842[12:1] + _T_843[12:1]; // @[el2_lib.scala 208:31] + wire [18:0] _T_849 = _T_842[31:13] + 19'h1; // @[el2_lib.scala 209:27] + wire [18:0] _T_852 = _T_842[31:13] - 19'h1; // @[el2_lib.scala 210:27] wire _T_855 = ~_T_846[12]; // @[el2_lib.scala 212:28] + wire _T_856 = _T_843[12] ^ _T_855; // @[el2_lib.scala 212:26] wire _T_859 = ~_T_843[12]; // @[el2_lib.scala 213:20] wire _T_861 = _T_859 & _T_846[12]; // @[el2_lib.scala 213:26] wire _T_865 = _T_843[12] & _T_855; // @[el2_lib.scala 214:26] - wire [18:0] _T_868 = _T_861 ? 19'h1 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_867 = _T_856 ? _T_842[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_868 = _T_861 ? _T_849 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_869 = _T_865 ? _T_852 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_871 = _T_868 | _T_869; // @[Mux.scala 27:72] + wire [18:0] _T_870 = _T_867 | _T_868; // @[Mux.scala 27:72] + wire [18:0] _T_871 = _T_870 | _T_869; // @[Mux.scala 27:72] wire [31:0] temp_pred_correct_npc_x = {_T_871,_T_846[11:0],1'h0}; // @[Cat.scala 29:58] - wire _T_887_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 778:61] - wire _T_887_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 778:61] - wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_887_mul; // @[el2_dec_decode_ctl.scala 778:24] - wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_887_alu; // @[el2_dec_decode_ctl.scala 778:24] - wire _T_896_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 780:61] - wire _T_896_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 780:61] - wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_896_mul; // @[el2_dec_decode_ctl.scala 780:24] - wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_896_alu; // @[el2_dec_decode_ctl.scala 780:24] - wire _T_909 = io_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 798:62] - wire _T_910 = io_dec_nonblock_load_waddr == i0r_rs1; // @[el2_dec_decode_ctl.scala 798:119] - wire i0_rs1_nonblock_load_bypass_en_d = _T_909 & _T_910; // @[el2_dec_decode_ctl.scala 798:89] - wire _T_911 = io_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 800:62] - wire _T_912 = io_dec_nonblock_load_waddr == i0r_rs2; // @[el2_dec_decode_ctl.scala 800:119] - wire i0_rs2_nonblock_load_bypass_en_d = _T_911 & _T_912; // @[el2_dec_decode_ctl.scala 800:89] - wire _T_914 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[el2_dec_decode_ctl.scala 803:66] - wire _T_915 = i0_rs1_depth_d[0] & _T_914; // @[el2_dec_decode_ctl.scala 803:45] - wire _T_917 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 803:108] - wire _T_920 = _T_914 | i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 803:196] - wire _T_921 = i0_rs1_depth_d[1] & _T_920; // @[el2_dec_decode_ctl.scala 803:153] + wire _T_887_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 774:61] + wire _T_887_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 774:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_887_mul; // @[el2_dec_decode_ctl.scala 774:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_887_alu; // @[el2_dec_decode_ctl.scala 774:24] + wire _T_896_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 776:61] + wire _T_896_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 776:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_896_mul; // @[el2_dec_decode_ctl.scala 776:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_896_alu; // @[el2_dec_decode_ctl.scala 776:24] + wire _T_909 = io_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 794:62] + wire _T_910 = io_dec_nonblock_load_waddr == i0r_rs1; // @[el2_dec_decode_ctl.scala 794:119] + wire i0_rs1_nonblock_load_bypass_en_d = _T_909 & _T_910; // @[el2_dec_decode_ctl.scala 794:89] + wire _T_911 = io_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 796:62] + wire _T_912 = io_dec_nonblock_load_waddr == i0r_rs2; // @[el2_dec_decode_ctl.scala 796:119] + wire i0_rs2_nonblock_load_bypass_en_d = _T_911 & _T_912; // @[el2_dec_decode_ctl.scala 796:89] + wire _T_914 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[el2_dec_decode_ctl.scala 799:66] + wire _T_915 = i0_rs1_depth_d[0] & _T_914; // @[el2_dec_decode_ctl.scala 799:45] + wire _T_917 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 799:108] + wire _T_920 = _T_914 | i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 799:196] + wire _T_921 = i0_rs1_depth_d[1] & _T_920; // @[el2_dec_decode_ctl.scala 799:153] wire [2:0] i0_rs1bypass = {_T_915,_T_917,_T_921}; // @[Cat.scala 29:58] - wire _T_925 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[el2_dec_decode_ctl.scala 805:67] - wire _T_926 = i0_rs2_depth_d[0] & _T_925; // @[el2_dec_decode_ctl.scala 805:45] - wire _T_928 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 805:109] - wire _T_931 = _T_925 | i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 805:196] - wire _T_932 = i0_rs2_depth_d[1] & _T_931; // @[el2_dec_decode_ctl.scala 805:153] + wire _T_925 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[el2_dec_decode_ctl.scala 801:67] + wire _T_926 = i0_rs2_depth_d[0] & _T_925; // @[el2_dec_decode_ctl.scala 801:45] + wire _T_928 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 801:109] + wire _T_931 = _T_925 | i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 801:196] + wire _T_932 = i0_rs2_depth_d[1] & _T_931; // @[el2_dec_decode_ctl.scala 801:153] wire [2:0] i0_rs2bypass = {_T_926,_T_928,_T_932}; // @[Cat.scala 29:58] - wire _T_938 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 807:75] - wire _T_940 = ~i0_rs1bypass[2]; // @[el2_dec_decode_ctl.scala 807:96] - wire _T_941 = _T_940 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 807:113] - wire _T_942 = _T_938 | _T_941; // @[el2_dec_decode_ctl.scala 807:93] - wire _T_947 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 808:75] - wire _T_949 = ~i0_rs2bypass[2]; // @[el2_dec_decode_ctl.scala 808:96] - wire _T_950 = _T_949 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 808:113] - wire _T_951 = _T_947 | _T_950; // @[el2_dec_decode_ctl.scala 808:93] - wire _T_958 = ~i0_rs1bypass[1]; // @[el2_dec_decode_ctl.scala 813:6] - wire _T_960 = ~i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 813:25] - wire _T_961 = _T_958 & _T_960; // @[el2_dec_decode_ctl.scala 813:23] - wire _T_962 = _T_961 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 813:42] + wire _T_938 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 803:75] + wire _T_940 = ~i0_rs1bypass[2]; // @[el2_dec_decode_ctl.scala 803:96] + wire _T_941 = _T_940 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 803:113] + wire _T_942 = _T_938 | _T_941; // @[el2_dec_decode_ctl.scala 803:93] + wire _T_947 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 804:75] + wire _T_949 = ~i0_rs2bypass[2]; // @[el2_dec_decode_ctl.scala 804:96] + wire _T_950 = _T_949 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 804:113] + wire _T_951 = _T_947 | _T_950; // @[el2_dec_decode_ctl.scala 804:93] + wire _T_958 = ~i0_rs1bypass[1]; // @[el2_dec_decode_ctl.scala 810:6] + wire _T_960 = ~i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 810:25] + wire _T_961 = _T_958 & _T_960; // @[el2_dec_decode_ctl.scala 810:23] + wire _T_962 = _T_961 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 810:42] wire [31:0] _T_964 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_965 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_966 = _T_962 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_967 = _T_964 | _T_965; // @[Mux.scala 27:72] - wire _T_975 = ~i0_rs2bypass[1]; // @[el2_dec_decode_ctl.scala 818:6] - wire _T_977 = ~i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 818:25] - wire _T_978 = _T_975 & _T_977; // @[el2_dec_decode_ctl.scala 818:23] - wire _T_979 = _T_978 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 818:42] + wire _T_975 = ~i0_rs2bypass[1]; // @[el2_dec_decode_ctl.scala 815:6] + wire _T_977 = ~i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 815:25] + wire _T_978 = _T_975 & _T_977; // @[el2_dec_decode_ctl.scala 815:23] + wire _T_979 = _T_978 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 815:42] wire [31:0] _T_981 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_982 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_983 = _T_979 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_984 = _T_981 | _T_982; // @[Mux.scala 27:72] - wire _T_987 = i0_dp_raw_load | i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 820:68] - wire _T_988 = io_dec_ib0_valid_d & _T_987; // @[el2_dec_decode_ctl.scala 820:50] - wire _T_989 = ~io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 820:89] - wire _T_990 = _T_988 & _T_989; // @[el2_dec_decode_ctl.scala 820:87] - wire _T_992 = _T_990 & _T_493; // @[el2_dec_decode_ctl.scala 820:112] - wire _T_994 = ~io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 822:6] - wire _T_995 = _T_994 & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 822:27] - wire _T_996 = _T_995 & i0_dp_load; // @[el2_dec_decode_ctl.scala 822:39] - wire _T_1001 = _T_995 & i0_dp_store; // @[el2_dec_decode_ctl.scala 823:39] + wire _T_987 = i0_dp_raw_load | i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 817:68] + wire _T_988 = io_dec_ib0_valid_d & _T_987; // @[el2_dec_decode_ctl.scala 817:50] + wire _T_989 = ~io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 817:89] + wire _T_990 = _T_988 & _T_989; // @[el2_dec_decode_ctl.scala 817:87] + wire _T_992 = _T_990 & _T_493; // @[el2_dec_decode_ctl.scala 817:112] + wire _T_994 = ~io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 819:6] + wire _T_995 = _T_994 & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 819:27] + wire _T_996 = _T_995 & i0_dp_load; // @[el2_dec_decode_ctl.scala 819:39] + wire _T_1001 = _T_995 & i0_dp_store; // @[el2_dec_decode_ctl.scala 820:39] wire [11:0] _T_1005 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] wire [11:0] _T_1006 = _T_996 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_1007 = _T_1001 ? _T_1005 : 12'h0; // @[Mux.scala 27:72] - rvclkhdr data_gated_cgc ( // @[el2_dec_decode_ctl.scala 222:29] - .io_l1clk(data_gated_cgc_io_l1clk), - .io_clk(data_gated_cgc_io_clk), - .io_en(data_gated_cgc_io_en), - .io_scan_mode(data_gated_cgc_io_scan_mode) + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) ); - el2_dec_dec_ctl i0_dec ( // @[el2_dec_decode_ctl.scala 396:22] + el2_dec_dec_ctl i0_dec ( // @[el2_dec_decode_ctl.scala 392:22] .io_ins(i0_dec_io_ins), .io_out_alu(i0_dec_io_out_alu), .io_out_rs1(i0_dec_io_out_rs1), @@ -47022,6 +47060,7 @@ module el2_dec_decode_ctl( .io_out_rd(i0_dec_io_out_rd), .io_out_shimm5(i0_dec_io_out_shimm5), .io_out_imm20(i0_dec_io_out_imm20), + .io_out_pc(i0_dec_io_out_pc), .io_out_load(i0_dec_io_out_load), .io_out_store(i0_dec_io_out_store), .io_out_lsu(i0_dec_io_out_lsu), @@ -47065,12 +47104,6 @@ module el2_dec_decode_ctl( .io_out_pm_alu(i0_dec_io_out_pm_alu), .io_out_legal(i0_dec_io_out_legal) ); - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] - .io_l1clk(rvclkhdr_io_l1clk), - .io_clk(rvclkhdr_io_clk), - .io_en(rvclkhdr_io_en), - .io_scan_mode(rvclkhdr_io_scan_mode) - ); rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), @@ -47089,7 +47122,7 @@ module el2_dec_decode_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 518:23] + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), @@ -47119,7 +47152,7 @@ module el2_dec_decode_ctl( .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 518:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), @@ -47179,130 +47212,134 @@ module el2_dec_decode_ctl( .io_en(rvclkhdr_18_io_en), .io_scan_mode(rvclkhdr_18_io_scan_mode) ); - assign io_dec_extint_stall = _T_339; // @[el2_dec_decode_ctl.scala 436:23] - assign io_dec_i0_inst_wb1 = _T_837; // @[el2_dec_decode_ctl.scala 757:22] - assign io_dec_i0_pc_wb1 = _T_840; // @[el2_dec_decode_ctl.scala 760:20] - assign io_dec_i0_rs1_en_d = i0_dp_rs1 & _T_556; // @[el2_dec_decode_ctl.scala 628:24] - assign io_dec_i0_rs2_en_d = i0_dp_rs2 & _T_558; // @[el2_dec_decode_ctl.scala 629:24] - assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 631:19] - assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 632:19] - assign io_dec_i0_immed_d = _T_563 | _T_564; // @[el2_dec_decode_ctl.scala 637:21] - assign io_dec_i0_br_immed_d = _T_768 ? i0_br_offset : _T_781; // @[el2_dec_decode_ctl.scala 715:24] - assign io_i0_ap_land = _T_40 ? 1'h0 : i0_dp_raw_land; // @[el2_dec_decode_ctl.scala 289:20] - assign io_i0_ap_lor = _T_40 | i0_dp_raw_lor; // @[el2_dec_decode_ctl.scala 290:20] - assign io_i0_ap_lxor = _T_40 ? 1'h0 : i0_dp_raw_lxor; // @[el2_dec_decode_ctl.scala 291:20] - assign io_i0_ap_sll = _T_40 ? 1'h0 : i0_dp_raw_sll; // @[el2_dec_decode_ctl.scala 292:20] - assign io_i0_ap_srl = _T_40 ? 1'h0 : i0_dp_raw_srl; // @[el2_dec_decode_ctl.scala 293:20] - assign io_i0_ap_sra = _T_40 ? 1'h0 : i0_dp_raw_sra; // @[el2_dec_decode_ctl.scala 294:20] - assign io_i0_ap_beq = _T_40 ? 1'h0 : i0_dp_raw_beq; // @[el2_dec_decode_ctl.scala 297:20] - assign io_i0_ap_bne = _T_40 ? 1'h0 : i0_dp_raw_bne; // @[el2_dec_decode_ctl.scala 298:20] - assign io_i0_ap_blt = _T_40 ? 1'h0 : i0_dp_raw_blt; // @[el2_dec_decode_ctl.scala 299:20] - assign io_i0_ap_bge = _T_40 ? 1'h0 : i0_dp_raw_bge; // @[el2_dec_decode_ctl.scala 300:20] - assign io_i0_ap_add = _T_40 ? 1'h0 : i0_dp_raw_add; // @[el2_dec_decode_ctl.scala 287:20] - assign io_i0_ap_sub = _T_40 ? 1'h0 : i0_dp_raw_sub; // @[el2_dec_decode_ctl.scala 288:20] - assign io_i0_ap_slt = _T_40 ? 1'h0 : i0_dp_raw_slt; // @[el2_dec_decode_ctl.scala 295:20] - assign io_i0_ap_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 296:20] - assign io_i0_ap_jal = _T_336 & _T_337; // @[el2_dec_decode_ctl.scala 303:22] - assign io_i0_ap_predict_t = _T_46 & i0_predict_br; // @[el2_dec_decode_ctl.scala 285:26] - assign io_i0_ap_predict_nt = _T_47 & i0_predict_br; // @[el2_dec_decode_ctl.scala 284:26] - assign io_i0_ap_csr_write = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 301:22] - assign io_i0_ap_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 302:22] - assign io_dec_i0_decode_d = _T_490 & _T_467; // @[el2_dec_decode_ctl.scala 556:22 el2_dec_decode_ctl.scala 622:22] - assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 576:26] - assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 810:31] - assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 815:31] - assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[el2_dec_decode_ctl.scala 698:27] - assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 700:32] - assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 701:26] - assign io_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_942}; // @[el2_dec_decode_ctl.scala 807:34] - assign io_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_951}; // @[el2_dec_decode_ctl.scala 808:34] - assign io_lsu_p_valid = io_dec_extint_stall | lsu_decode_d; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 443:24 el2_dec_decode_ctl.scala 445:35] - assign io_lsu_p_bits_fast_int = io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 442:29] - assign io_lsu_p_bits_by = io_dec_extint_stall ? 1'h0 : i0_dp_by; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 448:40] - assign io_lsu_p_bits_half = io_dec_extint_stall ? 1'h0 : i0_dp_half; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 449:40] - assign io_lsu_p_bits_word = io_dec_extint_stall | i0_dp_word; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 441:29 el2_dec_decode_ctl.scala 450:40] - assign io_lsu_p_bits_load = io_dec_extint_stall | i0_dp_load; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 440:29 el2_dec_decode_ctl.scala 446:40] - assign io_lsu_p_bits_store = io_dec_extint_stall ? 1'h0 : i0_dp_store; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 447:40] - assign io_lsu_p_bits_unsign = io_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 454:40] - assign io_lsu_p_bits_store_data_bypass_d = io_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 452:40] - assign io_lsu_p_bits_load_ldst_bypass_d = io_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 451:40] - assign io_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 431:21] - assign io_mul_p_bits_rs1_sign = _T_40 ? 1'h0 : i0_dp_raw_rs1_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 432:26] - assign io_mul_p_bits_rs2_sign = _T_40 ? 1'h0 : i0_dp_raw_rs2_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 433:26] - assign io_mul_p_bits_low = _T_40 ? 1'h0 : i0_dp_raw_low; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 434:26] - assign io_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 427:21] - assign io_div_p_bits_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 428:26] - assign io_div_p_bits_rem = _T_40 ? 1'h0 : i0_dp_raw_rem; // @[el2_dec_decode_ctl.scala 429:26] - assign io_div_waddr_wb = _T_830; // @[el2_dec_decode_ctl.scala 745:19] - assign io_dec_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 734:29] - assign io_dec_lsu_valid_raw_d = _T_992 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 820:26] - assign io_dec_lsu_offset_d = _T_1006 | _T_1007; // @[el2_dec_decode_ctl.scala 821:23] - assign io_dec_csr_ren_d = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 458:21] - assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[el2_dec_decode_ctl.scala 467:24] - assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 533:24] - assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 470:24] - assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 475:20] - assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[el2_dec_decode_ctl.scala 471:23] - assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 518:24] - assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 478:27] - assign io_dec_tlu_i0_valid_r = r_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 582:29] - assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 616:39 el2_dec_decode_ctl.scala 617:39] - assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 616:39] - assign io_dec_tlu_i0_pc_r = 31'h0; // @[el2_dec_decode_ctl.scala 763:27] - assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 540:23] - assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 768:25] - assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 240:38] - assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 238:43] - assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[el2_dec_decode_ctl.scala 239:43] - assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 252:49] - assign io_dec_i0_predict_p_d_bits_br_error = _T_32 & _T_17; // @[el2_dec_decode_ctl.scala 247:56] - assign io_dec_i0_predict_p_d_bits_br_start_error = _T_35 & _T_17; // @[el2_dec_decode_ctl.scala 248:56] - assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[el2_dec_decode_ctl.scala 237:43] - assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 234:43] - assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 236:43] - assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 235:43] - assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[el2_dec_decode_ctl.scala 254:56] - assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 253:32] - assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 249:32] - assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 250:32] - assign io_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[el2_dec_decode_ctl.scala 666:27] - assign io_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[el2_dec_decode_ctl.scala 667:27] - assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 561:28] - assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_498; // @[el2_dec_decode_ctl.scala 562:27] - assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 564:29] - assign io_dec_pmu_postsync_stall = postsync_stall; // @[el2_dec_decode_ctl.scala 563:29] - assign io_dec_nonblock_load_wen = _T_199 & _T_200; // @[el2_dec_decode_ctl.scala 358:28] - assign io_dec_nonblock_load_waddr = _T_245 | _T_237; // @[el2_dec_decode_ctl.scala 355:29 el2_dec_decode_ctl.scala 365:29] - assign io_dec_pause_state = pause_stall; // @[el2_dec_decode_ctl.scala 502:22] - assign io_dec_pause_state_cg = pause_stall & _T_420; // @[el2_dec_decode_ctl.scala 506:25] - assign io_dec_div_active = _T_821; // @[el2_dec_decode_ctl.scala 739:21] - assign data_gated_cgc_io_clk = clock; // @[el2_dec_decode_ctl.scala 225:31] - assign data_gated_cgc_io_en = _T_15 | _T_16; // @[el2_dec_decode_ctl.scala 223:31] - assign data_gated_cgc_io_scan_mode = io_scan_mode; // @[el2_dec_decode_ctl.scala 224:31] - assign i0_dec_io_ins = io_dec_i0_instr_d; // @[el2_dec_decode_ctl.scala 397:16] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_19_io_l1clk), + .io_clk(rvclkhdr_19_io_clk), + .io_en(rvclkhdr_19_io_en), + .io_scan_mode(rvclkhdr_19_io_scan_mode) + ); + assign io_dec_extint_stall = _T_339; // @[el2_dec_decode_ctl.scala 432:23] + assign io_dec_i0_inst_wb1 = _T_837; // @[el2_dec_decode_ctl.scala 753:22] + assign io_dec_i0_pc_wb1 = _T_840; // @[el2_dec_decode_ctl.scala 756:20] + assign io_dec_i0_rs1_en_d = i0_dp_rs1 & _T_556; // @[el2_dec_decode_ctl.scala 624:24] + assign io_dec_i0_rs2_en_d = i0_dp_rs2 & _T_558; // @[el2_dec_decode_ctl.scala 625:24] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 627:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 628:19] + assign io_dec_i0_immed_d = _T_563 | _T_564; // @[el2_dec_decode_ctl.scala 633:21] + assign io_dec_i0_br_immed_d = _T_768 ? i0_br_offset : _T_781; // @[el2_dec_decode_ctl.scala 711:24] + assign io_i0_ap_land = _T_41 ? 1'h0 : i0_dp_raw_land; // @[el2_dec_decode_ctl.scala 285:20] + assign io_i0_ap_lor = _T_41 | i0_dp_raw_lor; // @[el2_dec_decode_ctl.scala 286:20] + assign io_i0_ap_lxor = _T_41 ? 1'h0 : i0_dp_raw_lxor; // @[el2_dec_decode_ctl.scala 287:20] + assign io_i0_ap_sll = _T_41 ? 1'h0 : i0_dp_raw_sll; // @[el2_dec_decode_ctl.scala 288:20] + assign io_i0_ap_srl = _T_41 ? 1'h0 : i0_dp_raw_srl; // @[el2_dec_decode_ctl.scala 289:20] + assign io_i0_ap_sra = _T_41 ? 1'h0 : i0_dp_raw_sra; // @[el2_dec_decode_ctl.scala 290:20] + assign io_i0_ap_beq = _T_41 ? 1'h0 : i0_dp_raw_beq; // @[el2_dec_decode_ctl.scala 293:20] + assign io_i0_ap_bne = _T_41 ? 1'h0 : i0_dp_raw_bne; // @[el2_dec_decode_ctl.scala 294:20] + assign io_i0_ap_blt = _T_41 ? 1'h0 : i0_dp_raw_blt; // @[el2_dec_decode_ctl.scala 295:20] + assign io_i0_ap_bge = _T_41 ? 1'h0 : i0_dp_raw_bge; // @[el2_dec_decode_ctl.scala 296:20] + assign io_i0_ap_add = _T_41 ? 1'h0 : i0_dp_raw_add; // @[el2_dec_decode_ctl.scala 283:20] + assign io_i0_ap_sub = _T_41 ? 1'h0 : i0_dp_raw_sub; // @[el2_dec_decode_ctl.scala 284:20] + assign io_i0_ap_slt = _T_41 ? 1'h0 : i0_dp_raw_slt; // @[el2_dec_decode_ctl.scala 291:20] + assign io_i0_ap_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 292:20] + assign io_i0_ap_jal = _T_336 & _T_337; // @[el2_dec_decode_ctl.scala 299:22] + assign io_i0_ap_predict_t = _T_47 & i0_predict_br; // @[el2_dec_decode_ctl.scala 281:26] + assign io_i0_ap_predict_nt = _T_48 & i0_predict_br; // @[el2_dec_decode_ctl.scala 280:26] + assign io_i0_ap_csr_write = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 297:22] + assign io_i0_ap_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 298:22] + assign io_dec_i0_decode_d = _T_490 & _T_467; // @[el2_dec_decode_ctl.scala 552:22 el2_dec_decode_ctl.scala 618:22] + assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26] + assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31] + assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31] + assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 694:27] + assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32] + assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26] + assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25] + assign io_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_942}; // @[el2_dec_decode_ctl.scala 803:34] + assign io_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_951}; // @[el2_dec_decode_ctl.scala 804:34] + assign io_lsu_p_valid = io_dec_extint_stall | lsu_decode_d; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 439:24 el2_dec_decode_ctl.scala 441:35] + assign io_lsu_p_bits_fast_int = io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 438:29] + assign io_lsu_p_bits_by = io_dec_extint_stall ? 1'h0 : i0_dp_by; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 444:40] + assign io_lsu_p_bits_half = io_dec_extint_stall ? 1'h0 : i0_dp_half; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 445:40] + assign io_lsu_p_bits_word = io_dec_extint_stall | i0_dp_word; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 437:29 el2_dec_decode_ctl.scala 446:40] + assign io_lsu_p_bits_load = io_dec_extint_stall | i0_dp_load; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 436:29 el2_dec_decode_ctl.scala 442:40] + assign io_lsu_p_bits_store = io_dec_extint_stall ? 1'h0 : i0_dp_store; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 443:40] + assign io_lsu_p_bits_unsign = io_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 450:40] + assign io_lsu_p_bits_store_data_bypass_d = io_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 448:40] + assign io_lsu_p_bits_load_ldst_bypass_d = io_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[el2_dec_decode_ctl.scala 434:12 el2_dec_decode_ctl.scala 447:40] + assign io_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 427:21] + assign io_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 428:26] + assign io_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 429:26] + assign io_mul_p_bits_low = _T_41 ? 1'h0 : i0_dp_raw_low; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 430:26] + assign io_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 423:21] + assign io_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 424:26] + assign io_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[el2_dec_decode_ctl.scala 425:26] + assign io_div_waddr_wb = _T_830; // @[el2_dec_decode_ctl.scala 741:19] + assign io_dec_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 730:29] + assign io_dec_lsu_valid_raw_d = _T_992 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 817:26] + assign io_dec_lsu_offset_d = _T_1006 | _T_1007; // @[el2_dec_decode_ctl.scala 818:23] + assign io_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 454:21] + assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[el2_dec_decode_ctl.scala 463:24] + assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24] + assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24] + assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20] + assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] + assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] + assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27] + assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27] + assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23] + assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 764:25] + assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 236:38] + assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 234:43] + assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_hist; // @[el2_dec_decode_ctl.scala 235:43] + assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 248:49] + assign io_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[el2_dec_decode_ctl.scala 243:56] + assign io_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[el2_dec_decode_ctl.scala 244:56] + assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_prett; // @[el2_dec_decode_ctl.scala 233:43] + assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 230:43] + assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 232:43] + assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 231:43] + assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_way; // @[el2_dec_decode_ctl.scala 250:56] + assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 249:32] + assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 245:32] + assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 246:32] + assign io_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[el2_dec_decode_ctl.scala 662:27] + assign io_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[el2_dec_decode_ctl.scala 663:27] + assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 557:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_498; // @[el2_dec_decode_ctl.scala 558:27] + assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 560:29] + assign io_dec_pmu_postsync_stall = postsync_stall; // @[el2_dec_decode_ctl.scala 559:29] + assign io_dec_nonblock_load_wen = _T_200 & _T_201; // @[el2_dec_decode_ctl.scala 354:28] + assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[el2_dec_decode_ctl.scala 351:29 el2_dec_decode_ctl.scala 361:29] + assign io_dec_pause_state = pause_stall; // @[el2_dec_decode_ctl.scala 498:22] + assign io_dec_pause_state_cg = pause_stall & _T_420; // @[el2_dec_decode_ctl.scala 502:25] + assign io_dec_div_active = _T_821; // @[el2_dec_decode_ctl.scala 735:21] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = _T_15 | _T_16; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign i0_dec_io_ins = io_dec_i0_instr_d; // @[el2_dec_decode_ctl.scala 393:16] assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = _T_428 | pause_stall; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = shift_illegal & _T_464; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_en = _T_428 | pause_stall; // @[el2_lib.scala 511:17] assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_4_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = shift_illegal & _T_464; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 520:18] assign rvclkhdr_5_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] @@ -47310,41 +47347,44 @@ module el2_dec_decode_ctl( assign rvclkhdr_6_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_7_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_8_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 521:17] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_9_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_9_io_en = _T_710 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_10_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_10_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = i0_legal_decode_d & i0_dp_div; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_12_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_12_io_en = i0_legal_decode_d & i0_dp_div; // @[el2_lib.scala 511:17] assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_13_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_13_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_14_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_14_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_15_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_15_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_16_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_16_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_17_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_17_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_18_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_18_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_19_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -47395,73 +47435,73 @@ initial begin _RAND_6 = {1{`RANDOM}}; postsync_stall = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - x_d_valid = _RAND_7[0:0]; + x_d_i0valid = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; flush_final_r = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; illegal_lockout = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; - cam_raw_0_bits_tag = _RAND_10[2:0]; + cam_raw_0_tag = _RAND_10[2:0]; _RAND_11 = {1{`RANDOM}}; cam_raw_0_valid = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - cam_raw_1_bits_tag = _RAND_12[2:0]; + cam_raw_1_tag = _RAND_12[2:0]; _RAND_13 = {1{`RANDOM}}; cam_raw_1_valid = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - cam_raw_2_bits_tag = _RAND_14[2:0]; + cam_raw_2_tag = _RAND_14[2:0]; _RAND_15 = {1{`RANDOM}}; cam_raw_2_valid = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - cam_raw_3_bits_tag = _RAND_16[2:0]; + cam_raw_3_tag = _RAND_16[2:0]; _RAND_17 = {1{`RANDOM}}; cam_raw_3_valid = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - x_d_bits_i0load = _RAND_18[0:0]; + x_d_i0load = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - x_d_bits_i0rd = _RAND_19[4:0]; + x_d_i0rd = _RAND_19[4:0]; _RAND_20 = {1{`RANDOM}}; _T_701 = _RAND_20[2:0]; _RAND_21 = {1{`RANDOM}}; nonblock_load_valid_m_delay = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - r_d_bits_i0load = _RAND_22[0:0]; + r_d_i0load = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - r_d_bits_i0v = _RAND_23[0:0]; + r_d_i0v = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - r_d_bits_i0rd = _RAND_24[4:0]; + r_d_i0rd = _RAND_24[4:0]; _RAND_25 = {1{`RANDOM}}; - cam_raw_0_bits_rd = _RAND_25[4:0]; + cam_raw_0_rd = _RAND_25[4:0]; _RAND_26 = {1{`RANDOM}}; - cam_raw_0_bits_wb = _RAND_26[0:0]; + cam_raw_0_wb = _RAND_26[0:0]; _RAND_27 = {1{`RANDOM}}; - cam_raw_1_bits_rd = _RAND_27[4:0]; + cam_raw_1_rd = _RAND_27[4:0]; _RAND_28 = {1{`RANDOM}}; - cam_raw_1_bits_wb = _RAND_28[0:0]; + cam_raw_1_wb = _RAND_28[0:0]; _RAND_29 = {1{`RANDOM}}; - cam_raw_2_bits_rd = _RAND_29[4:0]; + cam_raw_2_rd = _RAND_29[4:0]; _RAND_30 = {1{`RANDOM}}; - cam_raw_2_bits_wb = _RAND_30[0:0]; + cam_raw_2_wb = _RAND_30[0:0]; _RAND_31 = {1{`RANDOM}}; - cam_raw_3_bits_rd = _RAND_31[4:0]; + cam_raw_3_rd = _RAND_31[4:0]; _RAND_32 = {1{`RANDOM}}; - cam_raw_3_bits_wb = _RAND_32[0:0]; + cam_raw_3_wb = _RAND_32[0:0]; _RAND_33 = {1{`RANDOM}}; lsu_idle = _RAND_33[0:0]; _RAND_34 = {1{`RANDOM}}; _T_339 = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - x_d_bits_i0v = _RAND_35[0:0]; + x_d_i0v = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; i0_x_c_load = _RAND_36[0:0]; _RAND_37 = {1{`RANDOM}}; i0_r_c_load = _RAND_37[0:0]; _RAND_38 = {1{`RANDOM}}; - r_d_bits_csrwen = _RAND_38[0:0]; + r_d_csrwen = _RAND_38[0:0]; _RAND_39 = {1{`RANDOM}}; - r_d_valid = _RAND_39[0:0]; + r_d_i0valid = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - r_d_bits_csrwaddr = _RAND_40[11:0]; + r_d_csrwaddr = _RAND_40[11:0]; _RAND_41 = {1{`RANDOM}}; csr_read_x = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; @@ -47477,13 +47517,13 @@ initial begin _RAND_47 = {1{`RANDOM}}; csr_rddata_x = _RAND_47[31:0]; _RAND_48 = {1{`RANDOM}}; - r_d_bits_csrwonly = _RAND_48[0:0]; + r_d_csrwonly = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; i0_result_r_raw = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; - x_d_bits_csrwonly = _RAND_50[0:0]; + x_d_csrwonly = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - wbd_bits_csrwonly = _RAND_51[0:0]; + wbd_csrwonly = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; _T_465 = _RAND_52[31:0]; _RAND_53 = {1{`RANDOM}}; @@ -47523,9 +47563,9 @@ initial begin _RAND_70 = {1{`RANDOM}}; lsu_pmu_misaligned_r = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - r_d_bits_i0store = _RAND_71[0:0]; + r_d_i0store = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - r_d_bits_i0div = _RAND_72[0:0]; + r_d_i0div = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; i0_x_c_mul = _RAND_73[0:0]; _RAND_74 = {1{`RANDOM}}; @@ -47535,13 +47575,13 @@ initial begin _RAND_76 = {1{`RANDOM}}; i0_r_c_alu = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - x_d_bits_i0store = _RAND_77[0:0]; + x_d_i0store = _RAND_77[0:0]; _RAND_78 = {1{`RANDOM}}; - x_d_bits_i0div = _RAND_78[0:0]; + x_d_i0div = _RAND_78[0:0]; _RAND_79 = {1{`RANDOM}}; - x_d_bits_csrwen = _RAND_79[0:0]; + x_d_csrwen = _RAND_79[0:0]; _RAND_80 = {1{`RANDOM}}; - x_d_bits_csrwaddr = _RAND_80[11:0]; + x_d_csrwaddr = _RAND_80[11:0]; _RAND_81 = {1{`RANDOM}}; last_br_immed_x = _RAND_81[11:0]; _RAND_82 = {1{`RANDOM}}; @@ -47560,6 +47600,8 @@ initial begin i0_pc_wb = _RAND_88[30:0]; _RAND_89 = {1{`RANDOM}}; _T_840 = _RAND_89[30:0]; + _RAND_90 = {1{`RANDOM}}; + dec_i0_pc_r = _RAND_90[30:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin tlu_wr_pause_r1 = 1'h0; @@ -47583,7 +47625,7 @@ initial begin postsync_stall = 1'h0; end if (reset) begin - x_d_valid = 1'h0; + x_d_i0valid = 1'h0; end if (reset) begin flush_final_r = 1'h0; @@ -47592,34 +47634,34 @@ initial begin illegal_lockout = 1'h0; end if (reset) begin - cam_raw_0_bits_tag = 3'h0; + cam_raw_0_tag = 3'h0; end if (reset) begin cam_raw_0_valid = 1'h0; end if (reset) begin - cam_raw_1_bits_tag = 3'h0; + cam_raw_1_tag = 3'h0; end if (reset) begin cam_raw_1_valid = 1'h0; end if (reset) begin - cam_raw_2_bits_tag = 3'h0; + cam_raw_2_tag = 3'h0; end if (reset) begin cam_raw_2_valid = 1'h0; end if (reset) begin - cam_raw_3_bits_tag = 3'h0; + cam_raw_3_tag = 3'h0; end if (reset) begin cam_raw_3_valid = 1'h0; end if (reset) begin - x_d_bits_i0load = 1'h0; + x_d_i0load = 1'h0; end if (reset) begin - x_d_bits_i0rd = 5'h0; + x_d_i0rd = 5'h0; end if (reset) begin _T_701 = 3'h0; @@ -47628,37 +47670,37 @@ initial begin nonblock_load_valid_m_delay = 1'h0; end if (reset) begin - r_d_bits_i0load = 1'h0; + r_d_i0load = 1'h0; end if (reset) begin - r_d_bits_i0v = 1'h0; + r_d_i0v = 1'h0; end if (reset) begin - r_d_bits_i0rd = 5'h0; + r_d_i0rd = 5'h0; end if (reset) begin - cam_raw_0_bits_rd = 5'h0; + cam_raw_0_rd = 5'h0; end if (reset) begin - cam_raw_0_bits_wb = 1'h0; + cam_raw_0_wb = 1'h0; end if (reset) begin - cam_raw_1_bits_rd = 5'h0; + cam_raw_1_rd = 5'h0; end if (reset) begin - cam_raw_1_bits_wb = 1'h0; + cam_raw_1_wb = 1'h0; end if (reset) begin - cam_raw_2_bits_rd = 5'h0; + cam_raw_2_rd = 5'h0; end if (reset) begin - cam_raw_2_bits_wb = 1'h0; + cam_raw_2_wb = 1'h0; end if (reset) begin - cam_raw_3_bits_rd = 5'h0; + cam_raw_3_rd = 5'h0; end if (reset) begin - cam_raw_3_bits_wb = 1'h0; + cam_raw_3_wb = 1'h0; end if (reset) begin lsu_idle = 1'h0; @@ -47667,16 +47709,16 @@ initial begin _T_339 = 1'h0; end if (reset) begin - x_d_bits_i0v = 1'h0; + x_d_i0v = 1'h0; end if (reset) begin - r_d_bits_csrwen = 1'h0; + r_d_csrwen = 1'h0; end if (reset) begin - r_d_valid = 1'h0; + r_d_i0valid = 1'h0; end if (reset) begin - r_d_bits_csrwaddr = 12'h0; + r_d_csrwaddr = 12'h0; end if (reset) begin csr_read_x = 1'h0; @@ -47700,16 +47742,16 @@ initial begin csr_rddata_x = 32'h0; end if (reset) begin - r_d_bits_csrwonly = 1'h0; + r_d_csrwonly = 1'h0; end if (reset) begin i0_result_r_raw = 32'h0; end if (reset) begin - x_d_bits_csrwonly = 1'h0; + x_d_csrwonly = 1'h0; end if (reset) begin - wbd_bits_csrwonly = 1'h0; + wbd_csrwonly = 1'h0; end if (reset) begin _T_465 = 32'h0; @@ -47769,22 +47811,22 @@ initial begin lsu_pmu_misaligned_r = 1'h0; end if (reset) begin - r_d_bits_i0store = 1'h0; + r_d_i0store = 1'h0; end if (reset) begin - r_d_bits_i0div = 1'h0; + r_d_i0div = 1'h0; end if (reset) begin - x_d_bits_i0store = 1'h0; + x_d_i0store = 1'h0; end if (reset) begin - x_d_bits_i0div = 1'h0; + x_d_i0div = 1'h0; end if (reset) begin - x_d_bits_csrwen = 1'h0; + x_d_csrwen = 1'h0; end if (reset) begin - x_d_bits_csrwaddr = 12'h0; + x_d_csrwaddr = 12'h0; end if (reset) begin last_br_immed_x = 12'h0; @@ -47813,6 +47855,9 @@ initial begin if (reset) begin _T_840 = 31'h0; end + if (reset) begin + dec_i0_pc_r = 31'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -47839,42 +47884,42 @@ end // initial i0_r_c_alu <= i0_x_c_alu; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin tlu_wr_pause_r1 <= 1'h0; end else begin tlu_wr_pause_r1 <= io_dec_tlu_wr_pause_r; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin tlu_wr_pause_r2 <= 1'h0; end else begin tlu_wr_pause_r2 <= tlu_wr_pause_r1; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin leak1_i1_stall <= 1'h0; end else begin - leak1_i1_stall <= io_dec_tlu_flush_leak_one_r | _T_280; + leak1_i1_stall <= io_dec_tlu_flush_leak_one_r | _T_281; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin leak1_i0_stall <= 1'h0; end else begin - leak1_i0_stall <= _T_283 | _T_285; + leak1_i0_stall <= _T_284 | _T_286; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin pause_stall <= 1'h0; end else begin pause_stall <= _T_412 & _T_413; end end - always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin write_csr_data <= 32'h0; end else if (pause_stall) begin @@ -47885,28 +47930,28 @@ end // initial write_csr_data <= write_csr_data_x; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin postsync_stall <= 1'h0; end else begin postsync_stall <= _T_506 | _T_507; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_valid <= 1'h0; + x_d_i0valid <= 1'h0; end else begin - x_d_valid <= io_dec_i0_decode_d; + x_d_i0valid <= io_dec_i0_decode_d; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin flush_final_r <= 1'h0; end else begin flush_final_r <= io_exu_flush_final; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin illegal_lockout <= 1'h0; end else begin @@ -47915,11 +47960,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_bits_tag <= 3'h0; + cam_raw_0_tag <= 3'h0; end else if (cam_wen[0]) begin - cam_raw_0_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; - end else if (_T_106) begin - cam_raw_0_bits_tag <= 3'h0; + cam_raw_0_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_107) begin + cam_raw_0_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -47933,11 +47978,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_bits_tag <= 3'h0; + cam_raw_1_tag <= 3'h0; end else if (cam_wen[1]) begin - cam_raw_1_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; - end else if (_T_132) begin - cam_raw_1_bits_tag <= 3'h0; + cam_raw_1_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_133) begin + cam_raw_1_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -47951,11 +47996,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_bits_tag <= 3'h0; + cam_raw_2_tag <= 3'h0; end else if (cam_wen[2]) begin - cam_raw_2_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; - end else if (_T_158) begin - cam_raw_2_bits_tag <= 3'h0; + cam_raw_2_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_159) begin + cam_raw_2_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -47969,11 +48014,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_bits_tag <= 3'h0; + cam_raw_3_tag <= 3'h0; end else if (cam_wen[3]) begin - cam_raw_3_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; - end else if (_T_184) begin - cam_raw_3_bits_tag <= 3'h0; + cam_raw_3_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_185) begin + cam_raw_3_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -47985,18 +48030,18 @@ end // initial cam_raw_3_valid <= _GEN_89; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0load <= 1'h0; + x_d_i0load <= 1'h0; end else begin - x_d_bits_i0load <= i0_dp_load & i0_legal_decode_d; + x_d_i0load <= i0_dp_load & i0_legal_decode_d; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0rd <= 5'h0; + x_d_i0rd <= 5'h0; end else begin - x_d_bits_i0rd <= io_dec_i0_instr_d[11:7]; + x_d_i0rd <= io_dec_i0_instr_d[11:7]; end end always @(posedge io_active_clk or posedge reset) begin @@ -48013,105 +48058,105 @@ end // initial nonblock_load_valid_m_delay <= io_lsu_nonblock_load_valid_m; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0load <= 1'h0; + r_d_i0load <= 1'h0; end else begin - r_d_bits_i0load <= x_d_bits_i0load; + r_d_i0load <= x_d_i0load; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0v <= 1'h0; + r_d_i0v <= 1'h0; end else begin - r_d_bits_i0v <= _T_733 & _T_279; + r_d_i0v <= _T_733 & _T_280; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0rd <= 5'h0; + r_d_i0rd <= 5'h0; end else begin - r_d_bits_i0rd <= x_d_bits_i0rd; + r_d_i0rd <= x_d_i0rd; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_bits_rd <= 5'h0; + cam_raw_0_rd <= 5'h0; end else if (cam_wen[0]) begin - if (x_d_bits_i0load) begin - cam_raw_0_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_0_rd <= x_d_i0rd; end else begin - cam_raw_0_bits_rd <= 5'h0; + cam_raw_0_rd <= 5'h0; end - end else if (_T_106) begin - cam_raw_0_bits_rd <= 5'h0; + end else if (_T_107) begin + cam_raw_0_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_bits_wb <= 1'h0; + cam_raw_0_wb <= 1'h0; end else begin - cam_raw_0_bits_wb <= _T_111 | _GEN_57; + cam_raw_0_wb <= _T_112 | _GEN_57; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_bits_rd <= 5'h0; + cam_raw_1_rd <= 5'h0; end else if (cam_wen[1]) begin - if (x_d_bits_i0load) begin - cam_raw_1_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_1_rd <= x_d_i0rd; end else begin - cam_raw_1_bits_rd <= 5'h0; + cam_raw_1_rd <= 5'h0; end - end else if (_T_132) begin - cam_raw_1_bits_rd <= 5'h0; + end else if (_T_133) begin + cam_raw_1_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_bits_wb <= 1'h0; + cam_raw_1_wb <= 1'h0; end else begin - cam_raw_1_bits_wb <= _T_137 | _GEN_68; + cam_raw_1_wb <= _T_138 | _GEN_68; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_bits_rd <= 5'h0; + cam_raw_2_rd <= 5'h0; end else if (cam_wen[2]) begin - if (x_d_bits_i0load) begin - cam_raw_2_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_2_rd <= x_d_i0rd; end else begin - cam_raw_2_bits_rd <= 5'h0; + cam_raw_2_rd <= 5'h0; end - end else if (_T_158) begin - cam_raw_2_bits_rd <= 5'h0; + end else if (_T_159) begin + cam_raw_2_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_bits_wb <= 1'h0; + cam_raw_2_wb <= 1'h0; end else begin - cam_raw_2_bits_wb <= _T_163 | _GEN_79; + cam_raw_2_wb <= _T_164 | _GEN_79; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_bits_rd <= 5'h0; + cam_raw_3_rd <= 5'h0; end else if (cam_wen[3]) begin - if (x_d_bits_i0load) begin - cam_raw_3_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_3_rd <= x_d_i0rd; end else begin - cam_raw_3_bits_rd <= 5'h0; + cam_raw_3_rd <= 5'h0; end - end else if (_T_184) begin - cam_raw_3_bits_rd <= 5'h0; + end else if (_T_185) begin + cam_raw_3_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_bits_wb <= 1'h0; + cam_raw_3_wb <= 1'h0; end else begin - cam_raw_3_bits_wb <= _T_189 | _GEN_90; + cam_raw_3_wb <= _T_190 | _GEN_90; end end always @(posedge io_active_clk or posedge reset) begin @@ -48121,39 +48166,39 @@ end // initial lsu_idle <= io_lsu_idle_any; end end - always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin _T_339 <= 1'h0; end else begin _T_339 <= io_dec_tlu_flush_extint; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin - if (reset) begin - x_d_bits_i0v <= 1'h0; - end else begin - x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d; - end - end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwen <= 1'h0; + x_d_i0v <= 1'h0; end else begin - r_d_bits_csrwen <= x_d_bits_csrwen; + x_d_i0v <= i0_rd_en_d & i0_legal_decode_d; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_valid <= 1'h0; + r_d_csrwen <= 1'h0; end else begin - r_d_valid <= _T_737 & _T_279; + r_d_csrwen <= x_d_csrwen; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwaddr <= 12'h0; + r_d_i0valid <= 1'h0; end else begin - r_d_bits_csrwaddr <= x_d_bits_csrwaddr; + r_d_i0valid <= _T_737 & _T_280; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + r_d_csrwaddr <= 12'h0; + end else begin + r_d_csrwaddr <= x_d_csrwaddr; end end always @(posedge io_active_clk or posedge reset) begin @@ -48187,34 +48232,34 @@ end // initial always @(posedge io_active_clk or posedge reset) begin if (reset) begin csr_imm_x <= 1'h0; - end else if (_T_40) begin + end else if (_T_41) begin csr_imm_x <= 1'h0; end else begin csr_imm_x <= i0_dp_raw_csr_imm; end end - always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin csrimm_x <= 5'h0; end else begin csrimm_x <= io_dec_i0_instr_d[19:15]; end end - always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin csr_rddata_x <= 32'h0; end else begin csr_rddata_x <= io_dec_csr_rddata_d; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwonly <= 1'h0; + r_d_csrwonly <= 1'h0; end else begin - r_d_bits_csrwonly <= x_d_bits_csrwonly; + r_d_csrwonly <= x_d_csrwonly; end end - always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin i0_result_r_raw <= 32'h0; end else if (_T_761) begin @@ -48223,21 +48268,21 @@ end // initial i0_result_r_raw <= io_exu_i0_result_x; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwonly <= 1'h0; + x_d_csrwonly <= 1'h0; end else begin - x_d_bits_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; + x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; end end - always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin - wbd_bits_csrwonly <= 1'h0; + wbd_csrwonly <= 1'h0; end else begin - wbd_bits_csrwonly <= r_d_bits_csrwonly; + wbd_csrwonly <= r_d_csrwonly; end end - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin if (reset) begin _T_465 <= 32'h0; end else if (io_dec_i0_pc4_d) begin @@ -48246,112 +48291,112 @@ end // initial _T_465 <= _T_462; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_legal <= 1'h0; end else begin x_t_legal <= io_dec_i0_decode_d & i0_legal; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_icaf <= 1'h0; end else begin x_t_icaf <= i0_icaf_d & i0_legal_decode_d; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_icaf_f1 <= 1'h0; end else begin x_t_icaf_f1 <= io_dec_i0_icaf_f1_d & i0_legal_decode_d; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_icaf_type <= 2'h0; end else begin x_t_icaf_type <= io_dec_i0_icaf_type_d; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_fence_i <= 1'h0; end else begin x_t_fence_i <= _T_517 & i0_legal_decode_d; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_i0trigger <= 4'h0; end else begin x_t_i0trigger <= io_dec_i0_trigger_match_d & _T_522; end end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin x_t_pmu_i0_itype <= 4'h0; end else begin - x_t_pmu_i0_itype <= _T_254 & _T_276; - end - end - always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin - if (reset) begin - x_t_pmu_i0_br_unpred <= 1'h0; - end else begin - x_t_pmu_i0_br_unpred <= i0_dp_jal & _T_252; + x_t_pmu_i0_itype <= _T_255 & _T_277; end end always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + x_t_pmu_i0_br_unpred <= 1'h0; + end else begin + x_t_pmu_i0_br_unpred <= i0_dp_jal & _T_253; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_legal <= 1'h0; end else begin r_t_legal <= x_t_legal; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_icaf <= 1'h0; end else begin r_t_icaf <= x_t_icaf; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_icaf_f1 <= 1'h0; end else begin r_t_icaf_f1 <= x_t_icaf_f1; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_icaf_type <= 2'h0; end else begin r_t_icaf_type <= x_t_icaf_type; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_fence_i <= 1'h0; end else begin r_t_fence_i <= x_t_fence_i; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_i0trigger <= 4'h0; end else begin r_t_i0trigger <= x_t_i0trigger & _T_531; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_pmu_i0_itype <= 4'h0; end else begin r_t_pmu_i0_itype <= x_t_pmu_i0_itype; end end - always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin r_t_pmu_i0_br_unpred <= 1'h0; end else begin @@ -48372,55 +48417,55 @@ end // initial lsu_pmu_misaligned_r <= io_lsu_pmu_misaligned_m; end end - always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0store <= 1'h0; + r_d_i0store <= 1'h0; end else begin - r_d_bits_i0store <= x_d_bits_i0store; + r_d_i0store <= x_d_i0store; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0div <= 1'h0; + end else begin + r_d_i0div <= x_d_i0div; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0div <= 1'h0; + x_d_i0store <= 1'h0; end else begin - r_d_bits_i0div <= x_d_bits_i0div; + x_d_i0store <= i0_dp_store & i0_legal_decode_d; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0store <= 1'h0; + x_d_i0div <= 1'h0; end else begin - x_d_bits_i0store <= i0_dp_store & i0_legal_decode_d; + x_d_i0div <= i0_dp_div & i0_legal_decode_d; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0div <= 1'h0; + x_d_csrwen <= 1'h0; end else begin - x_d_bits_i0div <= i0_dp_div & i0_legal_decode_d; + x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwen <= 1'h0; + x_d_csrwaddr <= 12'h0; end else begin - x_d_bits_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; + x_d_csrwaddr <= io_dec_i0_instr_d[31:20]; end end - always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin - if (reset) begin - x_d_bits_csrwaddr <= 12'h0; - end else begin - x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20]; - end - end - always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin if (reset) begin last_br_immed_x <= 12'h0; end else if (io_i0_ap_predict_nt) begin last_br_immed_x <= _T_781; end else if (_T_314) begin - last_br_immed_x <= i0_pcall_imm[12:1]; + last_br_immed_x <= i0_pcall_imm[11:0]; end else begin last_br_immed_x <= _T_323; end @@ -48439,7 +48484,7 @@ end // initial _T_830 <= i0r_rd; end end - always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin i0_inst_x <= 32'h0; end else if (io_dec_i0_pc4_d) begin @@ -48448,41 +48493,48 @@ end // initial i0_inst_x <= _T_462; end end - always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin if (reset) begin i0_inst_r <= 32'h0; end else begin i0_inst_r <= i0_inst_x; end end - always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin if (reset) begin i0_inst_wb <= 32'h0; end else begin i0_inst_wb <= i0_inst_r; end end - always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin if (reset) begin _T_837 <= 32'h0; end else begin _T_837 <= i0_inst_wb; end end - always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin i0_pc_wb <= 31'h0; end else begin i0_pc_wb <= io_dec_tlu_i0_pc_r; end end - always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin _T_840 <= 31'h0; end else begin _T_840 <= i0_pc_wb; end end + always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin + if (reset) begin + dec_i0_pc_r <= 31'h0; + end else begin + dec_i0_pc_r <= io_exu_i0_pc_x; + end + end endmodule module el2_dec_gpr_ctl( input clock, @@ -48659,423 +48711,423 @@ module el2_dec_gpr_ctl( wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23] wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23] - wire _T_95 = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_1 = io_wen0 & _T_95; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_112 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_2 = io_wen0 & _T_112; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_129 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_3 = io_wen0 & _T_129; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_146 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_4 = io_wen0 & _T_146; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_163 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_5 = io_wen0 & _T_163; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_180 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_6 = io_wen0 & _T_180; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_197 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_7 = io_wen0 & _T_197; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_214 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_8 = io_wen0 & _T_214; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_231 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_9 = io_wen0 & _T_231; // @[el2_dec_gpr_ctl.scala 26:28] - wire [9:0] _T_8 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] - wire _T_248 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_10 = io_wen0 & _T_248; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_265 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_11 = io_wen0 & _T_265; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_282 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_12 = io_wen0 & _T_282; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_299 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_13 = io_wen0 & _T_299; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_316 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_14 = io_wen0 & _T_316; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_333 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_15 = io_wen0 & _T_333; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_350 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_16 = io_wen0 & _T_350; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_367 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_17 = io_wen0 & _T_367; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_384 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_18 = io_wen0 & _T_384; // @[el2_dec_gpr_ctl.scala 26:28] - wire [18:0] _T_17 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_8}; // @[Cat.scala 29:58] - wire _T_401 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_19 = io_wen0 & _T_401; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_418 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_20 = io_wen0 & _T_418; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_435 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_21 = io_wen0 & _T_435; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_452 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_22 = io_wen0 & _T_452; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_469 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_23 = io_wen0 & _T_469; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_486 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_24 = io_wen0 & _T_486; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_503 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_25 = io_wen0 & _T_503; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_520 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_26 = io_wen0 & _T_520; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_537 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_27 = io_wen0 & _T_537; // @[el2_dec_gpr_ctl.scala 26:28] - wire [27:0] _T_26 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_17}; // @[Cat.scala 29:58] - wire _T_554 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_28 = io_wen0 & _T_554; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_571 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_29 = io_wen0 & _T_571; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_588 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_30 = io_wen0 & _T_588; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_605 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_31 = io_wen0 & _T_605; // @[el2_dec_gpr_ctl.scala 26:28] - wire [31:0] _T_30 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_26}; // @[Cat.scala 29:58] - wire _T_97 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_1 = io_wen1 & _T_97; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_114 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_2 = io_wen1 & _T_114; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_131 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_3 = io_wen1 & _T_131; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_148 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_4 = io_wen1 & _T_148; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_165 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_5 = io_wen1 & _T_165; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_182 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_6 = io_wen1 & _T_182; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_199 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_7 = io_wen1 & _T_199; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_216 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_8 = io_wen1 & _T_216; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_233 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_9 = io_wen1 & _T_233; // @[el2_dec_gpr_ctl.scala 27:28] - wire [9:0] _T_39 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] - wire _T_250 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_10 = io_wen1 & _T_250; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_267 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_11 = io_wen1 & _T_267; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_284 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_12 = io_wen1 & _T_284; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_301 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_13 = io_wen1 & _T_301; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_318 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_14 = io_wen1 & _T_318; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_335 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_15 = io_wen1 & _T_335; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_352 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_16 = io_wen1 & _T_352; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_369 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_17 = io_wen1 & _T_369; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_386 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_18 = io_wen1 & _T_386; // @[el2_dec_gpr_ctl.scala 27:28] - wire [18:0] _T_48 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_39}; // @[Cat.scala 29:58] - wire _T_403 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_19 = io_wen1 & _T_403; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_420 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_20 = io_wen1 & _T_420; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_437 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_21 = io_wen1 & _T_437; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_454 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_22 = io_wen1 & _T_454; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_471 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_23 = io_wen1 & _T_471; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_488 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_24 = io_wen1 & _T_488; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_505 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_25 = io_wen1 & _T_505; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_522 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_26 = io_wen1 & _T_522; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_539 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_27 = io_wen1 & _T_539; // @[el2_dec_gpr_ctl.scala 27:28] - wire [27:0] _T_57 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_48}; // @[Cat.scala 29:58] - wire _T_556 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_28 = io_wen1 & _T_556; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_573 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_29 = io_wen1 & _T_573; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_590 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_30 = io_wen1 & _T_590; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_607 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_31 = io_wen1 & _T_607; // @[el2_dec_gpr_ctl.scala 27:28] - wire [31:0] _T_61 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_57}; // @[Cat.scala 29:58] - wire [31:0] _T_62 = _T_30 | _T_61; // @[el2_dec_gpr_ctl.scala 23:51] - wire _T_99 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_1 = io_wen2 & _T_99; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_116 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_2 = io_wen2 & _T_116; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_133 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_3 = io_wen2 & _T_133; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_150 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_4 = io_wen2 & _T_150; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_167 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_5 = io_wen2 & _T_167; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_184 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_6 = io_wen2 & _T_184; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_201 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_7 = io_wen2 & _T_201; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_218 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_8 = io_wen2 & _T_218; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_235 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_9 = io_wen2 & _T_235; // @[el2_dec_gpr_ctl.scala 28:28] - wire [9:0] _T_71 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] - wire _T_252 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_10 = io_wen2 & _T_252; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_269 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_11 = io_wen2 & _T_269; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_286 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_12 = io_wen2 & _T_286; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_303 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_13 = io_wen2 & _T_303; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_320 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_14 = io_wen2 & _T_320; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_337 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_15 = io_wen2 & _T_337; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_354 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_16 = io_wen2 & _T_354; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_371 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_17 = io_wen2 & _T_371; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_388 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_18 = io_wen2 & _T_388; // @[el2_dec_gpr_ctl.scala 28:28] - wire [18:0] _T_80 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_71}; // @[Cat.scala 29:58] - wire _T_405 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_19 = io_wen2 & _T_405; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_422 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_20 = io_wen2 & _T_422; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_439 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_21 = io_wen2 & _T_439; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_456 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_22 = io_wen2 & _T_456; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_473 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_23 = io_wen2 & _T_473; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_490 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_24 = io_wen2 & _T_490; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_507 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_25 = io_wen2 & _T_507; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_524 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_26 = io_wen2 & _T_524; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_541 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_27 = io_wen2 & _T_541; // @[el2_dec_gpr_ctl.scala 28:28] - wire [27:0] _T_89 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_80}; // @[Cat.scala 29:58] - wire _T_558 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_28 = io_wen2 & _T_558; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_575 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_29 = io_wen2 & _T_575; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_592 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_30 = io_wen2 & _T_592; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_609 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_31 = io_wen2 & _T_609; // @[el2_dec_gpr_ctl.scala 28:28] - wire [31:0] _T_93 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_89}; // @[Cat.scala 29:58] - wire [31:0] gpr_wr_en = _T_62 | _T_93; // @[el2_dec_gpr_ctl.scala 23:89] - wire [31:0] _T_102 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_103 = _T_102 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_105 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_106 = _T_105 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_107 = _T_103 | _T_106; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_109 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_110 = _T_109 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_119 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_120 = _T_119 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_122 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_123 = _T_122 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_124 = _T_120 | _T_123; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_126 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_127 = _T_126 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_136 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_137 = _T_136 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_139 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_140 = _T_139 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_141 = _T_137 | _T_140; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_143 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_144 = _T_143 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_153 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_154 = _T_153 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_156 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_157 = _T_156 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_158 = _T_154 | _T_157; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_160 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_161 = _T_160 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_170 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_171 = _T_170 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_173 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_174 = _T_173 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_175 = _T_171 | _T_174; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_177 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_178 = _T_177 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_187 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_188 = _T_187 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_190 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_191 = _T_190 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_192 = _T_188 | _T_191; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_194 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_195 = _T_194 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_204 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_205 = _T_204 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_207 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_208 = _T_207 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_209 = _T_205 | _T_208; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_211 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_212 = _T_211 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_221 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_222 = _T_221 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_224 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_225 = _T_224 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_226 = _T_222 | _T_225; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_228 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_229 = _T_228 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_238 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_239 = _T_238 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_241 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_242 = _T_241 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_243 = _T_239 | _T_242; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_245 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_246 = _T_245 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_255 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_256 = _T_255 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_258 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_259 = _T_258 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_260 = _T_256 | _T_259; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_262 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_263 = _T_262 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_272 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_273 = _T_272 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_275 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_276 = _T_275 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_277 = _T_273 | _T_276; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_279 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_280 = _T_279 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_289 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_290 = _T_289 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_292 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_293 = _T_292 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_294 = _T_290 | _T_293; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_296 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_297 = _T_296 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_306 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_307 = _T_306 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_309 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_310 = _T_309 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_311 = _T_307 | _T_310; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_313 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_314 = _T_313 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_323 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_324 = _T_323 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_326 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_327 = _T_326 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_328 = _T_324 | _T_327; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_330 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_331 = _T_330 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_340 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_341 = _T_340 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_343 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_344 = _T_343 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_345 = _T_341 | _T_344; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_347 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_348 = _T_347 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_357 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_358 = _T_357 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_360 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_361 = _T_360 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_362 = _T_358 | _T_361; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_364 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_365 = _T_364 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_374 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_375 = _T_374 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_377 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_378 = _T_377 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_379 = _T_375 | _T_378; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_381 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_382 = _T_381 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_391 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_392 = _T_391 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_394 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_395 = _T_394 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_396 = _T_392 | _T_395; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_398 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_399 = _T_398 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_408 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_409 = _T_408 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_411 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_412 = _T_411 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_413 = _T_409 | _T_412; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_415 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_416 = _T_415 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_425 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_426 = _T_425 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_428 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_429 = _T_428 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_430 = _T_426 | _T_429; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_432 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_433 = _T_432 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_442 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_443 = _T_442 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_445 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_446 = _T_445 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_447 = _T_443 | _T_446; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_449 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_450 = _T_449 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_459 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_460 = _T_459 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_462 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_463 = _T_462 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_464 = _T_460 | _T_463; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_466 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_467 = _T_466 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_476 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_477 = _T_476 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_479 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_480 = _T_479 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_481 = _T_477 | _T_480; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_483 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_484 = _T_483 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_493 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_494 = _T_493 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_496 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_497 = _T_496 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_498 = _T_494 | _T_497; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_500 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_501 = _T_500 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_510 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_511 = _T_510 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_513 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_514 = _T_513 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_515 = _T_511 | _T_514; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_517 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_518 = _T_517 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_527 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_528 = _T_527 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_530 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_531 = _T_530 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_532 = _T_528 | _T_531; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_534 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_535 = _T_534 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_544 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_545 = _T_544 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_547 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_548 = _T_547 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_549 = _T_545 | _T_548; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_551 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_552 = _T_551 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_561 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_562 = _T_561 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_564 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_565 = _T_564 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_566 = _T_562 | _T_565; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_568 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_569 = _T_568 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_578 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_579 = _T_578 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_581 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_582 = _T_581 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_583 = _T_579 | _T_582; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_585 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_586 = _T_585 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_595 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_596 = _T_595 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_598 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_599 = _T_598 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_600 = _T_596 | _T_599; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_602 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_603 = _T_602 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_612 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_613 = _T_612 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_615 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_616 = _T_615 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_617 = _T_613 | _T_616; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_619 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_620 = _T_619 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire _T = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_1 = io_wen0 & _T; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_2 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_1 = io_wen1 & _T_2; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_4 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_1 = io_wen2 & _T_4; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_7 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_8 = _T_7 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_10 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_11 = _T_10 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_12 = _T_8 | _T_11; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_14 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_15 = _T_14 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_17 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_2 = io_wen0 & _T_17; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_19 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_2 = io_wen1 & _T_19; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_21 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_2 = io_wen2 & _T_21; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_24 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_25 = _T_24 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_27 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_28 = _T_27 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_29 = _T_25 | _T_28; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_31 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_32 = _T_31 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_34 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_3 = io_wen0 & _T_34; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_36 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_3 = io_wen1 & _T_36; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_38 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_3 = io_wen2 & _T_38; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_41 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_42 = _T_41 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_44 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_45 = _T_44 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_46 = _T_42 | _T_45; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_48 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_49 = _T_48 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_51 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_4 = io_wen0 & _T_51; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_53 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_4 = io_wen1 & _T_53; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_55 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_4 = io_wen2 & _T_55; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_58 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_59 = _T_58 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_61 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_62 = _T_61 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_63 = _T_59 | _T_62; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_65 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_66 = _T_65 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_68 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_5 = io_wen0 & _T_68; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_70 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_5 = io_wen1 & _T_70; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_72 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_5 = io_wen2 & _T_72; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_75 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_76 = _T_75 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_78 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_79 = _T_78 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_80 = _T_76 | _T_79; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_82 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_83 = _T_82 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_85 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_6 = io_wen0 & _T_85; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_87 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_6 = io_wen1 & _T_87; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_89 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_6 = io_wen2 & _T_89; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_92 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_93 = _T_92 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_95 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_96 = _T_95 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_97 = _T_93 | _T_96; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_99 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_100 = _T_99 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_102 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_7 = io_wen0 & _T_102; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_104 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_7 = io_wen1 & _T_104; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_106 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_7 = io_wen2 & _T_106; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_109 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_110 = _T_109 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_112 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_113 = _T_112 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_114 = _T_110 | _T_113; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_116 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_117 = _T_116 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_119 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_8 = io_wen0 & _T_119; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_121 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_8 = io_wen1 & _T_121; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_123 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_8 = io_wen2 & _T_123; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_126 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_127 = _T_126 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_129 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_130 = _T_129 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_131 = _T_127 | _T_130; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_133 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_134 = _T_133 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_136 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_9 = io_wen0 & _T_136; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_138 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_9 = io_wen1 & _T_138; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_140 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_9 = io_wen2 & _T_140; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_143 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_144 = _T_143 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_146 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_147 = _T_146 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_148 = _T_144 | _T_147; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_150 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_151 = _T_150 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_153 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_10 = io_wen0 & _T_153; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_155 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_10 = io_wen1 & _T_155; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_157 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_10 = io_wen2 & _T_157; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_160 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = _T_160 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_163 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_164 = _T_163 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_165 = _T_161 | _T_164; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_167 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_168 = _T_167 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_170 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_11 = io_wen0 & _T_170; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_172 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_11 = io_wen1 & _T_172; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_174 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_11 = io_wen2 & _T_174; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_177 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = _T_177 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_180 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_181 = _T_180 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_182 = _T_178 | _T_181; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_184 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_185 = _T_184 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_187 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_12 = io_wen0 & _T_187; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_189 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_12 = io_wen1 & _T_189; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_191 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_12 = io_wen2 & _T_191; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_194 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = _T_194 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_197 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_198 = _T_197 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_199 = _T_195 | _T_198; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_201 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_202 = _T_201 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_204 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_13 = io_wen0 & _T_204; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_206 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_13 = io_wen1 & _T_206; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_208 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_13 = io_wen2 & _T_208; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_211 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_211 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_214 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_215 = _T_214 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_216 = _T_212 | _T_215; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_218 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_219 = _T_218 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_221 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_14 = io_wen0 & _T_221; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_223 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_14 = io_wen1 & _T_223; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_225 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_14 = io_wen2 & _T_225; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_228 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = _T_228 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_231 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_232 = _T_231 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_233 = _T_229 | _T_232; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_235 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_236 = _T_235 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_238 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_15 = io_wen0 & _T_238; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_240 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_15 = io_wen1 & _T_240; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_242 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_15 = io_wen2 & _T_242; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_245 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_245 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_248 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_249 = _T_248 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_250 = _T_246 | _T_249; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_252 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_253 = _T_252 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_255 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_16 = io_wen0 & _T_255; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_257 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_16 = io_wen1 & _T_257; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_259 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_16 = io_wen2 & _T_259; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_262 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_263 = _T_262 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_265 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_266 = _T_265 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_267 = _T_263 | _T_266; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_269 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_270 = _T_269 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_272 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_17 = io_wen0 & _T_272; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_274 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_17 = io_wen1 & _T_274; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_276 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_17 = io_wen2 & _T_276; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_279 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = _T_279 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_282 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_283 = _T_282 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_284 = _T_280 | _T_283; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_286 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_287 = _T_286 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_289 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_18 = io_wen0 & _T_289; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_291 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_18 = io_wen1 & _T_291; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_293 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_18 = io_wen2 & _T_293; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_296 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_297 = _T_296 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_299 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_300 = _T_299 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_301 = _T_297 | _T_300; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_303 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_304 = _T_303 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_306 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_19 = io_wen0 & _T_306; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_308 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_19 = io_wen1 & _T_308; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_310 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_19 = io_wen2 & _T_310; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_313 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_314 = _T_313 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_316 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_317 = _T_316 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_318 = _T_314 | _T_317; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_320 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_321 = _T_320 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_323 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_20 = io_wen0 & _T_323; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_325 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_20 = io_wen1 & _T_325; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_327 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_20 = io_wen2 & _T_327; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_330 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_331 = _T_330 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_333 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_334 = _T_333 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_335 = _T_331 | _T_334; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_337 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_338 = _T_337 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_340 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_21 = io_wen0 & _T_340; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_342 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_21 = io_wen1 & _T_342; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_344 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_21 = io_wen2 & _T_344; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_347 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_348 = _T_347 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_350 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_351 = _T_350 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_352 = _T_348 | _T_351; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_354 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_355 = _T_354 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_357 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_22 = io_wen0 & _T_357; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_359 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_22 = io_wen1 & _T_359; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_361 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_22 = io_wen2 & _T_361; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_364 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_365 = _T_364 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_367 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_368 = _T_367 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_369 = _T_365 | _T_368; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_371 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_372 = _T_371 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_374 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_23 = io_wen0 & _T_374; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_376 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_23 = io_wen1 & _T_376; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_378 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_23 = io_wen2 & _T_378; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_381 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_382 = _T_381 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_384 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_385 = _T_384 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_386 = _T_382 | _T_385; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_388 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_389 = _T_388 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_391 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_24 = io_wen0 & _T_391; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_393 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_24 = io_wen1 & _T_393; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_395 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_24 = io_wen2 & _T_395; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_398 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_399 = _T_398 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_401 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_402 = _T_401 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_403 = _T_399 | _T_402; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_405 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_406 = _T_405 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_408 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_25 = io_wen0 & _T_408; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_410 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_25 = io_wen1 & _T_410; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_412 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_25 = io_wen2 & _T_412; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_415 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_418 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_419 = _T_418 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_420 = _T_416 | _T_419; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_422 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_423 = _T_422 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_425 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_26 = io_wen0 & _T_425; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_427 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_26 = io_wen1 & _T_427; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_429 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_26 = io_wen2 & _T_429; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_432 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_433 = _T_432 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_435 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_436 = _T_435 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_437 = _T_433 | _T_436; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_439 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_442 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_27 = io_wen0 & _T_442; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_444 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_27 = io_wen1 & _T_444; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_446 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_27 = io_wen2 & _T_446; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_449 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_452 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_453 = _T_452 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_454 = _T_450 | _T_453; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_456 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_457 = _T_456 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_459 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_28 = io_wen0 & _T_459; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_461 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_28 = io_wen1 & _T_461; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_463 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_28 = io_wen2 & _T_463; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_466 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_467 = _T_466 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_469 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_470 = _T_469 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_471 = _T_467 | _T_470; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_473 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_474 = _T_473 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_476 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_29 = io_wen0 & _T_476; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_478 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_29 = io_wen1 & _T_478; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_480 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_29 = io_wen2 & _T_480; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_483 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_484 = _T_483 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_486 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_487 = _T_486 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_488 = _T_484 | _T_487; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_490 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_491 = _T_490 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_493 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_30 = io_wen0 & _T_493; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_495 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_30 = io_wen1 & _T_495; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_497 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_30 = io_wen2 & _T_497; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_500 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_501 = _T_500 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_503 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_504 = _T_503 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_505 = _T_501 | _T_504; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_507 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_508 = _T_507 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_510 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_31 = io_wen0 & _T_510; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_512 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_31 = io_wen1 & _T_512; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_514 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_31 = io_wen2 & _T_514; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_517 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_518 = _T_517 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_520 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_521 = _T_520 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_522 = _T_518 | _T_521; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_524 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_525 = _T_524 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire [9:0] _T_535 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_544 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_535}; // @[Cat.scala 29:58] + wire [27:0] _T_553 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_544}; // @[Cat.scala 29:58] + wire [31:0] _T_557 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_553}; // @[Cat.scala 29:58] + wire [9:0] _T_566 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_575 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_566}; // @[Cat.scala 29:58] + wire [27:0] _T_584 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_575}; // @[Cat.scala 29:58] + wire [31:0] _T_588 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_584}; // @[Cat.scala 29:58] + wire [31:0] _T_589 = _T_557 | _T_588; // @[el2_dec_gpr_ctl.scala 40:51] + wire [9:0] _T_598 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_607 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_598}; // @[Cat.scala 29:58] + wire [27:0] _T_616 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_607}; // @[Cat.scala 29:58] + wire [31:0] _T_620 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_616}; // @[Cat.scala 29:58] + wire [31:0] gpr_wr_en = _T_589 | _T_620; // @[el2_dec_gpr_ctl.scala 40:89] reg [31:0] gpr_out_1; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_2; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_3; // @[el2_lib.scala 514:16] @@ -49107,37 +49159,37 @@ module el2_dec_gpr_ctl( reg [31:0] gpr_out_29; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_30; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_31; // @[el2_lib.scala 514:16] - wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 47:49] wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] @@ -49198,37 +49250,37 @@ module el2_dec_gpr_ctl( wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72] wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72] wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72] - wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 48:49] wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] @@ -49475,8 +49527,8 @@ module el2_dec_gpr_ctl( .io_en(rvclkhdr_30_io_en), .io_scan_mode(rvclkhdr_30_io_scan_mode) ); - assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 21:9 el2_dec_gpr_ctl.scala 36:9] - assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 22:9 el2_dec_gpr_ctl.scala 37:9] + assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 31:9 el2_dec_gpr_ctl.scala 47:9] + assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 32:9 el2_dec_gpr_ctl.scala 48:9] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_en = gpr_wr_en[1]; // @[el2_lib.scala 511:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] @@ -49771,217 +49823,217 @@ end // initial if (reset) begin gpr_out_1 <= 32'h0; end else begin - gpr_out_1 <= _T_107 | _T_110; + gpr_out_1 <= _T_12 | _T_15; end end always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin gpr_out_2 <= 32'h0; end else begin - gpr_out_2 <= _T_124 | _T_127; + gpr_out_2 <= _T_29 | _T_32; end end always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin gpr_out_3 <= 32'h0; end else begin - gpr_out_3 <= _T_141 | _T_144; + gpr_out_3 <= _T_46 | _T_49; end end always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin gpr_out_4 <= 32'h0; end else begin - gpr_out_4 <= _T_158 | _T_161; + gpr_out_4 <= _T_63 | _T_66; end end always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin if (reset) begin gpr_out_5 <= 32'h0; end else begin - gpr_out_5 <= _T_175 | _T_178; + gpr_out_5 <= _T_80 | _T_83; end end always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin gpr_out_6 <= 32'h0; end else begin - gpr_out_6 <= _T_192 | _T_195; + gpr_out_6 <= _T_97 | _T_100; end end always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin gpr_out_7 <= 32'h0; end else begin - gpr_out_7 <= _T_209 | _T_212; + gpr_out_7 <= _T_114 | _T_117; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin gpr_out_8 <= 32'h0; end else begin - gpr_out_8 <= _T_226 | _T_229; + gpr_out_8 <= _T_131 | _T_134; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin gpr_out_9 <= 32'h0; end else begin - gpr_out_9 <= _T_243 | _T_246; + gpr_out_9 <= _T_148 | _T_151; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin gpr_out_10 <= 32'h0; end else begin - gpr_out_10 <= _T_260 | _T_263; + gpr_out_10 <= _T_165 | _T_168; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin gpr_out_11 <= 32'h0; end else begin - gpr_out_11 <= _T_277 | _T_280; + gpr_out_11 <= _T_182 | _T_185; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin if (reset) begin gpr_out_12 <= 32'h0; end else begin - gpr_out_12 <= _T_294 | _T_297; + gpr_out_12 <= _T_199 | _T_202; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin gpr_out_13 <= 32'h0; end else begin - gpr_out_13 <= _T_311 | _T_314; + gpr_out_13 <= _T_216 | _T_219; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin gpr_out_14 <= 32'h0; end else begin - gpr_out_14 <= _T_328 | _T_331; + gpr_out_14 <= _T_233 | _T_236; end end always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin if (reset) begin gpr_out_15 <= 32'h0; end else begin - gpr_out_15 <= _T_345 | _T_348; + gpr_out_15 <= _T_250 | _T_253; end end always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin if (reset) begin gpr_out_16 <= 32'h0; end else begin - gpr_out_16 <= _T_362 | _T_365; + gpr_out_16 <= _T_267 | _T_270; end end always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin if (reset) begin gpr_out_17 <= 32'h0; end else begin - gpr_out_17 <= _T_379 | _T_382; + gpr_out_17 <= _T_284 | _T_287; end end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin gpr_out_18 <= 32'h0; end else begin - gpr_out_18 <= _T_396 | _T_399; + gpr_out_18 <= _T_301 | _T_304; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin gpr_out_19 <= 32'h0; end else begin - gpr_out_19 <= _T_413 | _T_416; + gpr_out_19 <= _T_318 | _T_321; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin gpr_out_20 <= 32'h0; end else begin - gpr_out_20 <= _T_430 | _T_433; + gpr_out_20 <= _T_335 | _T_338; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin if (reset) begin gpr_out_21 <= 32'h0; end else begin - gpr_out_21 <= _T_447 | _T_450; + gpr_out_21 <= _T_352 | _T_355; end end always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin if (reset) begin gpr_out_22 <= 32'h0; end else begin - gpr_out_22 <= _T_464 | _T_467; + gpr_out_22 <= _T_369 | _T_372; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin if (reset) begin gpr_out_23 <= 32'h0; end else begin - gpr_out_23 <= _T_481 | _T_484; + gpr_out_23 <= _T_386 | _T_389; end end always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin if (reset) begin gpr_out_24 <= 32'h0; end else begin - gpr_out_24 <= _T_498 | _T_501; + gpr_out_24 <= _T_403 | _T_406; end end always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin if (reset) begin gpr_out_25 <= 32'h0; end else begin - gpr_out_25 <= _T_515 | _T_518; + gpr_out_25 <= _T_420 | _T_423; end end always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin if (reset) begin gpr_out_26 <= 32'h0; end else begin - gpr_out_26 <= _T_532 | _T_535; + gpr_out_26 <= _T_437 | _T_440; end end always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin if (reset) begin gpr_out_27 <= 32'h0; end else begin - gpr_out_27 <= _T_549 | _T_552; + gpr_out_27 <= _T_454 | _T_457; end end always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin if (reset) begin gpr_out_28 <= 32'h0; end else begin - gpr_out_28 <= _T_566 | _T_569; + gpr_out_28 <= _T_471 | _T_474; end end always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin if (reset) begin gpr_out_29 <= 32'h0; end else begin - gpr_out_29 <= _T_583 | _T_586; + gpr_out_29 <= _T_488 | _T_491; end end always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin if (reset) begin gpr_out_30 <= 32'h0; end else begin - gpr_out_30 <= _T_600 | _T_603; + gpr_out_30 <= _T_505 | _T_508; end end always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin if (reset) begin gpr_out_31 <= 32'h0; end else begin - gpr_out_31 <= _T_617 | _T_620; + gpr_out_31 <= _T_522 | _T_525; end end endmodule @@ -50056,7 +50108,7 @@ module el2_dec_timer_ctl( wire _T_10 = ~io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 2765:167] wire mitcnt0_inc_ok = _T_9 & _T_10; // @[el2_dec_tlu_ctl.scala 2765:165] wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[el2_dec_tlu_ctl.scala 2766:29] - wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:60] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:59] wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[el2_dec_tlu_ctl.scala 2775:66] wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[el2_dec_tlu_ctl.scala 2775:43] reg [2:0] _T_66; // @[el2_dec_tlu_ctl.scala 2830:46] @@ -50301,28 +50353,28 @@ module csr_tlu( output io_dec_tlu_ic_diag_pkt_icache_wr_valid, input io_ifu_ic_debug_rd_data_valid, output io_trigger_pkt_any_0_select, - output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_match_pkt, output io_trigger_pkt_any_0_store, output io_trigger_pkt_any_0_load, output io_trigger_pkt_any_0_execute, output io_trigger_pkt_any_0_m, output [31:0] io_trigger_pkt_any_0_tdata2, output io_trigger_pkt_any_1_select, - output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_match_pkt, output io_trigger_pkt_any_1_store, output io_trigger_pkt_any_1_load, output io_trigger_pkt_any_1_execute, output io_trigger_pkt_any_1_m, output [31:0] io_trigger_pkt_any_1_tdata2, output io_trigger_pkt_any_2_select, - output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_match_pkt, output io_trigger_pkt_any_2_store, output io_trigger_pkt_any_2_load, output io_trigger_pkt_any_2_execute, output io_trigger_pkt_any_2_m, output [31:0] io_trigger_pkt_any_2_tdata2, output io_trigger_pkt_any_3_select, - output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_match_pkt, output io_trigger_pkt_any_3_store, output io_trigger_pkt_any_3_load, output io_trigger_pkt_any_3_execute, @@ -50364,6 +50416,7 @@ module csr_tlu( input io_dma_pmu_any_write, input io_dma_pmu_any_read, input io_lsu_pmu_bus_busy, + input [30:0] io_dec_tlu_i0_pc_r, input io_dec_tlu_i0_valid_r, input io_dec_csr_any_unq_d, output io_dec_tlu_misc_clk_override, @@ -50398,7 +50451,7 @@ module csr_tlu( output io_dec_tlu_external_ldfwd_disable, output [2:0] io_dec_tlu_dma_qos_prty, input [31:0] io_dec_illegal_inst, - input io_lsu_error_pkt_r_bits_mscause, + input [3:0] io_lsu_error_pkt_r_bits_mscause, input io_mexintpend, input [30:0] io_exu_npc_r, input io_mpc_reset_run_req, @@ -50594,8 +50647,8 @@ module csr_tlu( reg [31:0] _RAND_35; reg [31:0] _RAND_36; reg [31:0] _RAND_37; - reg [95:0] _RAND_38; - reg [31:0] _RAND_39; + reg [31:0] _RAND_38; + reg [95:0] _RAND_39; reg [31:0] _RAND_40; reg [31:0] _RAND_41; reg [31:0] _RAND_42; @@ -50629,6 +50682,7 @@ module csr_tlu( reg [31:0] _RAND_70; reg [31:0] _RAND_71; reg [31:0] _RAND_72; + reg [31:0] _RAND_73; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] @@ -50833,7 +50887,7 @@ module csr_tlu( wire [31:0] _T_533 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] wire [31:0] _GEN_12 = {{31'd0}, _T_531}; // @[el2_dec_tlu_ctl.scala 1946:61] wire [31:0] _T_534 = _GEN_12 & _T_533; // @[el2_dec_tlu_ctl.scala 1946:61] - wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1455:41 el2_dec_tlu_ctl.scala 1946:15] + wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1946:15] wire ce_int = _T_61 | mice_ce_req; // @[el2_dec_tlu_ctl.scala 1570:47] wire [2:0] _T_63 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_65 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] @@ -50910,15 +50964,25 @@ module csr_tlu( wire [30:0] _T_159 = _T_158 | _T_156; // @[Mux.scala 27:72] wire _T_162 = sel_exu_npc_r | sel_flush_npc_r; // @[el2_dec_tlu_ctl.scala 1687:49] reg [30:0] _T_165; // @[el2_lib.scala 514:16] + wire pc0_valid_r = _T_140 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 1690:45] + wire _T_168 = ~pc0_valid_r; // @[el2_dec_tlu_ctl.scala 1694:5] + wire [30:0] _T_169 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] + reg [30:0] pc_r_d1; // @[el2_lib.scala 514:16] + wire [30:0] _T_170 = _T_168 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] pc_r = _T_169 | _T_170; // @[Mux.scala 27:72] wire _T_174 = io_dec_csr_wraddr_r == 12'h341; // @[el2_dec_tlu_ctl.scala 1698:69] wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_174; // @[el2_dec_tlu_ctl.scala 1698:40] + wire _T_175 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 1701:30] + wire _T_176 = _T_175 | io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1701:51] wire _T_180 = wr_mepc_r & _T_15; // @[el2_dec_tlu_ctl.scala 1703:16] wire _T_183 = ~wr_mepc_r; // @[el2_dec_tlu_ctl.scala 1704:6] wire _T_185 = _T_183 & _T_15; // @[el2_dec_tlu_ctl.scala 1704:17] + wire [30:0] _T_187 = _T_176 ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_188 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_189 = _T_180 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_190 = _T_185 ? io_mepc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_192 = _T_188 | _T_189; // @[Mux.scala 27:72] + wire [30:0] _T_191 = _T_187 | _T_188; // @[Mux.scala 27:72] + wire [30:0] _T_192 = _T_191 | _T_189; // @[Mux.scala 27:72] reg [30:0] _T_194; // @[el2_dec_tlu_ctl.scala 1706:48] wire _T_196 = io_dec_csr_wraddr_r == 12'h342; // @[el2_dec_tlu_ctl.scala 1713:71] wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_196; // @[el2_dec_tlu_ctl.scala 1713:42] @@ -50953,14 +51017,14 @@ module csr_tlu( wire _T_237 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[el2_dec_tlu_ctl.scala 1741:57] wire [3:0] _T_238 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] wire [3:0] ifu_mscause = _T_237 ? 4'h9 : _T_238; // @[el2_dec_tlu_ctl.scala 1741:25] - wire _T_243 = io_lsu_i0_exc_r & io_lsu_error_pkt_r_bits_mscause; // @[Mux.scala 27:72] + wire [3:0] _T_243 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] wire [1:0] _T_245 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [3:0] _T_246 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] - wire _T_247 = _T_243 | io_i0_trigger_hit_r; // @[Mux.scala 27:72] - wire [1:0] _GEN_13 = {{1'd0}, _T_247}; // @[Mux.scala 27:72] - wire [1:0] _T_248 = _GEN_13 | _T_245; // @[Mux.scala 27:72] - wire [3:0] _GEN_14 = {{2'd0}, _T_248}; // @[Mux.scala 27:72] - wire [3:0] mscause_type = _GEN_14 | _T_246; // @[Mux.scala 27:72] + wire [3:0] _GEN_13 = {{3'd0}, io_i0_trigger_hit_r}; // @[Mux.scala 27:72] + wire [3:0] _T_247 = _T_243 | _GEN_13; // @[Mux.scala 27:72] + wire [3:0] _GEN_14 = {{2'd0}, _T_245}; // @[Mux.scala 27:72] + wire [3:0] _T_248 = _T_247 | _GEN_14; // @[Mux.scala 27:72] + wire [3:0] mscause_type = _T_248 | _T_246; // @[Mux.scala 27:72] wire _T_252 = wr_mscause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1752:19] wire _T_255 = ~wr_mscause_r; // @[el2_dec_tlu_ctl.scala 1753:6] wire _T_257 = _T_255 & _T_15; // @[el2_dec_tlu_ctl.scala 1753:20] @@ -50992,6 +51056,9 @@ module csr_tlu( wire _T_285 = _T_283 & _T_284; // @[el2_dec_tlu_ctl.scala 1767:91] wire _T_286 = ~io_mepc_trigger_hit_sel_pc_r; // @[el2_dec_tlu_ctl.scala 1767:116] wire mtval_clear_r = _T_285 & _T_286; // @[el2_dec_tlu_ctl.scala 1767:114] + wire [31:0] _T_288 = {pc_r,1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_291 = pc_r + 31'h1; // @[el2_dec_tlu_ctl.scala 1772:84] + wire [31:0] _T_292 = {_T_291,1'h0}; // @[Cat.scala 29:58] wire _T_295 = ~io_interrupt_valid_r; // @[el2_dec_tlu_ctl.scala 1775:19] wire _T_296 = wr_mtval_r & _T_295; // @[el2_dec_tlu_ctl.scala 1775:17] wire _T_299 = ~wr_mtval_r; // @[el2_dec_tlu_ctl.scala 1776:21] @@ -51001,13 +51068,15 @@ module csr_tlu( wire _T_305 = ~mtval_clear_r; // @[el2_dec_tlu_ctl.scala 1776:81] wire _T_306 = _T_304 & _T_305; // @[el2_dec_tlu_ctl.scala 1776:79] wire _T_308 = _T_306 & _T_284; // @[el2_dec_tlu_ctl.scala 1776:96] - wire [31:0] _T_311 = mtval_capture_pc_plus2_r ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_310 = mtval_capture_pc_r ? _T_288 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_311 = mtval_capture_pc_plus2_r ? _T_292 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_312 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_313 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_314 = _T_296 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] reg [31:0] mtval; // @[el2_dec_tlu_ctl.scala 1778:47] wire [31:0] _T_315 = _T_308 ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_317 = _T_311 | _T_312; // @[Mux.scala 27:72] + wire [31:0] _T_316 = _T_310 | _T_311; // @[Mux.scala 27:72] + wire [31:0] _T_317 = _T_316 | _T_312; // @[Mux.scala 27:72] wire [31:0] _T_318 = _T_317 | _T_313; // @[Mux.scala 27:72] wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72] wire _T_323 = io_dec_csr_wraddr_r == 12'h7f8; // @[el2_dec_tlu_ctl.scala 1793:69] @@ -51177,7 +51246,9 @@ module csr_tlu( wire _T_710 = _T_709 & wr_dpc_r; // @[el2_dec_tlu_ctl.scala 2143:41] wire _T_715 = _T_707 & dpc_capture_npc; // @[el2_dec_tlu_ctl.scala 2145:22] wire [30:0] _T_717 = _T_710 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_718 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_719 = _T_715 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_720 = _T_717 | _T_718; // @[Mux.scala 27:72] wire _T_722 = wr_dpc_r | io_request_debug_mode_r; // @[el2_dec_tlu_ctl.scala 2147:37] reg [30:0] _T_725; // @[el2_lib.scala 514:16] wire [2:0] _T_729 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] @@ -52489,28 +52560,28 @@ module csr_tlu( assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2243:42] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2244:42] assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_0_match_ = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[el2_dec_tlu_ctl.scala 2312:36] assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 2313:36] assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[el2_dec_tlu_ctl.scala 2326:53] assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_1_match_ = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[el2_dec_tlu_ctl.scala 2312:36] assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 2313:36] assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[el2_dec_tlu_ctl.scala 2326:53] assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_2_match_ = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[el2_dec_tlu_ctl.scala 2312:36] assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 2313:36] assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[el2_dec_tlu_ctl.scala 2326:53] assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_3_match_ = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[el2_dec_tlu_ctl.scala 2312:36] @@ -52741,113 +52812,115 @@ initial begin _RAND_18 = {1{`RANDOM}}; _T_165 = _RAND_18[30:0]; _RAND_19 = {1{`RANDOM}}; - _T_194 = _RAND_19[30:0]; + pc_r_d1 = _RAND_19[30:0]; _RAND_20 = {1{`RANDOM}}; - mcause = _RAND_20[31:0]; + _T_194 = _RAND_20[30:0]; _RAND_21 = {1{`RANDOM}}; - mscause = _RAND_21[3:0]; + mcause = _RAND_21[31:0]; _RAND_22 = {1{`RANDOM}}; - mtval = _RAND_22[31:0]; + mscause = _RAND_22[3:0]; _RAND_23 = {1{`RANDOM}}; - mcgc = _RAND_23[8:0]; + mtval = _RAND_23[31:0]; _RAND_24 = {1{`RANDOM}}; - mfdc_int = _RAND_24[14:0]; + mcgc = _RAND_24[8:0]; _RAND_25 = {1{`RANDOM}}; - mrac = _RAND_25[31:0]; + mfdc_int = _RAND_25[14:0]; _RAND_26 = {1{`RANDOM}}; - mdseac = _RAND_26[31:0]; + mrac = _RAND_26[31:0]; _RAND_27 = {1{`RANDOM}}; - mfdht = _RAND_27[5:0]; + mdseac = _RAND_27[31:0]; _RAND_28 = {1{`RANDOM}}; - mfdhs = _RAND_28[1:0]; + mfdht = _RAND_28[5:0]; _RAND_29 = {1{`RANDOM}}; - force_halt_ctr_f = _RAND_29[31:0]; + mfdhs = _RAND_29[1:0]; _RAND_30 = {1{`RANDOM}}; - meivt = _RAND_30[21:0]; + force_halt_ctr_f = _RAND_30[31:0]; _RAND_31 = {1{`RANDOM}}; - meihap = _RAND_31[7:0]; + meivt = _RAND_31[21:0]; _RAND_32 = {1{`RANDOM}}; - meicurpl = _RAND_32[3:0]; + meihap = _RAND_32[7:0]; _RAND_33 = {1{`RANDOM}}; - meicidpl = _RAND_33[3:0]; + meicurpl = _RAND_33[3:0]; _RAND_34 = {1{`RANDOM}}; - meipt = _RAND_34[3:0]; + meicidpl = _RAND_34[3:0]; _RAND_35 = {1{`RANDOM}}; - _T_700 = _RAND_35[15:0]; + meipt = _RAND_35[3:0]; _RAND_36 = {1{`RANDOM}}; - _T_725 = _RAND_36[30:0]; + _T_700 = _RAND_36[15:0]; _RAND_37 = {1{`RANDOM}}; - dicawics = _RAND_37[16:0]; - _RAND_38 = {3{`RANDOM}}; - dicad0 = _RAND_38[70:0]; - _RAND_39 = {1{`RANDOM}}; - dicad0h = _RAND_39[31:0]; + _T_725 = _RAND_37[30:0]; + _RAND_38 = {1{`RANDOM}}; + dicawics = _RAND_38[16:0]; + _RAND_39 = {3{`RANDOM}}; + dicad0 = _RAND_39[70:0]; _RAND_40 = {1{`RANDOM}}; - _T_757 = _RAND_40[31:0]; + dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - icache_rd_valid_f = _RAND_41[0:0]; + _T_757 = _RAND_41[31:0]; _RAND_42 = {1{`RANDOM}}; - icache_wr_valid_f = _RAND_42[0:0]; + icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - mtsel = _RAND_43[1:0]; + icache_wr_valid_f = _RAND_43[0:0]; _RAND_44 = {1{`RANDOM}}; - _T_871 = _RAND_44[9:0]; + mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_872 = _RAND_45[9:0]; + _T_871 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_873 = _RAND_46[9:0]; + _T_872 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_874 = _RAND_47[9:0]; + _T_873 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - mtdata2_t_0 = _RAND_48[31:0]; + _T_874 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; - mtdata2_t_1 = _RAND_49[31:0]; + mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; - mtdata2_t_2 = _RAND_50[31:0]; + mtdata2_t_1 = _RAND_50[31:0]; _RAND_51 = {1{`RANDOM}}; - mtdata2_t_3 = _RAND_51[31:0]; + mtdata2_t_2 = _RAND_51[31:0]; _RAND_52 = {1{`RANDOM}}; - mhpme3 = _RAND_52[9:0]; + mtdata2_t_3 = _RAND_52[31:0]; _RAND_53 = {1{`RANDOM}}; - mhpme4 = _RAND_53[9:0]; + mhpme3 = _RAND_53[9:0]; _RAND_54 = {1{`RANDOM}}; - mhpme5 = _RAND_54[9:0]; + mhpme4 = _RAND_54[9:0]; _RAND_55 = {1{`RANDOM}}; - mhpme6 = _RAND_55[9:0]; + mhpme5 = _RAND_55[9:0]; _RAND_56 = {1{`RANDOM}}; - mhpmc_inc_r_d1_0 = _RAND_56[0:0]; + mhpme6 = _RAND_56[9:0]; _RAND_57 = {1{`RANDOM}}; - mhpmc_inc_r_d1_1 = _RAND_57[0:0]; + mhpmc_inc_r_d1_0 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - mhpmc_inc_r_d1_2 = _RAND_58[0:0]; + mhpmc_inc_r_d1_1 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - mhpmc_inc_r_d1_3 = _RAND_59[0:0]; + mhpmc_inc_r_d1_2 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - perfcnt_halted_d1 = _RAND_60[0:0]; + mhpmc_inc_r_d1_3 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - mhpmc3h = _RAND_61[31:0]; + perfcnt_halted_d1 = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - mhpmc3 = _RAND_62[31:0]; + mhpmc3h = _RAND_62[31:0]; _RAND_63 = {1{`RANDOM}}; - mhpmc4h = _RAND_63[31:0]; + mhpmc3 = _RAND_63[31:0]; _RAND_64 = {1{`RANDOM}}; - mhpmc4 = _RAND_64[31:0]; + mhpmc4h = _RAND_64[31:0]; _RAND_65 = {1{`RANDOM}}; - mhpmc5h = _RAND_65[31:0]; + mhpmc4 = _RAND_65[31:0]; _RAND_66 = {1{`RANDOM}}; - mhpmc5 = _RAND_66[31:0]; + mhpmc5h = _RAND_66[31:0]; _RAND_67 = {1{`RANDOM}}; - mhpmc6h = _RAND_67[31:0]; + mhpmc5 = _RAND_67[31:0]; _RAND_68 = {1{`RANDOM}}; - mhpmc6 = _RAND_68[31:0]; + mhpmc6h = _RAND_68[31:0]; _RAND_69 = {1{`RANDOM}}; - _T_2325 = _RAND_69[0:0]; + mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2330 = _RAND_70[0:0]; + _T_2325 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2331 = _RAND_71[4:0]; + _T_2330 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2332 = _RAND_72[0:0]; + _T_2331 = _RAND_72[4:0]; + _RAND_73 = {1{`RANDOM}}; + _T_2332 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -52906,6 +52979,9 @@ initial begin if (reset) begin _T_165 = 31'h0; end + if (reset) begin + pc_r_d1 = 31'h0; + end if (reset) begin _T_194 = 31'h0; end @@ -53223,6 +53299,13 @@ end // initial _T_165 <= io_npc_r; end end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + pc_r_d1 <= 31'h0; + end else begin + pc_r_d1 <= _T_169 | _T_170; + end + end always @(posedge io_e4e5_int_clk or posedge reset) begin if (reset) begin _T_194 <= 31'h0; @@ -53360,7 +53443,7 @@ end // initial if (reset) begin _T_725 <= 31'h0; end else begin - _T_725 <= _T_717 | _T_719; + _T_725 <= _T_720 | _T_719; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin @@ -54146,8 +54229,8 @@ module el2_dec_tlu_ctl( input io_lsu_error_pkt_r_bits_single_ecc_error, input io_lsu_error_pkt_r_bits_inst_type, input io_lsu_error_pkt_r_bits_exc_type, - input io_lsu_error_pkt_r_bits_mscause, - input io_lsu_error_pkt_r_bits_addr, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, input io_lsu_single_ecc_error_incr, input io_dec_pause_state, input io_lsu_imprecise_error_store_any, @@ -54162,6 +54245,7 @@ module el2_dec_tlu_ctl( input io_dec_csr_stall_int_ff, input io_dec_tlu_i0_valid_r, input [30:0] io_exu_npc_r, + input [30:0] io_dec_tlu_i0_pc_r, input io_dec_tlu_packet_r_legal, input io_dec_tlu_packet_r_icaf, input io_dec_tlu_packet_r_icaf_f1, @@ -54199,28 +54283,28 @@ module el2_dec_tlu_ctl( input io_lsu_idle_any, input io_dec_div_active, output io_trigger_pkt_any_0_select, - output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_match_pkt, output io_trigger_pkt_any_0_store, output io_trigger_pkt_any_0_load, output io_trigger_pkt_any_0_execute, output io_trigger_pkt_any_0_m, output [31:0] io_trigger_pkt_any_0_tdata2, output io_trigger_pkt_any_1_select, - output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_match_pkt, output io_trigger_pkt_any_1_store, output io_trigger_pkt_any_1_load, output io_trigger_pkt_any_1_execute, output io_trigger_pkt_any_1_m, output [31:0] io_trigger_pkt_any_1_tdata2, output io_trigger_pkt_any_2_select, - output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_match_pkt, output io_trigger_pkt_any_2_store, output io_trigger_pkt_any_2_load, output io_trigger_pkt_any_2_execute, output io_trigger_pkt_any_2_m, output [31:0] io_trigger_pkt_any_2_tdata2, output io_trigger_pkt_any_3_select, - output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_match_pkt, output io_trigger_pkt_any_3_store, output io_trigger_pkt_any_3_load, output io_trigger_pkt_any_3_execute, @@ -54256,11 +54340,11 @@ module el2_dec_tlu_ctl( output [31:0] io_dec_csr_rddata_d, output io_dec_csr_legal_d, output io_dec_tlu_br0_r_pkt_valid, - output [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - output io_dec_tlu_br0_r_pkt_bits_br_error, - output io_dec_tlu_br0_r_pkt_bits_br_start_error, - output io_dec_tlu_br0_r_pkt_bits_way, - output io_dec_tlu_br0_r_pkt_bits_middle, + output [1:0] io_dec_tlu_br0_r_pkt_hist, + output io_dec_tlu_br0_r_pkt_br_error, + output io_dec_tlu_br0_r_pkt_br_start_error, + output io_dec_tlu_br0_r_pkt_way, + output io_dec_tlu_br0_r_pkt_middle, output io_dec_tlu_i0_kill_writeb_wb, output io_dec_tlu_flush_lower_wb, output io_dec_tlu_i0_commit_cmt, @@ -54426,28 +54510,28 @@ module el2_dec_tlu_ctl( wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 897:17] @@ -54489,6 +54573,7 @@ module el2_dec_tlu_ctl( wire csr_io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 897:17] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_dec_tlu_misc_clk_override; // @[el2_dec_tlu_ctl.scala 897:17] @@ -54523,7 +54608,7 @@ module el2_dec_tlu_ctl( wire csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 897:17] wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_mexintpend; // @[el2_dec_tlu_ctl.scala 897:17] wire [30:0] csr_io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 897:17] @@ -54759,7 +54844,7 @@ module el2_dec_tlu_ctl( wire i_cpu_run_req_sync = syncro_ff[2]; // @[el2_dec_tlu_ctl.scala 386:59] wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[el2_dec_tlu_ctl.scala 387:51] wire mpc_debug_run_req_sync = syncro_ff[0]; // @[el2_dec_tlu_ctl.scala 388:51] - wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 345:41 el2_dec_tlu_ctl.scala 1083:31] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 1083:31] reg lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 693:74] wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 392:61] reg e5_valid; // @[el2_dec_tlu_ctl.scala 404:89] @@ -54784,11 +54869,11 @@ module el2_dec_tlu_ctl( wire _T_44 = take_ext_int_start_d3 & _T_43; // @[el2_dec_tlu_ctl.scala 429:140] wire nmi_int_detected = _T_42 | _T_44; // @[el2_dec_tlu_ctl.scala 429:116] wire _T_631 = ~io_dec_csr_stall_int_ff; // @[el2_dec_tlu_ctl.scala 803:22] - wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 344:41 el2_dec_tlu_ctl.scala 1082:31] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 1082:31] wire _T_632 = _T_631 & mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 803:47] - wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 350:41 el2_dec_tlu_ctl.scala 1088:31] + wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 1088:31] wire _T_634 = _T_632 & mip[1]; // @[el2_dec_tlu_ctl.scala 803:64] - wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 339:41 el2_dec_tlu_ctl.scala 1077:31] + wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 1077:31] wire timer_int_ready = _T_634 & mie_ns[1]; // @[el2_dec_tlu_ctl.scala 803:82] wire _T_391 = nmi_int_detected | timer_int_ready; // @[el2_dec_tlu_ctl.scala 680:65] wire _T_628 = _T_632 & mip[0]; // @[el2_dec_tlu_ctl.scala 802:64] @@ -54844,7 +54929,7 @@ module el2_dec_tlu_ctl( reg ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 752:58] wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 503:126] reg debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 535:81] - wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 342:57 el2_dec_tlu_ctl.scala 1080:31] + wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 1080:31] reg lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 531:89] wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 497:47] wire _T_143 = _T_142 & io_ifu_miss_state_idle; // @[el2_dec_tlu_ctl.scala 497:64] @@ -54885,7 +54970,7 @@ module el2_dec_tlu_ctl( wire _T_167 = ~dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 514:67] wire _T_168 = debug_halt_req_f & _T_167; // @[el2_dec_tlu_ctl.scala 514:65] wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[el2_dec_tlu_ctl.scala 514:45] - wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 348:41 el2_dec_tlu_ctl.scala 1086:31] + wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 1086:31] wire _T_157 = ~dcsr[2]; // @[el2_dec_tlu_ctl.scala 506:100] wire _T_158 = debug_resume_req_f & _T_157; // @[el2_dec_tlu_ctl.scala 506:98] wire _T_159 = ~_T_158; // @[el2_dec_tlu_ctl.scala 506:77] @@ -54903,7 +54988,7 @@ module el2_dec_tlu_ctl( wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 649:54] wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[el2_dec_tlu_ctl.scala 649:79] wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[el2_dec_tlu_ctl.scala 665:49] - wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 346:41 el2_dec_tlu_ctl.scala 1084:31] + wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 1084:31] wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[el2_dec_tlu_ctl.scala 666:47] reg pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 658:73] wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 671:44] @@ -54962,7 +55047,7 @@ module el2_dec_tlu_ctl( wire [3:0] _T_290 = _T_287 & _T_289; // @[el2_dec_tlu_ctl.scala 593:65] wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[el2_dec_tlu_ctl.scala 593:34] wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:118] - wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 347:41 el2_dec_tlu_ctl.scala 1085:31] + wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 1085:31] wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:62] wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 587:86] wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:150] @@ -55354,7 +55439,7 @@ module el2_dec_tlu_ctl( wire _T_682 = _T_681 | take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 830:66] wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 832:45] - wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 349:41 el2_dec_tlu_ctl.scala 1087:31] + wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 1087:31] wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] wire [30:0] vectored_path = _T_769 + _T_771; // @[el2_dec_tlu_ctl.scala 860:50] @@ -55371,6 +55456,10 @@ module el2_dec_tlu_ctl( wire _T_800 = _T_799 | take_halt; // @[el2_dec_tlu_ctl.scala 866:73] wire _T_801 = _T_800 | take_reset; // @[el2_dec_tlu_ctl.scala 866:85] wire _T_807 = _T_529 & sel_npc_r; // @[el2_dec_tlu_ctl.scala 870:21] + wire _T_810 = _T_529 & rfpc_i0_r; // @[el2_dec_tlu_ctl.scala 871:21] + wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 871:39] + wire _T_813 = ~sel_npc_r; // @[el2_dec_tlu_ctl.scala 871:80] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_tlu_ctl.scala 871:69] wire _T_816 = ~take_ext_int; // @[el2_dec_tlu_ctl.scala 872:44] wire _T_817 = interrupt_valid_r & _T_816; // @[el2_dec_tlu_ctl.scala 872:30] wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[el2_dec_tlu_ctl.scala 873:28] @@ -55381,18 +55470,20 @@ module el2_dec_tlu_ctl( wire _T_833 = _T_529 & debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 875:16] wire _T_836 = _T_529 & sel_npc_resume; // @[el2_dec_tlu_ctl.scala 876:16] wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 337:41 el2_dec_tlu_ctl.scala 1075:31] + wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 1075:31] wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] - wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 340:41 el2_dec_tlu_ctl.scala 1078:31] + wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 1078:31] wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 343:41 el2_dec_tlu_ctl.scala 1081:31] + wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 1081:31] wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 338:41 el2_dec_tlu_ctl.scala 1076:31] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 1076:31] wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] - wire [30:0] _T_848 = _T_846 | _T_841; // @[Mux.scala 27:72] + wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] + wire [30:0] _T_848 = _T_847 | _T_841; // @[Mux.scala 27:72] wire [30:0] _T_849 = _T_848 | _T_842; // @[Mux.scala 27:72] wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72] wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72] @@ -55507,28 +55598,28 @@ module el2_dec_tlu_ctl( .io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid), .io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid), .io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(csr_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(csr_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute), .io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m), .io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(csr_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(csr_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute), .io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m), .io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(csr_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(csr_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute), .io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m), .io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(csr_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(csr_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute), @@ -55570,6 +55661,7 @@ module el2_dec_tlu_ctl( .io_dma_pmu_any_write(csr_io_dma_pmu_any_write), .io_dma_pmu_any_read(csr_io_dma_pmu_any_read), .io_lsu_pmu_bus_busy(csr_io_lsu_pmu_bus_busy), + .io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r), .io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r), .io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d), .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), @@ -55844,28 +55936,28 @@ module el2_dec_tlu_ctl( assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 557:27] assign io_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 956:44] assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_0_match_ = csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_1_match_ = csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_2_match_ = csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_3_match_ = csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 962:40] @@ -55887,11 +55979,11 @@ module el2_dec_tlu_ctl( assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40] assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22] assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49] - assign io_dec_tlu_br0_r_pkt_bits_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:57] - assign io_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49] - assign io_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:49] - assign io_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:57] - assign io_dec_tlu_br0_r_pkt_bits_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:57] + assign io_dec_tlu_br0_r_pkt_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:49] + assign io_dec_tlu_br0_r_pkt_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49] + assign io_dec_tlu_br0_r_pkt_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:41] + assign io_dec_tlu_br0_r_pkt_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:49] + assign io_dec_tlu_br0_r_pkt_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:49] assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33] assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33] assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28] @@ -55993,6 +56085,7 @@ module el2_dec_tlu_ctl( assign csr_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec_tlu_ctl.scala 927:44] assign csr_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec_tlu_ctl.scala 928:44] assign csr_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 929:44] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[el2_dec_tlu_ctl.scala 930:44] assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[el2_dec_tlu_ctl.scala 931:44] assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 933:44] assign csr_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec_tlu_ctl.scala 934:44] @@ -56042,7 +56135,7 @@ module el2_dec_tlu_ctl( assign csr_io_inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 1021:39] assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[el2_dec_tlu_ctl.scala 1022:39] assign csr_io_take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 1023:39] - assign csr_io_lsu_error_pkt_addr_r = {{31'd0}, io_lsu_error_pkt_r_bits_addr}; // @[el2_dec_tlu_ctl.scala 1024:39] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[el2_dec_tlu_ctl.scala 1024:39] assign csr_io_exc_cause_r = _T_603 | _T_591; // @[el2_dec_tlu_ctl.scala 1025:39] assign csr_io_i0_valid_wb = i0_valid_wb; // @[el2_dec_tlu_ctl.scala 1026:39] assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1027:39] @@ -57094,22 +57187,22 @@ end // initial endmodule module el2_dec_trigger( input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_execute, input io_trigger_pkt_any_0_m, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_execute, input io_trigger_pkt_any_1_m, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_execute, input io_trigger_pkt_any_2_m, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_execute, input io_trigger_pkt_any_3_m, input [31:0] io_trigger_pkt_any_3_tdata2, @@ -57151,7 +57244,7 @@ module el2_dec_trigger( wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83] wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] wire _T_152 = ~_T_151; // @[el2_lib.scala 241:39] - wire _T_153 = io_trigger_pkt_any_0_match_ & _T_152; // @[el2_lib.scala 241:37] + wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[el2_lib.scala 241:37] wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 242:52] wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 242:41] wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] @@ -57287,7 +57380,7 @@ module el2_dec_trigger( wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83] wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] wire _T_411 = ~_T_410; // @[el2_lib.scala 241:39] - wire _T_412 = io_trigger_pkt_any_1_match_ & _T_411; // @[el2_lib.scala 241:37] + wire _T_412 = io_trigger_pkt_any_1_match_pkt & _T_411; // @[el2_lib.scala 241:37] wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 242:52] wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 242:41] wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] @@ -57423,7 +57516,7 @@ module el2_dec_trigger( wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83] wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] wire _T_670 = ~_T_669; // @[el2_lib.scala 241:39] - wire _T_671 = io_trigger_pkt_any_2_match_ & _T_670; // @[el2_lib.scala 241:37] + wire _T_671 = io_trigger_pkt_any_2_match_pkt & _T_670; // @[el2_lib.scala 241:37] wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 242:52] wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 242:41] wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] @@ -57559,7 +57652,7 @@ module el2_dec_trigger( wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83] wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] wire _T_929 = ~_T_928; // @[el2_lib.scala 241:39] - wire _T_930 = io_trigger_pkt_any_3_match_ & _T_929; // @[el2_lib.scala 241:37] + wire _T_930 = io_trigger_pkt_any_3_match_pkt & _T_929; // @[el2_lib.scala 241:37] wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 242:52] wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 242:41] wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] @@ -57704,16 +57797,16 @@ module el2_dec( output io_dec_extint_stall, output io_dec_i0_decode_d, output io_dec_pause_state_cg, - input [31:0] io_rst_vec, + input [30:0] io_rst_vec, input io_nmi_int, - input [31:0] io_nmi_vec, + input [30:0] io_nmi_vec, input io_i_cpu_halt_req, input io_i_cpu_run_req, output io_o_cpu_halt_status, output io_o_cpu_halt_ack, output io_o_cpu_run_ack, output io_o_debug_mode_status, - input [31:0] io_core_id, + input [27:0] io_core_id, input io_mpc_debug_halt_req, input io_mpc_debug_run_req, input io_mpc_reset_run_req, @@ -57741,7 +57834,7 @@ module el2_dec( input io_dma_pmu_dccm_write, input io_dma_pmu_any_read, input io_dma_pmu_any_write, - input [31:0] io_lsu_fir_addr, + input [30:0] io_lsu_fir_addr, input [1:0] io_lsu_fir_error, input io_ifu_pmu_instr_aligned, input io_ifu_pmu_fetch_stall, @@ -57764,22 +57857,22 @@ module el2_dec( input io_ifu_i0_dbecc, input io_lsu_idle_any, input io_i0_brp_valid, - input [11:0] io_i0_brp_bits_toffset, - input [1:0] io_i0_brp_bits_hist, - input io_i0_brp_bits_br_error, - input io_i0_brp_bits_br_start_error, - input [30:0] io_i0_brp_bits_prett, - input io_i0_brp_bits_way, - input io_i0_brp_bits_ret, - input [8:0] io_ifu_i0_bp_index, + input [11:0] io_i0_brp_toffset, + input [1:0] io_i0_brp_hist, + input io_i0_brp_br_error, + input io_i0_brp_br_start_error, + input [30:0] io_i0_brp_prett, + input io_i0_brp_way, + input io_i0_brp_ret, + input [7:0] io_ifu_i0_bp_index, input [7:0] io_ifu_i0_bp_fghr, input [4:0] io_ifu_i0_bp_btag, input io_lsu_error_pkt_r_valid, input io_lsu_error_pkt_r_bits_single_ecc_error, input io_lsu_error_pkt_r_bits_inst_type, input io_lsu_error_pkt_r_bits_exc_type, - input io_lsu_error_pkt_r_bits_mscause, - input io_lsu_error_pkt_r_bits_addr, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, input io_lsu_single_ecc_error_incr, input io_lsu_imprecise_error_load_any, input io_lsu_imprecise_error_store_any, @@ -57795,11 +57888,13 @@ module el2_dec( input io_dma_iccm_stall_any, input io_iccm_dma_sb_error, input io_exu_flush_final, - input [31:0] io_exu_npc_r, + input [30:0] io_exu_npc_r, input [31:0] io_exu_i0_result_x, input io_ifu_i0_valid, input [31:0] io_ifu_i0_instr, - input [31:0] io_ifu_i0_pc, + input [30:0] io_ifu_i0_pc, + input io_ifu_i0_pc4, + input [30:0] io_exu_i0_pc_x, input io_mexintpend, input io_timer_int, input io_soft_int, @@ -57808,7 +57903,7 @@ module el2_dec( input io_mhwakeup, output [3:0] io_dec_tlu_meicurpl, output [3:0] io_dec_tlu_meipt, - input [69:0] io_ifu_ic_debug_rd_data, + input [70:0] io_ifu_ic_debug_rd_data, input io_ifu_ic_debug_rd_data_valid, output [70:0] io_dec_tlu_ic_diag_pkt_icache_wrdata, output [16:0] io_dec_tlu_ic_diag_pkt_icache_dicawics, @@ -57824,28 +57919,28 @@ module el2_dec( output io_dec_tlu_mpc_halted_only, output io_dec_tlu_flush_leak_one_r, output io_dec_tlu_flush_err_r, - output [31:0] io_dec_tlu_meihap, + output [29:0] io_dec_tlu_meihap, output io_dec_debug_wdata_rs1_d, output [31:0] io_dec_dbg_rddata, output io_dec_dbg_cmd_done, output io_dec_dbg_cmd_fail, output io_trigger_pkt_any_0_select, - output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_match_pkt, output io_trigger_pkt_any_0_store, output io_trigger_pkt_any_0_load, output [31:0] io_trigger_pkt_any_0_tdata2, output io_trigger_pkt_any_1_select, - output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_match_pkt, output io_trigger_pkt_any_1_store, output io_trigger_pkt_any_1_load, output [31:0] io_trigger_pkt_any_1_tdata2, output io_trigger_pkt_any_2_select, - output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_match_pkt, output io_trigger_pkt_any_2_store, output io_trigger_pkt_any_2_load, output [31:0] io_trigger_pkt_any_2_tdata2, output io_trigger_pkt_any_3_select, - output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_match_pkt, output io_trigger_pkt_any_3_store, output io_trigger_pkt_any_3_load, output [31:0] io_trigger_pkt_any_3_tdata2, @@ -57862,7 +57957,7 @@ module el2_dec( output [31:0] io_gpr_i0_rs1_d, output [31:0] io_gpr_i0_rs2_d, output [31:0] io_dec_i0_immed_d, - output [12:0] io_dec_i0_br_immed_d, + output [11:0] io_dec_i0_br_immed_d, output io_i0_ap_land, output io_i0_ap_lor, output io_i0_ap_lxor, @@ -57883,6 +57978,8 @@ module el2_dec( output io_i0_ap_csr_write, output io_i0_ap_csr_imm, output io_dec_i0_alu_decode_d, + output io_dec_i0_select_pc_d, + output [30:0] io_dec_i0_pc_d, output [1:0] io_dec_i0_rs1_bypass_en_d, output [1:0] io_dec_i0_rs2_bypass_en_d, output [31:0] io_dec_i0_rs1_bypass_data_d, @@ -57908,16 +58005,16 @@ module el2_dec( output [11:0] io_dec_lsu_offset_d, output io_dec_csr_ren_d, output io_dec_tlu_flush_lower_r, - output [31:0] io_dec_tlu_flush_path_r, + output [30:0] io_dec_tlu_flush_path_r, output io_dec_tlu_i0_kill_writeb_r, output io_dec_tlu_fence_i_r, - output [31:0] io_pred_correct_npc_x, + output [30:0] io_pred_correct_npc_x, output io_dec_tlu_br0_r_pkt_valid, - output [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - output io_dec_tlu_br0_r_pkt_bits_br_error, - output io_dec_tlu_br0_r_pkt_bits_br_start_error, - output io_dec_tlu_br0_r_pkt_bits_way, - output io_dec_tlu_br0_r_pkt_bits_middle, + output [1:0] io_dec_tlu_br0_r_pkt_hist, + output io_dec_tlu_br0_r_pkt_br_error, + output io_dec_tlu_br0_r_pkt_br_start_error, + output io_dec_tlu_br0_r_pkt_way, + output io_dec_tlu_br0_r_pkt_middle, output io_dec_tlu_perfcnt0, output io_dec_tlu_perfcnt1, output io_dec_tlu_perfcnt2, @@ -57934,7 +58031,7 @@ module el2_dec( output io_dec_i0_predict_p_d_bits_pja, output io_dec_i0_predict_p_d_bits_way, output [7:0] io_i0_predict_fghr_d, - output [8:0] io_i0_predict_index_d, + output [7:0] io_i0_predict_index_d, output [4:0] io_i0_predict_btag_d, output io_dec_lsu_valid_raw_d, output [31:0] io_dec_tlu_mrac_ff, @@ -57962,466 +58059,472 @@ module el2_dec( output io_dec_tlu_i0_commit_cmt, input io_scan_mode ); - wire instbuff_io_dbg_cmd_valid; // @[el2_dec.scala 353:24] - wire instbuff_io_dbg_cmd_write; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 353:24] - wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_valid; // @[el2_dec.scala 353:24] - wire [11:0] instbuff_io_i0_brp_bits_toffset; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_i0_brp_bits_hist; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_bits_br_error; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_bits_br_start_error; // @[el2_dec.scala 353:24] - wire [30:0] instbuff_io_i0_brp_bits_prett; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_bits_way; // @[el2_dec.scala 353:24] - wire instbuff_io_i0_brp_bits_ret; // @[el2_dec.scala 353:24] - wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 353:24] - wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 353:24] - wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 353:24] - wire instbuff_io_ifu_i0_valid; // @[el2_dec.scala 353:24] - wire instbuff_io_ifu_i0_icaf; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_ifu_i0_icaf_type; // @[el2_dec.scala 353:24] - wire instbuff_io_ifu_i0_icaf_f1; // @[el2_dec.scala 353:24] - wire instbuff_io_ifu_i0_dbecc; // @[el2_dec.scala 353:24] - wire [31:0] instbuff_io_ifu_i0_instr; // @[el2_dec.scala 353:24] - wire [30:0] instbuff_io_ifu_i0_pc; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 353:24] - wire [31:0] instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 353:24] - wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 353:24] - wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 353:24] - wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 353:24] - wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 353:24] - wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 353:24] - wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 353:24] - wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 353:24] - wire instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 353:24] - wire decode_clock; // @[el2_dec.scala 354:22] - wire decode_reset; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_extint; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_force_halt; // @[el2_dec.scala 354:22] - wire decode_io_dec_extint_stall; // @[el2_dec.scala 354:22] - wire [15:0] decode_io_ifu_i0_cinst; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_dec_i0_pc_wb1; // @[el2_dec.scala 354:22] - wire decode_io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 354:22] - wire decode_io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 354:22] - wire decode_io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 354:22] - wire decode_io_lsu_nonblock_load_data_error; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_lsu_nonblock_load_data; // @[el2_dec.scala 354:22] - wire [3:0] decode_io_dec_i0_trigger_match_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 354:22] - wire [3:0] decode_io_lsu_trigger_match_m; // @[el2_dec.scala 354:22] - wire decode_io_lsu_pmu_misaligned_m; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_debug_stall; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_debug_fence_d; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dbg_cmd_wrdata; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_icaf_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_valid; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_bits_way; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 354:22] - wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 354:22] - wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 354:22] - wire decode_io_lsu_idle_any; // @[el2_dec.scala 354:22] - wire decode_io_lsu_load_stall_any; // @[el2_dec.scala 354:22] - wire decode_io_lsu_store_stall_any; // @[el2_dec.scala 354:22] - wire decode_io_dma_dccm_stall_any; // @[el2_dec.scala 354:22] - wire decode_io_exu_div_wren; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_presync_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_postsync_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_pc4_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_csr_rddata_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_legal_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_exu_csr_rs1_x; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_lsu_result_m; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_lsu_result_corr_r; // @[el2_dec.scala 354:22] - wire decode_io_exu_flush_final; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_instr_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_ib0_valid_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_exu_i0_result_x; // @[el2_dec.scala 354:22] - wire decode_io_free_clk; // @[el2_dec.scala 354:22] - wire decode_io_active_clk; // @[el2_dec.scala 354:22] - wire decode_io_clk_override; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_i0_rs1_d; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_i0_rs2_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_immed_d; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_i0_br_immed_d; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_land; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_lor; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_lxor; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_sll; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_srl; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_sra; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_beq; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_bne; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_blt; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_bge; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_add; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_sub; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_slt; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_unsign; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_jal; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_predict_t; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_predict_nt; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_csr_write; // @[el2_dec.scala 354:22] - wire decode_io_i0_ap_csr_imm; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_decode_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_i0_waddr_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_wen_r; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_i0_wdata_r; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_valid; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_by; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_half; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_word; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_load; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_store; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 354:22] - wire decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 354:22] - wire decode_io_mul_p_valid; // @[el2_dec.scala 354:22] - wire decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 354:22] - wire decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 354:22] - wire decode_io_mul_p_bits_low; // @[el2_dec.scala 354:22] - wire decode_io_div_p_valid; // @[el2_dec.scala 354:22] - wire decode_io_div_p_bits_unsign; // @[el2_dec.scala 354:22] - wire decode_io_div_p_bits_rem; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_div_waddr_wb; // @[el2_dec.scala 354:22] - wire decode_io_dec_div_cancel; // @[el2_dec.scala 354:22] - wire decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_lsu_offset_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_ren_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_wen_r; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 354:22] - wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 354:22] - wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 354:22] - wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 354:22] - wire [31:0] decode_io_dec_illegal_inst; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_pred_correct_npc_x; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 354:22] - wire [11:0] decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 354:22] - wire [30:0] decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 354:22] - wire decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 354:22] - wire [7:0] decode_io_i0_predict_fghr_d; // @[el2_dec.scala 354:22] - wire [7:0] decode_io_i0_predict_index_d; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_i0_predict_btag_d; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_data_en; // @[el2_dec.scala 354:22] - wire [1:0] decode_io_dec_ctl_en; // @[el2_dec.scala 354:22] - wire decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 354:22] - wire decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 354:22] - wire decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 354:22] - wire decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 354:22] - wire decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 354:22] - wire [4:0] decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 354:22] - wire decode_io_dec_pause_state; // @[el2_dec.scala 354:22] - wire decode_io_dec_pause_state_cg; // @[el2_dec.scala 354:22] - wire decode_io_dec_div_active; // @[el2_dec.scala 354:22] - wire decode_io_scan_mode; // @[el2_dec.scala 354:22] - wire gpr_clock; // @[el2_dec.scala 355:19] - wire gpr_reset; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_raddr0; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_raddr1; // @[el2_dec.scala 355:19] - wire gpr_io_wen0; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_waddr0; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_wd0; // @[el2_dec.scala 355:19] - wire gpr_io_wen1; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_waddr1; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_wd1; // @[el2_dec.scala 355:19] - wire gpr_io_wen2; // @[el2_dec.scala 355:19] - wire [4:0] gpr_io_waddr2; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_wd2; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_rd0; // @[el2_dec.scala 355:19] - wire [31:0] gpr_io_rd1; // @[el2_dec.scala 355:19] - wire gpr_io_scan_mode; // @[el2_dec.scala 355:19] - wire tlu_clock; // @[el2_dec.scala 356:19] - wire tlu_reset; // @[el2_dec.scala 356:19] - wire tlu_io_active_clk; // @[el2_dec.scala 356:19] - wire tlu_io_free_clk; // @[el2_dec.scala 356:19] - wire tlu_io_scan_mode; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_rst_vec; // @[el2_dec.scala 356:19] - wire tlu_io_nmi_int; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_nmi_vec; // @[el2_dec.scala 356:19] - wire tlu_io_i_cpu_halt_req; // @[el2_dec.scala 356:19] - wire tlu_io_i_cpu_run_req; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_fastint_stall_any; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_instr_aligned; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_fetch_stall; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_ic_miss; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_ic_hit; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_bus_error; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_bus_busy; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_pmu_bus_trxn; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pmu_instr_decoded; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pmu_decode_stall; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pmu_presync_stall; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pmu_postsync_stall; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_store_stall_any; // @[el2_dec.scala 356:19] - wire tlu_io_dma_dccm_stall_any; // @[el2_dec.scala 356:19] - wire tlu_io_dma_iccm_stall_any; // @[el2_dec.scala 356:19] - wire tlu_io_exu_pmu_i0_br_misp; // @[el2_dec.scala 356:19] - wire tlu_io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 356:19] - wire tlu_io_exu_pmu_i0_pc4; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_bus_trxn; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_bus_error; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_bus_busy; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_load_external_m; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_pmu_store_external_m; // @[el2_dec.scala 356:19] - wire tlu_io_dma_pmu_dccm_read; // @[el2_dec.scala 356:19] - wire tlu_io_dma_pmu_dccm_write; // @[el2_dec.scala 356:19] - wire tlu_io_dma_pmu_any_read; // @[el2_dec.scala 356:19] - wire tlu_io_dma_pmu_any_write; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_lsu_fir_addr; // @[el2_dec.scala 356:19] - wire [1:0] tlu_io_lsu_fir_error; // @[el2_dec.scala 356:19] - wire tlu_io_iccm_dma_sb_error; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_valid; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_single_ecc_error_incr; // @[el2_dec.scala 356:19] - wire tlu_io_dec_pause_state; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_imprecise_error_store_any; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_imprecise_error_load_any; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_wen_unq_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_any_unq_d; // @[el2_dec.scala 356:19] - wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_wen_r; // @[el2_dec.scala 356:19] - wire [11:0] tlu_io_dec_csr_wraddr_r; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_csr_wrdata_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_stall_int_ff; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_exu_npc_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 356:19] - wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_illegal_inst; // @[el2_dec.scala 356:19] - wire tlu_io_dec_i0_decode_d; // @[el2_dec.scala 356:19] - wire [1:0] tlu_io_exu_i0_br_hist_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_error_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_start_error_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_valid_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_mp_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_middle_r; // @[el2_dec.scala 356:19] - wire tlu_io_exu_i0_br_way_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 356:19] - wire tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 356:19] - wire [29:0] tlu_io_dec_tlu_meihap; // @[el2_dec.scala 356:19] - wire tlu_io_dbg_halt_req; // @[el2_dec.scala 356:19] - wire tlu_io_dbg_resume_req; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_miss_state_idle; // @[el2_dec.scala 356:19] - wire tlu_io_lsu_idle_any; // @[el2_dec.scala 356:19] - wire tlu_io_dec_div_active; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 356:19] - wire tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_ic_error_start; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 356:19] - wire [70:0] tlu_io_ifu_ic_debug_rd_data; // @[el2_dec.scala 356:19] - wire tlu_io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 356:19] - wire [70:0] tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 356:19] - wire [16:0] tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 356:19] - wire [7:0] tlu_io_pic_claimid; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_pic_pl; // @[el2_dec.scala 356:19] - wire tlu_io_mhwakeup; // @[el2_dec.scala 356:19] - wire tlu_io_mexintpend; // @[el2_dec.scala 356:19] - wire tlu_io_timer_int; // @[el2_dec.scala 356:19] - wire tlu_io_soft_int; // @[el2_dec.scala 356:19] - wire tlu_io_o_cpu_halt_status; // @[el2_dec.scala 356:19] - wire tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 356:19] - wire tlu_io_o_cpu_run_ack; // @[el2_dec.scala 356:19] - wire tlu_io_o_debug_mode_status; // @[el2_dec.scala 356:19] - wire [27:0] tlu_io_core_id; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_debug_halt_req; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_debug_run_req; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_reset_run_req; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 356:19] - wire tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 356:19] - wire tlu_io_debug_brkpt_status; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 356:19] - wire [3:0] tlu_io_dec_tlu_meipt; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_csr_legal_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 356:19] - wire [1:0] tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 356:19] - wire [30:0] tlu_io_dec_tlu_flush_path_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_i0_valid_wb1; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_int_valid_wb1; // @[el2_dec.scala 356:19] - wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 356:19] - wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 356:19] - wire [2:0] tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 356:19] - wire tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 356:19] - wire dec_trigger_io_trigger_pkt_any_0_select; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_0_m; // @[el2_dec.scala 357:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_1_select; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_1_m; // @[el2_dec.scala 357:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_2_select; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_2_m; // @[el2_dec.scala 357:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_3_select; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 357:27] - wire dec_trigger_io_trigger_pkt_any_3_m; // @[el2_dec.scala 357:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 357:27] - wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[el2_dec.scala 357:27] - wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 357:27] - wire _T_1 = tlu_io_dec_tlu_i0_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 709:98] - el2_dec_ib_ctl instbuff ( // @[el2_dec.scala 353:24] + wire instbuff_io_dbg_cmd_valid; // @[el2_dec.scala 285:24] + wire instbuff_io_dbg_cmd_write; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 285:24] + wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_valid; // @[el2_dec.scala 285:24] + wire [11:0] instbuff_io_i0_brp_toffset; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_i0_brp_hist; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_br_error; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_br_start_error; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_i0_brp_prett; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_way; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_ret; // @[el2_dec.scala 285:24] + wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 285:24] + wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 285:24] + wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_pc4; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_valid; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_icaf; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_ifu_i0_icaf_type; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_icaf_f1; // @[el2_dec.scala 285:24] + wire instbuff_io_ifu_i0_dbecc; // @[el2_dec.scala 285:24] + wire [31:0] instbuff_io_ifu_i0_instr; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_ifu_i0_pc; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 285:24] + wire [31:0] instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 285:24] + wire [11:0] instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 285:24] + wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 285:24] + wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 285:24] + wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 285:24] + wire decode_clock; // @[el2_dec.scala 286:22] + wire decode_reset; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_extint; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_force_halt; // @[el2_dec.scala 286:22] + wire decode_io_dec_extint_stall; // @[el2_dec.scala 286:22] + wire [15:0] decode_io_ifu_i0_cinst; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_i0_pc_wb1; // @[el2_dec.scala 286:22] + wire decode_io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 286:22] + wire decode_io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 286:22] + wire decode_io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 286:22] + wire decode_io_lsu_nonblock_load_data_error; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_lsu_nonblock_load_data; // @[el2_dec.scala 286:22] + wire [3:0] decode_io_dec_i0_trigger_match_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 286:22] + wire [3:0] decode_io_lsu_trigger_match_m; // @[el2_dec.scala 286:22] + wire decode_io_lsu_pmu_misaligned_m; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_debug_stall; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_debug_fence_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dbg_cmd_wrdata; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_icaf_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_valid; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_i0_brp_toffset; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_brp_hist; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_br_error; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_i0_brp_prett; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_way; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_ret; // @[el2_dec.scala 286:22] + wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 286:22] + wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 286:22] + wire decode_io_lsu_idle_any; // @[el2_dec.scala 286:22] + wire decode_io_lsu_load_stall_any; // @[el2_dec.scala 286:22] + wire decode_io_lsu_store_stall_any; // @[el2_dec.scala 286:22] + wire decode_io_dma_dccm_stall_any; // @[el2_dec.scala 286:22] + wire decode_io_exu_div_wren; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_presync_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_postsync_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_pc4_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_csr_rddata_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_legal_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_exu_csr_rs1_x; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_lsu_result_m; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_lsu_result_corr_r; // @[el2_dec.scala 286:22] + wire decode_io_exu_flush_final; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_exu_i0_pc_x; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_instr_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_ib0_valid_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_exu_i0_result_x; // @[el2_dec.scala 286:22] + wire decode_io_free_clk; // @[el2_dec.scala 286:22] + wire decode_io_active_clk; // @[el2_dec.scala 286:22] + wire decode_io_clk_override; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_i0_rs1_d; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_i0_rs2_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_immed_d; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_i0_br_immed_d; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_land; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_lor; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_lxor; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_sll; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_srl; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_sra; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_beq; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_bne; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_blt; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_bge; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_add; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_sub; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_slt; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_unsign; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_jal; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_predict_t; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_predict_nt; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_csr_write; // @[el2_dec.scala 286:22] + wire decode_io_i0_ap_csr_imm; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_decode_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_i0_waddr_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_wen_r; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_i0_wdata_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_select_pc_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_valid; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_by; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_half; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_word; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_load; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_store; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 286:22] + wire decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 286:22] + wire decode_io_mul_p_valid; // @[el2_dec.scala 286:22] + wire decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 286:22] + wire decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 286:22] + wire decode_io_mul_p_bits_low; // @[el2_dec.scala 286:22] + wire decode_io_div_p_valid; // @[el2_dec.scala 286:22] + wire decode_io_div_p_bits_unsign; // @[el2_dec.scala 286:22] + wire decode_io_div_p_bits_rem; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_div_waddr_wb; // @[el2_dec.scala 286:22] + wire decode_io_dec_div_cancel; // @[el2_dec.scala 286:22] + wire decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_lsu_offset_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_ren_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_wen_r; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 286:22] + wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 286:22] + wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 286:22] + wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 286:22] + wire [31:0] decode_io_dec_illegal_inst; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_pred_correct_npc_x; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 286:22] + wire [7:0] decode_io_i0_predict_fghr_d; // @[el2_dec.scala 286:22] + wire [7:0] decode_io_i0_predict_index_d; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_i0_predict_btag_d; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_data_en; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_ctl_en; // @[el2_dec.scala 286:22] + wire decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 286:22] + wire decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 286:22] + wire decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 286:22] + wire decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 286:22] + wire decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 286:22] + wire [4:0] decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 286:22] + wire decode_io_dec_pause_state; // @[el2_dec.scala 286:22] + wire decode_io_dec_pause_state_cg; // @[el2_dec.scala 286:22] + wire decode_io_dec_div_active; // @[el2_dec.scala 286:22] + wire decode_io_scan_mode; // @[el2_dec.scala 286:22] + wire gpr_clock; // @[el2_dec.scala 287:19] + wire gpr_reset; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_raddr0; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_raddr1; // @[el2_dec.scala 287:19] + wire gpr_io_wen0; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_waddr0; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_wd0; // @[el2_dec.scala 287:19] + wire gpr_io_wen1; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_waddr1; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_wd1; // @[el2_dec.scala 287:19] + wire gpr_io_wen2; // @[el2_dec.scala 287:19] + wire [4:0] gpr_io_waddr2; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_wd2; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_rd0; // @[el2_dec.scala 287:19] + wire [31:0] gpr_io_rd1; // @[el2_dec.scala 287:19] + wire gpr_io_scan_mode; // @[el2_dec.scala 287:19] + wire tlu_clock; // @[el2_dec.scala 288:19] + wire tlu_reset; // @[el2_dec.scala 288:19] + wire tlu_io_active_clk; // @[el2_dec.scala 288:19] + wire tlu_io_free_clk; // @[el2_dec.scala 288:19] + wire tlu_io_scan_mode; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_rst_vec; // @[el2_dec.scala 288:19] + wire tlu_io_nmi_int; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_nmi_vec; // @[el2_dec.scala 288:19] + wire tlu_io_i_cpu_halt_req; // @[el2_dec.scala 288:19] + wire tlu_io_i_cpu_run_req; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_fastint_stall_any; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_instr_aligned; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_fetch_stall; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_ic_miss; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_ic_hit; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_bus_error; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_bus_busy; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_pmu_bus_trxn; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pmu_instr_decoded; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pmu_decode_stall; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pmu_presync_stall; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pmu_postsync_stall; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_store_stall_any; // @[el2_dec.scala 288:19] + wire tlu_io_dma_dccm_stall_any; // @[el2_dec.scala 288:19] + wire tlu_io_dma_iccm_stall_any; // @[el2_dec.scala 288:19] + wire tlu_io_exu_pmu_i0_br_misp; // @[el2_dec.scala 288:19] + wire tlu_io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 288:19] + wire tlu_io_exu_pmu_i0_pc4; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_bus_trxn; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_bus_error; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_bus_busy; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_load_external_m; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_pmu_store_external_m; // @[el2_dec.scala 288:19] + wire tlu_io_dma_pmu_dccm_read; // @[el2_dec.scala 288:19] + wire tlu_io_dma_pmu_dccm_write; // @[el2_dec.scala 288:19] + wire tlu_io_dma_pmu_any_read; // @[el2_dec.scala 288:19] + wire tlu_io_dma_pmu_any_write; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_lsu_fir_addr; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_lsu_fir_error; // @[el2_dec.scala 288:19] + wire tlu_io_iccm_dma_sb_error; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_valid; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_single_ecc_error_incr; // @[el2_dec.scala 288:19] + wire tlu_io_dec_pause_state; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_imprecise_error_store_any; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_imprecise_error_load_any; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_wen_unq_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_any_unq_d; // @[el2_dec.scala 288:19] + wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_wen_r; // @[el2_dec.scala 288:19] + wire [11:0] tlu_io_dec_csr_wraddr_r; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_csr_wrdata_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_stall_int_ff; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_exu_npc_r; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_illegal_inst; // @[el2_dec.scala 288:19] + wire tlu_io_dec_i0_decode_d; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_exu_i0_br_hist_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_error_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_start_error_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_valid_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_mp_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_middle_r; // @[el2_dec.scala 288:19] + wire tlu_io_exu_i0_br_way_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 288:19] + wire tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 288:19] + wire [29:0] tlu_io_dec_tlu_meihap; // @[el2_dec.scala 288:19] + wire tlu_io_dbg_halt_req; // @[el2_dec.scala 288:19] + wire tlu_io_dbg_resume_req; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_miss_state_idle; // @[el2_dec.scala 288:19] + wire tlu_io_lsu_idle_any; // @[el2_dec.scala 288:19] + wire tlu_io_dec_div_active; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_ic_error_start; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 288:19] + wire [70:0] tlu_io_ifu_ic_debug_rd_data; // @[el2_dec.scala 288:19] + wire tlu_io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 288:19] + wire [70:0] tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 288:19] + wire [16:0] tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 288:19] + wire [7:0] tlu_io_pic_claimid; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_pic_pl; // @[el2_dec.scala 288:19] + wire tlu_io_mhwakeup; // @[el2_dec.scala 288:19] + wire tlu_io_mexintpend; // @[el2_dec.scala 288:19] + wire tlu_io_timer_int; // @[el2_dec.scala 288:19] + wire tlu_io_soft_int; // @[el2_dec.scala 288:19] + wire tlu_io_o_cpu_halt_status; // @[el2_dec.scala 288:19] + wire tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 288:19] + wire tlu_io_o_cpu_run_ack; // @[el2_dec.scala 288:19] + wire tlu_io_o_debug_mode_status; // @[el2_dec.scala 288:19] + wire [27:0] tlu_io_core_id; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_debug_halt_req; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_debug_run_req; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_reset_run_req; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 288:19] + wire tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 288:19] + wire tlu_io_debug_brkpt_status; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_dec_tlu_meipt; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_csr_legal_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 288:19] + wire [30:0] tlu_io_dec_tlu_flush_path_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_i0_valid_wb1; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_int_valid_wb1; // @[el2_dec.scala 288:19] + wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 288:19] + wire [2:0] tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 288:19] + wire dec_trigger_io_trigger_pkt_any_0_select; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_0_m; // @[el2_dec.scala 289:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_select; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_m; // @[el2_dec.scala 289:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_select; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_m; // @[el2_dec.scala 289:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_select; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_m; // @[el2_dec.scala 289:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 289:27] + wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[el2_dec.scala 289:27] + wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 289:27] + wire _T_1 = tlu_io_dec_tlu_i0_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[el2_dec.scala 592:98] + el2_dec_ib_ctl instbuff ( // @[el2_dec.scala 285:24] .io_dbg_cmd_valid(instbuff_io_dbg_cmd_valid), .io_dbg_cmd_write(instbuff_io_dbg_cmd_write), .io_dbg_cmd_type(instbuff_io_dbg_cmd_type), .io_dbg_cmd_addr(instbuff_io_dbg_cmd_addr), .io_i0_brp_valid(instbuff_io_i0_brp_valid), - .io_i0_brp_bits_toffset(instbuff_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(instbuff_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(instbuff_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(instbuff_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_prett(instbuff_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(instbuff_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(instbuff_io_i0_brp_bits_ret), + .io_i0_brp_toffset(instbuff_io_i0_brp_toffset), + .io_i0_brp_hist(instbuff_io_i0_brp_hist), + .io_i0_brp_br_error(instbuff_io_i0_brp_br_error), + .io_i0_brp_br_start_error(instbuff_io_i0_brp_br_start_error), + .io_i0_brp_prett(instbuff_io_i0_brp_prett), + .io_i0_brp_way(instbuff_io_i0_brp_way), + .io_i0_brp_ret(instbuff_io_i0_brp_ret), .io_ifu_i0_bp_index(instbuff_io_ifu_i0_bp_index), .io_ifu_i0_bp_fghr(instbuff_io_ifu_i0_bp_fghr), .io_ifu_i0_bp_btag(instbuff_io_ifu_i0_bp_btag), + .io_ifu_i0_pc4(instbuff_io_ifu_i0_pc4), .io_ifu_i0_valid(instbuff_io_ifu_i0_valid), .io_ifu_i0_icaf(instbuff_io_ifu_i0_icaf), .io_ifu_i0_icaf_type(instbuff_io_ifu_i0_icaf_type), @@ -58433,14 +58536,15 @@ module el2_dec( .io_dec_i0_icaf_type_d(instbuff_io_dec_i0_icaf_type_d), .io_dec_i0_instr_d(instbuff_io_dec_i0_instr_d), .io_dec_i0_pc_d(instbuff_io_dec_i0_pc_d), + .io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d), .io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid), - .io_dec_i0_brp_bits_toffset(instbuff_io_dec_i0_brp_bits_toffset), - .io_dec_i0_brp_bits_hist(instbuff_io_dec_i0_brp_bits_hist), - .io_dec_i0_brp_bits_br_error(instbuff_io_dec_i0_brp_bits_br_error), - .io_dec_i0_brp_bits_br_start_error(instbuff_io_dec_i0_brp_bits_br_start_error), - .io_dec_i0_brp_bits_prett(instbuff_io_dec_i0_brp_bits_prett), - .io_dec_i0_brp_bits_way(instbuff_io_dec_i0_brp_bits_way), - .io_dec_i0_brp_bits_ret(instbuff_io_dec_i0_brp_bits_ret), + .io_dec_i0_brp_toffset(instbuff_io_dec_i0_brp_toffset), + .io_dec_i0_brp_hist(instbuff_io_dec_i0_brp_hist), + .io_dec_i0_brp_br_error(instbuff_io_dec_i0_brp_br_error), + .io_dec_i0_brp_br_start_error(instbuff_io_dec_i0_brp_br_start_error), + .io_dec_i0_brp_prett(instbuff_io_dec_i0_brp_prett), + .io_dec_i0_brp_way(instbuff_io_dec_i0_brp_way), + .io_dec_i0_brp_ret(instbuff_io_dec_i0_brp_ret), .io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index), .io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr), .io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag), @@ -58450,7 +58554,7 @@ module el2_dec( .io_dec_debug_wdata_rs1_d(instbuff_io_dec_debug_wdata_rs1_d), .io_dec_debug_fence_d(instbuff_io_dec_debug_fence_d) ); - el2_dec_decode_ctl decode ( // @[el2_dec.scala 354:22] + el2_dec_decode_ctl decode ( // @[el2_dec.scala 286:22] .clock(decode_clock), .reset(decode_reset), .io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint), @@ -58481,13 +58585,13 @@ module el2_dec( .io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d), .io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d), .io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid), - .io_dec_i0_brp_bits_toffset(decode_io_dec_i0_brp_bits_toffset), - .io_dec_i0_brp_bits_hist(decode_io_dec_i0_brp_bits_hist), - .io_dec_i0_brp_bits_br_error(decode_io_dec_i0_brp_bits_br_error), - .io_dec_i0_brp_bits_br_start_error(decode_io_dec_i0_brp_bits_br_start_error), - .io_dec_i0_brp_bits_prett(decode_io_dec_i0_brp_bits_prett), - .io_dec_i0_brp_bits_way(decode_io_dec_i0_brp_bits_way), - .io_dec_i0_brp_bits_ret(decode_io_dec_i0_brp_bits_ret), + .io_dec_i0_brp_toffset(decode_io_dec_i0_brp_toffset), + .io_dec_i0_brp_hist(decode_io_dec_i0_brp_hist), + .io_dec_i0_brp_br_error(decode_io_dec_i0_brp_br_error), + .io_dec_i0_brp_br_start_error(decode_io_dec_i0_brp_br_start_error), + .io_dec_i0_brp_prett(decode_io_dec_i0_brp_prett), + .io_dec_i0_brp_way(decode_io_dec_i0_brp_way), + .io_dec_i0_brp_ret(decode_io_dec_i0_brp_ret), .io_dec_i0_bp_index(decode_io_dec_i0_bp_index), .io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr), .io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag), @@ -58510,6 +58614,7 @@ module el2_dec( .io_lsu_result_m(decode_io_lsu_result_m), .io_lsu_result_corr_r(decode_io_lsu_result_corr_r), .io_exu_flush_final(decode_io_exu_flush_final), + .io_exu_i0_pc_x(decode_io_exu_i0_pc_x), .io_dec_i0_instr_d(decode_io_dec_i0_instr_d), .io_dec_ib0_valid_d(decode_io_dec_ib0_valid_d), .io_exu_i0_result_x(decode_io_exu_i0_result_x), @@ -58548,6 +58653,7 @@ module el2_dec( .io_dec_i0_waddr_r(decode_io_dec_i0_waddr_r), .io_dec_i0_wen_r(decode_io_dec_i0_wen_r), .io_dec_i0_wdata_r(decode_io_dec_i0_wdata_r), + .io_dec_i0_select_pc_d(decode_io_dec_i0_select_pc_d), .io_dec_i0_rs1_bypass_en_d(decode_io_dec_i0_rs1_bypass_en_d), .io_dec_i0_rs2_bypass_en_d(decode_io_dec_i0_rs2_bypass_en_d), .io_lsu_p_valid(decode_io_lsu_p_valid), @@ -58620,7 +58726,7 @@ module el2_dec( .io_dec_div_active(decode_io_dec_div_active), .io_scan_mode(decode_io_scan_mode) ); - el2_dec_gpr_ctl gpr ( // @[el2_dec.scala 355:19] + el2_dec_gpr_ctl gpr ( // @[el2_dec.scala 287:19] .clock(gpr_clock), .reset(gpr_reset), .io_raddr0(gpr_io_raddr0), @@ -58638,7 +58744,7 @@ module el2_dec( .io_rd1(gpr_io_rd1), .io_scan_mode(gpr_io_scan_mode) ); - el2_dec_tlu_ctl tlu ( // @[el2_dec.scala 356:19] + el2_dec_tlu_ctl tlu ( // @[el2_dec.scala 288:19] .clock(tlu_clock), .reset(tlu_reset), .io_active_clk(tlu_io_active_clk), @@ -58700,6 +58806,7 @@ module el2_dec( .io_dec_csr_stall_int_ff(tlu_io_dec_csr_stall_int_ff), .io_dec_tlu_i0_valid_r(tlu_io_dec_tlu_i0_valid_r), .io_exu_npc_r(tlu_io_exu_npc_r), + .io_dec_tlu_i0_pc_r(tlu_io_dec_tlu_i0_pc_r), .io_dec_tlu_packet_r_legal(tlu_io_dec_tlu_packet_r_legal), .io_dec_tlu_packet_r_icaf(tlu_io_dec_tlu_packet_r_icaf), .io_dec_tlu_packet_r_icaf_f1(tlu_io_dec_tlu_packet_r_icaf_f1), @@ -58737,28 +58844,28 @@ module el2_dec( .io_lsu_idle_any(tlu_io_lsu_idle_any), .io_dec_div_active(tlu_io_dec_div_active), .io_trigger_pkt_any_0_select(tlu_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(tlu_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(tlu_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(tlu_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(tlu_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_execute(tlu_io_trigger_pkt_any_0_execute), .io_trigger_pkt_any_0_m(tlu_io_trigger_pkt_any_0_m), .io_trigger_pkt_any_0_tdata2(tlu_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(tlu_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(tlu_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(tlu_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(tlu_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(tlu_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_execute(tlu_io_trigger_pkt_any_1_execute), .io_trigger_pkt_any_1_m(tlu_io_trigger_pkt_any_1_m), .io_trigger_pkt_any_1_tdata2(tlu_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(tlu_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(tlu_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(tlu_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(tlu_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(tlu_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_execute(tlu_io_trigger_pkt_any_2_execute), .io_trigger_pkt_any_2_m(tlu_io_trigger_pkt_any_2_m), .io_trigger_pkt_any_2_tdata2(tlu_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(tlu_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(tlu_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(tlu_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(tlu_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(tlu_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_execute(tlu_io_trigger_pkt_any_3_execute), @@ -58794,11 +58901,11 @@ module el2_dec( .io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d), .io_dec_csr_legal_d(tlu_io_dec_csr_legal_d), .io_dec_tlu_br0_r_pkt_valid(tlu_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(tlu_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(tlu_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(tlu_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(tlu_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(tlu_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(tlu_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(tlu_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(tlu_io_dec_tlu_br0_r_pkt_middle), .io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb), .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb), .io_dec_tlu_i0_commit_cmt(tlu_io_dec_tlu_i0_commit_cmt), @@ -58835,400 +58942,405 @@ module el2_dec( .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override) ); - el2_dec_trigger dec_trigger ( // @[el2_dec.scala 357:27] + el2_dec_trigger dec_trigger ( // @[el2_dec.scala 289:27] .io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(dec_trigger_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(dec_trigger_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute), .io_trigger_pkt_any_0_m(dec_trigger_io_trigger_pkt_any_0_m), .io_trigger_pkt_any_0_tdata2(dec_trigger_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(dec_trigger_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(dec_trigger_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(dec_trigger_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_execute(dec_trigger_io_trigger_pkt_any_1_execute), .io_trigger_pkt_any_1_m(dec_trigger_io_trigger_pkt_any_1_m), .io_trigger_pkt_any_1_tdata2(dec_trigger_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(dec_trigger_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(dec_trigger_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(dec_trigger_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_execute(dec_trigger_io_trigger_pkt_any_2_execute), .io_trigger_pkt_any_2_m(dec_trigger_io_trigger_pkt_any_2_m), .io_trigger_pkt_any_2_tdata2(dec_trigger_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(dec_trigger_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(dec_trigger_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(dec_trigger_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_execute(dec_trigger_io_trigger_pkt_any_3_execute), .io_trigger_pkt_any_3_m(dec_trigger_io_trigger_pkt_any_3_m), .io_trigger_pkt_any_3_tdata2(dec_trigger_io_trigger_pkt_any_3_tdata2), .io_dec_i0_pc_d(dec_trigger_io_dec_i0_pc_d), .io_dec_i0_trigger_match_d(dec_trigger_io_dec_i0_trigger_match_d) ); - assign io_dec_extint_stall = decode_io_dec_extint_stall; // @[el2_dec.scala 469:40] - assign io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 479:40] - assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[el2_dec.scala 522:40] - assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[el2_dec.scala 655:29] - assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 656:29] - assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[el2_dec.scala 657:29] - assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[el2_dec.scala 658:29] - assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 659:29] - assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 660:29] - assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[el2_dec.scala 661:29] - assign io_dec_tlu_meicurpl = tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 662:29] - assign io_dec_tlu_meipt = tlu_io_dec_tlu_meipt; // @[el2_dec.scala 663:29] - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 654:29] - assign io_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 654:29] - assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 654:29] - assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 654:29] - assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 643:28] - assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 644:28] - assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 645:28] - assign io_dec_tlu_flush_noredir_r = tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 647:34] - assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 648:34] - assign io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 649:34] - assign io_dec_tlu_flush_err_r = tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 650:34] - assign io_dec_tlu_meihap = {{2'd0}, tlu_io_dec_tlu_meihap}; // @[el2_dec.scala 652:29] - assign io_dec_debug_wdata_rs1_d = instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 393:38] - assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 717:21] - assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 641:28] - assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 642:28] - assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 653:29] - assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 653:29] - assign io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 679:29] - assign io_dec_i0_rs1_en_d = decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 472:40] - assign io_dec_i0_rs2_en_d = decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 473:40] - assign io_gpr_i0_rs1_d = gpr_io_rd0; // @[el2_dec.scala 545:19] - assign io_gpr_i0_rs2_d = gpr_io_rd1; // @[el2_dec.scala 546:19] - assign io_dec_i0_immed_d = decode_io_dec_i0_immed_d; // @[el2_dec.scala 476:40] - assign io_dec_i0_br_immed_d = {{1'd0}, decode_io_dec_i0_br_immed_d}; // @[el2_dec.scala 477:40] - assign io_i0_ap_land = decode_io_i0_ap_land; // @[el2_dec.scala 478:40] - assign io_i0_ap_lor = decode_io_i0_ap_lor; // @[el2_dec.scala 478:40] - assign io_i0_ap_lxor = decode_io_i0_ap_lxor; // @[el2_dec.scala 478:40] - assign io_i0_ap_sll = decode_io_i0_ap_sll; // @[el2_dec.scala 478:40] - assign io_i0_ap_srl = decode_io_i0_ap_srl; // @[el2_dec.scala 478:40] - assign io_i0_ap_sra = decode_io_i0_ap_sra; // @[el2_dec.scala 478:40] - assign io_i0_ap_beq = decode_io_i0_ap_beq; // @[el2_dec.scala 478:40] - assign io_i0_ap_bne = decode_io_i0_ap_bne; // @[el2_dec.scala 478:40] - assign io_i0_ap_blt = decode_io_i0_ap_blt; // @[el2_dec.scala 478:40] - assign io_i0_ap_bge = decode_io_i0_ap_bge; // @[el2_dec.scala 478:40] - assign io_i0_ap_add = decode_io_i0_ap_add; // @[el2_dec.scala 478:40] - assign io_i0_ap_sub = decode_io_i0_ap_sub; // @[el2_dec.scala 478:40] - assign io_i0_ap_slt = decode_io_i0_ap_slt; // @[el2_dec.scala 478:40] - assign io_i0_ap_unsign = decode_io_i0_ap_unsign; // @[el2_dec.scala 478:40] - assign io_i0_ap_jal = decode_io_i0_ap_jal; // @[el2_dec.scala 478:40] - assign io_i0_ap_predict_t = decode_io_i0_ap_predict_t; // @[el2_dec.scala 478:40] - assign io_i0_ap_predict_nt = decode_io_i0_ap_predict_nt; // @[el2_dec.scala 478:40] - assign io_i0_ap_csr_write = decode_io_i0_ap_csr_write; // @[el2_dec.scala 478:40] - assign io_i0_ap_csr_imm = decode_io_i0_ap_csr_imm; // @[el2_dec.scala 478:40] - assign io_dec_i0_alu_decode_d = decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 480:40] - assign io_dec_i0_rs1_bypass_en_d = decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 487:40] - assign io_dec_i0_rs2_bypass_en_d = decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 488:40] - assign io_dec_i0_rs1_bypass_data_d = decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 481:40] - assign io_dec_i0_rs2_bypass_data_d = decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 482:40] - assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 489:40] - assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 489:40] - assign io_mul_p_valid = decode_io_mul_p_valid; // @[el2_dec.scala 490:40] - assign io_mul_p_bits_rs1_sign = decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 490:40] - assign io_mul_p_bits_rs2_sign = decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 490:40] - assign io_mul_p_bits_low = decode_io_mul_p_bits_low; // @[el2_dec.scala 490:40] - assign io_div_p_valid = decode_io_div_p_valid; // @[el2_dec.scala 491:40] - assign io_div_p_bits_unsign = decode_io_div_p_bits_unsign; // @[el2_dec.scala 491:40] - assign io_div_p_bits_rem = decode_io_div_p_bits_rem; // @[el2_dec.scala 491:40] - assign io_dec_div_cancel = decode_io_dec_div_cancel; // @[el2_dec.scala 493:40] - assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[el2_dec.scala 495:40] - assign io_dec_csr_ren_d = decode_io_dec_csr_ren_d; // @[el2_dec.scala 496:40] - assign io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 671:34] - assign io_dec_tlu_flush_path_r = {{1'd0}, tlu_io_dec_tlu_flush_path_r}; // @[el2_dec.scala 672:34] - assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 670:34] - assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 673:34] - assign io_pred_correct_npc_x = {{1'd0}, decode_io_pred_correct_npc_x}; // @[el2_dec.scala 508:40] - assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_hist = tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_way = tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 666:42] - assign io_dec_tlu_br0_r_pkt_bits_middle = tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 666:42] - assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 680:29] - assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 681:29] - assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 682:29] - assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 683:29] - assign io_dec_i0_predict_p_d_valid = decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_pc4 = decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_hist = decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_toffset = decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_br_error = decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_br_start_error = decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_prett = decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_pcall = decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_pret = decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_pja = decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 509:40] - assign io_dec_i0_predict_p_d_bits_way = decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 509:40] - assign io_i0_predict_fghr_d = decode_io_i0_predict_fghr_d; // @[el2_dec.scala 510:40] - assign io_i0_predict_index_d = {{1'd0}, decode_io_i0_predict_index_d}; // @[el2_dec.scala 511:40] - assign io_i0_predict_btag_d = decode_io_i0_predict_btag_d; // @[el2_dec.scala 512:40] - assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 494:40] - assign io_dec_tlu_mrac_ff = tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 678:29] - assign io_dec_data_en = decode_io_dec_data_en; // @[el2_dec.scala 513:40] - assign io_dec_ctl_en = decode_io_dec_ctl_en; // @[el2_dec.scala 514:40] - assign io_rv_trace_pkt_rv_i_valid_ip = {tlu_io_dec_tlu_int_valid_wb1,_T_1}; // @[el2_dec.scala 709:33] - assign io_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 707:32] - assign io_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb1,1'h0}; // @[el2_dec.scala 708:35] - assign io_rv_trace_pkt_rv_i_exception_ip = {tlu_io_dec_tlu_int_valid_wb1,tlu_io_dec_tlu_i0_exc_valid_wb1}; // @[el2_dec.scala 710:37] - assign io_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 711:34] - assign io_rv_trace_pkt_rv_i_interrupt_ip = {tlu_io_dec_tlu_int_valid_wb1,1'h0}; // @[el2_dec.scala 712:37] - assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 713:32] - assign io_dec_tlu_external_ldfwd_disable = tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 689:43] - assign io_dec_tlu_sideeffect_posted_disable = tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 690:43] - assign io_dec_tlu_core_ecc_disable = tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 691:43] - assign io_dec_tlu_bpred_disable = tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 692:43] - assign io_dec_tlu_wb_coalescing_disable = tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 693:43] - assign io_dec_tlu_dma_qos_prty = tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 695:35] - assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 696:35] - assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 699:36] - assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 701:36] - assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 702:36] - assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 703:36] - assign io_dec_tlu_i0_commit_cmt = tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 669:34] - assign instbuff_io_dbg_cmd_valid = io_dbg_cmd_valid; // @[el2_dec.scala 364:45] - assign instbuff_io_dbg_cmd_write = io_dbg_cmd_write; // @[el2_dec.scala 365:45] - assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 366:45] - assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 367:45] - assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec.scala 368:55] - assign instbuff_io_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec.scala 368:55] - assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index[7:0]; // @[el2_dec.scala 369:35] - assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 370:35] - assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 371:35] - assign instbuff_io_ifu_i0_valid = io_ifu_i0_valid; // @[el2_dec.scala 373:35] - assign instbuff_io_ifu_i0_icaf = io_ifu_i0_icaf; // @[el2_dec.scala 374:35] - assign instbuff_io_ifu_i0_icaf_type = io_ifu_i0_icaf_type; // @[el2_dec.scala 375:35] - assign instbuff_io_ifu_i0_icaf_f1 = io_ifu_i0_icaf_f1; // @[el2_dec.scala 376:35] - assign instbuff_io_ifu_i0_dbecc = io_ifu_i0_dbecc; // @[el2_dec.scala 377:35] - assign instbuff_io_ifu_i0_instr = io_ifu_i0_instr; // @[el2_dec.scala 378:35] - assign instbuff_io_ifu_i0_pc = io_ifu_i0_pc[30:0]; // @[el2_dec.scala 379:35] + assign io_dec_extint_stall = decode_io_dec_extint_stall; // @[el2_dec.scala 389:40] + assign io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 397:40] + assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[el2_dec.scala 418:40] + assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[el2_dec.scala 548:29] + assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[el2_dec.scala 549:29] + assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[el2_dec.scala 550:29] + assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[el2_dec.scala 551:29] + assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[el2_dec.scala 552:29] + assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[el2_dec.scala 553:29] + assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[el2_dec.scala 554:29] + assign io_dec_tlu_meicurpl = tlu_io_dec_tlu_meicurpl; // @[el2_dec.scala 555:29] + assign io_dec_tlu_meipt = tlu_io_dec_tlu_meipt; // @[el2_dec.scala 556:29] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_dec.scala 547:29] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_dec.scala 547:29] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_dec.scala 547:29] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec.scala 547:29] + assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[el2_dec.scala 538:28] + assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[el2_dec.scala 539:28] + assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[el2_dec.scala 540:28] + assign io_dec_tlu_flush_noredir_r = tlu_io_dec_tlu_flush_noredir_r; // @[el2_dec.scala 541:34] + assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[el2_dec.scala 542:34] + assign io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 543:34] + assign io_dec_tlu_flush_err_r = tlu_io_dec_tlu_flush_err_r; // @[el2_dec.scala 544:34] + assign io_dec_tlu_meihap = tlu_io_dec_tlu_meihap; // @[el2_dec.scala 545:29] + assign io_dec_debug_wdata_rs1_d = instbuff_io_dec_debug_wdata_rs1_d; // @[el2_dec.scala 314:38] + assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 600:21] + assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 536:28] + assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 537:28] + assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 546:29] + assign io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 564:29] + assign io_dec_i0_rs1_en_d = decode_io_dec_i0_rs1_en_d; // @[el2_dec.scala 392:40] + assign io_dec_i0_rs2_en_d = decode_io_dec_i0_rs2_en_d; // @[el2_dec.scala 393:40] + assign io_gpr_i0_rs1_d = gpr_io_rd0; // @[el2_dec.scala 440:19] + assign io_gpr_i0_rs2_d = gpr_io_rd1; // @[el2_dec.scala 441:19] + assign io_dec_i0_immed_d = decode_io_dec_i0_immed_d; // @[el2_dec.scala 394:40] + assign io_dec_i0_br_immed_d = decode_io_dec_i0_br_immed_d; // @[el2_dec.scala 395:40] + assign io_i0_ap_land = decode_io_i0_ap_land; // @[el2_dec.scala 396:40] + assign io_i0_ap_lor = decode_io_i0_ap_lor; // @[el2_dec.scala 396:40] + assign io_i0_ap_lxor = decode_io_i0_ap_lxor; // @[el2_dec.scala 396:40] + assign io_i0_ap_sll = decode_io_i0_ap_sll; // @[el2_dec.scala 396:40] + assign io_i0_ap_srl = decode_io_i0_ap_srl; // @[el2_dec.scala 396:40] + assign io_i0_ap_sra = decode_io_i0_ap_sra; // @[el2_dec.scala 396:40] + assign io_i0_ap_beq = decode_io_i0_ap_beq; // @[el2_dec.scala 396:40] + assign io_i0_ap_bne = decode_io_i0_ap_bne; // @[el2_dec.scala 396:40] + assign io_i0_ap_blt = decode_io_i0_ap_blt; // @[el2_dec.scala 396:40] + assign io_i0_ap_bge = decode_io_i0_ap_bge; // @[el2_dec.scala 396:40] + assign io_i0_ap_add = decode_io_i0_ap_add; // @[el2_dec.scala 396:40] + assign io_i0_ap_sub = decode_io_i0_ap_sub; // @[el2_dec.scala 396:40] + assign io_i0_ap_slt = decode_io_i0_ap_slt; // @[el2_dec.scala 396:40] + assign io_i0_ap_unsign = decode_io_i0_ap_unsign; // @[el2_dec.scala 396:40] + assign io_i0_ap_jal = decode_io_i0_ap_jal; // @[el2_dec.scala 396:40] + assign io_i0_ap_predict_t = decode_io_i0_ap_predict_t; // @[el2_dec.scala 396:40] + assign io_i0_ap_predict_nt = decode_io_i0_ap_predict_nt; // @[el2_dec.scala 396:40] + assign io_i0_ap_csr_write = decode_io_i0_ap_csr_write; // @[el2_dec.scala 396:40] + assign io_i0_ap_csr_imm = decode_io_i0_ap_csr_imm; // @[el2_dec.scala 396:40] + assign io_dec_i0_alu_decode_d = decode_io_dec_i0_alu_decode_d; // @[el2_dec.scala 398:40] + assign io_dec_i0_select_pc_d = decode_io_dec_i0_select_pc_d; // @[el2_dec.scala 401:40] + assign io_dec_i0_pc_d = instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 291:18] + assign io_dec_i0_rs1_bypass_en_d = decode_io_dec_i0_rs1_bypass_en_d; // @[el2_dec.scala 402:40] + assign io_dec_i0_rs2_bypass_en_d = decode_io_dec_i0_rs2_bypass_en_d; // @[el2_dec.scala 403:40] + assign io_dec_i0_rs1_bypass_data_d = decode_io_dec_i0_rs1_bypass_data_d; // @[el2_dec.scala 399:40] + assign io_dec_i0_rs2_bypass_data_d = decode_io_dec_i0_rs2_bypass_data_d; // @[el2_dec.scala 400:40] + assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[el2_dec.scala 404:40] + assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_dec.scala 404:40] + assign io_mul_p_valid = decode_io_mul_p_valid; // @[el2_dec.scala 405:40] + assign io_mul_p_bits_rs1_sign = decode_io_mul_p_bits_rs1_sign; // @[el2_dec.scala 405:40] + assign io_mul_p_bits_rs2_sign = decode_io_mul_p_bits_rs2_sign; // @[el2_dec.scala 405:40] + assign io_mul_p_bits_low = decode_io_mul_p_bits_low; // @[el2_dec.scala 405:40] + assign io_div_p_valid = decode_io_div_p_valid; // @[el2_dec.scala 406:40] + assign io_div_p_bits_unsign = decode_io_div_p_bits_unsign; // @[el2_dec.scala 406:40] + assign io_div_p_bits_rem = decode_io_div_p_bits_rem; // @[el2_dec.scala 406:40] + assign io_dec_div_cancel = decode_io_dec_div_cancel; // @[el2_dec.scala 407:40] + assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[el2_dec.scala 409:40] + assign io_dec_csr_ren_d = decode_io_dec_csr_ren_d; // @[el2_dec.scala 410:40] + assign io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 560:34] + assign io_dec_tlu_flush_path_r = tlu_io_dec_tlu_flush_path_r; // @[el2_dec.scala 561:34] + assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 559:34] + assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 562:34] + assign io_pred_correct_npc_x = decode_io_pred_correct_npc_x; // @[el2_dec.scala 411:40] + assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_hist = tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_br_error = tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_br_start_error = tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_way = tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_middle = tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 557:42] + assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 565:29] + assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 566:29] + assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 567:29] + assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[el2_dec.scala 568:29] + assign io_dec_i0_predict_p_d_valid = decode_io_dec_i0_predict_p_d_valid; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_pc4 = decode_io_dec_i0_predict_p_d_bits_pc4; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_hist = decode_io_dec_i0_predict_p_d_bits_hist; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_toffset = decode_io_dec_i0_predict_p_d_bits_toffset; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_br_error = decode_io_dec_i0_predict_p_d_bits_br_error; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_br_start_error = decode_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_prett = decode_io_dec_i0_predict_p_d_bits_prett; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_pcall = decode_io_dec_i0_predict_p_d_bits_pcall; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_pret = decode_io_dec_i0_predict_p_d_bits_pret; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_pja = decode_io_dec_i0_predict_p_d_bits_pja; // @[el2_dec.scala 412:40] + assign io_dec_i0_predict_p_d_bits_way = decode_io_dec_i0_predict_p_d_bits_way; // @[el2_dec.scala 412:40] + assign io_i0_predict_fghr_d = decode_io_i0_predict_fghr_d; // @[el2_dec.scala 413:40] + assign io_i0_predict_index_d = decode_io_i0_predict_index_d; // @[el2_dec.scala 414:40] + assign io_i0_predict_btag_d = decode_io_i0_predict_btag_d; // @[el2_dec.scala 415:40] + assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[el2_dec.scala 408:40] + assign io_dec_tlu_mrac_ff = tlu_io_dec_tlu_mrac_ff; // @[el2_dec.scala 563:29] + assign io_dec_data_en = decode_io_dec_data_en; // @[el2_dec.scala 416:40] + assign io_dec_ctl_en = decode_io_dec_ctl_en; // @[el2_dec.scala 417:40] + assign io_rv_trace_pkt_rv_i_valid_ip = {tlu_io_dec_tlu_int_valid_wb1,_T_1}; // @[el2_dec.scala 592:33] + assign io_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb1; // @[el2_dec.scala 590:32] + assign io_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb1,1'h0}; // @[el2_dec.scala 591:35] + assign io_rv_trace_pkt_rv_i_exception_ip = {tlu_io_dec_tlu_int_valid_wb1,tlu_io_dec_tlu_i0_exc_valid_wb1}; // @[el2_dec.scala 593:37] + assign io_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[el2_dec.scala 594:34] + assign io_rv_trace_pkt_rv_i_interrupt_ip = {tlu_io_dec_tlu_int_valid_wb1,1'h0}; // @[el2_dec.scala 595:37] + assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[el2_dec.scala 596:32] + assign io_dec_tlu_external_ldfwd_disable = tlu_io_dec_tlu_external_ldfwd_disable; // @[el2_dec.scala 574:43] + assign io_dec_tlu_sideeffect_posted_disable = tlu_io_dec_tlu_sideeffect_posted_disable; // @[el2_dec.scala 575:43] + assign io_dec_tlu_core_ecc_disable = tlu_io_dec_tlu_core_ecc_disable; // @[el2_dec.scala 576:43] + assign io_dec_tlu_bpred_disable = tlu_io_dec_tlu_bpred_disable; // @[el2_dec.scala 577:43] + assign io_dec_tlu_wb_coalescing_disable = tlu_io_dec_tlu_wb_coalescing_disable; // @[el2_dec.scala 578:43] + assign io_dec_tlu_dma_qos_prty = tlu_io_dec_tlu_dma_qos_prty; // @[el2_dec.scala 579:35] + assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[el2_dec.scala 580:35] + assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[el2_dec.scala 582:36] + assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[el2_dec.scala 584:36] + assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 585:36] + assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 586:36] + assign io_dec_tlu_i0_commit_cmt = tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 558:34] + assign instbuff_io_dbg_cmd_valid = io_dbg_cmd_valid; // @[el2_dec.scala 297:45] + assign instbuff_io_dbg_cmd_write = io_dbg_cmd_write; // @[el2_dec.scala 298:45] + assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 299:45] + assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 300:45] + assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_hist = io_i0_brp_hist; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_prett = io_i0_brp_prett; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_way = io_i0_brp_way; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_ret = io_i0_brp_ret; // @[el2_dec.scala 301:55] + assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec.scala 302:35] + assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 303:35] + assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 304:35] + assign instbuff_io_ifu_i0_pc4 = io_ifu_i0_pc4; // @[el2_dec.scala 305:35] + assign instbuff_io_ifu_i0_valid = io_ifu_i0_valid; // @[el2_dec.scala 306:35] + assign instbuff_io_ifu_i0_icaf = io_ifu_i0_icaf; // @[el2_dec.scala 307:35] + assign instbuff_io_ifu_i0_icaf_type = io_ifu_i0_icaf_type; // @[el2_dec.scala 308:35] + assign instbuff_io_ifu_i0_icaf_f1 = io_ifu_i0_icaf_f1; // @[el2_dec.scala 309:35] + assign instbuff_io_ifu_i0_dbecc = io_ifu_i0_dbecc; // @[el2_dec.scala 310:35] + assign instbuff_io_ifu_i0_instr = io_ifu_i0_instr; // @[el2_dec.scala 311:35] + assign instbuff_io_ifu_i0_pc = io_ifu_i0_pc; // @[el2_dec.scala 312:35] assign decode_clock = clock; assign decode_reset = reset; - assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 410:48 el2_dec.scala 651:37] - assign decode_io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 411:48] - assign decode_io_ifu_i0_cinst = io_ifu_i0_cinst; // @[el2_dec.scala 412:48] - assign decode_io_lsu_nonblock_load_valid_m = io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 413:48] - assign decode_io_lsu_nonblock_load_tag_m = io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 414:48] - assign decode_io_lsu_nonblock_load_inv_r = io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 415:48] - assign decode_io_lsu_nonblock_load_inv_tag_r = io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 416:48] - assign decode_io_lsu_nonblock_load_data_valid = io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 417:48] - assign decode_io_lsu_nonblock_load_data_error = io_lsu_nonblock_load_data_error; // @[el2_dec.scala 418:48] - assign decode_io_lsu_nonblock_load_data_tag = io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 419:48] - assign decode_io_lsu_nonblock_load_data = io_lsu_nonblock_load_data; // @[el2_dec.scala 420:48] - assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 421:48] - assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 422:48 el2_dec.scala 674:35] - assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 423:48] - assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[el2_dec.scala 424:48] - assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 425:48] - assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 426:48 el2_dec.scala 646:36] - assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 427:48] - assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 394:38 el2_dec.scala 428:48] - assign decode_io_dbg_cmd_wrdata = io_dbg_cmd_wrdata; // @[el2_dec.scala 429:48] - assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 390:38 el2_dec.scala 430:48] - assign decode_io_dec_i0_icaf_f1_d = instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 391:38 el2_dec.scala 431:48] - assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 382:38 el2_dec.scala 432:48] - assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 392:38 el2_dec.scala 433:48] - assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 386:38 el2_dec.scala 434:48] - assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 387:38 el2_dec.scala 435:48] - assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 388:38 el2_dec.scala 436:48] - assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 389:38 el2_dec.scala 437:48] - assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 439:48] - assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[el2_dec.scala 440:48] - assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 441:48] - assign decode_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 442:48] - assign decode_io_exu_div_wren = io_exu_div_wren; // @[el2_dec.scala 443:48] - assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 444:48 el2_dec.scala 667:42] - assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 445:48 el2_dec.scala 668:42] - assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 446:48] - assign decode_io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 447:48] - assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 448:48 el2_dec.scala 675:35] - assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 449:48 el2_dec.scala 676:35] - assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 450:48 el2_dec.scala 677:35] - assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc_d[0]; // @[el2_dec.scala 385:38 el2_dec.scala 451:48] - assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 452:48 el2_dec.scala 664:33] - assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[el2_dec.scala 453:48 el2_dec.scala 665:33] - assign decode_io_exu_csr_rs1_x = io_exu_csr_rs1_x; // @[el2_dec.scala 454:48] - assign decode_io_lsu_result_m = io_lsu_result_m; // @[el2_dec.scala 455:48] - assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[el2_dec.scala 456:48] - assign decode_io_exu_flush_final = io_exu_flush_final; // @[el2_dec.scala 457:48] - assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 383:38 el2_dec.scala 459:48] - assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 381:38 el2_dec.scala 460:48] - assign decode_io_exu_i0_result_x = io_exu_i0_result_x; // @[el2_dec.scala 461:48] - assign decode_io_free_clk = io_free_clk; // @[el2_dec.scala 463:48] - assign decode_io_active_clk = io_active_clk; // @[el2_dec.scala 464:48] - assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 465:48] - assign decode_io_scan_mode = io_scan_mode; // @[el2_dec.scala 467:48] + assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[el2_dec.scala 330:48] + assign decode_io_dec_tlu_force_halt = tlu_io_dec_tlu_force_halt; // @[el2_dec.scala 331:48] + assign decode_io_ifu_i0_cinst = io_ifu_i0_cinst; // @[el2_dec.scala 332:48] + assign decode_io_lsu_nonblock_load_valid_m = io_lsu_nonblock_load_valid_m; // @[el2_dec.scala 333:48] + assign decode_io_lsu_nonblock_load_tag_m = io_lsu_nonblock_load_tag_m; // @[el2_dec.scala 334:48] + assign decode_io_lsu_nonblock_load_inv_r = io_lsu_nonblock_load_inv_r; // @[el2_dec.scala 335:48] + assign decode_io_lsu_nonblock_load_inv_tag_r = io_lsu_nonblock_load_inv_tag_r; // @[el2_dec.scala 336:48] + assign decode_io_lsu_nonblock_load_data_valid = io_lsu_nonblock_load_data_valid; // @[el2_dec.scala 337:48] + assign decode_io_lsu_nonblock_load_data_error = io_lsu_nonblock_load_data_error; // @[el2_dec.scala 338:48] + assign decode_io_lsu_nonblock_load_data_tag = io_lsu_nonblock_load_data_tag; // @[el2_dec.scala 339:48] + assign decode_io_lsu_nonblock_load_data = io_lsu_nonblock_load_data; // @[el2_dec.scala 340:48] + assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[el2_dec.scala 341:48] + assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[el2_dec.scala 342:48] + assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[el2_dec.scala 343:48] + assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[el2_dec.scala 344:48] + assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 345:48] + assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[el2_dec.scala 346:48] + assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_dec_tlu_flush_leak_one_r; // @[el2_dec.scala 347:48] + assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[el2_dec.scala 348:48] + assign decode_io_dbg_cmd_wrdata = io_dbg_cmd_wrdata; // @[el2_dec.scala 349:48] + assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[el2_dec.scala 350:48] + assign decode_io_dec_i0_icaf_f1_d = instbuff_io_dec_i0_icaf_f1_d; // @[el2_dec.scala 351:48] + assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 352:48] + assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:48] + assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_toffset = instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_hist = instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_br_error = instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_br_start_error = instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_prett = instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_way = instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_ret = instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 355:48] + assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 356:48] + assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 357:48] + assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 359:48] + assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[el2_dec.scala 360:48] + assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 361:48] + assign decode_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 362:48] + assign decode_io_exu_div_wren = io_exu_div_wren; // @[el2_dec.scala 363:48] + assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 364:48] + assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 365:48] + assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[el2_dec.scala 366:48] + assign decode_io_dec_tlu_flush_lower_r = tlu_io_dec_tlu_flush_lower_r; // @[el2_dec.scala 367:48] + assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[el2_dec.scala 368:48] + assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[el2_dec.scala 369:48] + assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[el2_dec.scala 370:48] + assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 371:48] + assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 372:48] + assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[el2_dec.scala 373:48] + assign decode_io_exu_csr_rs1_x = io_exu_csr_rs1_x; // @[el2_dec.scala 374:48] + assign decode_io_lsu_result_m = io_lsu_result_m; // @[el2_dec.scala 375:48] + assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[el2_dec.scala 376:48] + assign decode_io_exu_flush_final = io_exu_flush_final; // @[el2_dec.scala 377:48] + assign decode_io_exu_i0_pc_x = io_exu_i0_pc_x; // @[el2_dec.scala 378:48] + assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[el2_dec.scala 379:48] + assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[el2_dec.scala 380:48] + assign decode_io_exu_i0_result_x = io_exu_i0_result_x; // @[el2_dec.scala 381:48] + assign decode_io_free_clk = io_free_clk; // @[el2_dec.scala 383:48] + assign decode_io_active_clk = io_active_clk; // @[el2_dec.scala 384:48] + assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[el2_dec.scala 385:48] + assign decode_io_scan_mode = io_scan_mode; // @[el2_dec.scala 387:48] assign gpr_clock = clock; assign gpr_reset = reset; - assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[el2_dec.scala 474:40 el2_dec.scala 530:23] - assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[el2_dec.scala 475:40 el2_dec.scala 531:23] - assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[el2_dec.scala 484:40 el2_dec.scala 532:23] - assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[el2_dec.scala 483:40 el2_dec.scala 533:23] - assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 485:40 el2_dec.scala 534:23] - assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 535:23] - assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 536:23] - assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[el2_dec.scala 537:23] - assign gpr_io_wen2 = io_exu_div_wren; // @[el2_dec.scala 538:23] - assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[el2_dec.scala 492:40 el2_dec.scala 539:23] - assign gpr_io_wd2 = io_exu_div_result; // @[el2_dec.scala 540:23] - assign gpr_io_scan_mode = io_scan_mode; // @[el2_dec.scala 543:23] + assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[el2_dec.scala 425:23] + assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[el2_dec.scala 426:23] + assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[el2_dec.scala 427:23] + assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[el2_dec.scala 428:23] + assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[el2_dec.scala 429:23] + assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[el2_dec.scala 430:23] + assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[el2_dec.scala 431:23] + assign gpr_io_wd1 = io_lsu_nonblock_load_data; // @[el2_dec.scala 432:23] + assign gpr_io_wen2 = io_exu_div_wren; // @[el2_dec.scala 433:23] + assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[el2_dec.scala 434:23] + assign gpr_io_wd2 = io_exu_div_result; // @[el2_dec.scala 435:23] + assign gpr_io_scan_mode = io_scan_mode; // @[el2_dec.scala 438:23] assign tlu_clock = clock; assign tlu_reset = reset; - assign tlu_io_active_clk = io_active_clk; // @[el2_dec.scala 555:45] - assign tlu_io_free_clk = io_free_clk; // @[el2_dec.scala 556:45] - assign tlu_io_scan_mode = io_scan_mode; // @[el2_dec.scala 558:45] - assign tlu_io_rst_vec = io_rst_vec[30:0]; // @[el2_dec.scala 559:45] - assign tlu_io_nmi_int = io_nmi_int; // @[el2_dec.scala 560:45] - assign tlu_io_nmi_vec = io_nmi_vec[30:0]; // @[el2_dec.scala 561:45] - assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_dec.scala 562:45] - assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_dec.scala 563:45] - assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[el2_dec.scala 564:45] - assign tlu_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec.scala 565:45] - assign tlu_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec.scala 566:45] - assign tlu_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec.scala 567:45] - assign tlu_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec.scala 568:45] - assign tlu_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec.scala 569:45] - assign tlu_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec.scala 570:45] - assign tlu_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec.scala 571:45] - assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 572:45] - assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 573:45] - assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 574:45] - assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 515:40 el2_dec.scala 516:40 el2_dec.scala 517:40 el2_dec.scala 518:40 el2_dec.scala 519:40 el2_dec.scala 520:40 el2_dec.scala 521:40 el2_dec.scala 575:45] - assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 576:45] - assign tlu_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 577:45] - assign tlu_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec.scala 578:45] - assign tlu_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec.scala 579:45] - assign tlu_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 580:45] - assign tlu_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec.scala 581:45] - assign tlu_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec.scala 582:45] - assign tlu_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 583:45] - assign tlu_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec.scala 584:45] - assign tlu_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec.scala 585:45] - assign tlu_io_lsu_pmu_load_external_m = io_lsu_pmu_load_external_m; // @[el2_dec.scala 586:45] - assign tlu_io_lsu_pmu_store_external_m = io_lsu_pmu_store_external_m; // @[el2_dec.scala 587:45] - assign tlu_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec.scala 588:45] - assign tlu_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec.scala 589:45] - assign tlu_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec.scala 590:45] - assign tlu_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec.scala 591:45] - assign tlu_io_lsu_fir_addr = io_lsu_fir_addr[30:0]; // @[el2_dec.scala 592:45] - assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec.scala 593:45] - assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec.scala 594:45] - assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 595:45] - assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[el2_dec.scala 596:45] - assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[el2_dec.scala 597:45] - assign tlu_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec.scala 598:45] - assign tlu_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec.scala 599:45] - assign tlu_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 600:45] - assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 497:40 el2_dec.scala 601:45] - assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 498:40 el2_dec.scala 602:45] - assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 499:40 el2_dec.scala 603:45] - assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[el2_dec.scala 500:40 el2_dec.scala 604:45] - assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 501:40 el2_dec.scala 605:45] - assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 502:40 el2_dec.scala 606:45] - assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 503:40 el2_dec.scala 607:45] - assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 504:40 el2_dec.scala 608:45] - assign tlu_io_exu_npc_r = io_exu_npc_r[30:0]; // @[el2_dec.scala 609:45] - assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_icaf_f1 = decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 505:40 el2_dec.scala 611:45] - assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[el2_dec.scala 507:40 el2_dec.scala 612:45] - assign tlu_io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 613:45] - assign tlu_io_exu_i0_br_hist_r = io_exu_i0_br_hist_r; // @[el2_dec.scala 614:45] - assign tlu_io_exu_i0_br_error_r = io_exu_i0_br_error_r; // @[el2_dec.scala 615:45] - assign tlu_io_exu_i0_br_start_error_r = io_exu_i0_br_start_error_r; // @[el2_dec.scala 616:45] - assign tlu_io_exu_i0_br_valid_r = io_exu_i0_br_valid_r; // @[el2_dec.scala 617:45] - assign tlu_io_exu_i0_br_mp_r = io_exu_i0_br_mp_r; // @[el2_dec.scala 618:45] - assign tlu_io_exu_i0_br_middle_r = io_exu_i0_br_middle_r; // @[el2_dec.scala 619:45] - assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[el2_dec.scala 620:45] - assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[el2_dec.scala 621:45] - assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[el2_dec.scala 622:45] - assign tlu_io_ifu_miss_state_idle = io_ifu_miss_state_idle; // @[el2_dec.scala 623:45] - assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 624:45] - assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[el2_dec.scala 523:40 el2_dec.scala 625:45] - assign tlu_io_ifu_ic_error_start = io_ifu_ic_error_start; // @[el2_dec.scala 626:45] - assign tlu_io_ifu_iccm_rd_ecc_single_err = io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 627:45] - assign tlu_io_ifu_ic_debug_rd_data = {{1'd0}, io_ifu_ic_debug_rd_data}; // @[el2_dec.scala 628:45] - assign tlu_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 629:45] - assign tlu_io_pic_claimid = io_pic_claimid; // @[el2_dec.scala 630:45] - assign tlu_io_pic_pl = io_pic_pl; // @[el2_dec.scala 631:45] - assign tlu_io_mhwakeup = io_mhwakeup; // @[el2_dec.scala 632:45] - assign tlu_io_mexintpend = io_mexintpend; // @[el2_dec.scala 633:45] - assign tlu_io_timer_int = io_timer_int; // @[el2_dec.scala 634:45] - assign tlu_io_soft_int = io_soft_int; // @[el2_dec.scala 635:45] - assign tlu_io_core_id = io_core_id[27:0]; // @[el2_dec.scala 636:45] - assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_dec.scala 637:45] - assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_dec.scala 638:45] - assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec.scala 639:45] - assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 401:34] - assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 401:34] - assign dec_trigger_io_dec_i0_pc_d = instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 400:30] + assign tlu_io_active_clk = io_active_clk; // @[el2_dec.scala 450:45] + assign tlu_io_free_clk = io_free_clk; // @[el2_dec.scala 451:45] + assign tlu_io_scan_mode = io_scan_mode; // @[el2_dec.scala 453:45] + assign tlu_io_rst_vec = io_rst_vec; // @[el2_dec.scala 454:45] + assign tlu_io_nmi_int = io_nmi_int; // @[el2_dec.scala 455:45] + assign tlu_io_nmi_vec = io_nmi_vec; // @[el2_dec.scala 456:45] + assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_dec.scala 457:45] + assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_dec.scala 458:45] + assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[el2_dec.scala 459:45] + assign tlu_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[el2_dec.scala 460:45] + assign tlu_io_ifu_pmu_fetch_stall = io_ifu_pmu_fetch_stall; // @[el2_dec.scala 461:45] + assign tlu_io_ifu_pmu_ic_miss = io_ifu_pmu_ic_miss; // @[el2_dec.scala 462:45] + assign tlu_io_ifu_pmu_ic_hit = io_ifu_pmu_ic_hit; // @[el2_dec.scala 463:45] + assign tlu_io_ifu_pmu_bus_error = io_ifu_pmu_bus_error; // @[el2_dec.scala 464:45] + assign tlu_io_ifu_pmu_bus_busy = io_ifu_pmu_bus_busy; // @[el2_dec.scala 465:45] + assign tlu_io_ifu_pmu_bus_trxn = io_ifu_pmu_bus_trxn; // @[el2_dec.scala 466:45] + assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[el2_dec.scala 467:45] + assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[el2_dec.scala 468:45] + assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[el2_dec.scala 469:45] + assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[el2_dec.scala 470:45] + assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[el2_dec.scala 471:45] + assign tlu_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[el2_dec.scala 472:45] + assign tlu_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[el2_dec.scala 473:45] + assign tlu_io_exu_pmu_i0_br_misp = io_exu_pmu_i0_br_misp; // @[el2_dec.scala 474:45] + assign tlu_io_exu_pmu_i0_br_ataken = io_exu_pmu_i0_br_ataken; // @[el2_dec.scala 475:45] + assign tlu_io_exu_pmu_i0_pc4 = io_exu_pmu_i0_pc4; // @[el2_dec.scala 476:45] + assign tlu_io_lsu_pmu_bus_trxn = io_lsu_pmu_bus_trxn; // @[el2_dec.scala 477:45] + assign tlu_io_lsu_pmu_bus_misaligned = io_lsu_pmu_bus_misaligned; // @[el2_dec.scala 478:45] + assign tlu_io_lsu_pmu_bus_error = io_lsu_pmu_bus_error; // @[el2_dec.scala 479:45] + assign tlu_io_lsu_pmu_bus_busy = io_lsu_pmu_bus_busy; // @[el2_dec.scala 480:45] + assign tlu_io_lsu_pmu_load_external_m = io_lsu_pmu_load_external_m; // @[el2_dec.scala 481:45] + assign tlu_io_lsu_pmu_store_external_m = io_lsu_pmu_store_external_m; // @[el2_dec.scala 482:45] + assign tlu_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[el2_dec.scala 483:45] + assign tlu_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[el2_dec.scala 484:45] + assign tlu_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[el2_dec.scala 485:45] + assign tlu_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[el2_dec.scala 486:45] + assign tlu_io_lsu_fir_addr = io_lsu_fir_addr; // @[el2_dec.scala 487:45] + assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[el2_dec.scala 488:45] + assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[el2_dec.scala 489:45] + assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 490:45] + assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[el2_dec.scala 491:45] + assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[el2_dec.scala 492:45] + assign tlu_io_lsu_imprecise_error_store_any = io_lsu_imprecise_error_store_any; // @[el2_dec.scala 493:45] + assign tlu_io_lsu_imprecise_error_load_any = io_lsu_imprecise_error_load_any; // @[el2_dec.scala 494:45] + assign tlu_io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_addr_any; // @[el2_dec.scala 495:45] + assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[el2_dec.scala 496:45] + assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[el2_dec.scala 497:45] + assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[el2_dec.scala 498:45] + assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[el2_dec.scala 499:45] + assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[el2_dec.scala 500:45] + assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[el2_dec.scala 501:45] + assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[el2_dec.scala 502:45] + assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[el2_dec.scala 503:45] + assign tlu_io_exu_npc_r = io_exu_npc_r; // @[el2_dec.scala 504:45] + assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[el2_dec.scala 505:45] + assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_icaf_f1 = decode_io_dec_tlu_packet_r_icaf_f1; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[el2_dec.scala 506:45] + assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[el2_dec.scala 506:45] + assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[el2_dec.scala 507:45] + assign tlu_io_dec_i0_decode_d = decode_io_dec_i0_decode_d; // @[el2_dec.scala 508:45] + assign tlu_io_exu_i0_br_hist_r = io_exu_i0_br_hist_r; // @[el2_dec.scala 509:45] + assign tlu_io_exu_i0_br_error_r = io_exu_i0_br_error_r; // @[el2_dec.scala 510:45] + assign tlu_io_exu_i0_br_start_error_r = io_exu_i0_br_start_error_r; // @[el2_dec.scala 511:45] + assign tlu_io_exu_i0_br_valid_r = io_exu_i0_br_valid_r; // @[el2_dec.scala 512:45] + assign tlu_io_exu_i0_br_mp_r = io_exu_i0_br_mp_r; // @[el2_dec.scala 513:45] + assign tlu_io_exu_i0_br_middle_r = io_exu_i0_br_middle_r; // @[el2_dec.scala 514:45] + assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[el2_dec.scala 515:45] + assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[el2_dec.scala 516:45] + assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[el2_dec.scala 517:45] + assign tlu_io_ifu_miss_state_idle = io_ifu_miss_state_idle; // @[el2_dec.scala 518:45] + assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[el2_dec.scala 519:45] + assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[el2_dec.scala 520:45] + assign tlu_io_ifu_ic_error_start = io_ifu_ic_error_start; // @[el2_dec.scala 521:45] + assign tlu_io_ifu_iccm_rd_ecc_single_err = io_ifu_iccm_rd_ecc_single_err; // @[el2_dec.scala 522:45] + assign tlu_io_ifu_ic_debug_rd_data = io_ifu_ic_debug_rd_data; // @[el2_dec.scala 523:45] + assign tlu_io_ifu_ic_debug_rd_data_valid = io_ifu_ic_debug_rd_data_valid; // @[el2_dec.scala 524:45] + assign tlu_io_pic_claimid = io_pic_claimid; // @[el2_dec.scala 525:45] + assign tlu_io_pic_pl = io_pic_pl; // @[el2_dec.scala 526:45] + assign tlu_io_mhwakeup = io_mhwakeup; // @[el2_dec.scala 527:45] + assign tlu_io_mexintpend = io_mexintpend; // @[el2_dec.scala 528:45] + assign tlu_io_timer_int = io_timer_int; // @[el2_dec.scala 529:45] + assign tlu_io_soft_int = io_soft_int; // @[el2_dec.scala 530:45] + assign tlu_io_core_id = io_core_id; // @[el2_dec.scala 531:45] + assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_dec.scala 532:45] + assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_dec.scala 533:45] + assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec.scala 534:45] + assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 321:34] + assign dec_trigger_io_dec_i0_pc_d = instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 320:30] endmodule module rvclkhdr_757( output io_l1clk, @@ -59920,9 +60032,6 @@ initial begin _RAND_20 = {1{`RANDOM}}; data0_reg = _RAND_20[31:0]; `endif // RANDOMIZE_REG_INIT - if (io_dbg_rst_l) begin - dm_temp_0 = 1'h0; - end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -59986,6 +60095,11 @@ end // initial end else if (dmcontrol_wren) begin dm_temp <= _T_139; end + if (io_dbg_rst_l) begin + dm_temp_0 <= 1'h0; + end else if (dmcontrol_wren) begin + dm_temp_0 <= io_dmi_reg_wdata[0]; + end if (_T_29) begin dmstatus_havereset <= 1'h0; end else if (dmstatus_havereset_wren) begin @@ -60161,13 +60275,6 @@ end // initial data0_reg <= data0_din; end end - always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin - if (io_dbg_rst_l) begin - dm_temp_0 <= 1'h0; - end else if (dmcontrol_wren) begin - dm_temp_0 <= io_dmi_reg_wdata[0]; - end - end endmodule module el2_exu_alu_ctl( input clock, @@ -60199,7 +60306,9 @@ module el2_exu_alu_ctl( input io_csr_ren_in, input [31:0] io_a_in, input [31:0] io_b_in, + input [30:0] io_pc_in, input io_pp_in_valid, + input io_pp_in_bits_boffset, input io_pp_in_bits_pc4, input [1:0] io_pp_in_bits_hist, input [11:0] io_pp_in_bits_toffset, @@ -60215,10 +60324,12 @@ module el2_exu_alu_ctl( output io_flush_upper_out, output io_flush_final_out, output [30:0] io_flush_path_out, + output [30:0] io_pc_ff, output io_pred_correct_out, output io_predict_p_out_valid, output io_predict_p_out_bits_misp, output io_predict_p_out_bits_ataken, + output io_predict_p_out_bits_boffset, output io_predict_p_out_bits_pc4, output [1:0] io_predict_p_out_bits_hist, output [11:0] io_predict_p_out_bits_toffset, @@ -60231,6 +60342,7 @@ module el2_exu_alu_ctl( ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; + reg [31:0] _RAND_1; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] @@ -60240,6 +60352,7 @@ module el2_exu_alu_ctl( wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + reg [30:0] _T_1; // @[el2_lib.scala 514:16] reg [31:0] _T_3; // @[el2_lib.scala 514:16] wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37] wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17] @@ -60317,16 +60430,21 @@ module el2_exu_alu_ctl( wire _T_214 = _T_213 | io_pp_in_bits_pja; // @[el2_exu_alu_ctl.scala 79:63] wire sel_pc = _T_214 | io_pp_in_bits_pret; // @[el2_exu_alu_ctl.scala 79:83] wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40] + wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_221 = {{1'd0}, _T_218[12:1]}; // @[el2_lib.scala 208:31] - wire [18:0] _T_227 = 19'h0 - 19'h1; // @[el2_lib.scala 210:27] + wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 208:31] + wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 209:27] + wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27] wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28] + wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26] wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:20] wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:26] wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:26] - wire [18:0] _T_243 = _T_236 ? 19'h1 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_246 = _T_243 | _T_244; // @[Mux.scala 27:72] + wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72] + wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72] wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24] wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58] @@ -60392,10 +60510,12 @@ module el2_exu_alu_ctl( assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26] assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26] assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22] + assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12] assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26] assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:35] assign io_predict_p_out_bits_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:35] + assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[el2_exu_alu_ctl.scala 125:30] assign io_predict_p_out_bits_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:35] assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[el2_exu_alu_ctl.scala 125:30] @@ -60447,8 +60567,13 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - _T_3 = _RAND_0[31:0]; + _T_1 = _RAND_0[30:0]; + _RAND_1 = {1{`RANDOM}}; + _T_3 = _RAND_1[31:0]; `endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1 = 31'h0; + end if (reset) begin _T_3 = 32'h0; end @@ -60458,6 +60583,13 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_1 <= 31'h0; + end else begin + _T_1 <= io_pc_in; + end + end always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin _T_3 <= 32'h0; @@ -61490,6 +61622,8 @@ module el2_exu( input [31:0] io_dec_i0_rs2_bypass_data_d, input [11:0] io_dec_i0_br_immed_d, input io_dec_i0_alu_decode_d, + input io_dec_i0_select_pc_d, + input [30:0] io_dec_i0_pc_d, input [1:0] io_dec_i0_rs1_bypass_en_d, input [1:0] io_dec_i0_rs2_bypass_en_d, input io_dec_csr_ren_d, @@ -61511,6 +61645,7 @@ module el2_exu( output io_exu_flush_final, output [30:0] io_exu_flush_path_final, output [31:0] io_exu_i0_result_x, + output [30:0] io_exu_i0_pc_x, output [31:0] io_exu_csr_rs1_x, output [30:0] io_exu_npc_r, output [1:0] io_exu_i0_br_hist_r, @@ -61524,6 +61659,7 @@ module el2_exu( output io_exu_i0_br_way_r, output io_exu_mp_pkt_bits_misp, output io_exu_mp_pkt_bits_ataken, + output io_exu_mp_pkt_bits_boffset, output io_exu_mp_pkt_bits_pc4, output [1:0] io_exu_mp_pkt_bits_hist, output [11:0] io_exu_mp_pkt_bits_toffset, @@ -61578,6 +61714,8 @@ module el2_exu( reg [31:0] _RAND_33; reg [31:0] _RAND_34; reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] @@ -61680,7 +61818,9 @@ module el2_exu( wire i_alu_io_csr_ren_in; // @[el2_exu.scala 187:19] wire [31:0] i_alu_io_a_in; // @[el2_exu.scala 187:19] wire [31:0] i_alu_io_b_in; // @[el2_exu.scala 187:19] + wire [30:0] i_alu_io_pc_in; // @[el2_exu.scala 187:19] wire i_alu_io_pp_in_valid; // @[el2_exu.scala 187:19] + wire i_alu_io_pp_in_bits_boffset; // @[el2_exu.scala 187:19] wire i_alu_io_pp_in_bits_pc4; // @[el2_exu.scala 187:19] wire [1:0] i_alu_io_pp_in_bits_hist; // @[el2_exu.scala 187:19] wire [11:0] i_alu_io_pp_in_bits_toffset; // @[el2_exu.scala 187:19] @@ -61696,10 +61836,12 @@ module el2_exu( wire i_alu_io_flush_upper_out; // @[el2_exu.scala 187:19] wire i_alu_io_flush_final_out; // @[el2_exu.scala 187:19] wire [30:0] i_alu_io_flush_path_out; // @[el2_exu.scala 187:19] + wire [30:0] i_alu_io_pc_ff; // @[el2_exu.scala 187:19] wire i_alu_io_pred_correct_out; // @[el2_exu.scala 187:19] wire i_alu_io_predict_p_out_valid; // @[el2_exu.scala 187:19] wire i_alu_io_predict_p_out_bits_misp; // @[el2_exu.scala 187:19] wire i_alu_io_predict_p_out_bits_ataken; // @[el2_exu.scala 187:19] + wire i_alu_io_predict_p_out_bits_boffset; // @[el2_exu.scala 187:19] wire i_alu_io_predict_p_out_bits_pc4; // @[el2_exu.scala 187:19] wire [1:0] i_alu_io_predict_p_out_bits_hist; // @[el2_exu.scala 187:19] wire [11:0] i_alu_io_predict_p_out_bits_toffset; // @[el2_exu.scala 187:19] @@ -61736,6 +61878,7 @@ module el2_exu( reg i0_predict_p_x_valid; // @[el2_lib.scala 524:16] reg i0_predict_p_x_bits_misp; // @[el2_lib.scala 524:16] reg i0_predict_p_x_bits_ataken; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_bits_boffset; // @[el2_lib.scala 524:16] reg i0_predict_p_x_bits_pc4; // @[el2_lib.scala 524:16] reg [1:0] i0_predict_p_x_bits_hist; // @[el2_lib.scala 524:16] reg [11:0] i0_predict_p_x_bits_toffset; // @[el2_lib.scala 524:16] @@ -61755,6 +61898,7 @@ module el2_exu( reg i0_pp_r_valid; // @[el2_lib.scala 524:16] reg i0_pp_r_bits_misp; // @[el2_lib.scala 524:16] reg i0_pp_r_bits_ataken; // @[el2_lib.scala 524:16] + reg i0_pp_r_bits_boffset; // @[el2_lib.scala 524:16] reg i0_pp_r_bits_pc4; // @[el2_lib.scala 524:16] reg [1:0] i0_pp_r_bits_hist; // @[el2_lib.scala 524:16] reg i0_pp_r_bits_br_error; // @[el2_lib.scala 524:16] @@ -61796,14 +61940,18 @@ module el2_exu( wire [31:0] _T_60 = io_dec_i0_rs2_bypass_en_d[1] ? io_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] i0_rs2_bypass_data_d = _T_59 | _T_60; // @[Mux.scala 27:72] wire _T_63 = ~i0_rs1_bypass_en_d; // @[el2_exu.scala 150:6] + wire _T_64 = _T_63 & io_dec_i0_select_pc_d; // @[el2_exu.scala 150:26] + wire [31:0] _T_66 = {io_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] wire _T_68 = _T_63 & io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 151:26] wire _T_71 = ~io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 152:28] wire _T_72 = _T_63 & _T_71; // @[el2_exu.scala 152:26] wire _T_73 = _T_72 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 152:54] wire [31:0] _T_75 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_76 = _T_64 ? _T_66 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_77 = _T_68 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_78 = _T_73 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_80 = _T_75 | _T_77; // @[Mux.scala 27:72] + wire [31:0] _T_79 = _T_75 | _T_76; // @[Mux.scala 27:72] + wire [31:0] _T_80 = _T_79 | _T_77; // @[Mux.scala 27:72] wire [31:0] i0_rs1_d = _T_80 | _T_78; // @[Mux.scala 27:72] wire _T_82 = ~i0_rs2_bypass_en_d; // @[el2_exu.scala 156:6] wire _T_83 = _T_82 & io_dec_i0_rs2_en_d; // @[el2_exu.scala 156:26] @@ -61973,7 +62121,9 @@ module el2_exu( .io_csr_ren_in(i_alu_io_csr_ren_in), .io_a_in(i_alu_io_a_in), .io_b_in(i_alu_io_b_in), + .io_pc_in(i_alu_io_pc_in), .io_pp_in_valid(i_alu_io_pp_in_valid), + .io_pp_in_bits_boffset(i_alu_io_pp_in_bits_boffset), .io_pp_in_bits_pc4(i_alu_io_pp_in_bits_pc4), .io_pp_in_bits_hist(i_alu_io_pp_in_bits_hist), .io_pp_in_bits_toffset(i_alu_io_pp_in_bits_toffset), @@ -61989,10 +62139,12 @@ module el2_exu( .io_flush_upper_out(i_alu_io_flush_upper_out), .io_flush_final_out(i_alu_io_flush_final_out), .io_flush_path_out(i_alu_io_flush_path_out), + .io_pc_ff(i_alu_io_pc_ff), .io_pred_correct_out(i_alu_io_pred_correct_out), .io_predict_p_out_valid(i_alu_io_predict_p_out_valid), .io_predict_p_out_bits_misp(i_alu_io_predict_p_out_bits_misp), .io_predict_p_out_bits_ataken(i_alu_io_predict_p_out_bits_ataken), + .io_predict_p_out_bits_boffset(i_alu_io_predict_p_out_bits_boffset), .io_predict_p_out_bits_pc4(i_alu_io_predict_p_out_bits_pc4), .io_predict_p_out_bits_hist(i_alu_io_predict_p_out_bits_hist), .io_predict_p_out_bits_toffset(i_alu_io_predict_p_out_bits_toffset), @@ -62033,6 +62185,7 @@ module el2_exu( assign io_exu_flush_final = i_alu_io_flush_final_out; // @[el2_exu.scala 202:33] assign io_exu_flush_path_final = io_dec_tlu_flush_lower_r ? io_dec_tlu_flush_path_r : i0_flush_path_d; // @[el2_exu.scala 277:50] assign io_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[el2_exu.scala 224:42] + assign io_exu_i0_pc_x = i_alu_io_pc_ff; // @[el2_exu.scala 206:41] assign io_exu_csr_rs1_x = _T_3; // @[el2_exu.scala 107:41] assign io_exu_npc_r = _T_188[30:0]; // @[el2_exu.scala 278:50] assign io_exu_i0_br_hist_r = i0_pp_r_bits_hist; // @[el2_exu.scala 251:50] @@ -62041,11 +62194,12 @@ module el2_exu( assign io_exu_i0_br_index_r = predpipe_r[12:5]; // @[el2_exu.scala 256:42] assign io_exu_i0_br_valid_r = i0_pp_r_valid; // @[el2_exu.scala 248:36] assign io_exu_i0_br_mp_r = i0_pp_r_bits_misp; // @[el2_exu.scala 249:36] - assign io_exu_i0_br_middle_r = i0_pp_r_bits_pc4; // @[el2_exu.scala 253:36] + assign io_exu_i0_br_middle_r = i0_pp_r_bits_pc4 ^ i0_pp_r_bits_boffset; // @[el2_exu.scala 253:36] assign io_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[el2_exu.scala 255:50] assign io_exu_i0_br_way_r = i0_pp_r_bits_way; // @[el2_exu.scala 250:36] assign io_exu_mp_pkt_bits_misp = i0_flush_upper_x & i0_predict_p_x_bits_misp; // @[el2_exu.scala 264:41] assign io_exu_mp_pkt_bits_ataken = i0_flush_upper_x & i0_predict_p_x_bits_ataken; // @[el2_exu.scala 268:41] + assign io_exu_mp_pkt_bits_boffset = i0_flush_upper_x & i0_predict_p_x_bits_boffset; // @[el2_exu.scala 269:41] assign io_exu_mp_pkt_bits_pc4 = i0_flush_upper_x & i0_predict_p_x_bits_pc4; // @[el2_exu.scala 270:41] assign io_exu_mp_pkt_bits_hist = i0_flush_upper_x ? i0_predict_p_x_bits_hist : 2'h0; // @[el2_exu.scala 271:58] assign io_exu_mp_pkt_bits_toffset = i0_flush_upper_x ? i0_predict_p_x_bits_toffset : 12'h0; // @[el2_exu.scala 272:50] @@ -62145,7 +62299,9 @@ module el2_exu( assign i_alu_io_csr_ren_in = io_dec_csr_ren_d; // @[el2_exu.scala 199:33] assign i_alu_io_a_in = _T_80 | _T_78; // @[el2_exu.scala 194:33] assign i_alu_io_b_in = i0_rs2_d; // @[el2_exu.scala 195:33] + assign i_alu_io_pc_in = io_dec_i0_pc_d; // @[el2_exu.scala 196:41] assign i_alu_io_pp_in_valid = io_dec_i0_predict_p_d_valid; // @[el2_exu.scala 190:41] + assign i_alu_io_pp_in_bits_boffset = io_dec_i0_pc_d[0]; // @[el2_exu.scala 190:41] assign i_alu_io_pp_in_bits_pc4 = io_dec_i0_predict_p_d_bits_pc4; // @[el2_exu.scala 190:41] assign i_alu_io_pp_in_bits_hist = io_dec_i0_predict_p_d_bits_hist; // @[el2_exu.scala 190:41] assign i_alu_io_pp_in_bits_toffset = io_dec_i0_predict_p_d_bits_toffset; // @[el2_exu.scala 190:41] @@ -62221,67 +62377,71 @@ initial begin _RAND_4 = {1{`RANDOM}}; i0_predict_p_x_bits_ataken = _RAND_4[0:0]; _RAND_5 = {1{`RANDOM}}; - i0_predict_p_x_bits_pc4 = _RAND_5[0:0]; + i0_predict_p_x_bits_boffset = _RAND_5[0:0]; _RAND_6 = {1{`RANDOM}}; - i0_predict_p_x_bits_hist = _RAND_6[1:0]; + i0_predict_p_x_bits_pc4 = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - i0_predict_p_x_bits_toffset = _RAND_7[11:0]; + i0_predict_p_x_bits_hist = _RAND_7[1:0]; _RAND_8 = {1{`RANDOM}}; - i0_predict_p_x_bits_br_error = _RAND_8[0:0]; + i0_predict_p_x_bits_toffset = _RAND_8[11:0]; _RAND_9 = {1{`RANDOM}}; - i0_predict_p_x_bits_br_start_error = _RAND_9[0:0]; + i0_predict_p_x_bits_br_error = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; - i0_predict_p_x_bits_pcall = _RAND_10[0:0]; + i0_predict_p_x_bits_br_start_error = _RAND_10[0:0]; _RAND_11 = {1{`RANDOM}}; - i0_predict_p_x_bits_pret = _RAND_11[0:0]; + i0_predict_p_x_bits_pcall = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - i0_predict_p_x_bits_pja = _RAND_12[0:0]; + i0_predict_p_x_bits_pret = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - i0_predict_p_x_bits_way = _RAND_13[0:0]; + i0_predict_p_x_bits_pja = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - predpipe_x = _RAND_14[20:0]; + i0_predict_p_x_bits_way = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - predpipe_r = _RAND_15[20:0]; + predpipe_x = _RAND_15[20:0]; _RAND_16 = {1{`RANDOM}}; - ghr_x = _RAND_16[7:0]; + predpipe_r = _RAND_16[20:0]; _RAND_17 = {1{`RANDOM}}; - i0_pred_correct_upper_x = _RAND_17[0:0]; + ghr_x = _RAND_17[7:0]; _RAND_18 = {1{`RANDOM}}; - i0_flush_upper_x = _RAND_18[0:0]; + i0_pred_correct_upper_x = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - i0_taken_x = _RAND_19[0:0]; + i0_flush_upper_x = _RAND_19[0:0]; _RAND_20 = {1{`RANDOM}}; - i0_valid_x = _RAND_20[0:0]; + i0_taken_x = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - i0_pp_r_valid = _RAND_21[0:0]; + i0_valid_x = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - i0_pp_r_bits_misp = _RAND_22[0:0]; + i0_pp_r_valid = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - i0_pp_r_bits_ataken = _RAND_23[0:0]; + i0_pp_r_bits_misp = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - i0_pp_r_bits_pc4 = _RAND_24[0:0]; + i0_pp_r_bits_ataken = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - i0_pp_r_bits_hist = _RAND_25[1:0]; + i0_pp_r_bits_boffset = _RAND_25[0:0]; _RAND_26 = {1{`RANDOM}}; - i0_pp_r_bits_br_error = _RAND_26[0:0]; + i0_pp_r_bits_pc4 = _RAND_26[0:0]; _RAND_27 = {1{`RANDOM}}; - i0_pp_r_bits_br_start_error = _RAND_27[0:0]; + i0_pp_r_bits_hist = _RAND_27[1:0]; _RAND_28 = {1{`RANDOM}}; - i0_pp_r_bits_way = _RAND_28[0:0]; + i0_pp_r_bits_br_error = _RAND_28[0:0]; _RAND_29 = {1{`RANDOM}}; - pred_temp1 = _RAND_29[5:0]; + i0_pp_r_bits_br_start_error = _RAND_29[0:0]; _RAND_30 = {1{`RANDOM}}; - i0_pred_correct_upper_r = _RAND_30[0:0]; + i0_pp_r_bits_way = _RAND_30[0:0]; _RAND_31 = {1{`RANDOM}}; - i0_flush_path_upper_r = _RAND_31[30:0]; + pred_temp1 = _RAND_31[5:0]; _RAND_32 = {1{`RANDOM}}; - pred_temp2 = _RAND_32[24:0]; + i0_pred_correct_upper_r = _RAND_32[0:0]; _RAND_33 = {1{`RANDOM}}; - ghr_d = _RAND_33[7:0]; + i0_flush_path_upper_r = _RAND_33[30:0]; _RAND_34 = {1{`RANDOM}}; - mul_valid_x = _RAND_34[0:0]; + pred_temp2 = _RAND_34[24:0]; _RAND_35 = {1{`RANDOM}}; - flush_lower_ff = _RAND_35[0:0]; + ghr_d = _RAND_35[7:0]; + _RAND_36 = {1{`RANDOM}}; + mul_valid_x = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + flush_lower_ff = _RAND_37[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin i0_flush_path_x = 31'h0; @@ -62298,6 +62458,9 @@ initial begin if (reset) begin i0_predict_p_x_bits_ataken = 1'h0; end + if (reset) begin + i0_predict_p_x_bits_boffset = 1'h0; + end if (reset) begin i0_predict_p_x_bits_pc4 = 1'h0; end @@ -62355,6 +62518,9 @@ initial begin if (reset) begin i0_pp_r_bits_ataken = 1'h0; end + if (reset) begin + i0_pp_r_bits_boffset = 1'h0; + end if (reset) begin i0_pp_r_bits_pc4 = 1'h0; end @@ -62434,6 +62600,13 @@ end // initial i0_predict_p_x_bits_ataken <= i_alu_io_predict_p_out_bits_ataken; end end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_bits_boffset <= 1'h0; + end else begin + i0_predict_p_x_bits_boffset <= i_alu_io_predict_p_out_bits_boffset; + end + end always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin i0_predict_p_x_bits_pc4 <= 1'h0; @@ -62567,6 +62740,13 @@ end // initial i0_pp_r_bits_ataken <= i0_predict_p_x_bits_ataken; end end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_bits_boffset <= 1'h0; + end else begin + i0_pp_r_bits_boffset <= i0_predict_p_x_bits_boffset; + end + end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin i0_pp_r_bits_pc4 <= 1'h0; @@ -62886,8 +63066,8 @@ module el2_lsu_lsc_ctl( output io_lsu_error_pkt_r_bits_single_ecc_error, output io_lsu_error_pkt_r_bits_inst_type, output io_lsu_error_pkt_r_bits_exc_type, - output io_lsu_error_pkt_r_bits_mscause, - output io_lsu_error_pkt_r_bits_addr, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, output [30:0] io_lsu_fir_addr, output [1:0] io_lsu_fir_error, output io_addr_in_dccm_d, @@ -63065,14 +63245,13 @@ module el2_lsu_lsc_ctl( wire _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 183:78] wire _T_91 = ~access_fault_m; // @[el2_lsu_lsc_ctl.scala 183:102] wire _T_92 = _T_90 & _T_91; // @[el2_lsu_lsc_ctl.scala 183:100] - wire [3:0] _T_95 = _T_92 ? 4'h1 : exc_mscause_m; // @[el2_lsu_lsc_ctl.scala 183:49] wire _T_99 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 185:166] reg _T_105_valid; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_inst_type; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 186:75] - reg _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75] - reg _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75] + reg [3:0] _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75] + reg [31:0] _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75] reg [1:0] _T_106; // @[el2_lsu_lsc_ctl.scala 187:75] wire dma_pkt_d_bits_load = ~io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 194:30] wire dma_pkt_d_bits_by = io_dma_mem_sz == 3'h0; // @[el2_lsu_lsc_ctl.scala 195:50] @@ -63335,9 +63514,9 @@ initial begin _RAND_8 = {1{`RANDOM}}; _T_105_bits_exc_type = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - _T_105_bits_mscause = _RAND_9[0:0]; + _T_105_bits_mscause = _RAND_9[3:0]; _RAND_10 = {1{`RANDOM}}; - _T_105_bits_addr = _RAND_10[0:0]; + _T_105_bits_addr = _RAND_10[31:0]; _RAND_11 = {1{`RANDOM}}; _T_106 = _RAND_11[1:0]; _RAND_12 = {1{`RANDOM}}; @@ -63433,10 +63612,10 @@ initial begin _T_105_bits_exc_type = 1'h0; end if (reset) begin - _T_105_bits_mscause = 1'h0; + _T_105_bits_mscause = 4'h0; end if (reset) begin - _T_105_bits_addr = 1'h0; + _T_105_bits_addr = 32'h0; end if (reset) begin _T_106 = 2'h0; @@ -63608,16 +63787,18 @@ end // initial end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_105_bits_mscause <= 1'h0; + _T_105_bits_mscause <= 4'h0; + end else if (_T_92) begin + _T_105_bits_mscause <= 4'h1; end else begin - _T_105_bits_mscause <= _T_95[0]; + _T_105_bits_mscause <= exc_mscause_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_105_bits_addr <= 1'h0; + _T_105_bits_addr <= 32'h0; end else begin - _T_105_bits_addr <= io_lsu_addr_m[0]; + _T_105_bits_addr <= io_lsu_addr_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin @@ -66809,22 +66990,22 @@ end // initial endmodule module el2_lsu_trigger( input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_store, input io_trigger_pkt_any_0_load, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_store, input io_trigger_pkt_any_1_load, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_store, input io_trigger_pkt_any_2_load, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_store, input io_trigger_pkt_any_3_load, input [31:0] io_trigger_pkt_any_3_tdata2, @@ -66873,7 +67054,7 @@ module el2_lsu_trigger( wire _T_46 = _T_40 & _T_45; // @[el2_lsu_trigger.scala 18:94] wire _T_49 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] wire _T_50 = ~_T_49; // @[el2_lib.scala 241:39] - wire _T_51 = io_trigger_pkt_any_0_match_ & _T_50; // @[el2_lib.scala 241:37] + wire _T_51 = io_trigger_pkt_any_0_match_pkt & _T_50; // @[el2_lib.scala 241:37] wire _T_54 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[el2_lib.scala 242:52] wire _T_55 = _T_51 | _T_54; // @[el2_lib.scala 242:41] wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] @@ -67013,7 +67194,7 @@ module el2_lsu_trigger( wire _T_312 = _T_40 & _T_311; // @[el2_lsu_trigger.scala 18:94] wire _T_315 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] wire _T_316 = ~_T_315; // @[el2_lib.scala 241:39] - wire _T_317 = io_trigger_pkt_any_1_match_ & _T_316; // @[el2_lib.scala 241:37] + wire _T_317 = io_trigger_pkt_any_1_match_pkt & _T_316; // @[el2_lib.scala 241:37] wire _T_320 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[el2_lib.scala 242:52] wire _T_321 = _T_317 | _T_320; // @[el2_lib.scala 242:41] wire _T_323 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] @@ -67153,7 +67334,7 @@ module el2_lsu_trigger( wire _T_578 = _T_40 & _T_577; // @[el2_lsu_trigger.scala 18:94] wire _T_581 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] wire _T_582 = ~_T_581; // @[el2_lib.scala 241:39] - wire _T_583 = io_trigger_pkt_any_2_match_ & _T_582; // @[el2_lib.scala 241:37] + wire _T_583 = io_trigger_pkt_any_2_match_pkt & _T_582; // @[el2_lib.scala 241:37] wire _T_586 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[el2_lib.scala 242:52] wire _T_587 = _T_583 | _T_586; // @[el2_lib.scala 242:41] wire _T_589 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] @@ -67293,7 +67474,7 @@ module el2_lsu_trigger( wire _T_844 = _T_40 & _T_843; // @[el2_lsu_trigger.scala 18:94] wire _T_847 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] wire _T_848 = ~_T_847; // @[el2_lib.scala 241:39] - wire _T_849 = io_trigger_pkt_any_3_match_ & _T_848; // @[el2_lib.scala 241:37] + wire _T_849 = io_trigger_pkt_any_3_match_pkt & _T_848; // @[el2_lib.scala 241:37] wire _T_852 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[el2_lib.scala 242:52] wire _T_853 = _T_849 | _T_852; // @[el2_lib.scala 242:41] wire _T_855 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] @@ -72983,22 +73164,22 @@ module el2_lsu( input io_lsu_p_bits_store_data_bypass_d, input io_lsu_p_bits_load_ldst_bypass_d, input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_store, input io_trigger_pkt_any_0_load, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_store, input io_trigger_pkt_any_1_load, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_store, input io_trigger_pkt_any_2_load, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_store, input io_trigger_pkt_any_3_load, input [31:0] io_trigger_pkt_any_3_tdata2, @@ -73017,8 +73198,8 @@ module el2_lsu( output io_lsu_error_pkt_r_bits_single_ecc_error, output io_lsu_error_pkt_r_bits_inst_type, output io_lsu_error_pkt_r_bits_exc_type, - output io_lsu_error_pkt_r_bits_mscause, - output io_lsu_error_pkt_r_bits_addr, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, output io_lsu_imprecise_error_load_any, output io_lsu_imprecise_error_store_any, output [31:0] io_lsu_imprecise_error_addr_any, @@ -73146,8 +73327,8 @@ module el2_lsu( wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_lsu.scala 154:30] wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[el2_lsu.scala 154:30] wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[el2_lsu.scala 154:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[el2_lsu.scala 154:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[el2_lsu.scala 154:30] + wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[el2_lsu.scala 154:30] wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[el2_lsu.scala 154:30] wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[el2_lsu.scala 154:30] wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 154:30] @@ -73387,22 +73568,22 @@ module el2_lsu( wire ecc_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 159:30] wire ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 159:30] wire trigger_io_trigger_pkt_any_0_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_0_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_0_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_0_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_0_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_1_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_1_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_1_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_1_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_1_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_2_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_2_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_2_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_2_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_2_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_3_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_3_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_3_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_3_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_3_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 160:30] @@ -73862,22 +74043,22 @@ module el2_lsu( ); el2_lsu_trigger trigger ( // @[el2_lsu.scala 160:30] .io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(trigger_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(trigger_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(trigger_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_tdata2(trigger_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(trigger_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(trigger_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(trigger_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(trigger_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(trigger_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_tdata2(trigger_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(trigger_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(trigger_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(trigger_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(trigger_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(trigger_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_tdata2(trigger_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(trigger_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(trigger_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(trigger_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(trigger_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(trigger_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_tdata2(trigger_io_trigger_pkt_any_3_tdata2), @@ -74245,22 +74426,22 @@ module el2_lsu( assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[el2_lsu.scala 371:50] assign ecc_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 372:50] assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_0_match_ = io_trigger_pkt_any_0_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_1_match_ = io_trigger_pkt_any_1_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_2_match_ = io_trigger_pkt_any_2_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_3_match_ = io_trigger_pkt_any_3_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 376:50] @@ -80025,7 +80206,7 @@ module el2_swerv( output [38:0] io_dccm_wr_data_hi, input [38:0] io_dccm_rd_data_lo, input [38:0] io_dccm_rd_data_hi, - output [15:0] io_iccm_rw_addr, + output [14:0] io_iccm_rw_addr, output io_iccm_wren, output io_iccm_rden, output [2:0] io_iccm_wr_size, @@ -80107,7 +80288,7 @@ module el2_swerv( output [2:0] io_ifu_axi_awprot, output [3:0] io_ifu_axi_awqos, output io_ifu_axi_wvalid, - output io_ifu_axi_wready, + input io_ifu_axi_wready, output [63:0] io_ifu_axi_wdata, output [7:0] io_ifu_axi_wstrb, output io_ifu_axi_wlast, @@ -80263,762 +80444,772 @@ module el2_swerv( input io_soft_int, input io_scan_mode ); - wire ifu_clock; // @[el2_swerv.scala 323:19] - wire ifu_reset; // @[el2_swerv.scala 323:19] - wire ifu_io_free_clk; // @[el2_swerv.scala 323:19] - wire ifu_io_active_clk; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_i0_decode_d; // @[el2_swerv.scala 323:19] - wire ifu_io_exu_flush_final; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_i0_commit_cmt; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_flush_err_wb; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_flush_noredir_wb; // @[el2_swerv.scala 323:19] - wire [30:0] ifu_io_exu_flush_path_final; // @[el2_swerv.scala 323:19] - wire [31:0] ifu_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_fence_i_wb; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_flush_leak_one_wb; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_bpred_disable; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_force_halt; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_axi_arvalid; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_axi_arready; // @[el2_swerv.scala 323:19] - wire [2:0] ifu_io_ifu_axi_arid; // @[el2_swerv.scala 323:19] - wire [31:0] ifu_io_ifu_axi_araddr; // @[el2_swerv.scala 323:19] - wire [3:0] ifu_io_ifu_axi_arregion; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_axi_rvalid; // @[el2_swerv.scala 323:19] - wire [2:0] ifu_io_ifu_axi_rid; // @[el2_swerv.scala 323:19] - wire [63:0] ifu_io_ifu_axi_rdata; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_ifu_axi_rresp; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_bus_clk_en; // @[el2_swerv.scala 323:19] - wire ifu_io_dma_iccm_req; // @[el2_swerv.scala 323:19] - wire [31:0] ifu_io_dma_mem_addr; // @[el2_swerv.scala 323:19] - wire [2:0] ifu_io_dma_mem_sz; // @[el2_swerv.scala 323:19] - wire ifu_io_dma_mem_write; // @[el2_swerv.scala 323:19] - wire [63:0] ifu_io_dma_mem_wdata; // @[el2_swerv.scala 323:19] - wire [2:0] ifu_io_dma_mem_tag; // @[el2_swerv.scala 323:19] - wire ifu_io_dma_iccm_stall_any; // @[el2_swerv.scala 323:19] - wire ifu_io_iccm_dma_ecc_error; // @[el2_swerv.scala 323:19] - wire ifu_io_iccm_dma_rvalid; // @[el2_swerv.scala 323:19] - wire [63:0] ifu_io_iccm_dma_rdata; // @[el2_swerv.scala 323:19] - wire [2:0] ifu_io_iccm_dma_rtag; // @[el2_swerv.scala 323:19] - wire ifu_io_iccm_ready; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_ic_error_start; // @[el2_swerv.scala 323:19] - wire [30:0] ifu_io_ic_rw_addr; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_ic_wr_en; // @[el2_swerv.scala 323:19] - wire ifu_io_ic_rd_en; // @[el2_swerv.scala 323:19] - wire [70:0] ifu_io_ic_wr_data_0; // @[el2_swerv.scala 323:19] - wire [70:0] ifu_io_ic_wr_data_1; // @[el2_swerv.scala 323:19] - wire [63:0] ifu_io_ic_rd_data; // @[el2_swerv.scala 323:19] - wire [70:0] ifu_io_ic_debug_rd_data; // @[el2_swerv.scala 323:19] - wire [25:0] ifu_io_ictag_debug_rd_data; // @[el2_swerv.scala 323:19] - wire [70:0] ifu_io_ic_debug_wr_data; // @[el2_swerv.scala 323:19] - wire [70:0] ifu_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_ic_eccerr; // @[el2_swerv.scala 323:19] - wire [63:0] ifu_io_ic_premux_data; // @[el2_swerv.scala 323:19] - wire ifu_io_ic_sel_premux_data; // @[el2_swerv.scala 323:19] - wire [9:0] ifu_io_ic_debug_addr; // @[el2_swerv.scala 323:19] - wire ifu_io_ic_debug_rd_en; // @[el2_swerv.scala 323:19] - wire ifu_io_ic_debug_wr_en; // @[el2_swerv.scala 323:19] - wire ifu_io_ic_debug_tag_array; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_ic_debug_way; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_ic_tag_valid; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_ic_rd_hit; // @[el2_swerv.scala 323:19] - wire ifu_io_ic_tag_perr; // @[el2_swerv.scala 323:19] - wire [14:0] ifu_io_iccm_rw_addr; // @[el2_swerv.scala 323:19] - wire ifu_io_iccm_wren; // @[el2_swerv.scala 323:19] - wire ifu_io_iccm_rden; // @[el2_swerv.scala 323:19] - wire [77:0] ifu_io_iccm_wr_data; // @[el2_swerv.scala 323:19] - wire [2:0] ifu_io_iccm_wr_size; // @[el2_swerv.scala 323:19] - wire [63:0] ifu_io_iccm_rd_data; // @[el2_swerv.scala 323:19] - wire [77:0] ifu_io_iccm_rd_data_ecc; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_iccm_rd_ecc_single_err; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_pmu_ic_miss; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_pmu_ic_hit; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_pmu_bus_error; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_pmu_bus_busy; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_pmu_bus_trxn; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_i0_icaf; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_ifu_i0_icaf_type; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_i0_valid; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_i0_icaf_f1; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_i0_dbecc; // @[el2_swerv.scala 323:19] - wire ifu_io_iccm_dma_sb_error; // @[el2_swerv.scala 323:19] - wire [31:0] ifu_io_ifu_i0_instr; // @[el2_swerv.scala 323:19] - wire [30:0] ifu_io_ifu_i0_pc; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_miss_state_idle; // @[el2_swerv.scala 323:19] - wire ifu_io_i0_brp_valid; // @[el2_swerv.scala 323:19] - wire [11:0] ifu_io_i0_brp_bits_toffset; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_i0_brp_bits_hist; // @[el2_swerv.scala 323:19] - wire ifu_io_i0_brp_bits_br_error; // @[el2_swerv.scala 323:19] - wire ifu_io_i0_brp_bits_br_start_error; // @[el2_swerv.scala 323:19] - wire [30:0] ifu_io_i0_brp_bits_prett; // @[el2_swerv.scala 323:19] - wire ifu_io_i0_brp_bits_way; // @[el2_swerv.scala 323:19] - wire ifu_io_i0_brp_bits_ret; // @[el2_swerv.scala 323:19] - wire [7:0] ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 323:19] - wire [7:0] ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 323:19] - wire [4:0] ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 323:19] - wire ifu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 323:19] - wire ifu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 323:19] - wire ifu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 323:19] - wire [11:0] ifu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 323:19] - wire ifu_io_exu_mp_pkt_bits_pcall; // @[el2_swerv.scala 323:19] - wire ifu_io_exu_mp_pkt_bits_pret; // @[el2_swerv.scala 323:19] - wire ifu_io_exu_mp_pkt_bits_pja; // @[el2_swerv.scala 323:19] - wire ifu_io_exu_mp_pkt_bits_way; // @[el2_swerv.scala 323:19] - wire [7:0] ifu_io_exu_mp_eghr; // @[el2_swerv.scala 323:19] - wire [7:0] ifu_io_exu_mp_fghr; // @[el2_swerv.scala 323:19] - wire [7:0] ifu_io_exu_mp_index; // @[el2_swerv.scala 323:19] - wire [4:0] ifu_io_exu_mp_btag; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 323:19] - wire [1:0] ifu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_swerv.scala 323:19] - wire [7:0] ifu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 323:19] - wire [7:0] ifu_io_exu_i0_br_index_r; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_flush_lower_wb; // @[el2_swerv.scala 323:19] - wire [15:0] ifu_io_ifu_i0_cinst; // @[el2_swerv.scala 323:19] - wire [70:0] ifu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 323:19] - wire [16:0] ifu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_swerv.scala 323:19] - wire ifu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_swerv.scala 323:19] - wire ifu_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 323:19] - wire ifu_io_iccm_buf_correct_ecc; // @[el2_swerv.scala 323:19] - wire ifu_io_iccm_correction_state; // @[el2_swerv.scala 323:19] - wire ifu_io_scan_mode; // @[el2_swerv.scala 323:19] - wire dec_clock; // @[el2_swerv.scala 324:19] - wire dec_reset; // @[el2_swerv.scala 324:19] - wire dec_io_free_clk; // @[el2_swerv.scala 324:19] - wire dec_io_active_clk; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_fastint_stall_any; // @[el2_swerv.scala 324:19] - wire dec_io_dec_extint_stall; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_decode_d; // @[el2_swerv.scala 324:19] - wire dec_io_dec_pause_state_cg; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_rst_vec; // @[el2_swerv.scala 324:19] - wire dec_io_nmi_int; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_nmi_vec; // @[el2_swerv.scala 324:19] - wire dec_io_i_cpu_halt_req; // @[el2_swerv.scala 324:19] - wire dec_io_i_cpu_run_req; // @[el2_swerv.scala 324:19] - wire dec_io_o_cpu_halt_status; // @[el2_swerv.scala 324:19] - wire dec_io_o_cpu_halt_ack; // @[el2_swerv.scala 324:19] - wire dec_io_o_cpu_run_ack; // @[el2_swerv.scala 324:19] - wire dec_io_o_debug_mode_status; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_core_id; // @[el2_swerv.scala 324:19] - wire dec_io_mpc_debug_halt_req; // @[el2_swerv.scala 324:19] - wire dec_io_mpc_debug_run_req; // @[el2_swerv.scala 324:19] - wire dec_io_mpc_reset_run_req; // @[el2_swerv.scala 324:19] - wire dec_io_mpc_debug_halt_ack; // @[el2_swerv.scala 324:19] - wire dec_io_mpc_debug_run_ack; // @[el2_swerv.scala 324:19] - wire dec_io_debug_brkpt_status; // @[el2_swerv.scala 324:19] - wire dec_io_exu_pmu_i0_br_misp; // @[el2_swerv.scala 324:19] - wire dec_io_exu_pmu_i0_br_ataken; // @[el2_swerv.scala 324:19] - wire dec_io_exu_pmu_i0_pc4; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_nonblock_load_valid_m; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_lsu_nonblock_load_tag_m; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_nonblock_load_inv_r; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_lsu_nonblock_load_inv_tag_r; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_nonblock_load_data_valid; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_nonblock_load_data_error; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_lsu_nonblock_load_data_tag; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_lsu_nonblock_load_data; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_pmu_bus_trxn; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_pmu_bus_misaligned; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_pmu_bus_error; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_pmu_bus_busy; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_pmu_load_external_m; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_pmu_store_external_m; // @[el2_swerv.scala 324:19] - wire dec_io_dma_pmu_dccm_read; // @[el2_swerv.scala 324:19] - wire dec_io_dma_pmu_dccm_write; // @[el2_swerv.scala 324:19] - wire dec_io_dma_pmu_any_read; // @[el2_swerv.scala 324:19] - wire dec_io_dma_pmu_any_write; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_lsu_fir_addr; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_lsu_fir_error; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_pmu_ic_miss; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_pmu_ic_hit; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_pmu_bus_error; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_pmu_bus_busy; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_pmu_bus_trxn; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_ic_error_start; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_iccm_rd_ecc_single_err; // @[el2_swerv.scala 324:19] - wire [3:0] dec_io_lsu_trigger_match_m; // @[el2_swerv.scala 324:19] - wire dec_io_dbg_cmd_valid; // @[el2_swerv.scala 324:19] - wire dec_io_dbg_cmd_write; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_dbg_cmd_type; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_dbg_cmd_addr; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_dbg_cmd_wrdata; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_i0_icaf; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_ifu_i0_icaf_type; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_i0_icaf_f1; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_i0_dbecc; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_idle_any; // @[el2_swerv.scala 324:19] - wire dec_io_i0_brp_valid; // @[el2_swerv.scala 324:19] - wire [11:0] dec_io_i0_brp_bits_toffset; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_i0_brp_bits_hist; // @[el2_swerv.scala 324:19] - wire dec_io_i0_brp_bits_br_error; // @[el2_swerv.scala 324:19] - wire dec_io_i0_brp_bits_br_start_error; // @[el2_swerv.scala 324:19] - wire [30:0] dec_io_i0_brp_bits_prett; // @[el2_swerv.scala 324:19] - wire dec_io_i0_brp_bits_way; // @[el2_swerv.scala 324:19] - wire dec_io_i0_brp_bits_ret; // @[el2_swerv.scala 324:19] - wire [8:0] dec_io_ifu_i0_bp_index; // @[el2_swerv.scala 324:19] - wire [7:0] dec_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 324:19] - wire [4:0] dec_io_ifu_i0_bp_btag; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_exu_div_result; // @[el2_swerv.scala 324:19] - wire dec_io_exu_div_wren; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_exu_csr_rs1_x; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_lsu_result_m; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_lsu_result_corr_r; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_load_stall_any; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_store_stall_any; // @[el2_swerv.scala 324:19] - wire dec_io_dma_dccm_stall_any; // @[el2_swerv.scala 324:19] - wire dec_io_dma_iccm_stall_any; // @[el2_swerv.scala 324:19] - wire dec_io_iccm_dma_sb_error; // @[el2_swerv.scala 324:19] - wire dec_io_exu_flush_final; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_exu_npc_r; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_exu_i0_result_x; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_i0_valid; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_ifu_i0_instr; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_ifu_i0_pc; // @[el2_swerv.scala 324:19] - wire dec_io_mexintpend; // @[el2_swerv.scala 324:19] - wire dec_io_timer_int; // @[el2_swerv.scala 324:19] - wire dec_io_soft_int; // @[el2_swerv.scala 324:19] - wire [7:0] dec_io_pic_claimid; // @[el2_swerv.scala 324:19] - wire [3:0] dec_io_pic_pl; // @[el2_swerv.scala 324:19] - wire dec_io_mhwakeup; // @[el2_swerv.scala 324:19] - wire [3:0] dec_io_dec_tlu_meicurpl; // @[el2_swerv.scala 324:19] - wire [3:0] dec_io_dec_tlu_meipt; // @[el2_swerv.scala 324:19] - wire [69:0] dec_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 324:19] - wire [70:0] dec_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 324:19] - wire [16:0] dec_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_swerv.scala 324:19] - wire dec_io_dbg_halt_req; // @[el2_swerv.scala 324:19] - wire dec_io_dbg_resume_req; // @[el2_swerv.scala 324:19] - wire dec_io_ifu_miss_state_idle; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_dbg_halted; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_debug_mode; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_resume_ack; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_flush_noredir_r; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_flush_leak_one_r; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_flush_err_r; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_dec_tlu_meihap; // @[el2_swerv.scala 324:19] - wire dec_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_dec_dbg_rddata; // @[el2_swerv.scala 324:19] - wire dec_io_dec_dbg_cmd_done; // @[el2_swerv.scala 324:19] - wire dec_io_dec_dbg_cmd_fail; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_0_match_; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_1_match_; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_2_match_; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_3_match_; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 324:19] - wire dec_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_force_halt; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_exu_i0_br_hist_r; // @[el2_swerv.scala 324:19] - wire dec_io_exu_i0_br_error_r; // @[el2_swerv.scala 324:19] - wire dec_io_exu_i0_br_start_error_r; // @[el2_swerv.scala 324:19] - wire dec_io_exu_i0_br_valid_r; // @[el2_swerv.scala 324:19] - wire dec_io_exu_i0_br_mp_r; // @[el2_swerv.scala 324:19] - wire dec_io_exu_i0_br_middle_r; // @[el2_swerv.scala 324:19] - wire dec_io_exu_i0_br_way_r; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_gpr_i0_rs1_d; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_gpr_i0_rs2_d; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_dec_i0_immed_d; // @[el2_swerv.scala 324:19] - wire [12:0] dec_io_dec_i0_br_immed_d; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_land; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_lor; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_lxor; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_sll; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_srl; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_sra; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_beq; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_bne; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_blt; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_bge; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_add; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_sub; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_slt; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_unsign; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_jal; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_predict_t; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_predict_nt; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_csr_write; // @[el2_swerv.scala 324:19] - wire dec_io_i0_ap_csr_imm; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_valid; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_bits_fast_int; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_bits_by; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_bits_half; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_bits_word; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_bits_load; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_bits_store; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_bits_unsign; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 324:19] - wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 324:19] - wire dec_io_mul_p_valid; // @[el2_swerv.scala 324:19] - wire dec_io_mul_p_bits_rs1_sign; // @[el2_swerv.scala 324:19] - wire dec_io_mul_p_bits_rs2_sign; // @[el2_swerv.scala 324:19] - wire dec_io_mul_p_bits_low; // @[el2_swerv.scala 324:19] - wire dec_io_div_p_valid; // @[el2_swerv.scala 324:19] - wire dec_io_div_p_bits_unsign; // @[el2_swerv.scala 324:19] - wire dec_io_div_p_bits_rem; // @[el2_swerv.scala 324:19] - wire dec_io_dec_div_cancel; // @[el2_swerv.scala 324:19] - wire [11:0] dec_io_dec_lsu_offset_d; // @[el2_swerv.scala 324:19] - wire dec_io_dec_csr_ren_d; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_fence_i_r; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_pred_correct_npc_x; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_perfcnt0; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_perfcnt1; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_perfcnt2; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_perfcnt3; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_predict_p_d_valid; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_predict_p_d_bits_pc4; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_dec_i0_predict_p_d_bits_hist; // @[el2_swerv.scala 324:19] - wire [11:0] dec_io_dec_i0_predict_p_d_bits_toffset; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_predict_p_d_bits_br_error; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_swerv.scala 324:19] - wire [30:0] dec_io_dec_i0_predict_p_d_bits_prett; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_predict_p_d_bits_pcall; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_predict_p_d_bits_pret; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 324:19] - wire dec_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 324:19] - wire [7:0] dec_io_i0_predict_fghr_d; // @[el2_swerv.scala 324:19] - wire [8:0] dec_io_i0_predict_index_d; // @[el2_swerv.scala 324:19] - wire [4:0] dec_io_i0_predict_btag_d; // @[el2_swerv.scala 324:19] - wire dec_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_dec_data_en; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_dec_ctl_en; // @[el2_swerv.scala 324:19] - wire [15:0] dec_io_ifu_i0_cinst; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[el2_swerv.scala 324:19] - wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[el2_swerv.scala 324:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[el2_swerv.scala 324:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_external_ldfwd_disable; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_sideeffect_posted_disable; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_bpred_disable; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_wb_coalescing_disable; // @[el2_swerv.scala 324:19] - wire [2:0] dec_io_dec_tlu_dma_qos_prty; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_misc_clk_override; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_lsu_clk_override; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_pic_clk_override; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_dccm_clk_override; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_icm_clk_override; // @[el2_swerv.scala 324:19] - wire dec_io_dec_tlu_i0_commit_cmt; // @[el2_swerv.scala 324:19] - wire dec_io_scan_mode; // @[el2_swerv.scala 324:19] - wire dbg_clock; // @[el2_swerv.scala 325:19] - wire dbg_reset; // @[el2_swerv.scala 325:19] - wire [31:0] dbg_io_dbg_cmd_addr; // @[el2_swerv.scala 325:19] - wire [31:0] dbg_io_dbg_cmd_wrdata; // @[el2_swerv.scala 325:19] - wire dbg_io_dbg_cmd_valid; // @[el2_swerv.scala 325:19] - wire dbg_io_dbg_cmd_write; // @[el2_swerv.scala 325:19] - wire [1:0] dbg_io_dbg_cmd_type; // @[el2_swerv.scala 325:19] - wire [1:0] dbg_io_dbg_cmd_size; // @[el2_swerv.scala 325:19] - wire dbg_io_dbg_core_rst_l; // @[el2_swerv.scala 325:19] - wire [31:0] dbg_io_core_dbg_rddata; // @[el2_swerv.scala 325:19] - wire dbg_io_core_dbg_cmd_done; // @[el2_swerv.scala 325:19] - wire dbg_io_core_dbg_cmd_fail; // @[el2_swerv.scala 325:19] - wire dbg_io_dbg_dma_bubble; // @[el2_swerv.scala 325:19] - wire dbg_io_dma_dbg_ready; // @[el2_swerv.scala 325:19] - wire dbg_io_dbg_halt_req; // @[el2_swerv.scala 325:19] - wire dbg_io_dbg_resume_req; // @[el2_swerv.scala 325:19] - wire dbg_io_dec_tlu_debug_mode; // @[el2_swerv.scala 325:19] - wire dbg_io_dec_tlu_dbg_halted; // @[el2_swerv.scala 325:19] - wire dbg_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 325:19] - wire dbg_io_dec_tlu_resume_ack; // @[el2_swerv.scala 325:19] - wire dbg_io_dmi_reg_en; // @[el2_swerv.scala 325:19] - wire [6:0] dbg_io_dmi_reg_addr; // @[el2_swerv.scala 325:19] - wire dbg_io_dmi_reg_wr_en; // @[el2_swerv.scala 325:19] - wire [31:0] dbg_io_dmi_reg_wdata; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_awvalid; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_awready; // @[el2_swerv.scala 325:19] - wire [31:0] dbg_io_sb_axi_awaddr; // @[el2_swerv.scala 325:19] - wire [3:0] dbg_io_sb_axi_awregion; // @[el2_swerv.scala 325:19] - wire [2:0] dbg_io_sb_axi_awsize; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_wvalid; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_wready; // @[el2_swerv.scala 325:19] - wire [63:0] dbg_io_sb_axi_wdata; // @[el2_swerv.scala 325:19] - wire [7:0] dbg_io_sb_axi_wstrb; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_bvalid; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_bready; // @[el2_swerv.scala 325:19] - wire [1:0] dbg_io_sb_axi_bresp; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_arvalid; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_arready; // @[el2_swerv.scala 325:19] - wire [31:0] dbg_io_sb_axi_araddr; // @[el2_swerv.scala 325:19] - wire [3:0] dbg_io_sb_axi_arregion; // @[el2_swerv.scala 325:19] - wire [2:0] dbg_io_sb_axi_arsize; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_rvalid; // @[el2_swerv.scala 325:19] - wire dbg_io_sb_axi_rready; // @[el2_swerv.scala 325:19] - wire [63:0] dbg_io_sb_axi_rdata; // @[el2_swerv.scala 325:19] - wire [1:0] dbg_io_sb_axi_rresp; // @[el2_swerv.scala 325:19] - wire dbg_io_dbg_bus_clk_en; // @[el2_swerv.scala 325:19] - wire dbg_io_dbg_rst_l; // @[el2_swerv.scala 325:19] - wire dbg_io_clk_override; // @[el2_swerv.scala 325:19] - wire dbg_io_scan_mode; // @[el2_swerv.scala 325:19] - wire exu_clock; // @[el2_swerv.scala 326:19] - wire exu_reset; // @[el2_swerv.scala 326:19] - wire exu_io_scan_mode; // @[el2_swerv.scala 326:19] - wire [1:0] exu_io_dec_data_en; // @[el2_swerv.scala 326:19] - wire [1:0] exu_io_dec_ctl_en; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_dbg_cmd_wrdata; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_land; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_lor; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_lxor; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_sll; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_srl; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_sra; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_beq; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_bne; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_blt; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_bge; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_add; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_sub; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_slt; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_unsign; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_jal; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_predict_t; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_predict_nt; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_csr_write; // @[el2_swerv.scala 326:19] - wire exu_io_i0_ap_csr_imm; // @[el2_swerv.scala 326:19] - wire exu_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_predict_p_d_valid; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_predict_p_d_bits_pc4; // @[el2_swerv.scala 326:19] - wire [1:0] exu_io_dec_i0_predict_p_d_bits_hist; // @[el2_swerv.scala 326:19] - wire [11:0] exu_io_dec_i0_predict_p_d_bits_toffset; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_predict_p_d_bits_br_error; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_swerv.scala 326:19] - wire [30:0] exu_io_dec_i0_predict_p_d_bits_prett; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_predict_p_d_bits_pcall; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_predict_p_d_bits_pret; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 326:19] - wire [7:0] exu_io_i0_predict_fghr_d; // @[el2_swerv.scala 326:19] - wire [7:0] exu_io_i0_predict_index_d; // @[el2_swerv.scala 326:19] - wire [4:0] exu_io_i0_predict_btag_d; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_gpr_i0_rs1_d; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_gpr_i0_rs2_d; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_dec_i0_immed_d; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 326:19] - wire [11:0] exu_io_dec_i0_br_immed_d; // @[el2_swerv.scala 326:19] - wire exu_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 326:19] - wire [1:0] exu_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 326:19] - wire [1:0] exu_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 326:19] - wire exu_io_dec_csr_ren_d; // @[el2_swerv.scala 326:19] - wire exu_io_mul_p_valid; // @[el2_swerv.scala 326:19] - wire exu_io_mul_p_bits_rs1_sign; // @[el2_swerv.scala 326:19] - wire exu_io_mul_p_bits_rs2_sign; // @[el2_swerv.scala 326:19] - wire exu_io_mul_p_bits_low; // @[el2_swerv.scala 326:19] - wire exu_io_div_p_valid; // @[el2_swerv.scala 326:19] - wire exu_io_div_p_bits_unsign; // @[el2_swerv.scala 326:19] - wire exu_io_div_p_bits_rem; // @[el2_swerv.scala 326:19] - wire exu_io_dec_div_cancel; // @[el2_swerv.scala 326:19] - wire [30:0] exu_io_pred_correct_npc_x; // @[el2_swerv.scala 326:19] - wire exu_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 326:19] - wire [30:0] exu_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 326:19] - wire exu_io_dec_extint_stall; // @[el2_swerv.scala 326:19] - wire [29:0] exu_io_dec_tlu_meihap; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_exu_lsu_rs1_d; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_exu_lsu_rs2_d; // @[el2_swerv.scala 326:19] - wire exu_io_exu_flush_final; // @[el2_swerv.scala 326:19] - wire [30:0] exu_io_exu_flush_path_final; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_exu_i0_result_x; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_exu_csr_rs1_x; // @[el2_swerv.scala 326:19] - wire [30:0] exu_io_exu_npc_r; // @[el2_swerv.scala 326:19] - wire [1:0] exu_io_exu_i0_br_hist_r; // @[el2_swerv.scala 326:19] - wire exu_io_exu_i0_br_error_r; // @[el2_swerv.scala 326:19] - wire exu_io_exu_i0_br_start_error_r; // @[el2_swerv.scala 326:19] - wire [7:0] exu_io_exu_i0_br_index_r; // @[el2_swerv.scala 326:19] - wire exu_io_exu_i0_br_valid_r; // @[el2_swerv.scala 326:19] - wire exu_io_exu_i0_br_mp_r; // @[el2_swerv.scala 326:19] - wire exu_io_exu_i0_br_middle_r; // @[el2_swerv.scala 326:19] - wire [7:0] exu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 326:19] - wire exu_io_exu_i0_br_way_r; // @[el2_swerv.scala 326:19] - wire exu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 326:19] - wire exu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 326:19] - wire exu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 326:19] - wire [1:0] exu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 326:19] - wire [11:0] exu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 326:19] - wire exu_io_exu_mp_pkt_bits_pcall; // @[el2_swerv.scala 326:19] - wire exu_io_exu_mp_pkt_bits_pret; // @[el2_swerv.scala 326:19] - wire exu_io_exu_mp_pkt_bits_pja; // @[el2_swerv.scala 326:19] - wire exu_io_exu_mp_pkt_bits_way; // @[el2_swerv.scala 326:19] - wire [7:0] exu_io_exu_mp_eghr; // @[el2_swerv.scala 326:19] - wire [7:0] exu_io_exu_mp_fghr; // @[el2_swerv.scala 326:19] - wire [7:0] exu_io_exu_mp_index; // @[el2_swerv.scala 326:19] - wire [4:0] exu_io_exu_mp_btag; // @[el2_swerv.scala 326:19] - wire exu_io_exu_pmu_i0_br_misp; // @[el2_swerv.scala 326:19] - wire exu_io_exu_pmu_i0_br_ataken; // @[el2_swerv.scala 326:19] - wire exu_io_exu_pmu_i0_pc4; // @[el2_swerv.scala 326:19] - wire [31:0] exu_io_exu_div_result; // @[el2_swerv.scala 326:19] - wire exu_io_exu_div_wren; // @[el2_swerv.scala 326:19] - wire lsu_clock; // @[el2_swerv.scala 327:19] - wire lsu_reset; // @[el2_swerv.scala 327:19] - wire lsu_io_clk_override; // @[el2_swerv.scala 327:19] - wire lsu_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 327:19] - wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 327:19] - wire lsu_io_dec_tlu_force_halt; // @[el2_swerv.scala 327:19] - wire lsu_io_dec_tlu_external_ldfwd_disable; // @[el2_swerv.scala 327:19] - wire lsu_io_dec_tlu_wb_coalescing_disable; // @[el2_swerv.scala 327:19] - wire lsu_io_dec_tlu_sideeffect_posted_disable; // @[el2_swerv.scala 327:19] - wire lsu_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_exu_lsu_rs1_d; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_exu_lsu_rs2_d; // @[el2_swerv.scala 327:19] - wire [11:0] lsu_io_dec_lsu_offset_d; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_valid; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_bits_fast_int; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_bits_by; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_bits_half; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_bits_word; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_bits_load; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_bits_store; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_bits_unsign; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_0_match_; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_1_match_; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_2_match_; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_3_match_; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 327:19] - wire lsu_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 327:19] - wire lsu_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_lsu_result_m; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_lsu_result_corr_r; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_load_stall_any; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_store_stall_any; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_fastint_stall_any; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_idle_any; // @[el2_swerv.scala 327:19] - wire [30:0] lsu_io_lsu_fir_addr; // @[el2_swerv.scala 327:19] - wire [1:0] lsu_io_lsu_fir_error; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_nonblock_load_valid_m; // @[el2_swerv.scala 327:19] - wire [1:0] lsu_io_lsu_nonblock_load_tag_m; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_nonblock_load_inv_r; // @[el2_swerv.scala 327:19] - wire [1:0] lsu_io_lsu_nonblock_load_inv_tag_r; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_nonblock_load_data_valid; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_nonblock_load_data_error; // @[el2_swerv.scala 327:19] - wire [1:0] lsu_io_lsu_nonblock_load_data_tag; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_lsu_nonblock_load_data; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_pmu_load_external_m; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_pmu_store_external_m; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_pmu_bus_trxn; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_pmu_bus_misaligned; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_pmu_bus_error; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_pmu_bus_busy; // @[el2_swerv.scala 327:19] - wire [3:0] lsu_io_lsu_trigger_match_m; // @[el2_swerv.scala 327:19] - wire lsu_io_dccm_wren; // @[el2_swerv.scala 327:19] - wire lsu_io_dccm_rden; // @[el2_swerv.scala 327:19] - wire [15:0] lsu_io_dccm_wr_addr_lo; // @[el2_swerv.scala 327:19] - wire [15:0] lsu_io_dccm_wr_addr_hi; // @[el2_swerv.scala 327:19] - wire [15:0] lsu_io_dccm_rd_addr_lo; // @[el2_swerv.scala 327:19] - wire [15:0] lsu_io_dccm_rd_addr_hi; // @[el2_swerv.scala 327:19] - wire [38:0] lsu_io_dccm_wr_data_lo; // @[el2_swerv.scala 327:19] - wire [38:0] lsu_io_dccm_wr_data_hi; // @[el2_swerv.scala 327:19] - wire [38:0] lsu_io_dccm_rd_data_lo; // @[el2_swerv.scala 327:19] - wire [38:0] lsu_io_dccm_rd_data_hi; // @[el2_swerv.scala 327:19] - wire lsu_io_picm_wren; // @[el2_swerv.scala 327:19] - wire lsu_io_picm_rden; // @[el2_swerv.scala 327:19] - wire lsu_io_picm_mken; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_picm_rdaddr; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_picm_wraddr; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_picm_wr_data; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_picm_rd_data; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_axi_awvalid; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_axi_awready; // @[el2_swerv.scala 327:19] - wire [2:0] lsu_io_lsu_axi_awid; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_lsu_axi_awaddr; // @[el2_swerv.scala 327:19] - wire [3:0] lsu_io_lsu_axi_awregion; // @[el2_swerv.scala 327:19] - wire [2:0] lsu_io_lsu_axi_awsize; // @[el2_swerv.scala 327:19] - wire [3:0] lsu_io_lsu_axi_awcache; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_axi_wvalid; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_axi_wready; // @[el2_swerv.scala 327:19] - wire [63:0] lsu_io_lsu_axi_wdata; // @[el2_swerv.scala 327:19] - wire [7:0] lsu_io_lsu_axi_wstrb; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_axi_bvalid; // @[el2_swerv.scala 327:19] - wire [1:0] lsu_io_lsu_axi_bresp; // @[el2_swerv.scala 327:19] - wire [2:0] lsu_io_lsu_axi_bid; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_axi_arvalid; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_axi_arready; // @[el2_swerv.scala 327:19] - wire [2:0] lsu_io_lsu_axi_arid; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_lsu_axi_araddr; // @[el2_swerv.scala 327:19] - wire [3:0] lsu_io_lsu_axi_arregion; // @[el2_swerv.scala 327:19] - wire [2:0] lsu_io_lsu_axi_arsize; // @[el2_swerv.scala 327:19] - wire [3:0] lsu_io_lsu_axi_arcache; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_axi_rvalid; // @[el2_swerv.scala 327:19] - wire [63:0] lsu_io_lsu_axi_rdata; // @[el2_swerv.scala 327:19] - wire [2:0] lsu_io_lsu_axi_rid; // @[el2_swerv.scala 327:19] - wire lsu_io_lsu_bus_clk_en; // @[el2_swerv.scala 327:19] - wire lsu_io_dma_dccm_req; // @[el2_swerv.scala 327:19] - wire lsu_io_dma_mem_write; // @[el2_swerv.scala 327:19] - wire lsu_io_dccm_dma_rvalid; // @[el2_swerv.scala 327:19] - wire lsu_io_dccm_dma_ecc_error; // @[el2_swerv.scala 327:19] - wire [2:0] lsu_io_dma_mem_tag; // @[el2_swerv.scala 327:19] - wire [31:0] lsu_io_dma_mem_addr; // @[el2_swerv.scala 327:19] - wire [2:0] lsu_io_dma_mem_sz; // @[el2_swerv.scala 327:19] - wire [63:0] lsu_io_dma_mem_wdata; // @[el2_swerv.scala 327:19] - wire [2:0] lsu_io_dccm_dma_rtag; // @[el2_swerv.scala 327:19] - wire [63:0] lsu_io_dccm_dma_rdata; // @[el2_swerv.scala 327:19] - wire lsu_io_dccm_ready; // @[el2_swerv.scala 327:19] - wire lsu_io_scan_mode; // @[el2_swerv.scala 327:19] - wire lsu_io_free_clk; // @[el2_swerv.scala 327:19] - wire pic_ctl_inst_clock; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_reset; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_io_scan_mode; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_io_free_clk; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_io_active_clk; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_io_clk_override; // @[el2_swerv.scala 328:28] - wire [31:0] pic_ctl_inst_io_extintsrc_req; // @[el2_swerv.scala 328:28] - wire [31:0] pic_ctl_inst_io_picm_rdaddr; // @[el2_swerv.scala 328:28] - wire [31:0] pic_ctl_inst_io_picm_wraddr; // @[el2_swerv.scala 328:28] - wire [31:0] pic_ctl_inst_io_picm_wr_data; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_io_picm_wren; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_io_picm_rden; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_io_picm_mken; // @[el2_swerv.scala 328:28] - wire [3:0] pic_ctl_inst_io_meicurpl; // @[el2_swerv.scala 328:28] - wire [3:0] pic_ctl_inst_io_meipt; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_io_mexintpend; // @[el2_swerv.scala 328:28] - wire [7:0] pic_ctl_inst_io_claimid; // @[el2_swerv.scala 328:28] - wire [3:0] pic_ctl_inst_io_pl; // @[el2_swerv.scala 328:28] - wire [31:0] pic_ctl_inst_io_picm_rd_data; // @[el2_swerv.scala 328:28] - wire pic_ctl_inst_io_mhwakeup; // @[el2_swerv.scala 328:28] - wire dma_ctrl_clock; // @[el2_swerv.scala 329:24] - wire dma_ctrl_reset; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_free_clk; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_bus_clk_en; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_clk_override; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_scan_mode; // @[el2_swerv.scala 329:24] - wire [31:0] dma_ctrl_io_dbg_cmd_addr; // @[el2_swerv.scala 329:24] - wire [31:0] dma_ctrl_io_dbg_cmd_wrdata; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dbg_cmd_valid; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dbg_cmd_write; // @[el2_swerv.scala 329:24] - wire [1:0] dma_ctrl_io_dbg_cmd_type; // @[el2_swerv.scala 329:24] - wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dbg_dma_bubble; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_dbg_ready; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_dbg_cmd_done; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_dbg_cmd_fail; // @[el2_swerv.scala 329:24] - wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_dccm_req; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_iccm_req; // @[el2_swerv.scala 329:24] - wire [2:0] dma_ctrl_io_dma_mem_tag; // @[el2_swerv.scala 329:24] - wire [31:0] dma_ctrl_io_dma_mem_addr; // @[el2_swerv.scala 329:24] - wire [2:0] dma_ctrl_io_dma_mem_sz; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_mem_write; // @[el2_swerv.scala 329:24] - wire [63:0] dma_ctrl_io_dma_mem_wdata; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dccm_dma_rvalid; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dccm_dma_ecc_error; // @[el2_swerv.scala 329:24] - wire [2:0] dma_ctrl_io_dccm_dma_rtag; // @[el2_swerv.scala 329:24] - wire [63:0] dma_ctrl_io_dccm_dma_rdata; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_iccm_dma_rvalid; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_iccm_dma_ecc_error; // @[el2_swerv.scala 329:24] - wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[el2_swerv.scala 329:24] - wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_dccm_stall_any; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dccm_ready; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_iccm_ready; // @[el2_swerv.scala 329:24] - wire [2:0] dma_ctrl_io_dec_tlu_dma_qos_prty; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_pmu_dccm_read; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_pmu_dccm_write; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_pmu_any_read; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_pmu_any_write; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_awvalid; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_awready; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_awid; // @[el2_swerv.scala 329:24] - wire [31:0] dma_ctrl_io_dma_axi_awaddr; // @[el2_swerv.scala 329:24] - wire [2:0] dma_ctrl_io_dma_axi_awsize; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_wvalid; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_wready; // @[el2_swerv.scala 329:24] - wire [63:0] dma_ctrl_io_dma_axi_wdata; // @[el2_swerv.scala 329:24] - wire [7:0] dma_ctrl_io_dma_axi_wstrb; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_bvalid; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_bready; // @[el2_swerv.scala 329:24] - wire [1:0] dma_ctrl_io_dma_axi_bresp; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_bid; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_arvalid; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_arready; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_arid; // @[el2_swerv.scala 329:24] - wire [31:0] dma_ctrl_io_dma_axi_araddr; // @[el2_swerv.scala 329:24] - wire [2:0] dma_ctrl_io_dma_axi_arsize; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_rvalid; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_rready; // @[el2_swerv.scala 329:24] - wire dma_ctrl_io_dma_axi_rid; // @[el2_swerv.scala 329:24] - wire [63:0] dma_ctrl_io_dma_axi_rdata; // @[el2_swerv.scala 329:24] - wire [1:0] dma_ctrl_io_dma_axi_rresp; // @[el2_swerv.scala 329:24] + wire ifu_clock; // @[el2_swerv.scala 321:19] + wire ifu_reset; // @[el2_swerv.scala 321:19] + wire ifu_io_free_clk; // @[el2_swerv.scala 321:19] + wire ifu_io_active_clk; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_i0_decode_d; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_flush_final; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_i0_commit_cmt; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_flush_err_wb; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_flush_noredir_wb; // @[el2_swerv.scala 321:19] + wire [30:0] ifu_io_exu_flush_path_final; // @[el2_swerv.scala 321:19] + wire [31:0] ifu_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_fence_i_wb; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_flush_leak_one_wb; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_bpred_disable; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_force_halt; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_axi_arvalid; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_axi_arready; // @[el2_swerv.scala 321:19] + wire [2:0] ifu_io_ifu_axi_arid; // @[el2_swerv.scala 321:19] + wire [31:0] ifu_io_ifu_axi_araddr; // @[el2_swerv.scala 321:19] + wire [3:0] ifu_io_ifu_axi_arregion; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_axi_rvalid; // @[el2_swerv.scala 321:19] + wire [2:0] ifu_io_ifu_axi_rid; // @[el2_swerv.scala 321:19] + wire [63:0] ifu_io_ifu_axi_rdata; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_ifu_axi_rresp; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_bus_clk_en; // @[el2_swerv.scala 321:19] + wire ifu_io_dma_iccm_req; // @[el2_swerv.scala 321:19] + wire [31:0] ifu_io_dma_mem_addr; // @[el2_swerv.scala 321:19] + wire [2:0] ifu_io_dma_mem_sz; // @[el2_swerv.scala 321:19] + wire ifu_io_dma_mem_write; // @[el2_swerv.scala 321:19] + wire [63:0] ifu_io_dma_mem_wdata; // @[el2_swerv.scala 321:19] + wire [2:0] ifu_io_dma_mem_tag; // @[el2_swerv.scala 321:19] + wire ifu_io_dma_iccm_stall_any; // @[el2_swerv.scala 321:19] + wire ifu_io_iccm_dma_ecc_error; // @[el2_swerv.scala 321:19] + wire ifu_io_iccm_dma_rvalid; // @[el2_swerv.scala 321:19] + wire [63:0] ifu_io_iccm_dma_rdata; // @[el2_swerv.scala 321:19] + wire [2:0] ifu_io_iccm_dma_rtag; // @[el2_swerv.scala 321:19] + wire ifu_io_iccm_ready; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_ic_error_start; // @[el2_swerv.scala 321:19] + wire [30:0] ifu_io_ic_rw_addr; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_ic_wr_en; // @[el2_swerv.scala 321:19] + wire ifu_io_ic_rd_en; // @[el2_swerv.scala 321:19] + wire [70:0] ifu_io_ic_wr_data_0; // @[el2_swerv.scala 321:19] + wire [70:0] ifu_io_ic_wr_data_1; // @[el2_swerv.scala 321:19] + wire [63:0] ifu_io_ic_rd_data; // @[el2_swerv.scala 321:19] + wire [70:0] ifu_io_ic_debug_rd_data; // @[el2_swerv.scala 321:19] + wire [25:0] ifu_io_ictag_debug_rd_data; // @[el2_swerv.scala 321:19] + wire [70:0] ifu_io_ic_debug_wr_data; // @[el2_swerv.scala 321:19] + wire [70:0] ifu_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_ic_eccerr; // @[el2_swerv.scala 321:19] + wire [63:0] ifu_io_ic_premux_data; // @[el2_swerv.scala 321:19] + wire ifu_io_ic_sel_premux_data; // @[el2_swerv.scala 321:19] + wire [9:0] ifu_io_ic_debug_addr; // @[el2_swerv.scala 321:19] + wire ifu_io_ic_debug_rd_en; // @[el2_swerv.scala 321:19] + wire ifu_io_ic_debug_wr_en; // @[el2_swerv.scala 321:19] + wire ifu_io_ic_debug_tag_array; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_ic_debug_way; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_ic_tag_valid; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_ic_rd_hit; // @[el2_swerv.scala 321:19] + wire ifu_io_ic_tag_perr; // @[el2_swerv.scala 321:19] + wire [14:0] ifu_io_iccm_rw_addr; // @[el2_swerv.scala 321:19] + wire ifu_io_iccm_wren; // @[el2_swerv.scala 321:19] + wire ifu_io_iccm_rden; // @[el2_swerv.scala 321:19] + wire [77:0] ifu_io_iccm_wr_data; // @[el2_swerv.scala 321:19] + wire [2:0] ifu_io_iccm_wr_size; // @[el2_swerv.scala 321:19] + wire [63:0] ifu_io_iccm_rd_data; // @[el2_swerv.scala 321:19] + wire [77:0] ifu_io_iccm_rd_data_ecc; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_iccm_rd_ecc_single_err; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_pmu_ic_miss; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_pmu_ic_hit; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_pmu_bus_error; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_pmu_bus_busy; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_pmu_bus_trxn; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_i0_icaf; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_ifu_i0_icaf_type; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_i0_valid; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_i0_icaf_f1; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_i0_dbecc; // @[el2_swerv.scala 321:19] + wire ifu_io_iccm_dma_sb_error; // @[el2_swerv.scala 321:19] + wire [31:0] ifu_io_ifu_i0_instr; // @[el2_swerv.scala 321:19] + wire [30:0] ifu_io_ifu_i0_pc; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_i0_pc4; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_miss_state_idle; // @[el2_swerv.scala 321:19] + wire ifu_io_i0_brp_valid; // @[el2_swerv.scala 321:19] + wire [11:0] ifu_io_i0_brp_toffset; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_i0_brp_hist; // @[el2_swerv.scala 321:19] + wire ifu_io_i0_brp_br_error; // @[el2_swerv.scala 321:19] + wire ifu_io_i0_brp_br_start_error; // @[el2_swerv.scala 321:19] + wire [30:0] ifu_io_i0_brp_prett; // @[el2_swerv.scala 321:19] + wire ifu_io_i0_brp_way; // @[el2_swerv.scala 321:19] + wire ifu_io_i0_brp_ret; // @[el2_swerv.scala 321:19] + wire [7:0] ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 321:19] + wire [7:0] ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 321:19] + wire [4:0] ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_mp_pkt_bits_boffset; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 321:19] + wire [11:0] ifu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_mp_pkt_bits_pcall; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_mp_pkt_bits_pret; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_mp_pkt_bits_pja; // @[el2_swerv.scala 321:19] + wire ifu_io_exu_mp_pkt_bits_way; // @[el2_swerv.scala 321:19] + wire [7:0] ifu_io_exu_mp_eghr; // @[el2_swerv.scala 321:19] + wire [7:0] ifu_io_exu_mp_fghr; // @[el2_swerv.scala 321:19] + wire [7:0] ifu_io_exu_mp_index; // @[el2_swerv.scala 321:19] + wire [4:0] ifu_io_exu_mp_btag; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 321:19] + wire [7:0] ifu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 321:19] + wire [7:0] ifu_io_exu_i0_br_index_r; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_flush_lower_wb; // @[el2_swerv.scala 321:19] + wire [15:0] ifu_io_ifu_i0_cinst; // @[el2_swerv.scala 321:19] + wire [70:0] ifu_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 321:19] + wire [16:0] ifu_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_swerv.scala 321:19] + wire ifu_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 321:19] + wire ifu_io_iccm_buf_correct_ecc; // @[el2_swerv.scala 321:19] + wire ifu_io_iccm_correction_state; // @[el2_swerv.scala 321:19] + wire ifu_io_scan_mode; // @[el2_swerv.scala 321:19] + wire dec_clock; // @[el2_swerv.scala 322:19] + wire dec_reset; // @[el2_swerv.scala 322:19] + wire dec_io_free_clk; // @[el2_swerv.scala 322:19] + wire dec_io_active_clk; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_fastint_stall_any; // @[el2_swerv.scala 322:19] + wire dec_io_dec_extint_stall; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_decode_d; // @[el2_swerv.scala 322:19] + wire dec_io_dec_pause_state_cg; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_rst_vec; // @[el2_swerv.scala 322:19] + wire dec_io_nmi_int; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_nmi_vec; // @[el2_swerv.scala 322:19] + wire dec_io_i_cpu_halt_req; // @[el2_swerv.scala 322:19] + wire dec_io_i_cpu_run_req; // @[el2_swerv.scala 322:19] + wire dec_io_o_cpu_halt_status; // @[el2_swerv.scala 322:19] + wire dec_io_o_cpu_halt_ack; // @[el2_swerv.scala 322:19] + wire dec_io_o_cpu_run_ack; // @[el2_swerv.scala 322:19] + wire dec_io_o_debug_mode_status; // @[el2_swerv.scala 322:19] + wire [27:0] dec_io_core_id; // @[el2_swerv.scala 322:19] + wire dec_io_mpc_debug_halt_req; // @[el2_swerv.scala 322:19] + wire dec_io_mpc_debug_run_req; // @[el2_swerv.scala 322:19] + wire dec_io_mpc_reset_run_req; // @[el2_swerv.scala 322:19] + wire dec_io_mpc_debug_halt_ack; // @[el2_swerv.scala 322:19] + wire dec_io_mpc_debug_run_ack; // @[el2_swerv.scala 322:19] + wire dec_io_debug_brkpt_status; // @[el2_swerv.scala 322:19] + wire dec_io_exu_pmu_i0_br_misp; // @[el2_swerv.scala 322:19] + wire dec_io_exu_pmu_i0_br_ataken; // @[el2_swerv.scala 322:19] + wire dec_io_exu_pmu_i0_pc4; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_nonblock_load_valid_m; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_lsu_nonblock_load_tag_m; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_nonblock_load_inv_r; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_lsu_nonblock_load_inv_tag_r; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_nonblock_load_data_valid; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_nonblock_load_data_error; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_lsu_nonblock_load_data_tag; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_lsu_nonblock_load_data; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_pmu_bus_trxn; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_pmu_bus_misaligned; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_pmu_bus_error; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_pmu_bus_busy; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_pmu_load_external_m; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_pmu_store_external_m; // @[el2_swerv.scala 322:19] + wire dec_io_dma_pmu_dccm_read; // @[el2_swerv.scala 322:19] + wire dec_io_dma_pmu_dccm_write; // @[el2_swerv.scala 322:19] + wire dec_io_dma_pmu_any_read; // @[el2_swerv.scala 322:19] + wire dec_io_dma_pmu_any_write; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_lsu_fir_addr; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_lsu_fir_error; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_pmu_ic_miss; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_pmu_ic_hit; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_pmu_bus_error; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_pmu_bus_busy; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_pmu_bus_trxn; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_ic_error_start; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_iccm_rd_ecc_single_err; // @[el2_swerv.scala 322:19] + wire [3:0] dec_io_lsu_trigger_match_m; // @[el2_swerv.scala 322:19] + wire dec_io_dbg_cmd_valid; // @[el2_swerv.scala 322:19] + wire dec_io_dbg_cmd_write; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_dbg_cmd_type; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_dbg_cmd_addr; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_dbg_cmd_wrdata; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_i0_icaf; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_ifu_i0_icaf_type; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_i0_icaf_f1; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_i0_dbecc; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_idle_any; // @[el2_swerv.scala 322:19] + wire dec_io_i0_brp_valid; // @[el2_swerv.scala 322:19] + wire [11:0] dec_io_i0_brp_toffset; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_i0_brp_hist; // @[el2_swerv.scala 322:19] + wire dec_io_i0_brp_br_error; // @[el2_swerv.scala 322:19] + wire dec_io_i0_brp_br_start_error; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_i0_brp_prett; // @[el2_swerv.scala 322:19] + wire dec_io_i0_brp_way; // @[el2_swerv.scala 322:19] + wire dec_io_i0_brp_ret; // @[el2_swerv.scala 322:19] + wire [7:0] dec_io_ifu_i0_bp_index; // @[el2_swerv.scala 322:19] + wire [7:0] dec_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 322:19] + wire [4:0] dec_io_ifu_i0_bp_btag; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 322:19] + wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_exu_div_result; // @[el2_swerv.scala 322:19] + wire dec_io_exu_div_wren; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_exu_csr_rs1_x; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_lsu_result_m; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_lsu_result_corr_r; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_load_stall_any; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_store_stall_any; // @[el2_swerv.scala 322:19] + wire dec_io_dma_dccm_stall_any; // @[el2_swerv.scala 322:19] + wire dec_io_dma_iccm_stall_any; // @[el2_swerv.scala 322:19] + wire dec_io_iccm_dma_sb_error; // @[el2_swerv.scala 322:19] + wire dec_io_exu_flush_final; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_exu_npc_r; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_exu_i0_result_x; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_i0_valid; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_ifu_i0_instr; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_ifu_i0_pc; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_i0_pc4; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_exu_i0_pc_x; // @[el2_swerv.scala 322:19] + wire dec_io_mexintpend; // @[el2_swerv.scala 322:19] + wire dec_io_timer_int; // @[el2_swerv.scala 322:19] + wire dec_io_soft_int; // @[el2_swerv.scala 322:19] + wire [7:0] dec_io_pic_claimid; // @[el2_swerv.scala 322:19] + wire [3:0] dec_io_pic_pl; // @[el2_swerv.scala 322:19] + wire dec_io_mhwakeup; // @[el2_swerv.scala 322:19] + wire [3:0] dec_io_dec_tlu_meicurpl; // @[el2_swerv.scala 322:19] + wire [3:0] dec_io_dec_tlu_meipt; // @[el2_swerv.scala 322:19] + wire [70:0] dec_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 322:19] + wire [70:0] dec_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 322:19] + wire [16:0] dec_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_swerv.scala 322:19] + wire dec_io_dbg_halt_req; // @[el2_swerv.scala 322:19] + wire dec_io_dbg_resume_req; // @[el2_swerv.scala 322:19] + wire dec_io_ifu_miss_state_idle; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_dbg_halted; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_debug_mode; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_resume_ack; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_flush_noredir_r; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_flush_leak_one_r; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_flush_err_r; // @[el2_swerv.scala 322:19] + wire [29:0] dec_io_dec_tlu_meihap; // @[el2_swerv.scala 322:19] + wire dec_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_dec_dbg_rddata; // @[el2_swerv.scala 322:19] + wire dec_io_dec_dbg_cmd_done; // @[el2_swerv.scala 322:19] + wire dec_io_dec_dbg_cmd_fail; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_0_match_pkt; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_1_match_pkt; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_2_match_pkt; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_3_match_pkt; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_force_halt; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_exu_i0_br_hist_r; // @[el2_swerv.scala 322:19] + wire dec_io_exu_i0_br_error_r; // @[el2_swerv.scala 322:19] + wire dec_io_exu_i0_br_start_error_r; // @[el2_swerv.scala 322:19] + wire dec_io_exu_i0_br_valid_r; // @[el2_swerv.scala 322:19] + wire dec_io_exu_i0_br_mp_r; // @[el2_swerv.scala 322:19] + wire dec_io_exu_i0_br_middle_r; // @[el2_swerv.scala 322:19] + wire dec_io_exu_i0_br_way_r; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_gpr_i0_rs1_d; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_gpr_i0_rs2_d; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_dec_i0_immed_d; // @[el2_swerv.scala 322:19] + wire [11:0] dec_io_dec_i0_br_immed_d; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_land; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_lor; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_lxor; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_sll; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_srl; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_sra; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_beq; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_bne; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_blt; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_bge; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_add; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_sub; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_slt; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_unsign; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_jal; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_predict_t; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_predict_nt; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_csr_write; // @[el2_swerv.scala 322:19] + wire dec_io_i0_ap_csr_imm; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_select_pc_d; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_dec_i0_pc_d; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_valid; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_bits_fast_int; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_bits_by; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_bits_half; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_bits_word; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_bits_load; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_bits_store; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_bits_unsign; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 322:19] + wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 322:19] + wire dec_io_mul_p_valid; // @[el2_swerv.scala 322:19] + wire dec_io_mul_p_bits_rs1_sign; // @[el2_swerv.scala 322:19] + wire dec_io_mul_p_bits_rs2_sign; // @[el2_swerv.scala 322:19] + wire dec_io_mul_p_bits_low; // @[el2_swerv.scala 322:19] + wire dec_io_div_p_valid; // @[el2_swerv.scala 322:19] + wire dec_io_div_p_bits_unsign; // @[el2_swerv.scala 322:19] + wire dec_io_div_p_bits_rem; // @[el2_swerv.scala 322:19] + wire dec_io_dec_div_cancel; // @[el2_swerv.scala 322:19] + wire [11:0] dec_io_dec_lsu_offset_d; // @[el2_swerv.scala 322:19] + wire dec_io_dec_csr_ren_d; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_fence_i_r; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_pred_correct_npc_x; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_perfcnt0; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_perfcnt1; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_perfcnt2; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_perfcnt3; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_predict_p_d_valid; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_predict_p_d_bits_pc4; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_dec_i0_predict_p_d_bits_hist; // @[el2_swerv.scala 322:19] + wire [11:0] dec_io_dec_i0_predict_p_d_bits_toffset; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_predict_p_d_bits_br_error; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_dec_i0_predict_p_d_bits_prett; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_predict_p_d_bits_pcall; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_predict_p_d_bits_pret; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 322:19] + wire dec_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 322:19] + wire [7:0] dec_io_i0_predict_fghr_d; // @[el2_swerv.scala 322:19] + wire [7:0] dec_io_i0_predict_index_d; // @[el2_swerv.scala 322:19] + wire [4:0] dec_io_i0_predict_btag_d; // @[el2_swerv.scala 322:19] + wire dec_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_dec_data_en; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_dec_ctl_en; // @[el2_swerv.scala 322:19] + wire [15:0] dec_io_ifu_i0_cinst; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[el2_swerv.scala 322:19] + wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_external_ldfwd_disable; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_sideeffect_posted_disable; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_bpred_disable; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_wb_coalescing_disable; // @[el2_swerv.scala 322:19] + wire [2:0] dec_io_dec_tlu_dma_qos_prty; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_misc_clk_override; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_lsu_clk_override; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_pic_clk_override; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_dccm_clk_override; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_icm_clk_override; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_i0_commit_cmt; // @[el2_swerv.scala 322:19] + wire dec_io_scan_mode; // @[el2_swerv.scala 322:19] + wire dbg_clock; // @[el2_swerv.scala 323:19] + wire dbg_reset; // @[el2_swerv.scala 323:19] + wire [31:0] dbg_io_dbg_cmd_addr; // @[el2_swerv.scala 323:19] + wire [31:0] dbg_io_dbg_cmd_wrdata; // @[el2_swerv.scala 323:19] + wire dbg_io_dbg_cmd_valid; // @[el2_swerv.scala 323:19] + wire dbg_io_dbg_cmd_write; // @[el2_swerv.scala 323:19] + wire [1:0] dbg_io_dbg_cmd_type; // @[el2_swerv.scala 323:19] + wire [1:0] dbg_io_dbg_cmd_size; // @[el2_swerv.scala 323:19] + wire dbg_io_dbg_core_rst_l; // @[el2_swerv.scala 323:19] + wire [31:0] dbg_io_core_dbg_rddata; // @[el2_swerv.scala 323:19] + wire dbg_io_core_dbg_cmd_done; // @[el2_swerv.scala 323:19] + wire dbg_io_core_dbg_cmd_fail; // @[el2_swerv.scala 323:19] + wire dbg_io_dbg_dma_bubble; // @[el2_swerv.scala 323:19] + wire dbg_io_dma_dbg_ready; // @[el2_swerv.scala 323:19] + wire dbg_io_dbg_halt_req; // @[el2_swerv.scala 323:19] + wire dbg_io_dbg_resume_req; // @[el2_swerv.scala 323:19] + wire dbg_io_dec_tlu_debug_mode; // @[el2_swerv.scala 323:19] + wire dbg_io_dec_tlu_dbg_halted; // @[el2_swerv.scala 323:19] + wire dbg_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 323:19] + wire dbg_io_dec_tlu_resume_ack; // @[el2_swerv.scala 323:19] + wire dbg_io_dmi_reg_en; // @[el2_swerv.scala 323:19] + wire [6:0] dbg_io_dmi_reg_addr; // @[el2_swerv.scala 323:19] + wire dbg_io_dmi_reg_wr_en; // @[el2_swerv.scala 323:19] + wire [31:0] dbg_io_dmi_reg_wdata; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_awvalid; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_awready; // @[el2_swerv.scala 323:19] + wire [31:0] dbg_io_sb_axi_awaddr; // @[el2_swerv.scala 323:19] + wire [3:0] dbg_io_sb_axi_awregion; // @[el2_swerv.scala 323:19] + wire [2:0] dbg_io_sb_axi_awsize; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_wvalid; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_wready; // @[el2_swerv.scala 323:19] + wire [63:0] dbg_io_sb_axi_wdata; // @[el2_swerv.scala 323:19] + wire [7:0] dbg_io_sb_axi_wstrb; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_bvalid; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_bready; // @[el2_swerv.scala 323:19] + wire [1:0] dbg_io_sb_axi_bresp; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_arvalid; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_arready; // @[el2_swerv.scala 323:19] + wire [31:0] dbg_io_sb_axi_araddr; // @[el2_swerv.scala 323:19] + wire [3:0] dbg_io_sb_axi_arregion; // @[el2_swerv.scala 323:19] + wire [2:0] dbg_io_sb_axi_arsize; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_rvalid; // @[el2_swerv.scala 323:19] + wire dbg_io_sb_axi_rready; // @[el2_swerv.scala 323:19] + wire [63:0] dbg_io_sb_axi_rdata; // @[el2_swerv.scala 323:19] + wire [1:0] dbg_io_sb_axi_rresp; // @[el2_swerv.scala 323:19] + wire dbg_io_dbg_bus_clk_en; // @[el2_swerv.scala 323:19] + wire dbg_io_dbg_rst_l; // @[el2_swerv.scala 323:19] + wire dbg_io_clk_override; // @[el2_swerv.scala 323:19] + wire dbg_io_scan_mode; // @[el2_swerv.scala 323:19] + wire exu_clock; // @[el2_swerv.scala 324:19] + wire exu_reset; // @[el2_swerv.scala 324:19] + wire exu_io_scan_mode; // @[el2_swerv.scala 324:19] + wire [1:0] exu_io_dec_data_en; // @[el2_swerv.scala 324:19] + wire [1:0] exu_io_dec_ctl_en; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_dbg_cmd_wrdata; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_land; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_lor; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_lxor; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_sll; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_srl; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_sra; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_beq; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_bne; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_blt; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_bge; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_add; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_sub; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_slt; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_unsign; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_jal; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_predict_t; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_predict_nt; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_csr_write; // @[el2_swerv.scala 324:19] + wire exu_io_i0_ap_csr_imm; // @[el2_swerv.scala 324:19] + wire exu_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_predict_p_d_valid; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_predict_p_d_bits_pc4; // @[el2_swerv.scala 324:19] + wire [1:0] exu_io_dec_i0_predict_p_d_bits_hist; // @[el2_swerv.scala 324:19] + wire [11:0] exu_io_dec_i0_predict_p_d_bits_toffset; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_predict_p_d_bits_br_error; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_swerv.scala 324:19] + wire [30:0] exu_io_dec_i0_predict_p_d_bits_prett; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_predict_p_d_bits_pcall; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_predict_p_d_bits_pret; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 324:19] + wire [7:0] exu_io_i0_predict_fghr_d; // @[el2_swerv.scala 324:19] + wire [7:0] exu_io_i0_predict_index_d; // @[el2_swerv.scala 324:19] + wire [4:0] exu_io_i0_predict_btag_d; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_gpr_i0_rs1_d; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_gpr_i0_rs2_d; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_dec_i0_immed_d; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 324:19] + wire [11:0] exu_io_dec_i0_br_immed_d; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 324:19] + wire exu_io_dec_i0_select_pc_d; // @[el2_swerv.scala 324:19] + wire [30:0] exu_io_dec_i0_pc_d; // @[el2_swerv.scala 324:19] + wire [1:0] exu_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 324:19] + wire [1:0] exu_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 324:19] + wire exu_io_dec_csr_ren_d; // @[el2_swerv.scala 324:19] + wire exu_io_mul_p_valid; // @[el2_swerv.scala 324:19] + wire exu_io_mul_p_bits_rs1_sign; // @[el2_swerv.scala 324:19] + wire exu_io_mul_p_bits_rs2_sign; // @[el2_swerv.scala 324:19] + wire exu_io_mul_p_bits_low; // @[el2_swerv.scala 324:19] + wire exu_io_div_p_valid; // @[el2_swerv.scala 324:19] + wire exu_io_div_p_bits_unsign; // @[el2_swerv.scala 324:19] + wire exu_io_div_p_bits_rem; // @[el2_swerv.scala 324:19] + wire exu_io_dec_div_cancel; // @[el2_swerv.scala 324:19] + wire [30:0] exu_io_pred_correct_npc_x; // @[el2_swerv.scala 324:19] + wire exu_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 324:19] + wire [30:0] exu_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 324:19] + wire exu_io_dec_extint_stall; // @[el2_swerv.scala 324:19] + wire [29:0] exu_io_dec_tlu_meihap; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_exu_lsu_rs1_d; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_exu_lsu_rs2_d; // @[el2_swerv.scala 324:19] + wire exu_io_exu_flush_final; // @[el2_swerv.scala 324:19] + wire [30:0] exu_io_exu_flush_path_final; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_exu_i0_result_x; // @[el2_swerv.scala 324:19] + wire [30:0] exu_io_exu_i0_pc_x; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_exu_csr_rs1_x; // @[el2_swerv.scala 324:19] + wire [30:0] exu_io_exu_npc_r; // @[el2_swerv.scala 324:19] + wire [1:0] exu_io_exu_i0_br_hist_r; // @[el2_swerv.scala 324:19] + wire exu_io_exu_i0_br_error_r; // @[el2_swerv.scala 324:19] + wire exu_io_exu_i0_br_start_error_r; // @[el2_swerv.scala 324:19] + wire [7:0] exu_io_exu_i0_br_index_r; // @[el2_swerv.scala 324:19] + wire exu_io_exu_i0_br_valid_r; // @[el2_swerv.scala 324:19] + wire exu_io_exu_i0_br_mp_r; // @[el2_swerv.scala 324:19] + wire exu_io_exu_i0_br_middle_r; // @[el2_swerv.scala 324:19] + wire [7:0] exu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 324:19] + wire exu_io_exu_i0_br_way_r; // @[el2_swerv.scala 324:19] + wire exu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 324:19] + wire exu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 324:19] + wire exu_io_exu_mp_pkt_bits_boffset; // @[el2_swerv.scala 324:19] + wire exu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 324:19] + wire [1:0] exu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 324:19] + wire [11:0] exu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 324:19] + wire exu_io_exu_mp_pkt_bits_pcall; // @[el2_swerv.scala 324:19] + wire exu_io_exu_mp_pkt_bits_pret; // @[el2_swerv.scala 324:19] + wire exu_io_exu_mp_pkt_bits_pja; // @[el2_swerv.scala 324:19] + wire exu_io_exu_mp_pkt_bits_way; // @[el2_swerv.scala 324:19] + wire [7:0] exu_io_exu_mp_eghr; // @[el2_swerv.scala 324:19] + wire [7:0] exu_io_exu_mp_fghr; // @[el2_swerv.scala 324:19] + wire [7:0] exu_io_exu_mp_index; // @[el2_swerv.scala 324:19] + wire [4:0] exu_io_exu_mp_btag; // @[el2_swerv.scala 324:19] + wire exu_io_exu_pmu_i0_br_misp; // @[el2_swerv.scala 324:19] + wire exu_io_exu_pmu_i0_br_ataken; // @[el2_swerv.scala 324:19] + wire exu_io_exu_pmu_i0_pc4; // @[el2_swerv.scala 324:19] + wire [31:0] exu_io_exu_div_result; // @[el2_swerv.scala 324:19] + wire exu_io_exu_div_wren; // @[el2_swerv.scala 324:19] + wire lsu_clock; // @[el2_swerv.scala 325:19] + wire lsu_reset; // @[el2_swerv.scala 325:19] + wire lsu_io_clk_override; // @[el2_swerv.scala 325:19] + wire lsu_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 325:19] + wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 325:19] + wire lsu_io_dec_tlu_force_halt; // @[el2_swerv.scala 325:19] + wire lsu_io_dec_tlu_external_ldfwd_disable; // @[el2_swerv.scala 325:19] + wire lsu_io_dec_tlu_wb_coalescing_disable; // @[el2_swerv.scala 325:19] + wire lsu_io_dec_tlu_sideeffect_posted_disable; // @[el2_swerv.scala 325:19] + wire lsu_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_exu_lsu_rs1_d; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_exu_lsu_rs2_d; // @[el2_swerv.scala 325:19] + wire [11:0] lsu_io_dec_lsu_offset_d; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_valid; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_bits_fast_int; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_bits_by; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_bits_half; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_bits_word; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_bits_load; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_bits_store; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_bits_unsign; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_0_match_pkt; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_1_match_pkt; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_2_match_pkt; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_3_match_pkt; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 325:19] + wire lsu_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_lsu_result_m; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_lsu_result_corr_r; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_load_stall_any; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_store_stall_any; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_fastint_stall_any; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_idle_any; // @[el2_swerv.scala 325:19] + wire [30:0] lsu_io_lsu_fir_addr; // @[el2_swerv.scala 325:19] + wire [1:0] lsu_io_lsu_fir_error; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 325:19] + wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_nonblock_load_valid_m; // @[el2_swerv.scala 325:19] + wire [1:0] lsu_io_lsu_nonblock_load_tag_m; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_nonblock_load_inv_r; // @[el2_swerv.scala 325:19] + wire [1:0] lsu_io_lsu_nonblock_load_inv_tag_r; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_nonblock_load_data_valid; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_nonblock_load_data_error; // @[el2_swerv.scala 325:19] + wire [1:0] lsu_io_lsu_nonblock_load_data_tag; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_lsu_nonblock_load_data; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_pmu_load_external_m; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_pmu_store_external_m; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_pmu_bus_trxn; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_pmu_bus_misaligned; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_pmu_bus_error; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_pmu_bus_busy; // @[el2_swerv.scala 325:19] + wire [3:0] lsu_io_lsu_trigger_match_m; // @[el2_swerv.scala 325:19] + wire lsu_io_dccm_wren; // @[el2_swerv.scala 325:19] + wire lsu_io_dccm_rden; // @[el2_swerv.scala 325:19] + wire [15:0] lsu_io_dccm_wr_addr_lo; // @[el2_swerv.scala 325:19] + wire [15:0] lsu_io_dccm_wr_addr_hi; // @[el2_swerv.scala 325:19] + wire [15:0] lsu_io_dccm_rd_addr_lo; // @[el2_swerv.scala 325:19] + wire [15:0] lsu_io_dccm_rd_addr_hi; // @[el2_swerv.scala 325:19] + wire [38:0] lsu_io_dccm_wr_data_lo; // @[el2_swerv.scala 325:19] + wire [38:0] lsu_io_dccm_wr_data_hi; // @[el2_swerv.scala 325:19] + wire [38:0] lsu_io_dccm_rd_data_lo; // @[el2_swerv.scala 325:19] + wire [38:0] lsu_io_dccm_rd_data_hi; // @[el2_swerv.scala 325:19] + wire lsu_io_picm_wren; // @[el2_swerv.scala 325:19] + wire lsu_io_picm_rden; // @[el2_swerv.scala 325:19] + wire lsu_io_picm_mken; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_picm_rdaddr; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_picm_wraddr; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_picm_wr_data; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_picm_rd_data; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_axi_awvalid; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_axi_awready; // @[el2_swerv.scala 325:19] + wire [2:0] lsu_io_lsu_axi_awid; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_lsu_axi_awaddr; // @[el2_swerv.scala 325:19] + wire [3:0] lsu_io_lsu_axi_awregion; // @[el2_swerv.scala 325:19] + wire [2:0] lsu_io_lsu_axi_awsize; // @[el2_swerv.scala 325:19] + wire [3:0] lsu_io_lsu_axi_awcache; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_axi_wvalid; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_axi_wready; // @[el2_swerv.scala 325:19] + wire [63:0] lsu_io_lsu_axi_wdata; // @[el2_swerv.scala 325:19] + wire [7:0] lsu_io_lsu_axi_wstrb; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_axi_bvalid; // @[el2_swerv.scala 325:19] + wire [1:0] lsu_io_lsu_axi_bresp; // @[el2_swerv.scala 325:19] + wire [2:0] lsu_io_lsu_axi_bid; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_axi_arvalid; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_axi_arready; // @[el2_swerv.scala 325:19] + wire [2:0] lsu_io_lsu_axi_arid; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_lsu_axi_araddr; // @[el2_swerv.scala 325:19] + wire [3:0] lsu_io_lsu_axi_arregion; // @[el2_swerv.scala 325:19] + wire [2:0] lsu_io_lsu_axi_arsize; // @[el2_swerv.scala 325:19] + wire [3:0] lsu_io_lsu_axi_arcache; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_axi_rvalid; // @[el2_swerv.scala 325:19] + wire [63:0] lsu_io_lsu_axi_rdata; // @[el2_swerv.scala 325:19] + wire [2:0] lsu_io_lsu_axi_rid; // @[el2_swerv.scala 325:19] + wire lsu_io_lsu_bus_clk_en; // @[el2_swerv.scala 325:19] + wire lsu_io_dma_dccm_req; // @[el2_swerv.scala 325:19] + wire lsu_io_dma_mem_write; // @[el2_swerv.scala 325:19] + wire lsu_io_dccm_dma_rvalid; // @[el2_swerv.scala 325:19] + wire lsu_io_dccm_dma_ecc_error; // @[el2_swerv.scala 325:19] + wire [2:0] lsu_io_dma_mem_tag; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_dma_mem_addr; // @[el2_swerv.scala 325:19] + wire [2:0] lsu_io_dma_mem_sz; // @[el2_swerv.scala 325:19] + wire [63:0] lsu_io_dma_mem_wdata; // @[el2_swerv.scala 325:19] + wire [2:0] lsu_io_dccm_dma_rtag; // @[el2_swerv.scala 325:19] + wire [63:0] lsu_io_dccm_dma_rdata; // @[el2_swerv.scala 325:19] + wire lsu_io_dccm_ready; // @[el2_swerv.scala 325:19] + wire lsu_io_scan_mode; // @[el2_swerv.scala 325:19] + wire lsu_io_free_clk; // @[el2_swerv.scala 325:19] + wire pic_ctrl_inst_clock; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_reset; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_io_scan_mode; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_io_free_clk; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_io_active_clk; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_io_clk_override; // @[el2_swerv.scala 326:29] + wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[el2_swerv.scala 326:29] + wire [31:0] pic_ctrl_inst_io_picm_rdaddr; // @[el2_swerv.scala 326:29] + wire [31:0] pic_ctrl_inst_io_picm_wraddr; // @[el2_swerv.scala 326:29] + wire [31:0] pic_ctrl_inst_io_picm_wr_data; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_io_picm_wren; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_io_picm_rden; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_io_picm_mken; // @[el2_swerv.scala 326:29] + wire [3:0] pic_ctrl_inst_io_meicurpl; // @[el2_swerv.scala 326:29] + wire [3:0] pic_ctrl_inst_io_meipt; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_io_mexintpend; // @[el2_swerv.scala 326:29] + wire [7:0] pic_ctrl_inst_io_claimid; // @[el2_swerv.scala 326:29] + wire [3:0] pic_ctrl_inst_io_pl; // @[el2_swerv.scala 326:29] + wire [31:0] pic_ctrl_inst_io_picm_rd_data; // @[el2_swerv.scala 326:29] + wire pic_ctrl_inst_io_mhwakeup; // @[el2_swerv.scala 326:29] + wire dma_ctrl_clock; // @[el2_swerv.scala 327:24] + wire dma_ctrl_reset; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_free_clk; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_bus_clk_en; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_clk_override; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_scan_mode; // @[el2_swerv.scala 327:24] + wire [31:0] dma_ctrl_io_dbg_cmd_addr; // @[el2_swerv.scala 327:24] + wire [31:0] dma_ctrl_io_dbg_cmd_wrdata; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dbg_cmd_valid; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dbg_cmd_write; // @[el2_swerv.scala 327:24] + wire [1:0] dma_ctrl_io_dbg_cmd_type; // @[el2_swerv.scala 327:24] + wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dbg_dma_bubble; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_dbg_ready; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_dbg_cmd_done; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_dbg_cmd_fail; // @[el2_swerv.scala 327:24] + wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_dccm_req; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_iccm_req; // @[el2_swerv.scala 327:24] + wire [2:0] dma_ctrl_io_dma_mem_tag; // @[el2_swerv.scala 327:24] + wire [31:0] dma_ctrl_io_dma_mem_addr; // @[el2_swerv.scala 327:24] + wire [2:0] dma_ctrl_io_dma_mem_sz; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_mem_write; // @[el2_swerv.scala 327:24] + wire [63:0] dma_ctrl_io_dma_mem_wdata; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dccm_dma_rvalid; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dccm_dma_ecc_error; // @[el2_swerv.scala 327:24] + wire [2:0] dma_ctrl_io_dccm_dma_rtag; // @[el2_swerv.scala 327:24] + wire [63:0] dma_ctrl_io_dccm_dma_rdata; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_iccm_dma_rvalid; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_iccm_dma_ecc_error; // @[el2_swerv.scala 327:24] + wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[el2_swerv.scala 327:24] + wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_dccm_stall_any; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dccm_ready; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_iccm_ready; // @[el2_swerv.scala 327:24] + wire [2:0] dma_ctrl_io_dec_tlu_dma_qos_prty; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_pmu_dccm_read; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_pmu_dccm_write; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_pmu_any_read; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_pmu_any_write; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_awvalid; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_awready; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_awid; // @[el2_swerv.scala 327:24] + wire [31:0] dma_ctrl_io_dma_axi_awaddr; // @[el2_swerv.scala 327:24] + wire [2:0] dma_ctrl_io_dma_axi_awsize; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_wvalid; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_wready; // @[el2_swerv.scala 327:24] + wire [63:0] dma_ctrl_io_dma_axi_wdata; // @[el2_swerv.scala 327:24] + wire [7:0] dma_ctrl_io_dma_axi_wstrb; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_bvalid; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_bready; // @[el2_swerv.scala 327:24] + wire [1:0] dma_ctrl_io_dma_axi_bresp; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_bid; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_arvalid; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_arready; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_arid; // @[el2_swerv.scala 327:24] + wire [31:0] dma_ctrl_io_dma_axi_araddr; // @[el2_swerv.scala 327:24] + wire [2:0] dma_ctrl_io_dma_axi_arsize; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_rvalid; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_rready; // @[el2_swerv.scala 327:24] + wire dma_ctrl_io_dma_axi_rid; // @[el2_swerv.scala 327:24] + wire [63:0] dma_ctrl_io_dma_axi_rdata; // @[el2_swerv.scala 327:24] + wire [1:0] dma_ctrl_io_dma_axi_rresp; // @[el2_swerv.scala 327:24] wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] @@ -81027,12 +81218,11 @@ module el2_swerv( wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] - wire _T_1 = dbg_io_dbg_core_rst_l; // @[el2_swerv.scala 334:69] - wire _T_2 = _T_1 | io_scan_mode; // @[el2_swerv.scala 334:72] - wire _T_3 = reset & _T_2; // @[el2_swerv.scala 334:38] - wire _T_6 = ~dec_io_dec_pause_state_cg; // @[el2_swerv.scala 335:23] - wire _T_7 = _T_6 | dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 335:50] - el2_ifu ifu ( // @[el2_swerv.scala 323:19] + wire _T_1 = dbg_io_dbg_core_rst_l; // @[el2_swerv.scala 332:67] + wire _T_2 = _T_1 | io_scan_mode; // @[el2_swerv.scala 332:70] + wire _T_5 = ~dec_io_dec_pause_state_cg; // @[el2_swerv.scala 333:23] + wire _T_6 = _T_5 | dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 333:50] + el2_ifu ifu ( // @[el2_swerv.scala 321:19] .clock(ifu_clock), .reset(ifu_reset), .io_free_clk(ifu_io_free_clk), @@ -81116,20 +81306,22 @@ module el2_swerv( .io_iccm_dma_sb_error(ifu_io_iccm_dma_sb_error), .io_ifu_i0_instr(ifu_io_ifu_i0_instr), .io_ifu_i0_pc(ifu_io_ifu_i0_pc), + .io_ifu_i0_pc4(ifu_io_ifu_i0_pc4), .io_ifu_miss_state_idle(ifu_io_ifu_miss_state_idle), .io_i0_brp_valid(ifu_io_i0_brp_valid), - .io_i0_brp_bits_toffset(ifu_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(ifu_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(ifu_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(ifu_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_prett(ifu_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(ifu_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(ifu_io_i0_brp_bits_ret), + .io_i0_brp_toffset(ifu_io_i0_brp_toffset), + .io_i0_brp_hist(ifu_io_i0_brp_hist), + .io_i0_brp_br_error(ifu_io_i0_brp_br_error), + .io_i0_brp_br_start_error(ifu_io_i0_brp_br_start_error), + .io_i0_brp_prett(ifu_io_i0_brp_prett), + .io_i0_brp_way(ifu_io_i0_brp_way), + .io_i0_brp_ret(ifu_io_i0_brp_ret), .io_ifu_i0_bp_index(ifu_io_ifu_i0_bp_index), .io_ifu_i0_bp_fghr(ifu_io_ifu_i0_bp_fghr), .io_ifu_i0_bp_btag(ifu_io_ifu_i0_bp_btag), .io_exu_mp_pkt_bits_misp(ifu_io_exu_mp_pkt_bits_misp), .io_exu_mp_pkt_bits_ataken(ifu_io_exu_mp_pkt_bits_ataken), + .io_exu_mp_pkt_bits_boffset(ifu_io_exu_mp_pkt_bits_boffset), .io_exu_mp_pkt_bits_pc4(ifu_io_exu_mp_pkt_bits_pc4), .io_exu_mp_pkt_bits_hist(ifu_io_exu_mp_pkt_bits_hist), .io_exu_mp_pkt_bits_toffset(ifu_io_exu_mp_pkt_bits_toffset), @@ -81142,11 +81334,11 @@ module el2_swerv( .io_exu_mp_index(ifu_io_exu_mp_index), .io_exu_mp_btag(ifu_io_exu_mp_btag), .io_dec_tlu_br0_r_pkt_valid(ifu_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(ifu_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(ifu_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(ifu_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(ifu_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(ifu_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(ifu_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(ifu_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(ifu_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(ifu_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(ifu_io_dec_tlu_br0_r_pkt_middle), .io_exu_i0_br_fghr_r(ifu_io_exu_i0_br_fghr_r), .io_exu_i0_br_index_r(ifu_io_exu_i0_br_index_r), .io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb), @@ -81160,7 +81352,7 @@ module el2_swerv( .io_iccm_correction_state(ifu_io_iccm_correction_state), .io_scan_mode(ifu_io_scan_mode) ); - el2_dec dec ( // @[el2_swerv.scala 324:19] + el2_dec dec ( // @[el2_swerv.scala 322:19] .clock(dec_clock), .reset(dec_reset), .io_free_clk(dec_io_free_clk), @@ -81229,13 +81421,13 @@ module el2_swerv( .io_ifu_i0_dbecc(dec_io_ifu_i0_dbecc), .io_lsu_idle_any(dec_io_lsu_idle_any), .io_i0_brp_valid(dec_io_i0_brp_valid), - .io_i0_brp_bits_toffset(dec_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(dec_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(dec_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(dec_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_prett(dec_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(dec_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(dec_io_i0_brp_bits_ret), + .io_i0_brp_toffset(dec_io_i0_brp_toffset), + .io_i0_brp_hist(dec_io_i0_brp_hist), + .io_i0_brp_br_error(dec_io_i0_brp_br_error), + .io_i0_brp_br_start_error(dec_io_i0_brp_br_start_error), + .io_i0_brp_prett(dec_io_i0_brp_prett), + .io_i0_brp_way(dec_io_i0_brp_way), + .io_i0_brp_ret(dec_io_i0_brp_ret), .io_ifu_i0_bp_index(dec_io_ifu_i0_bp_index), .io_ifu_i0_bp_fghr(dec_io_ifu_i0_bp_fghr), .io_ifu_i0_bp_btag(dec_io_ifu_i0_bp_btag), @@ -81265,6 +81457,8 @@ module el2_swerv( .io_ifu_i0_valid(dec_io_ifu_i0_valid), .io_ifu_i0_instr(dec_io_ifu_i0_instr), .io_ifu_i0_pc(dec_io_ifu_i0_pc), + .io_ifu_i0_pc4(dec_io_ifu_i0_pc4), + .io_exu_i0_pc_x(dec_io_exu_i0_pc_x), .io_mexintpend(dec_io_mexintpend), .io_timer_int(dec_io_timer_int), .io_soft_int(dec_io_soft_int), @@ -81295,22 +81489,22 @@ module el2_swerv( .io_dec_dbg_cmd_done(dec_io_dec_dbg_cmd_done), .io_dec_dbg_cmd_fail(dec_io_dec_dbg_cmd_fail), .io_trigger_pkt_any_0_select(dec_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(dec_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(dec_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(dec_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(dec_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_tdata2(dec_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(dec_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(dec_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(dec_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(dec_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(dec_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_tdata2(dec_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(dec_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(dec_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(dec_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(dec_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(dec_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_tdata2(dec_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(dec_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(dec_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(dec_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(dec_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(dec_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_tdata2(dec_io_trigger_pkt_any_3_tdata2), @@ -81348,6 +81542,8 @@ module el2_swerv( .io_i0_ap_csr_write(dec_io_i0_ap_csr_write), .io_i0_ap_csr_imm(dec_io_i0_ap_csr_imm), .io_dec_i0_alu_decode_d(dec_io_dec_i0_alu_decode_d), + .io_dec_i0_select_pc_d(dec_io_dec_i0_select_pc_d), + .io_dec_i0_pc_d(dec_io_dec_i0_pc_d), .io_dec_i0_rs1_bypass_en_d(dec_io_dec_i0_rs1_bypass_en_d), .io_dec_i0_rs2_bypass_en_d(dec_io_dec_i0_rs2_bypass_en_d), .io_dec_i0_rs1_bypass_data_d(dec_io_dec_i0_rs1_bypass_data_d), @@ -81378,11 +81574,11 @@ module el2_swerv( .io_dec_tlu_fence_i_r(dec_io_dec_tlu_fence_i_r), .io_pred_correct_npc_x(dec_io_pred_correct_npc_x), .io_dec_tlu_br0_r_pkt_valid(dec_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(dec_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(dec_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(dec_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(dec_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(dec_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(dec_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(dec_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(dec_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(dec_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(dec_io_dec_tlu_br0_r_pkt_middle), .io_dec_tlu_perfcnt0(dec_io_dec_tlu_perfcnt0), .io_dec_tlu_perfcnt1(dec_io_dec_tlu_perfcnt1), .io_dec_tlu_perfcnt2(dec_io_dec_tlu_perfcnt2), @@ -81427,7 +81623,7 @@ module el2_swerv( .io_dec_tlu_i0_commit_cmt(dec_io_dec_tlu_i0_commit_cmt), .io_scan_mode(dec_io_scan_mode) ); - el2_dbg dbg ( // @[el2_swerv.scala 325:19] + el2_dbg dbg ( // @[el2_swerv.scala 323:19] .clock(dbg_clock), .reset(dbg_reset), .io_dbg_cmd_addr(dbg_io_dbg_cmd_addr), @@ -81478,7 +81674,7 @@ module el2_swerv( .io_clk_override(dbg_io_clk_override), .io_scan_mode(dbg_io_scan_mode) ); - el2_exu exu ( // @[el2_swerv.scala 326:19] + el2_exu exu ( // @[el2_swerv.scala 324:19] .clock(exu_clock), .reset(exu_reset), .io_scan_mode(exu_io_scan_mode), @@ -81528,6 +81724,8 @@ module el2_swerv( .io_dec_i0_rs2_bypass_data_d(exu_io_dec_i0_rs2_bypass_data_d), .io_dec_i0_br_immed_d(exu_io_dec_i0_br_immed_d), .io_dec_i0_alu_decode_d(exu_io_dec_i0_alu_decode_d), + .io_dec_i0_select_pc_d(exu_io_dec_i0_select_pc_d), + .io_dec_i0_pc_d(exu_io_dec_i0_pc_d), .io_dec_i0_rs1_bypass_en_d(exu_io_dec_i0_rs1_bypass_en_d), .io_dec_i0_rs2_bypass_en_d(exu_io_dec_i0_rs2_bypass_en_d), .io_dec_csr_ren_d(exu_io_dec_csr_ren_d), @@ -81549,6 +81747,7 @@ module el2_swerv( .io_exu_flush_final(exu_io_exu_flush_final), .io_exu_flush_path_final(exu_io_exu_flush_path_final), .io_exu_i0_result_x(exu_io_exu_i0_result_x), + .io_exu_i0_pc_x(exu_io_exu_i0_pc_x), .io_exu_csr_rs1_x(exu_io_exu_csr_rs1_x), .io_exu_npc_r(exu_io_exu_npc_r), .io_exu_i0_br_hist_r(exu_io_exu_i0_br_hist_r), @@ -81562,6 +81761,7 @@ module el2_swerv( .io_exu_i0_br_way_r(exu_io_exu_i0_br_way_r), .io_exu_mp_pkt_bits_misp(exu_io_exu_mp_pkt_bits_misp), .io_exu_mp_pkt_bits_ataken(exu_io_exu_mp_pkt_bits_ataken), + .io_exu_mp_pkt_bits_boffset(exu_io_exu_mp_pkt_bits_boffset), .io_exu_mp_pkt_bits_pc4(exu_io_exu_mp_pkt_bits_pc4), .io_exu_mp_pkt_bits_hist(exu_io_exu_mp_pkt_bits_hist), .io_exu_mp_pkt_bits_toffset(exu_io_exu_mp_pkt_bits_toffset), @@ -81579,7 +81779,7 @@ module el2_swerv( .io_exu_div_result(exu_io_exu_div_result), .io_exu_div_wren(exu_io_exu_div_wren) ); - el2_lsu lsu ( // @[el2_swerv.scala 327:19] + el2_lsu lsu ( // @[el2_swerv.scala 325:19] .clock(lsu_clock), .reset(lsu_reset), .io_clk_override(lsu_io_clk_override), @@ -81604,22 +81804,22 @@ module el2_swerv( .io_lsu_p_bits_store_data_bypass_d(lsu_io_lsu_p_bits_store_data_bypass_d), .io_lsu_p_bits_load_ldst_bypass_d(lsu_io_lsu_p_bits_load_ldst_bypass_d), .io_trigger_pkt_any_0_select(lsu_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(lsu_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(lsu_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(lsu_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(lsu_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_tdata2(lsu_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(lsu_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(lsu_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(lsu_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(lsu_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(lsu_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_tdata2(lsu_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(lsu_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(lsu_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(lsu_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(lsu_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(lsu_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_tdata2(lsu_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(lsu_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(lsu_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(lsu_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(lsu_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(lsu_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_tdata2(lsu_io_trigger_pkt_any_3_tdata2), @@ -81714,29 +81914,29 @@ module el2_swerv( .io_scan_mode(lsu_io_scan_mode), .io_free_clk(lsu_io_free_clk) ); - el2_pic_ctrl pic_ctl_inst ( // @[el2_swerv.scala 328:28] - .clock(pic_ctl_inst_clock), - .reset(pic_ctl_inst_reset), - .io_scan_mode(pic_ctl_inst_io_scan_mode), - .io_free_clk(pic_ctl_inst_io_free_clk), - .io_active_clk(pic_ctl_inst_io_active_clk), - .io_clk_override(pic_ctl_inst_io_clk_override), - .io_extintsrc_req(pic_ctl_inst_io_extintsrc_req), - .io_picm_rdaddr(pic_ctl_inst_io_picm_rdaddr), - .io_picm_wraddr(pic_ctl_inst_io_picm_wraddr), - .io_picm_wr_data(pic_ctl_inst_io_picm_wr_data), - .io_picm_wren(pic_ctl_inst_io_picm_wren), - .io_picm_rden(pic_ctl_inst_io_picm_rden), - .io_picm_mken(pic_ctl_inst_io_picm_mken), - .io_meicurpl(pic_ctl_inst_io_meicurpl), - .io_meipt(pic_ctl_inst_io_meipt), - .io_mexintpend(pic_ctl_inst_io_mexintpend), - .io_claimid(pic_ctl_inst_io_claimid), - .io_pl(pic_ctl_inst_io_pl), - .io_picm_rd_data(pic_ctl_inst_io_picm_rd_data), - .io_mhwakeup(pic_ctl_inst_io_mhwakeup) + el2_pic_ctrl pic_ctrl_inst ( // @[el2_swerv.scala 326:29] + .clock(pic_ctrl_inst_clock), + .reset(pic_ctrl_inst_reset), + .io_scan_mode(pic_ctrl_inst_io_scan_mode), + .io_free_clk(pic_ctrl_inst_io_free_clk), + .io_active_clk(pic_ctrl_inst_io_active_clk), + .io_clk_override(pic_ctrl_inst_io_clk_override), + .io_extintsrc_req(pic_ctrl_inst_io_extintsrc_req), + .io_picm_rdaddr(pic_ctrl_inst_io_picm_rdaddr), + .io_picm_wraddr(pic_ctrl_inst_io_picm_wraddr), + .io_picm_wr_data(pic_ctrl_inst_io_picm_wr_data), + .io_picm_wren(pic_ctrl_inst_io_picm_wren), + .io_picm_rden(pic_ctrl_inst_io_picm_rden), + .io_picm_mken(pic_ctrl_inst_io_picm_mken), + .io_meicurpl(pic_ctrl_inst_io_meicurpl), + .io_meipt(pic_ctrl_inst_io_meipt), + .io_mexintpend(pic_ctrl_inst_io_mexintpend), + .io_claimid(pic_ctrl_inst_io_claimid), + .io_pl(pic_ctrl_inst_io_pl), + .io_picm_rd_data(pic_ctrl_inst_io_picm_rd_data), + .io_mhwakeup(pic_ctrl_inst_io_mhwakeup) ); - el2_dma_ctrl dma_ctrl ( // @[el2_swerv.scala 329:24] + el2_dma_ctrl dma_ctrl ( // @[el2_swerv.scala 327:24] .clock(dma_ctrl_clock), .reset(dma_ctrl_reset), .io_free_clk(dma_ctrl_io_free_clk), @@ -81814,571 +82014,575 @@ module el2_swerv( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - assign io_core_rst_l = ~_T_3; // @[el2_swerv.scala 334:17] - assign io_trace_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[el2_swerv.scala 665:25] - assign io_trace_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[el2_swerv.scala 666:28] - assign io_trace_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[el2_swerv.scala 667:26] - assign io_trace_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[el2_swerv.scala 668:30] - assign io_trace_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[el2_swerv.scala 669:27] - assign io_trace_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[el2_swerv.scala 670:30] - assign io_trace_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[el2_swerv.scala 671:25] - assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[el2_swerv.scala 675:24] - assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[el2_swerv.scala 676:23] - assign io_dec_tlu_core_ecc_disable = dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 677:31] - assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[el2_swerv.scala 678:21] - assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[el2_swerv.scala 679:24] - assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[el2_swerv.scala 680:20] - assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[el2_swerv.scala 681:26] - assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[el2_swerv.scala 682:25] - assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[el2_swerv.scala 683:24] - assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[el2_swerv.scala 684:25] - assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[el2_swerv.scala 685:23] - assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[el2_swerv.scala 686:23] - assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[el2_swerv.scala 687:23] - assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[el2_swerv.scala 688:23] - assign io_dccm_wren = lsu_io_dccm_wren; // @[el2_swerv.scala 690:16] - assign io_dccm_rden = lsu_io_dccm_rden; // @[el2_swerv.scala 691:16] - assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[el2_swerv.scala 692:22] - assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[el2_swerv.scala 693:22] - assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[el2_swerv.scala 694:22] - assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[el2_swerv.scala 695:22] - assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[el2_swerv.scala 696:22] - assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[el2_swerv.scala 697:22] - assign io_iccm_rw_addr = {{1'd0}, ifu_io_iccm_rw_addr}; // @[el2_swerv.scala 699:19] - assign io_iccm_wren = ifu_io_iccm_wren; // @[el2_swerv.scala 700:16] - assign io_iccm_rden = ifu_io_iccm_rden; // @[el2_swerv.scala 701:16] - assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[el2_swerv.scala 702:19] - assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[el2_swerv.scala 703:19] - assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[el2_swerv.scala 704:27] - assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[el2_swerv.scala 705:28] - assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[el2_swerv.scala 706:17] - assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[el2_swerv.scala 707:19] - assign io_ic_wr_en = ifu_io_ic_wr_en; // @[el2_swerv.scala 708:15] - assign io_ic_rd_en = ifu_io_ic_rd_en; // @[el2_swerv.scala 709:15] - assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[el2_swerv.scala 710:17] - assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[el2_swerv.scala 710:17] - assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[el2_swerv.scala 711:23] - assign io_ic_premux_data = ifu_io_ic_premux_data; // @[el2_swerv.scala 712:21] - assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[el2_swerv.scala 713:25] - assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[el2_swerv.scala 714:20] - assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[el2_swerv.scala 715:21] - assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[el2_swerv.scala 716:21] - assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[el2_swerv.scala 717:25] - assign io_ic_debug_way = ifu_io_ic_debug_way; // @[el2_swerv.scala 718:19] - assign io_lsu_axi_awvalid = lsu_io_lsu_axi_awvalid; // @[el2_swerv.scala 721:22] - assign io_lsu_axi_awid = lsu_io_lsu_axi_awid; // @[el2_swerv.scala 722:19] - assign io_lsu_axi_awaddr = lsu_io_lsu_axi_awaddr; // @[el2_swerv.scala 723:21] - assign io_lsu_axi_awregion = lsu_io_lsu_axi_awregion; // @[el2_swerv.scala 724:23] - assign io_lsu_axi_awlen = 8'h0; // @[el2_swerv.scala 725:20] - assign io_lsu_axi_awsize = lsu_io_lsu_axi_awsize; // @[el2_swerv.scala 726:21] - assign io_lsu_axi_awburst = 2'h1; // @[el2_swerv.scala 727:22] - assign io_lsu_axi_awlock = 1'h0; // @[el2_swerv.scala 728:21] - assign io_lsu_axi_awcache = lsu_io_lsu_axi_awcache; // @[el2_swerv.scala 729:22] - assign io_lsu_axi_awprot = 3'h0; // @[el2_swerv.scala 730:21] - assign io_lsu_axi_awqos = 4'h0; // @[el2_swerv.scala 731:20] - assign io_lsu_axi_wvalid = lsu_io_lsu_axi_wvalid; // @[el2_swerv.scala 732:21] - assign io_lsu_axi_wdata = lsu_io_lsu_axi_wdata; // @[el2_swerv.scala 733:20] - assign io_lsu_axi_wstrb = lsu_io_lsu_axi_wstrb; // @[el2_swerv.scala 734:20] - assign io_lsu_axi_wlast = 1'h1; // @[el2_swerv.scala 735:20] - assign io_lsu_axi_bready = 1'h1; // @[el2_swerv.scala 736:21] - assign io_lsu_axi_arvalid = lsu_io_lsu_axi_arvalid; // @[el2_swerv.scala 737:22] - assign io_lsu_axi_arid = lsu_io_lsu_axi_arid; // @[el2_swerv.scala 738:19] - assign io_lsu_axi_araddr = lsu_io_lsu_axi_araddr; // @[el2_swerv.scala 739:21] - assign io_lsu_axi_arregion = lsu_io_lsu_axi_arregion; // @[el2_swerv.scala 740:23] - assign io_lsu_axi_arlen = 8'h0; // @[el2_swerv.scala 741:20] - assign io_lsu_axi_arsize = lsu_io_lsu_axi_arsize; // @[el2_swerv.scala 742:21] - assign io_lsu_axi_arburst = 2'h1; // @[el2_swerv.scala 743:22] - assign io_lsu_axi_arlock = 1'h0; // @[el2_swerv.scala 744:21] - assign io_lsu_axi_arcache = lsu_io_lsu_axi_arcache; // @[el2_swerv.scala 745:22] - assign io_lsu_axi_arprot = 3'h0; // @[el2_swerv.scala 746:21] - assign io_lsu_axi_arqos = 4'h0; // @[el2_swerv.scala 747:20] - assign io_lsu_axi_rready = 1'h1; // @[el2_swerv.scala 748:21] - assign io_ifu_axi_awvalid = 1'h0; // @[el2_swerv.scala 751:22] - assign io_ifu_axi_awid = 3'h0; // @[el2_swerv.scala 752:19] - assign io_ifu_axi_awaddr = 32'h0; // @[el2_swerv.scala 753:21] - assign io_ifu_axi_awregion = 4'h0; // @[el2_swerv.scala 754:23] - assign io_ifu_axi_awlen = 8'h0; // @[el2_swerv.scala 755:20] - assign io_ifu_axi_awsize = 3'h0; // @[el2_swerv.scala 756:21] - assign io_ifu_axi_awburst = 2'h0; // @[el2_swerv.scala 757:22] - assign io_ifu_axi_awlock = 1'h0; // @[el2_swerv.scala 758:21] - assign io_ifu_axi_awcache = 4'h0; // @[el2_swerv.scala 759:22] - assign io_ifu_axi_awprot = 3'h0; // @[el2_swerv.scala 760:21] - assign io_ifu_axi_awqos = 4'h0; // @[el2_swerv.scala 761:20] - assign io_ifu_axi_wvalid = 1'h0; // @[el2_swerv.scala 762:21] - assign io_ifu_axi_wready = 1'h0; // @[el2_swerv.scala 856:21] - assign io_ifu_axi_wdata = 64'h0; // @[el2_swerv.scala 763:20] - assign io_ifu_axi_wstrb = 8'h0; // @[el2_swerv.scala 764:20] - assign io_ifu_axi_wlast = 1'h0; // @[el2_swerv.scala 765:20] - assign io_ifu_axi_bready = 1'h0; // @[el2_swerv.scala 766:21] - assign io_ifu_axi_arvalid = ifu_io_ifu_axi_arvalid; // @[el2_swerv.scala 767:22] - assign io_ifu_axi_arid = ifu_io_ifu_axi_arid; // @[el2_swerv.scala 768:19] - assign io_ifu_axi_araddr = ifu_io_ifu_axi_araddr; // @[el2_swerv.scala 769:21] - assign io_ifu_axi_arregion = ifu_io_ifu_axi_arregion; // @[el2_swerv.scala 770:23] - assign io_ifu_axi_arlen = 8'h0; // @[el2_swerv.scala 771:20] - assign io_ifu_axi_arsize = 3'h3; // @[el2_swerv.scala 772:21] - assign io_ifu_axi_arburst = 2'h1; // @[el2_swerv.scala 773:22] - assign io_ifu_axi_arlock = 1'h0; // @[el2_swerv.scala 774:21] - assign io_ifu_axi_arcache = 4'hf; // @[el2_swerv.scala 775:22] - assign io_ifu_axi_arprot = 3'h0; // @[el2_swerv.scala 776:21] - assign io_ifu_axi_arqos = 4'h0; // @[el2_swerv.scala 777:20] - assign io_ifu_axi_rready = 1'h1; // @[el2_swerv.scala 778:21] - assign io_sb_axi_awvalid = dbg_io_sb_axi_awvalid; // @[el2_swerv.scala 782:21] - assign io_sb_axi_awid = 1'h0; // @[el2_swerv.scala 783:18] - assign io_sb_axi_awaddr = dbg_io_sb_axi_awaddr; // @[el2_swerv.scala 784:20] - assign io_sb_axi_awregion = dbg_io_sb_axi_awregion; // @[el2_swerv.scala 785:22] - assign io_sb_axi_awlen = 8'h0; // @[el2_swerv.scala 786:19] - assign io_sb_axi_awsize = dbg_io_sb_axi_awsize; // @[el2_swerv.scala 787:20] - assign io_sb_axi_awburst = 2'h1; // @[el2_swerv.scala 788:21] - assign io_sb_axi_awlock = 1'h0; // @[el2_swerv.scala 789:20] - assign io_sb_axi_awcache = 4'hf; // @[el2_swerv.scala 790:21] - assign io_sb_axi_awprot = 3'h0; // @[el2_swerv.scala 791:20] - assign io_sb_axi_awqos = 4'h0; // @[el2_swerv.scala 792:19] - assign io_sb_axi_wvalid = dbg_io_sb_axi_wvalid; // @[el2_swerv.scala 793:20] - assign io_sb_axi_wdata = dbg_io_sb_axi_wdata; // @[el2_swerv.scala 794:19] - assign io_sb_axi_wstrb = dbg_io_sb_axi_wstrb; // @[el2_swerv.scala 795:19] - assign io_sb_axi_wlast = 1'h1; // @[el2_swerv.scala 796:19] - assign io_sb_axi_bready = 1'h1; // @[el2_swerv.scala 797:20] - assign io_sb_axi_arvalid = dbg_io_sb_axi_arvalid; // @[el2_swerv.scala 798:21] - assign io_sb_axi_arid = 1'h0; // @[el2_swerv.scala 799:18] - assign io_sb_axi_araddr = dbg_io_sb_axi_araddr; // @[el2_swerv.scala 800:20] - assign io_sb_axi_arregion = dbg_io_sb_axi_arregion; // @[el2_swerv.scala 801:22] - assign io_sb_axi_arlen = 8'h0; // @[el2_swerv.scala 802:19] - assign io_sb_axi_arsize = dbg_io_sb_axi_arsize; // @[el2_swerv.scala 803:20] - assign io_sb_axi_arburst = 2'h1; // @[el2_swerv.scala 804:21] - assign io_sb_axi_arlock = 1'h0; // @[el2_swerv.scala 805:20] - assign io_sb_axi_arcache = 4'h0; // @[el2_swerv.scala 806:21] - assign io_sb_axi_arprot = 3'h0; // @[el2_swerv.scala 807:20] - assign io_sb_axi_arqos = 4'h0; // @[el2_swerv.scala 808:19] - assign io_sb_axi_rready = 1'h1; // @[el2_swerv.scala 809:20] - assign io_dma_axi_awready = dma_ctrl_io_dma_axi_awready; // @[el2_swerv.scala 812:22] - assign io_dma_axi_wready = dma_ctrl_io_dma_axi_wready; // @[el2_swerv.scala 813:21] - assign io_dma_axi_bvalid = dma_ctrl_io_dma_axi_bvalid; // @[el2_swerv.scala 814:21] - assign io_dma_axi_bresp = dma_ctrl_io_dma_axi_bresp; // @[el2_swerv.scala 815:20] - assign io_dma_axi_bid = dma_ctrl_io_dma_axi_bid; // @[el2_swerv.scala 816:18] - assign io_dma_axi_arready = dma_ctrl_io_dma_axi_arready; // @[el2_swerv.scala 817:22] - assign io_dma_axi_rvalid = dma_ctrl_io_dma_axi_rvalid; // @[el2_swerv.scala 818:21] - assign io_dma_axi_rid = dma_ctrl_io_dma_axi_rid; // @[el2_swerv.scala 819:18] - assign io_dma_axi_rdata = dma_ctrl_io_dma_axi_rdata; // @[el2_swerv.scala 820:20] - assign io_dma_axi_rresp = dma_ctrl_io_dma_axi_rresp; // @[el2_swerv.scala 821:20] - assign io_dma_axi_rlast = 1'h1; // @[el2_swerv.scala 822:20] - assign io_haddr = 32'h0; // @[el2_swerv.scala 831:12] - assign io_hburst = 3'h0; // @[el2_swerv.scala 825:13] - assign io_hmastlock = 1'h0; // @[el2_swerv.scala 826:16] - assign io_hprot = 4'h0; // @[el2_swerv.scala 827:12] - assign io_hsize = 3'h0; // @[el2_swerv.scala 828:12] - assign io_htrans = 2'h0; // @[el2_swerv.scala 829:13] - assign io_hwrite = 1'h0; // @[el2_swerv.scala 830:13] - assign io_lsu_haddr = 32'h0; // @[el2_swerv.scala 833:16] - assign io_lsu_hburst = 3'h0; // @[el2_swerv.scala 834:17] - assign io_lsu_hmastlock = 1'h0; // @[el2_swerv.scala 835:20] - assign io_lsu_hprot = 4'h0; // @[el2_swerv.scala 836:16] - assign io_lsu_hsize = 3'h0; // @[el2_swerv.scala 837:16] - assign io_lsu_htrans = 2'h0; // @[el2_swerv.scala 838:17] - assign io_lsu_hwrite = 1'h0; // @[el2_swerv.scala 839:17] - assign io_lsu_hwdata = 64'h0; // @[el2_swerv.scala 840:17] - assign io_sb_haddr = 32'h0; // @[el2_swerv.scala 843:15] - assign io_sb_hburst = 3'h0; // @[el2_swerv.scala 844:16] - assign io_sb_hmastlock = 1'h0; // @[el2_swerv.scala 845:19] - assign io_sb_hprot = 4'h0; // @[el2_swerv.scala 846:15] - assign io_sb_hsize = 3'h0; // @[el2_swerv.scala 847:15] - assign io_sb_htrans = 2'h0; // @[el2_swerv.scala 848:16] - assign io_sb_hwrite = 1'h0; // @[el2_swerv.scala 849:16] - assign io_sb_hwdata = 64'h0; // @[el2_swerv.scala 850:16] - assign io_dma_hrdata = 64'h0; // @[el2_swerv.scala 852:17] - assign io_dma_hreadyout = 1'h0; // @[el2_swerv.scala 853:20] - assign io_dma_hresp = 1'h0; // @[el2_swerv.scala 854:16 el2_swerv.scala 858:16] - assign io_dmi_reg_rdata = 32'h0; // @[el2_swerv.scala 860:20] + assign io_core_rst_l = reset & _T_2; // @[el2_swerv.scala 332:17] + assign io_trace_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[el2_swerv.scala 663:25] + assign io_trace_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[el2_swerv.scala 664:28] + assign io_trace_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[el2_swerv.scala 665:26] + assign io_trace_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[el2_swerv.scala 666:30] + assign io_trace_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[el2_swerv.scala 667:27] + assign io_trace_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[el2_swerv.scala 668:30] + assign io_trace_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[el2_swerv.scala 669:25] + assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[el2_swerv.scala 673:24] + assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[el2_swerv.scala 674:23] + assign io_dec_tlu_core_ecc_disable = dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 675:31] + assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[el2_swerv.scala 676:21] + assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[el2_swerv.scala 677:24] + assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[el2_swerv.scala 678:20] + assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[el2_swerv.scala 679:26] + assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[el2_swerv.scala 680:25] + assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[el2_swerv.scala 681:24] + assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[el2_swerv.scala 682:25] + assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[el2_swerv.scala 683:23] + assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[el2_swerv.scala 684:23] + assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[el2_swerv.scala 685:23] + assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[el2_swerv.scala 686:23] + assign io_dccm_wren = lsu_io_dccm_wren; // @[el2_swerv.scala 688:16] + assign io_dccm_rden = lsu_io_dccm_rden; // @[el2_swerv.scala 689:16] + assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[el2_swerv.scala 690:22] + assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[el2_swerv.scala 691:22] + assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[el2_swerv.scala 692:22] + assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[el2_swerv.scala 693:22] + assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[el2_swerv.scala 694:22] + assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[el2_swerv.scala 695:22] + assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[el2_swerv.scala 697:19] + assign io_iccm_wren = ifu_io_iccm_wren; // @[el2_swerv.scala 698:16] + assign io_iccm_rden = ifu_io_iccm_rden; // @[el2_swerv.scala 699:16] + assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[el2_swerv.scala 700:19] + assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[el2_swerv.scala 701:19] + assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[el2_swerv.scala 702:27] + assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[el2_swerv.scala 703:28] + assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[el2_swerv.scala 704:17] + assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[el2_swerv.scala 705:19] + assign io_ic_wr_en = ifu_io_ic_wr_en; // @[el2_swerv.scala 706:15] + assign io_ic_rd_en = ifu_io_ic_rd_en; // @[el2_swerv.scala 707:15] + assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[el2_swerv.scala 708:17] + assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[el2_swerv.scala 708:17] + assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[el2_swerv.scala 709:23] + assign io_ic_premux_data = ifu_io_ic_premux_data; // @[el2_swerv.scala 710:21] + assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[el2_swerv.scala 711:25] + assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[el2_swerv.scala 712:20] + assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[el2_swerv.scala 713:21] + assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[el2_swerv.scala 714:21] + assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[el2_swerv.scala 715:25] + assign io_ic_debug_way = ifu_io_ic_debug_way; // @[el2_swerv.scala 716:19] + assign io_lsu_axi_awvalid = lsu_io_lsu_axi_awvalid; // @[el2_swerv.scala 719:22] + assign io_lsu_axi_awid = lsu_io_lsu_axi_awid; // @[el2_swerv.scala 720:19] + assign io_lsu_axi_awaddr = lsu_io_lsu_axi_awaddr; // @[el2_swerv.scala 721:21] + assign io_lsu_axi_awregion = lsu_io_lsu_axi_awregion; // @[el2_swerv.scala 722:23] + assign io_lsu_axi_awlen = 8'h0; // @[el2_swerv.scala 723:20] + assign io_lsu_axi_awsize = lsu_io_lsu_axi_awsize; // @[el2_swerv.scala 724:21] + assign io_lsu_axi_awburst = 2'h1; // @[el2_swerv.scala 725:22] + assign io_lsu_axi_awlock = 1'h0; // @[el2_swerv.scala 726:21] + assign io_lsu_axi_awcache = lsu_io_lsu_axi_awcache; // @[el2_swerv.scala 727:22] + assign io_lsu_axi_awprot = 3'h0; // @[el2_swerv.scala 728:21] + assign io_lsu_axi_awqos = 4'h0; // @[el2_swerv.scala 729:20] + assign io_lsu_axi_wvalid = lsu_io_lsu_axi_wvalid; // @[el2_swerv.scala 730:21] + assign io_lsu_axi_wdata = lsu_io_lsu_axi_wdata; // @[el2_swerv.scala 731:20] + assign io_lsu_axi_wstrb = lsu_io_lsu_axi_wstrb; // @[el2_swerv.scala 732:20] + assign io_lsu_axi_wlast = 1'h1; // @[el2_swerv.scala 733:20] + assign io_lsu_axi_bready = 1'h1; // @[el2_swerv.scala 734:21] + assign io_lsu_axi_arvalid = lsu_io_lsu_axi_arvalid; // @[el2_swerv.scala 735:22] + assign io_lsu_axi_arid = lsu_io_lsu_axi_arid; // @[el2_swerv.scala 736:19] + assign io_lsu_axi_araddr = lsu_io_lsu_axi_araddr; // @[el2_swerv.scala 737:21] + assign io_lsu_axi_arregion = lsu_io_lsu_axi_arregion; // @[el2_swerv.scala 738:23] + assign io_lsu_axi_arlen = 8'h0; // @[el2_swerv.scala 739:20] + assign io_lsu_axi_arsize = lsu_io_lsu_axi_arsize; // @[el2_swerv.scala 740:21] + assign io_lsu_axi_arburst = 2'h1; // @[el2_swerv.scala 741:22] + assign io_lsu_axi_arlock = 1'h0; // @[el2_swerv.scala 742:21] + assign io_lsu_axi_arcache = lsu_io_lsu_axi_arcache; // @[el2_swerv.scala 743:22] + assign io_lsu_axi_arprot = 3'h0; // @[el2_swerv.scala 744:21] + assign io_lsu_axi_arqos = 4'h0; // @[el2_swerv.scala 745:20] + assign io_lsu_axi_rready = 1'h1; // @[el2_swerv.scala 746:21] + assign io_ifu_axi_awvalid = 1'h0; // @[el2_swerv.scala 749:22] + assign io_ifu_axi_awid = 3'h0; // @[el2_swerv.scala 750:19] + assign io_ifu_axi_awaddr = 32'h0; // @[el2_swerv.scala 751:21] + assign io_ifu_axi_awregion = 4'h0; // @[el2_swerv.scala 752:23] + assign io_ifu_axi_awlen = 8'h0; // @[el2_swerv.scala 753:20] + assign io_ifu_axi_awsize = 3'h0; // @[el2_swerv.scala 754:21] + assign io_ifu_axi_awburst = 2'h0; // @[el2_swerv.scala 755:22] + assign io_ifu_axi_awlock = 1'h0; // @[el2_swerv.scala 756:21] + assign io_ifu_axi_awcache = 4'h0; // @[el2_swerv.scala 757:22] + assign io_ifu_axi_awprot = 3'h0; // @[el2_swerv.scala 758:21] + assign io_ifu_axi_awqos = 4'h0; // @[el2_swerv.scala 759:20] + assign io_ifu_axi_wvalid = 1'h0; // @[el2_swerv.scala 760:21] + assign io_ifu_axi_wdata = 64'h0; // @[el2_swerv.scala 761:20] + assign io_ifu_axi_wstrb = 8'h0; // @[el2_swerv.scala 762:20] + assign io_ifu_axi_wlast = 1'h0; // @[el2_swerv.scala 763:20] + assign io_ifu_axi_bready = 1'h0; // @[el2_swerv.scala 764:21] + assign io_ifu_axi_arvalid = ifu_io_ifu_axi_arvalid; // @[el2_swerv.scala 765:22] + assign io_ifu_axi_arid = ifu_io_ifu_axi_arid; // @[el2_swerv.scala 766:19] + assign io_ifu_axi_araddr = ifu_io_ifu_axi_araddr; // @[el2_swerv.scala 767:21] + assign io_ifu_axi_arregion = ifu_io_ifu_axi_arregion; // @[el2_swerv.scala 768:23] + assign io_ifu_axi_arlen = 8'h0; // @[el2_swerv.scala 769:20] + assign io_ifu_axi_arsize = 3'h3; // @[el2_swerv.scala 770:21] + assign io_ifu_axi_arburst = 2'h1; // @[el2_swerv.scala 771:22] + assign io_ifu_axi_arlock = 1'h0; // @[el2_swerv.scala 772:21] + assign io_ifu_axi_arcache = 4'hf; // @[el2_swerv.scala 773:22] + assign io_ifu_axi_arprot = 3'h0; // @[el2_swerv.scala 774:21] + assign io_ifu_axi_arqos = 4'h0; // @[el2_swerv.scala 775:20] + assign io_ifu_axi_rready = 1'h1; // @[el2_swerv.scala 776:21] + assign io_sb_axi_awvalid = dbg_io_sb_axi_awvalid; // @[el2_swerv.scala 780:21] + assign io_sb_axi_awid = 1'h0; // @[el2_swerv.scala 781:18] + assign io_sb_axi_awaddr = dbg_io_sb_axi_awaddr; // @[el2_swerv.scala 782:20] + assign io_sb_axi_awregion = dbg_io_sb_axi_awregion; // @[el2_swerv.scala 783:22] + assign io_sb_axi_awlen = 8'h0; // @[el2_swerv.scala 784:19] + assign io_sb_axi_awsize = dbg_io_sb_axi_awsize; // @[el2_swerv.scala 785:20] + assign io_sb_axi_awburst = 2'h1; // @[el2_swerv.scala 786:21] + assign io_sb_axi_awlock = 1'h0; // @[el2_swerv.scala 787:20] + assign io_sb_axi_awcache = 4'hf; // @[el2_swerv.scala 788:21] + assign io_sb_axi_awprot = 3'h0; // @[el2_swerv.scala 789:20] + assign io_sb_axi_awqos = 4'h0; // @[el2_swerv.scala 790:19] + assign io_sb_axi_wvalid = dbg_io_sb_axi_wvalid; // @[el2_swerv.scala 791:20] + assign io_sb_axi_wdata = dbg_io_sb_axi_wdata; // @[el2_swerv.scala 792:19] + assign io_sb_axi_wstrb = dbg_io_sb_axi_wstrb; // @[el2_swerv.scala 793:19] + assign io_sb_axi_wlast = 1'h1; // @[el2_swerv.scala 794:19] + assign io_sb_axi_bready = 1'h1; // @[el2_swerv.scala 795:20] + assign io_sb_axi_arvalid = dbg_io_sb_axi_arvalid; // @[el2_swerv.scala 796:21] + assign io_sb_axi_arid = 1'h0; // @[el2_swerv.scala 797:18] + assign io_sb_axi_araddr = dbg_io_sb_axi_araddr; // @[el2_swerv.scala 798:20] + assign io_sb_axi_arregion = dbg_io_sb_axi_arregion; // @[el2_swerv.scala 799:22] + assign io_sb_axi_arlen = 8'h0; // @[el2_swerv.scala 800:19] + assign io_sb_axi_arsize = dbg_io_sb_axi_arsize; // @[el2_swerv.scala 801:20] + assign io_sb_axi_arburst = 2'h1; // @[el2_swerv.scala 802:21] + assign io_sb_axi_arlock = 1'h0; // @[el2_swerv.scala 803:20] + assign io_sb_axi_arcache = 4'h0; // @[el2_swerv.scala 804:21] + assign io_sb_axi_arprot = 3'h0; // @[el2_swerv.scala 805:20] + assign io_sb_axi_arqos = 4'h0; // @[el2_swerv.scala 806:19] + assign io_sb_axi_rready = 1'h1; // @[el2_swerv.scala 807:20] + assign io_dma_axi_awready = dma_ctrl_io_dma_axi_awready; // @[el2_swerv.scala 810:22] + assign io_dma_axi_wready = dma_ctrl_io_dma_axi_wready; // @[el2_swerv.scala 811:21] + assign io_dma_axi_bvalid = dma_ctrl_io_dma_axi_bvalid; // @[el2_swerv.scala 812:21] + assign io_dma_axi_bresp = dma_ctrl_io_dma_axi_bresp; // @[el2_swerv.scala 813:20] + assign io_dma_axi_bid = dma_ctrl_io_dma_axi_bid; // @[el2_swerv.scala 814:18] + assign io_dma_axi_arready = dma_ctrl_io_dma_axi_arready; // @[el2_swerv.scala 815:22] + assign io_dma_axi_rvalid = dma_ctrl_io_dma_axi_rvalid; // @[el2_swerv.scala 816:21] + assign io_dma_axi_rid = dma_ctrl_io_dma_axi_rid; // @[el2_swerv.scala 817:18] + assign io_dma_axi_rdata = dma_ctrl_io_dma_axi_rdata; // @[el2_swerv.scala 818:20] + assign io_dma_axi_rresp = dma_ctrl_io_dma_axi_rresp; // @[el2_swerv.scala 819:20] + assign io_dma_axi_rlast = 1'h1; // @[el2_swerv.scala 820:20] + assign io_haddr = 32'h0; // @[el2_swerv.scala 829:12] + assign io_hburst = 3'h0; // @[el2_swerv.scala 823:13] + assign io_hmastlock = 1'h0; // @[el2_swerv.scala 824:16] + assign io_hprot = 4'h0; // @[el2_swerv.scala 825:12] + assign io_hsize = 3'h0; // @[el2_swerv.scala 826:12] + assign io_htrans = 2'h0; // @[el2_swerv.scala 827:13] + assign io_hwrite = 1'h0; // @[el2_swerv.scala 828:13] + assign io_lsu_haddr = 32'h0; // @[el2_swerv.scala 831:16] + assign io_lsu_hburst = 3'h0; // @[el2_swerv.scala 832:17] + assign io_lsu_hmastlock = 1'h0; // @[el2_swerv.scala 833:20] + assign io_lsu_hprot = 4'h0; // @[el2_swerv.scala 834:16] + assign io_lsu_hsize = 3'h0; // @[el2_swerv.scala 835:16] + assign io_lsu_htrans = 2'h0; // @[el2_swerv.scala 836:17] + assign io_lsu_hwrite = 1'h0; // @[el2_swerv.scala 837:17] + assign io_lsu_hwdata = 64'h0; // @[el2_swerv.scala 838:17] + assign io_sb_haddr = 32'h0; // @[el2_swerv.scala 841:15] + assign io_sb_hburst = 3'h0; // @[el2_swerv.scala 842:16] + assign io_sb_hmastlock = 1'h0; // @[el2_swerv.scala 843:19] + assign io_sb_hprot = 4'h0; // @[el2_swerv.scala 844:15] + assign io_sb_hsize = 3'h0; // @[el2_swerv.scala 845:15] + assign io_sb_htrans = 2'h0; // @[el2_swerv.scala 846:16] + assign io_sb_hwrite = 1'h0; // @[el2_swerv.scala 847:16] + assign io_sb_hwdata = 64'h0; // @[el2_swerv.scala 848:16] + assign io_dma_hrdata = 64'h0; // @[el2_swerv.scala 850:17] + assign io_dma_hreadyout = 1'h0; // @[el2_swerv.scala 851:20] + assign io_dma_hresp = 1'h0; // @[el2_swerv.scala 852:16 el2_swerv.scala 856:16] + assign io_dmi_reg_rdata = 32'h0; // @[el2_swerv.scala 858:20] assign ifu_clock = clock; - assign ifu_reset = io_core_rst_l; // @[el2_swerv.scala 346:13] - assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 348:19] - assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 349:21] - assign ifu_io_dec_i0_decode_d = dec_io_dec_i0_decode_d; // @[el2_swerv.scala 351:26] - assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[el2_swerv.scala 352:26] - assign ifu_io_dec_tlu_i0_commit_cmt = dec_io_dec_tlu_i0_commit_cmt; // @[el2_swerv.scala 353:32] - assign ifu_io_dec_tlu_flush_err_wb = dec_io_dec_tlu_flush_err_r; // @[el2_swerv.scala 354:31] - assign ifu_io_dec_tlu_flush_noredir_wb = dec_io_dec_tlu_flush_noredir_r; // @[el2_swerv.scala 355:35] - assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[el2_swerv.scala 356:31] - assign ifu_io_dec_tlu_mrac_ff = dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 357:26] - assign ifu_io_dec_tlu_fence_i_wb = dec_io_dec_tlu_fence_i_r; // @[el2_swerv.scala 358:29] - assign ifu_io_dec_tlu_flush_leak_one_wb = dec_io_dec_tlu_flush_leak_one_r; // @[el2_swerv.scala 359:36] - assign ifu_io_dec_tlu_bpred_disable = dec_io_dec_tlu_bpred_disable; // @[el2_swerv.scala 360:32] - assign ifu_io_dec_tlu_core_ecc_disable = dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 361:35] - assign ifu_io_dec_tlu_force_halt = dec_io_dec_tlu_force_halt; // @[el2_swerv.scala 362:29] - assign ifu_io_ifu_axi_arready = io_ifu_axi_arready; // @[el2_swerv.scala 363:26] - assign ifu_io_ifu_axi_rvalid = io_ifu_axi_rvalid; // @[el2_swerv.scala 364:25] - assign ifu_io_ifu_axi_rid = io_ifu_axi_rid; // @[el2_swerv.scala 365:22] - assign ifu_io_ifu_axi_rdata = io_ifu_axi_rdata; // @[el2_swerv.scala 366:24] - assign ifu_io_ifu_axi_rresp = io_ifu_axi_rresp; // @[el2_swerv.scala 367:24] - assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[el2_swerv.scala 368:25] - assign ifu_io_dma_iccm_req = dma_ctrl_io_dma_iccm_req; // @[el2_swerv.scala 369:23] - assign ifu_io_dma_mem_addr = dma_ctrl_io_dma_mem_addr; // @[el2_swerv.scala 370:23] - assign ifu_io_dma_mem_sz = dma_ctrl_io_dma_mem_sz; // @[el2_swerv.scala 371:21] - assign ifu_io_dma_mem_write = dma_ctrl_io_dma_mem_write; // @[el2_swerv.scala 372:24] - assign ifu_io_dma_mem_wdata = dma_ctrl_io_dma_mem_wdata; // @[el2_swerv.scala 373:24] - assign ifu_io_dma_mem_tag = dma_ctrl_io_dma_mem_tag; // @[el2_swerv.scala 374:22] - assign ifu_io_dma_iccm_stall_any = dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 375:29] - assign ifu_io_ic_rd_data = io_ic_rd_data; // @[el2_swerv.scala 376:21] - assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[el2_swerv.scala 377:27] - assign ifu_io_ictag_debug_rd_data = io_ictag_debug_rd_data; // @[el2_swerv.scala 378:30] - assign ifu_io_ic_eccerr = io_ic_eccerr; // @[el2_swerv.scala 379:20] - assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[el2_swerv.scala 381:20] - assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[el2_swerv.scala 382:22] - assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[el2_swerv.scala 383:23] - assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[el2_swerv.scala 350:27] - assign ifu_io_exu_mp_pkt_bits_misp = exu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 384:21] - assign ifu_io_exu_mp_pkt_bits_ataken = exu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 384:21] - assign ifu_io_exu_mp_pkt_bits_pc4 = exu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 384:21] - assign ifu_io_exu_mp_pkt_bits_hist = exu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 384:21] - assign ifu_io_exu_mp_pkt_bits_toffset = exu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 384:21] - assign ifu_io_exu_mp_pkt_bits_pcall = exu_io_exu_mp_pkt_bits_pcall; // @[el2_swerv.scala 384:21] - assign ifu_io_exu_mp_pkt_bits_pret = exu_io_exu_mp_pkt_bits_pret; // @[el2_swerv.scala 384:21] - assign ifu_io_exu_mp_pkt_bits_pja = exu_io_exu_mp_pkt_bits_pja; // @[el2_swerv.scala 384:21] - assign ifu_io_exu_mp_pkt_bits_way = exu_io_exu_mp_pkt_bits_way; // @[el2_swerv.scala 384:21] - assign ifu_io_exu_mp_eghr = exu_io_exu_mp_eghr; // @[el2_swerv.scala 385:22] - assign ifu_io_exu_mp_fghr = exu_io_exu_mp_fghr; // @[el2_swerv.scala 386:22] - assign ifu_io_exu_mp_index = exu_io_exu_mp_index; // @[el2_swerv.scala 387:23] - assign ifu_io_exu_mp_btag = exu_io_exu_mp_btag; // @[el2_swerv.scala 388:22] - assign ifu_io_dec_tlu_br0_r_pkt_valid = dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 389:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_hist = dec_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 389:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_br_error = dec_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 389:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_swerv.scala 389:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_way = dec_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_swerv.scala 389:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_middle = dec_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_swerv.scala 389:28] - assign ifu_io_exu_i0_br_fghr_r = exu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 390:27] - assign ifu_io_exu_i0_br_index_r = exu_io_exu_i0_br_index_r; // @[el2_swerv.scala 391:28] - assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 392:33] - assign ifu_io_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 393:30] - assign ifu_io_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 393:30] - assign ifu_io_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_swerv.scala 393:30] - assign ifu_io_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_swerv.scala 393:30] - assign ifu_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 347:20] + assign ifu_reset = io_core_rst_l; // @[el2_swerv.scala 344:13] + assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 346:19] + assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 347:21] + assign ifu_io_dec_i0_decode_d = dec_io_dec_i0_decode_d; // @[el2_swerv.scala 349:26] + assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[el2_swerv.scala 350:26] + assign ifu_io_dec_tlu_i0_commit_cmt = dec_io_dec_tlu_i0_commit_cmt; // @[el2_swerv.scala 351:32] + assign ifu_io_dec_tlu_flush_err_wb = dec_io_dec_tlu_flush_err_r; // @[el2_swerv.scala 352:31] + assign ifu_io_dec_tlu_flush_noredir_wb = dec_io_dec_tlu_flush_noredir_r; // @[el2_swerv.scala 353:35] + assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[el2_swerv.scala 354:31] + assign ifu_io_dec_tlu_mrac_ff = dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 355:26] + assign ifu_io_dec_tlu_fence_i_wb = dec_io_dec_tlu_fence_i_r; // @[el2_swerv.scala 356:29] + assign ifu_io_dec_tlu_flush_leak_one_wb = dec_io_dec_tlu_flush_leak_one_r; // @[el2_swerv.scala 357:36] + assign ifu_io_dec_tlu_bpred_disable = dec_io_dec_tlu_bpred_disable; // @[el2_swerv.scala 358:32] + assign ifu_io_dec_tlu_core_ecc_disable = dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 359:35] + assign ifu_io_dec_tlu_force_halt = dec_io_dec_tlu_force_halt; // @[el2_swerv.scala 360:29] + assign ifu_io_ifu_axi_arready = io_ifu_axi_arready; // @[el2_swerv.scala 361:26] + assign ifu_io_ifu_axi_rvalid = io_ifu_axi_rvalid; // @[el2_swerv.scala 362:25] + assign ifu_io_ifu_axi_rid = io_ifu_axi_rid; // @[el2_swerv.scala 363:22] + assign ifu_io_ifu_axi_rdata = io_ifu_axi_rdata; // @[el2_swerv.scala 364:24] + assign ifu_io_ifu_axi_rresp = io_ifu_axi_rresp; // @[el2_swerv.scala 365:24] + assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[el2_swerv.scala 366:25] + assign ifu_io_dma_iccm_req = dma_ctrl_io_dma_iccm_req; // @[el2_swerv.scala 367:23] + assign ifu_io_dma_mem_addr = dma_ctrl_io_dma_mem_addr; // @[el2_swerv.scala 368:23] + assign ifu_io_dma_mem_sz = dma_ctrl_io_dma_mem_sz; // @[el2_swerv.scala 369:21] + assign ifu_io_dma_mem_write = dma_ctrl_io_dma_mem_write; // @[el2_swerv.scala 370:24] + assign ifu_io_dma_mem_wdata = dma_ctrl_io_dma_mem_wdata; // @[el2_swerv.scala 371:24] + assign ifu_io_dma_mem_tag = dma_ctrl_io_dma_mem_tag; // @[el2_swerv.scala 372:22] + assign ifu_io_dma_iccm_stall_any = dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 373:29] + assign ifu_io_ic_rd_data = io_ic_rd_data; // @[el2_swerv.scala 374:21] + assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[el2_swerv.scala 375:27] + assign ifu_io_ictag_debug_rd_data = io_ictag_debug_rd_data; // @[el2_swerv.scala 376:30] + assign ifu_io_ic_eccerr = io_ic_eccerr; // @[el2_swerv.scala 377:20] + assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[el2_swerv.scala 379:20] + assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[el2_swerv.scala 380:22] + assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[el2_swerv.scala 381:23] + assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[el2_swerv.scala 348:27] + assign ifu_io_exu_mp_pkt_bits_misp = exu_io_exu_mp_pkt_bits_misp; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_ataken = exu_io_exu_mp_pkt_bits_ataken; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_boffset = exu_io_exu_mp_pkt_bits_boffset; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_pc4 = exu_io_exu_mp_pkt_bits_pc4; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_hist = exu_io_exu_mp_pkt_bits_hist; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_toffset = exu_io_exu_mp_pkt_bits_toffset; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_pcall = exu_io_exu_mp_pkt_bits_pcall; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_pret = exu_io_exu_mp_pkt_bits_pret; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_pja = exu_io_exu_mp_pkt_bits_pja; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_pkt_bits_way = exu_io_exu_mp_pkt_bits_way; // @[el2_swerv.scala 382:21] + assign ifu_io_exu_mp_eghr = exu_io_exu_mp_eghr; // @[el2_swerv.scala 383:22] + assign ifu_io_exu_mp_fghr = exu_io_exu_mp_fghr; // @[el2_swerv.scala 384:22] + assign ifu_io_exu_mp_index = exu_io_exu_mp_index; // @[el2_swerv.scala 385:23] + assign ifu_io_exu_mp_btag = exu_io_exu_mp_btag; // @[el2_swerv.scala 386:22] + assign ifu_io_dec_tlu_br0_r_pkt_valid = dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_hist = dec_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_br_error = dec_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_br_start_error = dec_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_way = dec_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_middle = dec_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 387:28] + assign ifu_io_exu_i0_br_fghr_r = exu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 388:27] + assign ifu_io_exu_i0_br_index_r = exu_io_exu_i0_br_index_r; // @[el2_swerv.scala 389:28] + assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 390:33] + assign ifu_io_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_swerv.scala 391:30] + assign ifu_io_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[el2_swerv.scala 391:30] + assign ifu_io_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_swerv.scala 391:30] + assign ifu_io_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_swerv.scala 391:30] + assign ifu_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 345:20] assign dec_clock = clock; - assign dec_reset = io_core_rst_l; // @[el2_swerv.scala 396:13] - assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 397:19] - assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 398:21] - assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[el2_swerv.scala 399:32] - assign dec_io_rst_vec = {{1'd0}, io_rst_vec}; // @[el2_swerv.scala 400:18] - assign dec_io_nmi_int = io_nmi_int; // @[el2_swerv.scala 401:18] - assign dec_io_nmi_vec = {{1'd0}, io_nmi_vec}; // @[el2_swerv.scala 402:18] - assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_swerv.scala 403:25] - assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_swerv.scala 404:24] - assign dec_io_core_id = {{4'd0}, io_core_id}; // @[el2_swerv.scala 405:18] - assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_swerv.scala 406:29] - assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_swerv.scala 407:28] - assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_swerv.scala 408:28] - assign dec_io_exu_pmu_i0_br_misp = exu_io_exu_pmu_i0_br_misp; // @[el2_swerv.scala 409:29] - assign dec_io_exu_pmu_i0_br_ataken = exu_io_exu_pmu_i0_br_ataken; // @[el2_swerv.scala 410:31] - assign dec_io_exu_pmu_i0_pc4 = exu_io_exu_pmu_i0_pc4; // @[el2_swerv.scala 411:25] - assign dec_io_lsu_nonblock_load_valid_m = lsu_io_lsu_nonblock_load_valid_m; // @[el2_swerv.scala 412:36] - assign dec_io_lsu_nonblock_load_tag_m = lsu_io_lsu_nonblock_load_tag_m; // @[el2_swerv.scala 413:34] - assign dec_io_lsu_nonblock_load_inv_r = lsu_io_lsu_nonblock_load_inv_r; // @[el2_swerv.scala 414:34] - assign dec_io_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_nonblock_load_inv_tag_r; // @[el2_swerv.scala 415:38] - assign dec_io_lsu_nonblock_load_data_valid = lsu_io_lsu_nonblock_load_data_valid; // @[el2_swerv.scala 416:39] - assign dec_io_lsu_nonblock_load_data_error = lsu_io_lsu_nonblock_load_data_error; // @[el2_swerv.scala 417:39] - assign dec_io_lsu_nonblock_load_data_tag = lsu_io_lsu_nonblock_load_data_tag; // @[el2_swerv.scala 418:37] - assign dec_io_lsu_nonblock_load_data = lsu_io_lsu_nonblock_load_data; // @[el2_swerv.scala 419:33] - assign dec_io_lsu_pmu_bus_trxn = lsu_io_lsu_pmu_bus_trxn; // @[el2_swerv.scala 420:27] - assign dec_io_lsu_pmu_bus_misaligned = lsu_io_lsu_pmu_bus_misaligned; // @[el2_swerv.scala 421:33] - assign dec_io_lsu_pmu_bus_error = lsu_io_lsu_pmu_bus_error; // @[el2_swerv.scala 422:28] - assign dec_io_lsu_pmu_bus_busy = lsu_io_lsu_pmu_bus_busy; // @[el2_swerv.scala 423:27] - assign dec_io_lsu_pmu_load_external_m = lsu_io_lsu_pmu_load_external_m; // @[el2_swerv.scala 425:34] - assign dec_io_lsu_pmu_store_external_m = lsu_io_lsu_pmu_store_external_m; // @[el2_swerv.scala 426:35] - assign dec_io_dma_pmu_dccm_read = dma_ctrl_io_dma_pmu_dccm_read; // @[el2_swerv.scala 427:28] - assign dec_io_dma_pmu_dccm_write = dma_ctrl_io_dma_pmu_dccm_write; // @[el2_swerv.scala 428:29] - assign dec_io_dma_pmu_any_read = dma_ctrl_io_dma_pmu_any_read; // @[el2_swerv.scala 429:27] - assign dec_io_dma_pmu_any_write = dma_ctrl_io_dma_pmu_any_write; // @[el2_swerv.scala 430:28] - assign dec_io_lsu_fir_addr = {{1'd0}, lsu_io_lsu_fir_addr}; // @[el2_swerv.scala 431:23] - assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[el2_swerv.scala 432:24] - assign dec_io_ifu_pmu_instr_aligned = ifu_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 433:32] - assign dec_io_ifu_pmu_fetch_stall = ifu_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 434:30] - assign dec_io_ifu_pmu_ic_miss = ifu_io_ifu_pmu_ic_miss; // @[el2_swerv.scala 435:26] - assign dec_io_ifu_pmu_ic_hit = ifu_io_ifu_pmu_ic_hit; // @[el2_swerv.scala 436:25] - assign dec_io_ifu_pmu_bus_error = ifu_io_ifu_pmu_bus_error; // @[el2_swerv.scala 437:28] - assign dec_io_ifu_pmu_bus_busy = ifu_io_ifu_pmu_bus_busy; // @[el2_swerv.scala 438:27] - assign dec_io_ifu_pmu_bus_trxn = ifu_io_ifu_pmu_bus_trxn; // @[el2_swerv.scala 439:27] - assign dec_io_ifu_ic_error_start = ifu_io_ifu_ic_error_start; // @[el2_swerv.scala 440:29] - assign dec_io_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_iccm_rd_ecc_single_err; // @[el2_swerv.scala 441:37] - assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[el2_swerv.scala 442:30] - assign dec_io_dbg_cmd_valid = dbg_io_dbg_cmd_valid; // @[el2_swerv.scala 443:24] - assign dec_io_dbg_cmd_write = dbg_io_dbg_cmd_write; // @[el2_swerv.scala 444:24] - assign dec_io_dbg_cmd_type = dbg_io_dbg_cmd_type; // @[el2_swerv.scala 445:23] - assign dec_io_dbg_cmd_addr = dbg_io_dbg_cmd_addr; // @[el2_swerv.scala 446:23] - assign dec_io_dbg_cmd_wrdata = dbg_io_dbg_cmd_wrdata[1:0]; // @[el2_swerv.scala 447:25] - assign dec_io_ifu_i0_icaf = ifu_io_ifu_i0_icaf; // @[el2_swerv.scala 448:22] - assign dec_io_ifu_i0_icaf_type = ifu_io_ifu_i0_icaf_type; // @[el2_swerv.scala 449:27] - assign dec_io_ifu_i0_icaf_f1 = ifu_io_ifu_i0_icaf_f1; // @[el2_swerv.scala 450:25] - assign dec_io_ifu_i0_dbecc = ifu_io_ifu_i0_dbecc; // @[el2_swerv.scala 451:23] - assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[el2_swerv.scala 452:23] - assign dec_io_i0_brp_valid = ifu_io_i0_brp_valid; // @[el2_swerv.scala 453:17] - assign dec_io_i0_brp_bits_toffset = ifu_io_i0_brp_bits_toffset; // @[el2_swerv.scala 453:17] - assign dec_io_i0_brp_bits_hist = ifu_io_i0_brp_bits_hist; // @[el2_swerv.scala 453:17] - assign dec_io_i0_brp_bits_br_error = ifu_io_i0_brp_bits_br_error; // @[el2_swerv.scala 453:17] - assign dec_io_i0_brp_bits_br_start_error = ifu_io_i0_brp_bits_br_start_error; // @[el2_swerv.scala 453:17] - assign dec_io_i0_brp_bits_prett = ifu_io_i0_brp_bits_prett; // @[el2_swerv.scala 453:17] - assign dec_io_i0_brp_bits_way = ifu_io_i0_brp_bits_way; // @[el2_swerv.scala 453:17] - assign dec_io_i0_brp_bits_ret = ifu_io_i0_brp_bits_ret; // @[el2_swerv.scala 453:17] - assign dec_io_ifu_i0_bp_index = {{1'd0}, ifu_io_ifu_i0_bp_index}; // @[el2_swerv.scala 454:26] - assign dec_io_ifu_i0_bp_fghr = ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 455:25] - assign dec_io_ifu_i0_bp_btag = ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 456:25] - assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 457:26] - assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 457:26] - assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 457:26] - assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 457:26] - assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 457:26] - assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 457:26] - assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 458:36] - assign dec_io_lsu_imprecise_error_load_any = lsu_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 459:39] - assign dec_io_lsu_imprecise_error_store_any = lsu_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 460:40] - assign dec_io_lsu_imprecise_error_addr_any = lsu_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 461:39] - assign dec_io_exu_div_result = exu_io_exu_div_result; // @[el2_swerv.scala 462:25] - assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[el2_swerv.scala 463:23] - assign dec_io_exu_csr_rs1_x = exu_io_exu_csr_rs1_x; // @[el2_swerv.scala 464:24] - assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[el2_swerv.scala 465:23] - assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[el2_swerv.scala 466:28] - assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[el2_swerv.scala 467:29] - assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[el2_swerv.scala 468:30] - assign dec_io_dma_dccm_stall_any = dma_ctrl_io_dma_dccm_stall_any; // @[el2_swerv.scala 469:29] - assign dec_io_dma_iccm_stall_any = dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 470:29] - assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[el2_swerv.scala 471:28] - assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[el2_swerv.scala 472:26] - assign dec_io_exu_npc_r = {{1'd0}, exu_io_exu_npc_r}; // @[el2_swerv.scala 473:20] - assign dec_io_exu_i0_result_x = exu_io_exu_i0_result_x; // @[el2_swerv.scala 474:26] - assign dec_io_ifu_i0_valid = ifu_io_ifu_i0_valid; // @[el2_swerv.scala 475:23] - assign dec_io_ifu_i0_instr = ifu_io_ifu_i0_instr; // @[el2_swerv.scala 476:23] - assign dec_io_ifu_i0_pc = {{1'd0}, ifu_io_ifu_i0_pc}; // @[el2_swerv.scala 477:20] - assign dec_io_mexintpend = pic_ctl_inst_io_mexintpend; // @[el2_swerv.scala 480:21] - assign dec_io_timer_int = io_timer_int; // @[el2_swerv.scala 498:20] - assign dec_io_soft_int = io_soft_int; // @[el2_swerv.scala 481:19] - assign dec_io_pic_claimid = pic_ctl_inst_io_claimid; // @[el2_swerv.scala 482:22] - assign dec_io_pic_pl = pic_ctl_inst_io_pl; // @[el2_swerv.scala 483:17] - assign dec_io_mhwakeup = pic_ctl_inst_io_mhwakeup; // @[el2_swerv.scala 484:19] - assign dec_io_ifu_ic_debug_rd_data = ifu_io_ifu_ic_debug_rd_data[69:0]; // @[el2_swerv.scala 485:31] - assign dec_io_ifu_ic_debug_rd_data_valid = ifu_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 486:37] - assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[el2_swerv.scala 487:23] - assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[el2_swerv.scala 488:25] - assign dec_io_ifu_miss_state_idle = ifu_io_ifu_miss_state_idle; // @[el2_swerv.scala 489:30] - assign dec_io_exu_i0_br_hist_r = exu_io_exu_i0_br_hist_r; // @[el2_swerv.scala 490:27] - assign dec_io_exu_i0_br_error_r = exu_io_exu_i0_br_error_r; // @[el2_swerv.scala 491:28] - assign dec_io_exu_i0_br_start_error_r = exu_io_exu_i0_br_start_error_r; // @[el2_swerv.scala 492:34] - assign dec_io_exu_i0_br_valid_r = exu_io_exu_i0_br_valid_r; // @[el2_swerv.scala 493:28] - assign dec_io_exu_i0_br_mp_r = exu_io_exu_i0_br_mp_r; // @[el2_swerv.scala 494:25] - assign dec_io_exu_i0_br_middle_r = exu_io_exu_i0_br_middle_r; // @[el2_swerv.scala 495:29] - assign dec_io_exu_i0_br_way_r = exu_io_exu_i0_br_way_r; // @[el2_swerv.scala 496:26] - assign dec_io_ifu_i0_cinst = ifu_io_ifu_i0_cinst; // @[el2_swerv.scala 497:23] - assign dec_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 499:20] + assign dec_reset = io_core_rst_l; // @[el2_swerv.scala 394:13] + assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 395:19] + assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 396:21] + assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[el2_swerv.scala 397:32] + assign dec_io_rst_vec = io_rst_vec; // @[el2_swerv.scala 398:18] + assign dec_io_nmi_int = io_nmi_int; // @[el2_swerv.scala 399:18] + assign dec_io_nmi_vec = io_nmi_vec; // @[el2_swerv.scala 400:18] + assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[el2_swerv.scala 401:25] + assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[el2_swerv.scala 402:24] + assign dec_io_core_id = io_core_id; // @[el2_swerv.scala 403:18] + assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[el2_swerv.scala 404:29] + assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_swerv.scala 405:28] + assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_swerv.scala 406:28] + assign dec_io_exu_pmu_i0_br_misp = exu_io_exu_pmu_i0_br_misp; // @[el2_swerv.scala 407:29] + assign dec_io_exu_pmu_i0_br_ataken = exu_io_exu_pmu_i0_br_ataken; // @[el2_swerv.scala 408:31] + assign dec_io_exu_pmu_i0_pc4 = exu_io_exu_pmu_i0_pc4; // @[el2_swerv.scala 409:25] + assign dec_io_lsu_nonblock_load_valid_m = lsu_io_lsu_nonblock_load_valid_m; // @[el2_swerv.scala 410:36] + assign dec_io_lsu_nonblock_load_tag_m = lsu_io_lsu_nonblock_load_tag_m; // @[el2_swerv.scala 411:34] + assign dec_io_lsu_nonblock_load_inv_r = lsu_io_lsu_nonblock_load_inv_r; // @[el2_swerv.scala 412:34] + assign dec_io_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_nonblock_load_inv_tag_r; // @[el2_swerv.scala 413:38] + assign dec_io_lsu_nonblock_load_data_valid = lsu_io_lsu_nonblock_load_data_valid; // @[el2_swerv.scala 414:39] + assign dec_io_lsu_nonblock_load_data_error = lsu_io_lsu_nonblock_load_data_error; // @[el2_swerv.scala 415:39] + assign dec_io_lsu_nonblock_load_data_tag = lsu_io_lsu_nonblock_load_data_tag; // @[el2_swerv.scala 416:37] + assign dec_io_lsu_nonblock_load_data = lsu_io_lsu_nonblock_load_data; // @[el2_swerv.scala 417:33] + assign dec_io_lsu_pmu_bus_trxn = lsu_io_lsu_pmu_bus_trxn; // @[el2_swerv.scala 418:27] + assign dec_io_lsu_pmu_bus_misaligned = lsu_io_lsu_pmu_bus_misaligned; // @[el2_swerv.scala 419:33] + assign dec_io_lsu_pmu_bus_error = lsu_io_lsu_pmu_bus_error; // @[el2_swerv.scala 420:28] + assign dec_io_lsu_pmu_bus_busy = lsu_io_lsu_pmu_bus_busy; // @[el2_swerv.scala 421:27] + assign dec_io_lsu_pmu_load_external_m = lsu_io_lsu_pmu_load_external_m; // @[el2_swerv.scala 423:34] + assign dec_io_lsu_pmu_store_external_m = lsu_io_lsu_pmu_store_external_m; // @[el2_swerv.scala 424:35] + assign dec_io_dma_pmu_dccm_read = dma_ctrl_io_dma_pmu_dccm_read; // @[el2_swerv.scala 425:28] + assign dec_io_dma_pmu_dccm_write = dma_ctrl_io_dma_pmu_dccm_write; // @[el2_swerv.scala 426:29] + assign dec_io_dma_pmu_any_read = dma_ctrl_io_dma_pmu_any_read; // @[el2_swerv.scala 427:27] + assign dec_io_dma_pmu_any_write = dma_ctrl_io_dma_pmu_any_write; // @[el2_swerv.scala 428:28] + assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[el2_swerv.scala 429:23] + assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[el2_swerv.scala 430:24] + assign dec_io_ifu_pmu_instr_aligned = ifu_io_ifu_pmu_instr_aligned; // @[el2_swerv.scala 431:32] + assign dec_io_ifu_pmu_fetch_stall = ifu_io_ifu_pmu_fetch_stall; // @[el2_swerv.scala 432:30] + assign dec_io_ifu_pmu_ic_miss = ifu_io_ifu_pmu_ic_miss; // @[el2_swerv.scala 433:26] + assign dec_io_ifu_pmu_ic_hit = ifu_io_ifu_pmu_ic_hit; // @[el2_swerv.scala 434:25] + assign dec_io_ifu_pmu_bus_error = ifu_io_ifu_pmu_bus_error; // @[el2_swerv.scala 435:28] + assign dec_io_ifu_pmu_bus_busy = ifu_io_ifu_pmu_bus_busy; // @[el2_swerv.scala 436:27] + assign dec_io_ifu_pmu_bus_trxn = ifu_io_ifu_pmu_bus_trxn; // @[el2_swerv.scala 437:27] + assign dec_io_ifu_ic_error_start = ifu_io_ifu_ic_error_start; // @[el2_swerv.scala 438:29] + assign dec_io_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_iccm_rd_ecc_single_err; // @[el2_swerv.scala 439:37] + assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[el2_swerv.scala 440:30] + assign dec_io_dbg_cmd_valid = dbg_io_dbg_cmd_valid; // @[el2_swerv.scala 441:24] + assign dec_io_dbg_cmd_write = dbg_io_dbg_cmd_write; // @[el2_swerv.scala 442:24] + assign dec_io_dbg_cmd_type = dbg_io_dbg_cmd_type; // @[el2_swerv.scala 443:23] + assign dec_io_dbg_cmd_addr = dbg_io_dbg_cmd_addr; // @[el2_swerv.scala 444:23] + assign dec_io_dbg_cmd_wrdata = dbg_io_dbg_cmd_wrdata[1:0]; // @[el2_swerv.scala 445:25] + assign dec_io_ifu_i0_icaf = ifu_io_ifu_i0_icaf; // @[el2_swerv.scala 446:22] + assign dec_io_ifu_i0_icaf_type = ifu_io_ifu_i0_icaf_type; // @[el2_swerv.scala 447:27] + assign dec_io_ifu_i0_icaf_f1 = ifu_io_ifu_i0_icaf_f1; // @[el2_swerv.scala 448:25] + assign dec_io_ifu_i0_dbecc = ifu_io_ifu_i0_dbecc; // @[el2_swerv.scala 449:23] + assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[el2_swerv.scala 450:23] + assign dec_io_i0_brp_valid = ifu_io_i0_brp_valid; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_toffset = ifu_io_i0_brp_toffset; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_hist = ifu_io_i0_brp_hist; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_br_error = ifu_io_i0_brp_br_error; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_br_start_error = ifu_io_i0_brp_br_start_error; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_prett = ifu_io_i0_brp_prett; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_way = ifu_io_i0_brp_way; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_ret = ifu_io_i0_brp_ret; // @[el2_swerv.scala 451:17] + assign dec_io_ifu_i0_bp_index = ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 452:26] + assign dec_io_ifu_i0_bp_fghr = ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 453:25] + assign dec_io_ifu_i0_bp_btag = ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 454:25] + assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[el2_swerv.scala 455:26] + assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 455:26] + assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 455:26] + assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 455:26] + assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 455:26] + assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 455:26] + assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 456:36] + assign dec_io_lsu_imprecise_error_load_any = lsu_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 457:39] + assign dec_io_lsu_imprecise_error_store_any = lsu_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 458:40] + assign dec_io_lsu_imprecise_error_addr_any = lsu_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 459:39] + assign dec_io_exu_div_result = exu_io_exu_div_result; // @[el2_swerv.scala 460:25] + assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[el2_swerv.scala 461:23] + assign dec_io_exu_csr_rs1_x = exu_io_exu_csr_rs1_x; // @[el2_swerv.scala 462:24] + assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[el2_swerv.scala 463:23] + assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[el2_swerv.scala 464:28] + assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[el2_swerv.scala 465:29] + assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[el2_swerv.scala 466:30] + assign dec_io_dma_dccm_stall_any = dma_ctrl_io_dma_dccm_stall_any; // @[el2_swerv.scala 467:29] + assign dec_io_dma_iccm_stall_any = dma_ctrl_io_dma_iccm_stall_any; // @[el2_swerv.scala 468:29] + assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[el2_swerv.scala 469:28] + assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[el2_swerv.scala 470:26] + assign dec_io_exu_npc_r = exu_io_exu_npc_r; // @[el2_swerv.scala 471:20] + assign dec_io_exu_i0_result_x = exu_io_exu_i0_result_x; // @[el2_swerv.scala 472:26] + assign dec_io_ifu_i0_valid = ifu_io_ifu_i0_valid; // @[el2_swerv.scala 473:23] + assign dec_io_ifu_i0_instr = ifu_io_ifu_i0_instr; // @[el2_swerv.scala 474:23] + assign dec_io_ifu_i0_pc = ifu_io_ifu_i0_pc; // @[el2_swerv.scala 475:20] + assign dec_io_ifu_i0_pc4 = ifu_io_ifu_i0_pc4; // @[el2_swerv.scala 476:21] + assign dec_io_exu_i0_pc_x = exu_io_exu_i0_pc_x; // @[el2_swerv.scala 477:22] + assign dec_io_mexintpend = pic_ctrl_inst_io_mexintpend; // @[el2_swerv.scala 478:21] + assign dec_io_timer_int = io_timer_int; // @[el2_swerv.scala 496:20] + assign dec_io_soft_int = io_soft_int; // @[el2_swerv.scala 479:19] + assign dec_io_pic_claimid = pic_ctrl_inst_io_claimid; // @[el2_swerv.scala 480:22] + assign dec_io_pic_pl = pic_ctrl_inst_io_pl; // @[el2_swerv.scala 481:17] + assign dec_io_mhwakeup = pic_ctrl_inst_io_mhwakeup; // @[el2_swerv.scala 482:19] + assign dec_io_ifu_ic_debug_rd_data = ifu_io_ifu_ic_debug_rd_data; // @[el2_swerv.scala 483:31] + assign dec_io_ifu_ic_debug_rd_data_valid = ifu_io_ifu_ic_debug_rd_data_valid; // @[el2_swerv.scala 484:37] + assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[el2_swerv.scala 485:23] + assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[el2_swerv.scala 486:25] + assign dec_io_ifu_miss_state_idle = ifu_io_ifu_miss_state_idle; // @[el2_swerv.scala 487:30] + assign dec_io_exu_i0_br_hist_r = exu_io_exu_i0_br_hist_r; // @[el2_swerv.scala 488:27] + assign dec_io_exu_i0_br_error_r = exu_io_exu_i0_br_error_r; // @[el2_swerv.scala 489:28] + assign dec_io_exu_i0_br_start_error_r = exu_io_exu_i0_br_start_error_r; // @[el2_swerv.scala 490:34] + assign dec_io_exu_i0_br_valid_r = exu_io_exu_i0_br_valid_r; // @[el2_swerv.scala 491:28] + assign dec_io_exu_i0_br_mp_r = exu_io_exu_i0_br_mp_r; // @[el2_swerv.scala 492:25] + assign dec_io_exu_i0_br_middle_r = exu_io_exu_i0_br_middle_r; // @[el2_swerv.scala 493:29] + assign dec_io_exu_i0_br_way_r = exu_io_exu_i0_br_way_r; // @[el2_swerv.scala 494:26] + assign dec_io_ifu_i0_cinst = ifu_io_ifu_i0_cinst; // @[el2_swerv.scala 495:23] + assign dec_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 497:20] assign dbg_clock = clock; - assign dbg_reset = io_core_rst_l; // @[el2_swerv.scala 578:13] - assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[el2_swerv.scala 579:26] - assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[el2_swerv.scala 580:28] - assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[el2_swerv.scala 581:28] - assign dbg_io_dma_dbg_ready = dma_ctrl_io_dma_dbg_ready; // @[el2_swerv.scala 582:24] - assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[el2_swerv.scala 583:29] - assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[el2_swerv.scala 584:29] - assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 585:34] - assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[el2_swerv.scala 586:29] - assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[el2_swerv.scala 587:21] - assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[el2_swerv.scala 588:23] - assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[el2_swerv.scala 589:24] - assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[el2_swerv.scala 590:24] - assign dbg_io_sb_axi_awready = io_sb_axi_awready; // @[el2_swerv.scala 591:25] - assign dbg_io_sb_axi_wready = io_sb_axi_wready; // @[el2_swerv.scala 592:24] - assign dbg_io_sb_axi_bvalid = io_sb_axi_bvalid; // @[el2_swerv.scala 593:24] - assign dbg_io_sb_axi_bresp = io_sb_axi_bresp; // @[el2_swerv.scala 594:23] - assign dbg_io_sb_axi_arready = io_sb_axi_arready; // @[el2_swerv.scala 595:25] - assign dbg_io_sb_axi_rvalid = io_sb_axi_rvalid; // @[el2_swerv.scala 596:24] - assign dbg_io_sb_axi_rdata = io_sb_axi_rdata; // @[el2_swerv.scala 597:23] - assign dbg_io_sb_axi_rresp = io_sb_axi_rresp; // @[el2_swerv.scala 598:23] - assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[el2_swerv.scala 599:25] - assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[el2_swerv.scala 600:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[el2_swerv.scala 601:23] - assign dbg_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 602:20] + assign dbg_reset = io_core_rst_l; // @[el2_swerv.scala 576:13] + assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[el2_swerv.scala 577:26] + assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[el2_swerv.scala 578:28] + assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[el2_swerv.scala 579:28] + assign dbg_io_dma_dbg_ready = dma_ctrl_io_dma_dbg_ready; // @[el2_swerv.scala 580:24] + assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[el2_swerv.scala 581:29] + assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[el2_swerv.scala 582:29] + assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[el2_swerv.scala 583:34] + assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[el2_swerv.scala 584:29] + assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[el2_swerv.scala 585:21] + assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[el2_swerv.scala 586:23] + assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[el2_swerv.scala 587:24] + assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[el2_swerv.scala 588:24] + assign dbg_io_sb_axi_awready = io_sb_axi_awready; // @[el2_swerv.scala 589:25] + assign dbg_io_sb_axi_wready = io_sb_axi_wready; // @[el2_swerv.scala 590:24] + assign dbg_io_sb_axi_bvalid = io_sb_axi_bvalid; // @[el2_swerv.scala 591:24] + assign dbg_io_sb_axi_bresp = io_sb_axi_bresp; // @[el2_swerv.scala 592:23] + assign dbg_io_sb_axi_arready = io_sb_axi_arready; // @[el2_swerv.scala 593:25] + assign dbg_io_sb_axi_rvalid = io_sb_axi_rvalid; // @[el2_swerv.scala 594:24] + assign dbg_io_sb_axi_rdata = io_sb_axi_rdata; // @[el2_swerv.scala 595:23] + assign dbg_io_sb_axi_rresp = io_sb_axi_rresp; // @[el2_swerv.scala 596:23] + assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[el2_swerv.scala 597:25] + assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[el2_swerv.scala 598:20] + assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[el2_swerv.scala 599:23] + assign dbg_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 600:20] assign exu_clock = clock; - assign exu_reset = io_core_rst_l; // @[el2_swerv.scala 502:13] - assign exu_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 503:20] - assign exu_io_dec_data_en = dec_io_dec_data_en; // @[el2_swerv.scala 504:22] - assign exu_io_dec_ctl_en = dec_io_dec_ctl_en; // @[el2_swerv.scala 505:21] - assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_cmd_wrdata; // @[el2_swerv.scala 506:25] - assign exu_io_i0_ap_land = dec_io_i0_ap_land; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_lor = dec_io_i0_ap_lor; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_lxor = dec_io_i0_ap_lxor; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_sll = dec_io_i0_ap_sll; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_srl = dec_io_i0_ap_srl; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_sra = dec_io_i0_ap_sra; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_beq = dec_io_i0_ap_beq; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_bne = dec_io_i0_ap_bne; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_blt = dec_io_i0_ap_blt; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_bge = dec_io_i0_ap_bge; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_add = dec_io_i0_ap_add; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_sub = dec_io_i0_ap_sub; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_slt = dec_io_i0_ap_slt; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_unsign = dec_io_i0_ap_unsign; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_jal = dec_io_i0_ap_jal; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_predict_t = dec_io_i0_ap_predict_t; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_predict_nt = dec_io_i0_ap_predict_nt; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_csr_write = dec_io_i0_ap_csr_write; // @[el2_swerv.scala 507:16] - assign exu_io_i0_ap_csr_imm = dec_io_i0_ap_csr_imm; // @[el2_swerv.scala 507:16] - assign exu_io_dec_debug_wdata_rs1_d = dec_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 508:32] - assign exu_io_dec_i0_predict_p_d_valid = dec_io_dec_i0_predict_p_d_valid; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_i0_predict_p_d_bits_pc4; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_hist = dec_io_dec_i0_predict_p_d_bits_hist; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_toffset = dec_io_dec_i0_predict_p_d_bits_toffset; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_br_error = dec_io_dec_i0_predict_p_d_bits_br_error; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_prett = dec_io_dec_i0_predict_p_d_bits_prett; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_pcall = dec_io_dec_i0_predict_p_d_bits_pcall; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_pret = dec_io_dec_i0_predict_p_d_bits_pret; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_pja = dec_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 509:29] - assign exu_io_dec_i0_predict_p_d_bits_way = dec_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 509:29] - assign exu_io_i0_predict_fghr_d = dec_io_i0_predict_fghr_d; // @[el2_swerv.scala 510:28] - assign exu_io_i0_predict_index_d = dec_io_i0_predict_index_d[7:0]; // @[el2_swerv.scala 511:29] - assign exu_io_i0_predict_btag_d = dec_io_i0_predict_btag_d; // @[el2_swerv.scala 512:28] - assign exu_io_dec_i0_rs1_en_d = dec_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 513:26] - assign exu_io_dec_i0_rs2_en_d = dec_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 514:26] - assign exu_io_gpr_i0_rs1_d = dec_io_gpr_i0_rs1_d; // @[el2_swerv.scala 515:23] - assign exu_io_gpr_i0_rs2_d = dec_io_gpr_i0_rs2_d; // @[el2_swerv.scala 516:23] - assign exu_io_dec_i0_immed_d = dec_io_dec_i0_immed_d; // @[el2_swerv.scala 517:25] - assign exu_io_dec_i0_rs1_bypass_data_d = dec_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 518:35] - assign exu_io_dec_i0_rs2_bypass_data_d = dec_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 519:35] - assign exu_io_dec_i0_br_immed_d = dec_io_dec_i0_br_immed_d[11:0]; // @[el2_swerv.scala 520:28] - assign exu_io_dec_i0_alu_decode_d = dec_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 521:30] - assign exu_io_dec_i0_rs1_bypass_en_d = dec_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 524:33] - assign exu_io_dec_i0_rs2_bypass_en_d = dec_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 525:33] - assign exu_io_dec_csr_ren_d = dec_io_dec_csr_ren_d; // @[el2_swerv.scala 526:24] - assign exu_io_mul_p_valid = dec_io_mul_p_valid; // @[el2_swerv.scala 527:16] - assign exu_io_mul_p_bits_rs1_sign = dec_io_mul_p_bits_rs1_sign; // @[el2_swerv.scala 527:16] - assign exu_io_mul_p_bits_rs2_sign = dec_io_mul_p_bits_rs2_sign; // @[el2_swerv.scala 527:16] - assign exu_io_mul_p_bits_low = dec_io_mul_p_bits_low; // @[el2_swerv.scala 527:16] - assign exu_io_div_p_valid = dec_io_div_p_valid; // @[el2_swerv.scala 528:16] - assign exu_io_div_p_bits_unsign = dec_io_div_p_bits_unsign; // @[el2_swerv.scala 528:16] - assign exu_io_div_p_bits_rem = dec_io_div_p_bits_rem; // @[el2_swerv.scala 528:16] - assign exu_io_dec_div_cancel = dec_io_dec_div_cancel; // @[el2_swerv.scala 529:25] - assign exu_io_pred_correct_npc_x = dec_io_pred_correct_npc_x[30:0]; // @[el2_swerv.scala 530:29] - assign exu_io_dec_tlu_flush_lower_r = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 531:32] - assign exu_io_dec_tlu_flush_path_r = dec_io_dec_tlu_flush_path_r[30:0]; // @[el2_swerv.scala 532:31] - assign exu_io_dec_extint_stall = dec_io_dec_extint_stall; // @[el2_swerv.scala 533:27] - assign exu_io_dec_tlu_meihap = dec_io_dec_tlu_meihap[29:0]; // @[el2_swerv.scala 534:25] + assign exu_reset = io_core_rst_l; // @[el2_swerv.scala 500:13] + assign exu_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 501:20] + assign exu_io_dec_data_en = dec_io_dec_data_en; // @[el2_swerv.scala 502:22] + assign exu_io_dec_ctl_en = dec_io_dec_ctl_en; // @[el2_swerv.scala 503:21] + assign exu_io_dbg_cmd_wrdata = dbg_io_dbg_cmd_wrdata; // @[el2_swerv.scala 504:25] + assign exu_io_i0_ap_land = dec_io_i0_ap_land; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_lor = dec_io_i0_ap_lor; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_lxor = dec_io_i0_ap_lxor; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_sll = dec_io_i0_ap_sll; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_srl = dec_io_i0_ap_srl; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_sra = dec_io_i0_ap_sra; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_beq = dec_io_i0_ap_beq; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_bne = dec_io_i0_ap_bne; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_blt = dec_io_i0_ap_blt; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_bge = dec_io_i0_ap_bge; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_add = dec_io_i0_ap_add; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_sub = dec_io_i0_ap_sub; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_slt = dec_io_i0_ap_slt; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_unsign = dec_io_i0_ap_unsign; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_jal = dec_io_i0_ap_jal; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_predict_t = dec_io_i0_ap_predict_t; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_predict_nt = dec_io_i0_ap_predict_nt; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_csr_write = dec_io_i0_ap_csr_write; // @[el2_swerv.scala 505:16] + assign exu_io_i0_ap_csr_imm = dec_io_i0_ap_csr_imm; // @[el2_swerv.scala 505:16] + assign exu_io_dec_debug_wdata_rs1_d = dec_io_dec_debug_wdata_rs1_d; // @[el2_swerv.scala 506:32] + assign exu_io_dec_i0_predict_p_d_valid = dec_io_dec_i0_predict_p_d_valid; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_i0_predict_p_d_bits_pc4; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_hist = dec_io_dec_i0_predict_p_d_bits_hist; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_toffset = dec_io_dec_i0_predict_p_d_bits_toffset; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_br_error = dec_io_dec_i0_predict_p_d_bits_br_error; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_i0_predict_p_d_bits_br_start_error; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_prett = dec_io_dec_i0_predict_p_d_bits_prett; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_pcall = dec_io_dec_i0_predict_p_d_bits_pcall; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_pret = dec_io_dec_i0_predict_p_d_bits_pret; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_pja = dec_io_dec_i0_predict_p_d_bits_pja; // @[el2_swerv.scala 507:29] + assign exu_io_dec_i0_predict_p_d_bits_way = dec_io_dec_i0_predict_p_d_bits_way; // @[el2_swerv.scala 507:29] + assign exu_io_i0_predict_fghr_d = dec_io_i0_predict_fghr_d; // @[el2_swerv.scala 508:28] + assign exu_io_i0_predict_index_d = dec_io_i0_predict_index_d; // @[el2_swerv.scala 509:29] + assign exu_io_i0_predict_btag_d = dec_io_i0_predict_btag_d; // @[el2_swerv.scala 510:28] + assign exu_io_dec_i0_rs1_en_d = dec_io_dec_i0_rs1_en_d; // @[el2_swerv.scala 511:26] + assign exu_io_dec_i0_rs2_en_d = dec_io_dec_i0_rs2_en_d; // @[el2_swerv.scala 512:26] + assign exu_io_gpr_i0_rs1_d = dec_io_gpr_i0_rs1_d; // @[el2_swerv.scala 513:23] + assign exu_io_gpr_i0_rs2_d = dec_io_gpr_i0_rs2_d; // @[el2_swerv.scala 514:23] + assign exu_io_dec_i0_immed_d = dec_io_dec_i0_immed_d; // @[el2_swerv.scala 515:25] + assign exu_io_dec_i0_rs1_bypass_data_d = dec_io_dec_i0_rs1_bypass_data_d; // @[el2_swerv.scala 516:35] + assign exu_io_dec_i0_rs2_bypass_data_d = dec_io_dec_i0_rs2_bypass_data_d; // @[el2_swerv.scala 517:35] + assign exu_io_dec_i0_br_immed_d = dec_io_dec_i0_br_immed_d; // @[el2_swerv.scala 518:28] + assign exu_io_dec_i0_alu_decode_d = dec_io_dec_i0_alu_decode_d; // @[el2_swerv.scala 519:30] + assign exu_io_dec_i0_select_pc_d = dec_io_dec_i0_select_pc_d; // @[el2_swerv.scala 520:29] + assign exu_io_dec_i0_pc_d = dec_io_dec_i0_pc_d; // @[el2_swerv.scala 521:22] + assign exu_io_dec_i0_rs1_bypass_en_d = dec_io_dec_i0_rs1_bypass_en_d; // @[el2_swerv.scala 522:33] + assign exu_io_dec_i0_rs2_bypass_en_d = dec_io_dec_i0_rs2_bypass_en_d; // @[el2_swerv.scala 523:33] + assign exu_io_dec_csr_ren_d = dec_io_dec_csr_ren_d; // @[el2_swerv.scala 524:24] + assign exu_io_mul_p_valid = dec_io_mul_p_valid; // @[el2_swerv.scala 525:16] + assign exu_io_mul_p_bits_rs1_sign = dec_io_mul_p_bits_rs1_sign; // @[el2_swerv.scala 525:16] + assign exu_io_mul_p_bits_rs2_sign = dec_io_mul_p_bits_rs2_sign; // @[el2_swerv.scala 525:16] + assign exu_io_mul_p_bits_low = dec_io_mul_p_bits_low; // @[el2_swerv.scala 525:16] + assign exu_io_div_p_valid = dec_io_div_p_valid; // @[el2_swerv.scala 526:16] + assign exu_io_div_p_bits_unsign = dec_io_div_p_bits_unsign; // @[el2_swerv.scala 526:16] + assign exu_io_div_p_bits_rem = dec_io_div_p_bits_rem; // @[el2_swerv.scala 526:16] + assign exu_io_dec_div_cancel = dec_io_dec_div_cancel; // @[el2_swerv.scala 527:25] + assign exu_io_pred_correct_npc_x = dec_io_pred_correct_npc_x; // @[el2_swerv.scala 528:29] + assign exu_io_dec_tlu_flush_lower_r = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 529:32] + assign exu_io_dec_tlu_flush_path_r = dec_io_dec_tlu_flush_path_r; // @[el2_swerv.scala 530:31] + assign exu_io_dec_extint_stall = dec_io_dec_extint_stall; // @[el2_swerv.scala 531:27] + assign exu_io_dec_tlu_meihap = dec_io_dec_tlu_meihap; // @[el2_swerv.scala 532:25] assign lsu_clock = clock; - assign lsu_reset = io_core_rst_l; // @[el2_swerv.scala 538:13] - assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[el2_swerv.scala 539:23] - assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 540:32] - assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 541:35] - assign lsu_io_dec_tlu_force_halt = dec_io_dec_tlu_force_halt; // @[el2_swerv.scala 542:29] - assign lsu_io_dec_tlu_external_ldfwd_disable = dec_io_dec_tlu_external_ldfwd_disable; // @[el2_swerv.scala 543:41] - assign lsu_io_dec_tlu_wb_coalescing_disable = dec_io_dec_tlu_wb_coalescing_disable; // @[el2_swerv.scala 544:40] - assign lsu_io_dec_tlu_sideeffect_posted_disable = dec_io_dec_tlu_sideeffect_posted_disable; // @[el2_swerv.scala 545:44] - assign lsu_io_dec_tlu_core_ecc_disable = dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 546:35] - assign lsu_io_exu_lsu_rs1_d = exu_io_exu_lsu_rs1_d; // @[el2_swerv.scala 547:24] - assign lsu_io_exu_lsu_rs2_d = exu_io_exu_lsu_rs2_d; // @[el2_swerv.scala 548:24] - assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[el2_swerv.scala 549:27] - assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[el2_swerv.scala 550:16] - assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[el2_swerv.scala 550:16] - assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[el2_swerv.scala 550:16] - assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[el2_swerv.scala 550:16] - assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[el2_swerv.scala 550:16] - assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[el2_swerv.scala 550:16] - assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[el2_swerv.scala 550:16] - assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[el2_swerv.scala 550:16] - assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 550:16] - assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 550:16] - assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_0_match_ = dec_io_trigger_pkt_any_0_match_; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_1_match_ = dec_io_trigger_pkt_any_1_match_; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_2_match_ = dec_io_trigger_pkt_any_2_match_; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_3_match_ = dec_io_trigger_pkt_any_3_match_; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 553:26] - assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 553:26] - assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 551:30] - assign lsu_io_dec_tlu_mrac_ff = dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 552:26] - assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[el2_swerv.scala 554:26] - assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[el2_swerv.scala 555:26] - assign lsu_io_picm_rd_data = pic_ctl_inst_io_picm_rd_data; // @[el2_swerv.scala 659:23] - assign lsu_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_swerv.scala 556:26] - assign lsu_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_swerv.scala 557:25] - assign lsu_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_swerv.scala 558:25] - assign lsu_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_swerv.scala 559:24] - assign lsu_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_swerv.scala 560:22] - assign lsu_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_swerv.scala 561:26] - assign lsu_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_swerv.scala 562:25] - assign lsu_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_swerv.scala 564:24] - assign lsu_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_swerv.scala 563:22] - assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_swerv.scala 567:25] - assign lsu_io_dma_dccm_req = dma_ctrl_io_dma_dccm_req; // @[el2_swerv.scala 568:23] - assign lsu_io_dma_mem_write = dma_ctrl_io_dma_mem_write; // @[el2_swerv.scala 572:24] - assign lsu_io_dma_mem_tag = dma_ctrl_io_dma_mem_tag; // @[el2_swerv.scala 569:22] - assign lsu_io_dma_mem_addr = dma_ctrl_io_dma_mem_addr; // @[el2_swerv.scala 570:23] - assign lsu_io_dma_mem_sz = dma_ctrl_io_dma_mem_sz; // @[el2_swerv.scala 571:21] - assign lsu_io_dma_mem_wdata = dma_ctrl_io_dma_mem_wdata; // @[el2_swerv.scala 573:24] - assign lsu_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 574:20] - assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 575:19] - assign pic_ctl_inst_clock = clock; - assign pic_ctl_inst_reset = io_core_rst_l; // @[el2_swerv.scala 646:22] - assign pic_ctl_inst_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 645:29] - assign pic_ctl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 647:28] - assign pic_ctl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 648:30] - assign pic_ctl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[el2_swerv.scala 649:32] - assign pic_ctl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[el2_swerv.scala 650:33] - assign pic_ctl_inst_io_picm_rdaddr = lsu_io_picm_rdaddr; // @[el2_swerv.scala 651:31] - assign pic_ctl_inst_io_picm_wraddr = lsu_io_picm_wraddr; // @[el2_swerv.scala 652:31] - assign pic_ctl_inst_io_picm_wr_data = lsu_io_picm_wr_data; // @[el2_swerv.scala 653:32] - assign pic_ctl_inst_io_picm_wren = lsu_io_picm_wren; // @[el2_swerv.scala 654:29] - assign pic_ctl_inst_io_picm_rden = lsu_io_picm_rden; // @[el2_swerv.scala 655:29] - assign pic_ctl_inst_io_picm_mken = lsu_io_picm_mken; // @[el2_swerv.scala 656:29] - assign pic_ctl_inst_io_meicurpl = dec_io_dec_tlu_meicurpl; // @[el2_swerv.scala 657:28] - assign pic_ctl_inst_io_meipt = dec_io_dec_tlu_meipt; // @[el2_swerv.scala 658:25] + assign lsu_reset = io_core_rst_l; // @[el2_swerv.scala 536:13] + assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[el2_swerv.scala 537:23] + assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 538:32] + assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[el2_swerv.scala 539:35] + assign lsu_io_dec_tlu_force_halt = dec_io_dec_tlu_force_halt; // @[el2_swerv.scala 540:29] + assign lsu_io_dec_tlu_external_ldfwd_disable = dec_io_dec_tlu_external_ldfwd_disable; // @[el2_swerv.scala 541:41] + assign lsu_io_dec_tlu_wb_coalescing_disable = dec_io_dec_tlu_wb_coalescing_disable; // @[el2_swerv.scala 542:40] + assign lsu_io_dec_tlu_sideeffect_posted_disable = dec_io_dec_tlu_sideeffect_posted_disable; // @[el2_swerv.scala 543:44] + assign lsu_io_dec_tlu_core_ecc_disable = dec_io_dec_tlu_core_ecc_disable; // @[el2_swerv.scala 544:35] + assign lsu_io_exu_lsu_rs1_d = exu_io_exu_lsu_rs1_d; // @[el2_swerv.scala 545:24] + assign lsu_io_exu_lsu_rs2_d = exu_io_exu_lsu_rs2_d; // @[el2_swerv.scala 546:24] + assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[el2_swerv.scala 547:27] + assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[el2_swerv.scala 548:16] + assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[el2_swerv.scala 548:16] + assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[el2_swerv.scala 548:16] + assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[el2_swerv.scala 548:16] + assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[el2_swerv.scala 548:16] + assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[el2_swerv.scala 548:16] + assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[el2_swerv.scala 548:16] + assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[el2_swerv.scala 548:16] + assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 548:16] + assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 548:16] + assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 551:26] + assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[el2_swerv.scala 549:30] + assign lsu_io_dec_tlu_mrac_ff = dec_io_dec_tlu_mrac_ff; // @[el2_swerv.scala 550:26] + assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[el2_swerv.scala 552:26] + assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[el2_swerv.scala 553:26] + assign lsu_io_picm_rd_data = pic_ctrl_inst_io_picm_rd_data; // @[el2_swerv.scala 657:23] + assign lsu_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_swerv.scala 554:26] + assign lsu_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_swerv.scala 555:25] + assign lsu_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_swerv.scala 556:25] + assign lsu_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_swerv.scala 557:24] + assign lsu_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_swerv.scala 558:22] + assign lsu_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_swerv.scala 559:26] + assign lsu_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_swerv.scala 560:25] + assign lsu_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_swerv.scala 562:24] + assign lsu_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_swerv.scala 561:22] + assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_swerv.scala 565:25] + assign lsu_io_dma_dccm_req = dma_ctrl_io_dma_dccm_req; // @[el2_swerv.scala 566:23] + assign lsu_io_dma_mem_write = dma_ctrl_io_dma_mem_write; // @[el2_swerv.scala 570:24] + assign lsu_io_dma_mem_tag = dma_ctrl_io_dma_mem_tag; // @[el2_swerv.scala 567:22] + assign lsu_io_dma_mem_addr = dma_ctrl_io_dma_mem_addr; // @[el2_swerv.scala 568:23] + assign lsu_io_dma_mem_sz = dma_ctrl_io_dma_mem_sz; // @[el2_swerv.scala 569:21] + assign lsu_io_dma_mem_wdata = dma_ctrl_io_dma_mem_wdata; // @[el2_swerv.scala 571:24] + assign lsu_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 572:20] + assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 573:19] + assign pic_ctrl_inst_clock = clock; + assign pic_ctrl_inst_reset = io_core_rst_l; // @[el2_swerv.scala 644:23] + assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 643:30] + assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 645:29] + assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[el2_swerv.scala 646:31] + assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[el2_swerv.scala 647:33] + assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[el2_swerv.scala 648:34] + assign pic_ctrl_inst_io_picm_rdaddr = lsu_io_picm_rdaddr; // @[el2_swerv.scala 649:32] + assign pic_ctrl_inst_io_picm_wraddr = lsu_io_picm_wraddr; // @[el2_swerv.scala 650:32] + assign pic_ctrl_inst_io_picm_wr_data = lsu_io_picm_wr_data; // @[el2_swerv.scala 651:33] + assign pic_ctrl_inst_io_picm_wren = lsu_io_picm_wren; // @[el2_swerv.scala 652:30] + assign pic_ctrl_inst_io_picm_rden = lsu_io_picm_rden; // @[el2_swerv.scala 653:30] + assign pic_ctrl_inst_io_picm_mken = lsu_io_picm_mken; // @[el2_swerv.scala 654:30] + assign pic_ctrl_inst_io_meicurpl = dec_io_dec_tlu_meicurpl; // @[el2_swerv.scala 655:29] + assign pic_ctrl_inst_io_meipt = dec_io_dec_tlu_meipt; // @[el2_swerv.scala 656:26] assign dma_ctrl_clock = clock; - assign dma_ctrl_reset = io_core_rst_l; // @[el2_swerv.scala 606:18] - assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 607:24] - assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[el2_swerv.scala 608:30] - assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[el2_swerv.scala 609:28] - assign dma_ctrl_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 610:25] - assign dma_ctrl_io_dbg_cmd_addr = dbg_io_dbg_cmd_addr; // @[el2_swerv.scala 611:28] - assign dma_ctrl_io_dbg_cmd_wrdata = dbg_io_dbg_cmd_wrdata; // @[el2_swerv.scala 612:30] - assign dma_ctrl_io_dbg_cmd_valid = dbg_io_dbg_cmd_valid; // @[el2_swerv.scala 613:29] - assign dma_ctrl_io_dbg_cmd_write = dbg_io_dbg_cmd_write; // @[el2_swerv.scala 614:29] - assign dma_ctrl_io_dbg_cmd_type = dbg_io_dbg_cmd_type; // @[el2_swerv.scala 615:28] - assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[el2_swerv.scala 616:28] - assign dma_ctrl_io_dbg_dma_bubble = dbg_io_dbg_dma_bubble; // @[el2_swerv.scala 617:30] - assign dma_ctrl_io_dccm_dma_rvalid = lsu_io_dccm_dma_rvalid; // @[el2_swerv.scala 618:31] - assign dma_ctrl_io_dccm_dma_ecc_error = lsu_io_dccm_dma_ecc_error; // @[el2_swerv.scala 619:34] - assign dma_ctrl_io_dccm_dma_rtag = lsu_io_dccm_dma_rtag; // @[el2_swerv.scala 620:29] - assign dma_ctrl_io_dccm_dma_rdata = lsu_io_dccm_dma_rdata; // @[el2_swerv.scala 621:30] - assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[el2_swerv.scala 622:31] - assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[el2_swerv.scala 641:34] - assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[el2_swerv.scala 623:29] - assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[el2_swerv.scala 624:30] - assign dma_ctrl_io_dccm_ready = lsu_io_dccm_ready; // @[el2_swerv.scala 625:26] - assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[el2_swerv.scala 626:26] - assign dma_ctrl_io_dec_tlu_dma_qos_prty = dec_io_dec_tlu_dma_qos_prty; // @[el2_swerv.scala 627:36] - assign dma_ctrl_io_dma_axi_awvalid = io_dma_axi_awvalid; // @[el2_swerv.scala 628:31] - assign dma_ctrl_io_dma_axi_awid = io_dma_axi_awid; // @[el2_swerv.scala 629:28] - assign dma_ctrl_io_dma_axi_awaddr = io_dma_axi_awaddr; // @[el2_swerv.scala 630:30] - assign dma_ctrl_io_dma_axi_awsize = io_dma_axi_awsize; // @[el2_swerv.scala 631:30] - assign dma_ctrl_io_dma_axi_wvalid = io_dma_axi_wvalid; // @[el2_swerv.scala 632:30] - assign dma_ctrl_io_dma_axi_wdata = io_dma_axi_wdata; // @[el2_swerv.scala 633:29] - assign dma_ctrl_io_dma_axi_wstrb = io_dma_axi_wstrb; // @[el2_swerv.scala 634:29] - assign dma_ctrl_io_dma_axi_bready = io_dma_axi_bready; // @[el2_swerv.scala 635:30] - assign dma_ctrl_io_dma_axi_arvalid = io_dma_axi_arvalid; // @[el2_swerv.scala 636:31] - assign dma_ctrl_io_dma_axi_arid = io_dma_axi_arid; // @[el2_swerv.scala 637:28] - assign dma_ctrl_io_dma_axi_araddr = io_dma_axi_araddr; // @[el2_swerv.scala 638:30] - assign dma_ctrl_io_dma_axi_arsize = io_dma_axi_arsize; // @[el2_swerv.scala 639:30] - assign dma_ctrl_io_dma_axi_rready = io_dma_axi_rready; // @[el2_swerv.scala 640:30] + assign dma_ctrl_reset = io_core_rst_l; // @[el2_swerv.scala 604:18] + assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[el2_swerv.scala 605:24] + assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[el2_swerv.scala 606:30] + assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[el2_swerv.scala 607:28] + assign dma_ctrl_io_scan_mode = io_scan_mode; // @[el2_swerv.scala 608:25] + assign dma_ctrl_io_dbg_cmd_addr = dbg_io_dbg_cmd_addr; // @[el2_swerv.scala 609:28] + assign dma_ctrl_io_dbg_cmd_wrdata = dbg_io_dbg_cmd_wrdata; // @[el2_swerv.scala 610:30] + assign dma_ctrl_io_dbg_cmd_valid = dbg_io_dbg_cmd_valid; // @[el2_swerv.scala 611:29] + assign dma_ctrl_io_dbg_cmd_write = dbg_io_dbg_cmd_write; // @[el2_swerv.scala 612:29] + assign dma_ctrl_io_dbg_cmd_type = dbg_io_dbg_cmd_type; // @[el2_swerv.scala 613:28] + assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[el2_swerv.scala 614:28] + assign dma_ctrl_io_dbg_dma_bubble = dbg_io_dbg_dma_bubble; // @[el2_swerv.scala 615:30] + assign dma_ctrl_io_dccm_dma_rvalid = lsu_io_dccm_dma_rvalid; // @[el2_swerv.scala 616:31] + assign dma_ctrl_io_dccm_dma_ecc_error = lsu_io_dccm_dma_ecc_error; // @[el2_swerv.scala 617:34] + assign dma_ctrl_io_dccm_dma_rtag = lsu_io_dccm_dma_rtag; // @[el2_swerv.scala 618:29] + assign dma_ctrl_io_dccm_dma_rdata = lsu_io_dccm_dma_rdata; // @[el2_swerv.scala 619:30] + assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[el2_swerv.scala 620:31] + assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[el2_swerv.scala 639:34] + assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[el2_swerv.scala 621:29] + assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[el2_swerv.scala 622:30] + assign dma_ctrl_io_dccm_ready = lsu_io_dccm_ready; // @[el2_swerv.scala 623:26] + assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[el2_swerv.scala 624:26] + assign dma_ctrl_io_dec_tlu_dma_qos_prty = dec_io_dec_tlu_dma_qos_prty; // @[el2_swerv.scala 625:36] + assign dma_ctrl_io_dma_axi_awvalid = io_dma_axi_awvalid; // @[el2_swerv.scala 626:31] + assign dma_ctrl_io_dma_axi_awid = io_dma_axi_awid; // @[el2_swerv.scala 627:28] + assign dma_ctrl_io_dma_axi_awaddr = io_dma_axi_awaddr; // @[el2_swerv.scala 628:30] + assign dma_ctrl_io_dma_axi_awsize = io_dma_axi_awsize; // @[el2_swerv.scala 629:30] + assign dma_ctrl_io_dma_axi_wvalid = io_dma_axi_wvalid; // @[el2_swerv.scala 630:30] + assign dma_ctrl_io_dma_axi_wdata = io_dma_axi_wdata; // @[el2_swerv.scala 631:29] + assign dma_ctrl_io_dma_axi_wstrb = io_dma_axi_wstrb; // @[el2_swerv.scala 632:29] + assign dma_ctrl_io_dma_axi_bready = io_dma_axi_bready; // @[el2_swerv.scala 633:30] + assign dma_ctrl_io_dma_axi_arvalid = io_dma_axi_arvalid; // @[el2_swerv.scala 634:31] + assign dma_ctrl_io_dma_axi_arid = io_dma_axi_arid; // @[el2_swerv.scala 635:28] + assign dma_ctrl_io_dma_axi_araddr = io_dma_axi_araddr; // @[el2_swerv.scala 636:30] + assign dma_ctrl_io_dma_axi_arsize = io_dma_axi_arsize; // @[el2_swerv.scala 637:30] + assign dma_ctrl_io_dma_axi_rready = io_dma_axi_rready; // @[el2_swerv.scala 638:30] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_io_en = 1'h1; // @[el2_lib.scala 485:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = _T_7 | dec_io_dec_tlu_misc_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[el2_lib.scala 485:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] endmodule diff --git a/el2_swerv_wrapper.fir b/el2_swerv_wrapper.fir index eb381342..2fe6a999 100644 --- a/el2_swerv_wrapper.fir +++ b/el2_swerv_wrapper.fir @@ -29076,7 +29076,7 @@ circuit el2_swerv_wrapper : module el2_ifu_bp_ctl : input clock : Clock input reset : AsyncReset - output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt} + output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt} wire leak_one_f : UInt<1> leak_one_f <= UInt<1>("h00") @@ -29103,10 +29103,10 @@ circuit el2_swerv_wrapper : dec_tlu_way_wb <= UInt<1>("h00") node _T = eq(leak_one_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 72:51] node exu_mp_valid = and(io.exu_mp_pkt.bits.misp, _T) @[el2_ifu_bp_ctl.scala 72:49] - node _T_1 = or(io.dec_tlu_br0_r_pkt.bits.br_start_error, io.dec_tlu_br0_r_pkt.bits.br_error) @[el2_ifu_bp_ctl.scala 94:50] + node _T_1 = or(io.dec_tlu_br0_r_pkt.br_start_error, io.dec_tlu_br0_r_pkt.br_error) @[el2_ifu_bp_ctl.scala 94:50] dec_tlu_error_wb <= _T_1 @[el2_ifu_bp_ctl.scala 94:20] btb_error_addr_wb <= io.exu_i0_br_index_r @[el2_ifu_bp_ctl.scala 95:21] - dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu_bp_ctl.scala 96:18] + dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.way @[el2_ifu_bp_ctl.scala 96:18] node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 191:13] node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 191:51] node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 191:47] @@ -29913,8 +29913,8 @@ circuit el2_swerv_wrapper : node bht_wr_en0 = and(_T_556, _T_558) @[el2_ifu_bp_ctl.scala 408:84] node _T_559 = bits(io.dec_tlu_br0_r_pkt.valid, 0, 0) @[Bitwise.scala 72:15] node _T_560 = mux(_T_559, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_561 = not(io.dec_tlu_br0_r_pkt.bits.middle) @[el2_ifu_bp_ctl.scala 409:75] - node _T_562 = cat(io.dec_tlu_br0_r_pkt.bits.middle, _T_561) @[Cat.scala 29:58] + node _T_561 = not(io.dec_tlu_br0_r_pkt.middle) @[el2_ifu_bp_ctl.scala 409:75] + node _T_562 = cat(io.dec_tlu_br0_r_pkt.middle, _T_561) @[Cat.scala 29:58] node bht_wr_en2 = and(_T_560, _T_562) @[el2_ifu_bp_ctl.scala 409:46] node _T_563 = cat(io.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58] node _T_564 = bits(_T_563, 9, 2) @[el2_lib.scala 196:16] @@ -40254,7 +40254,7 @@ circuit el2_swerv_wrapper : node _T_6565 = and(_T_6562, _T_6564) @[el2_ifu_bp_ctl.scala 447:81] node _T_6566 = or(_T_6565, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6567 = bits(_T_6566, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6568 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6569 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6570 = eq(_T_6569, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40264,7 +40264,7 @@ circuit el2_swerv_wrapper : node _T_6574 = and(_T_6571, _T_6573) @[el2_ifu_bp_ctl.scala 447:81] node _T_6575 = or(_T_6574, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6576 = bits(_T_6575, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6577 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6578 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6579 = eq(_T_6578, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40274,7 +40274,7 @@ circuit el2_swerv_wrapper : node _T_6583 = and(_T_6580, _T_6582) @[el2_ifu_bp_ctl.scala 447:81] node _T_6584 = or(_T_6583, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6585 = bits(_T_6584, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6586 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6587 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6588 = eq(_T_6587, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40284,7 +40284,7 @@ circuit el2_swerv_wrapper : node _T_6592 = and(_T_6589, _T_6591) @[el2_ifu_bp_ctl.scala 447:81] node _T_6593 = or(_T_6592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6594 = bits(_T_6593, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6595 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6596 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6597 = eq(_T_6596, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40294,7 +40294,7 @@ circuit el2_swerv_wrapper : node _T_6601 = and(_T_6598, _T_6600) @[el2_ifu_bp_ctl.scala 447:81] node _T_6602 = or(_T_6601, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6603 = bits(_T_6602, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6604 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6605 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6606 = eq(_T_6605, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40304,7 +40304,7 @@ circuit el2_swerv_wrapper : node _T_6610 = and(_T_6607, _T_6609) @[el2_ifu_bp_ctl.scala 447:81] node _T_6611 = or(_T_6610, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6612 = bits(_T_6611, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6613 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6614 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6615 = eq(_T_6614, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40314,7 +40314,7 @@ circuit el2_swerv_wrapper : node _T_6619 = and(_T_6616, _T_6618) @[el2_ifu_bp_ctl.scala 447:81] node _T_6620 = or(_T_6619, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6621 = bits(_T_6620, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6622 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6623 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6624 = eq(_T_6623, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40324,7 +40324,7 @@ circuit el2_swerv_wrapper : node _T_6628 = and(_T_6625, _T_6627) @[el2_ifu_bp_ctl.scala 447:81] node _T_6629 = or(_T_6628, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6630 = bits(_T_6629, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6631 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6632 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6633 = eq(_T_6632, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40334,7 +40334,7 @@ circuit el2_swerv_wrapper : node _T_6637 = and(_T_6634, _T_6636) @[el2_ifu_bp_ctl.scala 447:81] node _T_6638 = or(_T_6637, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6639 = bits(_T_6638, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6640 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6641 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6642 = eq(_T_6641, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40344,7 +40344,7 @@ circuit el2_swerv_wrapper : node _T_6646 = and(_T_6643, _T_6645) @[el2_ifu_bp_ctl.scala 447:81] node _T_6647 = or(_T_6646, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6648 = bits(_T_6647, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6649 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6650 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6651 = eq(_T_6650, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40354,7 +40354,7 @@ circuit el2_swerv_wrapper : node _T_6655 = and(_T_6652, _T_6654) @[el2_ifu_bp_ctl.scala 447:81] node _T_6656 = or(_T_6655, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6657 = bits(_T_6656, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6658 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6659 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6660 = eq(_T_6659, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40364,7 +40364,7 @@ circuit el2_swerv_wrapper : node _T_6664 = and(_T_6661, _T_6663) @[el2_ifu_bp_ctl.scala 447:81] node _T_6665 = or(_T_6664, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6666 = bits(_T_6665, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6667 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6668 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6669 = eq(_T_6668, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40374,7 +40374,7 @@ circuit el2_swerv_wrapper : node _T_6673 = and(_T_6670, _T_6672) @[el2_ifu_bp_ctl.scala 447:81] node _T_6674 = or(_T_6673, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6675 = bits(_T_6674, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6676 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6677 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6678 = eq(_T_6677, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40384,7 +40384,7 @@ circuit el2_swerv_wrapper : node _T_6682 = and(_T_6679, _T_6681) @[el2_ifu_bp_ctl.scala 447:81] node _T_6683 = or(_T_6682, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6684 = bits(_T_6683, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6685 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6686 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6687 = eq(_T_6686, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40394,7 +40394,7 @@ circuit el2_swerv_wrapper : node _T_6691 = and(_T_6688, _T_6690) @[el2_ifu_bp_ctl.scala 447:81] node _T_6692 = or(_T_6691, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6693 = bits(_T_6692, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6694 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6695 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6696 = eq(_T_6695, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40404,7 +40404,7 @@ circuit el2_swerv_wrapper : node _T_6700 = and(_T_6697, _T_6699) @[el2_ifu_bp_ctl.scala 447:81] node _T_6701 = or(_T_6700, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6702 = bits(_T_6701, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6703 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6704 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6705 = eq(_T_6704, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40414,7 +40414,7 @@ circuit el2_swerv_wrapper : node _T_6709 = and(_T_6706, _T_6708) @[el2_ifu_bp_ctl.scala 447:81] node _T_6710 = or(_T_6709, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6711 = bits(_T_6710, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6712 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6713 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6714 = eq(_T_6713, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40424,7 +40424,7 @@ circuit el2_swerv_wrapper : node _T_6718 = and(_T_6715, _T_6717) @[el2_ifu_bp_ctl.scala 447:81] node _T_6719 = or(_T_6718, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6720 = bits(_T_6719, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6721 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6722 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6723 = eq(_T_6722, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40434,7 +40434,7 @@ circuit el2_swerv_wrapper : node _T_6727 = and(_T_6724, _T_6726) @[el2_ifu_bp_ctl.scala 447:81] node _T_6728 = or(_T_6727, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6729 = bits(_T_6728, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6730 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6731 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6732 = eq(_T_6731, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40444,7 +40444,7 @@ circuit el2_swerv_wrapper : node _T_6736 = and(_T_6733, _T_6735) @[el2_ifu_bp_ctl.scala 447:81] node _T_6737 = or(_T_6736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6738 = bits(_T_6737, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6739 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6740 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6741 = eq(_T_6740, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40454,7 +40454,7 @@ circuit el2_swerv_wrapper : node _T_6745 = and(_T_6742, _T_6744) @[el2_ifu_bp_ctl.scala 447:81] node _T_6746 = or(_T_6745, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6747 = bits(_T_6746, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6748 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6749 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6750 = eq(_T_6749, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40464,7 +40464,7 @@ circuit el2_swerv_wrapper : node _T_6754 = and(_T_6751, _T_6753) @[el2_ifu_bp_ctl.scala 447:81] node _T_6755 = or(_T_6754, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6756 = bits(_T_6755, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6757 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6758 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6759 = eq(_T_6758, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40474,7 +40474,7 @@ circuit el2_swerv_wrapper : node _T_6763 = and(_T_6760, _T_6762) @[el2_ifu_bp_ctl.scala 447:81] node _T_6764 = or(_T_6763, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6765 = bits(_T_6764, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6766 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6767 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6768 = eq(_T_6767, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40484,7 +40484,7 @@ circuit el2_swerv_wrapper : node _T_6772 = and(_T_6769, _T_6771) @[el2_ifu_bp_ctl.scala 447:81] node _T_6773 = or(_T_6772, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6774 = bits(_T_6773, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6775 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6776 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6777 = eq(_T_6776, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40494,7 +40494,7 @@ circuit el2_swerv_wrapper : node _T_6781 = and(_T_6778, _T_6780) @[el2_ifu_bp_ctl.scala 447:81] node _T_6782 = or(_T_6781, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6783 = bits(_T_6782, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6784 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6785 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6786 = eq(_T_6785, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40504,7 +40504,7 @@ circuit el2_swerv_wrapper : node _T_6790 = and(_T_6787, _T_6789) @[el2_ifu_bp_ctl.scala 447:81] node _T_6791 = or(_T_6790, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6792 = bits(_T_6791, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6793 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6794 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6795 = eq(_T_6794, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40514,7 +40514,7 @@ circuit el2_swerv_wrapper : node _T_6799 = and(_T_6796, _T_6798) @[el2_ifu_bp_ctl.scala 447:81] node _T_6800 = or(_T_6799, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6801 = bits(_T_6800, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6802 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6803 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6804 = eq(_T_6803, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40524,7 +40524,7 @@ circuit el2_swerv_wrapper : node _T_6808 = and(_T_6805, _T_6807) @[el2_ifu_bp_ctl.scala 447:81] node _T_6809 = or(_T_6808, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6810 = bits(_T_6809, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6811 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6812 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6813 = eq(_T_6812, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40534,7 +40534,7 @@ circuit el2_swerv_wrapper : node _T_6817 = and(_T_6814, _T_6816) @[el2_ifu_bp_ctl.scala 447:81] node _T_6818 = or(_T_6817, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6819 = bits(_T_6818, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6820 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6821 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6822 = eq(_T_6821, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40544,7 +40544,7 @@ circuit el2_swerv_wrapper : node _T_6826 = and(_T_6823, _T_6825) @[el2_ifu_bp_ctl.scala 447:81] node _T_6827 = or(_T_6826, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6828 = bits(_T_6827, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6829 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6830 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6831 = eq(_T_6830, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40554,7 +40554,7 @@ circuit el2_swerv_wrapper : node _T_6835 = and(_T_6832, _T_6834) @[el2_ifu_bp_ctl.scala 447:81] node _T_6836 = or(_T_6835, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6837 = bits(_T_6836, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6838 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6839 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6840 = eq(_T_6839, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40564,7 +40564,7 @@ circuit el2_swerv_wrapper : node _T_6844 = and(_T_6841, _T_6843) @[el2_ifu_bp_ctl.scala 447:81] node _T_6845 = or(_T_6844, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6846 = bits(_T_6845, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6847 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6848 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6849 = eq(_T_6848, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40574,7 +40574,7 @@ circuit el2_swerv_wrapper : node _T_6853 = and(_T_6850, _T_6852) @[el2_ifu_bp_ctl.scala 447:81] node _T_6854 = or(_T_6853, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6855 = bits(_T_6854, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6856 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6857 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6858 = eq(_T_6857, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40584,7 +40584,7 @@ circuit el2_swerv_wrapper : node _T_6862 = and(_T_6859, _T_6861) @[el2_ifu_bp_ctl.scala 447:81] node _T_6863 = or(_T_6862, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6864 = bits(_T_6863, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6865 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6866 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6867 = eq(_T_6866, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40594,7 +40594,7 @@ circuit el2_swerv_wrapper : node _T_6871 = and(_T_6868, _T_6870) @[el2_ifu_bp_ctl.scala 447:81] node _T_6872 = or(_T_6871, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6873 = bits(_T_6872, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6874 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6875 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6876 = eq(_T_6875, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40604,7 +40604,7 @@ circuit el2_swerv_wrapper : node _T_6880 = and(_T_6877, _T_6879) @[el2_ifu_bp_ctl.scala 447:81] node _T_6881 = or(_T_6880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6882 = bits(_T_6881, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6883 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6884 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6885 = eq(_T_6884, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40614,7 +40614,7 @@ circuit el2_swerv_wrapper : node _T_6889 = and(_T_6886, _T_6888) @[el2_ifu_bp_ctl.scala 447:81] node _T_6890 = or(_T_6889, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6891 = bits(_T_6890, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6892 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6893 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6894 = eq(_T_6893, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40624,7 +40624,7 @@ circuit el2_swerv_wrapper : node _T_6898 = and(_T_6895, _T_6897) @[el2_ifu_bp_ctl.scala 447:81] node _T_6899 = or(_T_6898, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6900 = bits(_T_6899, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6901 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6902 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6903 = eq(_T_6902, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40634,7 +40634,7 @@ circuit el2_swerv_wrapper : node _T_6907 = and(_T_6904, _T_6906) @[el2_ifu_bp_ctl.scala 447:81] node _T_6908 = or(_T_6907, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6909 = bits(_T_6908, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6910 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6911 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6912 = eq(_T_6911, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40644,7 +40644,7 @@ circuit el2_swerv_wrapper : node _T_6916 = and(_T_6913, _T_6915) @[el2_ifu_bp_ctl.scala 447:81] node _T_6917 = or(_T_6916, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6918 = bits(_T_6917, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6919 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6920 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6921 = eq(_T_6920, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40654,7 +40654,7 @@ circuit el2_swerv_wrapper : node _T_6925 = and(_T_6922, _T_6924) @[el2_ifu_bp_ctl.scala 447:81] node _T_6926 = or(_T_6925, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6927 = bits(_T_6926, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6928 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6929 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6930 = eq(_T_6929, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40664,7 +40664,7 @@ circuit el2_swerv_wrapper : node _T_6934 = and(_T_6931, _T_6933) @[el2_ifu_bp_ctl.scala 447:81] node _T_6935 = or(_T_6934, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6936 = bits(_T_6935, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6937 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6938 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6939 = eq(_T_6938, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40674,7 +40674,7 @@ circuit el2_swerv_wrapper : node _T_6943 = and(_T_6940, _T_6942) @[el2_ifu_bp_ctl.scala 447:81] node _T_6944 = or(_T_6943, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6945 = bits(_T_6944, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6946 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6947 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6948 = eq(_T_6947, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40684,7 +40684,7 @@ circuit el2_swerv_wrapper : node _T_6952 = and(_T_6949, _T_6951) @[el2_ifu_bp_ctl.scala 447:81] node _T_6953 = or(_T_6952, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6954 = bits(_T_6953, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6955 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6956 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6957 = eq(_T_6956, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40694,7 +40694,7 @@ circuit el2_swerv_wrapper : node _T_6961 = and(_T_6958, _T_6960) @[el2_ifu_bp_ctl.scala 447:81] node _T_6962 = or(_T_6961, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6963 = bits(_T_6962, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6964 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6965 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6966 = eq(_T_6965, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40704,7 +40704,7 @@ circuit el2_swerv_wrapper : node _T_6970 = and(_T_6967, _T_6969) @[el2_ifu_bp_ctl.scala 447:81] node _T_6971 = or(_T_6970, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6972 = bits(_T_6971, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6973 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6974 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6975 = eq(_T_6974, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40714,7 +40714,7 @@ circuit el2_swerv_wrapper : node _T_6979 = and(_T_6976, _T_6978) @[el2_ifu_bp_ctl.scala 447:81] node _T_6980 = or(_T_6979, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6981 = bits(_T_6980, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6982 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6983 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6984 = eq(_T_6983, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40724,7 +40724,7 @@ circuit el2_swerv_wrapper : node _T_6988 = and(_T_6985, _T_6987) @[el2_ifu_bp_ctl.scala 447:81] node _T_6989 = or(_T_6988, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6990 = bits(_T_6989, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_6991 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_6992 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_6993 = eq(_T_6992, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40734,7 +40734,7 @@ circuit el2_swerv_wrapper : node _T_6997 = and(_T_6994, _T_6996) @[el2_ifu_bp_ctl.scala 447:81] node _T_6998 = or(_T_6997, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_6999 = bits(_T_6998, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7000 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7001 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7002 = eq(_T_7001, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40744,7 +40744,7 @@ circuit el2_swerv_wrapper : node _T_7006 = and(_T_7003, _T_7005) @[el2_ifu_bp_ctl.scala 447:81] node _T_7007 = or(_T_7006, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7008 = bits(_T_7007, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7009 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7010 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7011 = eq(_T_7010, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40754,7 +40754,7 @@ circuit el2_swerv_wrapper : node _T_7015 = and(_T_7012, _T_7014) @[el2_ifu_bp_ctl.scala 447:81] node _T_7016 = or(_T_7015, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7017 = bits(_T_7016, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7018 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7019 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7020 = eq(_T_7019, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40764,7 +40764,7 @@ circuit el2_swerv_wrapper : node _T_7024 = and(_T_7021, _T_7023) @[el2_ifu_bp_ctl.scala 447:81] node _T_7025 = or(_T_7024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7026 = bits(_T_7025, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7027 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7028 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7029 = eq(_T_7028, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40774,7 +40774,7 @@ circuit el2_swerv_wrapper : node _T_7033 = and(_T_7030, _T_7032) @[el2_ifu_bp_ctl.scala 447:81] node _T_7034 = or(_T_7033, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7035 = bits(_T_7034, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7036 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7037 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7038 = eq(_T_7037, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40784,7 +40784,7 @@ circuit el2_swerv_wrapper : node _T_7042 = and(_T_7039, _T_7041) @[el2_ifu_bp_ctl.scala 447:81] node _T_7043 = or(_T_7042, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7044 = bits(_T_7043, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7045 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7046 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7047 = eq(_T_7046, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40794,7 +40794,7 @@ circuit el2_swerv_wrapper : node _T_7051 = and(_T_7048, _T_7050) @[el2_ifu_bp_ctl.scala 447:81] node _T_7052 = or(_T_7051, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7053 = bits(_T_7052, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7054 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7055 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7056 = eq(_T_7055, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40804,7 +40804,7 @@ circuit el2_swerv_wrapper : node _T_7060 = and(_T_7057, _T_7059) @[el2_ifu_bp_ctl.scala 447:81] node _T_7061 = or(_T_7060, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7062 = bits(_T_7061, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7063 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7064 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7065 = eq(_T_7064, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40814,7 +40814,7 @@ circuit el2_swerv_wrapper : node _T_7069 = and(_T_7066, _T_7068) @[el2_ifu_bp_ctl.scala 447:81] node _T_7070 = or(_T_7069, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7071 = bits(_T_7070, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7072 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7073 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7074 = eq(_T_7073, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40824,7 +40824,7 @@ circuit el2_swerv_wrapper : node _T_7078 = and(_T_7075, _T_7077) @[el2_ifu_bp_ctl.scala 447:81] node _T_7079 = or(_T_7078, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7080 = bits(_T_7079, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7081 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7082 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7083 = eq(_T_7082, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40834,7 +40834,7 @@ circuit el2_swerv_wrapper : node _T_7087 = and(_T_7084, _T_7086) @[el2_ifu_bp_ctl.scala 447:81] node _T_7088 = or(_T_7087, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7089 = bits(_T_7088, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7090 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7091 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7092 = eq(_T_7091, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40844,7 +40844,7 @@ circuit el2_swerv_wrapper : node _T_7096 = and(_T_7093, _T_7095) @[el2_ifu_bp_ctl.scala 447:81] node _T_7097 = or(_T_7096, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7098 = bits(_T_7097, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7099 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7100 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7101 = eq(_T_7100, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40854,7 +40854,7 @@ circuit el2_swerv_wrapper : node _T_7105 = and(_T_7102, _T_7104) @[el2_ifu_bp_ctl.scala 447:81] node _T_7106 = or(_T_7105, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7107 = bits(_T_7106, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7108 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7109 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7110 = eq(_T_7109, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40864,7 +40864,7 @@ circuit el2_swerv_wrapper : node _T_7114 = and(_T_7111, _T_7113) @[el2_ifu_bp_ctl.scala 447:81] node _T_7115 = or(_T_7114, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7116 = bits(_T_7115, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7117 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7118 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7119 = eq(_T_7118, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40874,7 +40874,7 @@ circuit el2_swerv_wrapper : node _T_7123 = and(_T_7120, _T_7122) @[el2_ifu_bp_ctl.scala 447:81] node _T_7124 = or(_T_7123, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7125 = bits(_T_7124, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7126 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7127 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7128 = eq(_T_7127, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40884,7 +40884,7 @@ circuit el2_swerv_wrapper : node _T_7132 = and(_T_7129, _T_7131) @[el2_ifu_bp_ctl.scala 447:81] node _T_7133 = or(_T_7132, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7134 = bits(_T_7133, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7135 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7136 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7137 = eq(_T_7136, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40894,7 +40894,7 @@ circuit el2_swerv_wrapper : node _T_7141 = and(_T_7138, _T_7140) @[el2_ifu_bp_ctl.scala 447:81] node _T_7142 = or(_T_7141, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7143 = bits(_T_7142, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7144 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7145 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7146 = eq(_T_7145, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40904,7 +40904,7 @@ circuit el2_swerv_wrapper : node _T_7150 = and(_T_7147, _T_7149) @[el2_ifu_bp_ctl.scala 447:81] node _T_7151 = or(_T_7150, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7152 = bits(_T_7151, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7153 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7154 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7155 = eq(_T_7154, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40914,7 +40914,7 @@ circuit el2_swerv_wrapper : node _T_7159 = and(_T_7156, _T_7158) @[el2_ifu_bp_ctl.scala 447:81] node _T_7160 = or(_T_7159, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7161 = bits(_T_7160, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7162 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7163 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7164 = eq(_T_7163, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40924,7 +40924,7 @@ circuit el2_swerv_wrapper : node _T_7168 = and(_T_7165, _T_7167) @[el2_ifu_bp_ctl.scala 447:81] node _T_7169 = or(_T_7168, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7170 = bits(_T_7169, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7171 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7172 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7173 = eq(_T_7172, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40934,7 +40934,7 @@ circuit el2_swerv_wrapper : node _T_7177 = and(_T_7174, _T_7176) @[el2_ifu_bp_ctl.scala 447:81] node _T_7178 = or(_T_7177, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7179 = bits(_T_7178, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7180 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7181 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7182 = eq(_T_7181, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40944,7 +40944,7 @@ circuit el2_swerv_wrapper : node _T_7186 = and(_T_7183, _T_7185) @[el2_ifu_bp_ctl.scala 447:81] node _T_7187 = or(_T_7186, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7188 = bits(_T_7187, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7189 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7190 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7191 = eq(_T_7190, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40954,7 +40954,7 @@ circuit el2_swerv_wrapper : node _T_7195 = and(_T_7192, _T_7194) @[el2_ifu_bp_ctl.scala 447:81] node _T_7196 = or(_T_7195, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7197 = bits(_T_7196, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7198 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7199 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7200 = eq(_T_7199, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40964,7 +40964,7 @@ circuit el2_swerv_wrapper : node _T_7204 = and(_T_7201, _T_7203) @[el2_ifu_bp_ctl.scala 447:81] node _T_7205 = or(_T_7204, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7206 = bits(_T_7205, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7207 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7208 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7209 = eq(_T_7208, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40974,7 +40974,7 @@ circuit el2_swerv_wrapper : node _T_7213 = and(_T_7210, _T_7212) @[el2_ifu_bp_ctl.scala 447:81] node _T_7214 = or(_T_7213, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7215 = bits(_T_7214, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7216 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7217 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7218 = eq(_T_7217, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40984,7 +40984,7 @@ circuit el2_swerv_wrapper : node _T_7222 = and(_T_7219, _T_7221) @[el2_ifu_bp_ctl.scala 447:81] node _T_7223 = or(_T_7222, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7224 = bits(_T_7223, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7225 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7226 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7227 = eq(_T_7226, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -40994,7 +40994,7 @@ circuit el2_swerv_wrapper : node _T_7231 = and(_T_7228, _T_7230) @[el2_ifu_bp_ctl.scala 447:81] node _T_7232 = or(_T_7231, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7233 = bits(_T_7232, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7234 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7235 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7236 = eq(_T_7235, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41004,7 +41004,7 @@ circuit el2_swerv_wrapper : node _T_7240 = and(_T_7237, _T_7239) @[el2_ifu_bp_ctl.scala 447:81] node _T_7241 = or(_T_7240, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7242 = bits(_T_7241, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7243 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7244 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7245 = eq(_T_7244, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41014,7 +41014,7 @@ circuit el2_swerv_wrapper : node _T_7249 = and(_T_7246, _T_7248) @[el2_ifu_bp_ctl.scala 447:81] node _T_7250 = or(_T_7249, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7251 = bits(_T_7250, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7252 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7253 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7254 = eq(_T_7253, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41024,7 +41024,7 @@ circuit el2_swerv_wrapper : node _T_7258 = and(_T_7255, _T_7257) @[el2_ifu_bp_ctl.scala 447:81] node _T_7259 = or(_T_7258, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7260 = bits(_T_7259, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7261 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7262 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7263 = eq(_T_7262, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41034,7 +41034,7 @@ circuit el2_swerv_wrapper : node _T_7267 = and(_T_7264, _T_7266) @[el2_ifu_bp_ctl.scala 447:81] node _T_7268 = or(_T_7267, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7269 = bits(_T_7268, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7270 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7271 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7272 = eq(_T_7271, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41044,7 +41044,7 @@ circuit el2_swerv_wrapper : node _T_7276 = and(_T_7273, _T_7275) @[el2_ifu_bp_ctl.scala 447:81] node _T_7277 = or(_T_7276, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7278 = bits(_T_7277, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7279 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7280 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7281 = eq(_T_7280, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41054,7 +41054,7 @@ circuit el2_swerv_wrapper : node _T_7285 = and(_T_7282, _T_7284) @[el2_ifu_bp_ctl.scala 447:81] node _T_7286 = or(_T_7285, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7287 = bits(_T_7286, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7288 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7289 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7290 = eq(_T_7289, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41064,7 +41064,7 @@ circuit el2_swerv_wrapper : node _T_7294 = and(_T_7291, _T_7293) @[el2_ifu_bp_ctl.scala 447:81] node _T_7295 = or(_T_7294, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7296 = bits(_T_7295, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7297 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7298 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7299 = eq(_T_7298, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41074,7 +41074,7 @@ circuit el2_swerv_wrapper : node _T_7303 = and(_T_7300, _T_7302) @[el2_ifu_bp_ctl.scala 447:81] node _T_7304 = or(_T_7303, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7305 = bits(_T_7304, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7306 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7307 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7308 = eq(_T_7307, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41084,7 +41084,7 @@ circuit el2_swerv_wrapper : node _T_7312 = and(_T_7309, _T_7311) @[el2_ifu_bp_ctl.scala 447:81] node _T_7313 = or(_T_7312, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7314 = bits(_T_7313, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7315 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7316 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7317 = eq(_T_7316, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41094,7 +41094,7 @@ circuit el2_swerv_wrapper : node _T_7321 = and(_T_7318, _T_7320) @[el2_ifu_bp_ctl.scala 447:81] node _T_7322 = or(_T_7321, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7323 = bits(_T_7322, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7324 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7325 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7326 = eq(_T_7325, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41104,7 +41104,7 @@ circuit el2_swerv_wrapper : node _T_7330 = and(_T_7327, _T_7329) @[el2_ifu_bp_ctl.scala 447:81] node _T_7331 = or(_T_7330, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7332 = bits(_T_7331, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7333 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7334 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7335 = eq(_T_7334, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41114,7 +41114,7 @@ circuit el2_swerv_wrapper : node _T_7339 = and(_T_7336, _T_7338) @[el2_ifu_bp_ctl.scala 447:81] node _T_7340 = or(_T_7339, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7341 = bits(_T_7340, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7342 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7343 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7344 = eq(_T_7343, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41124,7 +41124,7 @@ circuit el2_swerv_wrapper : node _T_7348 = and(_T_7345, _T_7347) @[el2_ifu_bp_ctl.scala 447:81] node _T_7349 = or(_T_7348, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7350 = bits(_T_7349, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7351 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7352 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7353 = eq(_T_7352, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41134,7 +41134,7 @@ circuit el2_swerv_wrapper : node _T_7357 = and(_T_7354, _T_7356) @[el2_ifu_bp_ctl.scala 447:81] node _T_7358 = or(_T_7357, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7359 = bits(_T_7358, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7360 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7361 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7362 = eq(_T_7361, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41144,7 +41144,7 @@ circuit el2_swerv_wrapper : node _T_7366 = and(_T_7363, _T_7365) @[el2_ifu_bp_ctl.scala 447:81] node _T_7367 = or(_T_7366, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7368 = bits(_T_7367, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7369 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7370 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7371 = eq(_T_7370, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41154,7 +41154,7 @@ circuit el2_swerv_wrapper : node _T_7375 = and(_T_7372, _T_7374) @[el2_ifu_bp_ctl.scala 447:81] node _T_7376 = or(_T_7375, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7377 = bits(_T_7376, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7378 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7379 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7380 = eq(_T_7379, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41164,7 +41164,7 @@ circuit el2_swerv_wrapper : node _T_7384 = and(_T_7381, _T_7383) @[el2_ifu_bp_ctl.scala 447:81] node _T_7385 = or(_T_7384, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7386 = bits(_T_7385, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7387 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7388 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7389 = eq(_T_7388, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41174,7 +41174,7 @@ circuit el2_swerv_wrapper : node _T_7393 = and(_T_7390, _T_7392) @[el2_ifu_bp_ctl.scala 447:81] node _T_7394 = or(_T_7393, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7395 = bits(_T_7394, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7396 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7397 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7398 = eq(_T_7397, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41184,7 +41184,7 @@ circuit el2_swerv_wrapper : node _T_7402 = and(_T_7399, _T_7401) @[el2_ifu_bp_ctl.scala 447:81] node _T_7403 = or(_T_7402, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7404 = bits(_T_7403, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7405 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7406 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7407 = eq(_T_7406, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41194,7 +41194,7 @@ circuit el2_swerv_wrapper : node _T_7411 = and(_T_7408, _T_7410) @[el2_ifu_bp_ctl.scala 447:81] node _T_7412 = or(_T_7411, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7413 = bits(_T_7412, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7414 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7415 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7416 = eq(_T_7415, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41204,7 +41204,7 @@ circuit el2_swerv_wrapper : node _T_7420 = and(_T_7417, _T_7419) @[el2_ifu_bp_ctl.scala 447:81] node _T_7421 = or(_T_7420, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7422 = bits(_T_7421, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7423 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7424 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7425 = eq(_T_7424, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41214,7 +41214,7 @@ circuit el2_swerv_wrapper : node _T_7429 = and(_T_7426, _T_7428) @[el2_ifu_bp_ctl.scala 447:81] node _T_7430 = or(_T_7429, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7431 = bits(_T_7430, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7432 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7433 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7434 = eq(_T_7433, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41224,7 +41224,7 @@ circuit el2_swerv_wrapper : node _T_7438 = and(_T_7435, _T_7437) @[el2_ifu_bp_ctl.scala 447:81] node _T_7439 = or(_T_7438, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7440 = bits(_T_7439, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7441 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7442 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7443 = eq(_T_7442, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41234,7 +41234,7 @@ circuit el2_swerv_wrapper : node _T_7447 = and(_T_7444, _T_7446) @[el2_ifu_bp_ctl.scala 447:81] node _T_7448 = or(_T_7447, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7449 = bits(_T_7448, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7450 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7451 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7452 = eq(_T_7451, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41244,7 +41244,7 @@ circuit el2_swerv_wrapper : node _T_7456 = and(_T_7453, _T_7455) @[el2_ifu_bp_ctl.scala 447:81] node _T_7457 = or(_T_7456, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7458 = bits(_T_7457, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7459 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7460 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7461 = eq(_T_7460, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41254,7 +41254,7 @@ circuit el2_swerv_wrapper : node _T_7465 = and(_T_7462, _T_7464) @[el2_ifu_bp_ctl.scala 447:81] node _T_7466 = or(_T_7465, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7467 = bits(_T_7466, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7468 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7469 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7470 = eq(_T_7469, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41264,7 +41264,7 @@ circuit el2_swerv_wrapper : node _T_7474 = and(_T_7471, _T_7473) @[el2_ifu_bp_ctl.scala 447:81] node _T_7475 = or(_T_7474, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7476 = bits(_T_7475, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7477 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7478 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7479 = eq(_T_7478, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41274,7 +41274,7 @@ circuit el2_swerv_wrapper : node _T_7483 = and(_T_7480, _T_7482) @[el2_ifu_bp_ctl.scala 447:81] node _T_7484 = or(_T_7483, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7485 = bits(_T_7484, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7486 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7487 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7488 = eq(_T_7487, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41284,7 +41284,7 @@ circuit el2_swerv_wrapper : node _T_7492 = and(_T_7489, _T_7491) @[el2_ifu_bp_ctl.scala 447:81] node _T_7493 = or(_T_7492, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7494 = bits(_T_7493, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7495 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7496 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7497 = eq(_T_7496, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41294,7 +41294,7 @@ circuit el2_swerv_wrapper : node _T_7501 = and(_T_7498, _T_7500) @[el2_ifu_bp_ctl.scala 447:81] node _T_7502 = or(_T_7501, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7503 = bits(_T_7502, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7504 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7505 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7506 = eq(_T_7505, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41304,7 +41304,7 @@ circuit el2_swerv_wrapper : node _T_7510 = and(_T_7507, _T_7509) @[el2_ifu_bp_ctl.scala 447:81] node _T_7511 = or(_T_7510, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7512 = bits(_T_7511, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7513 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7514 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7515 = eq(_T_7514, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41314,7 +41314,7 @@ circuit el2_swerv_wrapper : node _T_7519 = and(_T_7516, _T_7518) @[el2_ifu_bp_ctl.scala 447:81] node _T_7520 = or(_T_7519, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7521 = bits(_T_7520, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7522 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7523 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7524 = eq(_T_7523, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41324,7 +41324,7 @@ circuit el2_swerv_wrapper : node _T_7528 = and(_T_7525, _T_7527) @[el2_ifu_bp_ctl.scala 447:81] node _T_7529 = or(_T_7528, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7530 = bits(_T_7529, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7531 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7532 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7533 = eq(_T_7532, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41334,7 +41334,7 @@ circuit el2_swerv_wrapper : node _T_7537 = and(_T_7534, _T_7536) @[el2_ifu_bp_ctl.scala 447:81] node _T_7538 = or(_T_7537, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7539 = bits(_T_7538, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7540 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7541 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7542 = eq(_T_7541, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41344,7 +41344,7 @@ circuit el2_swerv_wrapper : node _T_7546 = and(_T_7543, _T_7545) @[el2_ifu_bp_ctl.scala 447:81] node _T_7547 = or(_T_7546, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7548 = bits(_T_7547, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7549 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7550 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7551 = eq(_T_7550, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41354,7 +41354,7 @@ circuit el2_swerv_wrapper : node _T_7555 = and(_T_7552, _T_7554) @[el2_ifu_bp_ctl.scala 447:81] node _T_7556 = or(_T_7555, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7557 = bits(_T_7556, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7558 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7559 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7560 = eq(_T_7559, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41364,7 +41364,7 @@ circuit el2_swerv_wrapper : node _T_7564 = and(_T_7561, _T_7563) @[el2_ifu_bp_ctl.scala 447:81] node _T_7565 = or(_T_7564, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7566 = bits(_T_7565, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7567 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7568 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7569 = eq(_T_7568, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41374,7 +41374,7 @@ circuit el2_swerv_wrapper : node _T_7573 = and(_T_7570, _T_7572) @[el2_ifu_bp_ctl.scala 447:81] node _T_7574 = or(_T_7573, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7575 = bits(_T_7574, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7576 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7577 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7578 = eq(_T_7577, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41384,7 +41384,7 @@ circuit el2_swerv_wrapper : node _T_7582 = and(_T_7579, _T_7581) @[el2_ifu_bp_ctl.scala 447:81] node _T_7583 = or(_T_7582, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7584 = bits(_T_7583, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7585 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7586 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7587 = eq(_T_7586, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41394,7 +41394,7 @@ circuit el2_swerv_wrapper : node _T_7591 = and(_T_7588, _T_7590) @[el2_ifu_bp_ctl.scala 447:81] node _T_7592 = or(_T_7591, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7593 = bits(_T_7592, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7594 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7595 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7596 = eq(_T_7595, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41404,7 +41404,7 @@ circuit el2_swerv_wrapper : node _T_7600 = and(_T_7597, _T_7599) @[el2_ifu_bp_ctl.scala 447:81] node _T_7601 = or(_T_7600, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7602 = bits(_T_7601, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7603 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7604 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7605 = eq(_T_7604, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41414,7 +41414,7 @@ circuit el2_swerv_wrapper : node _T_7609 = and(_T_7606, _T_7608) @[el2_ifu_bp_ctl.scala 447:81] node _T_7610 = or(_T_7609, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7611 = bits(_T_7610, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7612 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7613 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7614 = eq(_T_7613, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41424,7 +41424,7 @@ circuit el2_swerv_wrapper : node _T_7618 = and(_T_7615, _T_7617) @[el2_ifu_bp_ctl.scala 447:81] node _T_7619 = or(_T_7618, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7620 = bits(_T_7619, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7621 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7622 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7623 = eq(_T_7622, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41434,7 +41434,7 @@ circuit el2_swerv_wrapper : node _T_7627 = and(_T_7624, _T_7626) @[el2_ifu_bp_ctl.scala 447:81] node _T_7628 = or(_T_7627, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7629 = bits(_T_7628, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7630 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7631 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7632 = eq(_T_7631, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41444,7 +41444,7 @@ circuit el2_swerv_wrapper : node _T_7636 = and(_T_7633, _T_7635) @[el2_ifu_bp_ctl.scala 447:81] node _T_7637 = or(_T_7636, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7638 = bits(_T_7637, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7639 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7640 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7641 = eq(_T_7640, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41454,7 +41454,7 @@ circuit el2_swerv_wrapper : node _T_7645 = and(_T_7642, _T_7644) @[el2_ifu_bp_ctl.scala 447:81] node _T_7646 = or(_T_7645, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7647 = bits(_T_7646, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7648 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7649 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7650 = eq(_T_7649, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41464,7 +41464,7 @@ circuit el2_swerv_wrapper : node _T_7654 = and(_T_7651, _T_7653) @[el2_ifu_bp_ctl.scala 447:81] node _T_7655 = or(_T_7654, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7656 = bits(_T_7655, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7657 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7658 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7659 = eq(_T_7658, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41474,7 +41474,7 @@ circuit el2_swerv_wrapper : node _T_7663 = and(_T_7660, _T_7662) @[el2_ifu_bp_ctl.scala 447:81] node _T_7664 = or(_T_7663, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7665 = bits(_T_7664, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7666 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7667 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7668 = eq(_T_7667, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41484,7 +41484,7 @@ circuit el2_swerv_wrapper : node _T_7672 = and(_T_7669, _T_7671) @[el2_ifu_bp_ctl.scala 447:81] node _T_7673 = or(_T_7672, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7674 = bits(_T_7673, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7675 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7676 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7677 = eq(_T_7676, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41494,7 +41494,7 @@ circuit el2_swerv_wrapper : node _T_7681 = and(_T_7678, _T_7680) @[el2_ifu_bp_ctl.scala 447:81] node _T_7682 = or(_T_7681, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7683 = bits(_T_7682, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7684 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7685 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7686 = eq(_T_7685, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41504,7 +41504,7 @@ circuit el2_swerv_wrapper : node _T_7690 = and(_T_7687, _T_7689) @[el2_ifu_bp_ctl.scala 447:81] node _T_7691 = or(_T_7690, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7692 = bits(_T_7691, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7693 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7694 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7695 = eq(_T_7694, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41514,7 +41514,7 @@ circuit el2_swerv_wrapper : node _T_7699 = and(_T_7696, _T_7698) @[el2_ifu_bp_ctl.scala 447:81] node _T_7700 = or(_T_7699, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7701 = bits(_T_7700, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7702 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7703 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7704 = eq(_T_7703, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41524,7 +41524,7 @@ circuit el2_swerv_wrapper : node _T_7708 = and(_T_7705, _T_7707) @[el2_ifu_bp_ctl.scala 447:81] node _T_7709 = or(_T_7708, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7710 = bits(_T_7709, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7711 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7712 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7713 = eq(_T_7712, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41534,7 +41534,7 @@ circuit el2_swerv_wrapper : node _T_7717 = and(_T_7714, _T_7716) @[el2_ifu_bp_ctl.scala 447:81] node _T_7718 = or(_T_7717, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7719 = bits(_T_7718, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7720 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7721 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7722 = eq(_T_7721, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41544,7 +41544,7 @@ circuit el2_swerv_wrapper : node _T_7726 = and(_T_7723, _T_7725) @[el2_ifu_bp_ctl.scala 447:81] node _T_7727 = or(_T_7726, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7728 = bits(_T_7727, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7729 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7730 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7731 = eq(_T_7730, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41554,7 +41554,7 @@ circuit el2_swerv_wrapper : node _T_7735 = and(_T_7732, _T_7734) @[el2_ifu_bp_ctl.scala 447:81] node _T_7736 = or(_T_7735, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7737 = bits(_T_7736, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7738 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7739 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7740 = eq(_T_7739, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41564,7 +41564,7 @@ circuit el2_swerv_wrapper : node _T_7744 = and(_T_7741, _T_7743) @[el2_ifu_bp_ctl.scala 447:81] node _T_7745 = or(_T_7744, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7746 = bits(_T_7745, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7747 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7748 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7749 = eq(_T_7748, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41574,7 +41574,7 @@ circuit el2_swerv_wrapper : node _T_7753 = and(_T_7750, _T_7752) @[el2_ifu_bp_ctl.scala 447:81] node _T_7754 = or(_T_7753, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7755 = bits(_T_7754, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7756 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7757 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7758 = eq(_T_7757, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41584,7 +41584,7 @@ circuit el2_swerv_wrapper : node _T_7762 = and(_T_7759, _T_7761) @[el2_ifu_bp_ctl.scala 447:81] node _T_7763 = or(_T_7762, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7764 = bits(_T_7763, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7765 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7766 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7767 = eq(_T_7766, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41594,7 +41594,7 @@ circuit el2_swerv_wrapper : node _T_7771 = and(_T_7768, _T_7770) @[el2_ifu_bp_ctl.scala 447:81] node _T_7772 = or(_T_7771, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7773 = bits(_T_7772, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7774 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7775 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7776 = eq(_T_7775, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41604,7 +41604,7 @@ circuit el2_swerv_wrapper : node _T_7780 = and(_T_7777, _T_7779) @[el2_ifu_bp_ctl.scala 447:81] node _T_7781 = or(_T_7780, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7782 = bits(_T_7781, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7783 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7784 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7785 = eq(_T_7784, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41614,7 +41614,7 @@ circuit el2_swerv_wrapper : node _T_7789 = and(_T_7786, _T_7788) @[el2_ifu_bp_ctl.scala 447:81] node _T_7790 = or(_T_7789, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7791 = bits(_T_7790, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7792 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7793 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7794 = eq(_T_7793, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41624,7 +41624,7 @@ circuit el2_swerv_wrapper : node _T_7798 = and(_T_7795, _T_7797) @[el2_ifu_bp_ctl.scala 447:81] node _T_7799 = or(_T_7798, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7800 = bits(_T_7799, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7801 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7802 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7803 = eq(_T_7802, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41634,7 +41634,7 @@ circuit el2_swerv_wrapper : node _T_7807 = and(_T_7804, _T_7806) @[el2_ifu_bp_ctl.scala 447:81] node _T_7808 = or(_T_7807, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7809 = bits(_T_7808, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7810 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7811 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7812 = eq(_T_7811, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41644,7 +41644,7 @@ circuit el2_swerv_wrapper : node _T_7816 = and(_T_7813, _T_7815) @[el2_ifu_bp_ctl.scala 447:81] node _T_7817 = or(_T_7816, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7818 = bits(_T_7817, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7819 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7820 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7821 = eq(_T_7820, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41654,7 +41654,7 @@ circuit el2_swerv_wrapper : node _T_7825 = and(_T_7822, _T_7824) @[el2_ifu_bp_ctl.scala 447:81] node _T_7826 = or(_T_7825, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7827 = bits(_T_7826, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7828 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7829 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7830 = eq(_T_7829, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41664,7 +41664,7 @@ circuit el2_swerv_wrapper : node _T_7834 = and(_T_7831, _T_7833) @[el2_ifu_bp_ctl.scala 447:81] node _T_7835 = or(_T_7834, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7836 = bits(_T_7835, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7837 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7838 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7839 = eq(_T_7838, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41674,7 +41674,7 @@ circuit el2_swerv_wrapper : node _T_7843 = and(_T_7840, _T_7842) @[el2_ifu_bp_ctl.scala 447:81] node _T_7844 = or(_T_7843, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7845 = bits(_T_7844, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7846 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7847 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7848 = eq(_T_7847, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41684,7 +41684,7 @@ circuit el2_swerv_wrapper : node _T_7852 = and(_T_7849, _T_7851) @[el2_ifu_bp_ctl.scala 447:81] node _T_7853 = or(_T_7852, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7854 = bits(_T_7853, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7855 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7856 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7857 = eq(_T_7856, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41694,7 +41694,7 @@ circuit el2_swerv_wrapper : node _T_7861 = and(_T_7858, _T_7860) @[el2_ifu_bp_ctl.scala 447:81] node _T_7862 = or(_T_7861, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7863 = bits(_T_7862, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7864 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7865 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7866 = eq(_T_7865, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41704,7 +41704,7 @@ circuit el2_swerv_wrapper : node _T_7870 = and(_T_7867, _T_7869) @[el2_ifu_bp_ctl.scala 447:81] node _T_7871 = or(_T_7870, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7872 = bits(_T_7871, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7873 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7874 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7875 = eq(_T_7874, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41714,7 +41714,7 @@ circuit el2_swerv_wrapper : node _T_7879 = and(_T_7876, _T_7878) @[el2_ifu_bp_ctl.scala 447:81] node _T_7880 = or(_T_7879, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7881 = bits(_T_7880, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7882 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7883 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7884 = eq(_T_7883, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41724,7 +41724,7 @@ circuit el2_swerv_wrapper : node _T_7888 = and(_T_7885, _T_7887) @[el2_ifu_bp_ctl.scala 447:81] node _T_7889 = or(_T_7888, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7890 = bits(_T_7889, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7891 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7892 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7893 = eq(_T_7892, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41734,7 +41734,7 @@ circuit el2_swerv_wrapper : node _T_7897 = and(_T_7894, _T_7896) @[el2_ifu_bp_ctl.scala 447:81] node _T_7898 = or(_T_7897, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7899 = bits(_T_7898, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7900 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7901 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7902 = eq(_T_7901, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41744,7 +41744,7 @@ circuit el2_swerv_wrapper : node _T_7906 = and(_T_7903, _T_7905) @[el2_ifu_bp_ctl.scala 447:81] node _T_7907 = or(_T_7906, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7908 = bits(_T_7907, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7909 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7910 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7911 = eq(_T_7910, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41754,7 +41754,7 @@ circuit el2_swerv_wrapper : node _T_7915 = and(_T_7912, _T_7914) @[el2_ifu_bp_ctl.scala 447:81] node _T_7916 = or(_T_7915, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7917 = bits(_T_7916, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7918 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7919 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7920 = eq(_T_7919, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41764,7 +41764,7 @@ circuit el2_swerv_wrapper : node _T_7924 = and(_T_7921, _T_7923) @[el2_ifu_bp_ctl.scala 447:81] node _T_7925 = or(_T_7924, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7926 = bits(_T_7925, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7927 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7928 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7929 = eq(_T_7928, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41774,7 +41774,7 @@ circuit el2_swerv_wrapper : node _T_7933 = and(_T_7930, _T_7932) @[el2_ifu_bp_ctl.scala 447:81] node _T_7934 = or(_T_7933, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7935 = bits(_T_7934, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7936 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7937 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7938 = eq(_T_7937, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41784,7 +41784,7 @@ circuit el2_swerv_wrapper : node _T_7942 = and(_T_7939, _T_7941) @[el2_ifu_bp_ctl.scala 447:81] node _T_7943 = or(_T_7942, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7944 = bits(_T_7943, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7945 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7946 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7947 = eq(_T_7946, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41794,7 +41794,7 @@ circuit el2_swerv_wrapper : node _T_7951 = and(_T_7948, _T_7950) @[el2_ifu_bp_ctl.scala 447:81] node _T_7952 = or(_T_7951, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7953 = bits(_T_7952, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7954 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7955 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7956 = eq(_T_7955, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41804,7 +41804,7 @@ circuit el2_swerv_wrapper : node _T_7960 = and(_T_7957, _T_7959) @[el2_ifu_bp_ctl.scala 447:81] node _T_7961 = or(_T_7960, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7962 = bits(_T_7961, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7963 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7964 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7965 = eq(_T_7964, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41814,7 +41814,7 @@ circuit el2_swerv_wrapper : node _T_7969 = and(_T_7966, _T_7968) @[el2_ifu_bp_ctl.scala 447:81] node _T_7970 = or(_T_7969, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7971 = bits(_T_7970, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7972 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7973 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7974 = eq(_T_7973, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41824,7 +41824,7 @@ circuit el2_swerv_wrapper : node _T_7978 = and(_T_7975, _T_7977) @[el2_ifu_bp_ctl.scala 447:81] node _T_7979 = or(_T_7978, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7980 = bits(_T_7979, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7981 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7982 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7983 = eq(_T_7982, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41834,7 +41834,7 @@ circuit el2_swerv_wrapper : node _T_7987 = and(_T_7984, _T_7986) @[el2_ifu_bp_ctl.scala 447:81] node _T_7988 = or(_T_7987, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7989 = bits(_T_7988, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7990 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_7991 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_7992 = eq(_T_7991, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41844,7 +41844,7 @@ circuit el2_swerv_wrapper : node _T_7996 = and(_T_7993, _T_7995) @[el2_ifu_bp_ctl.scala 447:81] node _T_7997 = or(_T_7996, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_7998 = bits(_T_7997, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_7999 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8000 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8001 = eq(_T_8000, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41854,7 +41854,7 @@ circuit el2_swerv_wrapper : node _T_8005 = and(_T_8002, _T_8004) @[el2_ifu_bp_ctl.scala 447:81] node _T_8006 = or(_T_8005, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8007 = bits(_T_8006, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8008 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8009 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8010 = eq(_T_8009, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41864,7 +41864,7 @@ circuit el2_swerv_wrapper : node _T_8014 = and(_T_8011, _T_8013) @[el2_ifu_bp_ctl.scala 447:81] node _T_8015 = or(_T_8014, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8016 = bits(_T_8015, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8017 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8018 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8019 = eq(_T_8018, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41874,7 +41874,7 @@ circuit el2_swerv_wrapper : node _T_8023 = and(_T_8020, _T_8022) @[el2_ifu_bp_ctl.scala 447:81] node _T_8024 = or(_T_8023, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8025 = bits(_T_8024, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8026 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8027 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8028 = eq(_T_8027, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41884,7 +41884,7 @@ circuit el2_swerv_wrapper : node _T_8032 = and(_T_8029, _T_8031) @[el2_ifu_bp_ctl.scala 447:81] node _T_8033 = or(_T_8032, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8034 = bits(_T_8033, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8035 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8036 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8037 = eq(_T_8036, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41894,7 +41894,7 @@ circuit el2_swerv_wrapper : node _T_8041 = and(_T_8038, _T_8040) @[el2_ifu_bp_ctl.scala 447:81] node _T_8042 = or(_T_8041, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8043 = bits(_T_8042, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8044 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8045 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8046 = eq(_T_8045, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41904,7 +41904,7 @@ circuit el2_swerv_wrapper : node _T_8050 = and(_T_8047, _T_8049) @[el2_ifu_bp_ctl.scala 447:81] node _T_8051 = or(_T_8050, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8052 = bits(_T_8051, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8053 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8054 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8055 = eq(_T_8054, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41914,7 +41914,7 @@ circuit el2_swerv_wrapper : node _T_8059 = and(_T_8056, _T_8058) @[el2_ifu_bp_ctl.scala 447:81] node _T_8060 = or(_T_8059, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8061 = bits(_T_8060, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8062 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8063 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8064 = eq(_T_8063, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41924,7 +41924,7 @@ circuit el2_swerv_wrapper : node _T_8068 = and(_T_8065, _T_8067) @[el2_ifu_bp_ctl.scala 447:81] node _T_8069 = or(_T_8068, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8070 = bits(_T_8069, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8071 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8072 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8073 = eq(_T_8072, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41934,7 +41934,7 @@ circuit el2_swerv_wrapper : node _T_8077 = and(_T_8074, _T_8076) @[el2_ifu_bp_ctl.scala 447:81] node _T_8078 = or(_T_8077, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8079 = bits(_T_8078, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8080 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8081 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8082 = eq(_T_8081, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41944,7 +41944,7 @@ circuit el2_swerv_wrapper : node _T_8086 = and(_T_8083, _T_8085) @[el2_ifu_bp_ctl.scala 447:81] node _T_8087 = or(_T_8086, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8088 = bits(_T_8087, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8089 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8090 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8091 = eq(_T_8090, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41954,7 +41954,7 @@ circuit el2_swerv_wrapper : node _T_8095 = and(_T_8092, _T_8094) @[el2_ifu_bp_ctl.scala 447:81] node _T_8096 = or(_T_8095, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8097 = bits(_T_8096, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8098 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8099 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8100 = eq(_T_8099, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41964,7 +41964,7 @@ circuit el2_swerv_wrapper : node _T_8104 = and(_T_8101, _T_8103) @[el2_ifu_bp_ctl.scala 447:81] node _T_8105 = or(_T_8104, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8106 = bits(_T_8105, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8107 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8108 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8109 = eq(_T_8108, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41974,7 +41974,7 @@ circuit el2_swerv_wrapper : node _T_8113 = and(_T_8110, _T_8112) @[el2_ifu_bp_ctl.scala 447:81] node _T_8114 = or(_T_8113, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8115 = bits(_T_8114, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8116 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8117 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8118 = eq(_T_8117, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41984,7 +41984,7 @@ circuit el2_swerv_wrapper : node _T_8122 = and(_T_8119, _T_8121) @[el2_ifu_bp_ctl.scala 447:81] node _T_8123 = or(_T_8122, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8124 = bits(_T_8123, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8125 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8126 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8127 = eq(_T_8126, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -41994,7 +41994,7 @@ circuit el2_swerv_wrapper : node _T_8131 = and(_T_8128, _T_8130) @[el2_ifu_bp_ctl.scala 447:81] node _T_8132 = or(_T_8131, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8133 = bits(_T_8132, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8134 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8135 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8136 = eq(_T_8135, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42004,7 +42004,7 @@ circuit el2_swerv_wrapper : node _T_8140 = and(_T_8137, _T_8139) @[el2_ifu_bp_ctl.scala 447:81] node _T_8141 = or(_T_8140, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8142 = bits(_T_8141, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8143 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8144 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8145 = eq(_T_8144, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42014,7 +42014,7 @@ circuit el2_swerv_wrapper : node _T_8149 = and(_T_8146, _T_8148) @[el2_ifu_bp_ctl.scala 447:81] node _T_8150 = or(_T_8149, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8151 = bits(_T_8150, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8152 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8153 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8154 = eq(_T_8153, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42024,7 +42024,7 @@ circuit el2_swerv_wrapper : node _T_8158 = and(_T_8155, _T_8157) @[el2_ifu_bp_ctl.scala 447:81] node _T_8159 = or(_T_8158, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8160 = bits(_T_8159, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8161 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8162 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8163 = eq(_T_8162, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42034,7 +42034,7 @@ circuit el2_swerv_wrapper : node _T_8167 = and(_T_8164, _T_8166) @[el2_ifu_bp_ctl.scala 447:81] node _T_8168 = or(_T_8167, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8169 = bits(_T_8168, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8170 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8171 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8172 = eq(_T_8171, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42044,7 +42044,7 @@ circuit el2_swerv_wrapper : node _T_8176 = and(_T_8173, _T_8175) @[el2_ifu_bp_ctl.scala 447:81] node _T_8177 = or(_T_8176, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8178 = bits(_T_8177, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8179 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8180 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8181 = eq(_T_8180, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42054,7 +42054,7 @@ circuit el2_swerv_wrapper : node _T_8185 = and(_T_8182, _T_8184) @[el2_ifu_bp_ctl.scala 447:81] node _T_8186 = or(_T_8185, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8187 = bits(_T_8186, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8188 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8189 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8190 = eq(_T_8189, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42064,7 +42064,7 @@ circuit el2_swerv_wrapper : node _T_8194 = and(_T_8191, _T_8193) @[el2_ifu_bp_ctl.scala 447:81] node _T_8195 = or(_T_8194, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8196 = bits(_T_8195, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8197 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8198 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8199 = eq(_T_8198, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42074,7 +42074,7 @@ circuit el2_swerv_wrapper : node _T_8203 = and(_T_8200, _T_8202) @[el2_ifu_bp_ctl.scala 447:81] node _T_8204 = or(_T_8203, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8205 = bits(_T_8204, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8206 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8207 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8208 = eq(_T_8207, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42084,7 +42084,7 @@ circuit el2_swerv_wrapper : node _T_8212 = and(_T_8209, _T_8211) @[el2_ifu_bp_ctl.scala 447:81] node _T_8213 = or(_T_8212, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8214 = bits(_T_8213, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8215 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8216 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8217 = eq(_T_8216, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42094,7 +42094,7 @@ circuit el2_swerv_wrapper : node _T_8221 = and(_T_8218, _T_8220) @[el2_ifu_bp_ctl.scala 447:81] node _T_8222 = or(_T_8221, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8223 = bits(_T_8222, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8224 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8225 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8226 = eq(_T_8225, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42104,7 +42104,7 @@ circuit el2_swerv_wrapper : node _T_8230 = and(_T_8227, _T_8229) @[el2_ifu_bp_ctl.scala 447:81] node _T_8231 = or(_T_8230, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8232 = bits(_T_8231, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8233 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8234 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8235 = eq(_T_8234, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42114,7 +42114,7 @@ circuit el2_swerv_wrapper : node _T_8239 = and(_T_8236, _T_8238) @[el2_ifu_bp_ctl.scala 447:81] node _T_8240 = or(_T_8239, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8241 = bits(_T_8240, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8242 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8243 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8244 = eq(_T_8243, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42124,7 +42124,7 @@ circuit el2_swerv_wrapper : node _T_8248 = and(_T_8245, _T_8247) @[el2_ifu_bp_ctl.scala 447:81] node _T_8249 = or(_T_8248, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8250 = bits(_T_8249, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8251 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8252 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8253 = eq(_T_8252, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42134,7 +42134,7 @@ circuit el2_swerv_wrapper : node _T_8257 = and(_T_8254, _T_8256) @[el2_ifu_bp_ctl.scala 447:81] node _T_8258 = or(_T_8257, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8259 = bits(_T_8258, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8260 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8261 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8262 = eq(_T_8261, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42144,7 +42144,7 @@ circuit el2_swerv_wrapper : node _T_8266 = and(_T_8263, _T_8265) @[el2_ifu_bp_ctl.scala 447:81] node _T_8267 = or(_T_8266, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8268 = bits(_T_8267, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8269 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8270 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8271 = eq(_T_8270, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42154,7 +42154,7 @@ circuit el2_swerv_wrapper : node _T_8275 = and(_T_8272, _T_8274) @[el2_ifu_bp_ctl.scala 447:81] node _T_8276 = or(_T_8275, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8277 = bits(_T_8276, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8278 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8279 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8280 = eq(_T_8279, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42164,7 +42164,7 @@ circuit el2_swerv_wrapper : node _T_8284 = and(_T_8281, _T_8283) @[el2_ifu_bp_ctl.scala 447:81] node _T_8285 = or(_T_8284, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8286 = bits(_T_8285, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8287 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8288 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8289 = eq(_T_8288, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42174,7 +42174,7 @@ circuit el2_swerv_wrapper : node _T_8293 = and(_T_8290, _T_8292) @[el2_ifu_bp_ctl.scala 447:81] node _T_8294 = or(_T_8293, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8295 = bits(_T_8294, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8296 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8297 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8298 = eq(_T_8297, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42184,7 +42184,7 @@ circuit el2_swerv_wrapper : node _T_8302 = and(_T_8299, _T_8301) @[el2_ifu_bp_ctl.scala 447:81] node _T_8303 = or(_T_8302, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8304 = bits(_T_8303, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8305 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8306 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8307 = eq(_T_8306, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42194,7 +42194,7 @@ circuit el2_swerv_wrapper : node _T_8311 = and(_T_8308, _T_8310) @[el2_ifu_bp_ctl.scala 447:81] node _T_8312 = or(_T_8311, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8313 = bits(_T_8312, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8314 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8315 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8316 = eq(_T_8315, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42204,7 +42204,7 @@ circuit el2_swerv_wrapper : node _T_8320 = and(_T_8317, _T_8319) @[el2_ifu_bp_ctl.scala 447:81] node _T_8321 = or(_T_8320, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8322 = bits(_T_8321, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8323 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8324 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8325 = eq(_T_8324, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42214,7 +42214,7 @@ circuit el2_swerv_wrapper : node _T_8329 = and(_T_8326, _T_8328) @[el2_ifu_bp_ctl.scala 447:81] node _T_8330 = or(_T_8329, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8331 = bits(_T_8330, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8332 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8333 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8334 = eq(_T_8333, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42224,7 +42224,7 @@ circuit el2_swerv_wrapper : node _T_8338 = and(_T_8335, _T_8337) @[el2_ifu_bp_ctl.scala 447:81] node _T_8339 = or(_T_8338, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8340 = bits(_T_8339, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8341 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8342 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8343 = eq(_T_8342, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42234,7 +42234,7 @@ circuit el2_swerv_wrapper : node _T_8347 = and(_T_8344, _T_8346) @[el2_ifu_bp_ctl.scala 447:81] node _T_8348 = or(_T_8347, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8349 = bits(_T_8348, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8350 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8351 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8352 = eq(_T_8351, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42244,7 +42244,7 @@ circuit el2_swerv_wrapper : node _T_8356 = and(_T_8353, _T_8355) @[el2_ifu_bp_ctl.scala 447:81] node _T_8357 = or(_T_8356, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8358 = bits(_T_8357, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8359 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8360 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8361 = eq(_T_8360, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42254,7 +42254,7 @@ circuit el2_swerv_wrapper : node _T_8365 = and(_T_8362, _T_8364) @[el2_ifu_bp_ctl.scala 447:81] node _T_8366 = or(_T_8365, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8367 = bits(_T_8366, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8368 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8369 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8370 = eq(_T_8369, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42264,7 +42264,7 @@ circuit el2_swerv_wrapper : node _T_8374 = and(_T_8371, _T_8373) @[el2_ifu_bp_ctl.scala 447:81] node _T_8375 = or(_T_8374, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8376 = bits(_T_8375, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8377 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8378 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8379 = eq(_T_8378, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42274,7 +42274,7 @@ circuit el2_swerv_wrapper : node _T_8383 = and(_T_8380, _T_8382) @[el2_ifu_bp_ctl.scala 447:81] node _T_8384 = or(_T_8383, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8385 = bits(_T_8384, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8386 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8387 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8388 = eq(_T_8387, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42284,7 +42284,7 @@ circuit el2_swerv_wrapper : node _T_8392 = and(_T_8389, _T_8391) @[el2_ifu_bp_ctl.scala 447:81] node _T_8393 = or(_T_8392, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8394 = bits(_T_8393, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8395 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8396 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8397 = eq(_T_8396, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42294,7 +42294,7 @@ circuit el2_swerv_wrapper : node _T_8401 = and(_T_8398, _T_8400) @[el2_ifu_bp_ctl.scala 447:81] node _T_8402 = or(_T_8401, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8403 = bits(_T_8402, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8404 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8405 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8406 = eq(_T_8405, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42304,7 +42304,7 @@ circuit el2_swerv_wrapper : node _T_8410 = and(_T_8407, _T_8409) @[el2_ifu_bp_ctl.scala 447:81] node _T_8411 = or(_T_8410, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8412 = bits(_T_8411, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8413 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8414 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8415 = eq(_T_8414, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42314,7 +42314,7 @@ circuit el2_swerv_wrapper : node _T_8419 = and(_T_8416, _T_8418) @[el2_ifu_bp_ctl.scala 447:81] node _T_8420 = or(_T_8419, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8421 = bits(_T_8420, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8422 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8423 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8424 = eq(_T_8423, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42324,7 +42324,7 @@ circuit el2_swerv_wrapper : node _T_8428 = and(_T_8425, _T_8427) @[el2_ifu_bp_ctl.scala 447:81] node _T_8429 = or(_T_8428, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8430 = bits(_T_8429, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8431 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8432 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8433 = eq(_T_8432, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42334,7 +42334,7 @@ circuit el2_swerv_wrapper : node _T_8437 = and(_T_8434, _T_8436) @[el2_ifu_bp_ctl.scala 447:81] node _T_8438 = or(_T_8437, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8439 = bits(_T_8438, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8440 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8441 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8442 = eq(_T_8441, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42344,7 +42344,7 @@ circuit el2_swerv_wrapper : node _T_8446 = and(_T_8443, _T_8445) @[el2_ifu_bp_ctl.scala 447:81] node _T_8447 = or(_T_8446, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8448 = bits(_T_8447, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8449 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8450 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8451 = eq(_T_8450, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42354,7 +42354,7 @@ circuit el2_swerv_wrapper : node _T_8455 = and(_T_8452, _T_8454) @[el2_ifu_bp_ctl.scala 447:81] node _T_8456 = or(_T_8455, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8457 = bits(_T_8456, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8458 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8459 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8460 = eq(_T_8459, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42364,7 +42364,7 @@ circuit el2_swerv_wrapper : node _T_8464 = and(_T_8461, _T_8463) @[el2_ifu_bp_ctl.scala 447:81] node _T_8465 = or(_T_8464, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8466 = bits(_T_8465, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8467 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8468 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8469 = eq(_T_8468, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42374,7 +42374,7 @@ circuit el2_swerv_wrapper : node _T_8473 = and(_T_8470, _T_8472) @[el2_ifu_bp_ctl.scala 447:81] node _T_8474 = or(_T_8473, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8475 = bits(_T_8474, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8476 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8477 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8478 = eq(_T_8477, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42384,7 +42384,7 @@ circuit el2_swerv_wrapper : node _T_8482 = and(_T_8479, _T_8481) @[el2_ifu_bp_ctl.scala 447:81] node _T_8483 = or(_T_8482, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8484 = bits(_T_8483, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8485 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8486 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8487 = eq(_T_8486, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42394,7 +42394,7 @@ circuit el2_swerv_wrapper : node _T_8491 = and(_T_8488, _T_8490) @[el2_ifu_bp_ctl.scala 447:81] node _T_8492 = or(_T_8491, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8493 = bits(_T_8492, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8494 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8495 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8496 = eq(_T_8495, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42404,7 +42404,7 @@ circuit el2_swerv_wrapper : node _T_8500 = and(_T_8497, _T_8499) @[el2_ifu_bp_ctl.scala 447:81] node _T_8501 = or(_T_8500, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8502 = bits(_T_8501, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8503 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8504 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8505 = eq(_T_8504, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42414,7 +42414,7 @@ circuit el2_swerv_wrapper : node _T_8509 = and(_T_8506, _T_8508) @[el2_ifu_bp_ctl.scala 447:81] node _T_8510 = or(_T_8509, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8511 = bits(_T_8510, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8512 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8513 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8514 = eq(_T_8513, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42424,7 +42424,7 @@ circuit el2_swerv_wrapper : node _T_8518 = and(_T_8515, _T_8517) @[el2_ifu_bp_ctl.scala 447:81] node _T_8519 = or(_T_8518, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8520 = bits(_T_8519, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8521 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8522 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8523 = eq(_T_8522, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42434,7 +42434,7 @@ circuit el2_swerv_wrapper : node _T_8527 = and(_T_8524, _T_8526) @[el2_ifu_bp_ctl.scala 447:81] node _T_8528 = or(_T_8527, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8529 = bits(_T_8528, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8530 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8531 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8532 = eq(_T_8531, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42444,7 +42444,7 @@ circuit el2_swerv_wrapper : node _T_8536 = and(_T_8533, _T_8535) @[el2_ifu_bp_ctl.scala 447:81] node _T_8537 = or(_T_8536, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8538 = bits(_T_8537, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8539 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8540 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8541 = eq(_T_8540, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42454,7 +42454,7 @@ circuit el2_swerv_wrapper : node _T_8545 = and(_T_8542, _T_8544) @[el2_ifu_bp_ctl.scala 447:81] node _T_8546 = or(_T_8545, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8547 = bits(_T_8546, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8548 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8549 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8550 = eq(_T_8549, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42464,7 +42464,7 @@ circuit el2_swerv_wrapper : node _T_8554 = and(_T_8551, _T_8553) @[el2_ifu_bp_ctl.scala 447:81] node _T_8555 = or(_T_8554, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8556 = bits(_T_8555, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8557 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8558 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8559 = eq(_T_8558, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42474,7 +42474,7 @@ circuit el2_swerv_wrapper : node _T_8563 = and(_T_8560, _T_8562) @[el2_ifu_bp_ctl.scala 447:81] node _T_8564 = or(_T_8563, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8565 = bits(_T_8564, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8566 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8567 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8568 = eq(_T_8567, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42484,7 +42484,7 @@ circuit el2_swerv_wrapper : node _T_8572 = and(_T_8569, _T_8571) @[el2_ifu_bp_ctl.scala 447:81] node _T_8573 = or(_T_8572, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8574 = bits(_T_8573, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8575 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8576 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8577 = eq(_T_8576, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42494,7 +42494,7 @@ circuit el2_swerv_wrapper : node _T_8581 = and(_T_8578, _T_8580) @[el2_ifu_bp_ctl.scala 447:81] node _T_8582 = or(_T_8581, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8583 = bits(_T_8582, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8584 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8585 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8586 = eq(_T_8585, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42504,7 +42504,7 @@ circuit el2_swerv_wrapper : node _T_8590 = and(_T_8587, _T_8589) @[el2_ifu_bp_ctl.scala 447:81] node _T_8591 = or(_T_8590, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8592 = bits(_T_8591, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8593 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8594 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8595 = eq(_T_8594, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42514,7 +42514,7 @@ circuit el2_swerv_wrapper : node _T_8599 = and(_T_8596, _T_8598) @[el2_ifu_bp_ctl.scala 447:81] node _T_8600 = or(_T_8599, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8601 = bits(_T_8600, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8602 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8603 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8604 = eq(_T_8603, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42524,7 +42524,7 @@ circuit el2_swerv_wrapper : node _T_8608 = and(_T_8605, _T_8607) @[el2_ifu_bp_ctl.scala 447:81] node _T_8609 = or(_T_8608, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8610 = bits(_T_8609, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8611 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8612 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8613 = eq(_T_8612, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42534,7 +42534,7 @@ circuit el2_swerv_wrapper : node _T_8617 = and(_T_8614, _T_8616) @[el2_ifu_bp_ctl.scala 447:81] node _T_8618 = or(_T_8617, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8619 = bits(_T_8618, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8620 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8621 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8622 = eq(_T_8621, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42544,7 +42544,7 @@ circuit el2_swerv_wrapper : node _T_8626 = and(_T_8623, _T_8625) @[el2_ifu_bp_ctl.scala 447:81] node _T_8627 = or(_T_8626, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8628 = bits(_T_8627, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8629 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8630 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8631 = eq(_T_8630, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42554,7 +42554,7 @@ circuit el2_swerv_wrapper : node _T_8635 = and(_T_8632, _T_8634) @[el2_ifu_bp_ctl.scala 447:81] node _T_8636 = or(_T_8635, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8637 = bits(_T_8636, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8638 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8639 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8640 = eq(_T_8639, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42564,7 +42564,7 @@ circuit el2_swerv_wrapper : node _T_8644 = and(_T_8641, _T_8643) @[el2_ifu_bp_ctl.scala 447:81] node _T_8645 = or(_T_8644, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8646 = bits(_T_8645, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8647 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8648 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8649 = eq(_T_8648, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42574,7 +42574,7 @@ circuit el2_swerv_wrapper : node _T_8653 = and(_T_8650, _T_8652) @[el2_ifu_bp_ctl.scala 447:81] node _T_8654 = or(_T_8653, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8655 = bits(_T_8654, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8656 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8657 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8658 = eq(_T_8657, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42584,7 +42584,7 @@ circuit el2_swerv_wrapper : node _T_8662 = and(_T_8659, _T_8661) @[el2_ifu_bp_ctl.scala 447:81] node _T_8663 = or(_T_8662, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8664 = bits(_T_8663, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8665 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8666 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8667 = eq(_T_8666, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42594,7 +42594,7 @@ circuit el2_swerv_wrapper : node _T_8671 = and(_T_8668, _T_8670) @[el2_ifu_bp_ctl.scala 447:81] node _T_8672 = or(_T_8671, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8673 = bits(_T_8672, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8674 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8675 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8676 = eq(_T_8675, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42604,7 +42604,7 @@ circuit el2_swerv_wrapper : node _T_8680 = and(_T_8677, _T_8679) @[el2_ifu_bp_ctl.scala 447:81] node _T_8681 = or(_T_8680, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8682 = bits(_T_8681, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8683 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8684 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8685 = eq(_T_8684, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42614,7 +42614,7 @@ circuit el2_swerv_wrapper : node _T_8689 = and(_T_8686, _T_8688) @[el2_ifu_bp_ctl.scala 447:81] node _T_8690 = or(_T_8689, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8691 = bits(_T_8690, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8692 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8693 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8694 = eq(_T_8693, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42624,7 +42624,7 @@ circuit el2_swerv_wrapper : node _T_8698 = and(_T_8695, _T_8697) @[el2_ifu_bp_ctl.scala 447:81] node _T_8699 = or(_T_8698, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8700 = bits(_T_8699, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8701 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8702 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8703 = eq(_T_8702, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42634,7 +42634,7 @@ circuit el2_swerv_wrapper : node _T_8707 = and(_T_8704, _T_8706) @[el2_ifu_bp_ctl.scala 447:81] node _T_8708 = or(_T_8707, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8709 = bits(_T_8708, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8710 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8711 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8712 = eq(_T_8711, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42644,7 +42644,7 @@ circuit el2_swerv_wrapper : node _T_8716 = and(_T_8713, _T_8715) @[el2_ifu_bp_ctl.scala 447:81] node _T_8717 = or(_T_8716, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8718 = bits(_T_8717, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8719 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8720 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8721 = eq(_T_8720, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42654,7 +42654,7 @@ circuit el2_swerv_wrapper : node _T_8725 = and(_T_8722, _T_8724) @[el2_ifu_bp_ctl.scala 447:81] node _T_8726 = or(_T_8725, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8727 = bits(_T_8726, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8728 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8729 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8730 = eq(_T_8729, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42664,7 +42664,7 @@ circuit el2_swerv_wrapper : node _T_8734 = and(_T_8731, _T_8733) @[el2_ifu_bp_ctl.scala 447:81] node _T_8735 = or(_T_8734, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8736 = bits(_T_8735, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8737 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8738 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8739 = eq(_T_8738, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42674,7 +42674,7 @@ circuit el2_swerv_wrapper : node _T_8743 = and(_T_8740, _T_8742) @[el2_ifu_bp_ctl.scala 447:81] node _T_8744 = or(_T_8743, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8745 = bits(_T_8744, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8746 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8747 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8748 = eq(_T_8747, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42684,7 +42684,7 @@ circuit el2_swerv_wrapper : node _T_8752 = and(_T_8749, _T_8751) @[el2_ifu_bp_ctl.scala 447:81] node _T_8753 = or(_T_8752, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8754 = bits(_T_8753, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8755 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8756 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8757 = eq(_T_8756, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42694,7 +42694,7 @@ circuit el2_swerv_wrapper : node _T_8761 = and(_T_8758, _T_8760) @[el2_ifu_bp_ctl.scala 447:81] node _T_8762 = or(_T_8761, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8763 = bits(_T_8762, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8764 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8765 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8766 = eq(_T_8765, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42704,7 +42704,7 @@ circuit el2_swerv_wrapper : node _T_8770 = and(_T_8767, _T_8769) @[el2_ifu_bp_ctl.scala 447:81] node _T_8771 = or(_T_8770, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8772 = bits(_T_8771, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8773 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8774 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8775 = eq(_T_8774, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42714,7 +42714,7 @@ circuit el2_swerv_wrapper : node _T_8779 = and(_T_8776, _T_8778) @[el2_ifu_bp_ctl.scala 447:81] node _T_8780 = or(_T_8779, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8781 = bits(_T_8780, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8782 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8783 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8784 = eq(_T_8783, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42724,7 +42724,7 @@ circuit el2_swerv_wrapper : node _T_8788 = and(_T_8785, _T_8787) @[el2_ifu_bp_ctl.scala 447:81] node _T_8789 = or(_T_8788, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8790 = bits(_T_8789, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8791 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8792 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8793 = eq(_T_8792, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42734,7 +42734,7 @@ circuit el2_swerv_wrapper : node _T_8797 = and(_T_8794, _T_8796) @[el2_ifu_bp_ctl.scala 447:81] node _T_8798 = or(_T_8797, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8799 = bits(_T_8798, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8800 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8801 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8802 = eq(_T_8801, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42744,7 +42744,7 @@ circuit el2_swerv_wrapper : node _T_8806 = and(_T_8803, _T_8805) @[el2_ifu_bp_ctl.scala 447:81] node _T_8807 = or(_T_8806, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8808 = bits(_T_8807, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8809 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8810 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8811 = eq(_T_8810, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42754,7 +42754,7 @@ circuit el2_swerv_wrapper : node _T_8815 = and(_T_8812, _T_8814) @[el2_ifu_bp_ctl.scala 447:81] node _T_8816 = or(_T_8815, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8817 = bits(_T_8816, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8818 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8819 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8820 = eq(_T_8819, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42764,7 +42764,7 @@ circuit el2_swerv_wrapper : node _T_8824 = and(_T_8821, _T_8823) @[el2_ifu_bp_ctl.scala 447:81] node _T_8825 = or(_T_8824, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8826 = bits(_T_8825, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8827 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8828 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8829 = eq(_T_8828, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42774,7 +42774,7 @@ circuit el2_swerv_wrapper : node _T_8833 = and(_T_8830, _T_8832) @[el2_ifu_bp_ctl.scala 447:81] node _T_8834 = or(_T_8833, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8835 = bits(_T_8834, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8836 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8837 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8838 = eq(_T_8837, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42784,7 +42784,7 @@ circuit el2_swerv_wrapper : node _T_8842 = and(_T_8839, _T_8841) @[el2_ifu_bp_ctl.scala 447:81] node _T_8843 = or(_T_8842, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8844 = bits(_T_8843, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8845 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8846 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8847 = eq(_T_8846, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42794,7 +42794,7 @@ circuit el2_swerv_wrapper : node _T_8851 = and(_T_8848, _T_8850) @[el2_ifu_bp_ctl.scala 447:81] node _T_8852 = or(_T_8851, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8853 = bits(_T_8852, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8854 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20] node _T_8855 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8856 = eq(_T_8855, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42804,7 +42804,7 @@ circuit el2_swerv_wrapper : node _T_8860 = and(_T_8857, _T_8859) @[el2_ifu_bp_ctl.scala 447:81] node _T_8861 = or(_T_8860, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8862 = bits(_T_8861, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8863 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8864 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8865 = eq(_T_8864, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42814,7 +42814,7 @@ circuit el2_swerv_wrapper : node _T_8869 = and(_T_8866, _T_8868) @[el2_ifu_bp_ctl.scala 447:81] node _T_8870 = or(_T_8869, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8871 = bits(_T_8870, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8872 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8873 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8874 = eq(_T_8873, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42824,7 +42824,7 @@ circuit el2_swerv_wrapper : node _T_8878 = and(_T_8875, _T_8877) @[el2_ifu_bp_ctl.scala 447:81] node _T_8879 = or(_T_8878, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8880 = bits(_T_8879, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8881 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8882 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8883 = eq(_T_8882, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42834,7 +42834,7 @@ circuit el2_swerv_wrapper : node _T_8887 = and(_T_8884, _T_8886) @[el2_ifu_bp_ctl.scala 447:81] node _T_8888 = or(_T_8887, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8889 = bits(_T_8888, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8890 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8891 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8892 = eq(_T_8891, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42844,7 +42844,7 @@ circuit el2_swerv_wrapper : node _T_8896 = and(_T_8893, _T_8895) @[el2_ifu_bp_ctl.scala 447:81] node _T_8897 = or(_T_8896, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8898 = bits(_T_8897, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8899 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8900 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8901 = eq(_T_8900, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42854,7 +42854,7 @@ circuit el2_swerv_wrapper : node _T_8905 = and(_T_8902, _T_8904) @[el2_ifu_bp_ctl.scala 447:81] node _T_8906 = or(_T_8905, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8907 = bits(_T_8906, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8908 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8909 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8910 = eq(_T_8909, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42864,7 +42864,7 @@ circuit el2_swerv_wrapper : node _T_8914 = and(_T_8911, _T_8913) @[el2_ifu_bp_ctl.scala 447:81] node _T_8915 = or(_T_8914, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8916 = bits(_T_8915, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8917 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8918 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8919 = eq(_T_8918, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42874,7 +42874,7 @@ circuit el2_swerv_wrapper : node _T_8923 = and(_T_8920, _T_8922) @[el2_ifu_bp_ctl.scala 447:81] node _T_8924 = or(_T_8923, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8925 = bits(_T_8924, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8926 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8927 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8928 = eq(_T_8927, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42884,7 +42884,7 @@ circuit el2_swerv_wrapper : node _T_8932 = and(_T_8929, _T_8931) @[el2_ifu_bp_ctl.scala 447:81] node _T_8933 = or(_T_8932, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8934 = bits(_T_8933, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8935 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8936 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8937 = eq(_T_8936, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42894,7 +42894,7 @@ circuit el2_swerv_wrapper : node _T_8941 = and(_T_8938, _T_8940) @[el2_ifu_bp_ctl.scala 447:81] node _T_8942 = or(_T_8941, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8943 = bits(_T_8942, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8944 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8945 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8946 = eq(_T_8945, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42904,7 +42904,7 @@ circuit el2_swerv_wrapper : node _T_8950 = and(_T_8947, _T_8949) @[el2_ifu_bp_ctl.scala 447:81] node _T_8951 = or(_T_8950, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8952 = bits(_T_8951, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8953 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8954 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8955 = eq(_T_8954, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42914,7 +42914,7 @@ circuit el2_swerv_wrapper : node _T_8959 = and(_T_8956, _T_8958) @[el2_ifu_bp_ctl.scala 447:81] node _T_8960 = or(_T_8959, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8961 = bits(_T_8960, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8962 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8963 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8964 = eq(_T_8963, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42924,7 +42924,7 @@ circuit el2_swerv_wrapper : node _T_8968 = and(_T_8965, _T_8967) @[el2_ifu_bp_ctl.scala 447:81] node _T_8969 = or(_T_8968, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8970 = bits(_T_8969, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8971 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8972 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8973 = eq(_T_8972, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42934,7 +42934,7 @@ circuit el2_swerv_wrapper : node _T_8977 = and(_T_8974, _T_8976) @[el2_ifu_bp_ctl.scala 447:81] node _T_8978 = or(_T_8977, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8979 = bits(_T_8978, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8980 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8981 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8982 = eq(_T_8981, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42944,7 +42944,7 @@ circuit el2_swerv_wrapper : node _T_8986 = and(_T_8983, _T_8985) @[el2_ifu_bp_ctl.scala 447:81] node _T_8987 = or(_T_8986, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8988 = bits(_T_8987, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8989 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8990 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_8991 = eq(_T_8990, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42954,7 +42954,7 @@ circuit el2_swerv_wrapper : node _T_8995 = and(_T_8992, _T_8994) @[el2_ifu_bp_ctl.scala 447:81] node _T_8996 = or(_T_8995, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_8997 = bits(_T_8996, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_8998 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_8999 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9000 = eq(_T_8999, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42964,7 +42964,7 @@ circuit el2_swerv_wrapper : node _T_9004 = and(_T_9001, _T_9003) @[el2_ifu_bp_ctl.scala 447:81] node _T_9005 = or(_T_9004, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9006 = bits(_T_9005, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9007 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9008 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9009 = eq(_T_9008, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42974,7 +42974,7 @@ circuit el2_swerv_wrapper : node _T_9013 = and(_T_9010, _T_9012) @[el2_ifu_bp_ctl.scala 447:81] node _T_9014 = or(_T_9013, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9015 = bits(_T_9014, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9016 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9017 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9018 = eq(_T_9017, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42984,7 +42984,7 @@ circuit el2_swerv_wrapper : node _T_9022 = and(_T_9019, _T_9021) @[el2_ifu_bp_ctl.scala 447:81] node _T_9023 = or(_T_9022, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9024 = bits(_T_9023, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9025 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9026 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9027 = eq(_T_9026, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -42994,7 +42994,7 @@ circuit el2_swerv_wrapper : node _T_9031 = and(_T_9028, _T_9030) @[el2_ifu_bp_ctl.scala 447:81] node _T_9032 = or(_T_9031, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9033 = bits(_T_9032, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9034 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9035 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9036 = eq(_T_9035, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43004,7 +43004,7 @@ circuit el2_swerv_wrapper : node _T_9040 = and(_T_9037, _T_9039) @[el2_ifu_bp_ctl.scala 447:81] node _T_9041 = or(_T_9040, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9042 = bits(_T_9041, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9043 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9044 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9045 = eq(_T_9044, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43014,7 +43014,7 @@ circuit el2_swerv_wrapper : node _T_9049 = and(_T_9046, _T_9048) @[el2_ifu_bp_ctl.scala 447:81] node _T_9050 = or(_T_9049, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9051 = bits(_T_9050, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9052 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9053 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9054 = eq(_T_9053, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43024,7 +43024,7 @@ circuit el2_swerv_wrapper : node _T_9058 = and(_T_9055, _T_9057) @[el2_ifu_bp_ctl.scala 447:81] node _T_9059 = or(_T_9058, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9060 = bits(_T_9059, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9061 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9062 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9063 = eq(_T_9062, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43034,7 +43034,7 @@ circuit el2_swerv_wrapper : node _T_9067 = and(_T_9064, _T_9066) @[el2_ifu_bp_ctl.scala 447:81] node _T_9068 = or(_T_9067, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9069 = bits(_T_9068, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9070 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9071 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9072 = eq(_T_9071, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43044,7 +43044,7 @@ circuit el2_swerv_wrapper : node _T_9076 = and(_T_9073, _T_9075) @[el2_ifu_bp_ctl.scala 447:81] node _T_9077 = or(_T_9076, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9078 = bits(_T_9077, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9079 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9080 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9081 = eq(_T_9080, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43054,7 +43054,7 @@ circuit el2_swerv_wrapper : node _T_9085 = and(_T_9082, _T_9084) @[el2_ifu_bp_ctl.scala 447:81] node _T_9086 = or(_T_9085, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9087 = bits(_T_9086, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9088 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9089 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9090 = eq(_T_9089, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43064,7 +43064,7 @@ circuit el2_swerv_wrapper : node _T_9094 = and(_T_9091, _T_9093) @[el2_ifu_bp_ctl.scala 447:81] node _T_9095 = or(_T_9094, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9096 = bits(_T_9095, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9097 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9098 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9099 = eq(_T_9098, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43074,7 +43074,7 @@ circuit el2_swerv_wrapper : node _T_9103 = and(_T_9100, _T_9102) @[el2_ifu_bp_ctl.scala 447:81] node _T_9104 = or(_T_9103, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9105 = bits(_T_9104, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9106 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9107 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9108 = eq(_T_9107, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43084,7 +43084,7 @@ circuit el2_swerv_wrapper : node _T_9112 = and(_T_9109, _T_9111) @[el2_ifu_bp_ctl.scala 447:81] node _T_9113 = or(_T_9112, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9114 = bits(_T_9113, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9115 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9116 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9117 = eq(_T_9116, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43094,7 +43094,7 @@ circuit el2_swerv_wrapper : node _T_9121 = and(_T_9118, _T_9120) @[el2_ifu_bp_ctl.scala 447:81] node _T_9122 = or(_T_9121, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9123 = bits(_T_9122, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9124 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9125 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9126 = eq(_T_9125, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43104,7 +43104,7 @@ circuit el2_swerv_wrapper : node _T_9130 = and(_T_9127, _T_9129) @[el2_ifu_bp_ctl.scala 447:81] node _T_9131 = or(_T_9130, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9132 = bits(_T_9131, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9133 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9134 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9135 = eq(_T_9134, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43114,7 +43114,7 @@ circuit el2_swerv_wrapper : node _T_9139 = and(_T_9136, _T_9138) @[el2_ifu_bp_ctl.scala 447:81] node _T_9140 = or(_T_9139, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9141 = bits(_T_9140, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9142 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9143 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9144 = eq(_T_9143, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43124,7 +43124,7 @@ circuit el2_swerv_wrapper : node _T_9148 = and(_T_9145, _T_9147) @[el2_ifu_bp_ctl.scala 447:81] node _T_9149 = or(_T_9148, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9150 = bits(_T_9149, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9151 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9152 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9153 = eq(_T_9152, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43134,7 +43134,7 @@ circuit el2_swerv_wrapper : node _T_9157 = and(_T_9154, _T_9156) @[el2_ifu_bp_ctl.scala 447:81] node _T_9158 = or(_T_9157, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9159 = bits(_T_9158, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9160 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9161 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9162 = eq(_T_9161, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43144,7 +43144,7 @@ circuit el2_swerv_wrapper : node _T_9166 = and(_T_9163, _T_9165) @[el2_ifu_bp_ctl.scala 447:81] node _T_9167 = or(_T_9166, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9168 = bits(_T_9167, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9169 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9170 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9171 = eq(_T_9170, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43154,7 +43154,7 @@ circuit el2_swerv_wrapper : node _T_9175 = and(_T_9172, _T_9174) @[el2_ifu_bp_ctl.scala 447:81] node _T_9176 = or(_T_9175, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9177 = bits(_T_9176, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9178 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9179 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9180 = eq(_T_9179, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43164,7 +43164,7 @@ circuit el2_swerv_wrapper : node _T_9184 = and(_T_9181, _T_9183) @[el2_ifu_bp_ctl.scala 447:81] node _T_9185 = or(_T_9184, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9186 = bits(_T_9185, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9187 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9188 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9189 = eq(_T_9188, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43174,7 +43174,7 @@ circuit el2_swerv_wrapper : node _T_9193 = and(_T_9190, _T_9192) @[el2_ifu_bp_ctl.scala 447:81] node _T_9194 = or(_T_9193, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9195 = bits(_T_9194, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9196 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9197 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9198 = eq(_T_9197, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43184,7 +43184,7 @@ circuit el2_swerv_wrapper : node _T_9202 = and(_T_9199, _T_9201) @[el2_ifu_bp_ctl.scala 447:81] node _T_9203 = or(_T_9202, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9204 = bits(_T_9203, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9205 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9206 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9207 = eq(_T_9206, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43194,7 +43194,7 @@ circuit el2_swerv_wrapper : node _T_9211 = and(_T_9208, _T_9210) @[el2_ifu_bp_ctl.scala 447:81] node _T_9212 = or(_T_9211, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9213 = bits(_T_9212, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9214 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9215 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9216 = eq(_T_9215, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43204,7 +43204,7 @@ circuit el2_swerv_wrapper : node _T_9220 = and(_T_9217, _T_9219) @[el2_ifu_bp_ctl.scala 447:81] node _T_9221 = or(_T_9220, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9222 = bits(_T_9221, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9223 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9224 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9225 = eq(_T_9224, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43214,7 +43214,7 @@ circuit el2_swerv_wrapper : node _T_9229 = and(_T_9226, _T_9228) @[el2_ifu_bp_ctl.scala 447:81] node _T_9230 = or(_T_9229, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9231 = bits(_T_9230, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9232 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9233 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9234 = eq(_T_9233, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43224,7 +43224,7 @@ circuit el2_swerv_wrapper : node _T_9238 = and(_T_9235, _T_9237) @[el2_ifu_bp_ctl.scala 447:81] node _T_9239 = or(_T_9238, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9240 = bits(_T_9239, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9241 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9242 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9243 = eq(_T_9242, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43234,7 +43234,7 @@ circuit el2_swerv_wrapper : node _T_9247 = and(_T_9244, _T_9246) @[el2_ifu_bp_ctl.scala 447:81] node _T_9248 = or(_T_9247, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9249 = bits(_T_9248, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9250 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9251 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9252 = eq(_T_9251, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43244,7 +43244,7 @@ circuit el2_swerv_wrapper : node _T_9256 = and(_T_9253, _T_9255) @[el2_ifu_bp_ctl.scala 447:81] node _T_9257 = or(_T_9256, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9258 = bits(_T_9257, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9259 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9260 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9261 = eq(_T_9260, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43254,7 +43254,7 @@ circuit el2_swerv_wrapper : node _T_9265 = and(_T_9262, _T_9264) @[el2_ifu_bp_ctl.scala 447:81] node _T_9266 = or(_T_9265, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9267 = bits(_T_9266, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9268 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9269 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9270 = eq(_T_9269, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43264,7 +43264,7 @@ circuit el2_swerv_wrapper : node _T_9274 = and(_T_9271, _T_9273) @[el2_ifu_bp_ctl.scala 447:81] node _T_9275 = or(_T_9274, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9276 = bits(_T_9275, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9277 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9278 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9279 = eq(_T_9278, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43274,7 +43274,7 @@ circuit el2_swerv_wrapper : node _T_9283 = and(_T_9280, _T_9282) @[el2_ifu_bp_ctl.scala 447:81] node _T_9284 = or(_T_9283, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9285 = bits(_T_9284, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9286 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9287 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9288 = eq(_T_9287, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43284,7 +43284,7 @@ circuit el2_swerv_wrapper : node _T_9292 = and(_T_9289, _T_9291) @[el2_ifu_bp_ctl.scala 447:81] node _T_9293 = or(_T_9292, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9294 = bits(_T_9293, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9295 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9296 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9297 = eq(_T_9296, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43294,7 +43294,7 @@ circuit el2_swerv_wrapper : node _T_9301 = and(_T_9298, _T_9300) @[el2_ifu_bp_ctl.scala 447:81] node _T_9302 = or(_T_9301, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9303 = bits(_T_9302, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9304 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9305 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9306 = eq(_T_9305, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43304,7 +43304,7 @@ circuit el2_swerv_wrapper : node _T_9310 = and(_T_9307, _T_9309) @[el2_ifu_bp_ctl.scala 447:81] node _T_9311 = or(_T_9310, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9312 = bits(_T_9311, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9313 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9314 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9315 = eq(_T_9314, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43314,7 +43314,7 @@ circuit el2_swerv_wrapper : node _T_9319 = and(_T_9316, _T_9318) @[el2_ifu_bp_ctl.scala 447:81] node _T_9320 = or(_T_9319, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9321 = bits(_T_9320, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9322 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9323 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9324 = eq(_T_9323, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43324,7 +43324,7 @@ circuit el2_swerv_wrapper : node _T_9328 = and(_T_9325, _T_9327) @[el2_ifu_bp_ctl.scala 447:81] node _T_9329 = or(_T_9328, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9330 = bits(_T_9329, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9331 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9332 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9333 = eq(_T_9332, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43334,7 +43334,7 @@ circuit el2_swerv_wrapper : node _T_9337 = and(_T_9334, _T_9336) @[el2_ifu_bp_ctl.scala 447:81] node _T_9338 = or(_T_9337, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9339 = bits(_T_9338, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9340 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9341 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9342 = eq(_T_9341, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43344,7 +43344,7 @@ circuit el2_swerv_wrapper : node _T_9346 = and(_T_9343, _T_9345) @[el2_ifu_bp_ctl.scala 447:81] node _T_9347 = or(_T_9346, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9348 = bits(_T_9347, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9349 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9350 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9351 = eq(_T_9350, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43354,7 +43354,7 @@ circuit el2_swerv_wrapper : node _T_9355 = and(_T_9352, _T_9354) @[el2_ifu_bp_ctl.scala 447:81] node _T_9356 = or(_T_9355, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9357 = bits(_T_9356, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9358 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9359 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9360 = eq(_T_9359, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43364,7 +43364,7 @@ circuit el2_swerv_wrapper : node _T_9364 = and(_T_9361, _T_9363) @[el2_ifu_bp_ctl.scala 447:81] node _T_9365 = or(_T_9364, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9366 = bits(_T_9365, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9367 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9368 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9369 = eq(_T_9368, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43374,7 +43374,7 @@ circuit el2_swerv_wrapper : node _T_9373 = and(_T_9370, _T_9372) @[el2_ifu_bp_ctl.scala 447:81] node _T_9374 = or(_T_9373, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9375 = bits(_T_9374, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9376 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9377 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9378 = eq(_T_9377, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43384,7 +43384,7 @@ circuit el2_swerv_wrapper : node _T_9382 = and(_T_9379, _T_9381) @[el2_ifu_bp_ctl.scala 447:81] node _T_9383 = or(_T_9382, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9384 = bits(_T_9383, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9385 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9386 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9387 = eq(_T_9386, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43394,7 +43394,7 @@ circuit el2_swerv_wrapper : node _T_9391 = and(_T_9388, _T_9390) @[el2_ifu_bp_ctl.scala 447:81] node _T_9392 = or(_T_9391, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9393 = bits(_T_9392, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9394 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9395 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9396 = eq(_T_9395, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43404,7 +43404,7 @@ circuit el2_swerv_wrapper : node _T_9400 = and(_T_9397, _T_9399) @[el2_ifu_bp_ctl.scala 447:81] node _T_9401 = or(_T_9400, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9402 = bits(_T_9401, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9403 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9404 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9405 = eq(_T_9404, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43414,7 +43414,7 @@ circuit el2_swerv_wrapper : node _T_9409 = and(_T_9406, _T_9408) @[el2_ifu_bp_ctl.scala 447:81] node _T_9410 = or(_T_9409, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9411 = bits(_T_9410, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9412 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9413 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9414 = eq(_T_9413, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43424,7 +43424,7 @@ circuit el2_swerv_wrapper : node _T_9418 = and(_T_9415, _T_9417) @[el2_ifu_bp_ctl.scala 447:81] node _T_9419 = or(_T_9418, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9420 = bits(_T_9419, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9421 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9422 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9423 = eq(_T_9422, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43434,7 +43434,7 @@ circuit el2_swerv_wrapper : node _T_9427 = and(_T_9424, _T_9426) @[el2_ifu_bp_ctl.scala 447:81] node _T_9428 = or(_T_9427, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9429 = bits(_T_9428, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9430 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9431 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9432 = eq(_T_9431, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43444,7 +43444,7 @@ circuit el2_swerv_wrapper : node _T_9436 = and(_T_9433, _T_9435) @[el2_ifu_bp_ctl.scala 447:81] node _T_9437 = or(_T_9436, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9438 = bits(_T_9437, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9439 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9440 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9441 = eq(_T_9440, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43454,7 +43454,7 @@ circuit el2_swerv_wrapper : node _T_9445 = and(_T_9442, _T_9444) @[el2_ifu_bp_ctl.scala 447:81] node _T_9446 = or(_T_9445, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9447 = bits(_T_9446, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9448 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9449 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9450 = eq(_T_9449, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43464,7 +43464,7 @@ circuit el2_swerv_wrapper : node _T_9454 = and(_T_9451, _T_9453) @[el2_ifu_bp_ctl.scala 447:81] node _T_9455 = or(_T_9454, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9456 = bits(_T_9455, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9457 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9458 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9459 = eq(_T_9458, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43474,7 +43474,7 @@ circuit el2_swerv_wrapper : node _T_9463 = and(_T_9460, _T_9462) @[el2_ifu_bp_ctl.scala 447:81] node _T_9464 = or(_T_9463, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9465 = bits(_T_9464, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9466 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9467 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9468 = eq(_T_9467, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43484,7 +43484,7 @@ circuit el2_swerv_wrapper : node _T_9472 = and(_T_9469, _T_9471) @[el2_ifu_bp_ctl.scala 447:81] node _T_9473 = or(_T_9472, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9474 = bits(_T_9473, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9475 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9476 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9477 = eq(_T_9476, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43494,7 +43494,7 @@ circuit el2_swerv_wrapper : node _T_9481 = and(_T_9478, _T_9480) @[el2_ifu_bp_ctl.scala 447:81] node _T_9482 = or(_T_9481, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9483 = bits(_T_9482, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9484 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9485 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9486 = eq(_T_9485, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43504,7 +43504,7 @@ circuit el2_swerv_wrapper : node _T_9490 = and(_T_9487, _T_9489) @[el2_ifu_bp_ctl.scala 447:81] node _T_9491 = or(_T_9490, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9492 = bits(_T_9491, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9493 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9494 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9495 = eq(_T_9494, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43514,7 +43514,7 @@ circuit el2_swerv_wrapper : node _T_9499 = and(_T_9496, _T_9498) @[el2_ifu_bp_ctl.scala 447:81] node _T_9500 = or(_T_9499, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9501 = bits(_T_9500, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9502 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9503 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9504 = eq(_T_9503, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43524,7 +43524,7 @@ circuit el2_swerv_wrapper : node _T_9508 = and(_T_9505, _T_9507) @[el2_ifu_bp_ctl.scala 447:81] node _T_9509 = or(_T_9508, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9510 = bits(_T_9509, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9511 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9512 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9513 = eq(_T_9512, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43534,7 +43534,7 @@ circuit el2_swerv_wrapper : node _T_9517 = and(_T_9514, _T_9516) @[el2_ifu_bp_ctl.scala 447:81] node _T_9518 = or(_T_9517, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9519 = bits(_T_9518, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9520 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9521 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9522 = eq(_T_9521, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43544,7 +43544,7 @@ circuit el2_swerv_wrapper : node _T_9526 = and(_T_9523, _T_9525) @[el2_ifu_bp_ctl.scala 447:81] node _T_9527 = or(_T_9526, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9528 = bits(_T_9527, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9529 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9530 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9531 = eq(_T_9530, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43554,7 +43554,7 @@ circuit el2_swerv_wrapper : node _T_9535 = and(_T_9532, _T_9534) @[el2_ifu_bp_ctl.scala 447:81] node _T_9536 = or(_T_9535, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9537 = bits(_T_9536, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9538 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9539 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9540 = eq(_T_9539, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43564,7 +43564,7 @@ circuit el2_swerv_wrapper : node _T_9544 = and(_T_9541, _T_9543) @[el2_ifu_bp_ctl.scala 447:81] node _T_9545 = or(_T_9544, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9546 = bits(_T_9545, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9547 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9548 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9549 = eq(_T_9548, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43574,7 +43574,7 @@ circuit el2_swerv_wrapper : node _T_9553 = and(_T_9550, _T_9552) @[el2_ifu_bp_ctl.scala 447:81] node _T_9554 = or(_T_9553, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9555 = bits(_T_9554, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9556 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9557 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9558 = eq(_T_9557, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43584,7 +43584,7 @@ circuit el2_swerv_wrapper : node _T_9562 = and(_T_9559, _T_9561) @[el2_ifu_bp_ctl.scala 447:81] node _T_9563 = or(_T_9562, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9564 = bits(_T_9563, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9565 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9566 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9567 = eq(_T_9566, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43594,7 +43594,7 @@ circuit el2_swerv_wrapper : node _T_9571 = and(_T_9568, _T_9570) @[el2_ifu_bp_ctl.scala 447:81] node _T_9572 = or(_T_9571, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9573 = bits(_T_9572, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9574 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9575 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9576 = eq(_T_9575, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43604,7 +43604,7 @@ circuit el2_swerv_wrapper : node _T_9580 = and(_T_9577, _T_9579) @[el2_ifu_bp_ctl.scala 447:81] node _T_9581 = or(_T_9580, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9582 = bits(_T_9581, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9583 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9584 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9585 = eq(_T_9584, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43614,7 +43614,7 @@ circuit el2_swerv_wrapper : node _T_9589 = and(_T_9586, _T_9588) @[el2_ifu_bp_ctl.scala 447:81] node _T_9590 = or(_T_9589, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9591 = bits(_T_9590, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9592 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9593 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9594 = eq(_T_9593, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43624,7 +43624,7 @@ circuit el2_swerv_wrapper : node _T_9598 = and(_T_9595, _T_9597) @[el2_ifu_bp_ctl.scala 447:81] node _T_9599 = or(_T_9598, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9600 = bits(_T_9599, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9601 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9602 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9603 = eq(_T_9602, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43634,7 +43634,7 @@ circuit el2_swerv_wrapper : node _T_9607 = and(_T_9604, _T_9606) @[el2_ifu_bp_ctl.scala 447:81] node _T_9608 = or(_T_9607, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9609 = bits(_T_9608, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9610 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9611 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9612 = eq(_T_9611, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43644,7 +43644,7 @@ circuit el2_swerv_wrapper : node _T_9616 = and(_T_9613, _T_9615) @[el2_ifu_bp_ctl.scala 447:81] node _T_9617 = or(_T_9616, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9618 = bits(_T_9617, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9619 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9620 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9621 = eq(_T_9620, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43654,7 +43654,7 @@ circuit el2_swerv_wrapper : node _T_9625 = and(_T_9622, _T_9624) @[el2_ifu_bp_ctl.scala 447:81] node _T_9626 = or(_T_9625, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9627 = bits(_T_9626, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9628 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9629 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9630 = eq(_T_9629, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43664,7 +43664,7 @@ circuit el2_swerv_wrapper : node _T_9634 = and(_T_9631, _T_9633) @[el2_ifu_bp_ctl.scala 447:81] node _T_9635 = or(_T_9634, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9636 = bits(_T_9635, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9637 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9638 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9639 = eq(_T_9638, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43674,7 +43674,7 @@ circuit el2_swerv_wrapper : node _T_9643 = and(_T_9640, _T_9642) @[el2_ifu_bp_ctl.scala 447:81] node _T_9644 = or(_T_9643, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9645 = bits(_T_9644, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9646 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9647 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9648 = eq(_T_9647, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43684,7 +43684,7 @@ circuit el2_swerv_wrapper : node _T_9652 = and(_T_9649, _T_9651) @[el2_ifu_bp_ctl.scala 447:81] node _T_9653 = or(_T_9652, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9654 = bits(_T_9653, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9655 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9656 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9657 = eq(_T_9656, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43694,7 +43694,7 @@ circuit el2_swerv_wrapper : node _T_9661 = and(_T_9658, _T_9660) @[el2_ifu_bp_ctl.scala 447:81] node _T_9662 = or(_T_9661, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9663 = bits(_T_9662, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9664 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9665 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9666 = eq(_T_9665, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43704,7 +43704,7 @@ circuit el2_swerv_wrapper : node _T_9670 = and(_T_9667, _T_9669) @[el2_ifu_bp_ctl.scala 447:81] node _T_9671 = or(_T_9670, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9672 = bits(_T_9671, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9673 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9674 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9675 = eq(_T_9674, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43714,7 +43714,7 @@ circuit el2_swerv_wrapper : node _T_9679 = and(_T_9676, _T_9678) @[el2_ifu_bp_ctl.scala 447:81] node _T_9680 = or(_T_9679, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9681 = bits(_T_9680, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9682 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9683 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9684 = eq(_T_9683, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43724,7 +43724,7 @@ circuit el2_swerv_wrapper : node _T_9688 = and(_T_9685, _T_9687) @[el2_ifu_bp_ctl.scala 447:81] node _T_9689 = or(_T_9688, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9690 = bits(_T_9689, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9691 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9692 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9693 = eq(_T_9692, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43734,7 +43734,7 @@ circuit el2_swerv_wrapper : node _T_9697 = and(_T_9694, _T_9696) @[el2_ifu_bp_ctl.scala 447:81] node _T_9698 = or(_T_9697, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9699 = bits(_T_9698, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9700 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9701 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9702 = eq(_T_9701, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43744,7 +43744,7 @@ circuit el2_swerv_wrapper : node _T_9706 = and(_T_9703, _T_9705) @[el2_ifu_bp_ctl.scala 447:81] node _T_9707 = or(_T_9706, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9708 = bits(_T_9707, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9709 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9710 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9711 = eq(_T_9710, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43754,7 +43754,7 @@ circuit el2_swerv_wrapper : node _T_9715 = and(_T_9712, _T_9714) @[el2_ifu_bp_ctl.scala 447:81] node _T_9716 = or(_T_9715, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9717 = bits(_T_9716, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9718 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9719 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9720 = eq(_T_9719, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43764,7 +43764,7 @@ circuit el2_swerv_wrapper : node _T_9724 = and(_T_9721, _T_9723) @[el2_ifu_bp_ctl.scala 447:81] node _T_9725 = or(_T_9724, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9726 = bits(_T_9725, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9727 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9728 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9729 = eq(_T_9728, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43774,7 +43774,7 @@ circuit el2_swerv_wrapper : node _T_9733 = and(_T_9730, _T_9732) @[el2_ifu_bp_ctl.scala 447:81] node _T_9734 = or(_T_9733, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9735 = bits(_T_9734, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9736 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9737 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9738 = eq(_T_9737, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43784,7 +43784,7 @@ circuit el2_swerv_wrapper : node _T_9742 = and(_T_9739, _T_9741) @[el2_ifu_bp_ctl.scala 447:81] node _T_9743 = or(_T_9742, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9744 = bits(_T_9743, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9745 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9746 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9747 = eq(_T_9746, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43794,7 +43794,7 @@ circuit el2_swerv_wrapper : node _T_9751 = and(_T_9748, _T_9750) @[el2_ifu_bp_ctl.scala 447:81] node _T_9752 = or(_T_9751, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9753 = bits(_T_9752, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9754 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9755 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9756 = eq(_T_9755, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43804,7 +43804,7 @@ circuit el2_swerv_wrapper : node _T_9760 = and(_T_9757, _T_9759) @[el2_ifu_bp_ctl.scala 447:81] node _T_9761 = or(_T_9760, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9762 = bits(_T_9761, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9763 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9764 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9765 = eq(_T_9764, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43814,7 +43814,7 @@ circuit el2_swerv_wrapper : node _T_9769 = and(_T_9766, _T_9768) @[el2_ifu_bp_ctl.scala 447:81] node _T_9770 = or(_T_9769, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9771 = bits(_T_9770, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9772 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9773 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9774 = eq(_T_9773, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43824,7 +43824,7 @@ circuit el2_swerv_wrapper : node _T_9778 = and(_T_9775, _T_9777) @[el2_ifu_bp_ctl.scala 447:81] node _T_9779 = or(_T_9778, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9780 = bits(_T_9779, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9781 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9782 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9783 = eq(_T_9782, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43834,7 +43834,7 @@ circuit el2_swerv_wrapper : node _T_9787 = and(_T_9784, _T_9786) @[el2_ifu_bp_ctl.scala 447:81] node _T_9788 = or(_T_9787, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9789 = bits(_T_9788, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9790 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9791 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9792 = eq(_T_9791, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43844,7 +43844,7 @@ circuit el2_swerv_wrapper : node _T_9796 = and(_T_9793, _T_9795) @[el2_ifu_bp_ctl.scala 447:81] node _T_9797 = or(_T_9796, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9798 = bits(_T_9797, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9799 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9800 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9801 = eq(_T_9800, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43854,7 +43854,7 @@ circuit el2_swerv_wrapper : node _T_9805 = and(_T_9802, _T_9804) @[el2_ifu_bp_ctl.scala 447:81] node _T_9806 = or(_T_9805, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9807 = bits(_T_9806, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9808 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9809 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9810 = eq(_T_9809, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43864,7 +43864,7 @@ circuit el2_swerv_wrapper : node _T_9814 = and(_T_9811, _T_9813) @[el2_ifu_bp_ctl.scala 447:81] node _T_9815 = or(_T_9814, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9816 = bits(_T_9815, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9817 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9818 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9819 = eq(_T_9818, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43874,7 +43874,7 @@ circuit el2_swerv_wrapper : node _T_9823 = and(_T_9820, _T_9822) @[el2_ifu_bp_ctl.scala 447:81] node _T_9824 = or(_T_9823, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9825 = bits(_T_9824, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9826 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9827 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9828 = eq(_T_9827, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43884,7 +43884,7 @@ circuit el2_swerv_wrapper : node _T_9832 = and(_T_9829, _T_9831) @[el2_ifu_bp_ctl.scala 447:81] node _T_9833 = or(_T_9832, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9834 = bits(_T_9833, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9835 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9836 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9837 = eq(_T_9836, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43894,7 +43894,7 @@ circuit el2_swerv_wrapper : node _T_9841 = and(_T_9838, _T_9840) @[el2_ifu_bp_ctl.scala 447:81] node _T_9842 = or(_T_9841, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9843 = bits(_T_9842, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9844 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9845 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9846 = eq(_T_9845, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43904,7 +43904,7 @@ circuit el2_swerv_wrapper : node _T_9850 = and(_T_9847, _T_9849) @[el2_ifu_bp_ctl.scala 447:81] node _T_9851 = or(_T_9850, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9852 = bits(_T_9851, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9853 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9854 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9855 = eq(_T_9854, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43914,7 +43914,7 @@ circuit el2_swerv_wrapper : node _T_9859 = and(_T_9856, _T_9858) @[el2_ifu_bp_ctl.scala 447:81] node _T_9860 = or(_T_9859, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9861 = bits(_T_9860, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9862 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9863 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9864 = eq(_T_9863, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43924,7 +43924,7 @@ circuit el2_swerv_wrapper : node _T_9868 = and(_T_9865, _T_9867) @[el2_ifu_bp_ctl.scala 447:81] node _T_9869 = or(_T_9868, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9870 = bits(_T_9869, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9871 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9872 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9873 = eq(_T_9872, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43934,7 +43934,7 @@ circuit el2_swerv_wrapper : node _T_9877 = and(_T_9874, _T_9876) @[el2_ifu_bp_ctl.scala 447:81] node _T_9878 = or(_T_9877, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9879 = bits(_T_9878, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9880 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9881 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9882 = eq(_T_9881, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43944,7 +43944,7 @@ circuit el2_swerv_wrapper : node _T_9886 = and(_T_9883, _T_9885) @[el2_ifu_bp_ctl.scala 447:81] node _T_9887 = or(_T_9886, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9888 = bits(_T_9887, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9889 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9890 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9891 = eq(_T_9890, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43954,7 +43954,7 @@ circuit el2_swerv_wrapper : node _T_9895 = and(_T_9892, _T_9894) @[el2_ifu_bp_ctl.scala 447:81] node _T_9896 = or(_T_9895, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9897 = bits(_T_9896, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9898 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9899 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9900 = eq(_T_9899, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43964,7 +43964,7 @@ circuit el2_swerv_wrapper : node _T_9904 = and(_T_9901, _T_9903) @[el2_ifu_bp_ctl.scala 447:81] node _T_9905 = or(_T_9904, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9906 = bits(_T_9905, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9907 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9908 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9909 = eq(_T_9908, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43974,7 +43974,7 @@ circuit el2_swerv_wrapper : node _T_9913 = and(_T_9910, _T_9912) @[el2_ifu_bp_ctl.scala 447:81] node _T_9914 = or(_T_9913, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9915 = bits(_T_9914, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9916 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9917 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9918 = eq(_T_9917, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43984,7 +43984,7 @@ circuit el2_swerv_wrapper : node _T_9922 = and(_T_9919, _T_9921) @[el2_ifu_bp_ctl.scala 447:81] node _T_9923 = or(_T_9922, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9924 = bits(_T_9923, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9925 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9926 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9927 = eq(_T_9926, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -43994,7 +43994,7 @@ circuit el2_swerv_wrapper : node _T_9931 = and(_T_9928, _T_9930) @[el2_ifu_bp_ctl.scala 447:81] node _T_9932 = or(_T_9931, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9933 = bits(_T_9932, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9934 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9935 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9936 = eq(_T_9935, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44004,7 +44004,7 @@ circuit el2_swerv_wrapper : node _T_9940 = and(_T_9937, _T_9939) @[el2_ifu_bp_ctl.scala 447:81] node _T_9941 = or(_T_9940, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9942 = bits(_T_9941, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9943 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9944 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9945 = eq(_T_9944, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44014,7 +44014,7 @@ circuit el2_swerv_wrapper : node _T_9949 = and(_T_9946, _T_9948) @[el2_ifu_bp_ctl.scala 447:81] node _T_9950 = or(_T_9949, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9951 = bits(_T_9950, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9952 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9953 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9954 = eq(_T_9953, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44024,7 +44024,7 @@ circuit el2_swerv_wrapper : node _T_9958 = and(_T_9955, _T_9957) @[el2_ifu_bp_ctl.scala 447:81] node _T_9959 = or(_T_9958, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9960 = bits(_T_9959, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9961 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9962 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9963 = eq(_T_9962, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44034,7 +44034,7 @@ circuit el2_swerv_wrapper : node _T_9967 = and(_T_9964, _T_9966) @[el2_ifu_bp_ctl.scala 447:81] node _T_9968 = or(_T_9967, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9969 = bits(_T_9968, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9970 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9971 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9972 = eq(_T_9971, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44044,7 +44044,7 @@ circuit el2_swerv_wrapper : node _T_9976 = and(_T_9973, _T_9975) @[el2_ifu_bp_ctl.scala 447:81] node _T_9977 = or(_T_9976, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9978 = bits(_T_9977, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9979 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9980 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9981 = eq(_T_9980, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44054,7 +44054,7 @@ circuit el2_swerv_wrapper : node _T_9985 = and(_T_9982, _T_9984) @[el2_ifu_bp_ctl.scala 447:81] node _T_9986 = or(_T_9985, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9987 = bits(_T_9986, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9988 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9989 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9990 = eq(_T_9989, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44064,7 +44064,7 @@ circuit el2_swerv_wrapper : node _T_9994 = and(_T_9991, _T_9993) @[el2_ifu_bp_ctl.scala 447:81] node _T_9995 = or(_T_9994, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_9996 = bits(_T_9995, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_9997 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_9998 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_9999 = eq(_T_9998, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44074,7 +44074,7 @@ circuit el2_swerv_wrapper : node _T_10003 = and(_T_10000, _T_10002) @[el2_ifu_bp_ctl.scala 447:81] node _T_10004 = or(_T_10003, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10005 = bits(_T_10004, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10006 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10007 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10008 = eq(_T_10007, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44084,7 +44084,7 @@ circuit el2_swerv_wrapper : node _T_10012 = and(_T_10009, _T_10011) @[el2_ifu_bp_ctl.scala 447:81] node _T_10013 = or(_T_10012, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10014 = bits(_T_10013, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10015 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10016 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10017 = eq(_T_10016, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44094,7 +44094,7 @@ circuit el2_swerv_wrapper : node _T_10021 = and(_T_10018, _T_10020) @[el2_ifu_bp_ctl.scala 447:81] node _T_10022 = or(_T_10021, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10023 = bits(_T_10022, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10024 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10025 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10026 = eq(_T_10025, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44104,7 +44104,7 @@ circuit el2_swerv_wrapper : node _T_10030 = and(_T_10027, _T_10029) @[el2_ifu_bp_ctl.scala 447:81] node _T_10031 = or(_T_10030, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10032 = bits(_T_10031, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10033 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10034 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10035 = eq(_T_10034, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44114,7 +44114,7 @@ circuit el2_swerv_wrapper : node _T_10039 = and(_T_10036, _T_10038) @[el2_ifu_bp_ctl.scala 447:81] node _T_10040 = or(_T_10039, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10041 = bits(_T_10040, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10042 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10043 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10044 = eq(_T_10043, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44124,7 +44124,7 @@ circuit el2_swerv_wrapper : node _T_10048 = and(_T_10045, _T_10047) @[el2_ifu_bp_ctl.scala 447:81] node _T_10049 = or(_T_10048, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10050 = bits(_T_10049, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10051 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10052 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10053 = eq(_T_10052, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44134,7 +44134,7 @@ circuit el2_swerv_wrapper : node _T_10057 = and(_T_10054, _T_10056) @[el2_ifu_bp_ctl.scala 447:81] node _T_10058 = or(_T_10057, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10059 = bits(_T_10058, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10060 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10061 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10062 = eq(_T_10061, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44144,7 +44144,7 @@ circuit el2_swerv_wrapper : node _T_10066 = and(_T_10063, _T_10065) @[el2_ifu_bp_ctl.scala 447:81] node _T_10067 = or(_T_10066, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10068 = bits(_T_10067, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10069 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10070 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10071 = eq(_T_10070, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44154,7 +44154,7 @@ circuit el2_swerv_wrapper : node _T_10075 = and(_T_10072, _T_10074) @[el2_ifu_bp_ctl.scala 447:81] node _T_10076 = or(_T_10075, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10077 = bits(_T_10076, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10078 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10079 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10080 = eq(_T_10079, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44164,7 +44164,7 @@ circuit el2_swerv_wrapper : node _T_10084 = and(_T_10081, _T_10083) @[el2_ifu_bp_ctl.scala 447:81] node _T_10085 = or(_T_10084, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10086 = bits(_T_10085, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10087 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10088 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10089 = eq(_T_10088, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44174,7 +44174,7 @@ circuit el2_swerv_wrapper : node _T_10093 = and(_T_10090, _T_10092) @[el2_ifu_bp_ctl.scala 447:81] node _T_10094 = or(_T_10093, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10095 = bits(_T_10094, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10096 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10097 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10098 = eq(_T_10097, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44184,7 +44184,7 @@ circuit el2_swerv_wrapper : node _T_10102 = and(_T_10099, _T_10101) @[el2_ifu_bp_ctl.scala 447:81] node _T_10103 = or(_T_10102, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10104 = bits(_T_10103, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10105 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10106 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10107 = eq(_T_10106, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44194,7 +44194,7 @@ circuit el2_swerv_wrapper : node _T_10111 = and(_T_10108, _T_10110) @[el2_ifu_bp_ctl.scala 447:81] node _T_10112 = or(_T_10111, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10113 = bits(_T_10112, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10114 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10115 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10116 = eq(_T_10115, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44204,7 +44204,7 @@ circuit el2_swerv_wrapper : node _T_10120 = and(_T_10117, _T_10119) @[el2_ifu_bp_ctl.scala 447:81] node _T_10121 = or(_T_10120, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10122 = bits(_T_10121, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10123 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10124 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10125 = eq(_T_10124, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44214,7 +44214,7 @@ circuit el2_swerv_wrapper : node _T_10129 = and(_T_10126, _T_10128) @[el2_ifu_bp_ctl.scala 447:81] node _T_10130 = or(_T_10129, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10131 = bits(_T_10130, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10132 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10133 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10134 = eq(_T_10133, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44224,7 +44224,7 @@ circuit el2_swerv_wrapper : node _T_10138 = and(_T_10135, _T_10137) @[el2_ifu_bp_ctl.scala 447:81] node _T_10139 = or(_T_10138, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10140 = bits(_T_10139, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10141 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10142 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10143 = eq(_T_10142, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44234,7 +44234,7 @@ circuit el2_swerv_wrapper : node _T_10147 = and(_T_10144, _T_10146) @[el2_ifu_bp_ctl.scala 447:81] node _T_10148 = or(_T_10147, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10149 = bits(_T_10148, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10150 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10151 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10152 = eq(_T_10151, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44244,7 +44244,7 @@ circuit el2_swerv_wrapper : node _T_10156 = and(_T_10153, _T_10155) @[el2_ifu_bp_ctl.scala 447:81] node _T_10157 = or(_T_10156, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10158 = bits(_T_10157, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10159 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10160 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10161 = eq(_T_10160, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44254,7 +44254,7 @@ circuit el2_swerv_wrapper : node _T_10165 = and(_T_10162, _T_10164) @[el2_ifu_bp_ctl.scala 447:81] node _T_10166 = or(_T_10165, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10167 = bits(_T_10166, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10168 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10169 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10170 = eq(_T_10169, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44264,7 +44264,7 @@ circuit el2_swerv_wrapper : node _T_10174 = and(_T_10171, _T_10173) @[el2_ifu_bp_ctl.scala 447:81] node _T_10175 = or(_T_10174, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10176 = bits(_T_10175, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10177 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10178 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10179 = eq(_T_10178, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44274,7 +44274,7 @@ circuit el2_swerv_wrapper : node _T_10183 = and(_T_10180, _T_10182) @[el2_ifu_bp_ctl.scala 447:81] node _T_10184 = or(_T_10183, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10185 = bits(_T_10184, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10186 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10187 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10188 = eq(_T_10187, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44284,7 +44284,7 @@ circuit el2_swerv_wrapper : node _T_10192 = and(_T_10189, _T_10191) @[el2_ifu_bp_ctl.scala 447:81] node _T_10193 = or(_T_10192, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10194 = bits(_T_10193, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10195 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10196 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10197 = eq(_T_10196, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44294,7 +44294,7 @@ circuit el2_swerv_wrapper : node _T_10201 = and(_T_10198, _T_10200) @[el2_ifu_bp_ctl.scala 447:81] node _T_10202 = or(_T_10201, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10203 = bits(_T_10202, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10204 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10205 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10206 = eq(_T_10205, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44304,7 +44304,7 @@ circuit el2_swerv_wrapper : node _T_10210 = and(_T_10207, _T_10209) @[el2_ifu_bp_ctl.scala 447:81] node _T_10211 = or(_T_10210, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10212 = bits(_T_10211, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10213 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10214 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10215 = eq(_T_10214, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44314,7 +44314,7 @@ circuit el2_swerv_wrapper : node _T_10219 = and(_T_10216, _T_10218) @[el2_ifu_bp_ctl.scala 447:81] node _T_10220 = or(_T_10219, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10221 = bits(_T_10220, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10222 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10223 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10224 = eq(_T_10223, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44324,7 +44324,7 @@ circuit el2_swerv_wrapper : node _T_10228 = and(_T_10225, _T_10227) @[el2_ifu_bp_ctl.scala 447:81] node _T_10229 = or(_T_10228, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10230 = bits(_T_10229, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10231 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10232 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10233 = eq(_T_10232, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44334,7 +44334,7 @@ circuit el2_swerv_wrapper : node _T_10237 = and(_T_10234, _T_10236) @[el2_ifu_bp_ctl.scala 447:81] node _T_10238 = or(_T_10237, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10239 = bits(_T_10238, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10240 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10241 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10242 = eq(_T_10241, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44344,7 +44344,7 @@ circuit el2_swerv_wrapper : node _T_10246 = and(_T_10243, _T_10245) @[el2_ifu_bp_ctl.scala 447:81] node _T_10247 = or(_T_10246, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10248 = bits(_T_10247, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10249 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10250 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10251 = eq(_T_10250, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44354,7 +44354,7 @@ circuit el2_swerv_wrapper : node _T_10255 = and(_T_10252, _T_10254) @[el2_ifu_bp_ctl.scala 447:81] node _T_10256 = or(_T_10255, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10257 = bits(_T_10256, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10258 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10259 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10260 = eq(_T_10259, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44364,7 +44364,7 @@ circuit el2_swerv_wrapper : node _T_10264 = and(_T_10261, _T_10263) @[el2_ifu_bp_ctl.scala 447:81] node _T_10265 = or(_T_10264, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10266 = bits(_T_10265, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10267 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10268 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10269 = eq(_T_10268, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44374,7 +44374,7 @@ circuit el2_swerv_wrapper : node _T_10273 = and(_T_10270, _T_10272) @[el2_ifu_bp_ctl.scala 447:81] node _T_10274 = or(_T_10273, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10275 = bits(_T_10274, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10276 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10277 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10278 = eq(_T_10277, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44384,7 +44384,7 @@ circuit el2_swerv_wrapper : node _T_10282 = and(_T_10279, _T_10281) @[el2_ifu_bp_ctl.scala 447:81] node _T_10283 = or(_T_10282, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10284 = bits(_T_10283, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10285 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10286 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10287 = eq(_T_10286, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44394,7 +44394,7 @@ circuit el2_swerv_wrapper : node _T_10291 = and(_T_10288, _T_10290) @[el2_ifu_bp_ctl.scala 447:81] node _T_10292 = or(_T_10291, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10293 = bits(_T_10292, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10294 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10295 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10296 = eq(_T_10295, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44404,7 +44404,7 @@ circuit el2_swerv_wrapper : node _T_10300 = and(_T_10297, _T_10299) @[el2_ifu_bp_ctl.scala 447:81] node _T_10301 = or(_T_10300, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10302 = bits(_T_10301, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10303 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10304 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10305 = eq(_T_10304, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44414,7 +44414,7 @@ circuit el2_swerv_wrapper : node _T_10309 = and(_T_10306, _T_10308) @[el2_ifu_bp_ctl.scala 447:81] node _T_10310 = or(_T_10309, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10311 = bits(_T_10310, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10312 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10313 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10314 = eq(_T_10313, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44424,7 +44424,7 @@ circuit el2_swerv_wrapper : node _T_10318 = and(_T_10315, _T_10317) @[el2_ifu_bp_ctl.scala 447:81] node _T_10319 = or(_T_10318, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10320 = bits(_T_10319, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10321 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10322 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10323 = eq(_T_10322, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44434,7 +44434,7 @@ circuit el2_swerv_wrapper : node _T_10327 = and(_T_10324, _T_10326) @[el2_ifu_bp_ctl.scala 447:81] node _T_10328 = or(_T_10327, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10329 = bits(_T_10328, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10330 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10331 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10332 = eq(_T_10331, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44444,7 +44444,7 @@ circuit el2_swerv_wrapper : node _T_10336 = and(_T_10333, _T_10335) @[el2_ifu_bp_ctl.scala 447:81] node _T_10337 = or(_T_10336, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10338 = bits(_T_10337, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10339 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10340 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10341 = eq(_T_10340, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44454,7 +44454,7 @@ circuit el2_swerv_wrapper : node _T_10345 = and(_T_10342, _T_10344) @[el2_ifu_bp_ctl.scala 447:81] node _T_10346 = or(_T_10345, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10347 = bits(_T_10346, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10348 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10349 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10350 = eq(_T_10349, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44464,7 +44464,7 @@ circuit el2_swerv_wrapper : node _T_10354 = and(_T_10351, _T_10353) @[el2_ifu_bp_ctl.scala 447:81] node _T_10355 = or(_T_10354, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10356 = bits(_T_10355, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10357 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10358 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10359 = eq(_T_10358, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44474,7 +44474,7 @@ circuit el2_swerv_wrapper : node _T_10363 = and(_T_10360, _T_10362) @[el2_ifu_bp_ctl.scala 447:81] node _T_10364 = or(_T_10363, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10365 = bits(_T_10364, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10366 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10367 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10368 = eq(_T_10367, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44484,7 +44484,7 @@ circuit el2_swerv_wrapper : node _T_10372 = and(_T_10369, _T_10371) @[el2_ifu_bp_ctl.scala 447:81] node _T_10373 = or(_T_10372, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10374 = bits(_T_10373, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10375 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10376 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10377 = eq(_T_10376, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44494,7 +44494,7 @@ circuit el2_swerv_wrapper : node _T_10381 = and(_T_10378, _T_10380) @[el2_ifu_bp_ctl.scala 447:81] node _T_10382 = or(_T_10381, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10383 = bits(_T_10382, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10384 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10385 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10386 = eq(_T_10385, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44504,7 +44504,7 @@ circuit el2_swerv_wrapper : node _T_10390 = and(_T_10387, _T_10389) @[el2_ifu_bp_ctl.scala 447:81] node _T_10391 = or(_T_10390, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10392 = bits(_T_10391, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10393 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10394 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10395 = eq(_T_10394, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44514,7 +44514,7 @@ circuit el2_swerv_wrapper : node _T_10399 = and(_T_10396, _T_10398) @[el2_ifu_bp_ctl.scala 447:81] node _T_10400 = or(_T_10399, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10401 = bits(_T_10400, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10402 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10403 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10404 = eq(_T_10403, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44524,7 +44524,7 @@ circuit el2_swerv_wrapper : node _T_10408 = and(_T_10405, _T_10407) @[el2_ifu_bp_ctl.scala 447:81] node _T_10409 = or(_T_10408, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10410 = bits(_T_10409, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10411 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10412 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10413 = eq(_T_10412, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44534,7 +44534,7 @@ circuit el2_swerv_wrapper : node _T_10417 = and(_T_10414, _T_10416) @[el2_ifu_bp_ctl.scala 447:81] node _T_10418 = or(_T_10417, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10419 = bits(_T_10418, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10420 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10421 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10422 = eq(_T_10421, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44544,7 +44544,7 @@ circuit el2_swerv_wrapper : node _T_10426 = and(_T_10423, _T_10425) @[el2_ifu_bp_ctl.scala 447:81] node _T_10427 = or(_T_10426, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10428 = bits(_T_10427, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10429 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10430 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10431 = eq(_T_10430, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44554,7 +44554,7 @@ circuit el2_swerv_wrapper : node _T_10435 = and(_T_10432, _T_10434) @[el2_ifu_bp_ctl.scala 447:81] node _T_10436 = or(_T_10435, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10437 = bits(_T_10436, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10438 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10439 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10440 = eq(_T_10439, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44564,7 +44564,7 @@ circuit el2_swerv_wrapper : node _T_10444 = and(_T_10441, _T_10443) @[el2_ifu_bp_ctl.scala 447:81] node _T_10445 = or(_T_10444, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10446 = bits(_T_10445, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10447 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10448 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10449 = eq(_T_10448, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44574,7 +44574,7 @@ circuit el2_swerv_wrapper : node _T_10453 = and(_T_10450, _T_10452) @[el2_ifu_bp_ctl.scala 447:81] node _T_10454 = or(_T_10453, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10455 = bits(_T_10454, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10456 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10457 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10458 = eq(_T_10457, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44584,7 +44584,7 @@ circuit el2_swerv_wrapper : node _T_10462 = and(_T_10459, _T_10461) @[el2_ifu_bp_ctl.scala 447:81] node _T_10463 = or(_T_10462, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10464 = bits(_T_10463, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10465 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10466 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10467 = eq(_T_10466, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44594,7 +44594,7 @@ circuit el2_swerv_wrapper : node _T_10471 = and(_T_10468, _T_10470) @[el2_ifu_bp_ctl.scala 447:81] node _T_10472 = or(_T_10471, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10473 = bits(_T_10472, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10474 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10475 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10476 = eq(_T_10475, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44604,7 +44604,7 @@ circuit el2_swerv_wrapper : node _T_10480 = and(_T_10477, _T_10479) @[el2_ifu_bp_ctl.scala 447:81] node _T_10481 = or(_T_10480, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10482 = bits(_T_10481, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10483 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10484 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10485 = eq(_T_10484, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44614,7 +44614,7 @@ circuit el2_swerv_wrapper : node _T_10489 = and(_T_10486, _T_10488) @[el2_ifu_bp_ctl.scala 447:81] node _T_10490 = or(_T_10489, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10491 = bits(_T_10490, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10492 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10493 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10494 = eq(_T_10493, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44624,7 +44624,7 @@ circuit el2_swerv_wrapper : node _T_10498 = and(_T_10495, _T_10497) @[el2_ifu_bp_ctl.scala 447:81] node _T_10499 = or(_T_10498, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10500 = bits(_T_10499, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10501 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10502 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10503 = eq(_T_10502, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44634,7 +44634,7 @@ circuit el2_swerv_wrapper : node _T_10507 = and(_T_10504, _T_10506) @[el2_ifu_bp_ctl.scala 447:81] node _T_10508 = or(_T_10507, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10509 = bits(_T_10508, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10510 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10511 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10512 = eq(_T_10511, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44644,7 +44644,7 @@ circuit el2_swerv_wrapper : node _T_10516 = and(_T_10513, _T_10515) @[el2_ifu_bp_ctl.scala 447:81] node _T_10517 = or(_T_10516, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10518 = bits(_T_10517, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10519 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10520 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10521 = eq(_T_10520, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44654,7 +44654,7 @@ circuit el2_swerv_wrapper : node _T_10525 = and(_T_10522, _T_10524) @[el2_ifu_bp_ctl.scala 447:81] node _T_10526 = or(_T_10525, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10527 = bits(_T_10526, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10528 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10529 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10530 = eq(_T_10529, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44664,7 +44664,7 @@ circuit el2_swerv_wrapper : node _T_10534 = and(_T_10531, _T_10533) @[el2_ifu_bp_ctl.scala 447:81] node _T_10535 = or(_T_10534, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10536 = bits(_T_10535, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10537 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10538 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10539 = eq(_T_10538, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44674,7 +44674,7 @@ circuit el2_swerv_wrapper : node _T_10543 = and(_T_10540, _T_10542) @[el2_ifu_bp_ctl.scala 447:81] node _T_10544 = or(_T_10543, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10545 = bits(_T_10544, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10546 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10547 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10548 = eq(_T_10547, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44684,7 +44684,7 @@ circuit el2_swerv_wrapper : node _T_10552 = and(_T_10549, _T_10551) @[el2_ifu_bp_ctl.scala 447:81] node _T_10553 = or(_T_10552, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10554 = bits(_T_10553, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10555 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10556 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10557 = eq(_T_10556, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44694,7 +44694,7 @@ circuit el2_swerv_wrapper : node _T_10561 = and(_T_10558, _T_10560) @[el2_ifu_bp_ctl.scala 447:81] node _T_10562 = or(_T_10561, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10563 = bits(_T_10562, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10564 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10565 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10566 = eq(_T_10565, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44704,7 +44704,7 @@ circuit el2_swerv_wrapper : node _T_10570 = and(_T_10567, _T_10569) @[el2_ifu_bp_ctl.scala 447:81] node _T_10571 = or(_T_10570, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10572 = bits(_T_10571, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10573 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10574 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10575 = eq(_T_10574, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44714,7 +44714,7 @@ circuit el2_swerv_wrapper : node _T_10579 = and(_T_10576, _T_10578) @[el2_ifu_bp_ctl.scala 447:81] node _T_10580 = or(_T_10579, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10581 = bits(_T_10580, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10582 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10583 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10584 = eq(_T_10583, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44724,7 +44724,7 @@ circuit el2_swerv_wrapper : node _T_10588 = and(_T_10585, _T_10587) @[el2_ifu_bp_ctl.scala 447:81] node _T_10589 = or(_T_10588, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10590 = bits(_T_10589, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10591 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10592 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10593 = eq(_T_10592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44734,7 +44734,7 @@ circuit el2_swerv_wrapper : node _T_10597 = and(_T_10594, _T_10596) @[el2_ifu_bp_ctl.scala 447:81] node _T_10598 = or(_T_10597, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10599 = bits(_T_10598, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10600 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10601 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10602 = eq(_T_10601, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44744,7 +44744,7 @@ circuit el2_swerv_wrapper : node _T_10606 = and(_T_10603, _T_10605) @[el2_ifu_bp_ctl.scala 447:81] node _T_10607 = or(_T_10606, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10608 = bits(_T_10607, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10609 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10610 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10611 = eq(_T_10610, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44754,7 +44754,7 @@ circuit el2_swerv_wrapper : node _T_10615 = and(_T_10612, _T_10614) @[el2_ifu_bp_ctl.scala 447:81] node _T_10616 = or(_T_10615, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10617 = bits(_T_10616, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10618 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10619 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10620 = eq(_T_10619, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44764,7 +44764,7 @@ circuit el2_swerv_wrapper : node _T_10624 = and(_T_10621, _T_10623) @[el2_ifu_bp_ctl.scala 447:81] node _T_10625 = or(_T_10624, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10626 = bits(_T_10625, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10627 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10628 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10629 = eq(_T_10628, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44774,7 +44774,7 @@ circuit el2_swerv_wrapper : node _T_10633 = and(_T_10630, _T_10632) @[el2_ifu_bp_ctl.scala 447:81] node _T_10634 = or(_T_10633, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10635 = bits(_T_10634, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10636 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10637 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10638 = eq(_T_10637, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44784,7 +44784,7 @@ circuit el2_swerv_wrapper : node _T_10642 = and(_T_10639, _T_10641) @[el2_ifu_bp_ctl.scala 447:81] node _T_10643 = or(_T_10642, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10644 = bits(_T_10643, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10645 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10646 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10647 = eq(_T_10646, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44794,7 +44794,7 @@ circuit el2_swerv_wrapper : node _T_10651 = and(_T_10648, _T_10650) @[el2_ifu_bp_ctl.scala 447:81] node _T_10652 = or(_T_10651, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10653 = bits(_T_10652, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10654 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10655 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10656 = eq(_T_10655, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44804,7 +44804,7 @@ circuit el2_swerv_wrapper : node _T_10660 = and(_T_10657, _T_10659) @[el2_ifu_bp_ctl.scala 447:81] node _T_10661 = or(_T_10660, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10662 = bits(_T_10661, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10663 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10664 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10665 = eq(_T_10664, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44814,7 +44814,7 @@ circuit el2_swerv_wrapper : node _T_10669 = and(_T_10666, _T_10668) @[el2_ifu_bp_ctl.scala 447:81] node _T_10670 = or(_T_10669, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10671 = bits(_T_10670, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10672 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10673 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10674 = eq(_T_10673, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44824,7 +44824,7 @@ circuit el2_swerv_wrapper : node _T_10678 = and(_T_10675, _T_10677) @[el2_ifu_bp_ctl.scala 447:81] node _T_10679 = or(_T_10678, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10680 = bits(_T_10679, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10681 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10682 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10683 = eq(_T_10682, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44834,7 +44834,7 @@ circuit el2_swerv_wrapper : node _T_10687 = and(_T_10684, _T_10686) @[el2_ifu_bp_ctl.scala 447:81] node _T_10688 = or(_T_10687, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10689 = bits(_T_10688, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10690 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10691 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10692 = eq(_T_10691, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44844,7 +44844,7 @@ circuit el2_swerv_wrapper : node _T_10696 = and(_T_10693, _T_10695) @[el2_ifu_bp_ctl.scala 447:81] node _T_10697 = or(_T_10696, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10698 = bits(_T_10697, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10699 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10700 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10701 = eq(_T_10700, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44854,7 +44854,7 @@ circuit el2_swerv_wrapper : node _T_10705 = and(_T_10702, _T_10704) @[el2_ifu_bp_ctl.scala 447:81] node _T_10706 = or(_T_10705, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10707 = bits(_T_10706, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10708 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10709 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10710 = eq(_T_10709, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44864,7 +44864,7 @@ circuit el2_swerv_wrapper : node _T_10714 = and(_T_10711, _T_10713) @[el2_ifu_bp_ctl.scala 447:81] node _T_10715 = or(_T_10714, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10716 = bits(_T_10715, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10717 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10718 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10719 = eq(_T_10718, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44874,7 +44874,7 @@ circuit el2_swerv_wrapper : node _T_10723 = and(_T_10720, _T_10722) @[el2_ifu_bp_ctl.scala 447:81] node _T_10724 = or(_T_10723, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10725 = bits(_T_10724, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10726 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10727 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10728 = eq(_T_10727, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44884,7 +44884,7 @@ circuit el2_swerv_wrapper : node _T_10732 = and(_T_10729, _T_10731) @[el2_ifu_bp_ctl.scala 447:81] node _T_10733 = or(_T_10732, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10734 = bits(_T_10733, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10735 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10736 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10737 = eq(_T_10736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44894,7 +44894,7 @@ circuit el2_swerv_wrapper : node _T_10741 = and(_T_10738, _T_10740) @[el2_ifu_bp_ctl.scala 447:81] node _T_10742 = or(_T_10741, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10743 = bits(_T_10742, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10744 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10745 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10746 = eq(_T_10745, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44904,7 +44904,7 @@ circuit el2_swerv_wrapper : node _T_10750 = and(_T_10747, _T_10749) @[el2_ifu_bp_ctl.scala 447:81] node _T_10751 = or(_T_10750, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10752 = bits(_T_10751, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10753 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10754 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10755 = eq(_T_10754, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44914,7 +44914,7 @@ circuit el2_swerv_wrapper : node _T_10759 = and(_T_10756, _T_10758) @[el2_ifu_bp_ctl.scala 447:81] node _T_10760 = or(_T_10759, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10761 = bits(_T_10760, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10762 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10763 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10764 = eq(_T_10763, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44924,7 +44924,7 @@ circuit el2_swerv_wrapper : node _T_10768 = and(_T_10765, _T_10767) @[el2_ifu_bp_ctl.scala 447:81] node _T_10769 = or(_T_10768, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10770 = bits(_T_10769, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10771 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10772 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10773 = eq(_T_10772, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44934,7 +44934,7 @@ circuit el2_swerv_wrapper : node _T_10777 = and(_T_10774, _T_10776) @[el2_ifu_bp_ctl.scala 447:81] node _T_10778 = or(_T_10777, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10779 = bits(_T_10778, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10780 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10781 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10782 = eq(_T_10781, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44944,7 +44944,7 @@ circuit el2_swerv_wrapper : node _T_10786 = and(_T_10783, _T_10785) @[el2_ifu_bp_ctl.scala 447:81] node _T_10787 = or(_T_10786, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10788 = bits(_T_10787, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10789 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10790 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10791 = eq(_T_10790, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44954,7 +44954,7 @@ circuit el2_swerv_wrapper : node _T_10795 = and(_T_10792, _T_10794) @[el2_ifu_bp_ctl.scala 447:81] node _T_10796 = or(_T_10795, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10797 = bits(_T_10796, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10798 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10799 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10800 = eq(_T_10799, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44964,7 +44964,7 @@ circuit el2_swerv_wrapper : node _T_10804 = and(_T_10801, _T_10803) @[el2_ifu_bp_ctl.scala 447:81] node _T_10805 = or(_T_10804, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10806 = bits(_T_10805, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10807 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10808 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10809 = eq(_T_10808, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44974,7 +44974,7 @@ circuit el2_swerv_wrapper : node _T_10813 = and(_T_10810, _T_10812) @[el2_ifu_bp_ctl.scala 447:81] node _T_10814 = or(_T_10813, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10815 = bits(_T_10814, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10816 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10817 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10818 = eq(_T_10817, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44984,7 +44984,7 @@ circuit el2_swerv_wrapper : node _T_10822 = and(_T_10819, _T_10821) @[el2_ifu_bp_ctl.scala 447:81] node _T_10823 = or(_T_10822, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10824 = bits(_T_10823, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10825 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10826 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10827 = eq(_T_10826, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -44994,7 +44994,7 @@ circuit el2_swerv_wrapper : node _T_10831 = and(_T_10828, _T_10830) @[el2_ifu_bp_ctl.scala 447:81] node _T_10832 = or(_T_10831, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10833 = bits(_T_10832, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10834 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10835 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10836 = eq(_T_10835, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45004,7 +45004,7 @@ circuit el2_swerv_wrapper : node _T_10840 = and(_T_10837, _T_10839) @[el2_ifu_bp_ctl.scala 447:81] node _T_10841 = or(_T_10840, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10842 = bits(_T_10841, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10843 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10844 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10845 = eq(_T_10844, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45014,7 +45014,7 @@ circuit el2_swerv_wrapper : node _T_10849 = and(_T_10846, _T_10848) @[el2_ifu_bp_ctl.scala 447:81] node _T_10850 = or(_T_10849, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10851 = bits(_T_10850, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10852 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10853 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10854 = eq(_T_10853, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45024,7 +45024,7 @@ circuit el2_swerv_wrapper : node _T_10858 = and(_T_10855, _T_10857) @[el2_ifu_bp_ctl.scala 447:81] node _T_10859 = or(_T_10858, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10860 = bits(_T_10859, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10861 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10862 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10863 = eq(_T_10862, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45034,7 +45034,7 @@ circuit el2_swerv_wrapper : node _T_10867 = and(_T_10864, _T_10866) @[el2_ifu_bp_ctl.scala 447:81] node _T_10868 = or(_T_10867, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10869 = bits(_T_10868, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10870 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10871 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10872 = eq(_T_10871, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45044,7 +45044,7 @@ circuit el2_swerv_wrapper : node _T_10876 = and(_T_10873, _T_10875) @[el2_ifu_bp_ctl.scala 447:81] node _T_10877 = or(_T_10876, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10878 = bits(_T_10877, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10879 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10880 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10881 = eq(_T_10880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45054,7 +45054,7 @@ circuit el2_swerv_wrapper : node _T_10885 = and(_T_10882, _T_10884) @[el2_ifu_bp_ctl.scala 447:81] node _T_10886 = or(_T_10885, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10887 = bits(_T_10886, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10888 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10889 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10890 = eq(_T_10889, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45064,7 +45064,7 @@ circuit el2_swerv_wrapper : node _T_10894 = and(_T_10891, _T_10893) @[el2_ifu_bp_ctl.scala 447:81] node _T_10895 = or(_T_10894, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10896 = bits(_T_10895, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10897 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10898 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10899 = eq(_T_10898, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45074,7 +45074,7 @@ circuit el2_swerv_wrapper : node _T_10903 = and(_T_10900, _T_10902) @[el2_ifu_bp_ctl.scala 447:81] node _T_10904 = or(_T_10903, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10905 = bits(_T_10904, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10906 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10907 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10908 = eq(_T_10907, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45084,7 +45084,7 @@ circuit el2_swerv_wrapper : node _T_10912 = and(_T_10909, _T_10911) @[el2_ifu_bp_ctl.scala 447:81] node _T_10913 = or(_T_10912, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10914 = bits(_T_10913, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10915 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10916 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10917 = eq(_T_10916, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45094,7 +45094,7 @@ circuit el2_swerv_wrapper : node _T_10921 = and(_T_10918, _T_10920) @[el2_ifu_bp_ctl.scala 447:81] node _T_10922 = or(_T_10921, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10923 = bits(_T_10922, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10924 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10925 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10926 = eq(_T_10925, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45104,7 +45104,7 @@ circuit el2_swerv_wrapper : node _T_10930 = and(_T_10927, _T_10929) @[el2_ifu_bp_ctl.scala 447:81] node _T_10931 = or(_T_10930, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10932 = bits(_T_10931, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10933 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10934 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10935 = eq(_T_10934, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45114,7 +45114,7 @@ circuit el2_swerv_wrapper : node _T_10939 = and(_T_10936, _T_10938) @[el2_ifu_bp_ctl.scala 447:81] node _T_10940 = or(_T_10939, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10941 = bits(_T_10940, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10942 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10943 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10944 = eq(_T_10943, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45124,7 +45124,7 @@ circuit el2_swerv_wrapper : node _T_10948 = and(_T_10945, _T_10947) @[el2_ifu_bp_ctl.scala 447:81] node _T_10949 = or(_T_10948, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10950 = bits(_T_10949, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10951 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10952 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10953 = eq(_T_10952, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45134,7 +45134,7 @@ circuit el2_swerv_wrapper : node _T_10957 = and(_T_10954, _T_10956) @[el2_ifu_bp_ctl.scala 447:81] node _T_10958 = or(_T_10957, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10959 = bits(_T_10958, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10960 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10961 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10962 = eq(_T_10961, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45144,7 +45144,7 @@ circuit el2_swerv_wrapper : node _T_10966 = and(_T_10963, _T_10965) @[el2_ifu_bp_ctl.scala 447:81] node _T_10967 = or(_T_10966, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10968 = bits(_T_10967, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10969 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10970 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10971 = eq(_T_10970, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45154,7 +45154,7 @@ circuit el2_swerv_wrapper : node _T_10975 = and(_T_10972, _T_10974) @[el2_ifu_bp_ctl.scala 447:81] node _T_10976 = or(_T_10975, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10977 = bits(_T_10976, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10978 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10979 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10980 = eq(_T_10979, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45164,7 +45164,7 @@ circuit el2_swerv_wrapper : node _T_10984 = and(_T_10981, _T_10983) @[el2_ifu_bp_ctl.scala 447:81] node _T_10985 = or(_T_10984, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10986 = bits(_T_10985, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10987 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10988 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10989 = eq(_T_10988, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45174,7 +45174,7 @@ circuit el2_swerv_wrapper : node _T_10993 = and(_T_10990, _T_10992) @[el2_ifu_bp_ctl.scala 447:81] node _T_10994 = or(_T_10993, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_10995 = bits(_T_10994, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_10996 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_10997 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_10998 = eq(_T_10997, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45184,7 +45184,7 @@ circuit el2_swerv_wrapper : node _T_11002 = and(_T_10999, _T_11001) @[el2_ifu_bp_ctl.scala 447:81] node _T_11003 = or(_T_11002, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11004 = bits(_T_11003, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11005 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11006 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11007 = eq(_T_11006, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45194,7 +45194,7 @@ circuit el2_swerv_wrapper : node _T_11011 = and(_T_11008, _T_11010) @[el2_ifu_bp_ctl.scala 447:81] node _T_11012 = or(_T_11011, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11013 = bits(_T_11012, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11014 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11015 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11016 = eq(_T_11015, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45204,7 +45204,7 @@ circuit el2_swerv_wrapper : node _T_11020 = and(_T_11017, _T_11019) @[el2_ifu_bp_ctl.scala 447:81] node _T_11021 = or(_T_11020, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11022 = bits(_T_11021, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11023 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11024 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11025 = eq(_T_11024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45214,7 +45214,7 @@ circuit el2_swerv_wrapper : node _T_11029 = and(_T_11026, _T_11028) @[el2_ifu_bp_ctl.scala 447:81] node _T_11030 = or(_T_11029, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11031 = bits(_T_11030, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11032 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11033 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11034 = eq(_T_11033, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45224,7 +45224,7 @@ circuit el2_swerv_wrapper : node _T_11038 = and(_T_11035, _T_11037) @[el2_ifu_bp_ctl.scala 447:81] node _T_11039 = or(_T_11038, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11040 = bits(_T_11039, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11041 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11042 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11043 = eq(_T_11042, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45234,7 +45234,7 @@ circuit el2_swerv_wrapper : node _T_11047 = and(_T_11044, _T_11046) @[el2_ifu_bp_ctl.scala 447:81] node _T_11048 = or(_T_11047, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11049 = bits(_T_11048, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11050 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11051 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11052 = eq(_T_11051, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45244,7 +45244,7 @@ circuit el2_swerv_wrapper : node _T_11056 = and(_T_11053, _T_11055) @[el2_ifu_bp_ctl.scala 447:81] node _T_11057 = or(_T_11056, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11058 = bits(_T_11057, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11059 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11060 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11061 = eq(_T_11060, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45254,7 +45254,7 @@ circuit el2_swerv_wrapper : node _T_11065 = and(_T_11062, _T_11064) @[el2_ifu_bp_ctl.scala 447:81] node _T_11066 = or(_T_11065, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11067 = bits(_T_11066, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11068 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11069 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11070 = eq(_T_11069, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45264,7 +45264,7 @@ circuit el2_swerv_wrapper : node _T_11074 = and(_T_11071, _T_11073) @[el2_ifu_bp_ctl.scala 447:81] node _T_11075 = or(_T_11074, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11076 = bits(_T_11075, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11077 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11078 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11079 = eq(_T_11078, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45274,7 +45274,7 @@ circuit el2_swerv_wrapper : node _T_11083 = and(_T_11080, _T_11082) @[el2_ifu_bp_ctl.scala 447:81] node _T_11084 = or(_T_11083, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11085 = bits(_T_11084, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11086 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11087 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11088 = eq(_T_11087, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45284,7 +45284,7 @@ circuit el2_swerv_wrapper : node _T_11092 = and(_T_11089, _T_11091) @[el2_ifu_bp_ctl.scala 447:81] node _T_11093 = or(_T_11092, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11094 = bits(_T_11093, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11095 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11096 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11097 = eq(_T_11096, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45294,7 +45294,7 @@ circuit el2_swerv_wrapper : node _T_11101 = and(_T_11098, _T_11100) @[el2_ifu_bp_ctl.scala 447:81] node _T_11102 = or(_T_11101, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11103 = bits(_T_11102, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11104 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11105 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11106 = eq(_T_11105, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45304,7 +45304,7 @@ circuit el2_swerv_wrapper : node _T_11110 = and(_T_11107, _T_11109) @[el2_ifu_bp_ctl.scala 447:81] node _T_11111 = or(_T_11110, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11112 = bits(_T_11111, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11113 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11114 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11115 = eq(_T_11114, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45314,7 +45314,7 @@ circuit el2_swerv_wrapper : node _T_11119 = and(_T_11116, _T_11118) @[el2_ifu_bp_ctl.scala 447:81] node _T_11120 = or(_T_11119, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11121 = bits(_T_11120, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11122 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11123 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11124 = eq(_T_11123, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45324,7 +45324,7 @@ circuit el2_swerv_wrapper : node _T_11128 = and(_T_11125, _T_11127) @[el2_ifu_bp_ctl.scala 447:81] node _T_11129 = or(_T_11128, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11130 = bits(_T_11129, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11131 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11132 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11133 = eq(_T_11132, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45334,7 +45334,7 @@ circuit el2_swerv_wrapper : node _T_11137 = and(_T_11134, _T_11136) @[el2_ifu_bp_ctl.scala 447:81] node _T_11138 = or(_T_11137, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11139 = bits(_T_11138, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11140 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11141 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11142 = eq(_T_11141, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45344,7 +45344,7 @@ circuit el2_swerv_wrapper : node _T_11146 = and(_T_11143, _T_11145) @[el2_ifu_bp_ctl.scala 447:81] node _T_11147 = or(_T_11146, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11148 = bits(_T_11147, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11149 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11150 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11151 = eq(_T_11150, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45354,7 +45354,7 @@ circuit el2_swerv_wrapper : node _T_11155 = and(_T_11152, _T_11154) @[el2_ifu_bp_ctl.scala 447:81] node _T_11156 = or(_T_11155, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11157 = bits(_T_11156, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] node _T_11158 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20] node _T_11159 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37] node _T_11160 = eq(_T_11159, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74] @@ -45364,7 +45364,7 @@ circuit el2_swerv_wrapper : node _T_11164 = and(_T_11161, _T_11163) @[el2_ifu_bp_ctl.scala 447:81] node _T_11165 = or(_T_11164, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161] node _T_11166 = bits(_T_11165, 0, 0) @[el2_ifu_bp_ctl.scala 447:183] - node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] + node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8] wire bht_bank_sel : UInt<1>[16][16][2] @[el2_ifu_bp_ctl.scala 449:26] node _T_11167 = bits(bht_wr_en0, 0, 0) @[el2_ifu_bp_ctl.scala 455:41] node _T_11168 = bits(mp_hashed, 3, 0) @[el2_ifu_bp_ctl.scala 455:60] @@ -62506,7 +62506,7 @@ circuit el2_swerv_wrapper : module el2_ifu_aln_ctl : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}} + output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}} io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19] io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18] @@ -63615,62 +63615,62 @@ circuit el2_swerv_wrapper : node _T_726 = and(_T_724, _T_725) @[el2_ifu_aln_ctl.scala 378:100] node _T_727 = or(_T_722, _T_726) @[el2_ifu_aln_ctl.scala 378:75] io.i0_brp.valid <= _T_727 @[el2_ifu_aln_ctl.scala 378:19] - node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:44] - node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:34] - node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:70] - node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:60] - node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:49] - io.i0_brp.bits.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:22] + node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:39] + node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:29] + node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:65] + node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:55] + node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:44] + io.i0_brp.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:17] node _T_733 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 382:39] node _T_734 = and(first2B, _T_733) @[el2_ifu_aln_ctl.scala 382:29] node _T_735 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 382:65] node _T_736 = and(first4B, _T_735) @[el2_ifu_aln_ctl.scala 382:55] node i0_brp_pc4 = or(_T_734, _T_736) @[el2_ifu_aln_ctl.scala 382:44] - node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:50] - node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:38] - node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:55] - node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:71] - node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:85] - node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:28] - io.i0_brp.bits.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:22] - node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:51] - node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:39] - node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:79] - node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:67] - node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:56] + node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:45] + node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:33] + node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:50] + node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:66] + node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:80] + node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:23] + io.i0_brp.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:17] + node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:46] + node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:34] + node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:74] + node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:62] + node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:51] node _T_748 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 387:26] node _T_749 = and(first2B, _T_748) @[el2_ifu_aln_ctl.scala 387:14] node _T_750 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 387:54] node _T_751 = and(first4B, _T_750) @[el2_ifu_aln_ctl.scala 387:42] node _T_752 = or(_T_749, _T_751) @[el2_ifu_aln_ctl.scala 387:31] node _T_753 = cat(_T_747, _T_752) @[Cat.scala 29:58] - io.i0_brp.bits.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:23] + io.i0_brp.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:18] node i0_ends_f1 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 389:28] - node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:44] - node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:32] - io.i0_brp.bits.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:26] - node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:42] - node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:30] - io.i0_brp.bits.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:24] - node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:56] - node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:46] - node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:72] - node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:60] - io.i0_brp.bits.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:34] - node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:62] - node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:50] - node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:67] - node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:82] - node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:95] - node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:40] - io.i0_brp.bits.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:34] - node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:47] - node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:61] - node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:94] - node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:92] - node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:106] - node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:73] - io.i0_brp.bits.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:27] + node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:39] + node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:27] + io.i0_brp.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:21] + node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:37] + node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:25] + io.i0_brp.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:19] + node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:51] + node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:41] + node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:67] + node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:55] + io.i0_brp.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:29] + node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:57] + node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:45] + node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:62] + node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:77] + node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:90] + node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:35] + io.i0_brp.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:29] + node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:42] + node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:56] + node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:89] + node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:87] + node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:101] + node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:68] + io.i0_brp.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:22] node _T_774 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 400:50] node _T_775 = or(first2B, _T_774) @[el2_ifu_aln_ctl.scala 400:38] node _T_776 = bits(_T_775, 0, 0) @[el2_ifu_aln_ctl.scala 400:55] @@ -64009,7 +64009,7 @@ circuit el2_swerv_wrapper : module el2_ifu : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>} inst mem_ctl_ch of el2_ifu_mem_ctl @[el2_ifu.scala 146:26] mem_ctl_ch.clock <= clock @@ -64064,11 +64064,11 @@ circuit el2_swerv_wrapper : bp_ctl_ch.io.ic_hit_f <= mem_ctl_ch.io.ic_hit_f @[el2_ifu.scala 195:25] bp_ctl_ch.io.ifc_fetch_addr_f <= ifc_ctl_ch.io.ifc_fetch_addr_f @[el2_ifu.scala 196:33] bp_ctl_ch.io.ifc_fetch_req_f <= ifc_ctl_ch.io.ifc_fetch_req_f @[el2_ifu.scala 197:32] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.middle <= io.dec_tlu_br0_r_pkt.bits.middle @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.way <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_start_error <= io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_error <= io.dec_tlu_br0_r_pkt.bits.br_error @[el2_ifu.scala 198:34] - bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.hist <= io.dec_tlu_br0_r_pkt.bits.hist @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.middle <= io.dec_tlu_br0_r_pkt.middle @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.way <= io.dec_tlu_br0_r_pkt.way @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_start_error <= io.dec_tlu_br0_r_pkt.br_start_error @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_error <= io.dec_tlu_br0_r_pkt.br_error @[el2_ifu.scala 198:34] + bp_ctl_ch.io.dec_tlu_br0_r_pkt.hist <= io.dec_tlu_br0_r_pkt.hist @[el2_ifu.scala 198:34] bp_ctl_ch.io.dec_tlu_br0_r_pkt.valid <= io.dec_tlu_br0_r_pkt.valid @[el2_ifu.scala 198:34] bp_ctl_ch.io.exu_i0_br_fghr_r <= io.exu_i0_br_fghr_r @[el2_ifu.scala 199:33] bp_ctl_ch.io.exu_i0_br_index_r <= io.exu_i0_br_index_r @[el2_ifu.scala 200:34] @@ -64210,14 +64210,14 @@ circuit el2_swerv_wrapper : io.ifu_i0_pc <= aln_ctl_ch.io.ifu_i0_pc @[el2_ifu.scala 327:16] io.ifu_i0_pc4 <= aln_ctl_ch.io.ifu_i0_pc4 @[el2_ifu.scala 328:17] io.ifu_miss_state_idle <= mem_ctl_ch.io.ifu_miss_state_idle @[el2_ifu.scala 329:26] - io.i0_brp.bits.ret <= aln_ctl_ch.io.i0_brp.bits.ret @[el2_ifu.scala 331:13] - io.i0_brp.bits.way <= aln_ctl_ch.io.i0_brp.bits.way @[el2_ifu.scala 331:13] - io.i0_brp.bits.prett <= aln_ctl_ch.io.i0_brp.bits.prett @[el2_ifu.scala 331:13] - io.i0_brp.bits.bank <= aln_ctl_ch.io.i0_brp.bits.bank @[el2_ifu.scala 331:13] - io.i0_brp.bits.br_start_error <= aln_ctl_ch.io.i0_brp.bits.br_start_error @[el2_ifu.scala 331:13] - io.i0_brp.bits.br_error <= aln_ctl_ch.io.i0_brp.bits.br_error @[el2_ifu.scala 331:13] - io.i0_brp.bits.hist <= aln_ctl_ch.io.i0_brp.bits.hist @[el2_ifu.scala 331:13] - io.i0_brp.bits.toffset <= aln_ctl_ch.io.i0_brp.bits.toffset @[el2_ifu.scala 331:13] + io.i0_brp.ret <= aln_ctl_ch.io.i0_brp.ret @[el2_ifu.scala 331:13] + io.i0_brp.way <= aln_ctl_ch.io.i0_brp.way @[el2_ifu.scala 331:13] + io.i0_brp.prett <= aln_ctl_ch.io.i0_brp.prett @[el2_ifu.scala 331:13] + io.i0_brp.bank <= aln_ctl_ch.io.i0_brp.bank @[el2_ifu.scala 331:13] + io.i0_brp.br_start_error <= aln_ctl_ch.io.i0_brp.br_start_error @[el2_ifu.scala 331:13] + io.i0_brp.br_error <= aln_ctl_ch.io.i0_brp.br_error @[el2_ifu.scala 331:13] + io.i0_brp.hist <= aln_ctl_ch.io.i0_brp.hist @[el2_ifu.scala 331:13] + io.i0_brp.toffset <= aln_ctl_ch.io.i0_brp.toffset @[el2_ifu.scala 331:13] io.i0_brp.valid <= aln_ctl_ch.io.i0_brp.valid @[el2_ifu.scala 331:13] io.ifu_i0_bp_index <= aln_ctl_ch.io.ifu_i0_bp_index @[el2_ifu.scala 332:22] io.ifu_i0_bp_fghr <= aln_ctl_ch.io.ifu_i0_bp_fghr @[el2_ifu.scala 333:21] @@ -64231,52 +64231,52 @@ circuit el2_swerv_wrapper : module el2_dec_ib_ctl : input clock : Clock input reset : Reset - output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} + output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>} - io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 43:31] - io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 44:31] - io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 45:31] - io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 46:31] - io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 47:31] - io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 48:31] - io.dec_i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 49:31] - io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 50:31] - io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 51:31] - io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 52:31] - node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 66:60] - node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 66:41] - node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 67:38] - node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 67:36] - node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 68:36] - node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 70:55] - node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 70:37] - node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 71:55] - node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 71:37] - node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 72:55] - node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 72:37] - node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 73:55] - node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 73:37] - node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 75:40] - node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 76:40] - node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 79:20] + io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 8:31] + io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 9:31] + io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 10:31] + io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 11:31] + io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 12:31] + io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 13:31] + io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 14:31] + io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 15:31] + io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 16:31] + io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 17:31] + node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 31:60] + node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 31:41] + node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 32:38] + node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 32:36] + node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 33:36] + node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 35:55] + node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 35:37] + node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 36:55] + node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 36:37] + node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 37:55] + node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 37:37] + node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 38:55] + node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 38:37] + node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 40:40] + node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 41:40] + node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 44:20] node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58] node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58] - node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 80:21] - node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58] - node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58] - node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 81:20] - node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58] - node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 82:21] - node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58] + node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 45:21] + node _T_11 = cat(UInt<3>("h06"), dreg) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, UInt<6>("h033")) @[Cat.scala 29:58] + node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 46:20] + node _T_14 = cat(dcsr, UInt<14>("h02073")) @[Cat.scala 29:58] + node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 47:21] + node _T_16 = cat(dcsr, UInt<13>("h01073")) @[Cat.scala 29:58] node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72] node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72] @@ -64286,16 +64286,16 @@ circuit el2_swerv_wrapper : node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] wire ib0_debug_in : UInt<32> @[Mux.scala 27:72] ib0_debug_in <= _T_23 @[Mux.scala 27:72] - node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 86:47] - io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 86:28] - node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 89:51] - node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 89:43] - io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 89:24] - node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 91:41] - io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 91:22] - node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 92:41] - node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 92:28] - io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 92:22] + node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 51:47] + io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 51:28] + node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 54:51] + node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 54:43] + io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 54:24] + node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 56:41] + io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 56:22] + node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 57:41] + node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 57:28] + io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 57:22] extmodule gated_latch_661 : output Q : Clock @@ -64326,2039 +64326,2024 @@ circuit el2_swerv_wrapper : input reset : Reset output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} - node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 72:23] - node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 72:35] - node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 72:27] - node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 72:49] - node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:42] - node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:60] - node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 72:53] - node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 72:39] - node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 72:75] - node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:68] - node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:85] - node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 72:78] - node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 72:65] - io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 72:14] - node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 73:51] - node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 73:51] - node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 73:90] - node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 73:90] - node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 73:55] - node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 74:37] - node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 74:37] - node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 73:94] - node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 74:76] - node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 74:76] - node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 74:41] - node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_46 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_47 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_49 = and(_T_45, _T_46) @[el2_dec_dec_ctl.scala 75:38] - node _T_50 = and(_T_49, _T_48) @[el2_dec_dec_ctl.scala 75:38] - node _T_51 = or(_T_43, _T_50) @[el2_dec_dec_ctl.scala 74:80] - node _T_52 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_54 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_55 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_57 = and(_T_53, _T_54) @[el2_dec_dec_ctl.scala 75:76] - node _T_58 = and(_T_57, _T_56) @[el2_dec_dec_ctl.scala 75:76] - node _T_59 = or(_T_51, _T_58) @[el2_dec_dec_ctl.scala 75:42] - node _T_60 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_61 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_62 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_64 = and(_T_60, _T_61) @[el2_dec_dec_ctl.scala 76:37] - node _T_65 = and(_T_64, _T_63) @[el2_dec_dec_ctl.scala 76:37] - node _T_66 = or(_T_59, _T_65) @[el2_dec_dec_ctl.scala 75:80] - node _T_67 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_68 = eq(_T_67, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_69 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_70 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_71 = eq(_T_70, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_72 = and(_T_68, _T_69) @[el2_dec_dec_ctl.scala 76:75] - node _T_73 = and(_T_72, _T_71) @[el2_dec_dec_ctl.scala 76:75] - node _T_74 = or(_T_66, _T_73) @[el2_dec_dec_ctl.scala 76:41] - node _T_75 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_76 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_77 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_79 = and(_T_75, _T_76) @[el2_dec_dec_ctl.scala 77:37] - node _T_80 = and(_T_79, _T_78) @[el2_dec_dec_ctl.scala 77:37] - node _T_81 = or(_T_74, _T_80) @[el2_dec_dec_ctl.scala 76:79] - node _T_82 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_84 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_85 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_87 = and(_T_83, _T_84) @[el2_dec_dec_ctl.scala 77:75] - node _T_88 = and(_T_87, _T_86) @[el2_dec_dec_ctl.scala 77:75] - node _T_89 = or(_T_81, _T_88) @[el2_dec_dec_ctl.scala 77:41] - node _T_90 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_91 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_92 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_94 = and(_T_90, _T_91) @[el2_dec_dec_ctl.scala 78:37] - node _T_95 = and(_T_94, _T_93) @[el2_dec_dec_ctl.scala 78:37] - node _T_96 = or(_T_89, _T_95) @[el2_dec_dec_ctl.scala 77:79] - node _T_97 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_99 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_101 = and(_T_98, _T_100) @[el2_dec_dec_ctl.scala 78:71] - node _T_102 = or(_T_96, _T_101) @[el2_dec_dec_ctl.scala 78:41] - node _T_103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_104 = eq(_T_103, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_105 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_106 = eq(_T_105, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_107 = and(_T_104, _T_106) @[el2_dec_dec_ctl.scala 78:106] - node _T_108 = or(_T_102, _T_107) @[el2_dec_dec_ctl.scala 78:75] - io.out.rs1 <= _T_108 @[el2_dec_dec_ctl.scala 73:14] - node _T_109 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_112 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_114 = and(_T_109, _T_111) @[el2_dec_dec_ctl.scala 79:48] - node _T_115 = and(_T_114, _T_113) @[el2_dec_dec_ctl.scala 79:48] - node _T_116 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_118 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_119 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_121 = and(_T_117, _T_118) @[el2_dec_dec_ctl.scala 79:85] - node _T_122 = and(_T_121, _T_120) @[el2_dec_dec_ctl.scala 79:85] - node _T_123 = or(_T_115, _T_122) @[el2_dec_dec_ctl.scala 79:52] - io.out.rs2 <= _T_123 @[el2_dec_dec_ctl.scala 79:14] - node _T_124 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_126 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_127 = eq(_T_126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_128 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_129 = and(_T_125, _T_127) @[el2_dec_dec_ctl.scala 80:50] - node _T_130 = and(_T_129, _T_128) @[el2_dec_dec_ctl.scala 80:50] - node _T_131 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_132 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_134 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_135 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_137 = and(_T_131, _T_133) @[el2_dec_dec_ctl.scala 80:90] - node _T_138 = and(_T_137, _T_134) @[el2_dec_dec_ctl.scala 80:90] - node _T_139 = and(_T_138, _T_136) @[el2_dec_dec_ctl.scala 80:90] - node _T_140 = or(_T_130, _T_139) @[el2_dec_dec_ctl.scala 80:54] - node _T_141 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_142 = eq(_T_141, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_143 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_144 = eq(_T_143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_145 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_146 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_147 = and(_T_142, _T_144) @[el2_dec_dec_ctl.scala 81:40] - node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 81:40] - node _T_149 = and(_T_148, _T_146) @[el2_dec_dec_ctl.scala 81:40] - node _T_150 = or(_T_140, _T_149) @[el2_dec_dec_ctl.scala 80:94] - node _T_151 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_153 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_155 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_156 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_157 = eq(_T_156, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_158 = and(_T_152, _T_154) @[el2_dec_dec_ctl.scala 81:81] - node _T_159 = and(_T_158, _T_155) @[el2_dec_dec_ctl.scala 81:81] - node _T_160 = and(_T_159, _T_157) @[el2_dec_dec_ctl.scala 81:81] - node _T_161 = or(_T_150, _T_160) @[el2_dec_dec_ctl.scala 81:44] - io.out.imm12 <= _T_161 @[el2_dec_dec_ctl.scala 80:16] - node _T_162 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:24] - node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:17] - node _T_164 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:37] - node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:30] - node _T_166 = and(_T_163, _T_165) @[el2_dec_dec_ctl.scala 82:28] - node _T_167 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:51] - node _T_168 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:63] - node _T_169 = and(_T_167, _T_168) @[el2_dec_dec_ctl.scala 82:55] - node _T_170 = or(_T_166, _T_169) @[el2_dec_dec_ctl.scala 82:42] - node _T_171 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 82:76] - node _T_172 = or(_T_170, _T_171) @[el2_dec_dec_ctl.scala 82:68] - io.out.rd <= _T_172 @[el2_dec_dec_ctl.scala 82:13] - node _T_173 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_175 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_176 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_178 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_179 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_181 = and(_T_174, _T_175) @[el2_dec_dec_ctl.scala 83:58] - node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 83:58] - node _T_183 = and(_T_182, _T_178) @[el2_dec_dec_ctl.scala 83:58] - node _T_184 = and(_T_183, _T_180) @[el2_dec_dec_ctl.scala 83:58] - io.out.shimm5 <= _T_184 @[el2_dec_dec_ctl.scala 83:17] - node _T_185 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 84:26] - node _T_186 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 84:36] - node _T_187 = and(_T_185, _T_186) @[el2_dec_dec_ctl.scala 84:29] - node _T_188 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 84:50] - node _T_189 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 84:60] - node _T_190 = and(_T_188, _T_189) @[el2_dec_dec_ctl.scala 84:53] - node _T_191 = or(_T_187, _T_190) @[el2_dec_dec_ctl.scala 84:41] - io.out.imm20 <= _T_191 @[el2_dec_dec_ctl.scala 84:16] - node _T_192 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:24] - node _T_193 = eq(_T_192, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:17] - node _T_194 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:37] - node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:30] - node _T_196 = and(_T_193, _T_195) @[el2_dec_dec_ctl.scala 85:28] - node _T_197 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 85:49] - node _T_198 = and(_T_196, _T_197) @[el2_dec_dec_ctl.scala 85:41] - node _T_199 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:63] - node _T_200 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:75] - node _T_201 = and(_T_199, _T_200) @[el2_dec_dec_ctl.scala 85:67] - node _T_202 = or(_T_198, _T_201) @[el2_dec_dec_ctl.scala 85:54] - io.out.pc <= _T_202 @[el2_dec_dec_ctl.scala 85:13] - node _T_203 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_204 = eq(_T_203, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_205 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_207 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_209 = and(_T_204, _T_206) @[el2_dec_dec_ctl.scala 86:50] - node _T_210 = and(_T_209, _T_208) @[el2_dec_dec_ctl.scala 86:50] - io.out.load <= _T_210 @[el2_dec_dec_ctl.scala 86:15] - node _T_211 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_213 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_216 = and(_T_212, _T_213) @[el2_dec_dec_ctl.scala 87:50] - node _T_217 = and(_T_216, _T_215) @[el2_dec_dec_ctl.scala 87:50] - io.out.store <= _T_217 @[el2_dec_dec_ctl.scala 87:16] - node _T_218 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_219 = eq(_T_218, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_220 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_221 = eq(_T_220, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_222 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_223 = eq(_T_222, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_224 = and(_T_219, _T_221) @[el2_dec_dec_ctl.scala 88:49] - node _T_225 = and(_T_224, _T_223) @[el2_dec_dec_ctl.scala 88:49] - io.out.lsu <= _T_225 @[el2_dec_dec_ctl.scala 88:14] - node _T_226 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_228 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_230 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_232 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_234 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_235 = and(_T_227, _T_229) @[el2_dec_dec_ctl.scala 89:57] - node _T_236 = and(_T_235, _T_231) @[el2_dec_dec_ctl.scala 89:57] - node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 89:57] - node _T_238 = and(_T_237, _T_234) @[el2_dec_dec_ctl.scala 89:57] - node _T_239 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_241 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_243 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_244 = and(_T_240, _T_242) @[el2_dec_dec_ctl.scala 89:94] - node _T_245 = and(_T_244, _T_243) @[el2_dec_dec_ctl.scala 89:94] - node _T_246 = or(_T_238, _T_245) @[el2_dec_dec_ctl.scala 89:61] - node _T_247 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_249 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_250 = eq(_T_249, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_251 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_253 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_254 = eq(_T_253, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_255 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_257 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_259 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_260 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_261 = eq(_T_260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_262 = and(_T_248, _T_250) @[el2_dec_dec_ctl.scala 90:56] - node _T_263 = and(_T_262, _T_252) @[el2_dec_dec_ctl.scala 90:56] - node _T_264 = and(_T_263, _T_254) @[el2_dec_dec_ctl.scala 90:56] - node _T_265 = and(_T_264, _T_256) @[el2_dec_dec_ctl.scala 90:56] - node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 90:56] - node _T_267 = and(_T_266, _T_259) @[el2_dec_dec_ctl.scala 90:56] - node _T_268 = and(_T_267, _T_261) @[el2_dec_dec_ctl.scala 90:56] - node _T_269 = or(_T_246, _T_268) @[el2_dec_dec_ctl.scala 89:98] - io.out.add <= _T_269 @[el2_dec_dec_ctl.scala 89:14] - node _T_270 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] - node _T_271 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_272 = eq(_T_271, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_273 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_274 = eq(_T_273, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_275 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_276 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_279 = and(_T_270, _T_272) @[el2_dec_dec_ctl.scala 91:57] - node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 91:57] - node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 91:57] - node _T_282 = and(_T_281, _T_276) @[el2_dec_dec_ctl.scala 91:57] - node _T_283 = and(_T_282, _T_278) @[el2_dec_dec_ctl.scala 91:57] - node _T_284 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_286 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_288 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_289 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_290 = eq(_T_289, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_291 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_292 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_294 = and(_T_285, _T_287) @[el2_dec_dec_ctl.scala 91:105] - node _T_295 = and(_T_294, _T_288) @[el2_dec_dec_ctl.scala 91:105] - node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 91:105] - node _T_297 = and(_T_296, _T_291) @[el2_dec_dec_ctl.scala 91:105] - node _T_298 = and(_T_297, _T_293) @[el2_dec_dec_ctl.scala 91:105] - node _T_299 = or(_T_283, _T_298) @[el2_dec_dec_ctl.scala 91:61] - node _T_300 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_302 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_303 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_304 = eq(_T_303, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_305 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_306 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_308 = and(_T_301, _T_302) @[el2_dec_dec_ctl.scala 92:43] - node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 92:43] - node _T_310 = and(_T_309, _T_305) @[el2_dec_dec_ctl.scala 92:43] - node _T_311 = and(_T_310, _T_307) @[el2_dec_dec_ctl.scala 92:43] - node _T_312 = or(_T_299, _T_311) @[el2_dec_dec_ctl.scala 91:109] - node _T_313 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_314 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_316 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_318 = and(_T_313, _T_315) @[el2_dec_dec_ctl.scala 92:80] - node _T_319 = and(_T_318, _T_317) @[el2_dec_dec_ctl.scala 92:80] - node _T_320 = or(_T_312, _T_319) @[el2_dec_dec_ctl.scala 92:47] - io.out.sub <= _T_320 @[el2_dec_dec_ctl.scala 91:14] - node _T_321 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_322 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_323 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_324 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_326 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_328 = and(_T_321, _T_322) @[el2_dec_dec_ctl.scala 93:56] - node _T_329 = and(_T_328, _T_323) @[el2_dec_dec_ctl.scala 93:56] - node _T_330 = and(_T_329, _T_325) @[el2_dec_dec_ctl.scala 93:56] - node _T_331 = and(_T_330, _T_327) @[el2_dec_dec_ctl.scala 93:56] - node _T_332 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_334 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_335 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_336 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_337 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_339 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_341 = and(_T_333, _T_334) @[el2_dec_dec_ctl.scala 93:104] - node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 93:104] - node _T_343 = and(_T_342, _T_336) @[el2_dec_dec_ctl.scala 93:104] - node _T_344 = and(_T_343, _T_338) @[el2_dec_dec_ctl.scala 93:104] - node _T_345 = and(_T_344, _T_340) @[el2_dec_dec_ctl.scala 93:104] - node _T_346 = or(_T_331, _T_345) @[el2_dec_dec_ctl.scala 93:60] - io.out.land <= _T_346 @[el2_dec_dec_ctl.scala 93:15] - node _T_347 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_348 = eq(_T_347, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_349 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_350 = and(_T_348, _T_349) @[el2_dec_dec_ctl.scala 94:45] - node _T_351 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_353 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_354 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_355 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_356 = eq(_T_355, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_357 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_358 = eq(_T_357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_360 = eq(_T_359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_361 = and(_T_352, _T_353) @[el2_dec_dec_ctl.scala 94:94] - node _T_362 = and(_T_361, _T_354) @[el2_dec_dec_ctl.scala 94:94] - node _T_363 = and(_T_362, _T_356) @[el2_dec_dec_ctl.scala 94:94] - node _T_364 = and(_T_363, _T_358) @[el2_dec_dec_ctl.scala 94:94] - node _T_365 = and(_T_364, _T_360) @[el2_dec_dec_ctl.scala 94:94] - node _T_366 = or(_T_350, _T_365) @[el2_dec_dec_ctl.scala 94:49] - node _T_367 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_368 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_369 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_370 = and(_T_367, _T_368) @[el2_dec_dec_ctl.scala 95:34] - node _T_371 = and(_T_370, _T_369) @[el2_dec_dec_ctl.scala 95:34] - node _T_372 = or(_T_366, _T_371) @[el2_dec_dec_ctl.scala 94:98] - node _T_373 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_374 = eq(_T_373, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_375 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_377 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_378 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_379 = and(_T_374, _T_376) @[el2_dec_dec_ctl.scala 95:75] - node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 95:75] - node _T_381 = and(_T_380, _T_378) @[el2_dec_dec_ctl.scala 95:75] - node _T_382 = or(_T_372, _T_381) @[el2_dec_dec_ctl.scala 95:38] - node _T_383 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_384 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_385 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_387 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_389 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_391 = and(_T_383, _T_384) @[el2_dec_dec_ctl.scala 96:44] - node _T_392 = and(_T_391, _T_386) @[el2_dec_dec_ctl.scala 96:44] - node _T_393 = and(_T_392, _T_388) @[el2_dec_dec_ctl.scala 96:44] - node _T_394 = and(_T_393, _T_390) @[el2_dec_dec_ctl.scala 96:44] - node _T_395 = or(_T_382, _T_394) @[el2_dec_dec_ctl.scala 95:79] - io.out.lor <= _T_395 @[el2_dec_dec_ctl.scala 94:14] - node _T_396 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_398 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_399 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_401 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_403 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_404 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_405 = eq(_T_404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_406 = and(_T_397, _T_398) @[el2_dec_dec_ctl.scala 97:61] - node _T_407 = and(_T_406, _T_400) @[el2_dec_dec_ctl.scala 97:61] - node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 97:61] - node _T_409 = and(_T_408, _T_403) @[el2_dec_dec_ctl.scala 97:61] - node _T_410 = and(_T_409, _T_405) @[el2_dec_dec_ctl.scala 97:61] - node _T_411 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_412 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_414 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_415 = eq(_T_414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_416 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_418 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_419 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_421 = and(_T_411, _T_413) @[el2_dec_dec_ctl.scala 97:109] - node _T_422 = and(_T_421, _T_415) @[el2_dec_dec_ctl.scala 97:109] - node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 97:109] - node _T_424 = and(_T_423, _T_418) @[el2_dec_dec_ctl.scala 97:109] - node _T_425 = and(_T_424, _T_420) @[el2_dec_dec_ctl.scala 97:109] - node _T_426 = or(_T_410, _T_425) @[el2_dec_dec_ctl.scala 97:65] - io.out.lxor <= _T_426 @[el2_dec_dec_ctl.scala 97:15] - node _T_427 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_428 = eq(_T_427, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_429 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_431 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_433 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_434 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_436 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_437 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_438 = eq(_T_437, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_439 = and(_T_428, _T_430) @[el2_dec_dec_ctl.scala 98:63] - node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 98:63] - node _T_441 = and(_T_440, _T_433) @[el2_dec_dec_ctl.scala 98:63] - node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 98:63] - node _T_443 = and(_T_442, _T_436) @[el2_dec_dec_ctl.scala 98:63] - node _T_444 = and(_T_443, _T_438) @[el2_dec_dec_ctl.scala 98:63] - io.out.sll <= _T_444 @[el2_dec_dec_ctl.scala 98:14] - node _T_445 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] - node _T_446 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_447 = eq(_T_446, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_448 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_449 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_450 = eq(_T_449, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_451 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_452 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_454 = and(_T_445, _T_447) @[el2_dec_dec_ctl.scala 99:58] - node _T_455 = and(_T_454, _T_448) @[el2_dec_dec_ctl.scala 99:58] - node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 99:58] - node _T_457 = and(_T_456, _T_451) @[el2_dec_dec_ctl.scala 99:58] - node _T_458 = and(_T_457, _T_453) @[el2_dec_dec_ctl.scala 99:58] - io.out.sra <= _T_458 @[el2_dec_dec_ctl.scala 99:14] - node _T_459 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_461 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_463 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_464 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_466 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_467 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_469 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_470 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_471 = eq(_T_470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_472 = and(_T_460, _T_462) @[el2_dec_dec_ctl.scala 100:66] - node _T_473 = and(_T_472, _T_463) @[el2_dec_dec_ctl.scala 100:66] - node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 100:66] - node _T_475 = and(_T_474, _T_466) @[el2_dec_dec_ctl.scala 100:66] - node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 100:66] - node _T_477 = and(_T_476, _T_469) @[el2_dec_dec_ctl.scala 100:66] - node _T_478 = and(_T_477, _T_471) @[el2_dec_dec_ctl.scala 100:66] - io.out.srl <= _T_478 @[el2_dec_dec_ctl.scala 100:14] - node _T_479 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_480 = eq(_T_479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_481 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_482 = eq(_T_481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_483 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_484 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_485 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_487 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_488 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_490 = and(_T_480, _T_482) @[el2_dec_dec_ctl.scala 101:62] - node _T_491 = and(_T_490, _T_483) @[el2_dec_dec_ctl.scala 101:62] - node _T_492 = and(_T_491, _T_484) @[el2_dec_dec_ctl.scala 101:62] - node _T_493 = and(_T_492, _T_486) @[el2_dec_dec_ctl.scala 101:62] - node _T_494 = and(_T_493, _T_487) @[el2_dec_dec_ctl.scala 101:62] - node _T_495 = and(_T_494, _T_489) @[el2_dec_dec_ctl.scala 101:62] - node _T_496 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_498 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_499 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_501 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_502 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_503 = eq(_T_502, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_504 = and(_T_497, _T_498) @[el2_dec_dec_ctl.scala 101:106] - node _T_505 = and(_T_504, _T_500) @[el2_dec_dec_ctl.scala 101:106] - node _T_506 = and(_T_505, _T_501) @[el2_dec_dec_ctl.scala 101:106] - node _T_507 = and(_T_506, _T_503) @[el2_dec_dec_ctl.scala 101:106] - node _T_508 = or(_T_495, _T_507) @[el2_dec_dec_ctl.scala 101:66] - io.out.slt <= _T_508 @[el2_dec_dec_ctl.scala 101:14] - node _T_509 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_510 = eq(_T_509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_511 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_512 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_513 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_515 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_516 = eq(_T_515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_517 = and(_T_510, _T_511) @[el2_dec_dec_ctl.scala 102:59] - node _T_518 = and(_T_517, _T_512) @[el2_dec_dec_ctl.scala 102:59] - node _T_519 = and(_T_518, _T_514) @[el2_dec_dec_ctl.scala 102:59] - node _T_520 = and(_T_519, _T_516) @[el2_dec_dec_ctl.scala 102:59] - node _T_521 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_522 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_523 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_524 = eq(_T_523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_525 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_527 = and(_T_521, _T_522) @[el2_dec_dec_ctl.scala 102:99] - node _T_528 = and(_T_527, _T_524) @[el2_dec_dec_ctl.scala 102:99] - node _T_529 = and(_T_528, _T_526) @[el2_dec_dec_ctl.scala 102:99] - node _T_530 = or(_T_520, _T_529) @[el2_dec_dec_ctl.scala 102:63] - node _T_531 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_532 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_534 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_535 = eq(_T_534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_536 = and(_T_531, _T_533) @[el2_dec_dec_ctl.scala 103:37] - node _T_537 = and(_T_536, _T_535) @[el2_dec_dec_ctl.scala 103:37] - node _T_538 = or(_T_530, _T_537) @[el2_dec_dec_ctl.scala 102:103] - node _T_539 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_540 = eq(_T_539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_541 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_543 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_544 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_545 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_547 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_549 = and(_T_540, _T_542) @[el2_dec_dec_ctl.scala 103:86] - node _T_550 = and(_T_549, _T_543) @[el2_dec_dec_ctl.scala 103:86] - node _T_551 = and(_T_550, _T_544) @[el2_dec_dec_ctl.scala 103:86] - node _T_552 = and(_T_551, _T_546) @[el2_dec_dec_ctl.scala 103:86] - node _T_553 = and(_T_552, _T_548) @[el2_dec_dec_ctl.scala 103:86] - node _T_554 = or(_T_538, _T_553) @[el2_dec_dec_ctl.scala 103:41] - node _T_555 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_556 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_557 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_558 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_560 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_561 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_563 = and(_T_555, _T_556) @[el2_dec_dec_ctl.scala 104:45] - node _T_564 = and(_T_563, _T_557) @[el2_dec_dec_ctl.scala 104:45] - node _T_565 = and(_T_564, _T_559) @[el2_dec_dec_ctl.scala 104:45] - node _T_566 = and(_T_565, _T_560) @[el2_dec_dec_ctl.scala 104:45] - node _T_567 = and(_T_566, _T_562) @[el2_dec_dec_ctl.scala 104:45] - node _T_568 = or(_T_554, _T_567) @[el2_dec_dec_ctl.scala 103:90] - io.out.unsign <= _T_568 @[el2_dec_dec_ctl.scala 102:17] - node _T_569 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_570 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_571 = eq(_T_570, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_572 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_573 = eq(_T_572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_574 = and(_T_569, _T_571) @[el2_dec_dec_ctl.scala 105:51] - node _T_575 = and(_T_574, _T_573) @[el2_dec_dec_ctl.scala 105:51] - io.out.condbr <= _T_575 @[el2_dec_dec_ctl.scala 105:17] - node _T_576 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_577 = eq(_T_576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_578 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_580 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_581 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_583 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_584 = eq(_T_583, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_585 = and(_T_577, _T_579) @[el2_dec_dec_ctl.scala 106:56] - node _T_586 = and(_T_585, _T_580) @[el2_dec_dec_ctl.scala 106:56] - node _T_587 = and(_T_586, _T_582) @[el2_dec_dec_ctl.scala 106:56] - node _T_588 = and(_T_587, _T_584) @[el2_dec_dec_ctl.scala 106:56] - io.out.beq <= _T_588 @[el2_dec_dec_ctl.scala 106:14] - node _T_589 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_590 = eq(_T_589, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_591 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_592 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_593 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_594 = eq(_T_593, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_595 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_597 = and(_T_590, _T_591) @[el2_dec_dec_ctl.scala 107:55] - node _T_598 = and(_T_597, _T_592) @[el2_dec_dec_ctl.scala 107:55] - node _T_599 = and(_T_598, _T_594) @[el2_dec_dec_ctl.scala 107:55] - node _T_600 = and(_T_599, _T_596) @[el2_dec_dec_ctl.scala 107:55] - io.out.bne <= _T_600 @[el2_dec_dec_ctl.scala 107:14] - node _T_601 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_602 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_603 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_604 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_606 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_608 = and(_T_601, _T_602) @[el2_dec_dec_ctl.scala 108:54] - node _T_609 = and(_T_608, _T_603) @[el2_dec_dec_ctl.scala 108:54] - node _T_610 = and(_T_609, _T_605) @[el2_dec_dec_ctl.scala 108:54] - node _T_611 = and(_T_610, _T_607) @[el2_dec_dec_ctl.scala 108:54] - io.out.bge <= _T_611 @[el2_dec_dec_ctl.scala 108:14] - node _T_612 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_613 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_615 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_616 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_617 = eq(_T_616, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_618 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_620 = and(_T_612, _T_614) @[el2_dec_dec_ctl.scala 109:55] - node _T_621 = and(_T_620, _T_615) @[el2_dec_dec_ctl.scala 109:55] - node _T_622 = and(_T_621, _T_617) @[el2_dec_dec_ctl.scala 109:55] - node _T_623 = and(_T_622, _T_619) @[el2_dec_dec_ctl.scala 109:55] - io.out.blt <= _T_623 @[el2_dec_dec_ctl.scala 109:14] - node _T_624 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_625 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_626 = and(_T_624, _T_625) @[el2_dec_dec_ctl.scala 110:44] - io.out.jal <= _T_626 @[el2_dec_dec_ctl.scala 110:14] - node _T_627 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_628 = eq(_T_627, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_629 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_631 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_632 = eq(_T_631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_633 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_635 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_636 = eq(_T_635, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_637 = and(_T_628, _T_630) @[el2_dec_dec_ctl.scala 111:56] - node _T_638 = and(_T_637, _T_632) @[el2_dec_dec_ctl.scala 111:56] - node _T_639 = and(_T_638, _T_634) @[el2_dec_dec_ctl.scala 111:56] - node _T_640 = and(_T_639, _T_636) @[el2_dec_dec_ctl.scala 111:56] - io.out.by <= _T_640 @[el2_dec_dec_ctl.scala 111:13] - node _T_641 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_642 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_644 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_646 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_647 = eq(_T_646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_648 = and(_T_641, _T_643) @[el2_dec_dec_ctl.scala 112:53] - node _T_649 = and(_T_648, _T_645) @[el2_dec_dec_ctl.scala 112:53] - node _T_650 = and(_T_649, _T_647) @[el2_dec_dec_ctl.scala 112:53] - io.out.half <= _T_650 @[el2_dec_dec_ctl.scala 112:15] - node _T_651 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_652 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_654 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_656 = and(_T_651, _T_653) @[el2_dec_dec_ctl.scala 113:50] - node _T_657 = and(_T_656, _T_655) @[el2_dec_dec_ctl.scala 113:50] - io.out.word <= _T_657 @[el2_dec_dec_ctl.scala 113:15] - node _T_658 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_659 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_660 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_661 = and(_T_658, _T_659) @[el2_dec_dec_ctl.scala 114:52] - node _T_662 = and(_T_661, _T_660) @[el2_dec_dec_ctl.scala 114:52] - node _T_663 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_664 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_665 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_666 = and(_T_663, _T_664) @[el2_dec_dec_ctl.scala 114:87] - node _T_667 = and(_T_666, _T_665) @[el2_dec_dec_ctl.scala 114:87] - node _T_668 = or(_T_662, _T_667) @[el2_dec_dec_ctl.scala 114:56] - node _T_669 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_670 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_672 = and(_T_669, _T_670) @[el2_dec_dec_ctl.scala 115:34] - node _T_673 = and(_T_672, _T_671) @[el2_dec_dec_ctl.scala 115:34] - node _T_674 = or(_T_668, _T_673) @[el2_dec_dec_ctl.scala 114:91] - node _T_675 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_676 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_677 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_678 = and(_T_675, _T_676) @[el2_dec_dec_ctl.scala 115:69] - node _T_679 = and(_T_678, _T_677) @[el2_dec_dec_ctl.scala 115:69] - node _T_680 = or(_T_674, _T_679) @[el2_dec_dec_ctl.scala 115:38] - node _T_681 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_682 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_683 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_684 = and(_T_681, _T_682) @[el2_dec_dec_ctl.scala 115:105] - node _T_685 = and(_T_684, _T_683) @[el2_dec_dec_ctl.scala 115:105] - node _T_686 = or(_T_680, _T_685) @[el2_dec_dec_ctl.scala 115:73] - node _T_687 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_688 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_690 = and(_T_687, _T_688) @[el2_dec_dec_ctl.scala 116:35] - node _T_691 = and(_T_690, _T_689) @[el2_dec_dec_ctl.scala 116:35] - node _T_692 = or(_T_686, _T_691) @[el2_dec_dec_ctl.scala 115:109] - io.out.csr_read <= _T_692 @[el2_dec_dec_ctl.scala 114:19] - node _T_693 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_694 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_695 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_696 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_697 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_698 = and(_T_693, _T_694) @[el2_dec_dec_ctl.scala 117:57] - node _T_699 = and(_T_698, _T_695) @[el2_dec_dec_ctl.scala 117:57] - node _T_700 = and(_T_699, _T_696) @[el2_dec_dec_ctl.scala 117:57] - node _T_701 = and(_T_700, _T_697) @[el2_dec_dec_ctl.scala 117:57] - node _T_702 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_703 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_704 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_705 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_706 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_707 = and(_T_702, _T_703) @[el2_dec_dec_ctl.scala 117:99] - node _T_708 = and(_T_707, _T_704) @[el2_dec_dec_ctl.scala 117:99] - node _T_709 = and(_T_708, _T_705) @[el2_dec_dec_ctl.scala 117:99] - node _T_710 = and(_T_709, _T_706) @[el2_dec_dec_ctl.scala 117:99] - node _T_711 = or(_T_701, _T_710) @[el2_dec_dec_ctl.scala 117:61] - node _T_712 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_713 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_714 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_715 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_716 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_717 = and(_T_712, _T_713) @[el2_dec_dec_ctl.scala 118:41] - node _T_718 = and(_T_717, _T_714) @[el2_dec_dec_ctl.scala 118:41] - node _T_719 = and(_T_718, _T_715) @[el2_dec_dec_ctl.scala 118:41] - node _T_720 = and(_T_719, _T_716) @[el2_dec_dec_ctl.scala 118:41] - node _T_721 = or(_T_711, _T_720) @[el2_dec_dec_ctl.scala 117:103] - node _T_722 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_723 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_724 = eq(_T_723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_725 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_726 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_727 = and(_T_722, _T_724) @[el2_dec_dec_ctl.scala 118:81] - node _T_728 = and(_T_727, _T_725) @[el2_dec_dec_ctl.scala 118:81] - node _T_729 = and(_T_728, _T_726) @[el2_dec_dec_ctl.scala 118:81] - node _T_730 = or(_T_721, _T_729) @[el2_dec_dec_ctl.scala 118:45] - node _T_731 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_732 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_733 = eq(_T_732, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_734 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_735 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_736 = and(_T_731, _T_733) @[el2_dec_dec_ctl.scala 119:39] - node _T_737 = and(_T_736, _T_734) @[el2_dec_dec_ctl.scala 119:39] - node _T_738 = and(_T_737, _T_735) @[el2_dec_dec_ctl.scala 119:39] - node _T_739 = or(_T_730, _T_738) @[el2_dec_dec_ctl.scala 118:85] - io.out.csr_clr <= _T_739 @[el2_dec_dec_ctl.scala 117:18] - node _T_740 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_741 = eq(_T_740, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_742 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_743 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_744 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_745 = and(_T_741, _T_742) @[el2_dec_dec_ctl.scala 120:57] - node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 120:57] - node _T_747 = and(_T_746, _T_744) @[el2_dec_dec_ctl.scala 120:57] - io.out.csr_write <= _T_747 @[el2_dec_dec_ctl.scala 120:20] - node _T_748 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_749 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_750 = eq(_T_749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_752 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_753 = and(_T_748, _T_750) @[el2_dec_dec_ctl.scala 121:55] - node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 121:55] - node _T_755 = and(_T_754, _T_752) @[el2_dec_dec_ctl.scala 121:55] - node _T_756 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_757 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_758 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_759 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_760 = and(_T_756, _T_757) @[el2_dec_dec_ctl.scala 121:94] - node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 121:94] - node _T_762 = and(_T_761, _T_759) @[el2_dec_dec_ctl.scala 121:94] - node _T_763 = or(_T_755, _T_762) @[el2_dec_dec_ctl.scala 121:59] - node _T_764 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_765 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_766 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_767 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_768 = and(_T_764, _T_765) @[el2_dec_dec_ctl.scala 122:38] - node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 122:38] - node _T_770 = and(_T_769, _T_767) @[el2_dec_dec_ctl.scala 122:38] - node _T_771 = or(_T_763, _T_770) @[el2_dec_dec_ctl.scala 121:98] - node _T_772 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_773 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_774 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_775 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_776 = and(_T_772, _T_773) @[el2_dec_dec_ctl.scala 122:77] - node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 122:77] - node _T_778 = and(_T_777, _T_775) @[el2_dec_dec_ctl.scala 122:77] - node _T_779 = or(_T_771, _T_778) @[el2_dec_dec_ctl.scala 122:42] - node _T_780 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_781 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_782 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_783 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_784 = and(_T_780, _T_781) @[el2_dec_dec_ctl.scala 123:38] - node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 123:38] - node _T_786 = and(_T_785, _T_783) @[el2_dec_dec_ctl.scala 123:38] - node _T_787 = or(_T_779, _T_786) @[el2_dec_dec_ctl.scala 122:81] - node _T_788 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_789 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_790 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_791 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_792 = and(_T_788, _T_789) @[el2_dec_dec_ctl.scala 123:77] - node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 123:77] - node _T_794 = and(_T_793, _T_791) @[el2_dec_dec_ctl.scala 123:77] - node _T_795 = or(_T_787, _T_794) @[el2_dec_dec_ctl.scala 123:42] - io.out.csr_imm <= _T_795 @[el2_dec_dec_ctl.scala 121:18] - node _T_796 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_797 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_799 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_800 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_801 = and(_T_796, _T_798) @[el2_dec_dec_ctl.scala 124:55] - node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 124:55] - node _T_803 = and(_T_802, _T_800) @[el2_dec_dec_ctl.scala 124:55] - node _T_804 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_805 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_806 = eq(_T_805, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_807 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_808 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_809 = and(_T_804, _T_806) @[el2_dec_dec_ctl.scala 124:95] - node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 124:95] - node _T_811 = and(_T_810, _T_808) @[el2_dec_dec_ctl.scala 124:95] - node _T_812 = or(_T_803, _T_811) @[el2_dec_dec_ctl.scala 124:59] - node _T_813 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_815 = eq(_T_814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_816 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_817 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_818 = and(_T_813, _T_815) @[el2_dec_dec_ctl.scala 125:39] - node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 125:39] - node _T_820 = and(_T_819, _T_817) @[el2_dec_dec_ctl.scala 125:39] - node _T_821 = or(_T_812, _T_820) @[el2_dec_dec_ctl.scala 124:99] - node _T_822 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_823 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_824 = eq(_T_823, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_825 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_826 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_827 = and(_T_822, _T_824) @[el2_dec_dec_ctl.scala 125:79] - node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 125:79] - node _T_829 = and(_T_828, _T_826) @[el2_dec_dec_ctl.scala 125:79] - node _T_830 = or(_T_821, _T_829) @[el2_dec_dec_ctl.scala 125:43] - node _T_831 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_832 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_834 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_835 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_836 = and(_T_831, _T_833) @[el2_dec_dec_ctl.scala 126:39] - node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 126:39] - node _T_838 = and(_T_837, _T_835) @[el2_dec_dec_ctl.scala 126:39] - node _T_839 = or(_T_830, _T_838) @[el2_dec_dec_ctl.scala 125:83] - io.out.csr_set <= _T_839 @[el2_dec_dec_ctl.scala 124:18] - node _T_840 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_841 = eq(_T_840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_842 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] - node _T_843 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_845 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_846 = eq(_T_845, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_847 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_848 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_849 = and(_T_841, _T_842) @[el2_dec_dec_ctl.scala 127:62] - node _T_850 = and(_T_849, _T_844) @[el2_dec_dec_ctl.scala 127:62] - node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 127:62] - node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 127:62] - node _T_853 = and(_T_852, _T_848) @[el2_dec_dec_ctl.scala 127:62] - io.out.ebreak <= _T_853 @[el2_dec_dec_ctl.scala 127:17] - node _T_854 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_856 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] - node _T_857 = eq(_T_856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_858 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_859 = eq(_T_858, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_860 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_861 = eq(_T_860, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_862 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_864 = and(_T_855, _T_857) @[el2_dec_dec_ctl.scala 128:62] - node _T_865 = and(_T_864, _T_859) @[el2_dec_dec_ctl.scala 128:62] - node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 128:62] - node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 128:62] - node _T_868 = and(_T_867, _T_863) @[el2_dec_dec_ctl.scala 128:62] - io.out.ecall <= _T_868 @[el2_dec_dec_ctl.scala 128:16] - node _T_869 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] - node _T_870 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_872 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_873 = eq(_T_872, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_874 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_875 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_876 = and(_T_869, _T_871) @[el2_dec_dec_ctl.scala 129:56] - node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 129:56] - node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 129:56] - node _T_879 = and(_T_878, _T_875) @[el2_dec_dec_ctl.scala 129:56] - io.out.mret <= _T_879 @[el2_dec_dec_ctl.scala 129:15] - node _T_880 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_881 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_883 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_885 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_886 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_887 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_888 = eq(_T_887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_889 = and(_T_880, _T_882) @[el2_dec_dec_ctl.scala 130:57] - node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 130:57] - node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 130:57] - node _T_892 = and(_T_891, _T_886) @[el2_dec_dec_ctl.scala 130:57] - node _T_893 = and(_T_892, _T_888) @[el2_dec_dec_ctl.scala 130:57] - io.out.mul <= _T_893 @[el2_dec_dec_ctl.scala 130:14] - node _T_894 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_895 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_896 = eq(_T_895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_897 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_898 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_902 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_903 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_904 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_905 = eq(_T_904, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_906 = and(_T_894, _T_896) @[el2_dec_dec_ctl.scala 131:69] - node _T_907 = and(_T_906, _T_897) @[el2_dec_dec_ctl.scala 131:69] - node _T_908 = and(_T_907, _T_899) @[el2_dec_dec_ctl.scala 131:69] - node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 131:69] - node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 131:69] - node _T_911 = and(_T_910, _T_903) @[el2_dec_dec_ctl.scala 131:69] - node _T_912 = and(_T_911, _T_905) @[el2_dec_dec_ctl.scala 131:69] - node _T_913 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_914 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_915 = eq(_T_914, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_916 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_917 = eq(_T_916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_918 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_919 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_921 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_922 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_923 = eq(_T_922, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_924 = and(_T_913, _T_915) @[el2_dec_dec_ctl.scala 132:50] - node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 132:50] - node _T_926 = and(_T_925, _T_918) @[el2_dec_dec_ctl.scala 132:50] - node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 132:50] - node _T_928 = and(_T_927, _T_921) @[el2_dec_dec_ctl.scala 132:50] - node _T_929 = and(_T_928, _T_923) @[el2_dec_dec_ctl.scala 132:50] - node _T_930 = or(_T_912, _T_929) @[el2_dec_dec_ctl.scala 131:73] - io.out.rs1_sign <= _T_930 @[el2_dec_dec_ctl.scala 131:19] - node _T_931 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_934 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_935 = eq(_T_934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_936 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_937 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_938 = eq(_T_937, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_939 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_940 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_942 = and(_T_931, _T_933) @[el2_dec_dec_ctl.scala 133:67] - node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 133:67] - node _T_944 = and(_T_943, _T_936) @[el2_dec_dec_ctl.scala 133:67] - node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 133:67] - node _T_946 = and(_T_945, _T_939) @[el2_dec_dec_ctl.scala 133:67] - node _T_947 = and(_T_946, _T_941) @[el2_dec_dec_ctl.scala 133:67] - io.out.rs2_sign <= _T_947 @[el2_dec_dec_ctl.scala 133:19] - node _T_948 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_949 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_950 = eq(_T_949, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_951 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_952 = eq(_T_951, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_953 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_955 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_957 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_959 = and(_T_948, _T_950) @[el2_dec_dec_ctl.scala 134:62] - node _T_960 = and(_T_959, _T_952) @[el2_dec_dec_ctl.scala 134:62] - node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 134:62] - node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 134:62] - node _T_963 = and(_T_962, _T_956) @[el2_dec_dec_ctl.scala 134:62] - node _T_964 = and(_T_963, _T_958) @[el2_dec_dec_ctl.scala 134:62] - io.out.low <= _T_964 @[el2_dec_dec_ctl.scala 134:14] - node _T_965 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_966 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_969 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_970 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_971 = eq(_T_970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_972 = and(_T_965, _T_966) @[el2_dec_dec_ctl.scala 135:54] - node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 135:54] - node _T_974 = and(_T_973, _T_969) @[el2_dec_dec_ctl.scala 135:54] - node _T_975 = and(_T_974, _T_971) @[el2_dec_dec_ctl.scala 135:54] - io.out.div <= _T_975 @[el2_dec_dec_ctl.scala 135:14] - node _T_976 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] - node _T_977 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_978 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_979 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_981 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_982 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_983 = eq(_T_982, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_984 = and(_T_976, _T_977) @[el2_dec_dec_ctl.scala 136:57] - node _T_985 = and(_T_984, _T_978) @[el2_dec_dec_ctl.scala 136:57] - node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 136:57] - node _T_987 = and(_T_986, _T_981) @[el2_dec_dec_ctl.scala 136:57] - node _T_988 = and(_T_987, _T_983) @[el2_dec_dec_ctl.scala 136:57] - io.out.rem <= _T_988 @[el2_dec_dec_ctl.scala 136:14] - node _T_989 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_990 = eq(_T_989, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_991 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_992 = and(_T_990, _T_991) @[el2_dec_dec_ctl.scala 137:47] - io.out.fence <= _T_992 @[el2_dec_dec_ctl.scala 137:16] - node _T_993 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_994 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_995 = eq(_T_994, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_996 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_997 = and(_T_993, _T_995) @[el2_dec_dec_ctl.scala 138:52] - node _T_998 = and(_T_997, _T_996) @[el2_dec_dec_ctl.scala 138:52] - io.out.fence_i <= _T_998 @[el2_dec_dec_ctl.scala 138:18] - node _T_999 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] - node _T_1000 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] - node _T_1001 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1003 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1005 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1006 = and(_T_999, _T_1000) @[el2_dec_dec_ctl.scala 139:59] - node _T_1007 = and(_T_1006, _T_1002) @[el2_dec_dec_ctl.scala 139:59] - node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 139:59] - node _T_1009 = and(_T_1008, _T_1005) @[el2_dec_dec_ctl.scala 139:59] - node _T_1010 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1011 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1012 = and(_T_1010, _T_1011) @[el2_dec_dec_ctl.scala 139:92] - node _T_1013 = or(_T_1009, _T_1012) @[el2_dec_dec_ctl.scala 139:63] - node _T_1014 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1015 = eq(_T_1014, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1016 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1017 = eq(_T_1016, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1018 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1019 = and(_T_1015, _T_1017) @[el2_dec_dec_ctl.scala 140:37] - node _T_1020 = and(_T_1019, _T_1018) @[el2_dec_dec_ctl.scala 140:37] - node _T_1021 = or(_T_1013, _T_1020) @[el2_dec_dec_ctl.scala 139:96] - node _T_1022 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1024 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1025 = and(_T_1023, _T_1024) @[el2_dec_dec_ctl.scala 140:71] - node _T_1026 = or(_T_1021, _T_1025) @[el2_dec_dec_ctl.scala 140:41] - io.out.pm_alu <= _T_1026 @[el2_dec_dec_ctl.scala 139:17] - node _T_1027 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1028 = eq(_T_1027, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1029 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1030 = and(_T_1028, _T_1029) @[el2_dec_dec_ctl.scala 141:49] - node _T_1031 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1032 = eq(_T_1031, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1033 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_1034 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1035 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1036 = and(_T_1032, _T_1033) @[el2_dec_dec_ctl.scala 141:88] - node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 141:88] - node _T_1038 = and(_T_1037, _T_1035) @[el2_dec_dec_ctl.scala 141:88] - node _T_1039 = or(_T_1030, _T_1038) @[el2_dec_dec_ctl.scala 141:53] - node _T_1040 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1042 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_1043 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1044 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1045 = and(_T_1041, _T_1042) @[el2_dec_dec_ctl.scala 142:38] - node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 142:38] - node _T_1047 = and(_T_1046, _T_1044) @[el2_dec_dec_ctl.scala 142:38] - node _T_1048 = or(_T_1039, _T_1047) @[el2_dec_dec_ctl.scala 141:92] - node _T_1049 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1051 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_1052 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1053 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1054 = and(_T_1050, _T_1051) @[el2_dec_dec_ctl.scala 142:77] - node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 142:77] - node _T_1056 = and(_T_1055, _T_1053) @[el2_dec_dec_ctl.scala 142:77] - node _T_1057 = or(_T_1048, _T_1056) @[el2_dec_dec_ctl.scala 142:42] - node _T_1058 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1059 = eq(_T_1058, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1060 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_1061 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1062 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1063 = and(_T_1059, _T_1060) @[el2_dec_dec_ctl.scala 143:38] - node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 143:38] - node _T_1065 = and(_T_1064, _T_1062) @[el2_dec_dec_ctl.scala 143:38] - node _T_1066 = or(_T_1057, _T_1065) @[el2_dec_dec_ctl.scala 142:81] - node _T_1067 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1069 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_1070 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1071 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1072 = and(_T_1068, _T_1069) @[el2_dec_dec_ctl.scala 143:78] - node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 143:78] - node _T_1074 = and(_T_1073, _T_1071) @[el2_dec_dec_ctl.scala 143:78] - node _T_1075 = or(_T_1066, _T_1074) @[el2_dec_dec_ctl.scala 143:42] - node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1078 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_1079 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1080 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1081 = and(_T_1077, _T_1078) @[el2_dec_dec_ctl.scala 144:39] - node _T_1082 = and(_T_1081, _T_1079) @[el2_dec_dec_ctl.scala 144:39] - node _T_1083 = and(_T_1082, _T_1080) @[el2_dec_dec_ctl.scala 144:39] - node _T_1084 = or(_T_1075, _T_1083) @[el2_dec_dec_ctl.scala 143:82] - node _T_1085 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_1086 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1087 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1088 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1089 = and(_T_1085, _T_1086) @[el2_dec_dec_ctl.scala 144:78] - node _T_1090 = and(_T_1089, _T_1087) @[el2_dec_dec_ctl.scala 144:78] - node _T_1091 = and(_T_1090, _T_1088) @[el2_dec_dec_ctl.scala 144:78] - node _T_1092 = or(_T_1084, _T_1091) @[el2_dec_dec_ctl.scala 144:43] - node _T_1093 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_1094 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1095 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1096 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1097 = and(_T_1093, _T_1094) @[el2_dec_dec_ctl.scala 145:38] - node _T_1098 = and(_T_1097, _T_1095) @[el2_dec_dec_ctl.scala 145:38] - node _T_1099 = and(_T_1098, _T_1096) @[el2_dec_dec_ctl.scala 145:38] - node _T_1100 = or(_T_1092, _T_1099) @[el2_dec_dec_ctl.scala 144:82] - node _T_1101 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_1102 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1104 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1105 = and(_T_1101, _T_1102) @[el2_dec_dec_ctl.scala 145:77] - node _T_1106 = and(_T_1105, _T_1103) @[el2_dec_dec_ctl.scala 145:77] - node _T_1107 = and(_T_1106, _T_1104) @[el2_dec_dec_ctl.scala 145:77] - node _T_1108 = or(_T_1100, _T_1107) @[el2_dec_dec_ctl.scala 145:42] - node _T_1109 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_1110 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1111 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1112 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1113 = and(_T_1109, _T_1110) @[el2_dec_dec_ctl.scala 146:38] - node _T_1114 = and(_T_1113, _T_1111) @[el2_dec_dec_ctl.scala 146:38] - node _T_1115 = and(_T_1114, _T_1112) @[el2_dec_dec_ctl.scala 146:38] - node _T_1116 = or(_T_1108, _T_1115) @[el2_dec_dec_ctl.scala 145:81] - node _T_1117 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_1118 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1119 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1120 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1121 = and(_T_1117, _T_1118) @[el2_dec_dec_ctl.scala 146:77] - node _T_1122 = and(_T_1121, _T_1119) @[el2_dec_dec_ctl.scala 146:77] - node _T_1123 = and(_T_1122, _T_1120) @[el2_dec_dec_ctl.scala 146:77] - node _T_1124 = or(_T_1116, _T_1123) @[el2_dec_dec_ctl.scala 146:42] - io.out.presync <= _T_1124 @[el2_dec_dec_ctl.scala 141:18] - node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_1126 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1128 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1129 = and(_T_1125, _T_1127) @[el2_dec_dec_ctl.scala 147:53] - node _T_1130 = and(_T_1129, _T_1128) @[el2_dec_dec_ctl.scala 147:53] - node _T_1131 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1133 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1135 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1139 = and(_T_1132, _T_1134) @[el2_dec_dec_ctl.scala 147:98] - node _T_1140 = and(_T_1139, _T_1136) @[el2_dec_dec_ctl.scala 147:98] - node _T_1141 = and(_T_1140, _T_1137) @[el2_dec_dec_ctl.scala 147:98] - node _T_1142 = and(_T_1141, _T_1138) @[el2_dec_dec_ctl.scala 147:98] - node _T_1143 = or(_T_1130, _T_1142) @[el2_dec_dec_ctl.scala 147:57] - node _T_1144 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1146 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] - node _T_1147 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1148 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1149 = and(_T_1145, _T_1146) @[el2_dec_dec_ctl.scala 148:38] - node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 148:38] - node _T_1151 = and(_T_1150, _T_1148) @[el2_dec_dec_ctl.scala 148:38] - node _T_1152 = or(_T_1143, _T_1151) @[el2_dec_dec_ctl.scala 147:102] - node _T_1153 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1155 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] - node _T_1156 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1157 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1158 = and(_T_1154, _T_1155) @[el2_dec_dec_ctl.scala 148:77] - node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 148:77] - node _T_1160 = and(_T_1159, _T_1157) @[el2_dec_dec_ctl.scala 148:77] - node _T_1161 = or(_T_1152, _T_1160) @[el2_dec_dec_ctl.scala 148:42] - node _T_1162 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1164 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] - node _T_1165 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1166 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1167 = and(_T_1163, _T_1164) @[el2_dec_dec_ctl.scala 149:38] - node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 149:38] - node _T_1169 = and(_T_1168, _T_1166) @[el2_dec_dec_ctl.scala 149:38] - node _T_1170 = or(_T_1161, _T_1169) @[el2_dec_dec_ctl.scala 148:81] - node _T_1171 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1172 = eq(_T_1171, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1173 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] - node _T_1174 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1175 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1176 = and(_T_1172, _T_1173) @[el2_dec_dec_ctl.scala 149:78] - node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 149:78] - node _T_1178 = and(_T_1177, _T_1175) @[el2_dec_dec_ctl.scala 149:78] - node _T_1179 = or(_T_1170, _T_1178) @[el2_dec_dec_ctl.scala 149:42] - node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1182 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] - node _T_1183 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1184 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1185 = and(_T_1181, _T_1182) @[el2_dec_dec_ctl.scala 150:39] - node _T_1186 = and(_T_1185, _T_1183) @[el2_dec_dec_ctl.scala 150:39] - node _T_1187 = and(_T_1186, _T_1184) @[el2_dec_dec_ctl.scala 150:39] - node _T_1188 = or(_T_1179, _T_1187) @[el2_dec_dec_ctl.scala 149:82] - node _T_1189 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] - node _T_1190 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1191 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1192 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1193 = and(_T_1189, _T_1190) @[el2_dec_dec_ctl.scala 150:78] - node _T_1194 = and(_T_1193, _T_1191) @[el2_dec_dec_ctl.scala 150:78] - node _T_1195 = and(_T_1194, _T_1192) @[el2_dec_dec_ctl.scala 150:78] - node _T_1196 = or(_T_1188, _T_1195) @[el2_dec_dec_ctl.scala 150:43] - node _T_1197 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] - node _T_1198 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1199 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1200 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1201 = and(_T_1197, _T_1198) @[el2_dec_dec_ctl.scala 151:38] - node _T_1202 = and(_T_1201, _T_1199) @[el2_dec_dec_ctl.scala 151:38] - node _T_1203 = and(_T_1202, _T_1200) @[el2_dec_dec_ctl.scala 151:38] - node _T_1204 = or(_T_1196, _T_1203) @[el2_dec_dec_ctl.scala 150:82] - node _T_1205 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] - node _T_1206 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1207 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1208 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1209 = and(_T_1205, _T_1206) @[el2_dec_dec_ctl.scala 151:77] - node _T_1210 = and(_T_1209, _T_1207) @[el2_dec_dec_ctl.scala 151:77] - node _T_1211 = and(_T_1210, _T_1208) @[el2_dec_dec_ctl.scala 151:77] - node _T_1212 = or(_T_1204, _T_1211) @[el2_dec_dec_ctl.scala 151:42] - node _T_1213 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] - node _T_1214 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1215 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1216 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1217 = and(_T_1213, _T_1214) @[el2_dec_dec_ctl.scala 152:38] - node _T_1218 = and(_T_1217, _T_1215) @[el2_dec_dec_ctl.scala 152:38] - node _T_1219 = and(_T_1218, _T_1216) @[el2_dec_dec_ctl.scala 152:38] - node _T_1220 = or(_T_1212, _T_1219) @[el2_dec_dec_ctl.scala 151:81] - node _T_1221 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] - node _T_1222 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1223 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1224 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1225 = and(_T_1221, _T_1222) @[el2_dec_dec_ctl.scala 152:77] - node _T_1226 = and(_T_1225, _T_1223) @[el2_dec_dec_ctl.scala 152:77] - node _T_1227 = and(_T_1226, _T_1224) @[el2_dec_dec_ctl.scala 152:77] - node _T_1228 = or(_T_1220, _T_1227) @[el2_dec_dec_ctl.scala 152:42] - io.out.postsync <= _T_1228 @[el2_dec_dec_ctl.scala 147:19] - node _T_1229 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1231 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1233 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] - node _T_1234 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] - node _T_1235 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1237 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1238 = eq(_T_1237, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1239 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1241 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1243 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1244 = eq(_T_1243, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1245 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1246 = eq(_T_1245, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1247 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:33] - node _T_1248 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] - node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1250 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1252 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1254 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1256 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1258 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1260 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1262 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1264 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1266 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1267 = eq(_T_1266, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1268 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1269 = eq(_T_1268, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1270 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1273 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1274 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1275 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1279 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1280 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1281 = eq(_T_1280, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1282 = and(_T_1230, _T_1232) @[el2_dec_dec_ctl.scala 153:144] - node _T_1283 = and(_T_1282, _T_1233) @[el2_dec_dec_ctl.scala 153:144] - node _T_1284 = and(_T_1283, _T_1234) @[el2_dec_dec_ctl.scala 153:144] - node _T_1285 = and(_T_1284, _T_1236) @[el2_dec_dec_ctl.scala 153:144] - node _T_1286 = and(_T_1285, _T_1238) @[el2_dec_dec_ctl.scala 153:144] - node _T_1287 = and(_T_1286, _T_1240) @[el2_dec_dec_ctl.scala 153:144] - node _T_1288 = and(_T_1287, _T_1242) @[el2_dec_dec_ctl.scala 153:144] - node _T_1289 = and(_T_1288, _T_1244) @[el2_dec_dec_ctl.scala 153:144] - node _T_1290 = and(_T_1289, _T_1246) @[el2_dec_dec_ctl.scala 153:144] - node _T_1291 = and(_T_1290, _T_1247) @[el2_dec_dec_ctl.scala 153:144] - node _T_1292 = and(_T_1291, _T_1249) @[el2_dec_dec_ctl.scala 153:144] - node _T_1293 = and(_T_1292, _T_1251) @[el2_dec_dec_ctl.scala 153:144] - node _T_1294 = and(_T_1293, _T_1253) @[el2_dec_dec_ctl.scala 153:144] - node _T_1295 = and(_T_1294, _T_1255) @[el2_dec_dec_ctl.scala 153:144] - node _T_1296 = and(_T_1295, _T_1257) @[el2_dec_dec_ctl.scala 153:144] - node _T_1297 = and(_T_1296, _T_1259) @[el2_dec_dec_ctl.scala 153:144] - node _T_1298 = and(_T_1297, _T_1261) @[el2_dec_dec_ctl.scala 153:144] - node _T_1299 = and(_T_1298, _T_1263) @[el2_dec_dec_ctl.scala 153:144] - node _T_1300 = and(_T_1299, _T_1265) @[el2_dec_dec_ctl.scala 153:144] - node _T_1301 = and(_T_1300, _T_1267) @[el2_dec_dec_ctl.scala 153:144] - node _T_1302 = and(_T_1301, _T_1269) @[el2_dec_dec_ctl.scala 153:144] - node _T_1303 = and(_T_1302, _T_1271) @[el2_dec_dec_ctl.scala 153:144] - node _T_1304 = and(_T_1303, _T_1272) @[el2_dec_dec_ctl.scala 153:144] - node _T_1305 = and(_T_1304, _T_1273) @[el2_dec_dec_ctl.scala 153:144] - node _T_1306 = and(_T_1305, _T_1274) @[el2_dec_dec_ctl.scala 153:144] - node _T_1307 = and(_T_1306, _T_1276) @[el2_dec_dec_ctl.scala 153:144] - node _T_1308 = and(_T_1307, _T_1278) @[el2_dec_dec_ctl.scala 153:144] - node _T_1309 = and(_T_1308, _T_1279) @[el2_dec_dec_ctl.scala 153:144] - node _T_1310 = and(_T_1309, _T_1281) @[el2_dec_dec_ctl.scala 153:144] - node _T_1311 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1313 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1315 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1317 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] - node _T_1318 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1320 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1321 = eq(_T_1320, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1322 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1324 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1326 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1328 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] - node _T_1329 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1331 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] - node _T_1332 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1334 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1336 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1338 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1339 = eq(_T_1338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1340 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1342 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1343 = eq(_T_1342, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1344 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1345 = eq(_T_1344, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1346 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1348 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1350 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1352 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1354 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1355 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1356 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1357 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1358 = eq(_T_1357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1360 = eq(_T_1359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1361 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1362 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1364 = and(_T_1312, _T_1314) @[el2_dec_dec_ctl.scala 154:130] - node _T_1365 = and(_T_1364, _T_1316) @[el2_dec_dec_ctl.scala 154:130] - node _T_1366 = and(_T_1365, _T_1317) @[el2_dec_dec_ctl.scala 154:130] - node _T_1367 = and(_T_1366, _T_1319) @[el2_dec_dec_ctl.scala 154:130] - node _T_1368 = and(_T_1367, _T_1321) @[el2_dec_dec_ctl.scala 154:130] - node _T_1369 = and(_T_1368, _T_1323) @[el2_dec_dec_ctl.scala 154:130] - node _T_1370 = and(_T_1369, _T_1325) @[el2_dec_dec_ctl.scala 154:130] - node _T_1371 = and(_T_1370, _T_1327) @[el2_dec_dec_ctl.scala 154:130] - node _T_1372 = and(_T_1371, _T_1328) @[el2_dec_dec_ctl.scala 154:130] - node _T_1373 = and(_T_1372, _T_1330) @[el2_dec_dec_ctl.scala 154:130] - node _T_1374 = and(_T_1373, _T_1331) @[el2_dec_dec_ctl.scala 154:130] - node _T_1375 = and(_T_1374, _T_1333) @[el2_dec_dec_ctl.scala 154:130] - node _T_1376 = and(_T_1375, _T_1335) @[el2_dec_dec_ctl.scala 154:130] - node _T_1377 = and(_T_1376, _T_1337) @[el2_dec_dec_ctl.scala 154:130] - node _T_1378 = and(_T_1377, _T_1339) @[el2_dec_dec_ctl.scala 154:130] - node _T_1379 = and(_T_1378, _T_1341) @[el2_dec_dec_ctl.scala 154:130] - node _T_1380 = and(_T_1379, _T_1343) @[el2_dec_dec_ctl.scala 154:130] - node _T_1381 = and(_T_1380, _T_1345) @[el2_dec_dec_ctl.scala 154:130] - node _T_1382 = and(_T_1381, _T_1347) @[el2_dec_dec_ctl.scala 154:130] - node _T_1383 = and(_T_1382, _T_1349) @[el2_dec_dec_ctl.scala 154:130] - node _T_1384 = and(_T_1383, _T_1351) @[el2_dec_dec_ctl.scala 154:130] - node _T_1385 = and(_T_1384, _T_1353) @[el2_dec_dec_ctl.scala 154:130] - node _T_1386 = and(_T_1385, _T_1354) @[el2_dec_dec_ctl.scala 154:130] - node _T_1387 = and(_T_1386, _T_1355) @[el2_dec_dec_ctl.scala 154:130] - node _T_1388 = and(_T_1387, _T_1356) @[el2_dec_dec_ctl.scala 154:130] - node _T_1389 = and(_T_1388, _T_1358) @[el2_dec_dec_ctl.scala 154:130] - node _T_1390 = and(_T_1389, _T_1360) @[el2_dec_dec_ctl.scala 154:130] - node _T_1391 = and(_T_1390, _T_1361) @[el2_dec_dec_ctl.scala 154:130] - node _T_1392 = and(_T_1391, _T_1363) @[el2_dec_dec_ctl.scala 154:130] - node _T_1393 = or(_T_1310, _T_1392) @[el2_dec_dec_ctl.scala 153:148] - node _T_1394 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1396 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1398 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1400 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1402 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1404 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1406 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1408 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1410 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1412 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1414 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1416 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1418 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1420 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1422 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1424 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1426 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1428 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1430 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1432 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1434 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1436 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1437 = eq(_T_1436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1438 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1439 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1440 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1442 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1444 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1445 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1447 = and(_T_1395, _T_1397) @[el2_dec_dec_ctl.scala 155:127] - node _T_1448 = and(_T_1447, _T_1399) @[el2_dec_dec_ctl.scala 155:127] - node _T_1449 = and(_T_1448, _T_1401) @[el2_dec_dec_ctl.scala 155:127] - node _T_1450 = and(_T_1449, _T_1403) @[el2_dec_dec_ctl.scala 155:127] - node _T_1451 = and(_T_1450, _T_1405) @[el2_dec_dec_ctl.scala 155:127] - node _T_1452 = and(_T_1451, _T_1407) @[el2_dec_dec_ctl.scala 155:127] - node _T_1453 = and(_T_1452, _T_1409) @[el2_dec_dec_ctl.scala 155:127] - node _T_1454 = and(_T_1453, _T_1411) @[el2_dec_dec_ctl.scala 155:127] - node _T_1455 = and(_T_1454, _T_1413) @[el2_dec_dec_ctl.scala 155:127] - node _T_1456 = and(_T_1455, _T_1415) @[el2_dec_dec_ctl.scala 155:127] - node _T_1457 = and(_T_1456, _T_1417) @[el2_dec_dec_ctl.scala 155:127] - node _T_1458 = and(_T_1457, _T_1419) @[el2_dec_dec_ctl.scala 155:127] - node _T_1459 = and(_T_1458, _T_1421) @[el2_dec_dec_ctl.scala 155:127] - node _T_1460 = and(_T_1459, _T_1423) @[el2_dec_dec_ctl.scala 155:127] - node _T_1461 = and(_T_1460, _T_1425) @[el2_dec_dec_ctl.scala 155:127] - node _T_1462 = and(_T_1461, _T_1427) @[el2_dec_dec_ctl.scala 155:127] - node _T_1463 = and(_T_1462, _T_1429) @[el2_dec_dec_ctl.scala 155:127] - node _T_1464 = and(_T_1463, _T_1431) @[el2_dec_dec_ctl.scala 155:127] - node _T_1465 = and(_T_1464, _T_1433) @[el2_dec_dec_ctl.scala 155:127] - node _T_1466 = and(_T_1465, _T_1435) @[el2_dec_dec_ctl.scala 155:127] - node _T_1467 = and(_T_1466, _T_1437) @[el2_dec_dec_ctl.scala 155:127] - node _T_1468 = and(_T_1467, _T_1438) @[el2_dec_dec_ctl.scala 155:127] - node _T_1469 = and(_T_1468, _T_1439) @[el2_dec_dec_ctl.scala 155:127] - node _T_1470 = and(_T_1469, _T_1441) @[el2_dec_dec_ctl.scala 155:127] - node _T_1471 = and(_T_1470, _T_1443) @[el2_dec_dec_ctl.scala 155:127] - node _T_1472 = and(_T_1471, _T_1444) @[el2_dec_dec_ctl.scala 155:127] - node _T_1473 = and(_T_1472, _T_1446) @[el2_dec_dec_ctl.scala 155:127] - node _T_1474 = or(_T_1393, _T_1473) @[el2_dec_dec_ctl.scala 154:134] - node _T_1475 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1477 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1479 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1481 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1483 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1485 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1486 = eq(_T_1485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1487 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1489 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1491 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1492 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1494 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1495 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1497 = and(_T_1476, _T_1478) @[el2_dec_dec_ctl.scala 156:68] - node _T_1498 = and(_T_1497, _T_1480) @[el2_dec_dec_ctl.scala 156:68] - node _T_1499 = and(_T_1498, _T_1482) @[el2_dec_dec_ctl.scala 156:68] - node _T_1500 = and(_T_1499, _T_1484) @[el2_dec_dec_ctl.scala 156:68] - node _T_1501 = and(_T_1500, _T_1486) @[el2_dec_dec_ctl.scala 156:68] - node _T_1502 = and(_T_1501, _T_1488) @[el2_dec_dec_ctl.scala 156:68] - node _T_1503 = and(_T_1502, _T_1490) @[el2_dec_dec_ctl.scala 156:68] - node _T_1504 = and(_T_1503, _T_1491) @[el2_dec_dec_ctl.scala 156:68] - node _T_1505 = and(_T_1504, _T_1493) @[el2_dec_dec_ctl.scala 156:68] - node _T_1506 = and(_T_1505, _T_1494) @[el2_dec_dec_ctl.scala 156:68] - node _T_1507 = and(_T_1506, _T_1496) @[el2_dec_dec_ctl.scala 156:68] - node _T_1508 = or(_T_1474, _T_1507) @[el2_dec_dec_ctl.scala 155:131] - node _T_1509 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1511 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1513 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1515 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1517 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1519 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1520 = eq(_T_1519, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1521 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1523 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1525 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1527 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1529 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1530 = eq(_T_1529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1531 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1532 = eq(_T_1531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1533 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1534 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1536 = and(_T_1510, _T_1512) @[el2_dec_dec_ctl.scala 157:77] - node _T_1537 = and(_T_1536, _T_1514) @[el2_dec_dec_ctl.scala 157:77] - node _T_1538 = and(_T_1537, _T_1516) @[el2_dec_dec_ctl.scala 157:77] - node _T_1539 = and(_T_1538, _T_1518) @[el2_dec_dec_ctl.scala 157:77] - node _T_1540 = and(_T_1539, _T_1520) @[el2_dec_dec_ctl.scala 157:77] - node _T_1541 = and(_T_1540, _T_1522) @[el2_dec_dec_ctl.scala 157:77] - node _T_1542 = and(_T_1541, _T_1524) @[el2_dec_dec_ctl.scala 157:77] - node _T_1543 = and(_T_1542, _T_1526) @[el2_dec_dec_ctl.scala 157:77] - node _T_1544 = and(_T_1543, _T_1528) @[el2_dec_dec_ctl.scala 157:77] - node _T_1545 = and(_T_1544, _T_1530) @[el2_dec_dec_ctl.scala 157:77] - node _T_1546 = and(_T_1545, _T_1532) @[el2_dec_dec_ctl.scala 157:77] - node _T_1547 = and(_T_1546, _T_1533) @[el2_dec_dec_ctl.scala 157:77] - node _T_1548 = and(_T_1547, _T_1535) @[el2_dec_dec_ctl.scala 157:77] - node _T_1549 = or(_T_1508, _T_1548) @[el2_dec_dec_ctl.scala 156:72] - node _T_1550 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1552 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1554 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1556 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1558 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1559 = eq(_T_1558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1560 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1562 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_1563 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1564 = eq(_T_1563, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1565 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_1566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1567 = eq(_T_1566, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1568 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1569 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1571 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1572 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1574 = and(_T_1551, _T_1553) @[el2_dec_dec_ctl.scala 158:74] - node _T_1575 = and(_T_1574, _T_1555) @[el2_dec_dec_ctl.scala 158:74] - node _T_1576 = and(_T_1575, _T_1557) @[el2_dec_dec_ctl.scala 158:74] - node _T_1577 = and(_T_1576, _T_1559) @[el2_dec_dec_ctl.scala 158:74] - node _T_1578 = and(_T_1577, _T_1561) @[el2_dec_dec_ctl.scala 158:74] - node _T_1579 = and(_T_1578, _T_1562) @[el2_dec_dec_ctl.scala 158:74] - node _T_1580 = and(_T_1579, _T_1564) @[el2_dec_dec_ctl.scala 158:74] - node _T_1581 = and(_T_1580, _T_1565) @[el2_dec_dec_ctl.scala 158:74] - node _T_1582 = and(_T_1581, _T_1567) @[el2_dec_dec_ctl.scala 158:74] - node _T_1583 = and(_T_1582, _T_1568) @[el2_dec_dec_ctl.scala 158:74] - node _T_1584 = and(_T_1583, _T_1570) @[el2_dec_dec_ctl.scala 158:74] - node _T_1585 = and(_T_1584, _T_1571) @[el2_dec_dec_ctl.scala 158:74] - node _T_1586 = and(_T_1585, _T_1573) @[el2_dec_dec_ctl.scala 158:74] - node _T_1587 = or(_T_1549, _T_1586) @[el2_dec_dec_ctl.scala 157:81] - node _T_1588 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1590 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1592 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1594 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1596 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1598 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1599 = eq(_T_1598, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1600 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1601 = eq(_T_1600, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1602 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1603 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1604 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1606 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1607 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1609 = and(_T_1589, _T_1591) @[el2_dec_dec_ctl.scala 159:66] - node _T_1610 = and(_T_1609, _T_1593) @[el2_dec_dec_ctl.scala 159:66] - node _T_1611 = and(_T_1610, _T_1595) @[el2_dec_dec_ctl.scala 159:66] - node _T_1612 = and(_T_1611, _T_1597) @[el2_dec_dec_ctl.scala 159:66] - node _T_1613 = and(_T_1612, _T_1599) @[el2_dec_dec_ctl.scala 159:66] - node _T_1614 = and(_T_1613, _T_1601) @[el2_dec_dec_ctl.scala 159:66] - node _T_1615 = and(_T_1614, _T_1602) @[el2_dec_dec_ctl.scala 159:66] - node _T_1616 = and(_T_1615, _T_1603) @[el2_dec_dec_ctl.scala 159:66] - node _T_1617 = and(_T_1616, _T_1605) @[el2_dec_dec_ctl.scala 159:66] - node _T_1618 = and(_T_1617, _T_1606) @[el2_dec_dec_ctl.scala 159:66] - node _T_1619 = and(_T_1618, _T_1608) @[el2_dec_dec_ctl.scala 159:66] - node _T_1620 = or(_T_1587, _T_1619) @[el2_dec_dec_ctl.scala 158:78] - node _T_1621 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1622 = eq(_T_1621, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1623 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1624 = eq(_T_1623, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1625 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1627 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1628 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1629 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1631 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1632 = eq(_T_1631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1633 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1634 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1636 = and(_T_1622, _T_1624) @[el2_dec_dec_ctl.scala 160:54] - node _T_1637 = and(_T_1636, _T_1626) @[el2_dec_dec_ctl.scala 160:54] - node _T_1638 = and(_T_1637, _T_1627) @[el2_dec_dec_ctl.scala 160:54] - node _T_1639 = and(_T_1638, _T_1628) @[el2_dec_dec_ctl.scala 160:54] - node _T_1640 = and(_T_1639, _T_1630) @[el2_dec_dec_ctl.scala 160:54] - node _T_1641 = and(_T_1640, _T_1632) @[el2_dec_dec_ctl.scala 160:54] - node _T_1642 = and(_T_1641, _T_1633) @[el2_dec_dec_ctl.scala 160:54] - node _T_1643 = and(_T_1642, _T_1635) @[el2_dec_dec_ctl.scala 160:54] - node _T_1644 = or(_T_1620, _T_1643) @[el2_dec_dec_ctl.scala 159:70] - node _T_1645 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] - node _T_1646 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1647 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1648 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1650 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1652 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1653 = eq(_T_1652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1654 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1655 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1656 = eq(_T_1655, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1657 = and(_T_1645, _T_1646) @[el2_dec_dec_ctl.scala 161:48] - node _T_1658 = and(_T_1657, _T_1647) @[el2_dec_dec_ctl.scala 161:48] - node _T_1659 = and(_T_1658, _T_1649) @[el2_dec_dec_ctl.scala 161:48] - node _T_1660 = and(_T_1659, _T_1651) @[el2_dec_dec_ctl.scala 161:48] - node _T_1661 = and(_T_1660, _T_1653) @[el2_dec_dec_ctl.scala 161:48] - node _T_1662 = and(_T_1661, _T_1654) @[el2_dec_dec_ctl.scala 161:48] - node _T_1663 = and(_T_1662, _T_1656) @[el2_dec_dec_ctl.scala 161:48] - node _T_1664 = or(_T_1644, _T_1663) @[el2_dec_dec_ctl.scala 160:58] - node _T_1665 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1666 = eq(_T_1665, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1668 = eq(_T_1667, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1669 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1672 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1673 = eq(_T_1672, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1674 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1675 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1677 = and(_T_1666, _T_1668) @[el2_dec_dec_ctl.scala 162:47] - node _T_1678 = and(_T_1677, _T_1670) @[el2_dec_dec_ctl.scala 162:47] - node _T_1679 = and(_T_1678, _T_1671) @[el2_dec_dec_ctl.scala 162:47] - node _T_1680 = and(_T_1679, _T_1673) @[el2_dec_dec_ctl.scala 162:47] - node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 162:47] - node _T_1682 = and(_T_1681, _T_1676) @[el2_dec_dec_ctl.scala 162:47] - node _T_1683 = or(_T_1664, _T_1682) @[el2_dec_dec_ctl.scala 161:52] - node _T_1684 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1685 = eq(_T_1684, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1686 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1688 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1691 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1693 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1695 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1696 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1697 = eq(_T_1696, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1698 = and(_T_1685, _T_1687) @[el2_dec_dec_ctl.scala 162:99] - node _T_1699 = and(_T_1698, _T_1688) @[el2_dec_dec_ctl.scala 162:99] - node _T_1700 = and(_T_1699, _T_1690) @[el2_dec_dec_ctl.scala 162:99] - node _T_1701 = and(_T_1700, _T_1692) @[el2_dec_dec_ctl.scala 162:99] - node _T_1702 = and(_T_1701, _T_1694) @[el2_dec_dec_ctl.scala 162:99] - node _T_1703 = and(_T_1702, _T_1695) @[el2_dec_dec_ctl.scala 162:99] - node _T_1704 = and(_T_1703, _T_1697) @[el2_dec_dec_ctl.scala 162:99] - node _T_1705 = or(_T_1683, _T_1704) @[el2_dec_dec_ctl.scala 162:51] - node _T_1706 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] - node _T_1707 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1708 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1709 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1710 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1711 = eq(_T_1710, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1712 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1714 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1715 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1717 = and(_T_1706, _T_1707) @[el2_dec_dec_ctl.scala 163:47] - node _T_1718 = and(_T_1717, _T_1708) @[el2_dec_dec_ctl.scala 163:47] - node _T_1719 = and(_T_1718, _T_1709) @[el2_dec_dec_ctl.scala 163:47] - node _T_1720 = and(_T_1719, _T_1711) @[el2_dec_dec_ctl.scala 163:47] - node _T_1721 = and(_T_1720, _T_1713) @[el2_dec_dec_ctl.scala 163:47] - node _T_1722 = and(_T_1721, _T_1714) @[el2_dec_dec_ctl.scala 163:47] - node _T_1723 = and(_T_1722, _T_1716) @[el2_dec_dec_ctl.scala 163:47] - node _T_1724 = or(_T_1705, _T_1723) @[el2_dec_dec_ctl.scala 162:103] - node _T_1725 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1727 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1729 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1731 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1733 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] - node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1735 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] - node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1737 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] - node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1739 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] - node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1741 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] - node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1743 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] - node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1745 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] - node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1747 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] - node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1749 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1751 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1753 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1755 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1757 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1759 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1761 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1762 = eq(_T_1761, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1763 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1764 = eq(_T_1763, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1765 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1767 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1768 = eq(_T_1767, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1769 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1770 = eq(_T_1769, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1771 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1773 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1775 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1777 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1778 = eq(_T_1777, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1779 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1781 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1782 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1783 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1784 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1785 = eq(_T_1784, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1786 = and(_T_1726, _T_1728) @[el2_dec_dec_ctl.scala 164:142] - node _T_1787 = and(_T_1786, _T_1730) @[el2_dec_dec_ctl.scala 164:142] - node _T_1788 = and(_T_1787, _T_1732) @[el2_dec_dec_ctl.scala 164:142] - node _T_1789 = and(_T_1788, _T_1734) @[el2_dec_dec_ctl.scala 164:142] - node _T_1790 = and(_T_1789, _T_1736) @[el2_dec_dec_ctl.scala 164:142] - node _T_1791 = and(_T_1790, _T_1738) @[el2_dec_dec_ctl.scala 164:142] - node _T_1792 = and(_T_1791, _T_1740) @[el2_dec_dec_ctl.scala 164:142] - node _T_1793 = and(_T_1792, _T_1742) @[el2_dec_dec_ctl.scala 164:142] - node _T_1794 = and(_T_1793, _T_1744) @[el2_dec_dec_ctl.scala 164:142] - node _T_1795 = and(_T_1794, _T_1746) @[el2_dec_dec_ctl.scala 164:142] - node _T_1796 = and(_T_1795, _T_1748) @[el2_dec_dec_ctl.scala 164:142] - node _T_1797 = and(_T_1796, _T_1750) @[el2_dec_dec_ctl.scala 164:142] - node _T_1798 = and(_T_1797, _T_1752) @[el2_dec_dec_ctl.scala 164:142] - node _T_1799 = and(_T_1798, _T_1754) @[el2_dec_dec_ctl.scala 164:142] - node _T_1800 = and(_T_1799, _T_1756) @[el2_dec_dec_ctl.scala 164:142] - node _T_1801 = and(_T_1800, _T_1758) @[el2_dec_dec_ctl.scala 164:142] - node _T_1802 = and(_T_1801, _T_1760) @[el2_dec_dec_ctl.scala 164:142] - node _T_1803 = and(_T_1802, _T_1762) @[el2_dec_dec_ctl.scala 164:142] - node _T_1804 = and(_T_1803, _T_1764) @[el2_dec_dec_ctl.scala 164:142] - node _T_1805 = and(_T_1804, _T_1766) @[el2_dec_dec_ctl.scala 164:142] - node _T_1806 = and(_T_1805, _T_1768) @[el2_dec_dec_ctl.scala 164:142] - node _T_1807 = and(_T_1806, _T_1770) @[el2_dec_dec_ctl.scala 164:142] - node _T_1808 = and(_T_1807, _T_1772) @[el2_dec_dec_ctl.scala 164:142] - node _T_1809 = and(_T_1808, _T_1774) @[el2_dec_dec_ctl.scala 164:142] - node _T_1810 = and(_T_1809, _T_1776) @[el2_dec_dec_ctl.scala 164:142] - node _T_1811 = and(_T_1810, _T_1778) @[el2_dec_dec_ctl.scala 164:142] - node _T_1812 = and(_T_1811, _T_1780) @[el2_dec_dec_ctl.scala 164:142] - node _T_1813 = and(_T_1812, _T_1781) @[el2_dec_dec_ctl.scala 164:142] - node _T_1814 = and(_T_1813, _T_1782) @[el2_dec_dec_ctl.scala 164:142] - node _T_1815 = and(_T_1814, _T_1783) @[el2_dec_dec_ctl.scala 164:142] - node _T_1816 = and(_T_1815, _T_1785) @[el2_dec_dec_ctl.scala 164:142] - node _T_1817 = or(_T_1724, _T_1816) @[el2_dec_dec_ctl.scala 163:51] - node _T_1818 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] - node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1820 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] - node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1822 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] - node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1824 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] - node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1826 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] - node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1828 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] - node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1830 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] - node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1832 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] - node _T_1833 = eq(_T_1832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1834 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] - node _T_1835 = eq(_T_1834, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1836 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1837 = eq(_T_1836, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1838 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1839 = eq(_T_1838, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1840 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1841 = eq(_T_1840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1842 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] - node _T_1843 = eq(_T_1842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1844 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] - node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1846 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] - node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1848 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] - node _T_1849 = eq(_T_1848, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1850 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] - node _T_1851 = eq(_T_1850, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1852 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1854 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1855 = eq(_T_1854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1856 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1857 = eq(_T_1856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1858 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1859 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1860 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1861 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1863 = and(_T_1819, _T_1821) @[el2_dec_dec_ctl.scala 165:110] - node _T_1864 = and(_T_1863, _T_1823) @[el2_dec_dec_ctl.scala 165:110] - node _T_1865 = and(_T_1864, _T_1825) @[el2_dec_dec_ctl.scala 165:110] - node _T_1866 = and(_T_1865, _T_1827) @[el2_dec_dec_ctl.scala 165:110] - node _T_1867 = and(_T_1866, _T_1829) @[el2_dec_dec_ctl.scala 165:110] - node _T_1868 = and(_T_1867, _T_1831) @[el2_dec_dec_ctl.scala 165:110] - node _T_1869 = and(_T_1868, _T_1833) @[el2_dec_dec_ctl.scala 165:110] - node _T_1870 = and(_T_1869, _T_1835) @[el2_dec_dec_ctl.scala 165:110] - node _T_1871 = and(_T_1870, _T_1837) @[el2_dec_dec_ctl.scala 165:110] - node _T_1872 = and(_T_1871, _T_1839) @[el2_dec_dec_ctl.scala 165:110] - node _T_1873 = and(_T_1872, _T_1841) @[el2_dec_dec_ctl.scala 165:110] - node _T_1874 = and(_T_1873, _T_1843) @[el2_dec_dec_ctl.scala 165:110] - node _T_1875 = and(_T_1874, _T_1845) @[el2_dec_dec_ctl.scala 165:110] - node _T_1876 = and(_T_1875, _T_1847) @[el2_dec_dec_ctl.scala 165:110] - node _T_1877 = and(_T_1876, _T_1849) @[el2_dec_dec_ctl.scala 165:110] - node _T_1878 = and(_T_1877, _T_1851) @[el2_dec_dec_ctl.scala 165:110] - node _T_1879 = and(_T_1878, _T_1853) @[el2_dec_dec_ctl.scala 165:110] - node _T_1880 = and(_T_1879, _T_1855) @[el2_dec_dec_ctl.scala 165:110] - node _T_1881 = and(_T_1880, _T_1857) @[el2_dec_dec_ctl.scala 165:110] - node _T_1882 = and(_T_1881, _T_1858) @[el2_dec_dec_ctl.scala 165:110] - node _T_1883 = and(_T_1882, _T_1859) @[el2_dec_dec_ctl.scala 165:110] - node _T_1884 = and(_T_1883, _T_1860) @[el2_dec_dec_ctl.scala 165:110] - node _T_1885 = and(_T_1884, _T_1862) @[el2_dec_dec_ctl.scala 165:110] - node _T_1886 = or(_T_1817, _T_1885) @[el2_dec_dec_ctl.scala 164:146] - node _T_1887 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] - node _T_1888 = eq(_T_1887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1889 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1891 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1892 = eq(_T_1891, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1893 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1895 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1897 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1898 = eq(_T_1897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1899 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1900 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1902 = and(_T_1888, _T_1890) @[el2_dec_dec_ctl.scala 166:51] - node _T_1903 = and(_T_1902, _T_1892) @[el2_dec_dec_ctl.scala 166:51] - node _T_1904 = and(_T_1903, _T_1894) @[el2_dec_dec_ctl.scala 166:51] - node _T_1905 = and(_T_1904, _T_1896) @[el2_dec_dec_ctl.scala 166:51] - node _T_1906 = and(_T_1905, _T_1898) @[el2_dec_dec_ctl.scala 166:51] - node _T_1907 = and(_T_1906, _T_1899) @[el2_dec_dec_ctl.scala 166:51] - node _T_1908 = and(_T_1907, _T_1901) @[el2_dec_dec_ctl.scala 166:51] - node _T_1909 = or(_T_1886, _T_1908) @[el2_dec_dec_ctl.scala 165:114] - node _T_1910 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] - node _T_1911 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] - node _T_1912 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1914 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] - node _T_1915 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1916 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1917 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1919 = and(_T_1910, _T_1911) @[el2_dec_dec_ctl.scala 166:95] - node _T_1920 = and(_T_1919, _T_1913) @[el2_dec_dec_ctl.scala 166:95] - node _T_1921 = and(_T_1920, _T_1914) @[el2_dec_dec_ctl.scala 166:95] - node _T_1922 = and(_T_1921, _T_1915) @[el2_dec_dec_ctl.scala 166:95] - node _T_1923 = and(_T_1922, _T_1916) @[el2_dec_dec_ctl.scala 166:95] - node _T_1924 = and(_T_1923, _T_1918) @[el2_dec_dec_ctl.scala 166:95] - node _T_1925 = or(_T_1909, _T_1924) @[el2_dec_dec_ctl.scala 166:55] - node _T_1926 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] - node _T_1927 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1928 = eq(_T_1927, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1929 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] - node _T_1930 = eq(_T_1929, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1931 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1932 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1934 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1935 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1937 = and(_T_1926, _T_1928) @[el2_dec_dec_ctl.scala 167:46] - node _T_1938 = and(_T_1937, _T_1930) @[el2_dec_dec_ctl.scala 167:46] - node _T_1939 = and(_T_1938, _T_1931) @[el2_dec_dec_ctl.scala 167:46] - node _T_1940 = and(_T_1939, _T_1933) @[el2_dec_dec_ctl.scala 167:46] - node _T_1941 = and(_T_1940, _T_1934) @[el2_dec_dec_ctl.scala 167:46] - node _T_1942 = and(_T_1941, _T_1936) @[el2_dec_dec_ctl.scala 167:46] - node _T_1943 = or(_T_1925, _T_1942) @[el2_dec_dec_ctl.scala 166:99] - node _T_1944 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] - node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1946 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] - node _T_1947 = eq(_T_1946, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1948 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1949 = eq(_T_1948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1950 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] - node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1952 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1954 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1956 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1957 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1959 = and(_T_1945, _T_1947) @[el2_dec_dec_ctl.scala 167:99] - node _T_1960 = and(_T_1959, _T_1949) @[el2_dec_dec_ctl.scala 167:99] - node _T_1961 = and(_T_1960, _T_1951) @[el2_dec_dec_ctl.scala 167:99] - node _T_1962 = and(_T_1961, _T_1953) @[el2_dec_dec_ctl.scala 167:99] - node _T_1963 = and(_T_1962, _T_1955) @[el2_dec_dec_ctl.scala 167:99] - node _T_1964 = and(_T_1963, _T_1956) @[el2_dec_dec_ctl.scala 167:99] - node _T_1965 = and(_T_1964, _T_1958) @[el2_dec_dec_ctl.scala 167:99] - node _T_1966 = or(_T_1943, _T_1965) @[el2_dec_dec_ctl.scala 167:50] - node _T_1967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] - node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] - node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] - node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] - node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1974 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1975 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1976 = eq(_T_1975, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1977 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:43] - node _T_1978 = and(_T_1977, _T_1971) @[el2_dec_dec_ctl.scala 168:43] - node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:43] - node _T_1980 = and(_T_1979, _T_1974) @[el2_dec_dec_ctl.scala 168:43] - node _T_1981 = and(_T_1980, _T_1976) @[el2_dec_dec_ctl.scala 168:43] - node _T_1982 = or(_T_1966, _T_1981) @[el2_dec_dec_ctl.scala 167:103] - io.out.legal <= _T_1982 @[el2_dec_dec_ctl.scala 153:16] + node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 20:23] + node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 20:35] + node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 20:27] + node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 20:49] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 20:42] + node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 20:60] + node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 20:53] + node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 20:39] + node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 20:75] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 20:68] + node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 20:85] + node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 20:78] + node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 20:65] + io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 20:14] + node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 17:17] + node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 17:17] + node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 17:17] + node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 17:17] + node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 21:43] + node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 17:17] + node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 17:17] + node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 21:70] + node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 17:17] + node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 17:17] + node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 22:29] + node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_45 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_46 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_48 = and(_T_44, _T_45) @[el2_dec_dec_ctl.scala 17:17] + node _T_49 = and(_T_48, _T_47) @[el2_dec_dec_ctl.scala 17:17] + node _T_50 = or(_T_43, _T_49) @[el2_dec_dec_ctl.scala 22:56] + node _T_51 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_53 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_54 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_56 = and(_T_52, _T_53) @[el2_dec_dec_ctl.scala 17:17] + node _T_57 = and(_T_56, _T_55) @[el2_dec_dec_ctl.scala 17:17] + node _T_58 = or(_T_50, _T_57) @[el2_dec_dec_ctl.scala 23:29] + node _T_59 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_60 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_61 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_63 = and(_T_59, _T_60) @[el2_dec_dec_ctl.scala 17:17] + node _T_64 = and(_T_63, _T_62) @[el2_dec_dec_ctl.scala 17:17] + node _T_65 = or(_T_58, _T_64) @[el2_dec_dec_ctl.scala 23:55] + node _T_66 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_68 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_69 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_70 = eq(_T_69, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_71 = and(_T_67, _T_68) @[el2_dec_dec_ctl.scala 17:17] + node _T_72 = and(_T_71, _T_70) @[el2_dec_dec_ctl.scala 17:17] + node _T_73 = or(_T_65, _T_72) @[el2_dec_dec_ctl.scala 24:29] + node _T_74 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_75 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_76 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_77 = eq(_T_76, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_78 = and(_T_74, _T_75) @[el2_dec_dec_ctl.scala 17:17] + node _T_79 = and(_T_78, _T_77) @[el2_dec_dec_ctl.scala 17:17] + node _T_80 = or(_T_73, _T_79) @[el2_dec_dec_ctl.scala 24:55] + node _T_81 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_83 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_84 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_86 = and(_T_82, _T_83) @[el2_dec_dec_ctl.scala 17:17] + node _T_87 = and(_T_86, _T_85) @[el2_dec_dec_ctl.scala 17:17] + node _T_88 = or(_T_80, _T_87) @[el2_dec_dec_ctl.scala 25:29] + node _T_89 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_90 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_91 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_93 = and(_T_89, _T_90) @[el2_dec_dec_ctl.scala 17:17] + node _T_94 = and(_T_93, _T_92) @[el2_dec_dec_ctl.scala 17:17] + node _T_95 = or(_T_88, _T_94) @[el2_dec_dec_ctl.scala 25:55] + node _T_96 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_97 = eq(_T_96, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_98 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_99 = eq(_T_98, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_100 = and(_T_97, _T_99) @[el2_dec_dec_ctl.scala 17:17] + node _T_101 = or(_T_95, _T_100) @[el2_dec_dec_ctl.scala 26:29] + node _T_102 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_104 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_105 = eq(_T_104, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_106 = and(_T_103, _T_105) @[el2_dec_dec_ctl.scala 17:17] + node _T_107 = or(_T_101, _T_106) @[el2_dec_dec_ctl.scala 26:51] + io.out.rs1 <= _T_107 @[el2_dec_dec_ctl.scala 21:14] + node _T_108 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_109 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_111 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_113 = and(_T_108, _T_110) @[el2_dec_dec_ctl.scala 17:17] + node _T_114 = and(_T_113, _T_112) @[el2_dec_dec_ctl.scala 17:17] + node _T_115 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_117 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_118 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_119 = eq(_T_118, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_120 = and(_T_116, _T_117) @[el2_dec_dec_ctl.scala 17:17] + node _T_121 = and(_T_120, _T_119) @[el2_dec_dec_ctl.scala 17:17] + node _T_122 = or(_T_114, _T_121) @[el2_dec_dec_ctl.scala 27:40] + io.out.rs2 <= _T_122 @[el2_dec_dec_ctl.scala 27:14] + node _T_123 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_125 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_127 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_128 = and(_T_124, _T_126) @[el2_dec_dec_ctl.scala 17:17] + node _T_129 = and(_T_128, _T_127) @[el2_dec_dec_ctl.scala 17:17] + node _T_130 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_131 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_133 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_134 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_135 = eq(_T_134, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_136 = and(_T_130, _T_132) @[el2_dec_dec_ctl.scala 17:17] + node _T_137 = and(_T_136, _T_133) @[el2_dec_dec_ctl.scala 17:17] + node _T_138 = and(_T_137, _T_135) @[el2_dec_dec_ctl.scala 17:17] + node _T_139 = or(_T_129, _T_138) @[el2_dec_dec_ctl.scala 28:42] + node _T_140 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_142 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_143 = eq(_T_142, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_144 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_145 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_146 = and(_T_141, _T_143) @[el2_dec_dec_ctl.scala 17:17] + node _T_147 = and(_T_146, _T_144) @[el2_dec_dec_ctl.scala 17:17] + node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 17:17] + node _T_149 = or(_T_139, _T_148) @[el2_dec_dec_ctl.scala 28:70] + node _T_150 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_152 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_154 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_155 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_156 = eq(_T_155, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_157 = and(_T_151, _T_153) @[el2_dec_dec_ctl.scala 17:17] + node _T_158 = and(_T_157, _T_154) @[el2_dec_dec_ctl.scala 17:17] + node _T_159 = and(_T_158, _T_156) @[el2_dec_dec_ctl.scala 17:17] + node _T_160 = or(_T_149, _T_159) @[el2_dec_dec_ctl.scala 29:32] + io.out.imm12 <= _T_160 @[el2_dec_dec_ctl.scala 28:16] + node _T_161 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 30:24] + node _T_162 = eq(_T_161, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 30:17] + node _T_163 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 30:37] + node _T_164 = eq(_T_163, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 30:30] + node _T_165 = and(_T_162, _T_164) @[el2_dec_dec_ctl.scala 30:28] + node _T_166 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 30:51] + node _T_167 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 30:63] + node _T_168 = and(_T_166, _T_167) @[el2_dec_dec_ctl.scala 30:55] + node _T_169 = or(_T_165, _T_168) @[el2_dec_dec_ctl.scala 30:42] + node _T_170 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 30:76] + node _T_171 = or(_T_169, _T_170) @[el2_dec_dec_ctl.scala 30:68] + io.out.rd <= _T_171 @[el2_dec_dec_ctl.scala 30:13] + node _T_172 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_173 = eq(_T_172, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_174 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_175 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_177 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_178 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_180 = and(_T_173, _T_174) @[el2_dec_dec_ctl.scala 17:17] + node _T_181 = and(_T_180, _T_176) @[el2_dec_dec_ctl.scala 17:17] + node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 17:17] + node _T_183 = and(_T_182, _T_179) @[el2_dec_dec_ctl.scala 17:17] + io.out.shimm5 <= _T_183 @[el2_dec_dec_ctl.scala 31:17] + node _T_184 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 32:26] + node _T_185 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 32:36] + node _T_186 = and(_T_184, _T_185) @[el2_dec_dec_ctl.scala 32:29] + node _T_187 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 32:50] + node _T_188 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 32:60] + node _T_189 = and(_T_187, _T_188) @[el2_dec_dec_ctl.scala 32:53] + node _T_190 = or(_T_186, _T_189) @[el2_dec_dec_ctl.scala 32:41] + io.out.imm20 <= _T_190 @[el2_dec_dec_ctl.scala 32:16] + node _T_191 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 33:24] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 33:17] + node _T_193 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 33:37] + node _T_194 = eq(_T_193, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 33:30] + node _T_195 = and(_T_192, _T_194) @[el2_dec_dec_ctl.scala 33:28] + node _T_196 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 33:49] + node _T_197 = and(_T_195, _T_196) @[el2_dec_dec_ctl.scala 33:41] + node _T_198 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 33:63] + node _T_199 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 33:75] + node _T_200 = and(_T_198, _T_199) @[el2_dec_dec_ctl.scala 33:67] + node _T_201 = or(_T_197, _T_200) @[el2_dec_dec_ctl.scala 33:54] + io.out.pc <= _T_201 @[el2_dec_dec_ctl.scala 33:13] + node _T_202 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_203 = eq(_T_202, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_204 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_206 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_208 = and(_T_203, _T_205) @[el2_dec_dec_ctl.scala 17:17] + node _T_209 = and(_T_208, _T_207) @[el2_dec_dec_ctl.scala 17:17] + io.out.load <= _T_209 @[el2_dec_dec_ctl.scala 34:15] + node _T_210 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_212 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_213 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_215 = and(_T_211, _T_212) @[el2_dec_dec_ctl.scala 17:17] + node _T_216 = and(_T_215, _T_214) @[el2_dec_dec_ctl.scala 17:17] + io.out.store <= _T_216 @[el2_dec_dec_ctl.scala 35:16] + node _T_217 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_218 = eq(_T_217, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_219 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_220 = eq(_T_219, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_221 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_222 = eq(_T_221, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_223 = and(_T_218, _T_220) @[el2_dec_dec_ctl.scala 17:17] + node _T_224 = and(_T_223, _T_222) @[el2_dec_dec_ctl.scala 17:17] + io.out.lsu <= _T_224 @[el2_dec_dec_ctl.scala 36:14] + node _T_225 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_227 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_229 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_231 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_232 = eq(_T_231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_233 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_234 = and(_T_226, _T_228) @[el2_dec_dec_ctl.scala 17:17] + node _T_235 = and(_T_234, _T_230) @[el2_dec_dec_ctl.scala 17:17] + node _T_236 = and(_T_235, _T_232) @[el2_dec_dec_ctl.scala 17:17] + node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 17:17] + node _T_238 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_240 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_242 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_243 = and(_T_239, _T_241) @[el2_dec_dec_ctl.scala 17:17] + node _T_244 = and(_T_243, _T_242) @[el2_dec_dec_ctl.scala 17:17] + node _T_245 = or(_T_237, _T_244) @[el2_dec_dec_ctl.scala 37:49] + node _T_246 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_247 = eq(_T_246, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_248 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_250 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_251 = eq(_T_250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_252 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_254 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_256 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_258 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_259 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_261 = and(_T_247, _T_249) @[el2_dec_dec_ctl.scala 17:17] + node _T_262 = and(_T_261, _T_251) @[el2_dec_dec_ctl.scala 17:17] + node _T_263 = and(_T_262, _T_253) @[el2_dec_dec_ctl.scala 17:17] + node _T_264 = and(_T_263, _T_255) @[el2_dec_dec_ctl.scala 17:17] + node _T_265 = and(_T_264, _T_257) @[el2_dec_dec_ctl.scala 17:17] + node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 17:17] + node _T_267 = and(_T_266, _T_260) @[el2_dec_dec_ctl.scala 17:17] + node _T_268 = or(_T_245, _T_267) @[el2_dec_dec_ctl.scala 37:74] + io.out.add <= _T_268 @[el2_dec_dec_ctl.scala 37:14] + node _T_269 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:34] + node _T_270 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_274 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_275 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_276 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_278 = and(_T_269, _T_271) @[el2_dec_dec_ctl.scala 17:17] + node _T_279 = and(_T_278, _T_273) @[el2_dec_dec_ctl.scala 17:17] + node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 17:17] + node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 17:17] + node _T_282 = and(_T_281, _T_277) @[el2_dec_dec_ctl.scala 17:17] + node _T_283 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_285 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_286 = eq(_T_285, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_287 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_288 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_290 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_291 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_293 = and(_T_284, _T_286) @[el2_dec_dec_ctl.scala 17:17] + node _T_294 = and(_T_293, _T_287) @[el2_dec_dec_ctl.scala 17:17] + node _T_295 = and(_T_294, _T_289) @[el2_dec_dec_ctl.scala 17:17] + node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 17:17] + node _T_297 = and(_T_296, _T_292) @[el2_dec_dec_ctl.scala 17:17] + node _T_298 = or(_T_282, _T_297) @[el2_dec_dec_ctl.scala 39:49] + node _T_299 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_300 = eq(_T_299, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_301 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_302 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_304 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_305 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_307 = and(_T_300, _T_301) @[el2_dec_dec_ctl.scala 17:17] + node _T_308 = and(_T_307, _T_303) @[el2_dec_dec_ctl.scala 17:17] + node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 17:17] + node _T_310 = and(_T_309, _T_306) @[el2_dec_dec_ctl.scala 17:17] + node _T_311 = or(_T_298, _T_310) @[el2_dec_dec_ctl.scala 39:85] + node _T_312 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_313 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_315 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_316 = eq(_T_315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_317 = and(_T_312, _T_314) @[el2_dec_dec_ctl.scala 17:17] + node _T_318 = and(_T_317, _T_316) @[el2_dec_dec_ctl.scala 17:17] + node _T_319 = or(_T_311, _T_318) @[el2_dec_dec_ctl.scala 40:35] + io.out.sub <= _T_319 @[el2_dec_dec_ctl.scala 39:14] + node _T_320 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_321 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_322 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_323 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_324 = eq(_T_323, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_325 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_326 = eq(_T_325, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_327 = and(_T_320, _T_321) @[el2_dec_dec_ctl.scala 17:17] + node _T_328 = and(_T_327, _T_322) @[el2_dec_dec_ctl.scala 17:17] + node _T_329 = and(_T_328, _T_324) @[el2_dec_dec_ctl.scala 17:17] + node _T_330 = and(_T_329, _T_326) @[el2_dec_dec_ctl.scala 17:17] + node _T_331 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_332 = eq(_T_331, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_333 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_334 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_335 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_336 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_337 = eq(_T_336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_338 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_340 = and(_T_332, _T_333) @[el2_dec_dec_ctl.scala 17:17] + node _T_341 = and(_T_340, _T_334) @[el2_dec_dec_ctl.scala 17:17] + node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 17:17] + node _T_343 = and(_T_342, _T_337) @[el2_dec_dec_ctl.scala 17:17] + node _T_344 = and(_T_343, _T_339) @[el2_dec_dec_ctl.scala 17:17] + node _T_345 = or(_T_330, _T_344) @[el2_dec_dec_ctl.scala 41:48] + io.out.land <= _T_345 @[el2_dec_dec_ctl.scala 41:15] + node _T_346 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_347 = eq(_T_346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_348 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_349 = and(_T_347, _T_348) @[el2_dec_dec_ctl.scala 17:17] + node _T_350 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_351 = eq(_T_350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_352 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_353 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_354 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_356 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_358 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_360 = and(_T_351, _T_352) @[el2_dec_dec_ctl.scala 17:17] + node _T_361 = and(_T_360, _T_353) @[el2_dec_dec_ctl.scala 17:17] + node _T_362 = and(_T_361, _T_355) @[el2_dec_dec_ctl.scala 17:17] + node _T_363 = and(_T_362, _T_357) @[el2_dec_dec_ctl.scala 17:17] + node _T_364 = and(_T_363, _T_359) @[el2_dec_dec_ctl.scala 17:17] + node _T_365 = or(_T_349, _T_364) @[el2_dec_dec_ctl.scala 42:37] + node _T_366 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_367 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_368 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_369 = and(_T_366, _T_367) @[el2_dec_dec_ctl.scala 17:17] + node _T_370 = and(_T_369, _T_368) @[el2_dec_dec_ctl.scala 17:17] + node _T_371 = or(_T_365, _T_370) @[el2_dec_dec_ctl.scala 42:74] + node _T_372 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_374 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_376 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_377 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_378 = and(_T_373, _T_375) @[el2_dec_dec_ctl.scala 17:17] + node _T_379 = and(_T_378, _T_376) @[el2_dec_dec_ctl.scala 17:17] + node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 17:17] + node _T_381 = or(_T_371, _T_380) @[el2_dec_dec_ctl.scala 43:26] + node _T_382 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_383 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_384 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_385 = eq(_T_384, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_386 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_388 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_390 = and(_T_382, _T_383) @[el2_dec_dec_ctl.scala 17:17] + node _T_391 = and(_T_390, _T_385) @[el2_dec_dec_ctl.scala 17:17] + node _T_392 = and(_T_391, _T_387) @[el2_dec_dec_ctl.scala 17:17] + node _T_393 = and(_T_392, _T_389) @[el2_dec_dec_ctl.scala 17:17] + node _T_394 = or(_T_381, _T_393) @[el2_dec_dec_ctl.scala 43:55] + io.out.lor <= _T_394 @[el2_dec_dec_ctl.scala 42:14] + node _T_395 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_397 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_398 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_399 = eq(_T_398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_400 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_401 = eq(_T_400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_402 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_403 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_405 = and(_T_396, _T_397) @[el2_dec_dec_ctl.scala 17:17] + node _T_406 = and(_T_405, _T_399) @[el2_dec_dec_ctl.scala 17:17] + node _T_407 = and(_T_406, _T_401) @[el2_dec_dec_ctl.scala 17:17] + node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 17:17] + node _T_409 = and(_T_408, _T_404) @[el2_dec_dec_ctl.scala 17:17] + node _T_410 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_411 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_412 = eq(_T_411, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_413 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_414 = eq(_T_413, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_415 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_417 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_418 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_420 = and(_T_410, _T_412) @[el2_dec_dec_ctl.scala 17:17] + node _T_421 = and(_T_420, _T_414) @[el2_dec_dec_ctl.scala 17:17] + node _T_422 = and(_T_421, _T_416) @[el2_dec_dec_ctl.scala 17:17] + node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 17:17] + node _T_424 = and(_T_423, _T_419) @[el2_dec_dec_ctl.scala 17:17] + node _T_425 = or(_T_409, _T_424) @[el2_dec_dec_ctl.scala 45:53] + io.out.lxor <= _T_425 @[el2_dec_dec_ctl.scala 45:15] + node _T_426 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_428 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_430 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_431 = eq(_T_430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_432 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_433 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_434 = eq(_T_433, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_435 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_436 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_438 = and(_T_427, _T_429) @[el2_dec_dec_ctl.scala 17:17] + node _T_439 = and(_T_438, _T_431) @[el2_dec_dec_ctl.scala 17:17] + node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 17:17] + node _T_441 = and(_T_440, _T_434) @[el2_dec_dec_ctl.scala 17:17] + node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 17:17] + node _T_443 = and(_T_442, _T_437) @[el2_dec_dec_ctl.scala 17:17] + io.out.sll <= _T_443 @[el2_dec_dec_ctl.scala 46:14] + node _T_444 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:34] + node _T_445 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_447 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_448 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_449 = eq(_T_448, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_450 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_451 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_453 = and(_T_444, _T_446) @[el2_dec_dec_ctl.scala 17:17] + node _T_454 = and(_T_453, _T_447) @[el2_dec_dec_ctl.scala 17:17] + node _T_455 = and(_T_454, _T_449) @[el2_dec_dec_ctl.scala 17:17] + node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 17:17] + node _T_457 = and(_T_456, _T_452) @[el2_dec_dec_ctl.scala 17:17] + io.out.sra <= _T_457 @[el2_dec_dec_ctl.scala 47:14] + node _T_458 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_460 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_461 = eq(_T_460, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_462 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_463 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_464 = eq(_T_463, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_465 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_466 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_468 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_469 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_471 = and(_T_459, _T_461) @[el2_dec_dec_ctl.scala 17:17] + node _T_472 = and(_T_471, _T_462) @[el2_dec_dec_ctl.scala 17:17] + node _T_473 = and(_T_472, _T_464) @[el2_dec_dec_ctl.scala 17:17] + node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 17:17] + node _T_475 = and(_T_474, _T_467) @[el2_dec_dec_ctl.scala 17:17] + node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 17:17] + node _T_477 = and(_T_476, _T_470) @[el2_dec_dec_ctl.scala 17:17] + io.out.srl <= _T_477 @[el2_dec_dec_ctl.scala 48:14] + node _T_478 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_479 = eq(_T_478, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_480 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_482 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_483 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_485 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_486 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_487 = eq(_T_486, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_488 = and(_T_479, _T_481) @[el2_dec_dec_ctl.scala 17:17] + node _T_489 = and(_T_488, _T_482) @[el2_dec_dec_ctl.scala 17:17] + node _T_490 = and(_T_489, _T_484) @[el2_dec_dec_ctl.scala 17:17] + node _T_491 = and(_T_490, _T_485) @[el2_dec_dec_ctl.scala 17:17] + node _T_492 = and(_T_491, _T_487) @[el2_dec_dec_ctl.scala 17:17] + node _T_493 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_495 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_496 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_498 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_499 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_501 = and(_T_494, _T_495) @[el2_dec_dec_ctl.scala 17:17] + node _T_502 = and(_T_501, _T_497) @[el2_dec_dec_ctl.scala 17:17] + node _T_503 = and(_T_502, _T_498) @[el2_dec_dec_ctl.scala 17:17] + node _T_504 = and(_T_503, _T_500) @[el2_dec_dec_ctl.scala 17:17] + node _T_505 = or(_T_492, _T_504) @[el2_dec_dec_ctl.scala 49:51] + io.out.slt <= _T_505 @[el2_dec_dec_ctl.scala 49:14] + node _T_506 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_507 = eq(_T_506, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_508 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_509 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_510 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_511 = eq(_T_510, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_512 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_513 = eq(_T_512, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_514 = and(_T_507, _T_508) @[el2_dec_dec_ctl.scala 17:17] + node _T_515 = and(_T_514, _T_509) @[el2_dec_dec_ctl.scala 17:17] + node _T_516 = and(_T_515, _T_511) @[el2_dec_dec_ctl.scala 17:17] + node _T_517 = and(_T_516, _T_513) @[el2_dec_dec_ctl.scala 17:17] + node _T_518 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_519 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_520 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_522 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_523 = eq(_T_522, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_524 = and(_T_518, _T_519) @[el2_dec_dec_ctl.scala 17:17] + node _T_525 = and(_T_524, _T_521) @[el2_dec_dec_ctl.scala 17:17] + node _T_526 = and(_T_525, _T_523) @[el2_dec_dec_ctl.scala 17:17] + node _T_527 = or(_T_517, _T_526) @[el2_dec_dec_ctl.scala 50:51] + node _T_528 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_529 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_530 = eq(_T_529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_531 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_533 = and(_T_528, _T_530) @[el2_dec_dec_ctl.scala 17:17] + node _T_534 = and(_T_533, _T_532) @[el2_dec_dec_ctl.scala 17:17] + node _T_535 = or(_T_527, _T_534) @[el2_dec_dec_ctl.scala 50:79] + node _T_536 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_537 = eq(_T_536, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_538 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_540 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_541 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_542 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_543 = eq(_T_542, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_544 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_545 = eq(_T_544, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_546 = and(_T_537, _T_539) @[el2_dec_dec_ctl.scala 17:17] + node _T_547 = and(_T_546, _T_540) @[el2_dec_dec_ctl.scala 17:17] + node _T_548 = and(_T_547, _T_541) @[el2_dec_dec_ctl.scala 17:17] + node _T_549 = and(_T_548, _T_543) @[el2_dec_dec_ctl.scala 17:17] + node _T_550 = and(_T_549, _T_545) @[el2_dec_dec_ctl.scala 17:17] + node _T_551 = or(_T_535, _T_550) @[el2_dec_dec_ctl.scala 51:29] + node _T_552 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_553 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_554 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_555 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_557 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_558 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_560 = and(_T_552, _T_553) @[el2_dec_dec_ctl.scala 17:17] + node _T_561 = and(_T_560, _T_554) @[el2_dec_dec_ctl.scala 17:17] + node _T_562 = and(_T_561, _T_556) @[el2_dec_dec_ctl.scala 17:17] + node _T_563 = and(_T_562, _T_557) @[el2_dec_dec_ctl.scala 17:17] + node _T_564 = and(_T_563, _T_559) @[el2_dec_dec_ctl.scala 17:17] + node _T_565 = or(_T_551, _T_564) @[el2_dec_dec_ctl.scala 51:66] + io.out.unsign <= _T_565 @[el2_dec_dec_ctl.scala 50:17] + node _T_566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_567 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_569 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_570 = eq(_T_569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_571 = and(_T_566, _T_568) @[el2_dec_dec_ctl.scala 17:17] + node _T_572 = and(_T_571, _T_570) @[el2_dec_dec_ctl.scala 17:17] + io.out.condbr <= _T_572 @[el2_dec_dec_ctl.scala 53:17] + node _T_573 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_574 = eq(_T_573, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_575 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_576 = eq(_T_575, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_577 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_578 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_580 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_582 = and(_T_574, _T_576) @[el2_dec_dec_ctl.scala 17:17] + node _T_583 = and(_T_582, _T_577) @[el2_dec_dec_ctl.scala 17:17] + node _T_584 = and(_T_583, _T_579) @[el2_dec_dec_ctl.scala 17:17] + node _T_585 = and(_T_584, _T_581) @[el2_dec_dec_ctl.scala 17:17] + io.out.beq <= _T_585 @[el2_dec_dec_ctl.scala 54:14] + node _T_586 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_587 = eq(_T_586, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_588 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_589 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_590 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_591 = eq(_T_590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_592 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_593 = eq(_T_592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_594 = and(_T_587, _T_588) @[el2_dec_dec_ctl.scala 17:17] + node _T_595 = and(_T_594, _T_589) @[el2_dec_dec_ctl.scala 17:17] + node _T_596 = and(_T_595, _T_591) @[el2_dec_dec_ctl.scala 17:17] + node _T_597 = and(_T_596, _T_593) @[el2_dec_dec_ctl.scala 17:17] + io.out.bne <= _T_597 @[el2_dec_dec_ctl.scala 55:14] + node _T_598 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_599 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_600 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_601 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_603 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_605 = and(_T_598, _T_599) @[el2_dec_dec_ctl.scala 17:17] + node _T_606 = and(_T_605, _T_600) @[el2_dec_dec_ctl.scala 17:17] + node _T_607 = and(_T_606, _T_602) @[el2_dec_dec_ctl.scala 17:17] + node _T_608 = and(_T_607, _T_604) @[el2_dec_dec_ctl.scala 17:17] + io.out.bge <= _T_608 @[el2_dec_dec_ctl.scala 56:14] + node _T_609 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_610 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_611 = eq(_T_610, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_612 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_613 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_615 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_616 = eq(_T_615, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_617 = and(_T_609, _T_611) @[el2_dec_dec_ctl.scala 17:17] + node _T_618 = and(_T_617, _T_612) @[el2_dec_dec_ctl.scala 17:17] + node _T_619 = and(_T_618, _T_614) @[el2_dec_dec_ctl.scala 17:17] + node _T_620 = and(_T_619, _T_616) @[el2_dec_dec_ctl.scala 17:17] + io.out.blt <= _T_620 @[el2_dec_dec_ctl.scala 57:14] + node _T_621 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_622 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_623 = and(_T_621, _T_622) @[el2_dec_dec_ctl.scala 17:17] + io.out.jal <= _T_623 @[el2_dec_dec_ctl.scala 58:14] + node _T_624 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_626 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_628 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_629 = eq(_T_628, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_630 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_632 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_634 = and(_T_625, _T_627) @[el2_dec_dec_ctl.scala 17:17] + node _T_635 = and(_T_634, _T_629) @[el2_dec_dec_ctl.scala 17:17] + node _T_636 = and(_T_635, _T_631) @[el2_dec_dec_ctl.scala 17:17] + node _T_637 = and(_T_636, _T_633) @[el2_dec_dec_ctl.scala 17:17] + io.out.by <= _T_637 @[el2_dec_dec_ctl.scala 59:13] + node _T_638 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_639 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_641 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_642 = eq(_T_641, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_643 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_644 = eq(_T_643, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_645 = and(_T_638, _T_640) @[el2_dec_dec_ctl.scala 17:17] + node _T_646 = and(_T_645, _T_642) @[el2_dec_dec_ctl.scala 17:17] + node _T_647 = and(_T_646, _T_644) @[el2_dec_dec_ctl.scala 17:17] + io.out.half <= _T_647 @[el2_dec_dec_ctl.scala 60:15] + node _T_648 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_649 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_650 = eq(_T_649, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_651 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_652 = eq(_T_651, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_653 = and(_T_648, _T_650) @[el2_dec_dec_ctl.scala 17:17] + node _T_654 = and(_T_653, _T_652) @[el2_dec_dec_ctl.scala 17:17] + io.out.word <= _T_654 @[el2_dec_dec_ctl.scala 61:15] + node _T_655 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_656 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_657 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_658 = and(_T_655, _T_656) @[el2_dec_dec_ctl.scala 17:17] + node _T_659 = and(_T_658, _T_657) @[el2_dec_dec_ctl.scala 17:17] + node _T_660 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_661 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_662 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_663 = and(_T_660, _T_661) @[el2_dec_dec_ctl.scala 17:17] + node _T_664 = and(_T_663, _T_662) @[el2_dec_dec_ctl.scala 17:17] + node _T_665 = or(_T_659, _T_664) @[el2_dec_dec_ctl.scala 62:44] + node _T_666 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_668 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_669 = and(_T_666, _T_667) @[el2_dec_dec_ctl.scala 17:17] + node _T_670 = and(_T_669, _T_668) @[el2_dec_dec_ctl.scala 17:17] + node _T_671 = or(_T_665, _T_670) @[el2_dec_dec_ctl.scala 62:67] + node _T_672 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_673 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_674 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_675 = and(_T_672, _T_673) @[el2_dec_dec_ctl.scala 17:17] + node _T_676 = and(_T_675, _T_674) @[el2_dec_dec_ctl.scala 17:17] + node _T_677 = or(_T_671, _T_676) @[el2_dec_dec_ctl.scala 63:26] + node _T_678 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_679 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_680 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_681 = and(_T_678, _T_679) @[el2_dec_dec_ctl.scala 17:17] + node _T_682 = and(_T_681, _T_680) @[el2_dec_dec_ctl.scala 17:17] + node _T_683 = or(_T_677, _T_682) @[el2_dec_dec_ctl.scala 63:49] + node _T_684 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_685 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_686 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_687 = and(_T_684, _T_685) @[el2_dec_dec_ctl.scala 17:17] + node _T_688 = and(_T_687, _T_686) @[el2_dec_dec_ctl.scala 17:17] + node _T_689 = or(_T_683, _T_688) @[el2_dec_dec_ctl.scala 63:73] + io.out.csr_read <= _T_689 @[el2_dec_dec_ctl.scala 62:19] + node _T_690 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_691 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_692 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_693 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_694 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_695 = and(_T_690, _T_691) @[el2_dec_dec_ctl.scala 17:17] + node _T_696 = and(_T_695, _T_692) @[el2_dec_dec_ctl.scala 17:17] + node _T_697 = and(_T_696, _T_693) @[el2_dec_dec_ctl.scala 17:17] + node _T_698 = and(_T_697, _T_694) @[el2_dec_dec_ctl.scala 17:17] + node _T_699 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_700 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_701 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_702 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_703 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_704 = and(_T_699, _T_700) @[el2_dec_dec_ctl.scala 17:17] + node _T_705 = and(_T_704, _T_701) @[el2_dec_dec_ctl.scala 17:17] + node _T_706 = and(_T_705, _T_702) @[el2_dec_dec_ctl.scala 17:17] + node _T_707 = and(_T_706, _T_703) @[el2_dec_dec_ctl.scala 17:17] + node _T_708 = or(_T_698, _T_707) @[el2_dec_dec_ctl.scala 65:49] + node _T_709 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_710 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_711 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_712 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_713 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_714 = and(_T_709, _T_710) @[el2_dec_dec_ctl.scala 17:17] + node _T_715 = and(_T_714, _T_711) @[el2_dec_dec_ctl.scala 17:17] + node _T_716 = and(_T_715, _T_712) @[el2_dec_dec_ctl.scala 17:17] + node _T_717 = and(_T_716, _T_713) @[el2_dec_dec_ctl.scala 17:17] + node _T_718 = or(_T_708, _T_717) @[el2_dec_dec_ctl.scala 65:79] + node _T_719 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_720 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_721 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_722 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_723 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_724 = and(_T_719, _T_720) @[el2_dec_dec_ctl.scala 17:17] + node _T_725 = and(_T_724, _T_721) @[el2_dec_dec_ctl.scala 17:17] + node _T_726 = and(_T_725, _T_722) @[el2_dec_dec_ctl.scala 17:17] + node _T_727 = and(_T_726, _T_723) @[el2_dec_dec_ctl.scala 17:17] + node _T_728 = or(_T_718, _T_727) @[el2_dec_dec_ctl.scala 66:33] + node _T_729 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_730 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_731 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_732 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_733 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_734 = and(_T_729, _T_730) @[el2_dec_dec_ctl.scala 17:17] + node _T_735 = and(_T_734, _T_731) @[el2_dec_dec_ctl.scala 17:17] + node _T_736 = and(_T_735, _T_732) @[el2_dec_dec_ctl.scala 17:17] + node _T_737 = and(_T_736, _T_733) @[el2_dec_dec_ctl.scala 17:17] + node _T_738 = or(_T_728, _T_737) @[el2_dec_dec_ctl.scala 66:63] + io.out.csr_clr <= _T_738 @[el2_dec_dec_ctl.scala 65:18] + node _T_739 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_740 = eq(_T_739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_741 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_742 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_743 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_744 = and(_T_740, _T_741) @[el2_dec_dec_ctl.scala 17:17] + node _T_745 = and(_T_744, _T_742) @[el2_dec_dec_ctl.scala 17:17] + node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 17:17] + io.out.csr_write <= _T_746 @[el2_dec_dec_ctl.scala 68:20] + node _T_747 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_748 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_749 = eq(_T_748, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_750 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_751 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_752 = and(_T_747, _T_749) @[el2_dec_dec_ctl.scala 17:17] + node _T_753 = and(_T_752, _T_750) @[el2_dec_dec_ctl.scala 17:17] + node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 17:17] + node _T_755 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_756 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_757 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_758 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_759 = and(_T_755, _T_756) @[el2_dec_dec_ctl.scala 17:17] + node _T_760 = and(_T_759, _T_757) @[el2_dec_dec_ctl.scala 17:17] + node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 17:17] + node _T_762 = or(_T_754, _T_761) @[el2_dec_dec_ctl.scala 69:47] + node _T_763 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_764 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_765 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_766 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_767 = and(_T_763, _T_764) @[el2_dec_dec_ctl.scala 17:17] + node _T_768 = and(_T_767, _T_765) @[el2_dec_dec_ctl.scala 17:17] + node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 17:17] + node _T_770 = or(_T_762, _T_769) @[el2_dec_dec_ctl.scala 69:74] + node _T_771 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_772 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_773 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_774 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_775 = and(_T_771, _T_772) @[el2_dec_dec_ctl.scala 17:17] + node _T_776 = and(_T_775, _T_773) @[el2_dec_dec_ctl.scala 17:17] + node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 17:17] + node _T_778 = or(_T_770, _T_777) @[el2_dec_dec_ctl.scala 70:30] + node _T_779 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_780 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_781 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_782 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_783 = and(_T_779, _T_780) @[el2_dec_dec_ctl.scala 17:17] + node _T_784 = and(_T_783, _T_781) @[el2_dec_dec_ctl.scala 17:17] + node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 17:17] + node _T_786 = or(_T_778, _T_785) @[el2_dec_dec_ctl.scala 70:57] + node _T_787 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_788 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_789 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_790 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_791 = and(_T_787, _T_788) @[el2_dec_dec_ctl.scala 17:17] + node _T_792 = and(_T_791, _T_789) @[el2_dec_dec_ctl.scala 17:17] + node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 17:17] + node _T_794 = or(_T_786, _T_793) @[el2_dec_dec_ctl.scala 71:30] + io.out.csr_imm <= _T_794 @[el2_dec_dec_ctl.scala 69:18] + node _T_795 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_796 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_798 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_799 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_800 = and(_T_795, _T_797) @[el2_dec_dec_ctl.scala 17:17] + node _T_801 = and(_T_800, _T_798) @[el2_dec_dec_ctl.scala 17:17] + node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 17:17] + node _T_803 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_804 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_805 = eq(_T_804, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_806 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_807 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_808 = and(_T_803, _T_805) @[el2_dec_dec_ctl.scala 17:17] + node _T_809 = and(_T_808, _T_806) @[el2_dec_dec_ctl.scala 17:17] + node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 17:17] + node _T_811 = or(_T_802, _T_810) @[el2_dec_dec_ctl.scala 72:47] + node _T_812 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_813 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_814 = eq(_T_813, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_815 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_816 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_817 = and(_T_812, _T_814) @[el2_dec_dec_ctl.scala 17:17] + node _T_818 = and(_T_817, _T_815) @[el2_dec_dec_ctl.scala 17:17] + node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 17:17] + node _T_820 = or(_T_811, _T_819) @[el2_dec_dec_ctl.scala 72:75] + node _T_821 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_822 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_823 = eq(_T_822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_824 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_825 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_826 = and(_T_821, _T_823) @[el2_dec_dec_ctl.scala 17:17] + node _T_827 = and(_T_826, _T_824) @[el2_dec_dec_ctl.scala 17:17] + node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 17:17] + node _T_829 = or(_T_820, _T_828) @[el2_dec_dec_ctl.scala 73:31] + node _T_830 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_831 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_832 = eq(_T_831, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_833 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_834 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_835 = and(_T_830, _T_832) @[el2_dec_dec_ctl.scala 17:17] + node _T_836 = and(_T_835, _T_833) @[el2_dec_dec_ctl.scala 17:17] + node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 17:17] + node _T_838 = or(_T_829, _T_837) @[el2_dec_dec_ctl.scala 73:59] + io.out.csr_set <= _T_838 @[el2_dec_dec_ctl.scala 72:18] + node _T_839 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_840 = eq(_T_839, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_841 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:34] + node _T_842 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_843 = eq(_T_842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_844 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_845 = eq(_T_844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_846 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_847 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_848 = and(_T_840, _T_841) @[el2_dec_dec_ctl.scala 17:17] + node _T_849 = and(_T_848, _T_843) @[el2_dec_dec_ctl.scala 17:17] + node _T_850 = and(_T_849, _T_845) @[el2_dec_dec_ctl.scala 17:17] + node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 17:17] + node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 17:17] + io.out.ebreak <= _T_852 @[el2_dec_dec_ctl.scala 75:17] + node _T_853 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_854 = eq(_T_853, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_855 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53] + node _T_856 = eq(_T_855, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_857 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_859 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_861 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_862 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_863 = and(_T_854, _T_856) @[el2_dec_dec_ctl.scala 17:17] + node _T_864 = and(_T_863, _T_858) @[el2_dec_dec_ctl.scala 17:17] + node _T_865 = and(_T_864, _T_860) @[el2_dec_dec_ctl.scala 17:17] + node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 17:17] + node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 17:17] + io.out.ecall <= _T_867 @[el2_dec_dec_ctl.scala 76:16] + node _T_868 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:34] + node _T_869 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_870 = eq(_T_869, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_871 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_872 = eq(_T_871, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_873 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_874 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_875 = and(_T_868, _T_870) @[el2_dec_dec_ctl.scala 17:17] + node _T_876 = and(_T_875, _T_872) @[el2_dec_dec_ctl.scala 17:17] + node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 17:17] + node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 17:17] + io.out.mret <= _T_878 @[el2_dec_dec_ctl.scala 77:15] + node _T_879 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_880 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_881 = eq(_T_880, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_882 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_883 = eq(_T_882, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_884 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_885 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_886 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_887 = eq(_T_886, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_888 = and(_T_879, _T_881) @[el2_dec_dec_ctl.scala 17:17] + node _T_889 = and(_T_888, _T_883) @[el2_dec_dec_ctl.scala 17:17] + node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 17:17] + node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 17:17] + node _T_892 = and(_T_891, _T_887) @[el2_dec_dec_ctl.scala 17:17] + io.out.mul <= _T_892 @[el2_dec_dec_ctl.scala 78:14] + node _T_893 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_894 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_896 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_897 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_898 = eq(_T_897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_899 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_900 = eq(_T_899, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_901 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_902 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_903 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_904 = eq(_T_903, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_905 = and(_T_893, _T_895) @[el2_dec_dec_ctl.scala 17:17] + node _T_906 = and(_T_905, _T_896) @[el2_dec_dec_ctl.scala 17:17] + node _T_907 = and(_T_906, _T_898) @[el2_dec_dec_ctl.scala 17:17] + node _T_908 = and(_T_907, _T_900) @[el2_dec_dec_ctl.scala 17:17] + node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 17:17] + node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 17:17] + node _T_911 = and(_T_910, _T_904) @[el2_dec_dec_ctl.scala 17:17] + node _T_912 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_913 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_914 = eq(_T_913, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_915 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_917 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_918 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_919 = eq(_T_918, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_920 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_921 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_922 = eq(_T_921, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_923 = and(_T_912, _T_914) @[el2_dec_dec_ctl.scala 17:17] + node _T_924 = and(_T_923, _T_916) @[el2_dec_dec_ctl.scala 17:17] + node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 17:17] + node _T_926 = and(_T_925, _T_919) @[el2_dec_dec_ctl.scala 17:17] + node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 17:17] + node _T_928 = and(_T_927, _T_922) @[el2_dec_dec_ctl.scala 17:17] + node _T_929 = or(_T_911, _T_928) @[el2_dec_dec_ctl.scala 79:61] + io.out.rs1_sign <= _T_929 @[el2_dec_dec_ctl.scala 79:19] + node _T_930 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_931 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_932 = eq(_T_931, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_933 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_934 = eq(_T_933, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_935 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_936 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_937 = eq(_T_936, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_938 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_939 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_941 = and(_T_930, _T_932) @[el2_dec_dec_ctl.scala 17:17] + node _T_942 = and(_T_941, _T_934) @[el2_dec_dec_ctl.scala 17:17] + node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 17:17] + node _T_944 = and(_T_943, _T_937) @[el2_dec_dec_ctl.scala 17:17] + node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 17:17] + node _T_946 = and(_T_945, _T_940) @[el2_dec_dec_ctl.scala 17:17] + io.out.rs2_sign <= _T_946 @[el2_dec_dec_ctl.scala 81:19] + node _T_947 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_948 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_950 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_952 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_953 = eq(_T_952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_954 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_955 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_956 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_957 = eq(_T_956, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_958 = and(_T_947, _T_949) @[el2_dec_dec_ctl.scala 17:17] + node _T_959 = and(_T_958, _T_951) @[el2_dec_dec_ctl.scala 17:17] + node _T_960 = and(_T_959, _T_953) @[el2_dec_dec_ctl.scala 17:17] + node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 17:17] + node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 17:17] + node _T_963 = and(_T_962, _T_957) @[el2_dec_dec_ctl.scala 17:17] + io.out.low <= _T_963 @[el2_dec_dec_ctl.scala 82:14] + node _T_964 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_965 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_966 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_967 = eq(_T_966, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_968 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_969 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_970 = eq(_T_969, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_971 = and(_T_964, _T_965) @[el2_dec_dec_ctl.scala 17:17] + node _T_972 = and(_T_971, _T_967) @[el2_dec_dec_ctl.scala 17:17] + node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 17:17] + node _T_974 = and(_T_973, _T_970) @[el2_dec_dec_ctl.scala 17:17] + io.out.div <= _T_974 @[el2_dec_dec_ctl.scala 83:14] + node _T_975 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:34] + node _T_976 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_977 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_978 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_979 = eq(_T_978, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_980 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_981 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_983 = and(_T_975, _T_976) @[el2_dec_dec_ctl.scala 17:17] + node _T_984 = and(_T_983, _T_977) @[el2_dec_dec_ctl.scala 17:17] + node _T_985 = and(_T_984, _T_979) @[el2_dec_dec_ctl.scala 17:17] + node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 17:17] + node _T_987 = and(_T_986, _T_982) @[el2_dec_dec_ctl.scala 17:17] + io.out.rem <= _T_987 @[el2_dec_dec_ctl.scala 84:14] + node _T_988 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_989 = eq(_T_988, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_990 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_991 = and(_T_989, _T_990) @[el2_dec_dec_ctl.scala 17:17] + io.out.fence <= _T_991 @[el2_dec_dec_ctl.scala 85:16] + node _T_992 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_993 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_995 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_996 = and(_T_992, _T_994) @[el2_dec_dec_ctl.scala 17:17] + node _T_997 = and(_T_996, _T_995) @[el2_dec_dec_ctl.scala 17:17] + io.out.fence_i <= _T_997 @[el2_dec_dec_ctl.scala 86:18] + node _T_998 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34] + node _T_999 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:34] + node _T_1000 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1001 = eq(_T_1000, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1002 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1003 = eq(_T_1002, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1004 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1005 = and(_T_998, _T_999) @[el2_dec_dec_ctl.scala 17:17] + node _T_1006 = and(_T_1005, _T_1001) @[el2_dec_dec_ctl.scala 17:17] + node _T_1007 = and(_T_1006, _T_1003) @[el2_dec_dec_ctl.scala 17:17] + node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 17:17] + node _T_1009 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1010 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1011 = and(_T_1009, _T_1010) @[el2_dec_dec_ctl.scala 17:17] + node _T_1012 = or(_T_1008, _T_1011) @[el2_dec_dec_ctl.scala 87:51] + node _T_1013 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1015 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1016 = eq(_T_1015, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1017 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1018 = and(_T_1014, _T_1016) @[el2_dec_dec_ctl.scala 17:17] + node _T_1019 = and(_T_1018, _T_1017) @[el2_dec_dec_ctl.scala 17:17] + node _T_1020 = or(_T_1012, _T_1019) @[el2_dec_dec_ctl.scala 87:72] + node _T_1021 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1022 = eq(_T_1021, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1023 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1024 = and(_T_1022, _T_1023) @[el2_dec_dec_ctl.scala 17:17] + node _T_1025 = or(_T_1020, _T_1024) @[el2_dec_dec_ctl.scala 88:29] + io.out.pm_alu <= _T_1025 @[el2_dec_dec_ctl.scala 87:17] + node _T_1026 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1028 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1029 = and(_T_1027, _T_1028) @[el2_dec_dec_ctl.scala 17:17] + node _T_1030 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1032 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_1033 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1034 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1035 = and(_T_1031, _T_1032) @[el2_dec_dec_ctl.scala 17:17] + node _T_1036 = and(_T_1035, _T_1033) @[el2_dec_dec_ctl.scala 17:17] + node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 17:17] + node _T_1038 = or(_T_1029, _T_1037) @[el2_dec_dec_ctl.scala 89:41] + node _T_1039 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1040 = eq(_T_1039, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1041 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_1042 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1043 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1044 = and(_T_1040, _T_1041) @[el2_dec_dec_ctl.scala 17:17] + node _T_1045 = and(_T_1044, _T_1042) @[el2_dec_dec_ctl.scala 17:17] + node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 17:17] + node _T_1047 = or(_T_1038, _T_1046) @[el2_dec_dec_ctl.scala 89:68] + node _T_1048 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1049 = eq(_T_1048, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1050 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_1051 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1052 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1053 = and(_T_1049, _T_1050) @[el2_dec_dec_ctl.scala 17:17] + node _T_1054 = and(_T_1053, _T_1051) @[el2_dec_dec_ctl.scala 17:17] + node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 17:17] + node _T_1056 = or(_T_1047, _T_1055) @[el2_dec_dec_ctl.scala 90:30] + node _T_1057 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1058 = eq(_T_1057, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1059 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_1060 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1061 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1062 = and(_T_1058, _T_1059) @[el2_dec_dec_ctl.scala 17:17] + node _T_1063 = and(_T_1062, _T_1060) @[el2_dec_dec_ctl.scala 17:17] + node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 17:17] + node _T_1065 = or(_T_1056, _T_1064) @[el2_dec_dec_ctl.scala 90:57] + node _T_1066 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1067 = eq(_T_1066, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1068 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_1069 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1070 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1071 = and(_T_1067, _T_1068) @[el2_dec_dec_ctl.scala 17:17] + node _T_1072 = and(_T_1071, _T_1069) @[el2_dec_dec_ctl.scala 17:17] + node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 17:17] + node _T_1074 = or(_T_1065, _T_1073) @[el2_dec_dec_ctl.scala 91:31] + node _T_1075 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1077 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1078 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1079 = and(_T_1075, _T_1076) @[el2_dec_dec_ctl.scala 17:17] + node _T_1080 = and(_T_1079, _T_1077) @[el2_dec_dec_ctl.scala 17:17] + node _T_1081 = and(_T_1080, _T_1078) @[el2_dec_dec_ctl.scala 17:17] + node _T_1082 = or(_T_1074, _T_1081) @[el2_dec_dec_ctl.scala 91:59] + node _T_1083 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_1084 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1085 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1086 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1087 = and(_T_1083, _T_1084) @[el2_dec_dec_ctl.scala 17:17] + node _T_1088 = and(_T_1087, _T_1085) @[el2_dec_dec_ctl.scala 17:17] + node _T_1089 = and(_T_1088, _T_1086) @[el2_dec_dec_ctl.scala 17:17] + node _T_1090 = or(_T_1082, _T_1089) @[el2_dec_dec_ctl.scala 92:30] + node _T_1091 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_1092 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1093 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1094 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1095 = and(_T_1091, _T_1092) @[el2_dec_dec_ctl.scala 17:17] + node _T_1096 = and(_T_1095, _T_1093) @[el2_dec_dec_ctl.scala 17:17] + node _T_1097 = and(_T_1096, _T_1094) @[el2_dec_dec_ctl.scala 17:17] + node _T_1098 = or(_T_1090, _T_1097) @[el2_dec_dec_ctl.scala 92:57] + node _T_1099 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_1100 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1101 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1102 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1103 = and(_T_1099, _T_1100) @[el2_dec_dec_ctl.scala 17:17] + node _T_1104 = and(_T_1103, _T_1101) @[el2_dec_dec_ctl.scala 17:17] + node _T_1105 = and(_T_1104, _T_1102) @[el2_dec_dec_ctl.scala 17:17] + node _T_1106 = or(_T_1098, _T_1105) @[el2_dec_dec_ctl.scala 93:30] + node _T_1107 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_1108 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1109 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1111 = and(_T_1107, _T_1108) @[el2_dec_dec_ctl.scala 17:17] + node _T_1112 = and(_T_1111, _T_1109) @[el2_dec_dec_ctl.scala 17:17] + node _T_1113 = and(_T_1112, _T_1110) @[el2_dec_dec_ctl.scala 17:17] + node _T_1114 = or(_T_1106, _T_1113) @[el2_dec_dec_ctl.scala 93:57] + io.out.presync <= _T_1114 @[el2_dec_dec_ctl.scala 89:18] + node _T_1115 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_1116 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1118 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1119 = and(_T_1115, _T_1117) @[el2_dec_dec_ctl.scala 17:17] + node _T_1120 = and(_T_1119, _T_1118) @[el2_dec_dec_ctl.scala 17:17] + node _T_1121 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1122 = eq(_T_1121, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1123 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1126 = eq(_T_1125, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1127 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1128 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1129 = and(_T_1122, _T_1124) @[el2_dec_dec_ctl.scala 17:17] + node _T_1130 = and(_T_1129, _T_1126) @[el2_dec_dec_ctl.scala 17:17] + node _T_1131 = and(_T_1130, _T_1127) @[el2_dec_dec_ctl.scala 17:17] + node _T_1132 = and(_T_1131, _T_1128) @[el2_dec_dec_ctl.scala 17:17] + node _T_1133 = or(_T_1120, _T_1132) @[el2_dec_dec_ctl.scala 95:45] + node _T_1134 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1135 = eq(_T_1134, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1136 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:34] + node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1139 = and(_T_1135, _T_1136) @[el2_dec_dec_ctl.scala 17:17] + node _T_1140 = and(_T_1139, _T_1137) @[el2_dec_dec_ctl.scala 17:17] + node _T_1141 = and(_T_1140, _T_1138) @[el2_dec_dec_ctl.scala 17:17] + node _T_1142 = or(_T_1133, _T_1141) @[el2_dec_dec_ctl.scala 95:78] + node _T_1143 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1144 = eq(_T_1143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1145 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:34] + node _T_1146 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1147 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1148 = and(_T_1144, _T_1145) @[el2_dec_dec_ctl.scala 17:17] + node _T_1149 = and(_T_1148, _T_1146) @[el2_dec_dec_ctl.scala 17:17] + node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 17:17] + node _T_1151 = or(_T_1142, _T_1150) @[el2_dec_dec_ctl.scala 96:30] + node _T_1152 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1153 = eq(_T_1152, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1154 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:34] + node _T_1155 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1156 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1157 = and(_T_1153, _T_1154) @[el2_dec_dec_ctl.scala 17:17] + node _T_1158 = and(_T_1157, _T_1155) @[el2_dec_dec_ctl.scala 17:17] + node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 17:17] + node _T_1160 = or(_T_1151, _T_1159) @[el2_dec_dec_ctl.scala 96:57] + node _T_1161 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1162 = eq(_T_1161, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1163 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:34] + node _T_1164 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1165 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1166 = and(_T_1162, _T_1163) @[el2_dec_dec_ctl.scala 17:17] + node _T_1167 = and(_T_1166, _T_1164) @[el2_dec_dec_ctl.scala 17:17] + node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 17:17] + node _T_1169 = or(_T_1160, _T_1168) @[el2_dec_dec_ctl.scala 97:30] + node _T_1170 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1172 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:34] + node _T_1173 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1174 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1175 = and(_T_1171, _T_1172) @[el2_dec_dec_ctl.scala 17:17] + node _T_1176 = and(_T_1175, _T_1173) @[el2_dec_dec_ctl.scala 17:17] + node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 17:17] + node _T_1178 = or(_T_1169, _T_1177) @[el2_dec_dec_ctl.scala 97:58] + node _T_1179 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:34] + node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1181 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1182 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1183 = and(_T_1179, _T_1180) @[el2_dec_dec_ctl.scala 17:17] + node _T_1184 = and(_T_1183, _T_1181) @[el2_dec_dec_ctl.scala 17:17] + node _T_1185 = and(_T_1184, _T_1182) @[el2_dec_dec_ctl.scala 17:17] + node _T_1186 = or(_T_1178, _T_1185) @[el2_dec_dec_ctl.scala 98:31] + node _T_1187 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:34] + node _T_1188 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1189 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1190 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1191 = and(_T_1187, _T_1188) @[el2_dec_dec_ctl.scala 17:17] + node _T_1192 = and(_T_1191, _T_1189) @[el2_dec_dec_ctl.scala 17:17] + node _T_1193 = and(_T_1192, _T_1190) @[el2_dec_dec_ctl.scala 17:17] + node _T_1194 = or(_T_1186, _T_1193) @[el2_dec_dec_ctl.scala 98:58] + node _T_1195 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:34] + node _T_1196 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1197 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1198 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1199 = and(_T_1195, _T_1196) @[el2_dec_dec_ctl.scala 17:17] + node _T_1200 = and(_T_1199, _T_1197) @[el2_dec_dec_ctl.scala 17:17] + node _T_1201 = and(_T_1200, _T_1198) @[el2_dec_dec_ctl.scala 17:17] + node _T_1202 = or(_T_1194, _T_1201) @[el2_dec_dec_ctl.scala 99:30] + node _T_1203 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:34] + node _T_1204 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1205 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1206 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1207 = and(_T_1203, _T_1204) @[el2_dec_dec_ctl.scala 17:17] + node _T_1208 = and(_T_1207, _T_1205) @[el2_dec_dec_ctl.scala 17:17] + node _T_1209 = and(_T_1208, _T_1206) @[el2_dec_dec_ctl.scala 17:17] + node _T_1210 = or(_T_1202, _T_1209) @[el2_dec_dec_ctl.scala 99:57] + node _T_1211 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:34] + node _T_1212 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1213 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1215 = and(_T_1211, _T_1212) @[el2_dec_dec_ctl.scala 17:17] + node _T_1216 = and(_T_1215, _T_1213) @[el2_dec_dec_ctl.scala 17:17] + node _T_1217 = and(_T_1216, _T_1214) @[el2_dec_dec_ctl.scala 17:17] + node _T_1218 = or(_T_1210, _T_1217) @[el2_dec_dec_ctl.scala 100:30] + io.out.postsync <= _T_1218 @[el2_dec_dec_ctl.scala 95:19] + node _T_1219 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1220 = eq(_T_1219, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1221 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1222 = eq(_T_1221, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1223 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:34] + node _T_1224 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34] + node _T_1225 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1226 = eq(_T_1225, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1227 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1228 = eq(_T_1227, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1229 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1231 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1233 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1234 = eq(_T_1233, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1235 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1237 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:34] + node _T_1238 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53] + node _T_1239 = eq(_T_1238, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1240 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1241 = eq(_T_1240, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1242 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1243 = eq(_T_1242, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1244 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1245 = eq(_T_1244, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1246 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1247 = eq(_T_1246, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1248 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1250 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1252 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1254 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1256 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1258 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1260 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1262 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1263 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1264 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1265 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1266 = eq(_T_1265, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1267 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1268 = eq(_T_1267, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1269 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1270 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1271 = and(_T_1220, _T_1222) @[el2_dec_dec_ctl.scala 17:17] + node _T_1272 = and(_T_1271, _T_1223) @[el2_dec_dec_ctl.scala 17:17] + node _T_1273 = and(_T_1272, _T_1224) @[el2_dec_dec_ctl.scala 17:17] + node _T_1274 = and(_T_1273, _T_1226) @[el2_dec_dec_ctl.scala 17:17] + node _T_1275 = and(_T_1274, _T_1228) @[el2_dec_dec_ctl.scala 17:17] + node _T_1276 = and(_T_1275, _T_1230) @[el2_dec_dec_ctl.scala 17:17] + node _T_1277 = and(_T_1276, _T_1232) @[el2_dec_dec_ctl.scala 17:17] + node _T_1278 = and(_T_1277, _T_1234) @[el2_dec_dec_ctl.scala 17:17] + node _T_1279 = and(_T_1278, _T_1236) @[el2_dec_dec_ctl.scala 17:17] + node _T_1280 = and(_T_1279, _T_1237) @[el2_dec_dec_ctl.scala 17:17] + node _T_1281 = and(_T_1280, _T_1239) @[el2_dec_dec_ctl.scala 17:17] + node _T_1282 = and(_T_1281, _T_1241) @[el2_dec_dec_ctl.scala 17:17] + node _T_1283 = and(_T_1282, _T_1243) @[el2_dec_dec_ctl.scala 17:17] + node _T_1284 = and(_T_1283, _T_1245) @[el2_dec_dec_ctl.scala 17:17] + node _T_1285 = and(_T_1284, _T_1247) @[el2_dec_dec_ctl.scala 17:17] + node _T_1286 = and(_T_1285, _T_1249) @[el2_dec_dec_ctl.scala 17:17] + node _T_1287 = and(_T_1286, _T_1251) @[el2_dec_dec_ctl.scala 17:17] + node _T_1288 = and(_T_1287, _T_1253) @[el2_dec_dec_ctl.scala 17:17] + node _T_1289 = and(_T_1288, _T_1255) @[el2_dec_dec_ctl.scala 17:17] + node _T_1290 = and(_T_1289, _T_1257) @[el2_dec_dec_ctl.scala 17:17] + node _T_1291 = and(_T_1290, _T_1259) @[el2_dec_dec_ctl.scala 17:17] + node _T_1292 = and(_T_1291, _T_1261) @[el2_dec_dec_ctl.scala 17:17] + node _T_1293 = and(_T_1292, _T_1262) @[el2_dec_dec_ctl.scala 17:17] + node _T_1294 = and(_T_1293, _T_1263) @[el2_dec_dec_ctl.scala 17:17] + node _T_1295 = and(_T_1294, _T_1264) @[el2_dec_dec_ctl.scala 17:17] + node _T_1296 = and(_T_1295, _T_1266) @[el2_dec_dec_ctl.scala 17:17] + node _T_1297 = and(_T_1296, _T_1268) @[el2_dec_dec_ctl.scala 17:17] + node _T_1298 = and(_T_1297, _T_1269) @[el2_dec_dec_ctl.scala 17:17] + node _T_1299 = and(_T_1298, _T_1270) @[el2_dec_dec_ctl.scala 17:17] + node _T_1300 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1302 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1304 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1306 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:34] + node _T_1307 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1309 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1310 = eq(_T_1309, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1311 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1313 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1315 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1317 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:34] + node _T_1318 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1320 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:34] + node _T_1321 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1322 = eq(_T_1321, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1323 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1324 = eq(_T_1323, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1325 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1326 = eq(_T_1325, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1327 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1329 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1331 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1332 = eq(_T_1331, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1333 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1334 = eq(_T_1333, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1335 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1336 = eq(_T_1335, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1337 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1338 = eq(_T_1337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1339 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1340 = eq(_T_1339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1341 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1342 = eq(_T_1341, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1343 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1344 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1345 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1346 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1348 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1350 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1351 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1352 = and(_T_1301, _T_1303) @[el2_dec_dec_ctl.scala 17:17] + node _T_1353 = and(_T_1352, _T_1305) @[el2_dec_dec_ctl.scala 17:17] + node _T_1354 = and(_T_1353, _T_1306) @[el2_dec_dec_ctl.scala 17:17] + node _T_1355 = and(_T_1354, _T_1308) @[el2_dec_dec_ctl.scala 17:17] + node _T_1356 = and(_T_1355, _T_1310) @[el2_dec_dec_ctl.scala 17:17] + node _T_1357 = and(_T_1356, _T_1312) @[el2_dec_dec_ctl.scala 17:17] + node _T_1358 = and(_T_1357, _T_1314) @[el2_dec_dec_ctl.scala 17:17] + node _T_1359 = and(_T_1358, _T_1316) @[el2_dec_dec_ctl.scala 17:17] + node _T_1360 = and(_T_1359, _T_1317) @[el2_dec_dec_ctl.scala 17:17] + node _T_1361 = and(_T_1360, _T_1319) @[el2_dec_dec_ctl.scala 17:17] + node _T_1362 = and(_T_1361, _T_1320) @[el2_dec_dec_ctl.scala 17:17] + node _T_1363 = and(_T_1362, _T_1322) @[el2_dec_dec_ctl.scala 17:17] + node _T_1364 = and(_T_1363, _T_1324) @[el2_dec_dec_ctl.scala 17:17] + node _T_1365 = and(_T_1364, _T_1326) @[el2_dec_dec_ctl.scala 17:17] + node _T_1366 = and(_T_1365, _T_1328) @[el2_dec_dec_ctl.scala 17:17] + node _T_1367 = and(_T_1366, _T_1330) @[el2_dec_dec_ctl.scala 17:17] + node _T_1368 = and(_T_1367, _T_1332) @[el2_dec_dec_ctl.scala 17:17] + node _T_1369 = and(_T_1368, _T_1334) @[el2_dec_dec_ctl.scala 17:17] + node _T_1370 = and(_T_1369, _T_1336) @[el2_dec_dec_ctl.scala 17:17] + node _T_1371 = and(_T_1370, _T_1338) @[el2_dec_dec_ctl.scala 17:17] + node _T_1372 = and(_T_1371, _T_1340) @[el2_dec_dec_ctl.scala 17:17] + node _T_1373 = and(_T_1372, _T_1342) @[el2_dec_dec_ctl.scala 17:17] + node _T_1374 = and(_T_1373, _T_1343) @[el2_dec_dec_ctl.scala 17:17] + node _T_1375 = and(_T_1374, _T_1344) @[el2_dec_dec_ctl.scala 17:17] + node _T_1376 = and(_T_1375, _T_1345) @[el2_dec_dec_ctl.scala 17:17] + node _T_1377 = and(_T_1376, _T_1347) @[el2_dec_dec_ctl.scala 17:17] + node _T_1378 = and(_T_1377, _T_1349) @[el2_dec_dec_ctl.scala 17:17] + node _T_1379 = and(_T_1378, _T_1350) @[el2_dec_dec_ctl.scala 17:17] + node _T_1380 = and(_T_1379, _T_1351) @[el2_dec_dec_ctl.scala 17:17] + node _T_1381 = or(_T_1299, _T_1380) @[el2_dec_dec_ctl.scala 101:136] + node _T_1382 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1383 = eq(_T_1382, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1384 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1385 = eq(_T_1384, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1386 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1388 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1389 = eq(_T_1388, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1390 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1391 = eq(_T_1390, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1392 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1393 = eq(_T_1392, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1394 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1396 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1398 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1400 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1402 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1404 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1406 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1408 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1410 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1412 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1414 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1416 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1418 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1420 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1422 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1424 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1426 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1427 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1428 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1430 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1432 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1433 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1434 = and(_T_1383, _T_1385) @[el2_dec_dec_ctl.scala 17:17] + node _T_1435 = and(_T_1434, _T_1387) @[el2_dec_dec_ctl.scala 17:17] + node _T_1436 = and(_T_1435, _T_1389) @[el2_dec_dec_ctl.scala 17:17] + node _T_1437 = and(_T_1436, _T_1391) @[el2_dec_dec_ctl.scala 17:17] + node _T_1438 = and(_T_1437, _T_1393) @[el2_dec_dec_ctl.scala 17:17] + node _T_1439 = and(_T_1438, _T_1395) @[el2_dec_dec_ctl.scala 17:17] + node _T_1440 = and(_T_1439, _T_1397) @[el2_dec_dec_ctl.scala 17:17] + node _T_1441 = and(_T_1440, _T_1399) @[el2_dec_dec_ctl.scala 17:17] + node _T_1442 = and(_T_1441, _T_1401) @[el2_dec_dec_ctl.scala 17:17] + node _T_1443 = and(_T_1442, _T_1403) @[el2_dec_dec_ctl.scala 17:17] + node _T_1444 = and(_T_1443, _T_1405) @[el2_dec_dec_ctl.scala 17:17] + node _T_1445 = and(_T_1444, _T_1407) @[el2_dec_dec_ctl.scala 17:17] + node _T_1446 = and(_T_1445, _T_1409) @[el2_dec_dec_ctl.scala 17:17] + node _T_1447 = and(_T_1446, _T_1411) @[el2_dec_dec_ctl.scala 17:17] + node _T_1448 = and(_T_1447, _T_1413) @[el2_dec_dec_ctl.scala 17:17] + node _T_1449 = and(_T_1448, _T_1415) @[el2_dec_dec_ctl.scala 17:17] + node _T_1450 = and(_T_1449, _T_1417) @[el2_dec_dec_ctl.scala 17:17] + node _T_1451 = and(_T_1450, _T_1419) @[el2_dec_dec_ctl.scala 17:17] + node _T_1452 = and(_T_1451, _T_1421) @[el2_dec_dec_ctl.scala 17:17] + node _T_1453 = and(_T_1452, _T_1423) @[el2_dec_dec_ctl.scala 17:17] + node _T_1454 = and(_T_1453, _T_1425) @[el2_dec_dec_ctl.scala 17:17] + node _T_1455 = and(_T_1454, _T_1426) @[el2_dec_dec_ctl.scala 17:17] + node _T_1456 = and(_T_1455, _T_1427) @[el2_dec_dec_ctl.scala 17:17] + node _T_1457 = and(_T_1456, _T_1429) @[el2_dec_dec_ctl.scala 17:17] + node _T_1458 = and(_T_1457, _T_1431) @[el2_dec_dec_ctl.scala 17:17] + node _T_1459 = and(_T_1458, _T_1432) @[el2_dec_dec_ctl.scala 17:17] + node _T_1460 = and(_T_1459, _T_1433) @[el2_dec_dec_ctl.scala 17:17] + node _T_1461 = or(_T_1381, _T_1460) @[el2_dec_dec_ctl.scala 102:122] + node _T_1462 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1463 = eq(_T_1462, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1464 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1465 = eq(_T_1464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1466 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1467 = eq(_T_1466, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1468 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1469 = eq(_T_1468, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1470 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1471 = eq(_T_1470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1472 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1473 = eq(_T_1472, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1474 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1475 = eq(_T_1474, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1476 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1478 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1479 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1481 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1482 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1483 = and(_T_1463, _T_1465) @[el2_dec_dec_ctl.scala 17:17] + node _T_1484 = and(_T_1483, _T_1467) @[el2_dec_dec_ctl.scala 17:17] + node _T_1485 = and(_T_1484, _T_1469) @[el2_dec_dec_ctl.scala 17:17] + node _T_1486 = and(_T_1485, _T_1471) @[el2_dec_dec_ctl.scala 17:17] + node _T_1487 = and(_T_1486, _T_1473) @[el2_dec_dec_ctl.scala 17:17] + node _T_1488 = and(_T_1487, _T_1475) @[el2_dec_dec_ctl.scala 17:17] + node _T_1489 = and(_T_1488, _T_1477) @[el2_dec_dec_ctl.scala 17:17] + node _T_1490 = and(_T_1489, _T_1478) @[el2_dec_dec_ctl.scala 17:17] + node _T_1491 = and(_T_1490, _T_1480) @[el2_dec_dec_ctl.scala 17:17] + node _T_1492 = and(_T_1491, _T_1481) @[el2_dec_dec_ctl.scala 17:17] + node _T_1493 = and(_T_1492, _T_1482) @[el2_dec_dec_ctl.scala 17:17] + node _T_1494 = or(_T_1461, _T_1493) @[el2_dec_dec_ctl.scala 103:119] + node _T_1495 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1497 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1498 = eq(_T_1497, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1499 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1500 = eq(_T_1499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1501 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1502 = eq(_T_1501, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1503 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1504 = eq(_T_1503, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1505 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1506 = eq(_T_1505, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1507 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1508 = eq(_T_1507, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1509 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1511 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1513 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1515 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1517 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1519 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1520 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1521 = and(_T_1496, _T_1498) @[el2_dec_dec_ctl.scala 17:17] + node _T_1522 = and(_T_1521, _T_1500) @[el2_dec_dec_ctl.scala 17:17] + node _T_1523 = and(_T_1522, _T_1502) @[el2_dec_dec_ctl.scala 17:17] + node _T_1524 = and(_T_1523, _T_1504) @[el2_dec_dec_ctl.scala 17:17] + node _T_1525 = and(_T_1524, _T_1506) @[el2_dec_dec_ctl.scala 17:17] + node _T_1526 = and(_T_1525, _T_1508) @[el2_dec_dec_ctl.scala 17:17] + node _T_1527 = and(_T_1526, _T_1510) @[el2_dec_dec_ctl.scala 17:17] + node _T_1528 = and(_T_1527, _T_1512) @[el2_dec_dec_ctl.scala 17:17] + node _T_1529 = and(_T_1528, _T_1514) @[el2_dec_dec_ctl.scala 17:17] + node _T_1530 = and(_T_1529, _T_1516) @[el2_dec_dec_ctl.scala 17:17] + node _T_1531 = and(_T_1530, _T_1518) @[el2_dec_dec_ctl.scala 17:17] + node _T_1532 = and(_T_1531, _T_1519) @[el2_dec_dec_ctl.scala 17:17] + node _T_1533 = and(_T_1532, _T_1520) @[el2_dec_dec_ctl.scala 17:17] + node _T_1534 = or(_T_1494, _T_1533) @[el2_dec_dec_ctl.scala 104:60] + node _T_1535 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1536 = eq(_T_1535, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1537 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1538 = eq(_T_1537, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1539 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1541 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1542 = eq(_T_1541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1543 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1544 = eq(_T_1543, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1545 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1546 = eq(_T_1545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1547 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_1548 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1550 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_1551 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1552 = eq(_T_1551, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1553 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1554 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1556 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1557 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1558 = and(_T_1536, _T_1538) @[el2_dec_dec_ctl.scala 17:17] + node _T_1559 = and(_T_1558, _T_1540) @[el2_dec_dec_ctl.scala 17:17] + node _T_1560 = and(_T_1559, _T_1542) @[el2_dec_dec_ctl.scala 17:17] + node _T_1561 = and(_T_1560, _T_1544) @[el2_dec_dec_ctl.scala 17:17] + node _T_1562 = and(_T_1561, _T_1546) @[el2_dec_dec_ctl.scala 17:17] + node _T_1563 = and(_T_1562, _T_1547) @[el2_dec_dec_ctl.scala 17:17] + node _T_1564 = and(_T_1563, _T_1549) @[el2_dec_dec_ctl.scala 17:17] + node _T_1565 = and(_T_1564, _T_1550) @[el2_dec_dec_ctl.scala 17:17] + node _T_1566 = and(_T_1565, _T_1552) @[el2_dec_dec_ctl.scala 17:17] + node _T_1567 = and(_T_1566, _T_1553) @[el2_dec_dec_ctl.scala 17:17] + node _T_1568 = and(_T_1567, _T_1555) @[el2_dec_dec_ctl.scala 17:17] + node _T_1569 = and(_T_1568, _T_1556) @[el2_dec_dec_ctl.scala 17:17] + node _T_1570 = and(_T_1569, _T_1557) @[el2_dec_dec_ctl.scala 17:17] + node _T_1571 = or(_T_1534, _T_1570) @[el2_dec_dec_ctl.scala 105:69] + node _T_1572 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1574 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1575 = eq(_T_1574, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1576 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1577 = eq(_T_1576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1578 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1579 = eq(_T_1578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1580 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1581 = eq(_T_1580, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1582 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1584 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1586 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1587 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1588 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1590 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1591 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1592 = and(_T_1573, _T_1575) @[el2_dec_dec_ctl.scala 17:17] + node _T_1593 = and(_T_1592, _T_1577) @[el2_dec_dec_ctl.scala 17:17] + node _T_1594 = and(_T_1593, _T_1579) @[el2_dec_dec_ctl.scala 17:17] + node _T_1595 = and(_T_1594, _T_1581) @[el2_dec_dec_ctl.scala 17:17] + node _T_1596 = and(_T_1595, _T_1583) @[el2_dec_dec_ctl.scala 17:17] + node _T_1597 = and(_T_1596, _T_1585) @[el2_dec_dec_ctl.scala 17:17] + node _T_1598 = and(_T_1597, _T_1586) @[el2_dec_dec_ctl.scala 17:17] + node _T_1599 = and(_T_1598, _T_1587) @[el2_dec_dec_ctl.scala 17:17] + node _T_1600 = and(_T_1599, _T_1589) @[el2_dec_dec_ctl.scala 17:17] + node _T_1601 = and(_T_1600, _T_1590) @[el2_dec_dec_ctl.scala 17:17] + node _T_1602 = and(_T_1601, _T_1591) @[el2_dec_dec_ctl.scala 17:17] + node _T_1603 = or(_T_1571, _T_1602) @[el2_dec_dec_ctl.scala 106:66] + node _T_1604 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1606 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1607 = eq(_T_1606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1608 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1609 = eq(_T_1608, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1610 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1611 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1612 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1613 = eq(_T_1612, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1614 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1615 = eq(_T_1614, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1616 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1617 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1618 = and(_T_1605, _T_1607) @[el2_dec_dec_ctl.scala 17:17] + node _T_1619 = and(_T_1618, _T_1609) @[el2_dec_dec_ctl.scala 17:17] + node _T_1620 = and(_T_1619, _T_1610) @[el2_dec_dec_ctl.scala 17:17] + node _T_1621 = and(_T_1620, _T_1611) @[el2_dec_dec_ctl.scala 17:17] + node _T_1622 = and(_T_1621, _T_1613) @[el2_dec_dec_ctl.scala 17:17] + node _T_1623 = and(_T_1622, _T_1615) @[el2_dec_dec_ctl.scala 17:17] + node _T_1624 = and(_T_1623, _T_1616) @[el2_dec_dec_ctl.scala 17:17] + node _T_1625 = and(_T_1624, _T_1617) @[el2_dec_dec_ctl.scala 17:17] + node _T_1626 = or(_T_1603, _T_1625) @[el2_dec_dec_ctl.scala 107:58] + node _T_1627 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:34] + node _T_1628 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1629 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1630 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1631 = eq(_T_1630, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1632 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1633 = eq(_T_1632, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1634 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1636 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1637 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1638 = and(_T_1627, _T_1628) @[el2_dec_dec_ctl.scala 17:17] + node _T_1639 = and(_T_1638, _T_1629) @[el2_dec_dec_ctl.scala 17:17] + node _T_1640 = and(_T_1639, _T_1631) @[el2_dec_dec_ctl.scala 17:17] + node _T_1641 = and(_T_1640, _T_1633) @[el2_dec_dec_ctl.scala 17:17] + node _T_1642 = and(_T_1641, _T_1635) @[el2_dec_dec_ctl.scala 17:17] + node _T_1643 = and(_T_1642, _T_1636) @[el2_dec_dec_ctl.scala 17:17] + node _T_1644 = and(_T_1643, _T_1637) @[el2_dec_dec_ctl.scala 17:17] + node _T_1645 = or(_T_1626, _T_1644) @[el2_dec_dec_ctl.scala 108:46] + node _T_1646 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1647 = eq(_T_1646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1648 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1650 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1652 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1653 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1654 = eq(_T_1653, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1655 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1656 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1657 = and(_T_1647, _T_1649) @[el2_dec_dec_ctl.scala 17:17] + node _T_1658 = and(_T_1657, _T_1651) @[el2_dec_dec_ctl.scala 17:17] + node _T_1659 = and(_T_1658, _T_1652) @[el2_dec_dec_ctl.scala 17:17] + node _T_1660 = and(_T_1659, _T_1654) @[el2_dec_dec_ctl.scala 17:17] + node _T_1661 = and(_T_1660, _T_1655) @[el2_dec_dec_ctl.scala 17:17] + node _T_1662 = and(_T_1661, _T_1656) @[el2_dec_dec_ctl.scala 17:17] + node _T_1663 = or(_T_1645, _T_1662) @[el2_dec_dec_ctl.scala 109:40] + node _T_1664 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1665 = eq(_T_1664, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1666 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1668 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1669 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1671 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1672 = eq(_T_1671, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1673 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1674 = eq(_T_1673, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1675 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1676 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1677 = and(_T_1665, _T_1667) @[el2_dec_dec_ctl.scala 17:17] + node _T_1678 = and(_T_1677, _T_1668) @[el2_dec_dec_ctl.scala 17:17] + node _T_1679 = and(_T_1678, _T_1670) @[el2_dec_dec_ctl.scala 17:17] + node _T_1680 = and(_T_1679, _T_1672) @[el2_dec_dec_ctl.scala 17:17] + node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 17:17] + node _T_1682 = and(_T_1681, _T_1675) @[el2_dec_dec_ctl.scala 17:17] + node _T_1683 = and(_T_1682, _T_1676) @[el2_dec_dec_ctl.scala 17:17] + node _T_1684 = or(_T_1663, _T_1683) @[el2_dec_dec_ctl.scala 110:39] + node _T_1685 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:34] + node _T_1686 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1687 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1688 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1689 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1691 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1693 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1694 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1695 = and(_T_1685, _T_1686) @[el2_dec_dec_ctl.scala 17:17] + node _T_1696 = and(_T_1695, _T_1687) @[el2_dec_dec_ctl.scala 17:17] + node _T_1697 = and(_T_1696, _T_1688) @[el2_dec_dec_ctl.scala 17:17] + node _T_1698 = and(_T_1697, _T_1690) @[el2_dec_dec_ctl.scala 17:17] + node _T_1699 = and(_T_1698, _T_1692) @[el2_dec_dec_ctl.scala 17:17] + node _T_1700 = and(_T_1699, _T_1693) @[el2_dec_dec_ctl.scala 17:17] + node _T_1701 = and(_T_1700, _T_1694) @[el2_dec_dec_ctl.scala 17:17] + node _T_1702 = or(_T_1684, _T_1701) @[el2_dec_dec_ctl.scala 111:43] + node _T_1703 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1704 = eq(_T_1703, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1705 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1706 = eq(_T_1705, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1707 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1708 = eq(_T_1707, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1709 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1710 = eq(_T_1709, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1711 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 15:53] + node _T_1712 = eq(_T_1711, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1713 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 15:53] + node _T_1714 = eq(_T_1713, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1715 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 15:53] + node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1717 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 15:53] + node _T_1718 = eq(_T_1717, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1719 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 15:53] + node _T_1720 = eq(_T_1719, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1721 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 15:53] + node _T_1722 = eq(_T_1721, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1723 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 15:53] + node _T_1724 = eq(_T_1723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1725 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 15:53] + node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1727 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1729 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1731 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1733 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1735 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1737 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1739 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1741 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1743 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1745 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1747 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1749 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1753 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1755 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1757 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1758 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1759 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1760 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1761 = and(_T_1704, _T_1706) @[el2_dec_dec_ctl.scala 17:17] + node _T_1762 = and(_T_1761, _T_1708) @[el2_dec_dec_ctl.scala 17:17] + node _T_1763 = and(_T_1762, _T_1710) @[el2_dec_dec_ctl.scala 17:17] + node _T_1764 = and(_T_1763, _T_1712) @[el2_dec_dec_ctl.scala 17:17] + node _T_1765 = and(_T_1764, _T_1714) @[el2_dec_dec_ctl.scala 17:17] + node _T_1766 = and(_T_1765, _T_1716) @[el2_dec_dec_ctl.scala 17:17] + node _T_1767 = and(_T_1766, _T_1718) @[el2_dec_dec_ctl.scala 17:17] + node _T_1768 = and(_T_1767, _T_1720) @[el2_dec_dec_ctl.scala 17:17] + node _T_1769 = and(_T_1768, _T_1722) @[el2_dec_dec_ctl.scala 17:17] + node _T_1770 = and(_T_1769, _T_1724) @[el2_dec_dec_ctl.scala 17:17] + node _T_1771 = and(_T_1770, _T_1726) @[el2_dec_dec_ctl.scala 17:17] + node _T_1772 = and(_T_1771, _T_1728) @[el2_dec_dec_ctl.scala 17:17] + node _T_1773 = and(_T_1772, _T_1730) @[el2_dec_dec_ctl.scala 17:17] + node _T_1774 = and(_T_1773, _T_1732) @[el2_dec_dec_ctl.scala 17:17] + node _T_1775 = and(_T_1774, _T_1734) @[el2_dec_dec_ctl.scala 17:17] + node _T_1776 = and(_T_1775, _T_1736) @[el2_dec_dec_ctl.scala 17:17] + node _T_1777 = and(_T_1776, _T_1738) @[el2_dec_dec_ctl.scala 17:17] + node _T_1778 = and(_T_1777, _T_1740) @[el2_dec_dec_ctl.scala 17:17] + node _T_1779 = and(_T_1778, _T_1742) @[el2_dec_dec_ctl.scala 17:17] + node _T_1780 = and(_T_1779, _T_1744) @[el2_dec_dec_ctl.scala 17:17] + node _T_1781 = and(_T_1780, _T_1746) @[el2_dec_dec_ctl.scala 17:17] + node _T_1782 = and(_T_1781, _T_1748) @[el2_dec_dec_ctl.scala 17:17] + node _T_1783 = and(_T_1782, _T_1750) @[el2_dec_dec_ctl.scala 17:17] + node _T_1784 = and(_T_1783, _T_1752) @[el2_dec_dec_ctl.scala 17:17] + node _T_1785 = and(_T_1784, _T_1754) @[el2_dec_dec_ctl.scala 17:17] + node _T_1786 = and(_T_1785, _T_1756) @[el2_dec_dec_ctl.scala 17:17] + node _T_1787 = and(_T_1786, _T_1757) @[el2_dec_dec_ctl.scala 17:17] + node _T_1788 = and(_T_1787, _T_1758) @[el2_dec_dec_ctl.scala 17:17] + node _T_1789 = and(_T_1788, _T_1759) @[el2_dec_dec_ctl.scala 17:17] + node _T_1790 = and(_T_1789, _T_1760) @[el2_dec_dec_ctl.scala 17:17] + node _T_1791 = or(_T_1702, _T_1790) @[el2_dec_dec_ctl.scala 112:39] + node _T_1792 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 15:53] + node _T_1793 = eq(_T_1792, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1794 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 15:53] + node _T_1795 = eq(_T_1794, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1796 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 15:53] + node _T_1797 = eq(_T_1796, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1798 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 15:53] + node _T_1799 = eq(_T_1798, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1800 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 15:53] + node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1802 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 15:53] + node _T_1803 = eq(_T_1802, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1804 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 15:53] + node _T_1805 = eq(_T_1804, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1806 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 15:53] + node _T_1807 = eq(_T_1806, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1808 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 15:53] + node _T_1809 = eq(_T_1808, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1810 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1811 = eq(_T_1810, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1812 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1813 = eq(_T_1812, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1815 = eq(_T_1814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1816 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 15:53] + node _T_1817 = eq(_T_1816, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1818 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 15:53] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1820 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 15:53] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1822 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 15:53] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1824 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 15:53] + node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1826 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1828 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1830 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1832 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1833 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1834 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1835 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1836 = and(_T_1793, _T_1795) @[el2_dec_dec_ctl.scala 17:17] + node _T_1837 = and(_T_1836, _T_1797) @[el2_dec_dec_ctl.scala 17:17] + node _T_1838 = and(_T_1837, _T_1799) @[el2_dec_dec_ctl.scala 17:17] + node _T_1839 = and(_T_1838, _T_1801) @[el2_dec_dec_ctl.scala 17:17] + node _T_1840 = and(_T_1839, _T_1803) @[el2_dec_dec_ctl.scala 17:17] + node _T_1841 = and(_T_1840, _T_1805) @[el2_dec_dec_ctl.scala 17:17] + node _T_1842 = and(_T_1841, _T_1807) @[el2_dec_dec_ctl.scala 17:17] + node _T_1843 = and(_T_1842, _T_1809) @[el2_dec_dec_ctl.scala 17:17] + node _T_1844 = and(_T_1843, _T_1811) @[el2_dec_dec_ctl.scala 17:17] + node _T_1845 = and(_T_1844, _T_1813) @[el2_dec_dec_ctl.scala 17:17] + node _T_1846 = and(_T_1845, _T_1815) @[el2_dec_dec_ctl.scala 17:17] + node _T_1847 = and(_T_1846, _T_1817) @[el2_dec_dec_ctl.scala 17:17] + node _T_1848 = and(_T_1847, _T_1819) @[el2_dec_dec_ctl.scala 17:17] + node _T_1849 = and(_T_1848, _T_1821) @[el2_dec_dec_ctl.scala 17:17] + node _T_1850 = and(_T_1849, _T_1823) @[el2_dec_dec_ctl.scala 17:17] + node _T_1851 = and(_T_1850, _T_1825) @[el2_dec_dec_ctl.scala 17:17] + node _T_1852 = and(_T_1851, _T_1827) @[el2_dec_dec_ctl.scala 17:17] + node _T_1853 = and(_T_1852, _T_1829) @[el2_dec_dec_ctl.scala 17:17] + node _T_1854 = and(_T_1853, _T_1831) @[el2_dec_dec_ctl.scala 17:17] + node _T_1855 = and(_T_1854, _T_1832) @[el2_dec_dec_ctl.scala 17:17] + node _T_1856 = and(_T_1855, _T_1833) @[el2_dec_dec_ctl.scala 17:17] + node _T_1857 = and(_T_1856, _T_1834) @[el2_dec_dec_ctl.scala 17:17] + node _T_1858 = and(_T_1857, _T_1835) @[el2_dec_dec_ctl.scala 17:17] + node _T_1859 = or(_T_1791, _T_1858) @[el2_dec_dec_ctl.scala 113:130] + node _T_1860 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1861 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1862 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1864 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1866 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1867 = eq(_T_1866, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1868 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1869 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1870 = and(_T_1860, _T_1861) @[el2_dec_dec_ctl.scala 17:17] + node _T_1871 = and(_T_1870, _T_1862) @[el2_dec_dec_ctl.scala 17:17] + node _T_1872 = and(_T_1871, _T_1863) @[el2_dec_dec_ctl.scala 17:17] + node _T_1873 = and(_T_1872, _T_1865) @[el2_dec_dec_ctl.scala 17:17] + node _T_1874 = and(_T_1873, _T_1867) @[el2_dec_dec_ctl.scala 17:17] + node _T_1875 = and(_T_1874, _T_1868) @[el2_dec_dec_ctl.scala 17:17] + node _T_1876 = and(_T_1875, _T_1869) @[el2_dec_dec_ctl.scala 17:17] + node _T_1877 = or(_T_1859, _T_1876) @[el2_dec_dec_ctl.scala 114:102] + node _T_1878 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:53] + node _T_1879 = eq(_T_1878, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1880 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1881 = eq(_T_1880, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1882 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1883 = eq(_T_1882, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1884 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1885 = eq(_T_1884, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1886 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1887 = eq(_T_1886, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1888 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1889 = eq(_T_1888, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1890 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1891 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1892 = and(_T_1879, _T_1881) @[el2_dec_dec_ctl.scala 17:17] + node _T_1893 = and(_T_1892, _T_1883) @[el2_dec_dec_ctl.scala 17:17] + node _T_1894 = and(_T_1893, _T_1885) @[el2_dec_dec_ctl.scala 17:17] + node _T_1895 = and(_T_1894, _T_1887) @[el2_dec_dec_ctl.scala 17:17] + node _T_1896 = and(_T_1895, _T_1889) @[el2_dec_dec_ctl.scala 17:17] + node _T_1897 = and(_T_1896, _T_1890) @[el2_dec_dec_ctl.scala 17:17] + node _T_1898 = and(_T_1897, _T_1891) @[el2_dec_dec_ctl.scala 17:17] + node _T_1899 = or(_T_1877, _T_1898) @[el2_dec_dec_ctl.scala 115:39] + node _T_1900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:34] + node _T_1901 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:34] + node _T_1902 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1903 = eq(_T_1902, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1904 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:34] + node _T_1905 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1906 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1907 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1908 = and(_T_1900, _T_1901) @[el2_dec_dec_ctl.scala 17:17] + node _T_1909 = and(_T_1908, _T_1903) @[el2_dec_dec_ctl.scala 17:17] + node _T_1910 = and(_T_1909, _T_1904) @[el2_dec_dec_ctl.scala 17:17] + node _T_1911 = and(_T_1910, _T_1905) @[el2_dec_dec_ctl.scala 17:17] + node _T_1912 = and(_T_1911, _T_1906) @[el2_dec_dec_ctl.scala 17:17] + node _T_1913 = and(_T_1912, _T_1907) @[el2_dec_dec_ctl.scala 17:17] + node _T_1914 = or(_T_1899, _T_1913) @[el2_dec_dec_ctl.scala 116:43] + node _T_1915 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 15:34] + node _T_1916 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1917 = eq(_T_1916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1918 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 15:53] + node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1920 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1921 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1922 = eq(_T_1921, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1923 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1924 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1925 = and(_T_1915, _T_1917) @[el2_dec_dec_ctl.scala 17:17] + node _T_1926 = and(_T_1925, _T_1919) @[el2_dec_dec_ctl.scala 17:17] + node _T_1927 = and(_T_1926, _T_1920) @[el2_dec_dec_ctl.scala 17:17] + node _T_1928 = and(_T_1927, _T_1922) @[el2_dec_dec_ctl.scala 17:17] + node _T_1929 = and(_T_1928, _T_1923) @[el2_dec_dec_ctl.scala 17:17] + node _T_1930 = and(_T_1929, _T_1924) @[el2_dec_dec_ctl.scala 17:17] + node _T_1931 = or(_T_1914, _T_1930) @[el2_dec_dec_ctl.scala 117:35] + node _T_1932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 15:53] + node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1934 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 15:53] + node _T_1935 = eq(_T_1934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1936 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1937 = eq(_T_1936, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1938 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:53] + node _T_1939 = eq(_T_1938, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1940 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1942 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:53] + node _T_1943 = eq(_T_1942, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1944 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1945 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1946 = and(_T_1933, _T_1935) @[el2_dec_dec_ctl.scala 17:17] + node _T_1947 = and(_T_1946, _T_1937) @[el2_dec_dec_ctl.scala 17:17] + node _T_1948 = and(_T_1947, _T_1939) @[el2_dec_dec_ctl.scala 17:17] + node _T_1949 = and(_T_1948, _T_1941) @[el2_dec_dec_ctl.scala 17:17] + node _T_1950 = and(_T_1949, _T_1943) @[el2_dec_dec_ctl.scala 17:17] + node _T_1951 = and(_T_1950, _T_1944) @[el2_dec_dec_ctl.scala 17:17] + node _T_1952 = and(_T_1951, _T_1945) @[el2_dec_dec_ctl.scala 17:17] + node _T_1953 = or(_T_1931, _T_1952) @[el2_dec_dec_ctl.scala 118:38] + node _T_1954 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 15:53] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 15:34] + node _T_1957 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 15:53] + node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 15:46] + node _T_1959 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 15:34] + node _T_1960 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 15:34] + node _T_1961 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 15:34] + node _T_1962 = and(_T_1955, _T_1956) @[el2_dec_dec_ctl.scala 17:17] + node _T_1963 = and(_T_1962, _T_1958) @[el2_dec_dec_ctl.scala 17:17] + node _T_1964 = and(_T_1963, _T_1959) @[el2_dec_dec_ctl.scala 17:17] + node _T_1965 = and(_T_1964, _T_1960) @[el2_dec_dec_ctl.scala 17:17] + node _T_1966 = and(_T_1965, _T_1961) @[el2_dec_dec_ctl.scala 17:17] + node _T_1967 = or(_T_1953, _T_1966) @[el2_dec_dec_ctl.scala 119:44] + io.out.legal <= _T_1967 @[el2_dec_dec_ctl.scala 101:16] extmodule gated_latch_662 : output Q : Clock @@ -66819,7 +66804,7 @@ circuit el2_swerv_wrapper : module el2_dec_decode_ctl : input clock : Clock input reset : AsyncReset - output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[el2_dec_decode_ctl.scala 126:27] _T.bits.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] @@ -66870,11 +66855,11 @@ circuit el2_swerv_wrapper : wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] - wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 136:17] - wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 137:17] - wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 138:17] - wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 139:20] - wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 140:17] + wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] + wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] + wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] + wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] + wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] @@ -66884,14 +66869,14 @@ circuit el2_swerv_wrapper : i0_rs2_depth_d <= UInt<1>("h00") wire cam_wen : UInt<4> cam_wen <= UInt<1>("h00") - wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 147:17] + wire cam : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 147:17] wire cam_write : UInt<1> cam_write <= UInt<1>("h00") wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29] wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30] wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31] - wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 152:20] - wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[el2_dec_decode_ctl.scala 153:20] + wire cam_raw : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 152:20] + wire cam_in : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 153:20] wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18] wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22] wire i0_rs1bypass : UInt<3> @@ -67028,9 +67013,9 @@ circuit el2_swerv_wrapper : io.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 230:43] io.dec_i0_predict_p_d.bits.pja <= i0_pja @[el2_dec_decode_ctl.scala 231:43] io.dec_i0_predict_p_d.bits.pret <= i0_pret @[el2_dec_decode_ctl.scala 232:43] - io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[el2_dec_decode_ctl.scala 233:43] + io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.prett @[el2_dec_decode_ctl.scala 233:43] io.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 234:43] - io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[el2_dec_decode_ctl.scala 235:43] + io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.hist @[el2_dec_decode_ctl.scala 235:43] node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 236:55] io.dec_i0_predict_p_d.valid <= _T_19 @[el2_dec_decode_ctl.scala 236:38] node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 237:75] @@ -67038,34 +67023,34 @@ circuit el2_swerv_wrapper : node _T_22 = or(_T_21, i0_pret_raw) @[el2_dec_decode_ctl.scala 237:103] node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 237:56] node i0_notbr_error = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 237:54] - node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:72] + node _T_24 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:67] node _T_25 = and(i0_brp_valid, _T_24) @[el2_dec_decode_ctl.scala 240:47] - node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:106] - node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:76] - node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:126] - node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:124] - node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[el2_dec_decode_ctl.scala 241:47] - node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:74] - node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:72] - node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:62] - node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:79] - node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:101] + node _T_26 = neq(io.dec_i0_brp.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:96] + node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:71] + node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:116] + node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:114] + node _T_29 = and(i0_brp_valid, io.dec_i0_brp.ret) @[el2_dec_decode_ctl.scala 241:47] + node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:69] + node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:67] + node _T_31 = or(io.dec_i0_brp.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:57] + node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:74] + node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:96] node _T_33 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 243:72] node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 243:94] node _T_35 = and(_T_33, _T_34) @[el2_dec_decode_ctl.scala 243:92] io.dec_i0_predict_p_d.bits.br_error <= _T_35 @[el2_dec_decode_ctl.scala 243:56] - node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:94] - node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:116] - node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:114] + node _T_36 = and(io.dec_i0_brp.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:89] + node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:111] + node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:109] io.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[el2_dec_decode_ctl.scala 244:56] io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 245:32] io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 246:32] - node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[el2_dec_decode_ctl.scala 247:47] - node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:86] - node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:84] + node _T_39 = or(i0_br_error, io.dec_i0_brp.br_start_error) @[el2_dec_decode_ctl.scala 247:47] + node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:81] + node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:79] io.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 248:49] io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 249:32] - io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[el2_dec_decode_ctl.scala 250:56] + io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.way @[el2_dec_decode_ctl.scala 250:56] node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 256:36] i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 259:9] i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 259:9] @@ -67232,13 +67217,13 @@ circuit el2_swerv_wrapper : node _T_44 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 274:38] node _T_45 = or(_T_44, i0_pja) @[el2_dec_decode_ctl.scala 274:49] node i0_predict_br = or(_T_45, i0_pret) @[el2_dec_decode_ctl.scala 274:58] - node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:51] - node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:55] + node _T_46 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:46] + node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:50] node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 276:26] - node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:71] - node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:51] - node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:55] - node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:71] + node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:66] + node _T_49 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:46] + node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:50] + node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:66] node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 278:20] io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 280:26] io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 281:26] @@ -67302,34 +67287,34 @@ circuit el2_swerv_wrapper : cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 305:25] node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 306:54] node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 311:63] - node _T_89 = bits(x_d.bits.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:48] - node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] + node _T_89 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 314:43] + node nonblock_load_rd = mux(_T_89, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 314:31] node _T_90 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 318:116] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_90 : @[Reg.scala 28:19] nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 319:56] - node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 319:56] + node _T_91 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 321:66] node _T_92 = and(io.lsu_nonblock_load_inv_r, _T_91) @[el2_dec_decode_ctl.scala 321:45] - node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:87] + node _T_93 = and(_T_92, cam[0].valid) @[el2_dec_decode_ctl.scala 321:82] cam_inv_reset_val[0] <= _T_93 @[el2_dec_decode_ctl.scala 321:26] - node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_94 = eq(io.lsu_nonblock_load_data_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 322:67] node _T_95 = and(cam_data_reset, _T_94) @[el2_dec_decode_ctl.scala 322:45] - node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:88] + node _T_96 = and(_T_95, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 322:83] cam_data_reset_val[0] <= _T_96 @[el2_dec_decode_ctl.scala 322:27] - wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] - _T_97.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_97.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_97.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_97 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_97.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_97.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_97.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[0].bits.rd <= _T_97.bits.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[0].bits.tag <= _T_97.bits.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[0].bits.wb <= _T_97.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].rd <= _T_97.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].tag <= _T_97.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[0].wb <= _T_97.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[0].valid <= _T_97.valid @[el2_dec_decode_ctl.scala 323:14] - cam[0].bits.rd <= cam_raw[0].bits.rd @[el2_dec_decode_ctl.scala 324:11] - cam[0].bits.tag <= cam_raw[0].bits.tag @[el2_dec_decode_ctl.scala 324:11] - cam[0].bits.wb <= cam_raw[0].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[0].rd <= cam_raw[0].rd @[el2_dec_decode_ctl.scala 324:11] + cam[0].tag <= cam_raw[0].tag @[el2_dec_decode_ctl.scala 324:11] + cam[0].wb <= cam_raw[0].wb @[el2_dec_decode_ctl.scala 324:11] cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 324:11] node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_98 : @[el2_dec_decode_ctl.scala 326:39] @@ -67339,75 +67324,75 @@ circuit el2_swerv_wrapper : node _T_100 = bits(_T_99, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_100 : @[el2_dec_decode_ctl.scala 329:28] cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[0].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] - cam_in[0].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] - cam_in[0].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + cam_in[0].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[0].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[0].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:116] node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_102 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_103 = eq(r_d_in.i0rd, cam[0].rd) @[el2_dec_decode_ctl.scala 334:80] node _T_104 = and(_T_102, _T_103) @[el2_dec_decode_ctl.scala 334:64] - node _T_105 = bits(cam[0].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:105] + node _T_105 = bits(cam[0].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_106 = and(_T_104, _T_105) @[el2_dec_decode_ctl.scala 334:95] node _T_107 = or(_T_101, _T_106) @[el2_dec_decode_ctl.scala 334:44] - when _T_107 : @[el2_dec_decode_ctl.scala 334:131] + when _T_107 : @[el2_dec_decode_ctl.scala 334:116] cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:116] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[0].bits.rd <= cam[0].bits.rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[0].bits.tag <= cam[0].bits.tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[0].bits.wb <= cam[0].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].rd <= cam[0].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].tag <= cam[0].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[0].wb <= cam[0].wb @[el2_dec_decode_ctl.scala 337:22] cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_109 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 339:79] node _T_110 = and(_T_108, _T_109) @[el2_dec_decode_ctl.scala 339:44] - node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] - node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:100] - when _T_112 : @[el2_dec_decode_ctl.scala 339:122] - cam_in[0].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] - skip @[el2_dec_decode_ctl.scala 339:122] + node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_112 = and(_T_110, _T_111) @[el2_dec_decode_ctl.scala 339:95] + when _T_112 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[0].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] - _T_113.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_113.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_113.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_113 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_113.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_113.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_113.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47] - _T_114.bits.rd <= cam_in[0].bits.rd @[el2_dec_decode_ctl.scala 347:47] - _T_114.bits.tag <= cam_in[0].bits.tag @[el2_dec_decode_ctl.scala 347:47] - _T_114.bits.wb <= cam_in[0].bits.wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_114 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_113)) @[el2_dec_decode_ctl.scala 347:47] + _T_114.rd <= cam_in[0].rd @[el2_dec_decode_ctl.scala 347:47] + _T_114.tag <= cam_in[0].tag @[el2_dec_decode_ctl.scala 347:47] + _T_114.wb <= cam_in[0].wb @[el2_dec_decode_ctl.scala 347:47] _T_114.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[0].bits.rd <= _T_114.bits.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[0].bits.tag <= _T_114.bits.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[0].bits.wb <= _T_114.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].rd <= _T_114.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].tag <= _T_114.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[0].wb <= _T_114.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[0].valid <= _T_114.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:71] + node _T_115 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_116 = and(_T_115, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 348:66] nonblock_load_write[0] <= _T_116 @[el2_dec_decode_ctl.scala 348:28] - node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_117 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 321:66] node _T_118 = and(io.lsu_nonblock_load_inv_r, _T_117) @[el2_dec_decode_ctl.scala 321:45] - node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:87] + node _T_119 = and(_T_118, cam[1].valid) @[el2_dec_decode_ctl.scala 321:82] cam_inv_reset_val[1] <= _T_119 @[el2_dec_decode_ctl.scala 321:26] - node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_120 = eq(io.lsu_nonblock_load_data_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 322:67] node _T_121 = and(cam_data_reset, _T_120) @[el2_dec_decode_ctl.scala 322:45] - node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:88] + node _T_122 = and(_T_121, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 322:83] cam_data_reset_val[1] <= _T_122 @[el2_dec_decode_ctl.scala 322:27] - wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] - _T_123.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_123.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_123.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_123 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_123.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_123.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_123.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[1].bits.rd <= _T_123.bits.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[1].bits.tag <= _T_123.bits.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[1].bits.wb <= _T_123.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].rd <= _T_123.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].tag <= _T_123.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[1].wb <= _T_123.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[1].valid <= _T_123.valid @[el2_dec_decode_ctl.scala 323:14] - cam[1].bits.rd <= cam_raw[1].bits.rd @[el2_dec_decode_ctl.scala 324:11] - cam[1].bits.tag <= cam_raw[1].bits.tag @[el2_dec_decode_ctl.scala 324:11] - cam[1].bits.wb <= cam_raw[1].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[1].rd <= cam_raw[1].rd @[el2_dec_decode_ctl.scala 324:11] + cam[1].tag <= cam_raw[1].tag @[el2_dec_decode_ctl.scala 324:11] + cam[1].wb <= cam_raw[1].wb @[el2_dec_decode_ctl.scala 324:11] cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 324:11] node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_124 : @[el2_dec_decode_ctl.scala 326:39] @@ -67417,75 +67402,75 @@ circuit el2_swerv_wrapper : node _T_126 = bits(_T_125, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_126 : @[el2_dec_decode_ctl.scala 329:28] cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[1].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] - cam_in[1].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] - cam_in[1].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + cam_in[1].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[1].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[1].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:116] node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_128 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_129 = eq(r_d_in.i0rd, cam[1].rd) @[el2_dec_decode_ctl.scala 334:80] node _T_130 = and(_T_128, _T_129) @[el2_dec_decode_ctl.scala 334:64] - node _T_131 = bits(cam[1].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:105] + node _T_131 = bits(cam[1].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_132 = and(_T_130, _T_131) @[el2_dec_decode_ctl.scala 334:95] node _T_133 = or(_T_127, _T_132) @[el2_dec_decode_ctl.scala 334:44] - when _T_133 : @[el2_dec_decode_ctl.scala 334:131] + when _T_133 : @[el2_dec_decode_ctl.scala 334:116] cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:116] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[1].bits.rd <= cam[1].bits.rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[1].bits.tag <= cam[1].bits.tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[1].bits.wb <= cam[1].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].rd <= cam[1].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].tag <= cam[1].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[1].wb <= cam[1].wb @[el2_dec_decode_ctl.scala 337:22] cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_135 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 339:79] node _T_136 = and(_T_134, _T_135) @[el2_dec_decode_ctl.scala 339:44] - node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] - node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:100] - when _T_138 : @[el2_dec_decode_ctl.scala 339:122] - cam_in[1].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] - skip @[el2_dec_decode_ctl.scala 339:122] + node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_138 = and(_T_136, _T_137) @[el2_dec_decode_ctl.scala 339:95] + when _T_138 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[1].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] - _T_139.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_139.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_139.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_139 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_139.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_139.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_139.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47] - _T_140.bits.rd <= cam_in[1].bits.rd @[el2_dec_decode_ctl.scala 347:47] - _T_140.bits.tag <= cam_in[1].bits.tag @[el2_dec_decode_ctl.scala 347:47] - _T_140.bits.wb <= cam_in[1].bits.wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_140 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_139)) @[el2_dec_decode_ctl.scala 347:47] + _T_140.rd <= cam_in[1].rd @[el2_dec_decode_ctl.scala 347:47] + _T_140.tag <= cam_in[1].tag @[el2_dec_decode_ctl.scala 347:47] + _T_140.wb <= cam_in[1].wb @[el2_dec_decode_ctl.scala 347:47] _T_140.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[1].bits.rd <= _T_140.bits.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[1].bits.tag <= _T_140.bits.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[1].bits.wb <= _T_140.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].rd <= _T_140.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].tag <= _T_140.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[1].wb <= _T_140.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[1].valid <= _T_140.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:71] + node _T_141 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_142 = and(_T_141, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 348:66] nonblock_load_write[1] <= _T_142 @[el2_dec_decode_ctl.scala 348:28] - node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_143 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 321:66] node _T_144 = and(io.lsu_nonblock_load_inv_r, _T_143) @[el2_dec_decode_ctl.scala 321:45] - node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:87] + node _T_145 = and(_T_144, cam[2].valid) @[el2_dec_decode_ctl.scala 321:82] cam_inv_reset_val[2] <= _T_145 @[el2_dec_decode_ctl.scala 321:26] - node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_146 = eq(io.lsu_nonblock_load_data_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 322:67] node _T_147 = and(cam_data_reset, _T_146) @[el2_dec_decode_ctl.scala 322:45] - node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:88] + node _T_148 = and(_T_147, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 322:83] cam_data_reset_val[2] <= _T_148 @[el2_dec_decode_ctl.scala 322:27] - wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] - _T_149.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_149.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_149.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_149 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_149.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_149.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_149.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[2].bits.rd <= _T_149.bits.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[2].bits.tag <= _T_149.bits.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[2].bits.wb <= _T_149.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].rd <= _T_149.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].tag <= _T_149.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[2].wb <= _T_149.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[2].valid <= _T_149.valid @[el2_dec_decode_ctl.scala 323:14] - cam[2].bits.rd <= cam_raw[2].bits.rd @[el2_dec_decode_ctl.scala 324:11] - cam[2].bits.tag <= cam_raw[2].bits.tag @[el2_dec_decode_ctl.scala 324:11] - cam[2].bits.wb <= cam_raw[2].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[2].rd <= cam_raw[2].rd @[el2_dec_decode_ctl.scala 324:11] + cam[2].tag <= cam_raw[2].tag @[el2_dec_decode_ctl.scala 324:11] + cam[2].wb <= cam_raw[2].wb @[el2_dec_decode_ctl.scala 324:11] cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 324:11] node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_150 : @[el2_dec_decode_ctl.scala 326:39] @@ -67495,75 +67480,75 @@ circuit el2_swerv_wrapper : node _T_152 = bits(_T_151, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_152 : @[el2_dec_decode_ctl.scala 329:28] cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[2].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] - cam_in[2].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] - cam_in[2].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + cam_in[2].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[2].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[2].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:116] node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_154 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_155 = eq(r_d_in.i0rd, cam[2].rd) @[el2_dec_decode_ctl.scala 334:80] node _T_156 = and(_T_154, _T_155) @[el2_dec_decode_ctl.scala 334:64] - node _T_157 = bits(cam[2].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:105] + node _T_157 = bits(cam[2].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_158 = and(_T_156, _T_157) @[el2_dec_decode_ctl.scala 334:95] node _T_159 = or(_T_153, _T_158) @[el2_dec_decode_ctl.scala 334:44] - when _T_159 : @[el2_dec_decode_ctl.scala 334:131] + when _T_159 : @[el2_dec_decode_ctl.scala 334:116] cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:116] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[2].bits.rd <= cam[2].bits.rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[2].bits.tag <= cam[2].bits.tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[2].bits.wb <= cam[2].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].rd <= cam[2].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].tag <= cam[2].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[2].wb <= cam[2].wb @[el2_dec_decode_ctl.scala 337:22] cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_161 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 339:79] node _T_162 = and(_T_160, _T_161) @[el2_dec_decode_ctl.scala 339:44] - node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] - node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:100] - when _T_164 : @[el2_dec_decode_ctl.scala 339:122] - cam_in[2].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] - skip @[el2_dec_decode_ctl.scala 339:122] + node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_164 = and(_T_162, _T_163) @[el2_dec_decode_ctl.scala 339:95] + when _T_164 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[2].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] - _T_165.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_165.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_165.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_165 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_165.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_165.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_165.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47] - _T_166.bits.rd <= cam_in[2].bits.rd @[el2_dec_decode_ctl.scala 347:47] - _T_166.bits.tag <= cam_in[2].bits.tag @[el2_dec_decode_ctl.scala 347:47] - _T_166.bits.wb <= cam_in[2].bits.wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_166 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_165)) @[el2_dec_decode_ctl.scala 347:47] + _T_166.rd <= cam_in[2].rd @[el2_dec_decode_ctl.scala 347:47] + _T_166.tag <= cam_in[2].tag @[el2_dec_decode_ctl.scala 347:47] + _T_166.wb <= cam_in[2].wb @[el2_dec_decode_ctl.scala 347:47] _T_166.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[2].bits.rd <= _T_166.bits.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[2].bits.tag <= _T_166.bits.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[2].bits.wb <= _T_166.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].rd <= _T_166.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].tag <= _T_166.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[2].wb <= _T_166.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[2].valid <= _T_166.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:71] + node _T_167 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_168 = and(_T_167, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 348:66] nonblock_load_write[2] <= _T_168 @[el2_dec_decode_ctl.scala 348:28] - node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 321:66] + node _T_169 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 321:66] node _T_170 = and(io.lsu_nonblock_load_inv_r, _T_169) @[el2_dec_decode_ctl.scala 321:45] - node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:87] + node _T_171 = and(_T_170, cam[3].valid) @[el2_dec_decode_ctl.scala 321:82] cam_inv_reset_val[3] <= _T_171 @[el2_dec_decode_ctl.scala 321:26] - node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 322:67] + node _T_172 = eq(io.lsu_nonblock_load_data_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 322:67] node _T_173 = and(cam_data_reset, _T_172) @[el2_dec_decode_ctl.scala 322:45] - node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:88] + node _T_174 = and(_T_173, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 322:83] cam_data_reset_val[3] <= _T_174 @[el2_dec_decode_ctl.scala 322:27] - wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 323:28] - _T_175.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_175.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] - _T_175.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] + wire _T_175 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 323:28] + _T_175.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 323:28] + _T_175.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] _T_175.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 323:28] - cam_in[3].bits.rd <= _T_175.bits.rd @[el2_dec_decode_ctl.scala 323:14] - cam_in[3].bits.tag <= _T_175.bits.tag @[el2_dec_decode_ctl.scala 323:14] - cam_in[3].bits.wb <= _T_175.bits.wb @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].rd <= _T_175.rd @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].tag <= _T_175.tag @[el2_dec_decode_ctl.scala 323:14] + cam_in[3].wb <= _T_175.wb @[el2_dec_decode_ctl.scala 323:14] cam_in[3].valid <= _T_175.valid @[el2_dec_decode_ctl.scala 323:14] - cam[3].bits.rd <= cam_raw[3].bits.rd @[el2_dec_decode_ctl.scala 324:11] - cam[3].bits.tag <= cam_raw[3].bits.tag @[el2_dec_decode_ctl.scala 324:11] - cam[3].bits.wb <= cam_raw[3].bits.wb @[el2_dec_decode_ctl.scala 324:11] + cam[3].rd <= cam_raw[3].rd @[el2_dec_decode_ctl.scala 324:11] + cam[3].tag <= cam_raw[3].tag @[el2_dec_decode_ctl.scala 324:11] + cam[3].wb <= cam_raw[3].wb @[el2_dec_decode_ctl.scala 324:11] cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 324:11] node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 326:32] when _T_176 : @[el2_dec_decode_ctl.scala 326:39] @@ -67573,58 +67558,58 @@ circuit el2_swerv_wrapper : node _T_178 = bits(_T_177, 0, 0) @[el2_dec_decode_ctl.scala 329:21] when _T_178 : @[el2_dec_decode_ctl.scala 329:28] cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 330:27] - cam_in[3].bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:32] - cam_in[3].bits.tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:32] - cam_in[3].bits.rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:32] + cam_in[3].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:27] + cam_in[3].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 332:27] + cam_in[3].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 333:27] skip @[el2_dec_decode_ctl.scala 329:28] - else : @[el2_dec_decode_ctl.scala 334:131] + else : @[el2_dec_decode_ctl.scala 334:116] node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 334:37] node _T_180 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 334:57] - node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 334:85] + node _T_181 = eq(r_d_in.i0rd, cam[3].rd) @[el2_dec_decode_ctl.scala 334:80] node _T_182 = and(_T_180, _T_181) @[el2_dec_decode_ctl.scala 334:64] - node _T_183 = bits(cam[3].bits.wb, 0, 0) @[el2_dec_decode_ctl.scala 334:123] - node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:105] + node _T_183 = bits(cam[3].wb, 0, 0) @[el2_dec_decode_ctl.scala 334:108] + node _T_184 = and(_T_182, _T_183) @[el2_dec_decode_ctl.scala 334:95] node _T_185 = or(_T_179, _T_184) @[el2_dec_decode_ctl.scala 334:44] - when _T_185 : @[el2_dec_decode_ctl.scala 334:131] + when _T_185 : @[el2_dec_decode_ctl.scala 334:116] cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:23] - skip @[el2_dec_decode_ctl.scala 334:131] + skip @[el2_dec_decode_ctl.scala 334:116] else : @[el2_dec_decode_ctl.scala 336:16] - cam_in[3].bits.rd <= cam[3].bits.rd @[el2_dec_decode_ctl.scala 337:22] - cam_in[3].bits.tag <= cam[3].bits.tag @[el2_dec_decode_ctl.scala 337:22] - cam_in[3].bits.wb <= cam[3].bits.wb @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].rd <= cam[3].rd @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].tag <= cam[3].tag @[el2_dec_decode_ctl.scala 337:22] + cam_in[3].wb <= cam[3].wb @[el2_dec_decode_ctl.scala 337:22] cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 337:22] skip @[el2_dec_decode_ctl.scala 336:16] node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:37] - node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[el2_dec_decode_ctl.scala 339:79] + node _T_187 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 339:79] node _T_188 = and(_T_186, _T_187) @[el2_dec_decode_ctl.scala 339:44] - node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:115] - node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:100] - when _T_190 : @[el2_dec_decode_ctl.scala 339:122] - cam_in[3].bits.wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:25] - skip @[el2_dec_decode_ctl.scala 339:122] + node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 339:110] + node _T_190 = and(_T_188, _T_189) @[el2_dec_decode_ctl.scala 339:95] + when _T_190 : @[el2_dec_decode_ctl.scala 339:117] + cam_in[3].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 340:20] + skip @[el2_dec_decode_ctl.scala 339:117] when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 343:32] cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 344:23] skip @[el2_dec_decode_ctl.scala 343:32] - wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[el2_dec_decode_ctl.scala 347:70] - _T_191.bits.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_191.bits.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] - _T_191.bits.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] + wire _T_191 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 347:70] + _T_191.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 347:70] + _T_191.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] _T_191.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 347:70] - reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47] - _T_192.bits.rd <= cam_in[3].bits.rd @[el2_dec_decode_ctl.scala 347:47] - _T_192.bits.tag <= cam_in[3].bits.tag @[el2_dec_decode_ctl.scala 347:47] - _T_192.bits.wb <= cam_in[3].bits.wb @[el2_dec_decode_ctl.scala 347:47] + reg _T_192 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_191)) @[el2_dec_decode_ctl.scala 347:47] + _T_192.rd <= cam_in[3].rd @[el2_dec_decode_ctl.scala 347:47] + _T_192.tag <= cam_in[3].tag @[el2_dec_decode_ctl.scala 347:47] + _T_192.wb <= cam_in[3].wb @[el2_dec_decode_ctl.scala 347:47] _T_192.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 347:47] - cam_raw[3].bits.rd <= _T_192.bits.rd @[el2_dec_decode_ctl.scala 347:15] - cam_raw[3].bits.tag <= _T_192.bits.tag @[el2_dec_decode_ctl.scala 347:15] - cam_raw[3].bits.wb <= _T_192.bits.wb @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].rd <= _T_192.rd @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].tag <= _T_192.tag @[el2_dec_decode_ctl.scala 347:15] + cam_raw[3].wb <= _T_192.wb @[el2_dec_decode_ctl.scala 347:15] cam_raw[3].valid <= _T_192.valid @[el2_dec_decode_ctl.scala 347:15] - node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[el2_dec_decode_ctl.scala 348:46] - node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:71] + node _T_193 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].tag) @[el2_dec_decode_ctl.scala 348:46] + node _T_194 = and(_T_193, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 348:66] nonblock_load_write[3] <= _T_194 @[el2_dec_decode_ctl.scala 348:28] io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:29] - node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:49] - node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:81] + node _T_195 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 353:44] + node nonblock_load_cancel = and(_T_195, i0_wen_r) @[el2_dec_decode_ctl.scala 353:76] node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 354:95] node _T_197 = or(_T_196, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 354:95] node _T_198 = or(_T_197, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 354:95] @@ -67643,40 +67628,40 @@ circuit el2_swerv_wrapper : i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 357:26] node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_211 = and(_T_210, cam[0].bits.rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:126] - node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] - node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:141] - node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:192] - node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] - node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:207] + node _T_211 = and(_T_210, cam[0].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_212 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_213 = eq(cam[0].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_214 = and(_T_212, _T_213) @[el2_dec_decode_ctl.scala 359:136] + node _T_215 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_216 = eq(cam[0].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_217 = and(_T_215, _T_216) @[el2_dec_decode_ctl.scala 359:197] node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_220 = and(_T_219, cam[1].bits.rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:126] - node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] - node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:141] - node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:192] - node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] - node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:207] + node _T_220 = and(_T_219, cam[1].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_221 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_222 = eq(cam[1].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_223 = and(_T_221, _T_222) @[el2_dec_decode_ctl.scala 359:136] + node _T_224 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_225 = eq(cam[1].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_226 = and(_T_224, _T_225) @[el2_dec_decode_ctl.scala 359:197] node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_229 = and(_T_228, cam[2].bits.rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:126] - node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] - node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:141] - node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:192] - node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] - node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:207] + node _T_229 = and(_T_228, cam[2].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_230 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_231 = eq(cam[2].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_232 = and(_T_230, _T_231) @[el2_dec_decode_ctl.scala 359:136] + node _T_233 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_234 = eq(cam[2].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_235 = and(_T_233, _T_234) @[el2_dec_decode_ctl.scala 359:197] node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_238 = and(_T_237, cam[3].bits.rd) @[el2_dec_decode_ctl.scala 359:88] - node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:126] - node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:159] - node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:141] - node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:192] - node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:225] - node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:207] + node _T_238 = and(_T_237, cam[3].rd) @[el2_dec_decode_ctl.scala 359:88] + node _T_239 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:121] + node _T_240 = eq(cam[3].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:149] + node _T_241 = and(_T_239, _T_240) @[el2_dec_decode_ctl.scala 359:136] + node _T_242 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 359:182] + node _T_243 = eq(cam[3].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:210] + node _T_244 = and(_T_242, _T_243) @[el2_dec_decode_ctl.scala 359:197] node _T_245 = or(_T_211, _T_220) @[el2_dec_decode_ctl.scala 360:69] node _T_246 = or(_T_245, _T_229) @[el2_dec_decode_ctl.scala 360:69] node waddr = or(_T_246, _T_238) @[el2_dec_decode_ctl.scala 360:69] @@ -67929,18 +67914,18 @@ circuit el2_swerv_wrapper : io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 463:24] node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 466:30] io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 466:24] - io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 467:23] - node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[el2_dec_decode_ctl.scala 471:39] - node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:53] - node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:51] + io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 467:23] + node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 471:34] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 471:50] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 471:48] io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 471:20] - node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:50] - node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:85] - node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:64] - node _T_358 = and(_T_357, r_d.bits.csrwen) @[el2_dec_decode_ctl.scala 474:100] - node _T_359 = and(_T_358, r_d.valid) @[el2_dec_decode_ctl.scala 474:118] - node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:132] - node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:130] + node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 474:45] + node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 474:75] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 474:59] + node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 474:90] + node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 474:103] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 474:119] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 474:117] io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 474:27] reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 476:52] csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 476:52] @@ -68087,11 +68072,11 @@ circuit el2_swerv_wrapper : reg _T_429 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_429 <= write_csr_data_in @[el2_lib.scala 514:16] write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 508:18] - node _T_430 = bits(r_d.bits.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:49] + node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 514:44] node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 514:30] io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 514:24] - node _T_432 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:43] - node prior_csr_write = or(_T_432, wbd.bits.csrwonly) @[el2_dec_decode_ctl.scala 516:63] + node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 516:38] + node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 516:53] node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 518:67] node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 518:48] node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 519:67] @@ -68211,8 +68196,8 @@ circuit el2_swerv_wrapper : io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 559:29] node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 560:46] io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 560:29] - node prior_inflight = or(x_d.valid, r_d.valid) @[el2_dec_decode_ctl.scala 564:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] + node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 564:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 565:31] node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 567:37] presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 567:22] reg _T_503 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 568:53] @@ -68221,7 +68206,7 @@ circuit el2_swerv_wrapper : node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 570:56] node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 570:54] node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 570:39] - node _T_507 = and(postsync_stall, x_d.valid) @[el2_dec_decode_ctl.scala 570:88] + node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 570:88] node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 570:69] ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 570:15] node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 572:50] @@ -68232,8 +68217,8 @@ circuit el2_swerv_wrapper : mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 575:16] node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 576:40] div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 576:16] - node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:45] - node _T_514 = and(r_d.valid, _T_513) @[el2_dec_decode_ctl.scala 578:43] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 578:47] + node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 578:45] io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 578:29] d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 581:26] node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 582:40] @@ -68370,7 +68355,7 @@ circuit el2_swerv_wrapper : r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 605:10] r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 605:10] r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 605:10] - node _T_536 = or(r_d.bits.i0load, r_d.bits.i0store) @[el2_dec_decode_ctl.scala 607:61] + node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 607:56] wire _T_537 : UInt<1>[4] @[el2_lib.scala 162:48] _T_537[0] <= _T_536 @[el2_lib.scala 162:48] _T_537[1] <= _T_536 @[el2_lib.scala 162:48] @@ -68379,8 +68364,8 @@ circuit el2_swerv_wrapper : node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] - node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:82] - node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:105] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 607:72] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 607:95] r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 607:33] r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 608:33] node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 610:35] @@ -68417,7 +68402,7 @@ circuit el2_swerv_wrapper : io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 612:39] io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 612:39] - node _T_545 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 613:58] + node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 613:53] io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 613:39] reg _T_546 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 616:52] _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 616:52] @@ -68737,22 +68722,22 @@ circuit el2_swerv_wrapper : io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 662:27] node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 663:27] - d_d.bits.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:34] - node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:50] - d_d.bits.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:34] - d_d.valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:27] - node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:50] - d_d.bits.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:34] - node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:50] - d_d.bits.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:34] - node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:50] - d_d.bits.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:34] - node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:61] - d_d.bits.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:34] - node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:58] - d_d.bits.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:34] - node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:40] - d_d.bits.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:34] + d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 665:29] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 666:45] + d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 666:29] + d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 667:29] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 669:45] + d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 669:29] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:45] + d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 670:29] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 671:45] + d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 671:29] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:56] + d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 673:29] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 674:53] + d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 674:29] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 675:35] + d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 675:29] node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 677:34] inst rvclkhdr_7 of rvclkhdr_668 @[el2_lib.scala 518:23] rvclkhdr_7.clock <= clock @@ -68760,55 +68745,55 @@ circuit el2_swerv_wrapper : rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_7.io.en <= _T_729 @[el2_lib.scala 521:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_730 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_730.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_730.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_730.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_731 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] - _T_731.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16] - _T_731.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16] - _T_731.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16] - _T_731.bits.i0v <= d_d.bits.i0v @[el2_lib.scala 524:16] - _T_731.bits.i0div <= d_d.bits.i0div @[el2_lib.scala 524:16] - _T_731.bits.i0store <= d_d.bits.i0store @[el2_lib.scala 524:16] - _T_731.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16] - _T_731.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16] - _T_731.valid <= d_d.valid @[el2_lib.scala 524:16] - x_d.bits.csrwaddr <= _T_731.bits.csrwaddr @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.csrwonly <= _T_731.bits.csrwonly @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.csrwen <= _T_731.bits.csrwen @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0v <= _T_731.bits.i0v @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0div <= _T_731.bits.i0div @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0store <= _T_731.bits.i0store @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0load <= _T_731.bits.i0load @[el2_dec_decode_ctl.scala 677:7] - x_d.bits.i0rd <= _T_731.bits.i0rd @[el2_dec_decode_ctl.scala 677:7] - x_d.valid <= _T_731.valid @[el2_dec_decode_ctl.scala 677:7] - wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_dec_decode_ctl.scala 678:20] - x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.csrwen <= x_d.bits.csrwen @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0v <= x_d.bits.i0v @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0div <= x_d.bits.i0div @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0store <= x_d.bits.i0store @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0load <= x_d.bits.i0load @[el2_dec_decode_ctl.scala 679:10] - x_d_in.bits.i0rd <= x_d.bits.i0rd @[el2_dec_decode_ctl.scala 679:10] - x_d_in.valid <= x_d.valid @[el2_dec_decode_ctl.scala 679:10] - node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:49] - node _T_733 = and(x_d.bits.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:47] - node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:78] - node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:76] - x_d_in.bits.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:27] - node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:35] - node _T_737 = and(x_d.valid, _T_736) @[el2_dec_decode_ctl.scala 681:33] - node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:64] - node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:62] - x_d_in.valid <= _T_739 @[el2_dec_decode_ctl.scala 681:20] + wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] + _T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 524:16] + _T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 524:16] + _T_731.csrwen <= d_d.csrwen @[el2_lib.scala 524:16] + _T_731.i0valid <= d_d.i0valid @[el2_lib.scala 524:16] + _T_731.i0v <= d_d.i0v @[el2_lib.scala 524:16] + _T_731.i0div <= d_d.i0div @[el2_lib.scala 524:16] + _T_731.i0store <= d_d.i0store @[el2_lib.scala 524:16] + _T_731.i0load <= d_d.i0load @[el2_lib.scala 524:16] + _T_731.i0rd <= d_d.i0rd @[el2_lib.scala 524:16] + x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 677:7] + x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 677:7] + x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 677:7] + x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 677:7] + x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 677:7] + x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 677:7] + x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 677:7] + x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 677:7] + wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 678:20] + x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 679:10] + x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 679:10] + x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 679:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:39] + node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 680:37] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 680:68] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 680:66] + x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 680:22] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:39] + node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 681:37] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 681:68] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 681:66] + x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 681:22] node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 683:36] inst rvclkhdr_8 of rvclkhdr_669 @[el2_lib.scala 518:23] rvclkhdr_8.clock <= clock @@ -68816,57 +68801,57 @@ circuit el2_swerv_wrapper : rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_8.io.en <= _T_740 @[el2_lib.scala 521:17] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_741 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_741.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_741.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_741.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_742 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] - _T_742.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_742.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_742.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_742.bits.i0v <= x_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_742.bits.i0div <= x_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_742.bits.i0store <= x_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_742.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_742.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_742.valid <= x_d_in.valid @[el2_lib.scala 524:16] - r_d.bits.csrwaddr <= _T_742.bits.csrwaddr @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.csrwonly <= _T_742.bits.csrwonly @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.csrwen <= _T_742.bits.csrwen @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0v <= _T_742.bits.i0v @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0div <= _T_742.bits.i0div @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0store <= _T_742.bits.i0store @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0load <= _T_742.bits.i0load @[el2_dec_decode_ctl.scala 683:7] - r_d.bits.i0rd <= _T_742.bits.i0rd @[el2_dec_decode_ctl.scala 683:7] - r_d.valid <= _T_742.valid @[el2_dec_decode_ctl.scala 683:7] - r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.csrwen <= r_d.bits.csrwen @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0v <= r_d.bits.i0v @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0div <= r_d.bits.i0div @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0store <= r_d.bits.i0store @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0load <= r_d.bits.i0load @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 684:10] - r_d_in.valid <= r_d.valid @[el2_dec_decode_ctl.scala 684:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[el2_dec_decode_ctl.scala 685:22] - node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:51] - node _T_744 = and(r_d.bits.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:49] - r_d_in.bits.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:27] - node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:37] - node _T_746 = and(r_d.valid, _T_745) @[el2_dec_decode_ctl.scala 688:35] - r_d_in.valid <= _T_746 @[el2_dec_decode_ctl.scala 688:20] - node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:51] - node _T_748 = and(r_d.bits.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:49] - r_d_in.bits.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:27] - node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:51] - node _T_750 = and(r_d.bits.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:49] - r_d_in.bits.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:27] + wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] + _T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 524:16] + _T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 524:16] + _T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 524:16] + _T_742.i0v <= x_d_in.i0v @[el2_lib.scala 524:16] + _T_742.i0div <= x_d_in.i0div @[el2_lib.scala 524:16] + _T_742.i0store <= x_d_in.i0store @[el2_lib.scala 524:16] + _T_742.i0load <= x_d_in.i0load @[el2_lib.scala 524:16] + _T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 524:16] + r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 683:7] + r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 683:7] + r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 683:7] + r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 683:7] + r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 683:7] + r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 683:7] + r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 683:7] + r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 683:7] + r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 684:10] + r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 684:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 685:17] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 687:41] + node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 687:39] + r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 687:22] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 688:41] + node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 688:39] + r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 688:22] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 689:41] + node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 689:39] + r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 689:22] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 690:41] + node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 690:39] + r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 690:22] node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 692:37] inst rvclkhdr_9 of rvclkhdr_670 @[el2_lib.scala 518:23] rvclkhdr_9.clock <= clock @@ -68874,43 +68859,43 @@ circuit el2_swerv_wrapper : rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18] rvclkhdr_9.io.en <= _T_751 @[el2_lib.scala 521:17] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_752 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_752.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_752.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_752.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_753 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] - _T_753.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_753.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_753.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_753.bits.i0v <= r_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_753.bits.i0div <= r_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_753.bits.i0store <= r_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_753.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_753.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_753.valid <= r_d_in.valid @[el2_lib.scala 524:16] - wbd.bits.csrwaddr <= _T_753.bits.csrwaddr @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.csrwonly <= _T_753.bits.csrwonly @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.csrwen <= _T_753.bits.csrwen @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0v <= _T_753.bits.i0v @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0div <= _T_753.bits.i0div @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0store <= _T_753.bits.i0store @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0load <= _T_753.bits.i0load @[el2_dec_decode_ctl.scala 692:7] - wbd.bits.i0rd <= _T_753.bits.i0rd @[el2_dec_decode_ctl.scala 692:7] - wbd.valid <= _T_753.valid @[el2_dec_decode_ctl.scala 692:7] - io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[el2_dec_decode_ctl.scala 694:27] - node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:47] - node _T_755 = and(r_d_in.bits.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:45] + wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] + _T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 524:16] + _T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 524:16] + _T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 524:16] + _T_753.i0v <= r_d_in.i0v @[el2_lib.scala 524:16] + _T_753.i0div <= r_d_in.i0div @[el2_lib.scala 524:16] + _T_753.i0store <= r_d_in.i0store @[el2_lib.scala 524:16] + _T_753.i0load <= r_d_in.i0load @[el2_lib.scala 524:16] + _T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 524:16] + wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 692:7] + wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 692:7] + wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 692:7] + wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 692:7] + wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 692:7] + wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 692:7] + wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 692:7] + wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 692:7] + io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 694:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 695:42] + node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 695:40] i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 695:25] - node _T_756 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] + node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:49] node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 696:47] - node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:70] - node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:68] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 696:65] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 696:63] io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 696:32] io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 697:26] node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 699:57] @@ -68922,13 +68907,13 @@ circuit el2_swerv_wrapper : rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] - node _T_761 = and(x_d.bits.i0v, x_d.bits.i0load) @[el2_dec_decode_ctl.scala 705:47] - node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:66] + node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 705:42] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 705:56] node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 705:32] i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 705:26] i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 706:26] - node _T_764 = and(r_d.bits.i0v, r_d.bits.i0load) @[el2_dec_decode_ctl.scala 710:42] - node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:61] + node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 710:37] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 710:51] node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 710:27] i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 710:21] node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 711:54] @@ -68997,25 +68982,25 @@ circuit el2_swerv_wrapper : reg _T_798 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_798 <= last_br_immed_d @[el2_lib.scala 514:16] last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 715:19] - node _T_799 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 719:45] - node _T_800 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 719:76] - node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:58] - node _T_801 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 721:48] - node _T_802 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:77] - node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:60] - node _T_804 = and(x_d.bits.i0div, x_d.valid) @[el2_dec_decode_ctl.scala 722:21] - node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:33] - node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:94] - node _T_807 = and(r_d.bits.i0div, r_d.valid) @[el2_dec_decode_ctl.scala 723:21] - node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:33] - node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:60] - node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:62] + node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 719:40] + node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 719:68] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 719:55] + node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 721:43] + node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 721:69] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 721:57] + node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 722:16] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 722:30] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 721:86] + node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 723:16] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 723:30] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 723:57] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 722:59] node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 727:51] node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 728:26] node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 728:24] - node _T_813 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:56] + node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 728:51] node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 728:39] - node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:77] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 728:72] node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 727:65] node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 730:53] io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 730:29] @@ -69155,18 +69140,18 @@ circuit el2_swerv_wrapper : node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 764:51] io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 764:25] - node _T_876 = and(io.dec_i0_rs1_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 768:48] - node _T_877 = eq(x_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:80] - node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:63] - node _T_878 = and(io.dec_i0_rs1_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 769:48] - node _T_879 = eq(r_d.bits.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:80] - node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:63] - node _T_880 = and(io.dec_i0_rs2_en_d, x_d.bits.i0v) @[el2_dec_decode_ctl.scala 771:48] - node _T_881 = eq(x_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:80] - node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:63] - node _T_882 = and(io.dec_i0_rs2_en_d, r_d.bits.i0v) @[el2_dec_decode_ctl.scala 772:48] - node _T_883 = eq(r_d.bits.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:80] - node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:63] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 768:48] + node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 768:70] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 768:58] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 769:48] + node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 769:70] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 769:58] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 771:48] + node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 771:70] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 771:58] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 772:70] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 772:58] node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 774:44] node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 774:81] wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 774:109] @@ -70075,766 +70060,927 @@ circuit el2_swerv_wrapper : output io : {flip raddr0 : UInt<5>, flip raddr1 : UInt<5>, flip wen0 : UInt<1>, flip waddr0 : UInt<5>, flip wd0 : UInt<32>, flip wen1 : UInt<1>, flip waddr1 : UInt<5>, flip wd1 : UInt<32>, flip wen2 : UInt<1>, flip waddr2 : UInt<5>, flip wd2 : UInt<32>, rd0 : UInt<32>, rd1 : UInt<32>, flip scan_mode : UInt<1>} wire w0v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 10:30] - wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 11:30] - wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 12:30] - wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 13:22] - wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 14:22] - wire gpr_wr_en : UInt<32> @[el2_dec_gpr_ctl.scala 15:22] - w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 16:9] - w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:9] - w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 18:9] - gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 19:13] - gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:12] - io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 21:9] - io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 22:9] - node _T = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] - node _T_1 = cat(w0v[2], _T) @[Cat.scala 29:58] - node _T_2 = cat(w0v[3], _T_1) @[Cat.scala 29:58] - node _T_3 = cat(w0v[4], _T_2) @[Cat.scala 29:58] - node _T_4 = cat(w0v[5], _T_3) @[Cat.scala 29:58] - node _T_5 = cat(w0v[6], _T_4) @[Cat.scala 29:58] - node _T_6 = cat(w0v[7], _T_5) @[Cat.scala 29:58] - node _T_7 = cat(w0v[8], _T_6) @[Cat.scala 29:58] - node _T_8 = cat(w0v[9], _T_7) @[Cat.scala 29:58] - node _T_9 = cat(w0v[10], _T_8) @[Cat.scala 29:58] - node _T_10 = cat(w0v[11], _T_9) @[Cat.scala 29:58] - node _T_11 = cat(w0v[12], _T_10) @[Cat.scala 29:58] - node _T_12 = cat(w0v[13], _T_11) @[Cat.scala 29:58] - node _T_13 = cat(w0v[14], _T_12) @[Cat.scala 29:58] - node _T_14 = cat(w0v[15], _T_13) @[Cat.scala 29:58] - node _T_15 = cat(w0v[16], _T_14) @[Cat.scala 29:58] - node _T_16 = cat(w0v[17], _T_15) @[Cat.scala 29:58] - node _T_17 = cat(w0v[18], _T_16) @[Cat.scala 29:58] - node _T_18 = cat(w0v[19], _T_17) @[Cat.scala 29:58] - node _T_19 = cat(w0v[20], _T_18) @[Cat.scala 29:58] - node _T_20 = cat(w0v[21], _T_19) @[Cat.scala 29:58] - node _T_21 = cat(w0v[22], _T_20) @[Cat.scala 29:58] - node _T_22 = cat(w0v[23], _T_21) @[Cat.scala 29:58] - node _T_23 = cat(w0v[24], _T_22) @[Cat.scala 29:58] - node _T_24 = cat(w0v[25], _T_23) @[Cat.scala 29:58] - node _T_25 = cat(w0v[26], _T_24) @[Cat.scala 29:58] - node _T_26 = cat(w0v[27], _T_25) @[Cat.scala 29:58] - node _T_27 = cat(w0v[28], _T_26) @[Cat.scala 29:58] - node _T_28 = cat(w0v[29], _T_27) @[Cat.scala 29:58] - node _T_29 = cat(w0v[30], _T_28) @[Cat.scala 29:58] - node _T_30 = cat(w0v[31], _T_29) @[Cat.scala 29:58] - node _T_31 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] - node _T_32 = cat(w1v[2], _T_31) @[Cat.scala 29:58] - node _T_33 = cat(w1v[3], _T_32) @[Cat.scala 29:58] - node _T_34 = cat(w1v[4], _T_33) @[Cat.scala 29:58] - node _T_35 = cat(w1v[5], _T_34) @[Cat.scala 29:58] - node _T_36 = cat(w1v[6], _T_35) @[Cat.scala 29:58] - node _T_37 = cat(w1v[7], _T_36) @[Cat.scala 29:58] - node _T_38 = cat(w1v[8], _T_37) @[Cat.scala 29:58] - node _T_39 = cat(w1v[9], _T_38) @[Cat.scala 29:58] - node _T_40 = cat(w1v[10], _T_39) @[Cat.scala 29:58] - node _T_41 = cat(w1v[11], _T_40) @[Cat.scala 29:58] - node _T_42 = cat(w1v[12], _T_41) @[Cat.scala 29:58] - node _T_43 = cat(w1v[13], _T_42) @[Cat.scala 29:58] - node _T_44 = cat(w1v[14], _T_43) @[Cat.scala 29:58] - node _T_45 = cat(w1v[15], _T_44) @[Cat.scala 29:58] - node _T_46 = cat(w1v[16], _T_45) @[Cat.scala 29:58] - node _T_47 = cat(w1v[17], _T_46) @[Cat.scala 29:58] - node _T_48 = cat(w1v[18], _T_47) @[Cat.scala 29:58] - node _T_49 = cat(w1v[19], _T_48) @[Cat.scala 29:58] - node _T_50 = cat(w1v[20], _T_49) @[Cat.scala 29:58] - node _T_51 = cat(w1v[21], _T_50) @[Cat.scala 29:58] - node _T_52 = cat(w1v[22], _T_51) @[Cat.scala 29:58] - node _T_53 = cat(w1v[23], _T_52) @[Cat.scala 29:58] - node _T_54 = cat(w1v[24], _T_53) @[Cat.scala 29:58] - node _T_55 = cat(w1v[25], _T_54) @[Cat.scala 29:58] - node _T_56 = cat(w1v[26], _T_55) @[Cat.scala 29:58] - node _T_57 = cat(w1v[27], _T_56) @[Cat.scala 29:58] - node _T_58 = cat(w1v[28], _T_57) @[Cat.scala 29:58] - node _T_59 = cat(w1v[29], _T_58) @[Cat.scala 29:58] - node _T_60 = cat(w1v[30], _T_59) @[Cat.scala 29:58] - node _T_61 = cat(w1v[31], _T_60) @[Cat.scala 29:58] - node _T_62 = or(_T_30, _T_61) @[el2_dec_gpr_ctl.scala 23:51] - node _T_63 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] - node _T_64 = cat(w2v[2], _T_63) @[Cat.scala 29:58] - node _T_65 = cat(w2v[3], _T_64) @[Cat.scala 29:58] - node _T_66 = cat(w2v[4], _T_65) @[Cat.scala 29:58] - node _T_67 = cat(w2v[5], _T_66) @[Cat.scala 29:58] - node _T_68 = cat(w2v[6], _T_67) @[Cat.scala 29:58] - node _T_69 = cat(w2v[7], _T_68) @[Cat.scala 29:58] - node _T_70 = cat(w2v[8], _T_69) @[Cat.scala 29:58] - node _T_71 = cat(w2v[9], _T_70) @[Cat.scala 29:58] - node _T_72 = cat(w2v[10], _T_71) @[Cat.scala 29:58] - node _T_73 = cat(w2v[11], _T_72) @[Cat.scala 29:58] - node _T_74 = cat(w2v[12], _T_73) @[Cat.scala 29:58] - node _T_75 = cat(w2v[13], _T_74) @[Cat.scala 29:58] - node _T_76 = cat(w2v[14], _T_75) @[Cat.scala 29:58] - node _T_77 = cat(w2v[15], _T_76) @[Cat.scala 29:58] - node _T_78 = cat(w2v[16], _T_77) @[Cat.scala 29:58] - node _T_79 = cat(w2v[17], _T_78) @[Cat.scala 29:58] - node _T_80 = cat(w2v[18], _T_79) @[Cat.scala 29:58] - node _T_81 = cat(w2v[19], _T_80) @[Cat.scala 29:58] - node _T_82 = cat(w2v[20], _T_81) @[Cat.scala 29:58] - node _T_83 = cat(w2v[21], _T_82) @[Cat.scala 29:58] - node _T_84 = cat(w2v[22], _T_83) @[Cat.scala 29:58] - node _T_85 = cat(w2v[23], _T_84) @[Cat.scala 29:58] - node _T_86 = cat(w2v[24], _T_85) @[Cat.scala 29:58] - node _T_87 = cat(w2v[25], _T_86) @[Cat.scala 29:58] - node _T_88 = cat(w2v[26], _T_87) @[Cat.scala 29:58] - node _T_89 = cat(w2v[27], _T_88) @[Cat.scala 29:58] - node _T_90 = cat(w2v[28], _T_89) @[Cat.scala 29:58] - node _T_91 = cat(w2v[29], _T_90) @[Cat.scala 29:58] - node _T_92 = cat(w2v[30], _T_91) @[Cat.scala 29:58] - node _T_93 = cat(w2v[31], _T_92) @[Cat.scala 29:58] - node _T_94 = or(_T_62, _T_93) @[el2_dec_gpr_ctl.scala 23:89] - gpr_wr_en <= _T_94 @[el2_dec_gpr_ctl.scala 23:12] - node _T_95 = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_96 = and(io.wen0, _T_95) @[el2_dec_gpr_ctl.scala 26:28] - w0v[1] <= _T_96 @[el2_dec_gpr_ctl.scala 26:16] - node _T_97 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_98 = and(io.wen1, _T_97) @[el2_dec_gpr_ctl.scala 27:28] - w1v[1] <= _T_98 @[el2_dec_gpr_ctl.scala 27:16] - node _T_99 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_100 = and(io.wen2, _T_99) @[el2_dec_gpr_ctl.scala 28:28] - w2v[1] <= _T_100 @[el2_dec_gpr_ctl.scala 28:16] - node _T_101 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] - node _T_102 = mux(_T_101, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_103 = and(_T_102, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_104 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] - node _T_105 = mux(_T_104, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_106 = and(_T_105, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_107 = or(_T_103, _T_106) @[el2_dec_gpr_ctl.scala 29:47] - node _T_108 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + w0v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 11:7] + wire w1v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 13:30] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + w1v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 14:7] + wire w2v : UInt<1>[32] @[el2_dec_gpr_ctl.scala 16:30] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + w2v[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 17:7] + wire gpr_in : UInt<32>[32] @[el2_dec_gpr_ctl.scala 19:22] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + gpr_in[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 20:10] + wire gpr_out : UInt<32>[32] @[el2_dec_gpr_ctl.scala 22:22] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[1] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[2] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[3] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[4] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[5] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[6] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[7] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[8] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[9] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[10] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[11] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[12] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[13] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[14] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[15] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[16] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[17] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[18] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[19] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[20] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[21] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[22] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[23] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[24] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[25] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[26] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[27] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[28] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[29] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[30] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + gpr_out[31] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 23:11] + wire gpr_wr_en : UInt<32> + gpr_wr_en <= UInt<1>("h00") + w0v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 26:9] + w1v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 27:9] + w2v[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 28:9] + gpr_out[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 29:13] + gpr_in[0] <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 30:12] + io.rd0 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 31:9] + io.rd1 <= UInt<1>("h00") @[el2_dec_gpr_ctl.scala 32:9] + node _T = eq(io.waddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_1 = and(io.wen0, _T) @[el2_dec_gpr_ctl.scala 35:28] + w0v[1] <= _T_1 @[el2_dec_gpr_ctl.scala 35:16] + node _T_2 = eq(io.waddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_3 = and(io.wen1, _T_2) @[el2_dec_gpr_ctl.scala 36:28] + w1v[1] <= _T_3 @[el2_dec_gpr_ctl.scala 36:16] + node _T_4 = eq(io.waddr2, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_5 = and(io.wen2, _T_4) @[el2_dec_gpr_ctl.scala 37:28] + w2v[1] <= _T_5 @[el2_dec_gpr_ctl.scala 37:16] + node _T_6 = bits(w0v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_7 = mux(_T_6, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_8 = and(_T_7, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_9 = bits(w1v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_10 = mux(_T_9, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_11 = and(_T_10, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_12 = or(_T_8, _T_11) @[el2_dec_gpr_ctl.scala 38:47] + node _T_13 = bits(w2v[1], 0, 0) @[Bitwise.scala 72:15] + node _T_14 = mux(_T_13, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_15 = and(_T_14, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_16 = or(_T_12, _T_15) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[1] <= _T_16 @[el2_dec_gpr_ctl.scala 38:16] + node _T_17 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_18 = and(io.wen0, _T_17) @[el2_dec_gpr_ctl.scala 35:28] + w0v[2] <= _T_18 @[el2_dec_gpr_ctl.scala 35:16] + node _T_19 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_20 = and(io.wen1, _T_19) @[el2_dec_gpr_ctl.scala 36:28] + w1v[2] <= _T_20 @[el2_dec_gpr_ctl.scala 36:16] + node _T_21 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_22 = and(io.wen2, _T_21) @[el2_dec_gpr_ctl.scala 37:28] + w2v[2] <= _T_22 @[el2_dec_gpr_ctl.scala 37:16] + node _T_23 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_24 = mux(_T_23, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_25 = and(_T_24, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_26 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_27 = mux(_T_26, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_28 = and(_T_27, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_29 = or(_T_25, _T_28) @[el2_dec_gpr_ctl.scala 38:47] + node _T_30 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_31 = mux(_T_30, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_32 = and(_T_31, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_33 = or(_T_29, _T_32) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[2] <= _T_33 @[el2_dec_gpr_ctl.scala 38:16] + node _T_34 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_35 = and(io.wen0, _T_34) @[el2_dec_gpr_ctl.scala 35:28] + w0v[3] <= _T_35 @[el2_dec_gpr_ctl.scala 35:16] + node _T_36 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_37 = and(io.wen1, _T_36) @[el2_dec_gpr_ctl.scala 36:28] + w1v[3] <= _T_37 @[el2_dec_gpr_ctl.scala 36:16] + node _T_38 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_39 = and(io.wen2, _T_38) @[el2_dec_gpr_ctl.scala 37:28] + w2v[3] <= _T_39 @[el2_dec_gpr_ctl.scala 37:16] + node _T_40 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_41 = mux(_T_40, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_42 = and(_T_41, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_43 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_44 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_45 = and(_T_44, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_46 = or(_T_42, _T_45) @[el2_dec_gpr_ctl.scala 38:47] + node _T_47 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_48 = mux(_T_47, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_49 = and(_T_48, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_50 = or(_T_46, _T_49) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[3] <= _T_50 @[el2_dec_gpr_ctl.scala 38:16] + node _T_51 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_52 = and(io.wen0, _T_51) @[el2_dec_gpr_ctl.scala 35:28] + w0v[4] <= _T_52 @[el2_dec_gpr_ctl.scala 35:16] + node _T_53 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_54 = and(io.wen1, _T_53) @[el2_dec_gpr_ctl.scala 36:28] + w1v[4] <= _T_54 @[el2_dec_gpr_ctl.scala 36:16] + node _T_55 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_56 = and(io.wen2, _T_55) @[el2_dec_gpr_ctl.scala 37:28] + w2v[4] <= _T_56 @[el2_dec_gpr_ctl.scala 37:16] + node _T_57 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_58 = mux(_T_57, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_59 = and(_T_58, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_60 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_61 = mux(_T_60, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_62 = and(_T_61, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_63 = or(_T_59, _T_62) @[el2_dec_gpr_ctl.scala 38:47] + node _T_64 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_65 = mux(_T_64, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_66 = and(_T_65, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_67 = or(_T_63, _T_66) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[4] <= _T_67 @[el2_dec_gpr_ctl.scala 38:16] + node _T_68 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_69 = and(io.wen0, _T_68) @[el2_dec_gpr_ctl.scala 35:28] + w0v[5] <= _T_69 @[el2_dec_gpr_ctl.scala 35:16] + node _T_70 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_71 = and(io.wen1, _T_70) @[el2_dec_gpr_ctl.scala 36:28] + w1v[5] <= _T_71 @[el2_dec_gpr_ctl.scala 36:16] + node _T_72 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_73 = and(io.wen2, _T_72) @[el2_dec_gpr_ctl.scala 37:28] + w2v[5] <= _T_73 @[el2_dec_gpr_ctl.scala 37:16] + node _T_74 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_75 = mux(_T_74, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_76 = and(_T_75, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_77 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_79 = and(_T_78, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_80 = or(_T_76, _T_79) @[el2_dec_gpr_ctl.scala 38:47] + node _T_81 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_82 = mux(_T_81, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_83 = and(_T_82, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_84 = or(_T_80, _T_83) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[5] <= _T_84 @[el2_dec_gpr_ctl.scala 38:16] + node _T_85 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_86 = and(io.wen0, _T_85) @[el2_dec_gpr_ctl.scala 35:28] + w0v[6] <= _T_86 @[el2_dec_gpr_ctl.scala 35:16] + node _T_87 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_88 = and(io.wen1, _T_87) @[el2_dec_gpr_ctl.scala 36:28] + w1v[6] <= _T_88 @[el2_dec_gpr_ctl.scala 36:16] + node _T_89 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_90 = and(io.wen2, _T_89) @[el2_dec_gpr_ctl.scala 37:28] + w2v[6] <= _T_90 @[el2_dec_gpr_ctl.scala 37:16] + node _T_91 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_92 = mux(_T_91, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_93 = and(_T_92, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_94 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_95 = mux(_T_94, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_96 = and(_T_95, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_97 = or(_T_93, _T_96) @[el2_dec_gpr_ctl.scala 38:47] + node _T_98 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_101 = or(_T_97, _T_100) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[6] <= _T_101 @[el2_dec_gpr_ctl.scala 38:16] + node _T_102 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_103 = and(io.wen0, _T_102) @[el2_dec_gpr_ctl.scala 35:28] + w0v[7] <= _T_103 @[el2_dec_gpr_ctl.scala 35:16] + node _T_104 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_105 = and(io.wen1, _T_104) @[el2_dec_gpr_ctl.scala 36:28] + w1v[7] <= _T_105 @[el2_dec_gpr_ctl.scala 36:16] + node _T_106 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_107 = and(io.wen2, _T_106) @[el2_dec_gpr_ctl.scala 37:28] + w2v[7] <= _T_107 @[el2_dec_gpr_ctl.scala 37:16] + node _T_108 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] node _T_109 = mux(_T_108, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_110 = and(_T_109, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_111 = or(_T_107, _T_110) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[1] <= _T_111 @[el2_dec_gpr_ctl.scala 29:16] - node _T_112 = eq(io.waddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_113 = and(io.wen0, _T_112) @[el2_dec_gpr_ctl.scala 26:28] - w0v[2] <= _T_113 @[el2_dec_gpr_ctl.scala 26:16] - node _T_114 = eq(io.waddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_115 = and(io.wen1, _T_114) @[el2_dec_gpr_ctl.scala 27:28] - w1v[2] <= _T_115 @[el2_dec_gpr_ctl.scala 27:16] - node _T_116 = eq(io.waddr2, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_117 = and(io.wen2, _T_116) @[el2_dec_gpr_ctl.scala 28:28] - w2v[2] <= _T_117 @[el2_dec_gpr_ctl.scala 28:16] - node _T_118 = bits(w0v[2], 0, 0) @[Bitwise.scala 72:15] - node _T_119 = mux(_T_118, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_120 = and(_T_119, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_121 = bits(w1v[2], 0, 0) @[Bitwise.scala 72:15] - node _T_122 = mux(_T_121, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_123 = and(_T_122, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_124 = or(_T_120, _T_123) @[el2_dec_gpr_ctl.scala 29:47] - node _T_125 = bits(w2v[2], 0, 0) @[Bitwise.scala 72:15] + node _T_110 = and(_T_109, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_111 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_113 = and(_T_112, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_114 = or(_T_110, _T_113) @[el2_dec_gpr_ctl.scala 38:47] + node _T_115 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_116 = mux(_T_115, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_117 = and(_T_116, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_118 = or(_T_114, _T_117) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[7] <= _T_118 @[el2_dec_gpr_ctl.scala 38:16] + node _T_119 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_120 = and(io.wen0, _T_119) @[el2_dec_gpr_ctl.scala 35:28] + w0v[8] <= _T_120 @[el2_dec_gpr_ctl.scala 35:16] + node _T_121 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_122 = and(io.wen1, _T_121) @[el2_dec_gpr_ctl.scala 36:28] + w1v[8] <= _T_122 @[el2_dec_gpr_ctl.scala 36:16] + node _T_123 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_124 = and(io.wen2, _T_123) @[el2_dec_gpr_ctl.scala 37:28] + w2v[8] <= _T_124 @[el2_dec_gpr_ctl.scala 37:16] + node _T_125 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] node _T_126 = mux(_T_125, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_127 = and(_T_126, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_128 = or(_T_124, _T_127) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[2] <= _T_128 @[el2_dec_gpr_ctl.scala 29:16] - node _T_129 = eq(io.waddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_130 = and(io.wen0, _T_129) @[el2_dec_gpr_ctl.scala 26:28] - w0v[3] <= _T_130 @[el2_dec_gpr_ctl.scala 26:16] - node _T_131 = eq(io.waddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_132 = and(io.wen1, _T_131) @[el2_dec_gpr_ctl.scala 27:28] - w1v[3] <= _T_132 @[el2_dec_gpr_ctl.scala 27:16] - node _T_133 = eq(io.waddr2, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_134 = and(io.wen2, _T_133) @[el2_dec_gpr_ctl.scala 28:28] - w2v[3] <= _T_134 @[el2_dec_gpr_ctl.scala 28:16] - node _T_135 = bits(w0v[3], 0, 0) @[Bitwise.scala 72:15] - node _T_136 = mux(_T_135, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_137 = and(_T_136, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_138 = bits(w1v[3], 0, 0) @[Bitwise.scala 72:15] - node _T_139 = mux(_T_138, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_140 = and(_T_139, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_141 = or(_T_137, _T_140) @[el2_dec_gpr_ctl.scala 29:47] - node _T_142 = bits(w2v[3], 0, 0) @[Bitwise.scala 72:15] + node _T_127 = and(_T_126, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_128 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_129 = mux(_T_128, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_130 = and(_T_129, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_131 = or(_T_127, _T_130) @[el2_dec_gpr_ctl.scala 38:47] + node _T_132 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_133 = mux(_T_132, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_134 = and(_T_133, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_135 = or(_T_131, _T_134) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[8] <= _T_135 @[el2_dec_gpr_ctl.scala 38:16] + node _T_136 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_137 = and(io.wen0, _T_136) @[el2_dec_gpr_ctl.scala 35:28] + w0v[9] <= _T_137 @[el2_dec_gpr_ctl.scala 35:16] + node _T_138 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_139 = and(io.wen1, _T_138) @[el2_dec_gpr_ctl.scala 36:28] + w1v[9] <= _T_139 @[el2_dec_gpr_ctl.scala 36:16] + node _T_140 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_141 = and(io.wen2, _T_140) @[el2_dec_gpr_ctl.scala 37:28] + w2v[9] <= _T_141 @[el2_dec_gpr_ctl.scala 37:16] + node _T_142 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] node _T_143 = mux(_T_142, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_144 = and(_T_143, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_145 = or(_T_141, _T_144) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[3] <= _T_145 @[el2_dec_gpr_ctl.scala 29:16] - node _T_146 = eq(io.waddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_147 = and(io.wen0, _T_146) @[el2_dec_gpr_ctl.scala 26:28] - w0v[4] <= _T_147 @[el2_dec_gpr_ctl.scala 26:16] - node _T_148 = eq(io.waddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_149 = and(io.wen1, _T_148) @[el2_dec_gpr_ctl.scala 27:28] - w1v[4] <= _T_149 @[el2_dec_gpr_ctl.scala 27:16] - node _T_150 = eq(io.waddr2, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_151 = and(io.wen2, _T_150) @[el2_dec_gpr_ctl.scala 28:28] - w2v[4] <= _T_151 @[el2_dec_gpr_ctl.scala 28:16] - node _T_152 = bits(w0v[4], 0, 0) @[Bitwise.scala 72:15] - node _T_153 = mux(_T_152, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_154 = and(_T_153, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_155 = bits(w1v[4], 0, 0) @[Bitwise.scala 72:15] - node _T_156 = mux(_T_155, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_157 = and(_T_156, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_158 = or(_T_154, _T_157) @[el2_dec_gpr_ctl.scala 29:47] - node _T_159 = bits(w2v[4], 0, 0) @[Bitwise.scala 72:15] + node _T_144 = and(_T_143, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_145 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_146 = mux(_T_145, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_147 = and(_T_146, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_148 = or(_T_144, _T_147) @[el2_dec_gpr_ctl.scala 38:47] + node _T_149 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_150 = mux(_T_149, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_151 = and(_T_150, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_152 = or(_T_148, _T_151) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[9] <= _T_152 @[el2_dec_gpr_ctl.scala 38:16] + node _T_153 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_154 = and(io.wen0, _T_153) @[el2_dec_gpr_ctl.scala 35:28] + w0v[10] <= _T_154 @[el2_dec_gpr_ctl.scala 35:16] + node _T_155 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_156 = and(io.wen1, _T_155) @[el2_dec_gpr_ctl.scala 36:28] + w1v[10] <= _T_156 @[el2_dec_gpr_ctl.scala 36:16] + node _T_157 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_158 = and(io.wen2, _T_157) @[el2_dec_gpr_ctl.scala 37:28] + w2v[10] <= _T_158 @[el2_dec_gpr_ctl.scala 37:16] + node _T_159 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] node _T_160 = mux(_T_159, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_161 = and(_T_160, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_162 = or(_T_158, _T_161) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[4] <= _T_162 @[el2_dec_gpr_ctl.scala 29:16] - node _T_163 = eq(io.waddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_164 = and(io.wen0, _T_163) @[el2_dec_gpr_ctl.scala 26:28] - w0v[5] <= _T_164 @[el2_dec_gpr_ctl.scala 26:16] - node _T_165 = eq(io.waddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_166 = and(io.wen1, _T_165) @[el2_dec_gpr_ctl.scala 27:28] - w1v[5] <= _T_166 @[el2_dec_gpr_ctl.scala 27:16] - node _T_167 = eq(io.waddr2, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_168 = and(io.wen2, _T_167) @[el2_dec_gpr_ctl.scala 28:28] - w2v[5] <= _T_168 @[el2_dec_gpr_ctl.scala 28:16] - node _T_169 = bits(w0v[5], 0, 0) @[Bitwise.scala 72:15] - node _T_170 = mux(_T_169, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_171 = and(_T_170, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_172 = bits(w1v[5], 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(_T_173, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_175 = or(_T_171, _T_174) @[el2_dec_gpr_ctl.scala 29:47] - node _T_176 = bits(w2v[5], 0, 0) @[Bitwise.scala 72:15] + node _T_161 = and(_T_160, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_162 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_163 = mux(_T_162, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_164 = and(_T_163, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_165 = or(_T_161, _T_164) @[el2_dec_gpr_ctl.scala 38:47] + node _T_166 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_167 = mux(_T_166, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_168 = and(_T_167, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_169 = or(_T_165, _T_168) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[10] <= _T_169 @[el2_dec_gpr_ctl.scala 38:16] + node _T_170 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_171 = and(io.wen0, _T_170) @[el2_dec_gpr_ctl.scala 35:28] + w0v[11] <= _T_171 @[el2_dec_gpr_ctl.scala 35:16] + node _T_172 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_173 = and(io.wen1, _T_172) @[el2_dec_gpr_ctl.scala 36:28] + w1v[11] <= _T_173 @[el2_dec_gpr_ctl.scala 36:16] + node _T_174 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_175 = and(io.wen2, _T_174) @[el2_dec_gpr_ctl.scala 37:28] + w2v[11] <= _T_175 @[el2_dec_gpr_ctl.scala 37:16] + node _T_176 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] node _T_177 = mux(_T_176, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_178 = and(_T_177, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_179 = or(_T_175, _T_178) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[5] <= _T_179 @[el2_dec_gpr_ctl.scala 29:16] - node _T_180 = eq(io.waddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_181 = and(io.wen0, _T_180) @[el2_dec_gpr_ctl.scala 26:28] - w0v[6] <= _T_181 @[el2_dec_gpr_ctl.scala 26:16] - node _T_182 = eq(io.waddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_183 = and(io.wen1, _T_182) @[el2_dec_gpr_ctl.scala 27:28] - w1v[6] <= _T_183 @[el2_dec_gpr_ctl.scala 27:16] - node _T_184 = eq(io.waddr2, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_185 = and(io.wen2, _T_184) @[el2_dec_gpr_ctl.scala 28:28] - w2v[6] <= _T_185 @[el2_dec_gpr_ctl.scala 28:16] - node _T_186 = bits(w0v[6], 0, 0) @[Bitwise.scala 72:15] - node _T_187 = mux(_T_186, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_188 = and(_T_187, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_189 = bits(w1v[6], 0, 0) @[Bitwise.scala 72:15] - node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_191 = and(_T_190, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_192 = or(_T_188, _T_191) @[el2_dec_gpr_ctl.scala 29:47] - node _T_193 = bits(w2v[6], 0, 0) @[Bitwise.scala 72:15] + node _T_178 = and(_T_177, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_179 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_180 = mux(_T_179, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_181 = and(_T_180, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_182 = or(_T_178, _T_181) @[el2_dec_gpr_ctl.scala 38:47] + node _T_183 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(_T_184, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_186 = or(_T_182, _T_185) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[11] <= _T_186 @[el2_dec_gpr_ctl.scala 38:16] + node _T_187 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_188 = and(io.wen0, _T_187) @[el2_dec_gpr_ctl.scala 35:28] + w0v[12] <= _T_188 @[el2_dec_gpr_ctl.scala 35:16] + node _T_189 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_190 = and(io.wen1, _T_189) @[el2_dec_gpr_ctl.scala 36:28] + w1v[12] <= _T_190 @[el2_dec_gpr_ctl.scala 36:16] + node _T_191 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_192 = and(io.wen2, _T_191) @[el2_dec_gpr_ctl.scala 37:28] + w2v[12] <= _T_192 @[el2_dec_gpr_ctl.scala 37:16] + node _T_193 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] node _T_194 = mux(_T_193, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_195 = and(_T_194, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_196 = or(_T_192, _T_195) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[6] <= _T_196 @[el2_dec_gpr_ctl.scala 29:16] - node _T_197 = eq(io.waddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_198 = and(io.wen0, _T_197) @[el2_dec_gpr_ctl.scala 26:28] - w0v[7] <= _T_198 @[el2_dec_gpr_ctl.scala 26:16] - node _T_199 = eq(io.waddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_200 = and(io.wen1, _T_199) @[el2_dec_gpr_ctl.scala 27:28] - w1v[7] <= _T_200 @[el2_dec_gpr_ctl.scala 27:16] - node _T_201 = eq(io.waddr2, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_202 = and(io.wen2, _T_201) @[el2_dec_gpr_ctl.scala 28:28] - w2v[7] <= _T_202 @[el2_dec_gpr_ctl.scala 28:16] - node _T_203 = bits(w0v[7], 0, 0) @[Bitwise.scala 72:15] - node _T_204 = mux(_T_203, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_205 = and(_T_204, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_206 = bits(w1v[7], 0, 0) @[Bitwise.scala 72:15] - node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_208 = and(_T_207, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_209 = or(_T_205, _T_208) @[el2_dec_gpr_ctl.scala 29:47] - node _T_210 = bits(w2v[7], 0, 0) @[Bitwise.scala 72:15] + node _T_195 = and(_T_194, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_196 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_197 = mux(_T_196, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_198 = and(_T_197, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_199 = or(_T_195, _T_198) @[el2_dec_gpr_ctl.scala 38:47] + node _T_200 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_202 = and(_T_201, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_203 = or(_T_199, _T_202) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[12] <= _T_203 @[el2_dec_gpr_ctl.scala 38:16] + node _T_204 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_205 = and(io.wen0, _T_204) @[el2_dec_gpr_ctl.scala 35:28] + w0v[13] <= _T_205 @[el2_dec_gpr_ctl.scala 35:16] + node _T_206 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_207 = and(io.wen1, _T_206) @[el2_dec_gpr_ctl.scala 36:28] + w1v[13] <= _T_207 @[el2_dec_gpr_ctl.scala 36:16] + node _T_208 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_209 = and(io.wen2, _T_208) @[el2_dec_gpr_ctl.scala 37:28] + w2v[13] <= _T_209 @[el2_dec_gpr_ctl.scala 37:16] + node _T_210 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] node _T_211 = mux(_T_210, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_212 = and(_T_211, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_213 = or(_T_209, _T_212) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[7] <= _T_213 @[el2_dec_gpr_ctl.scala 29:16] - node _T_214 = eq(io.waddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_215 = and(io.wen0, _T_214) @[el2_dec_gpr_ctl.scala 26:28] - w0v[8] <= _T_215 @[el2_dec_gpr_ctl.scala 26:16] - node _T_216 = eq(io.waddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_217 = and(io.wen1, _T_216) @[el2_dec_gpr_ctl.scala 27:28] - w1v[8] <= _T_217 @[el2_dec_gpr_ctl.scala 27:16] - node _T_218 = eq(io.waddr2, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_219 = and(io.wen2, _T_218) @[el2_dec_gpr_ctl.scala 28:28] - w2v[8] <= _T_219 @[el2_dec_gpr_ctl.scala 28:16] - node _T_220 = bits(w0v[8], 0, 0) @[Bitwise.scala 72:15] - node _T_221 = mux(_T_220, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_222 = and(_T_221, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_223 = bits(w1v[8], 0, 0) @[Bitwise.scala 72:15] - node _T_224 = mux(_T_223, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_225 = and(_T_224, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_226 = or(_T_222, _T_225) @[el2_dec_gpr_ctl.scala 29:47] - node _T_227 = bits(w2v[8], 0, 0) @[Bitwise.scala 72:15] + node _T_212 = and(_T_211, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_213 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_214 = mux(_T_213, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_215 = and(_T_214, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_216 = or(_T_212, _T_215) @[el2_dec_gpr_ctl.scala 38:47] + node _T_217 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_218 = mux(_T_217, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_219 = and(_T_218, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_220 = or(_T_216, _T_219) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[13] <= _T_220 @[el2_dec_gpr_ctl.scala 38:16] + node _T_221 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_222 = and(io.wen0, _T_221) @[el2_dec_gpr_ctl.scala 35:28] + w0v[14] <= _T_222 @[el2_dec_gpr_ctl.scala 35:16] + node _T_223 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_224 = and(io.wen1, _T_223) @[el2_dec_gpr_ctl.scala 36:28] + w1v[14] <= _T_224 @[el2_dec_gpr_ctl.scala 36:16] + node _T_225 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_226 = and(io.wen2, _T_225) @[el2_dec_gpr_ctl.scala 37:28] + w2v[14] <= _T_226 @[el2_dec_gpr_ctl.scala 37:16] + node _T_227 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] node _T_228 = mux(_T_227, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_229 = and(_T_228, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_230 = or(_T_226, _T_229) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[8] <= _T_230 @[el2_dec_gpr_ctl.scala 29:16] - node _T_231 = eq(io.waddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_232 = and(io.wen0, _T_231) @[el2_dec_gpr_ctl.scala 26:28] - w0v[9] <= _T_232 @[el2_dec_gpr_ctl.scala 26:16] - node _T_233 = eq(io.waddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_234 = and(io.wen1, _T_233) @[el2_dec_gpr_ctl.scala 27:28] - w1v[9] <= _T_234 @[el2_dec_gpr_ctl.scala 27:16] - node _T_235 = eq(io.waddr2, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_236 = and(io.wen2, _T_235) @[el2_dec_gpr_ctl.scala 28:28] - w2v[9] <= _T_236 @[el2_dec_gpr_ctl.scala 28:16] - node _T_237 = bits(w0v[9], 0, 0) @[Bitwise.scala 72:15] - node _T_238 = mux(_T_237, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_239 = and(_T_238, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_240 = bits(w1v[9], 0, 0) @[Bitwise.scala 72:15] - node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_242 = and(_T_241, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_243 = or(_T_239, _T_242) @[el2_dec_gpr_ctl.scala 29:47] - node _T_244 = bits(w2v[9], 0, 0) @[Bitwise.scala 72:15] + node _T_229 = and(_T_228, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_230 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_232 = and(_T_231, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_233 = or(_T_229, _T_232) @[el2_dec_gpr_ctl.scala 38:47] + node _T_234 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_236 = and(_T_235, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_237 = or(_T_233, _T_236) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[14] <= _T_237 @[el2_dec_gpr_ctl.scala 38:16] + node _T_238 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_239 = and(io.wen0, _T_238) @[el2_dec_gpr_ctl.scala 35:28] + w0v[15] <= _T_239 @[el2_dec_gpr_ctl.scala 35:16] + node _T_240 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_241 = and(io.wen1, _T_240) @[el2_dec_gpr_ctl.scala 36:28] + w1v[15] <= _T_241 @[el2_dec_gpr_ctl.scala 36:16] + node _T_242 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_243 = and(io.wen2, _T_242) @[el2_dec_gpr_ctl.scala 37:28] + w2v[15] <= _T_243 @[el2_dec_gpr_ctl.scala 37:16] + node _T_244 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] node _T_245 = mux(_T_244, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_246 = and(_T_245, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_247 = or(_T_243, _T_246) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[9] <= _T_247 @[el2_dec_gpr_ctl.scala 29:16] - node _T_248 = eq(io.waddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_249 = and(io.wen0, _T_248) @[el2_dec_gpr_ctl.scala 26:28] - w0v[10] <= _T_249 @[el2_dec_gpr_ctl.scala 26:16] - node _T_250 = eq(io.waddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_251 = and(io.wen1, _T_250) @[el2_dec_gpr_ctl.scala 27:28] - w1v[10] <= _T_251 @[el2_dec_gpr_ctl.scala 27:16] - node _T_252 = eq(io.waddr2, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_253 = and(io.wen2, _T_252) @[el2_dec_gpr_ctl.scala 28:28] - w2v[10] <= _T_253 @[el2_dec_gpr_ctl.scala 28:16] - node _T_254 = bits(w0v[10], 0, 0) @[Bitwise.scala 72:15] - node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_256 = and(_T_255, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_257 = bits(w1v[10], 0, 0) @[Bitwise.scala 72:15] - node _T_258 = mux(_T_257, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_259 = and(_T_258, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_260 = or(_T_256, _T_259) @[el2_dec_gpr_ctl.scala 29:47] - node _T_261 = bits(w2v[10], 0, 0) @[Bitwise.scala 72:15] + node _T_246 = and(_T_245, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_247 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_249 = and(_T_248, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_250 = or(_T_246, _T_249) @[el2_dec_gpr_ctl.scala 38:47] + node _T_251 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_253 = and(_T_252, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_254 = or(_T_250, _T_253) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[15] <= _T_254 @[el2_dec_gpr_ctl.scala 38:16] + node _T_255 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_256 = and(io.wen0, _T_255) @[el2_dec_gpr_ctl.scala 35:28] + w0v[16] <= _T_256 @[el2_dec_gpr_ctl.scala 35:16] + node _T_257 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_258 = and(io.wen1, _T_257) @[el2_dec_gpr_ctl.scala 36:28] + w1v[16] <= _T_258 @[el2_dec_gpr_ctl.scala 36:16] + node _T_259 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_260 = and(io.wen2, _T_259) @[el2_dec_gpr_ctl.scala 37:28] + w2v[16] <= _T_260 @[el2_dec_gpr_ctl.scala 37:16] + node _T_261 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] node _T_262 = mux(_T_261, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_263 = and(_T_262, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_264 = or(_T_260, _T_263) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[10] <= _T_264 @[el2_dec_gpr_ctl.scala 29:16] - node _T_265 = eq(io.waddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_266 = and(io.wen0, _T_265) @[el2_dec_gpr_ctl.scala 26:28] - w0v[11] <= _T_266 @[el2_dec_gpr_ctl.scala 26:16] - node _T_267 = eq(io.waddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_268 = and(io.wen1, _T_267) @[el2_dec_gpr_ctl.scala 27:28] - w1v[11] <= _T_268 @[el2_dec_gpr_ctl.scala 27:16] - node _T_269 = eq(io.waddr2, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_270 = and(io.wen2, _T_269) @[el2_dec_gpr_ctl.scala 28:28] - w2v[11] <= _T_270 @[el2_dec_gpr_ctl.scala 28:16] - node _T_271 = bits(w0v[11], 0, 0) @[Bitwise.scala 72:15] - node _T_272 = mux(_T_271, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_273 = and(_T_272, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_274 = bits(w1v[11], 0, 0) @[Bitwise.scala 72:15] - node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_276 = and(_T_275, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_277 = or(_T_273, _T_276) @[el2_dec_gpr_ctl.scala 29:47] - node _T_278 = bits(w2v[11], 0, 0) @[Bitwise.scala 72:15] + node _T_263 = and(_T_262, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_264 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_265 = mux(_T_264, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_266 = and(_T_265, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_267 = or(_T_263, _T_266) @[el2_dec_gpr_ctl.scala 38:47] + node _T_268 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_269 = mux(_T_268, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_270 = and(_T_269, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_271 = or(_T_267, _T_270) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[16] <= _T_271 @[el2_dec_gpr_ctl.scala 38:16] + node _T_272 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_273 = and(io.wen0, _T_272) @[el2_dec_gpr_ctl.scala 35:28] + w0v[17] <= _T_273 @[el2_dec_gpr_ctl.scala 35:16] + node _T_274 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_275 = and(io.wen1, _T_274) @[el2_dec_gpr_ctl.scala 36:28] + w1v[17] <= _T_275 @[el2_dec_gpr_ctl.scala 36:16] + node _T_276 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_277 = and(io.wen2, _T_276) @[el2_dec_gpr_ctl.scala 37:28] + w2v[17] <= _T_277 @[el2_dec_gpr_ctl.scala 37:16] + node _T_278 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] node _T_279 = mux(_T_278, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_281 = or(_T_277, _T_280) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[11] <= _T_281 @[el2_dec_gpr_ctl.scala 29:16] - node _T_282 = eq(io.waddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_283 = and(io.wen0, _T_282) @[el2_dec_gpr_ctl.scala 26:28] - w0v[12] <= _T_283 @[el2_dec_gpr_ctl.scala 26:16] - node _T_284 = eq(io.waddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_285 = and(io.wen1, _T_284) @[el2_dec_gpr_ctl.scala 27:28] - w1v[12] <= _T_285 @[el2_dec_gpr_ctl.scala 27:16] - node _T_286 = eq(io.waddr2, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_287 = and(io.wen2, _T_286) @[el2_dec_gpr_ctl.scala 28:28] - w2v[12] <= _T_287 @[el2_dec_gpr_ctl.scala 28:16] - node _T_288 = bits(w0v[12], 0, 0) @[Bitwise.scala 72:15] - node _T_289 = mux(_T_288, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_290 = and(_T_289, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_291 = bits(w1v[12], 0, 0) @[Bitwise.scala 72:15] - node _T_292 = mux(_T_291, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_293 = and(_T_292, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_294 = or(_T_290, _T_293) @[el2_dec_gpr_ctl.scala 29:47] - node _T_295 = bits(w2v[12], 0, 0) @[Bitwise.scala 72:15] + node _T_280 = and(_T_279, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_281 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_282 = mux(_T_281, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_283 = and(_T_282, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_284 = or(_T_280, _T_283) @[el2_dec_gpr_ctl.scala 38:47] + node _T_285 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_286 = mux(_T_285, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_287 = and(_T_286, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_288 = or(_T_284, _T_287) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[17] <= _T_288 @[el2_dec_gpr_ctl.scala 38:16] + node _T_289 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_290 = and(io.wen0, _T_289) @[el2_dec_gpr_ctl.scala 35:28] + w0v[18] <= _T_290 @[el2_dec_gpr_ctl.scala 35:16] + node _T_291 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_292 = and(io.wen1, _T_291) @[el2_dec_gpr_ctl.scala 36:28] + w1v[18] <= _T_292 @[el2_dec_gpr_ctl.scala 36:16] + node _T_293 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_294 = and(io.wen2, _T_293) @[el2_dec_gpr_ctl.scala 37:28] + w2v[18] <= _T_294 @[el2_dec_gpr_ctl.scala 37:16] + node _T_295 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_297 = and(_T_296, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_298 = or(_T_294, _T_297) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[12] <= _T_298 @[el2_dec_gpr_ctl.scala 29:16] - node _T_299 = eq(io.waddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_300 = and(io.wen0, _T_299) @[el2_dec_gpr_ctl.scala 26:28] - w0v[13] <= _T_300 @[el2_dec_gpr_ctl.scala 26:16] - node _T_301 = eq(io.waddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_302 = and(io.wen1, _T_301) @[el2_dec_gpr_ctl.scala 27:28] - w1v[13] <= _T_302 @[el2_dec_gpr_ctl.scala 27:16] - node _T_303 = eq(io.waddr2, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_304 = and(io.wen2, _T_303) @[el2_dec_gpr_ctl.scala 28:28] - w2v[13] <= _T_304 @[el2_dec_gpr_ctl.scala 28:16] - node _T_305 = bits(w0v[13], 0, 0) @[Bitwise.scala 72:15] - node _T_306 = mux(_T_305, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_307 = and(_T_306, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_308 = bits(w1v[13], 0, 0) @[Bitwise.scala 72:15] - node _T_309 = mux(_T_308, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_310 = and(_T_309, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_311 = or(_T_307, _T_310) @[el2_dec_gpr_ctl.scala 29:47] - node _T_312 = bits(w2v[13], 0, 0) @[Bitwise.scala 72:15] + node _T_297 = and(_T_296, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_298 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_300 = and(_T_299, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_301 = or(_T_297, _T_300) @[el2_dec_gpr_ctl.scala 38:47] + node _T_302 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_303 = mux(_T_302, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_304 = and(_T_303, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_305 = or(_T_301, _T_304) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[18] <= _T_305 @[el2_dec_gpr_ctl.scala 38:16] + node _T_306 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_307 = and(io.wen0, _T_306) @[el2_dec_gpr_ctl.scala 35:28] + w0v[19] <= _T_307 @[el2_dec_gpr_ctl.scala 35:16] + node _T_308 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_309 = and(io.wen1, _T_308) @[el2_dec_gpr_ctl.scala 36:28] + w1v[19] <= _T_309 @[el2_dec_gpr_ctl.scala 36:16] + node _T_310 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_311 = and(io.wen2, _T_310) @[el2_dec_gpr_ctl.scala 37:28] + w2v[19] <= _T_311 @[el2_dec_gpr_ctl.scala 37:16] + node _T_312 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] node _T_313 = mux(_T_312, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_314 = and(_T_313, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_315 = or(_T_311, _T_314) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[13] <= _T_315 @[el2_dec_gpr_ctl.scala 29:16] - node _T_316 = eq(io.waddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_317 = and(io.wen0, _T_316) @[el2_dec_gpr_ctl.scala 26:28] - w0v[14] <= _T_317 @[el2_dec_gpr_ctl.scala 26:16] - node _T_318 = eq(io.waddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_319 = and(io.wen1, _T_318) @[el2_dec_gpr_ctl.scala 27:28] - w1v[14] <= _T_319 @[el2_dec_gpr_ctl.scala 27:16] - node _T_320 = eq(io.waddr2, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_321 = and(io.wen2, _T_320) @[el2_dec_gpr_ctl.scala 28:28] - w2v[14] <= _T_321 @[el2_dec_gpr_ctl.scala 28:16] - node _T_322 = bits(w0v[14], 0, 0) @[Bitwise.scala 72:15] - node _T_323 = mux(_T_322, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_324 = and(_T_323, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_325 = bits(w1v[14], 0, 0) @[Bitwise.scala 72:15] - node _T_326 = mux(_T_325, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_327 = and(_T_326, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_328 = or(_T_324, _T_327) @[el2_dec_gpr_ctl.scala 29:47] - node _T_329 = bits(w2v[14], 0, 0) @[Bitwise.scala 72:15] + node _T_314 = and(_T_313, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_315 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_316 = mux(_T_315, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_317 = and(_T_316, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_318 = or(_T_314, _T_317) @[el2_dec_gpr_ctl.scala 38:47] + node _T_319 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_320 = mux(_T_319, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_321 = and(_T_320, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_322 = or(_T_318, _T_321) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[19] <= _T_322 @[el2_dec_gpr_ctl.scala 38:16] + node _T_323 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_324 = and(io.wen0, _T_323) @[el2_dec_gpr_ctl.scala 35:28] + w0v[20] <= _T_324 @[el2_dec_gpr_ctl.scala 35:16] + node _T_325 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_326 = and(io.wen1, _T_325) @[el2_dec_gpr_ctl.scala 36:28] + w1v[20] <= _T_326 @[el2_dec_gpr_ctl.scala 36:16] + node _T_327 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_328 = and(io.wen2, _T_327) @[el2_dec_gpr_ctl.scala 37:28] + w2v[20] <= _T_328 @[el2_dec_gpr_ctl.scala 37:16] + node _T_329 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] node _T_330 = mux(_T_329, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_331 = and(_T_330, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_332 = or(_T_328, _T_331) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[14] <= _T_332 @[el2_dec_gpr_ctl.scala 29:16] - node _T_333 = eq(io.waddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_334 = and(io.wen0, _T_333) @[el2_dec_gpr_ctl.scala 26:28] - w0v[15] <= _T_334 @[el2_dec_gpr_ctl.scala 26:16] - node _T_335 = eq(io.waddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_336 = and(io.wen1, _T_335) @[el2_dec_gpr_ctl.scala 27:28] - w1v[15] <= _T_336 @[el2_dec_gpr_ctl.scala 27:16] - node _T_337 = eq(io.waddr2, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_338 = and(io.wen2, _T_337) @[el2_dec_gpr_ctl.scala 28:28] - w2v[15] <= _T_338 @[el2_dec_gpr_ctl.scala 28:16] - node _T_339 = bits(w0v[15], 0, 0) @[Bitwise.scala 72:15] - node _T_340 = mux(_T_339, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_341 = and(_T_340, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_342 = bits(w1v[15], 0, 0) @[Bitwise.scala 72:15] - node _T_343 = mux(_T_342, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_344 = and(_T_343, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_345 = or(_T_341, _T_344) @[el2_dec_gpr_ctl.scala 29:47] - node _T_346 = bits(w2v[15], 0, 0) @[Bitwise.scala 72:15] + node _T_331 = and(_T_330, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_332 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_333 = mux(_T_332, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_334 = and(_T_333, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_335 = or(_T_331, _T_334) @[el2_dec_gpr_ctl.scala 38:47] + node _T_336 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_337 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_338 = and(_T_337, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_339 = or(_T_335, _T_338) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[20] <= _T_339 @[el2_dec_gpr_ctl.scala 38:16] + node _T_340 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_341 = and(io.wen0, _T_340) @[el2_dec_gpr_ctl.scala 35:28] + w0v[21] <= _T_341 @[el2_dec_gpr_ctl.scala 35:16] + node _T_342 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_343 = and(io.wen1, _T_342) @[el2_dec_gpr_ctl.scala 36:28] + w1v[21] <= _T_343 @[el2_dec_gpr_ctl.scala 36:16] + node _T_344 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_345 = and(io.wen2, _T_344) @[el2_dec_gpr_ctl.scala 37:28] + w2v[21] <= _T_345 @[el2_dec_gpr_ctl.scala 37:16] + node _T_346 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] node _T_347 = mux(_T_346, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_348 = and(_T_347, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_349 = or(_T_345, _T_348) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[15] <= _T_349 @[el2_dec_gpr_ctl.scala 29:16] - node _T_350 = eq(io.waddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_351 = and(io.wen0, _T_350) @[el2_dec_gpr_ctl.scala 26:28] - w0v[16] <= _T_351 @[el2_dec_gpr_ctl.scala 26:16] - node _T_352 = eq(io.waddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_353 = and(io.wen1, _T_352) @[el2_dec_gpr_ctl.scala 27:28] - w1v[16] <= _T_353 @[el2_dec_gpr_ctl.scala 27:16] - node _T_354 = eq(io.waddr2, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_355 = and(io.wen2, _T_354) @[el2_dec_gpr_ctl.scala 28:28] - w2v[16] <= _T_355 @[el2_dec_gpr_ctl.scala 28:16] - node _T_356 = bits(w0v[16], 0, 0) @[Bitwise.scala 72:15] - node _T_357 = mux(_T_356, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_358 = and(_T_357, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_359 = bits(w1v[16], 0, 0) @[Bitwise.scala 72:15] - node _T_360 = mux(_T_359, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_361 = and(_T_360, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_362 = or(_T_358, _T_361) @[el2_dec_gpr_ctl.scala 29:47] - node _T_363 = bits(w2v[16], 0, 0) @[Bitwise.scala 72:15] + node _T_348 = and(_T_347, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_349 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_350 = mux(_T_349, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_351 = and(_T_350, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_352 = or(_T_348, _T_351) @[el2_dec_gpr_ctl.scala 38:47] + node _T_353 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_354 = mux(_T_353, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_355 = and(_T_354, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_356 = or(_T_352, _T_355) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[21] <= _T_356 @[el2_dec_gpr_ctl.scala 38:16] + node _T_357 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_358 = and(io.wen0, _T_357) @[el2_dec_gpr_ctl.scala 35:28] + w0v[22] <= _T_358 @[el2_dec_gpr_ctl.scala 35:16] + node _T_359 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_360 = and(io.wen1, _T_359) @[el2_dec_gpr_ctl.scala 36:28] + w1v[22] <= _T_360 @[el2_dec_gpr_ctl.scala 36:16] + node _T_361 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_362 = and(io.wen2, _T_361) @[el2_dec_gpr_ctl.scala 37:28] + w2v[22] <= _T_362 @[el2_dec_gpr_ctl.scala 37:16] + node _T_363 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] node _T_364 = mux(_T_363, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_365 = and(_T_364, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_366 = or(_T_362, _T_365) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[16] <= _T_366 @[el2_dec_gpr_ctl.scala 29:16] - node _T_367 = eq(io.waddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_368 = and(io.wen0, _T_367) @[el2_dec_gpr_ctl.scala 26:28] - w0v[17] <= _T_368 @[el2_dec_gpr_ctl.scala 26:16] - node _T_369 = eq(io.waddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_370 = and(io.wen1, _T_369) @[el2_dec_gpr_ctl.scala 27:28] - w1v[17] <= _T_370 @[el2_dec_gpr_ctl.scala 27:16] - node _T_371 = eq(io.waddr2, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_372 = and(io.wen2, _T_371) @[el2_dec_gpr_ctl.scala 28:28] - w2v[17] <= _T_372 @[el2_dec_gpr_ctl.scala 28:16] - node _T_373 = bits(w0v[17], 0, 0) @[Bitwise.scala 72:15] - node _T_374 = mux(_T_373, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_375 = and(_T_374, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_376 = bits(w1v[17], 0, 0) @[Bitwise.scala 72:15] - node _T_377 = mux(_T_376, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_378 = and(_T_377, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_379 = or(_T_375, _T_378) @[el2_dec_gpr_ctl.scala 29:47] - node _T_380 = bits(w2v[17], 0, 0) @[Bitwise.scala 72:15] + node _T_365 = and(_T_364, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_366 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_367 = mux(_T_366, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_368 = and(_T_367, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_369 = or(_T_365, _T_368) @[el2_dec_gpr_ctl.scala 38:47] + node _T_370 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_371 = mux(_T_370, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_372 = and(_T_371, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_373 = or(_T_369, _T_372) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[22] <= _T_373 @[el2_dec_gpr_ctl.scala 38:16] + node _T_374 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_375 = and(io.wen0, _T_374) @[el2_dec_gpr_ctl.scala 35:28] + w0v[23] <= _T_375 @[el2_dec_gpr_ctl.scala 35:16] + node _T_376 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_377 = and(io.wen1, _T_376) @[el2_dec_gpr_ctl.scala 36:28] + w1v[23] <= _T_377 @[el2_dec_gpr_ctl.scala 36:16] + node _T_378 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_379 = and(io.wen2, _T_378) @[el2_dec_gpr_ctl.scala 37:28] + w2v[23] <= _T_379 @[el2_dec_gpr_ctl.scala 37:16] + node _T_380 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] node _T_381 = mux(_T_380, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_382 = and(_T_381, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_383 = or(_T_379, _T_382) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[17] <= _T_383 @[el2_dec_gpr_ctl.scala 29:16] - node _T_384 = eq(io.waddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_385 = and(io.wen0, _T_384) @[el2_dec_gpr_ctl.scala 26:28] - w0v[18] <= _T_385 @[el2_dec_gpr_ctl.scala 26:16] - node _T_386 = eq(io.waddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_387 = and(io.wen1, _T_386) @[el2_dec_gpr_ctl.scala 27:28] - w1v[18] <= _T_387 @[el2_dec_gpr_ctl.scala 27:16] - node _T_388 = eq(io.waddr2, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_389 = and(io.wen2, _T_388) @[el2_dec_gpr_ctl.scala 28:28] - w2v[18] <= _T_389 @[el2_dec_gpr_ctl.scala 28:16] - node _T_390 = bits(w0v[18], 0, 0) @[Bitwise.scala 72:15] - node _T_391 = mux(_T_390, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_392 = and(_T_391, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_393 = bits(w1v[18], 0, 0) @[Bitwise.scala 72:15] - node _T_394 = mux(_T_393, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_395 = and(_T_394, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_396 = or(_T_392, _T_395) @[el2_dec_gpr_ctl.scala 29:47] - node _T_397 = bits(w2v[18], 0, 0) @[Bitwise.scala 72:15] + node _T_382 = and(_T_381, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_383 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_384 = mux(_T_383, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_385 = and(_T_384, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_386 = or(_T_382, _T_385) @[el2_dec_gpr_ctl.scala 38:47] + node _T_387 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_388 = mux(_T_387, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_389 = and(_T_388, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_390 = or(_T_386, _T_389) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[23] <= _T_390 @[el2_dec_gpr_ctl.scala 38:16] + node _T_391 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_392 = and(io.wen0, _T_391) @[el2_dec_gpr_ctl.scala 35:28] + w0v[24] <= _T_392 @[el2_dec_gpr_ctl.scala 35:16] + node _T_393 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_394 = and(io.wen1, _T_393) @[el2_dec_gpr_ctl.scala 36:28] + w1v[24] <= _T_394 @[el2_dec_gpr_ctl.scala 36:16] + node _T_395 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_396 = and(io.wen2, _T_395) @[el2_dec_gpr_ctl.scala 37:28] + w2v[24] <= _T_396 @[el2_dec_gpr_ctl.scala 37:16] + node _T_397 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] node _T_398 = mux(_T_397, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_399 = and(_T_398, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_400 = or(_T_396, _T_399) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[18] <= _T_400 @[el2_dec_gpr_ctl.scala 29:16] - node _T_401 = eq(io.waddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_402 = and(io.wen0, _T_401) @[el2_dec_gpr_ctl.scala 26:28] - w0v[19] <= _T_402 @[el2_dec_gpr_ctl.scala 26:16] - node _T_403 = eq(io.waddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_404 = and(io.wen1, _T_403) @[el2_dec_gpr_ctl.scala 27:28] - w1v[19] <= _T_404 @[el2_dec_gpr_ctl.scala 27:16] - node _T_405 = eq(io.waddr2, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_406 = and(io.wen2, _T_405) @[el2_dec_gpr_ctl.scala 28:28] - w2v[19] <= _T_406 @[el2_dec_gpr_ctl.scala 28:16] - node _T_407 = bits(w0v[19], 0, 0) @[Bitwise.scala 72:15] - node _T_408 = mux(_T_407, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_409 = and(_T_408, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_410 = bits(w1v[19], 0, 0) @[Bitwise.scala 72:15] - node _T_411 = mux(_T_410, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_412 = and(_T_411, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_413 = or(_T_409, _T_412) @[el2_dec_gpr_ctl.scala 29:47] - node _T_414 = bits(w2v[19], 0, 0) @[Bitwise.scala 72:15] + node _T_399 = and(_T_398, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_400 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_401 = mux(_T_400, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_402 = and(_T_401, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_403 = or(_T_399, _T_402) @[el2_dec_gpr_ctl.scala 38:47] + node _T_404 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_405 = mux(_T_404, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_406 = and(_T_405, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_407 = or(_T_403, _T_406) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[24] <= _T_407 @[el2_dec_gpr_ctl.scala 38:16] + node _T_408 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_409 = and(io.wen0, _T_408) @[el2_dec_gpr_ctl.scala 35:28] + w0v[25] <= _T_409 @[el2_dec_gpr_ctl.scala 35:16] + node _T_410 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_411 = and(io.wen1, _T_410) @[el2_dec_gpr_ctl.scala 36:28] + w1v[25] <= _T_411 @[el2_dec_gpr_ctl.scala 36:16] + node _T_412 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_413 = and(io.wen2, _T_412) @[el2_dec_gpr_ctl.scala 37:28] + w2v[25] <= _T_413 @[el2_dec_gpr_ctl.scala 37:16] + node _T_414 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] node _T_415 = mux(_T_414, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_416 = and(_T_415, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_417 = or(_T_413, _T_416) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[19] <= _T_417 @[el2_dec_gpr_ctl.scala 29:16] - node _T_418 = eq(io.waddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_419 = and(io.wen0, _T_418) @[el2_dec_gpr_ctl.scala 26:28] - w0v[20] <= _T_419 @[el2_dec_gpr_ctl.scala 26:16] - node _T_420 = eq(io.waddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_421 = and(io.wen1, _T_420) @[el2_dec_gpr_ctl.scala 27:28] - w1v[20] <= _T_421 @[el2_dec_gpr_ctl.scala 27:16] - node _T_422 = eq(io.waddr2, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_423 = and(io.wen2, _T_422) @[el2_dec_gpr_ctl.scala 28:28] - w2v[20] <= _T_423 @[el2_dec_gpr_ctl.scala 28:16] - node _T_424 = bits(w0v[20], 0, 0) @[Bitwise.scala 72:15] - node _T_425 = mux(_T_424, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_426 = and(_T_425, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_427 = bits(w1v[20], 0, 0) @[Bitwise.scala 72:15] - node _T_428 = mux(_T_427, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_429 = and(_T_428, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_430 = or(_T_426, _T_429) @[el2_dec_gpr_ctl.scala 29:47] - node _T_431 = bits(w2v[20], 0, 0) @[Bitwise.scala 72:15] + node _T_416 = and(_T_415, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_417 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_418 = mux(_T_417, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_419 = and(_T_418, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_420 = or(_T_416, _T_419) @[el2_dec_gpr_ctl.scala 38:47] + node _T_421 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_422 = mux(_T_421, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_423 = and(_T_422, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_424 = or(_T_420, _T_423) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[25] <= _T_424 @[el2_dec_gpr_ctl.scala 38:16] + node _T_425 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_426 = and(io.wen0, _T_425) @[el2_dec_gpr_ctl.scala 35:28] + w0v[26] <= _T_426 @[el2_dec_gpr_ctl.scala 35:16] + node _T_427 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_428 = and(io.wen1, _T_427) @[el2_dec_gpr_ctl.scala 36:28] + w1v[26] <= _T_428 @[el2_dec_gpr_ctl.scala 36:16] + node _T_429 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_430 = and(io.wen2, _T_429) @[el2_dec_gpr_ctl.scala 37:28] + w2v[26] <= _T_430 @[el2_dec_gpr_ctl.scala 37:16] + node _T_431 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] node _T_432 = mux(_T_431, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_433 = and(_T_432, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_434 = or(_T_430, _T_433) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[20] <= _T_434 @[el2_dec_gpr_ctl.scala 29:16] - node _T_435 = eq(io.waddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_436 = and(io.wen0, _T_435) @[el2_dec_gpr_ctl.scala 26:28] - w0v[21] <= _T_436 @[el2_dec_gpr_ctl.scala 26:16] - node _T_437 = eq(io.waddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_438 = and(io.wen1, _T_437) @[el2_dec_gpr_ctl.scala 27:28] - w1v[21] <= _T_438 @[el2_dec_gpr_ctl.scala 27:16] - node _T_439 = eq(io.waddr2, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_440 = and(io.wen2, _T_439) @[el2_dec_gpr_ctl.scala 28:28] - w2v[21] <= _T_440 @[el2_dec_gpr_ctl.scala 28:16] - node _T_441 = bits(w0v[21], 0, 0) @[Bitwise.scala 72:15] - node _T_442 = mux(_T_441, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_443 = and(_T_442, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_444 = bits(w1v[21], 0, 0) @[Bitwise.scala 72:15] - node _T_445 = mux(_T_444, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_446 = and(_T_445, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_447 = or(_T_443, _T_446) @[el2_dec_gpr_ctl.scala 29:47] - node _T_448 = bits(w2v[21], 0, 0) @[Bitwise.scala 72:15] + node _T_433 = and(_T_432, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_434 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_436 = and(_T_435, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_437 = or(_T_433, _T_436) @[el2_dec_gpr_ctl.scala 38:47] + node _T_438 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] + node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_440 = and(_T_439, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_441 = or(_T_437, _T_440) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[26] <= _T_441 @[el2_dec_gpr_ctl.scala 38:16] + node _T_442 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_443 = and(io.wen0, _T_442) @[el2_dec_gpr_ctl.scala 35:28] + w0v[27] <= _T_443 @[el2_dec_gpr_ctl.scala 35:16] + node _T_444 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_445 = and(io.wen1, _T_444) @[el2_dec_gpr_ctl.scala 36:28] + w1v[27] <= _T_445 @[el2_dec_gpr_ctl.scala 36:16] + node _T_446 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_447 = and(io.wen2, _T_446) @[el2_dec_gpr_ctl.scala 37:28] + w2v[27] <= _T_447 @[el2_dec_gpr_ctl.scala 37:16] + node _T_448 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_450 = and(_T_449, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_451 = or(_T_447, _T_450) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[21] <= _T_451 @[el2_dec_gpr_ctl.scala 29:16] - node _T_452 = eq(io.waddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_453 = and(io.wen0, _T_452) @[el2_dec_gpr_ctl.scala 26:28] - w0v[22] <= _T_453 @[el2_dec_gpr_ctl.scala 26:16] - node _T_454 = eq(io.waddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_455 = and(io.wen1, _T_454) @[el2_dec_gpr_ctl.scala 27:28] - w1v[22] <= _T_455 @[el2_dec_gpr_ctl.scala 27:16] - node _T_456 = eq(io.waddr2, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_457 = and(io.wen2, _T_456) @[el2_dec_gpr_ctl.scala 28:28] - w2v[22] <= _T_457 @[el2_dec_gpr_ctl.scala 28:16] - node _T_458 = bits(w0v[22], 0, 0) @[Bitwise.scala 72:15] - node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_460 = and(_T_459, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_461 = bits(w1v[22], 0, 0) @[Bitwise.scala 72:15] - node _T_462 = mux(_T_461, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_463 = and(_T_462, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_464 = or(_T_460, _T_463) @[el2_dec_gpr_ctl.scala 29:47] - node _T_465 = bits(w2v[22], 0, 0) @[Bitwise.scala 72:15] + node _T_450 = and(_T_449, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_451 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_452 = mux(_T_451, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_453 = and(_T_452, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_454 = or(_T_450, _T_453) @[el2_dec_gpr_ctl.scala 38:47] + node _T_455 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(_T_456, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_458 = or(_T_454, _T_457) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[27] <= _T_458 @[el2_dec_gpr_ctl.scala 38:16] + node _T_459 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_460 = and(io.wen0, _T_459) @[el2_dec_gpr_ctl.scala 35:28] + w0v[28] <= _T_460 @[el2_dec_gpr_ctl.scala 35:16] + node _T_461 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_462 = and(io.wen1, _T_461) @[el2_dec_gpr_ctl.scala 36:28] + w1v[28] <= _T_462 @[el2_dec_gpr_ctl.scala 36:16] + node _T_463 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_464 = and(io.wen2, _T_463) @[el2_dec_gpr_ctl.scala 37:28] + w2v[28] <= _T_464 @[el2_dec_gpr_ctl.scala 37:16] + node _T_465 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_467 = and(_T_466, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_468 = or(_T_464, _T_467) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[22] <= _T_468 @[el2_dec_gpr_ctl.scala 29:16] - node _T_469 = eq(io.waddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_470 = and(io.wen0, _T_469) @[el2_dec_gpr_ctl.scala 26:28] - w0v[23] <= _T_470 @[el2_dec_gpr_ctl.scala 26:16] - node _T_471 = eq(io.waddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_472 = and(io.wen1, _T_471) @[el2_dec_gpr_ctl.scala 27:28] - w1v[23] <= _T_472 @[el2_dec_gpr_ctl.scala 27:16] - node _T_473 = eq(io.waddr2, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_474 = and(io.wen2, _T_473) @[el2_dec_gpr_ctl.scala 28:28] - w2v[23] <= _T_474 @[el2_dec_gpr_ctl.scala 28:16] - node _T_475 = bits(w0v[23], 0, 0) @[Bitwise.scala 72:15] - node _T_476 = mux(_T_475, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_477 = and(_T_476, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_478 = bits(w1v[23], 0, 0) @[Bitwise.scala 72:15] - node _T_479 = mux(_T_478, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_480 = and(_T_479, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_481 = or(_T_477, _T_480) @[el2_dec_gpr_ctl.scala 29:47] - node _T_482 = bits(w2v[23], 0, 0) @[Bitwise.scala 72:15] + node _T_467 = and(_T_466, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_468 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_470 = and(_T_469, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_471 = or(_T_467, _T_470) @[el2_dec_gpr_ctl.scala 38:47] + node _T_472 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] + node _T_473 = mux(_T_472, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_474 = and(_T_473, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_475 = or(_T_471, _T_474) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[28] <= _T_475 @[el2_dec_gpr_ctl.scala 38:16] + node _T_476 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_477 = and(io.wen0, _T_476) @[el2_dec_gpr_ctl.scala 35:28] + w0v[29] <= _T_477 @[el2_dec_gpr_ctl.scala 35:16] + node _T_478 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_479 = and(io.wen1, _T_478) @[el2_dec_gpr_ctl.scala 36:28] + w1v[29] <= _T_479 @[el2_dec_gpr_ctl.scala 36:16] + node _T_480 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_481 = and(io.wen2, _T_480) @[el2_dec_gpr_ctl.scala 37:28] + w2v[29] <= _T_481 @[el2_dec_gpr_ctl.scala 37:16] + node _T_482 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] node _T_483 = mux(_T_482, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_484 = and(_T_483, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_485 = or(_T_481, _T_484) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[23] <= _T_485 @[el2_dec_gpr_ctl.scala 29:16] - node _T_486 = eq(io.waddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_487 = and(io.wen0, _T_486) @[el2_dec_gpr_ctl.scala 26:28] - w0v[24] <= _T_487 @[el2_dec_gpr_ctl.scala 26:16] - node _T_488 = eq(io.waddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_489 = and(io.wen1, _T_488) @[el2_dec_gpr_ctl.scala 27:28] - w1v[24] <= _T_489 @[el2_dec_gpr_ctl.scala 27:16] - node _T_490 = eq(io.waddr2, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_491 = and(io.wen2, _T_490) @[el2_dec_gpr_ctl.scala 28:28] - w2v[24] <= _T_491 @[el2_dec_gpr_ctl.scala 28:16] - node _T_492 = bits(w0v[24], 0, 0) @[Bitwise.scala 72:15] - node _T_493 = mux(_T_492, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_494 = and(_T_493, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_495 = bits(w1v[24], 0, 0) @[Bitwise.scala 72:15] - node _T_496 = mux(_T_495, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_497 = and(_T_496, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_498 = or(_T_494, _T_497) @[el2_dec_gpr_ctl.scala 29:47] - node _T_499 = bits(w2v[24], 0, 0) @[Bitwise.scala 72:15] + node _T_484 = and(_T_483, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_485 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_486 = mux(_T_485, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_487 = and(_T_486, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_488 = or(_T_484, _T_487) @[el2_dec_gpr_ctl.scala 38:47] + node _T_489 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] + node _T_490 = mux(_T_489, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_491 = and(_T_490, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_492 = or(_T_488, _T_491) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[29] <= _T_492 @[el2_dec_gpr_ctl.scala 38:16] + node _T_493 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_494 = and(io.wen0, _T_493) @[el2_dec_gpr_ctl.scala 35:28] + w0v[30] <= _T_494 @[el2_dec_gpr_ctl.scala 35:16] + node _T_495 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_496 = and(io.wen1, _T_495) @[el2_dec_gpr_ctl.scala 36:28] + w1v[30] <= _T_496 @[el2_dec_gpr_ctl.scala 36:16] + node _T_497 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_498 = and(io.wen2, _T_497) @[el2_dec_gpr_ctl.scala 37:28] + w2v[30] <= _T_498 @[el2_dec_gpr_ctl.scala 37:16] + node _T_499 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] node _T_500 = mux(_T_499, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_501 = and(_T_500, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_502 = or(_T_498, _T_501) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[24] <= _T_502 @[el2_dec_gpr_ctl.scala 29:16] - node _T_503 = eq(io.waddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_504 = and(io.wen0, _T_503) @[el2_dec_gpr_ctl.scala 26:28] - w0v[25] <= _T_504 @[el2_dec_gpr_ctl.scala 26:16] - node _T_505 = eq(io.waddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_506 = and(io.wen1, _T_505) @[el2_dec_gpr_ctl.scala 27:28] - w1v[25] <= _T_506 @[el2_dec_gpr_ctl.scala 27:16] - node _T_507 = eq(io.waddr2, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_508 = and(io.wen2, _T_507) @[el2_dec_gpr_ctl.scala 28:28] - w2v[25] <= _T_508 @[el2_dec_gpr_ctl.scala 28:16] - node _T_509 = bits(w0v[25], 0, 0) @[Bitwise.scala 72:15] - node _T_510 = mux(_T_509, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_511 = and(_T_510, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_512 = bits(w1v[25], 0, 0) @[Bitwise.scala 72:15] - node _T_513 = mux(_T_512, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_514 = and(_T_513, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_515 = or(_T_511, _T_514) @[el2_dec_gpr_ctl.scala 29:47] - node _T_516 = bits(w2v[25], 0, 0) @[Bitwise.scala 72:15] + node _T_501 = and(_T_500, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_502 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_503 = mux(_T_502, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_504 = and(_T_503, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_505 = or(_T_501, _T_504) @[el2_dec_gpr_ctl.scala 38:47] + node _T_506 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] + node _T_507 = mux(_T_506, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_508 = and(_T_507, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_509 = or(_T_505, _T_508) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[30] <= _T_509 @[el2_dec_gpr_ctl.scala 38:16] + node _T_510 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 35:40] + node _T_511 = and(io.wen0, _T_510) @[el2_dec_gpr_ctl.scala 35:28] + w0v[31] <= _T_511 @[el2_dec_gpr_ctl.scala 35:16] + node _T_512 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:40] + node _T_513 = and(io.wen1, _T_512) @[el2_dec_gpr_ctl.scala 36:28] + w1v[31] <= _T_513 @[el2_dec_gpr_ctl.scala 36:16] + node _T_514 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:40] + node _T_515 = and(io.wen2, _T_514) @[el2_dec_gpr_ctl.scala 37:28] + w2v[31] <= _T_515 @[el2_dec_gpr_ctl.scala 37:16] + node _T_516 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] node _T_517 = mux(_T_516, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_518 = and(_T_517, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_519 = or(_T_515, _T_518) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[25] <= _T_519 @[el2_dec_gpr_ctl.scala 29:16] - node _T_520 = eq(io.waddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_521 = and(io.wen0, _T_520) @[el2_dec_gpr_ctl.scala 26:28] - w0v[26] <= _T_521 @[el2_dec_gpr_ctl.scala 26:16] - node _T_522 = eq(io.waddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_523 = and(io.wen1, _T_522) @[el2_dec_gpr_ctl.scala 27:28] - w1v[26] <= _T_523 @[el2_dec_gpr_ctl.scala 27:16] - node _T_524 = eq(io.waddr2, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_525 = and(io.wen2, _T_524) @[el2_dec_gpr_ctl.scala 28:28] - w2v[26] <= _T_525 @[el2_dec_gpr_ctl.scala 28:16] - node _T_526 = bits(w0v[26], 0, 0) @[Bitwise.scala 72:15] - node _T_527 = mux(_T_526, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_528 = and(_T_527, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_529 = bits(w1v[26], 0, 0) @[Bitwise.scala 72:15] - node _T_530 = mux(_T_529, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_531 = and(_T_530, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_532 = or(_T_528, _T_531) @[el2_dec_gpr_ctl.scala 29:47] - node _T_533 = bits(w2v[26], 0, 0) @[Bitwise.scala 72:15] - node _T_534 = mux(_T_533, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_535 = and(_T_534, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_536 = or(_T_532, _T_535) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[26] <= _T_536 @[el2_dec_gpr_ctl.scala 29:16] - node _T_537 = eq(io.waddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_538 = and(io.wen0, _T_537) @[el2_dec_gpr_ctl.scala 26:28] - w0v[27] <= _T_538 @[el2_dec_gpr_ctl.scala 26:16] - node _T_539 = eq(io.waddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_540 = and(io.wen1, _T_539) @[el2_dec_gpr_ctl.scala 27:28] - w1v[27] <= _T_540 @[el2_dec_gpr_ctl.scala 27:16] - node _T_541 = eq(io.waddr2, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_542 = and(io.wen2, _T_541) @[el2_dec_gpr_ctl.scala 28:28] - w2v[27] <= _T_542 @[el2_dec_gpr_ctl.scala 28:16] - node _T_543 = bits(w0v[27], 0, 0) @[Bitwise.scala 72:15] - node _T_544 = mux(_T_543, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_545 = and(_T_544, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_546 = bits(w1v[27], 0, 0) @[Bitwise.scala 72:15] - node _T_547 = mux(_T_546, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_548 = and(_T_547, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_549 = or(_T_545, _T_548) @[el2_dec_gpr_ctl.scala 29:47] - node _T_550 = bits(w2v[27], 0, 0) @[Bitwise.scala 72:15] - node _T_551 = mux(_T_550, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_552 = and(_T_551, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_553 = or(_T_549, _T_552) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[27] <= _T_553 @[el2_dec_gpr_ctl.scala 29:16] - node _T_554 = eq(io.waddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_555 = and(io.wen0, _T_554) @[el2_dec_gpr_ctl.scala 26:28] - w0v[28] <= _T_555 @[el2_dec_gpr_ctl.scala 26:16] - node _T_556 = eq(io.waddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_557 = and(io.wen1, _T_556) @[el2_dec_gpr_ctl.scala 27:28] - w1v[28] <= _T_557 @[el2_dec_gpr_ctl.scala 27:16] - node _T_558 = eq(io.waddr2, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_559 = and(io.wen2, _T_558) @[el2_dec_gpr_ctl.scala 28:28] - w2v[28] <= _T_559 @[el2_dec_gpr_ctl.scala 28:16] - node _T_560 = bits(w0v[28], 0, 0) @[Bitwise.scala 72:15] - node _T_561 = mux(_T_560, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_562 = and(_T_561, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_563 = bits(w1v[28], 0, 0) @[Bitwise.scala 72:15] - node _T_564 = mux(_T_563, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_565 = and(_T_564, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_566 = or(_T_562, _T_565) @[el2_dec_gpr_ctl.scala 29:47] - node _T_567 = bits(w2v[28], 0, 0) @[Bitwise.scala 72:15] - node _T_568 = mux(_T_567, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_569 = and(_T_568, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_570 = or(_T_566, _T_569) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[28] <= _T_570 @[el2_dec_gpr_ctl.scala 29:16] - node _T_571 = eq(io.waddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_572 = and(io.wen0, _T_571) @[el2_dec_gpr_ctl.scala 26:28] - w0v[29] <= _T_572 @[el2_dec_gpr_ctl.scala 26:16] - node _T_573 = eq(io.waddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_574 = and(io.wen1, _T_573) @[el2_dec_gpr_ctl.scala 27:28] - w1v[29] <= _T_574 @[el2_dec_gpr_ctl.scala 27:16] - node _T_575 = eq(io.waddr2, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_576 = and(io.wen2, _T_575) @[el2_dec_gpr_ctl.scala 28:28] - w2v[29] <= _T_576 @[el2_dec_gpr_ctl.scala 28:16] - node _T_577 = bits(w0v[29], 0, 0) @[Bitwise.scala 72:15] - node _T_578 = mux(_T_577, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_579 = and(_T_578, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_580 = bits(w1v[29], 0, 0) @[Bitwise.scala 72:15] - node _T_581 = mux(_T_580, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_582 = and(_T_581, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_583 = or(_T_579, _T_582) @[el2_dec_gpr_ctl.scala 29:47] - node _T_584 = bits(w2v[29], 0, 0) @[Bitwise.scala 72:15] - node _T_585 = mux(_T_584, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_586 = and(_T_585, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_587 = or(_T_583, _T_586) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[29] <= _T_587 @[el2_dec_gpr_ctl.scala 29:16] - node _T_588 = eq(io.waddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_589 = and(io.wen0, _T_588) @[el2_dec_gpr_ctl.scala 26:28] - w0v[30] <= _T_589 @[el2_dec_gpr_ctl.scala 26:16] - node _T_590 = eq(io.waddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_591 = and(io.wen1, _T_590) @[el2_dec_gpr_ctl.scala 27:28] - w1v[30] <= _T_591 @[el2_dec_gpr_ctl.scala 27:16] - node _T_592 = eq(io.waddr2, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_593 = and(io.wen2, _T_592) @[el2_dec_gpr_ctl.scala 28:28] - w2v[30] <= _T_593 @[el2_dec_gpr_ctl.scala 28:16] - node _T_594 = bits(w0v[30], 0, 0) @[Bitwise.scala 72:15] - node _T_595 = mux(_T_594, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_596 = and(_T_595, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_597 = bits(w1v[30], 0, 0) @[Bitwise.scala 72:15] - node _T_598 = mux(_T_597, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_599 = and(_T_598, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_600 = or(_T_596, _T_599) @[el2_dec_gpr_ctl.scala 29:47] - node _T_601 = bits(w2v[30], 0, 0) @[Bitwise.scala 72:15] - node _T_602 = mux(_T_601, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_603 = and(_T_602, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_604 = or(_T_600, _T_603) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[30] <= _T_604 @[el2_dec_gpr_ctl.scala 29:16] - node _T_605 = eq(io.waddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 26:40] - node _T_606 = and(io.wen0, _T_605) @[el2_dec_gpr_ctl.scala 26:28] - w0v[31] <= _T_606 @[el2_dec_gpr_ctl.scala 26:16] - node _T_607 = eq(io.waddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 27:40] - node _T_608 = and(io.wen1, _T_607) @[el2_dec_gpr_ctl.scala 27:28] - w1v[31] <= _T_608 @[el2_dec_gpr_ctl.scala 27:16] - node _T_609 = eq(io.waddr2, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 28:40] - node _T_610 = and(io.wen2, _T_609) @[el2_dec_gpr_ctl.scala 28:28] - w2v[31] <= _T_610 @[el2_dec_gpr_ctl.scala 28:16] - node _T_611 = bits(w0v[31], 0, 0) @[Bitwise.scala 72:15] - node _T_612 = mux(_T_611, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_613 = and(_T_612, io.wd0) @[el2_dec_gpr_ctl.scala 29:37] - node _T_614 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] - node _T_615 = mux(_T_614, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_616 = and(_T_615, io.wd1) @[el2_dec_gpr_ctl.scala 29:66] - node _T_617 = or(_T_613, _T_616) @[el2_dec_gpr_ctl.scala 29:47] - node _T_618 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] - node _T_619 = mux(_T_618, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_620 = and(_T_619, io.wd2) @[el2_dec_gpr_ctl.scala 29:95] - node _T_621 = or(_T_617, _T_620) @[el2_dec_gpr_ctl.scala 29:76] - gpr_in[31] <= _T_621 @[el2_dec_gpr_ctl.scala 29:16] - node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 33:43] + node _T_518 = and(_T_517, io.wd0) @[el2_dec_gpr_ctl.scala 38:37] + node _T_519 = bits(w1v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_520 = mux(_T_519, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_521 = and(_T_520, io.wd1) @[el2_dec_gpr_ctl.scala 38:66] + node _T_522 = or(_T_518, _T_521) @[el2_dec_gpr_ctl.scala 38:47] + node _T_523 = bits(w2v[31], 0, 0) @[Bitwise.scala 72:15] + node _T_524 = mux(_T_523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_525 = and(_T_524, io.wd2) @[el2_dec_gpr_ctl.scala 38:95] + node _T_526 = or(_T_522, _T_525) @[el2_dec_gpr_ctl.scala 38:76] + gpr_in[31] <= _T_526 @[el2_dec_gpr_ctl.scala 38:16] + node _T_527 = cat(w0v[1], w0v[0]) @[Cat.scala 29:58] + node _T_528 = cat(w0v[2], _T_527) @[Cat.scala 29:58] + node _T_529 = cat(w0v[3], _T_528) @[Cat.scala 29:58] + node _T_530 = cat(w0v[4], _T_529) @[Cat.scala 29:58] + node _T_531 = cat(w0v[5], _T_530) @[Cat.scala 29:58] + node _T_532 = cat(w0v[6], _T_531) @[Cat.scala 29:58] + node _T_533 = cat(w0v[7], _T_532) @[Cat.scala 29:58] + node _T_534 = cat(w0v[8], _T_533) @[Cat.scala 29:58] + node _T_535 = cat(w0v[9], _T_534) @[Cat.scala 29:58] + node _T_536 = cat(w0v[10], _T_535) @[Cat.scala 29:58] + node _T_537 = cat(w0v[11], _T_536) @[Cat.scala 29:58] + node _T_538 = cat(w0v[12], _T_537) @[Cat.scala 29:58] + node _T_539 = cat(w0v[13], _T_538) @[Cat.scala 29:58] + node _T_540 = cat(w0v[14], _T_539) @[Cat.scala 29:58] + node _T_541 = cat(w0v[15], _T_540) @[Cat.scala 29:58] + node _T_542 = cat(w0v[16], _T_541) @[Cat.scala 29:58] + node _T_543 = cat(w0v[17], _T_542) @[Cat.scala 29:58] + node _T_544 = cat(w0v[18], _T_543) @[Cat.scala 29:58] + node _T_545 = cat(w0v[19], _T_544) @[Cat.scala 29:58] + node _T_546 = cat(w0v[20], _T_545) @[Cat.scala 29:58] + node _T_547 = cat(w0v[21], _T_546) @[Cat.scala 29:58] + node _T_548 = cat(w0v[22], _T_547) @[Cat.scala 29:58] + node _T_549 = cat(w0v[23], _T_548) @[Cat.scala 29:58] + node _T_550 = cat(w0v[24], _T_549) @[Cat.scala 29:58] + node _T_551 = cat(w0v[25], _T_550) @[Cat.scala 29:58] + node _T_552 = cat(w0v[26], _T_551) @[Cat.scala 29:58] + node _T_553 = cat(w0v[27], _T_552) @[Cat.scala 29:58] + node _T_554 = cat(w0v[28], _T_553) @[Cat.scala 29:58] + node _T_555 = cat(w0v[29], _T_554) @[Cat.scala 29:58] + node _T_556 = cat(w0v[30], _T_555) @[Cat.scala 29:58] + node _T_557 = cat(w0v[31], _T_556) @[Cat.scala 29:58] + node _T_558 = cat(w1v[1], w1v[0]) @[Cat.scala 29:58] + node _T_559 = cat(w1v[2], _T_558) @[Cat.scala 29:58] + node _T_560 = cat(w1v[3], _T_559) @[Cat.scala 29:58] + node _T_561 = cat(w1v[4], _T_560) @[Cat.scala 29:58] + node _T_562 = cat(w1v[5], _T_561) @[Cat.scala 29:58] + node _T_563 = cat(w1v[6], _T_562) @[Cat.scala 29:58] + node _T_564 = cat(w1v[7], _T_563) @[Cat.scala 29:58] + node _T_565 = cat(w1v[8], _T_564) @[Cat.scala 29:58] + node _T_566 = cat(w1v[9], _T_565) @[Cat.scala 29:58] + node _T_567 = cat(w1v[10], _T_566) @[Cat.scala 29:58] + node _T_568 = cat(w1v[11], _T_567) @[Cat.scala 29:58] + node _T_569 = cat(w1v[12], _T_568) @[Cat.scala 29:58] + node _T_570 = cat(w1v[13], _T_569) @[Cat.scala 29:58] + node _T_571 = cat(w1v[14], _T_570) @[Cat.scala 29:58] + node _T_572 = cat(w1v[15], _T_571) @[Cat.scala 29:58] + node _T_573 = cat(w1v[16], _T_572) @[Cat.scala 29:58] + node _T_574 = cat(w1v[17], _T_573) @[Cat.scala 29:58] + node _T_575 = cat(w1v[18], _T_574) @[Cat.scala 29:58] + node _T_576 = cat(w1v[19], _T_575) @[Cat.scala 29:58] + node _T_577 = cat(w1v[20], _T_576) @[Cat.scala 29:58] + node _T_578 = cat(w1v[21], _T_577) @[Cat.scala 29:58] + node _T_579 = cat(w1v[22], _T_578) @[Cat.scala 29:58] + node _T_580 = cat(w1v[23], _T_579) @[Cat.scala 29:58] + node _T_581 = cat(w1v[24], _T_580) @[Cat.scala 29:58] + node _T_582 = cat(w1v[25], _T_581) @[Cat.scala 29:58] + node _T_583 = cat(w1v[26], _T_582) @[Cat.scala 29:58] + node _T_584 = cat(w1v[27], _T_583) @[Cat.scala 29:58] + node _T_585 = cat(w1v[28], _T_584) @[Cat.scala 29:58] + node _T_586 = cat(w1v[29], _T_585) @[Cat.scala 29:58] + node _T_587 = cat(w1v[30], _T_586) @[Cat.scala 29:58] + node _T_588 = cat(w1v[31], _T_587) @[Cat.scala 29:58] + node _T_589 = or(_T_557, _T_588) @[el2_dec_gpr_ctl.scala 40:51] + node _T_590 = cat(w2v[1], w2v[0]) @[Cat.scala 29:58] + node _T_591 = cat(w2v[2], _T_590) @[Cat.scala 29:58] + node _T_592 = cat(w2v[3], _T_591) @[Cat.scala 29:58] + node _T_593 = cat(w2v[4], _T_592) @[Cat.scala 29:58] + node _T_594 = cat(w2v[5], _T_593) @[Cat.scala 29:58] + node _T_595 = cat(w2v[6], _T_594) @[Cat.scala 29:58] + node _T_596 = cat(w2v[7], _T_595) @[Cat.scala 29:58] + node _T_597 = cat(w2v[8], _T_596) @[Cat.scala 29:58] + node _T_598 = cat(w2v[9], _T_597) @[Cat.scala 29:58] + node _T_599 = cat(w2v[10], _T_598) @[Cat.scala 29:58] + node _T_600 = cat(w2v[11], _T_599) @[Cat.scala 29:58] + node _T_601 = cat(w2v[12], _T_600) @[Cat.scala 29:58] + node _T_602 = cat(w2v[13], _T_601) @[Cat.scala 29:58] + node _T_603 = cat(w2v[14], _T_602) @[Cat.scala 29:58] + node _T_604 = cat(w2v[15], _T_603) @[Cat.scala 29:58] + node _T_605 = cat(w2v[16], _T_604) @[Cat.scala 29:58] + node _T_606 = cat(w2v[17], _T_605) @[Cat.scala 29:58] + node _T_607 = cat(w2v[18], _T_606) @[Cat.scala 29:58] + node _T_608 = cat(w2v[19], _T_607) @[Cat.scala 29:58] + node _T_609 = cat(w2v[20], _T_608) @[Cat.scala 29:58] + node _T_610 = cat(w2v[21], _T_609) @[Cat.scala 29:58] + node _T_611 = cat(w2v[22], _T_610) @[Cat.scala 29:58] + node _T_612 = cat(w2v[23], _T_611) @[Cat.scala 29:58] + node _T_613 = cat(w2v[24], _T_612) @[Cat.scala 29:58] + node _T_614 = cat(w2v[25], _T_613) @[Cat.scala 29:58] + node _T_615 = cat(w2v[26], _T_614) @[Cat.scala 29:58] + node _T_616 = cat(w2v[27], _T_615) @[Cat.scala 29:58] + node _T_617 = cat(w2v[28], _T_616) @[Cat.scala 29:58] + node _T_618 = cat(w2v[29], _T_617) @[Cat.scala 29:58] + node _T_619 = cat(w2v[30], _T_618) @[Cat.scala 29:58] + node _T_620 = cat(w2v[31], _T_619) @[Cat.scala 29:58] + node _T_621 = or(_T_589, _T_620) @[el2_dec_gpr_ctl.scala 40:89] + gpr_wr_en <= _T_621 @[el2_dec_gpr_ctl.scala 40:12] + node _T_622 = bits(gpr_wr_en, 1, 1) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr of rvclkhdr_681 @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -70843,8 +70989,8 @@ circuit el2_swerv_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_623 <= gpr_in[1] @[el2_lib.scala 514:16] - gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 33:15] - node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[1] <= _T_623 @[el2_dec_gpr_ctl.scala 44:15] + node _T_624 = bits(gpr_wr_en, 2, 2) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_1 of rvclkhdr_682 @[el2_lib.scala 508:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -70853,8 +70999,8 @@ circuit el2_swerv_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_625 <= gpr_in[2] @[el2_lib.scala 514:16] - gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 33:15] - node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[2] <= _T_625 @[el2_dec_gpr_ctl.scala 44:15] + node _T_626 = bits(gpr_wr_en, 3, 3) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_2 of rvclkhdr_683 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -70863,8 +71009,8 @@ circuit el2_swerv_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_627 <= gpr_in[3] @[el2_lib.scala 514:16] - gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 33:15] - node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[3] <= _T_627 @[el2_dec_gpr_ctl.scala 44:15] + node _T_628 = bits(gpr_wr_en, 4, 4) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_3 of rvclkhdr_684 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -70873,8 +71019,8 @@ circuit el2_swerv_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_629 <= gpr_in[4] @[el2_lib.scala 514:16] - gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 33:15] - node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[4] <= _T_629 @[el2_dec_gpr_ctl.scala 44:15] + node _T_630 = bits(gpr_wr_en, 5, 5) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_4 of rvclkhdr_685 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -70883,8 +71029,8 @@ circuit el2_swerv_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_631 <= gpr_in[5] @[el2_lib.scala 514:16] - gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 33:15] - node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[5] <= _T_631 @[el2_dec_gpr_ctl.scala 44:15] + node _T_632 = bits(gpr_wr_en, 6, 6) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_5 of rvclkhdr_686 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -70893,8 +71039,8 @@ circuit el2_swerv_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_633 <= gpr_in[6] @[el2_lib.scala 514:16] - gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 33:15] - node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[6] <= _T_633 @[el2_dec_gpr_ctl.scala 44:15] + node _T_634 = bits(gpr_wr_en, 7, 7) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_6 of rvclkhdr_687 @[el2_lib.scala 508:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -70903,8 +71049,8 @@ circuit el2_swerv_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_635 <= gpr_in[7] @[el2_lib.scala 514:16] - gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 33:15] - node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[7] <= _T_635 @[el2_dec_gpr_ctl.scala 44:15] + node _T_636 = bits(gpr_wr_en, 8, 8) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_7 of rvclkhdr_688 @[el2_lib.scala 508:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -70913,8 +71059,8 @@ circuit el2_swerv_wrapper : rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_637 <= gpr_in[8] @[el2_lib.scala 514:16] - gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 33:15] - node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[8] <= _T_637 @[el2_dec_gpr_ctl.scala 44:15] + node _T_638 = bits(gpr_wr_en, 9, 9) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_8 of rvclkhdr_689 @[el2_lib.scala 508:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -70923,8 +71069,8 @@ circuit el2_swerv_wrapper : rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_639 <= gpr_in[9] @[el2_lib.scala 514:16] - gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 33:15] - node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[9] <= _T_639 @[el2_dec_gpr_ctl.scala 44:15] + node _T_640 = bits(gpr_wr_en, 10, 10) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_9 of rvclkhdr_690 @[el2_lib.scala 508:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -70933,8 +71079,8 @@ circuit el2_swerv_wrapper : rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_641 <= gpr_in[10] @[el2_lib.scala 514:16] - gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 33:15] - node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[10] <= _T_641 @[el2_dec_gpr_ctl.scala 44:15] + node _T_642 = bits(gpr_wr_en, 11, 11) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_10 of rvclkhdr_691 @[el2_lib.scala 508:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -70943,8 +71089,8 @@ circuit el2_swerv_wrapper : rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_643 <= gpr_in[11] @[el2_lib.scala 514:16] - gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 33:15] - node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[11] <= _T_643 @[el2_dec_gpr_ctl.scala 44:15] + node _T_644 = bits(gpr_wr_en, 12, 12) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_11 of rvclkhdr_692 @[el2_lib.scala 508:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset @@ -70953,8 +71099,8 @@ circuit el2_swerv_wrapper : rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_645 <= gpr_in[12] @[el2_lib.scala 514:16] - gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 33:15] - node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[12] <= _T_645 @[el2_dec_gpr_ctl.scala 44:15] + node _T_646 = bits(gpr_wr_en, 13, 13) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_12 of rvclkhdr_693 @[el2_lib.scala 508:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset @@ -70963,8 +71109,8 @@ circuit el2_swerv_wrapper : rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_647 <= gpr_in[13] @[el2_lib.scala 514:16] - gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 33:15] - node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[13] <= _T_647 @[el2_dec_gpr_ctl.scala 44:15] + node _T_648 = bits(gpr_wr_en, 14, 14) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_13 of rvclkhdr_694 @[el2_lib.scala 508:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset @@ -70973,8 +71119,8 @@ circuit el2_swerv_wrapper : rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_649 <= gpr_in[14] @[el2_lib.scala 514:16] - gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 33:15] - node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[14] <= _T_649 @[el2_dec_gpr_ctl.scala 44:15] + node _T_650 = bits(gpr_wr_en, 15, 15) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_14 of rvclkhdr_695 @[el2_lib.scala 508:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset @@ -70983,8 +71129,8 @@ circuit el2_swerv_wrapper : rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_651 <= gpr_in[15] @[el2_lib.scala 514:16] - gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 33:15] - node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[15] <= _T_651 @[el2_dec_gpr_ctl.scala 44:15] + node _T_652 = bits(gpr_wr_en, 16, 16) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_15 of rvclkhdr_696 @[el2_lib.scala 508:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset @@ -70993,8 +71139,8 @@ circuit el2_swerv_wrapper : rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_653 <= gpr_in[16] @[el2_lib.scala 514:16] - gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 33:15] - node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[16] <= _T_653 @[el2_dec_gpr_ctl.scala 44:15] + node _T_654 = bits(gpr_wr_en, 17, 17) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_16 of rvclkhdr_697 @[el2_lib.scala 508:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset @@ -71003,8 +71149,8 @@ circuit el2_swerv_wrapper : rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_655 <= gpr_in[17] @[el2_lib.scala 514:16] - gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 33:15] - node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[17] <= _T_655 @[el2_dec_gpr_ctl.scala 44:15] + node _T_656 = bits(gpr_wr_en, 18, 18) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_17 of rvclkhdr_698 @[el2_lib.scala 508:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset @@ -71013,8 +71159,8 @@ circuit el2_swerv_wrapper : rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_657 <= gpr_in[18] @[el2_lib.scala 514:16] - gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 33:15] - node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[18] <= _T_657 @[el2_dec_gpr_ctl.scala 44:15] + node _T_658 = bits(gpr_wr_en, 19, 19) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_18 of rvclkhdr_699 @[el2_lib.scala 508:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset @@ -71023,8 +71169,8 @@ circuit el2_swerv_wrapper : rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_659 <= gpr_in[19] @[el2_lib.scala 514:16] - gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 33:15] - node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[19] <= _T_659 @[el2_dec_gpr_ctl.scala 44:15] + node _T_660 = bits(gpr_wr_en, 20, 20) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_19 of rvclkhdr_700 @[el2_lib.scala 508:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset @@ -71033,8 +71179,8 @@ circuit el2_swerv_wrapper : rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_661 <= gpr_in[20] @[el2_lib.scala 514:16] - gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 33:15] - node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[20] <= _T_661 @[el2_dec_gpr_ctl.scala 44:15] + node _T_662 = bits(gpr_wr_en, 21, 21) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_20 of rvclkhdr_701 @[el2_lib.scala 508:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset @@ -71043,8 +71189,8 @@ circuit el2_swerv_wrapper : rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_663 <= gpr_in[21] @[el2_lib.scala 514:16] - gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 33:15] - node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[21] <= _T_663 @[el2_dec_gpr_ctl.scala 44:15] + node _T_664 = bits(gpr_wr_en, 22, 22) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_21 of rvclkhdr_702 @[el2_lib.scala 508:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset @@ -71053,8 +71199,8 @@ circuit el2_swerv_wrapper : rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_665 <= gpr_in[22] @[el2_lib.scala 514:16] - gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 33:15] - node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[22] <= _T_665 @[el2_dec_gpr_ctl.scala 44:15] + node _T_666 = bits(gpr_wr_en, 23, 23) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_22 of rvclkhdr_703 @[el2_lib.scala 508:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset @@ -71063,8 +71209,8 @@ circuit el2_swerv_wrapper : rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_667 <= gpr_in[23] @[el2_lib.scala 514:16] - gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 33:15] - node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[23] <= _T_667 @[el2_dec_gpr_ctl.scala 44:15] + node _T_668 = bits(gpr_wr_en, 24, 24) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_23 of rvclkhdr_704 @[el2_lib.scala 508:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset @@ -71073,8 +71219,8 @@ circuit el2_swerv_wrapper : rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_669 <= gpr_in[24] @[el2_lib.scala 514:16] - gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 33:15] - node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[24] <= _T_669 @[el2_dec_gpr_ctl.scala 44:15] + node _T_670 = bits(gpr_wr_en, 25, 25) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_24 of rvclkhdr_705 @[el2_lib.scala 508:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset @@ -71083,8 +71229,8 @@ circuit el2_swerv_wrapper : rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_671 <= gpr_in[25] @[el2_lib.scala 514:16] - gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 33:15] - node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[25] <= _T_671 @[el2_dec_gpr_ctl.scala 44:15] + node _T_672 = bits(gpr_wr_en, 26, 26) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_25 of rvclkhdr_706 @[el2_lib.scala 508:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset @@ -71093,8 +71239,8 @@ circuit el2_swerv_wrapper : rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_673 <= gpr_in[26] @[el2_lib.scala 514:16] - gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 33:15] - node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[26] <= _T_673 @[el2_dec_gpr_ctl.scala 44:15] + node _T_674 = bits(gpr_wr_en, 27, 27) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_26 of rvclkhdr_707 @[el2_lib.scala 508:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset @@ -71103,8 +71249,8 @@ circuit el2_swerv_wrapper : rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_675 <= gpr_in[27] @[el2_lib.scala 514:16] - gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 33:15] - node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[27] <= _T_675 @[el2_dec_gpr_ctl.scala 44:15] + node _T_676 = bits(gpr_wr_en, 28, 28) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_27 of rvclkhdr_708 @[el2_lib.scala 508:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset @@ -71113,8 +71259,8 @@ circuit el2_swerv_wrapper : rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_677 <= gpr_in[28] @[el2_lib.scala 514:16] - gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 33:15] - node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[28] <= _T_677 @[el2_dec_gpr_ctl.scala 44:15] + node _T_678 = bits(gpr_wr_en, 29, 29) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_28 of rvclkhdr_709 @[el2_lib.scala 508:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset @@ -71123,8 +71269,8 @@ circuit el2_swerv_wrapper : rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_679 <= gpr_in[29] @[el2_lib.scala 514:16] - gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 33:15] - node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[29] <= _T_679 @[el2_dec_gpr_ctl.scala 44:15] + node _T_680 = bits(gpr_wr_en, 30, 30) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_29 of rvclkhdr_710 @[el2_lib.scala 508:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset @@ -71133,8 +71279,8 @@ circuit el2_swerv_wrapper : rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_681 <= gpr_in[30] @[el2_lib.scala 514:16] - gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 33:15] - node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 33:43] + gpr_out[30] <= _T_681 @[el2_dec_gpr_ctl.scala 44:15] + node _T_682 = bits(gpr_wr_en, 31, 31) @[el2_dec_gpr_ctl.scala 44:43] inst rvclkhdr_30 of rvclkhdr_711 @[el2_lib.scala 508:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset @@ -71143,69 +71289,69 @@ circuit el2_swerv_wrapper : rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] _T_683 <= gpr_in[31] @[el2_lib.scala 514:16] - gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 33:15] - node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] - node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 36:49] - node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 36:57] + gpr_out[31] <= _T_683 @[el2_dec_gpr_ctl.scala 44:15] + node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_685 = bits(_T_684, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_686 = eq(io.raddr0, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_687 = bits(_T_686, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_688 = eq(io.raddr0, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_689 = bits(_T_688, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_690 = eq(io.raddr0, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_691 = bits(_T_690, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_692 = eq(io.raddr0, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_693 = bits(_T_692, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_694 = eq(io.raddr0, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_695 = bits(_T_694, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_696 = eq(io.raddr0, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_697 = bits(_T_696, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_698 = eq(io.raddr0, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_699 = bits(_T_698, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_700 = eq(io.raddr0, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_701 = bits(_T_700, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_702 = eq(io.raddr0, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_703 = bits(_T_702, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_704 = eq(io.raddr0, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_705 = bits(_T_704, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_706 = eq(io.raddr0, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_707 = bits(_T_706, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_708 = eq(io.raddr0, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_709 = bits(_T_708, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_710 = eq(io.raddr0, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_711 = bits(_T_710, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_712 = eq(io.raddr0, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_713 = bits(_T_712, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_714 = eq(io.raddr0, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_715 = bits(_T_714, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_716 = eq(io.raddr0, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_717 = bits(_T_716, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_718 = eq(io.raddr0, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_719 = bits(_T_718, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_720 = eq(io.raddr0, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_721 = bits(_T_720, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_722 = eq(io.raddr0, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_723 = bits(_T_722, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_724 = eq(io.raddr0, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_725 = bits(_T_724, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_726 = eq(io.raddr0, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_727 = bits(_T_726, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_728 = eq(io.raddr0, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_729 = bits(_T_728, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_730 = eq(io.raddr0, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_731 = bits(_T_730, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_732 = eq(io.raddr0, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_733 = bits(_T_732, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_734 = eq(io.raddr0, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_735 = bits(_T_734, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_736 = eq(io.raddr0, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_737 = bits(_T_736, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_738 = eq(io.raddr0, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_739 = bits(_T_738, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_740 = eq(io.raddr0, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_741 = bits(_T_740, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_742 = eq(io.raddr0, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_743 = bits(_T_742, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] + node _T_744 = eq(io.raddr0, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 47:49] + node _T_745 = bits(_T_744, 0, 0) @[el2_dec_gpr_ctl.scala 47:57] node _T_746 = mux(_T_685, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_747 = mux(_T_687, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_748 = mux(_T_689, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] @@ -71269,69 +71415,69 @@ circuit el2_swerv_wrapper : node _T_806 = or(_T_805, _T_776) @[Mux.scala 27:72] wire _T_807 : UInt<32> @[Mux.scala 27:72] _T_807 <= _T_806 @[Mux.scala 27:72] - io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 36:9] - node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] - node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 37:49] - node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 37:57] + io.rd0 <= _T_807 @[el2_dec_gpr_ctl.scala 47:9] + node _T_808 = eq(io.raddr1, UInt<1>("h01")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_809 = bits(_T_808, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_810 = eq(io.raddr1, UInt<2>("h02")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_811 = bits(_T_810, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_812 = eq(io.raddr1, UInt<2>("h03")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_813 = bits(_T_812, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_814 = eq(io.raddr1, UInt<3>("h04")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_815 = bits(_T_814, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_816 = eq(io.raddr1, UInt<3>("h05")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_817 = bits(_T_816, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_818 = eq(io.raddr1, UInt<3>("h06")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_819 = bits(_T_818, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_820 = eq(io.raddr1, UInt<3>("h07")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_821 = bits(_T_820, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_822 = eq(io.raddr1, UInt<4>("h08")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_823 = bits(_T_822, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_824 = eq(io.raddr1, UInt<4>("h09")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_825 = bits(_T_824, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_826 = eq(io.raddr1, UInt<4>("h0a")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_827 = bits(_T_826, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_828 = eq(io.raddr1, UInt<4>("h0b")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_829 = bits(_T_828, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_830 = eq(io.raddr1, UInt<4>("h0c")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_831 = bits(_T_830, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_832 = eq(io.raddr1, UInt<4>("h0d")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_833 = bits(_T_832, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_834 = eq(io.raddr1, UInt<4>("h0e")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_835 = bits(_T_834, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_836 = eq(io.raddr1, UInt<4>("h0f")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_837 = bits(_T_836, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_838 = eq(io.raddr1, UInt<5>("h010")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_839 = bits(_T_838, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_840 = eq(io.raddr1, UInt<5>("h011")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_841 = bits(_T_840, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_842 = eq(io.raddr1, UInt<5>("h012")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_843 = bits(_T_842, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_844 = eq(io.raddr1, UInt<5>("h013")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_845 = bits(_T_844, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_846 = eq(io.raddr1, UInt<5>("h014")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_847 = bits(_T_846, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_848 = eq(io.raddr1, UInt<5>("h015")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_849 = bits(_T_848, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_850 = eq(io.raddr1, UInt<5>("h016")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_851 = bits(_T_850, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_852 = eq(io.raddr1, UInt<5>("h017")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_853 = bits(_T_852, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_854 = eq(io.raddr1, UInt<5>("h018")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_855 = bits(_T_854, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_856 = eq(io.raddr1, UInt<5>("h019")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_857 = bits(_T_856, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_858 = eq(io.raddr1, UInt<5>("h01a")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_859 = bits(_T_858, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_860 = eq(io.raddr1, UInt<5>("h01b")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_861 = bits(_T_860, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_862 = eq(io.raddr1, UInt<5>("h01c")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_863 = bits(_T_862, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_864 = eq(io.raddr1, UInt<5>("h01d")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_865 = bits(_T_864, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_866 = eq(io.raddr1, UInt<5>("h01e")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_867 = bits(_T_866, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] + node _T_868 = eq(io.raddr1, UInt<5>("h01f")) @[el2_dec_gpr_ctl.scala 48:49] + node _T_869 = bits(_T_868, 0, 0) @[el2_dec_gpr_ctl.scala 48:57] node _T_870 = mux(_T_809, gpr_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_871 = mux(_T_811, gpr_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_872 = mux(_T_813, gpr_out[3], UInt<1>("h00")) @[Mux.scala 27:72] @@ -71395,7 +71541,7 @@ circuit el2_swerv_wrapper : node _T_930 = or(_T_929, _T_900) @[Mux.scala 27:72] wire _T_931 : UInt<32> @[Mux.scala 27:72] _T_931 <= _T_930 @[Mux.scala 27:72] - io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 37:9] + io.rd1 <= _T_931 @[el2_dec_gpr_ctl.scala 48:9] extmodule gated_latch_712 : output Q : Clock @@ -71495,15 +71641,21 @@ circuit el2_swerv_wrapper : module el2_dec_timer_ctl : input clock : Clock - input reset : Reset + input reset : AsyncReset output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wen_r_mod : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip csr_mitctl0 : UInt<1>, flip csr_mitctl1 : UInt<1>, flip csr_mitb0 : UInt<1>, flip csr_mitb1 : UInt<1>, flip csr_mitcnt0 : UInt<1>, flip csr_mitcnt1 : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip internal_dbg_halt_timers : UInt<1>, dec_timer_rddata_d : UInt<32>, dec_timer_read_d : UInt<1>, dec_timer_t0_pulse : UInt<1>, dec_timer_t1_pulse : UInt<1>} - wire mitctl1 : UInt<4> @[el2_dec_tlu_ctl.scala 2745:19] - wire mitctl0 : UInt<3> @[el2_dec_tlu_ctl.scala 2746:19] - wire mitb1 : UInt<32> @[el2_dec_tlu_ctl.scala 2747:19] - wire mitb0 : UInt<32> @[el2_dec_tlu_ctl.scala 2748:19] - wire mitcnt1 : UInt<32> @[el2_dec_tlu_ctl.scala 2749:19] - wire mitcnt0 : UInt<32> @[el2_dec_tlu_ctl.scala 2750:19] + wire mitctl1 : UInt<4> + mitctl1 <= UInt<1>("h00") + wire mitctl0 : UInt<3> + mitctl0 <= UInt<1>("h00") + wire mitb1 : UInt<32> + mitb1 <= UInt<1>("h00") + wire mitb0 : UInt<32> + mitb0 <= UInt<1>("h00") + wire mitcnt1 : UInt<32> + mitcnt1 <= UInt<1>("h00") + wire mitcnt0 : UInt<32> + mitcnt0 <= UInt<1>("h00") node mit0_match_ns = geq(mitcnt0, mitb0) @[el2_dec_tlu_ctl.scala 2752:30] node mit1_match_ns = geq(mitcnt1, mitb1) @[el2_dec_tlu_ctl.scala 2753:30] io.dec_timer_t0_pulse <= mit0_match_ns @[el2_dec_tlu_ctl.scala 2755:25] @@ -71527,9 +71679,9 @@ circuit el2_swerv_wrapper : node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[el2_dec_tlu_ctl.scala 2767:68] node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[el2_dec_tlu_ctl.scala 2767:54] node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[el2_dec_tlu_ctl.scala 2767:23] - node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:60] - node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:77] - node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:94] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[el2_dec_tlu_ctl.scala 2768:59] + node _T_16 = or(_T_15, mit0_match_ns) @[el2_dec_tlu_ctl.scala 2768:76] + node _T_17 = bits(_T_16, 0, 0) @[el2_dec_tlu_ctl.scala 2768:93] inst rvclkhdr of rvclkhdr_712 @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -71591,7 +71743,7 @@ circuit el2_swerv_wrapper : mitb0 <= _T_46 @[el2_dec_tlu_ctl.scala 2791:11] node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[el2_dec_tlu_ctl.scala 2798:63] node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[el2_dec_tlu_ctl.scala 2798:41] - node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:24] + node _T_48 = not(io.dec_csr_wrdata_r) @[el2_dec_tlu_ctl.scala 2799:23] node _T_49 = bits(wr_mitb1_r, 0, 0) @[el2_dec_tlu_ctl.scala 2799:56] inst rvclkhdr_3 of rvclkhdr_715 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock @@ -72605,15 +72757,21 @@ circuit el2_swerv_wrapper : module csr_tlu : input clock : Clock - input reset : Reset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]} + input reset : AsyncReset + output io : {flip free_clk : Clock, flip active_clk : Clock, flip scan_mode : UInt<1>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip ifu_ic_debug_rd_data_valid : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_pmu_bus_trxn : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, flip dec_csr_wen_r : UInt<1>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, dec_tlu_meipt : UInt<4>, flip pic_pl : UInt<4>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meihap : UInt<30>, flip pic_claimid : UInt<8>, flip iccm_dma_sb_error : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dec_illegal_inst : UInt<32>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip mexintpend : UInt<1>, flip exu_npc_r : UInt<31>, flip mpc_reset_run_req : UInt<1>, flip rst_vec : UInt<31>, flip core_id : UInt<28>, flip dec_timer_rddata_d : UInt<32>, flip dec_timer_read_d : UInt<1>, dec_csr_wen_r_mod : UInt<1>, flip rfpc_i0_r : UInt<1>, flip i0_trigger_hit_r : UInt<1>, fw_halt_req : UInt<1>, mstatus : UInt<2>, flip exc_or_int_valid_r : UInt<1>, flip mret_r : UInt<1>, mstatus_mie_ns : UInt<1>, flip dcsr_single_step_running_f : UInt<1>, dcsr : UInt<16>, mtvec : UInt<31>, mip : UInt<6>, flip dec_timer_t0_pulse : UInt<1>, flip dec_timer_t1_pulse : UInt<1>, flip timer_int_sync : UInt<1>, flip soft_int_sync : UInt<1>, mie_ns : UInt<6>, flip csr_wr_clk : Clock, flip ebreak_to_debug_mode_r : UInt<1>, flip dec_tlu_pmu_fw_halted : UInt<1>, flip lsu_fir_error : UInt<2>, npc_r : UInt<31>, flip tlu_flush_lower_r_d1 : UInt<1>, flip dec_tlu_flush_noredir_r_d1 : UInt<1>, flip tlu_flush_path_r_d1 : UInt<31>, npc_r_d1 : UInt<31>, flip reset_delayed : UInt<1>, mepc : UInt<31>, flip interrupt_valid_r : UInt<1>, flip i0_exception_valid_r : UInt<1>, flip lsu_exc_valid_r : UInt<1>, flip mepc_trigger_hit_sel_pc_r : UInt<1>, flip e4e5_int_clk : Clock, flip lsu_i0_exc_r : UInt<1>, flip inst_acc_r : UInt<1>, flip inst_acc_second_r : UInt<1>, flip take_nmi : UInt<1>, flip lsu_error_pkt_addr_r : UInt<32>, flip exc_cause_r : UInt<5>, flip i0_valid_wb : UInt<1>, flip exc_or_int_valid_r_d1 : UInt<1>, flip interrupt_valid_r_d1 : UInt<1>, flip clk_override : UInt<1>, flip i0_exception_valid_r_d1 : UInt<1>, flip lsu_i0_exc_r_d1 : UInt<1>, flip exc_cause_wb : UInt<5>, flip nmi_lsu_store_type : UInt<1>, flip nmi_lsu_load_type : UInt<1>, flip tlu_i0_commit_cmt : UInt<1>, flip ebreak_r : UInt<1>, flip ecall_r : UInt<1>, flip illegal_r : UInt<1>, mdseac_locked_ns : UInt<1>, flip mdseac_locked_f : UInt<1>, flip nmi_int_detected_f : UInt<1>, flip internal_dbg_halt_mode_f2 : UInt<1>, flip ext_int_freeze_d1 : UInt<1>, flip ic_perr_r_d1 : UInt<1>, flip iccm_sbecc_r_d1 : UInt<1>, flip lsu_single_ecc_error_r_d1 : UInt<1>, flip ifu_miss_state_idle_f : UInt<1>, flip lsu_idle_any_f : UInt<1>, flip dbg_tlu_halted_f : UInt<1>, flip dbg_tlu_halted : UInt<1>, flip debug_halt_req_f : UInt<1>, force_halt : UInt<1>, flip take_ext_int_start : UInt<1>, flip trigger_hit_dmode_r_d1 : UInt<1>, flip trigger_hit_r_d1 : UInt<1>, flip dcsr_single_step_done_f : UInt<1>, flip ebreak_to_debug_mode_r_d1 : UInt<1>, flip debug_halt_req : UInt<1>, flip allow_dbg_halt_csr_write : UInt<1>, flip internal_dbg_halt_mode_f : UInt<1>, flip enter_debug_halt_req : UInt<1>, flip internal_dbg_halt_mode : UInt<1>, flip request_debug_mode_done : UInt<1>, flip request_debug_mode_r : UInt<1>, dpc : UInt<31>, flip update_hit_bit_r : UInt<4>, flip take_timer_int : UInt<1>, flip take_int_timer0_int : UInt<1>, flip take_int_timer1_int : UInt<1>, flip take_ext_int : UInt<1>, flip tlu_flush_lower_r : UInt<1>, flip dec_tlu_br0_error_r : UInt<1>, flip dec_tlu_br0_start_error_r : UInt<1>, flip lsu_pmu_load_external_r : UInt<1>, flip lsu_pmu_store_external_r : UInt<1>, flip csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}, mtdata1_t : UInt<10>[4]} - wire miccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1454:41] - wire mice_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1455:41] - wire mdccme_ce_req : UInt<1> @[el2_dec_tlu_ctl.scala 1456:41] - wire pc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 1457:41] - wire mpmc_b_ns : UInt<1> @[el2_dec_tlu_ctl.scala 1458:41] - wire mpmc_b : UInt<1> @[el2_dec_tlu_ctl.scala 1459:41] + wire miccme_ce_req : UInt<1> + miccme_ce_req <= UInt<1>("h00") + wire mice_ce_req : UInt<1> + mice_ce_req <= UInt<1>("h00") + wire mdccme_ce_req : UInt<1> + mdccme_ce_req <= UInt<1>("h00") + wire pc_r_d1 : UInt<31> + pc_r_d1 <= UInt<1>("h00") + wire mpmc_b_ns : UInt<1> + mpmc_b_ns <= UInt<1>("h00") + wire mpmc_b : UInt<1> + mpmc_b <= UInt<1>("h00") wire wr_mcycleh_r : UInt<1> wr_mcycleh_r <= UInt<1>("h00") wire mcycleh : UInt<32> @@ -74068,8 +74226,8 @@ circuit el2_swerv_wrapper : mtdata1_tsel_out <= _T_941 @[Mux.scala 27:72] node _T_942 = bits(io.mtdata1_t[0], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[0].select <= _T_942 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[0].match_ <= _T_943 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_943 = bits(io.mtdata1_t[0], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[0].match_pkt <= _T_943 @[el2_dec_tlu_ctl.scala 2309:39] node _T_944 = bits(io.mtdata1_t[0], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[0].store <= _T_944 @[el2_dec_tlu_ctl.scala 2310:36] node _T_945 = bits(io.mtdata1_t[0], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -74080,8 +74238,8 @@ circuit el2_swerv_wrapper : io.trigger_pkt_any[0].m <= _T_947 @[el2_dec_tlu_ctl.scala 2313:36] node _T_948 = bits(io.mtdata1_t[1], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[1].select <= _T_948 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[1].match_ <= _T_949 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_949 = bits(io.mtdata1_t[1], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[1].match_pkt <= _T_949 @[el2_dec_tlu_ctl.scala 2309:39] node _T_950 = bits(io.mtdata1_t[1], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[1].store <= _T_950 @[el2_dec_tlu_ctl.scala 2310:36] node _T_951 = bits(io.mtdata1_t[1], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -74092,8 +74250,8 @@ circuit el2_swerv_wrapper : io.trigger_pkt_any[1].m <= _T_953 @[el2_dec_tlu_ctl.scala 2313:36] node _T_954 = bits(io.mtdata1_t[2], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[2].select <= _T_954 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[2].match_ <= _T_955 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_955 = bits(io.mtdata1_t[2], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[2].match_pkt <= _T_955 @[el2_dec_tlu_ctl.scala 2309:39] node _T_956 = bits(io.mtdata1_t[2], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[2].store <= _T_956 @[el2_dec_tlu_ctl.scala 2310:36] node _T_957 = bits(io.mtdata1_t[2], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -74104,8 +74262,8 @@ circuit el2_swerv_wrapper : io.trigger_pkt_any[2].m <= _T_959 @[el2_dec_tlu_ctl.scala 2313:36] node _T_960 = bits(io.mtdata1_t[3], 7, 7) @[el2_dec_tlu_ctl.scala 2308:54] io.trigger_pkt_any[3].select <= _T_960 @[el2_dec_tlu_ctl.scala 2308:36] - node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:54] - io.trigger_pkt_any[3].match_ <= _T_961 @[el2_dec_tlu_ctl.scala 2309:36] + node _T_961 = bits(io.mtdata1_t[3], 4, 4) @[el2_dec_tlu_ctl.scala 2309:57] + io.trigger_pkt_any[3].match_pkt <= _T_961 @[el2_dec_tlu_ctl.scala 2309:39] node _T_962 = bits(io.mtdata1_t[3], 1, 1) @[el2_dec_tlu_ctl.scala 2310:54] io.trigger_pkt_any[3].store <= _T_962 @[el2_dec_tlu_ctl.scala 2310:36] node _T_963 = bits(io.mtdata1_t[3], 0, 0) @[el2_dec_tlu_ctl.scala 2311:54] @@ -75986,7 +76144,7 @@ circuit el2_swerv_wrapper : module el2_dec_decode_csr_read : input clock : Clock - input reset : Reset + input reset : AsyncReset output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[el2_dec_tlu_ctl.scala 2648:143] @@ -77668,124 +77826,238 @@ circuit el2_swerv_wrapper : module el2_dec_tlu_ctl : input clock : Clock input reset : AsyncReset - output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>} + output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>} wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 236:59] - wire pause_expired_wb : UInt<1> @[el2_dec_tlu_ctl.scala 237:54] - wire take_nmi_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 238:62] - wire exc_or_int_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 239:54] - wire interrupt_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 240:54] - wire tlu_flush_lower_r : UInt<1> @[el2_dec_tlu_ctl.scala 241:54] - wire synchronous_flush_r : UInt<1> @[el2_dec_tlu_ctl.scala 242:62] - wire interrupt_valid_r : UInt<1> @[el2_dec_tlu_ctl.scala 243:54] - wire take_nmi : UInt<1> @[el2_dec_tlu_ctl.scala 244:62] - wire take_reset : UInt<1> @[el2_dec_tlu_ctl.scala 245:70] - wire take_int_timer1_int : UInt<1> @[el2_dec_tlu_ctl.scala 246:62] - wire take_int_timer0_int : UInt<1> @[el2_dec_tlu_ctl.scala 247:62] - wire take_timer_int : UInt<1> @[el2_dec_tlu_ctl.scala 248:62] - wire take_soft_int : UInt<1> @[el2_dec_tlu_ctl.scala 249:62] - wire take_ce_int : UInt<1> @[el2_dec_tlu_ctl.scala 250:70] - wire take_ext_int_start : UInt<1> @[el2_dec_tlu_ctl.scala 251:62] - wire ext_int_freeze : UInt<1> @[el2_dec_tlu_ctl.scala 252:62] - wire ext_int_freeze_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 253:62] - wire take_ext_int_start_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 254:54] - wire take_ext_int_start_d2 : UInt<1> @[el2_dec_tlu_ctl.scala 255:54] - wire take_ext_int_start_d3 : UInt<1> @[el2_dec_tlu_ctl.scala 256:54] - wire fast_int_meicpct : UInt<1> @[el2_dec_tlu_ctl.scala 257:54] - wire ignore_ext_int_due_to_lsu_stall : UInt<1> @[el2_dec_tlu_ctl.scala 258:44] - wire take_ext_int : UInt<1> @[el2_dec_tlu_ctl.scala 259:62] - wire internal_dbg_halt_timers : UInt<1> @[el2_dec_tlu_ctl.scala 260:46] - wire int_timer1_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 261:62] - wire int_timer0_int_hold : UInt<1> @[el2_dec_tlu_ctl.scala 262:62] - wire mhwakeup_ready : UInt<1> @[el2_dec_tlu_ctl.scala 263:62] - wire ext_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 264:54] - wire ce_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 265:54] - wire soft_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 266:54] - wire timer_int_ready : UInt<1> @[el2_dec_tlu_ctl.scala 267:54] - wire ebreak_to_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 268:54] - wire ebreak_to_debug_mode_r : UInt<1> @[el2_dec_tlu_ctl.scala 269:54] - wire inst_acc_r : UInt<1> @[el2_dec_tlu_ctl.scala 270:70] - wire inst_acc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 271:62] - wire iccm_sbecc_r : UInt<1> @[el2_dec_tlu_ctl.scala 272:62] - wire ic_perr_r : UInt<1> @[el2_dec_tlu_ctl.scala 273:62] - wire fence_i_r : UInt<1> @[el2_dec_tlu_ctl.scala 274:62] - wire ebreak_r : UInt<1> @[el2_dec_tlu_ctl.scala 275:62] - wire ecall_r : UInt<1> @[el2_dec_tlu_ctl.scala 276:62] - wire illegal_r : UInt<1> @[el2_dec_tlu_ctl.scala 277:62] - wire mret_r : UInt<1> @[el2_dec_tlu_ctl.scala 278:62] - wire iccm_repair_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 279:54] - wire rfpc_i0_r : UInt<1> @[el2_dec_tlu_ctl.scala 280:70] - wire tlu_i0_kill_writeb_r : UInt<1> @[el2_dec_tlu_ctl.scala 281:54] - wire lsu_exc_valid_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 282:62] - wire lsu_i0_exc_r_raw : UInt<1> @[el2_dec_tlu_ctl.scala 283:54] - wire mdseac_locked_f : UInt<1> @[el2_dec_tlu_ctl.scala 284:62] - wire i_cpu_run_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 285:54] - wire cpu_run_ack : UInt<1> @[el2_dec_tlu_ctl.scala 286:70] - wire cpu_halt_status : UInt<1> @[el2_dec_tlu_ctl.scala 287:62] - wire cpu_halt_ack : UInt<1> @[el2_dec_tlu_ctl.scala 288:62] - wire pmu_fw_tlu_halted : UInt<1> @[el2_dec_tlu_ctl.scala 289:54] - wire internal_pmu_fw_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 290:46] - wire pmu_fw_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 291:62] - wire pmu_fw_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 292:62] - wire pmu_fw_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 293:54] - wire int_timer0_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 294:54] - wire int_timer1_int_hold_f : UInt<1> @[el2_dec_tlu_ctl.scala 295:54] - wire trigger_hit_dmode_r : UInt<1> @[el2_dec_tlu_ctl.scala 296:54] - wire i0_trigger_hit_r : UInt<1> @[el2_dec_tlu_ctl.scala 297:54] - wire pause_expired_r : UInt<1> @[el2_dec_tlu_ctl.scala 298:62] - wire dec_tlu_pmu_fw_halted : UInt<1> @[el2_dec_tlu_ctl.scala 299:54] - wire dec_tlu_flush_noredir_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 300:54] - wire halt_taken_f : UInt<1> @[el2_dec_tlu_ctl.scala 301:62] - wire lsu_idle_any_f : UInt<1> @[el2_dec_tlu_ctl.scala 302:62] - wire ifu_miss_state_idle_f : UInt<1> @[el2_dec_tlu_ctl.scala 303:54] - wire dbg_tlu_halted_f : UInt<1> @[el2_dec_tlu_ctl.scala 304:54] - wire debug_halt_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 305:54] - wire debug_resume_req_f : UInt<1> @[el2_dec_tlu_ctl.scala 306:62] - wire trigger_hit_dmode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 307:54] - wire dcsr_single_step_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 308:54] - wire debug_halt_req_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 309:54] - wire request_debug_mode_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 310:54] - wire request_debug_mode_done_f : UInt<1> @[el2_dec_tlu_ctl.scala 311:46] - wire dcsr_single_step_running_f : UInt<1> @[el2_dec_tlu_ctl.scala 312:54] - wire dec_tlu_flush_pause_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 313:46] - wire dbg_halt_req_held : UInt<1> @[el2_dec_tlu_ctl.scala 314:54] - wire debug_halt_req_ns : UInt<1> @[el2_dec_tlu_ctl.scala 315:62] - wire internal_dbg_halt_mode : UInt<1> @[el2_dec_tlu_ctl.scala 316:54] - wire core_empty : UInt<1> @[el2_dec_tlu_ctl.scala 317:70] - wire dbg_halt_req_final : UInt<1> @[el2_dec_tlu_ctl.scala 318:62] - wire debug_brkpt_status_ns : UInt<1> @[el2_dec_tlu_ctl.scala 319:54] - wire mpc_debug_halt_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 320:54] - wire mpc_debug_run_ack_ns : UInt<1> @[el2_dec_tlu_ctl.scala 321:54] - wire mpc_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 322:62] - wire mpc_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 323:54] - wire dbg_halt_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 324:62] - wire dbg_run_state_ns : UInt<1> @[el2_dec_tlu_ctl.scala 325:54] - wire dbg_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 326:54] - wire mpc_halt_state_f : UInt<1> @[el2_dec_tlu_ctl.scala 327:54] - wire nmi_int_detected : UInt<1> @[el2_dec_tlu_ctl.scala 328:54] - wire nmi_lsu_load_type : UInt<1> @[el2_dec_tlu_ctl.scala 329:62] - wire nmi_lsu_store_type : UInt<1> @[el2_dec_tlu_ctl.scala 330:62] - wire reset_delayed : UInt<1> @[el2_dec_tlu_ctl.scala 331:62] - wire debug_mode_status : UInt<1> @[el2_dec_tlu_ctl.scala 332:46] - wire e5_valid : UInt<1> @[el2_dec_tlu_ctl.scala 333:62] - wire ic_perr_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 334:62] - wire iccm_sbecc_r_d1 : UInt<1> @[el2_dec_tlu_ctl.scala 335:62] - wire npc_r : UInt<31> @[el2_dec_tlu_ctl.scala 337:41] - wire npc_r_d1 : UInt<31> @[el2_dec_tlu_ctl.scala 338:41] - wire mie_ns : UInt<6> @[el2_dec_tlu_ctl.scala 339:41] - wire mepc : UInt<31> @[el2_dec_tlu_ctl.scala 340:41] - wire mdseac_locked_ns : UInt<1> @[el2_dec_tlu_ctl.scala 341:41] - wire force_halt : UInt<1> @[el2_dec_tlu_ctl.scala 342:57] - wire dpc : UInt<31> @[el2_dec_tlu_ctl.scala 343:41] - wire mstatus_mie_ns : UInt<1> @[el2_dec_tlu_ctl.scala 344:41] - wire dec_csr_wen_r_mod : UInt<1> @[el2_dec_tlu_ctl.scala 345:41] - wire fw_halt_req : UInt<1> @[el2_dec_tlu_ctl.scala 346:41] - wire mstatus : UInt<2> @[el2_dec_tlu_ctl.scala 347:41] - wire dcsr : UInt<16> @[el2_dec_tlu_ctl.scala 348:41] - wire mtvec : UInt<31> @[el2_dec_tlu_ctl.scala 349:41] - wire mip : UInt<6> @[el2_dec_tlu_ctl.scala 350:41] + wire pause_expired_wb : UInt<1> + pause_expired_wb <= UInt<1>("h00") + wire take_nmi_r_d1 : UInt<1> + take_nmi_r_d1 <= UInt<1>("h00") + wire exc_or_int_valid_r_d1 : UInt<1> + exc_or_int_valid_r_d1 <= UInt<1>("h00") + wire interrupt_valid_r_d1 : UInt<1> + interrupt_valid_r_d1 <= UInt<1>("h00") + wire tlu_flush_lower_r : UInt<1> + tlu_flush_lower_r <= UInt<1>("h00") + wire synchronous_flush_r : UInt<1> + synchronous_flush_r <= UInt<1>("h00") + wire interrupt_valid_r : UInt<1> + interrupt_valid_r <= UInt<1>("h00") + wire take_nmi : UInt<1> + take_nmi <= UInt<1>("h00") + wire take_reset : UInt<1> + take_reset <= UInt<1>("h00") + wire take_int_timer1_int : UInt<1> + take_int_timer1_int <= UInt<1>("h00") + wire take_int_timer0_int : UInt<1> + take_int_timer0_int <= UInt<1>("h00") + wire take_timer_int : UInt<1> + take_timer_int <= UInt<1>("h00") + wire take_soft_int : UInt<1> + take_soft_int <= UInt<1>("h00") + wire take_ce_int : UInt<1> + take_ce_int <= UInt<1>("h00") + wire take_ext_int_start : UInt<1> + take_ext_int_start <= UInt<1>("h00") + wire ext_int_freeze : UInt<1> + ext_int_freeze <= UInt<1>("h00") + wire ext_int_freeze_d1 : UInt<1> + ext_int_freeze_d1 <= UInt<1>("h00") + wire take_ext_int_start_d1 : UInt<1> + take_ext_int_start_d1 <= UInt<1>("h00") + wire take_ext_int_start_d2 : UInt<1> + take_ext_int_start_d2 <= UInt<1>("h00") + wire take_ext_int_start_d3 : UInt<1> + take_ext_int_start_d3 <= UInt<1>("h00") + wire fast_int_meicpct : UInt<1> + fast_int_meicpct <= UInt<1>("h00") + wire ignore_ext_int_due_to_lsu_stall : UInt<1> + ignore_ext_int_due_to_lsu_stall <= UInt<1>("h00") + wire take_ext_int : UInt<1> + take_ext_int <= UInt<1>("h00") + wire internal_dbg_halt_timers : UInt<1> + internal_dbg_halt_timers <= UInt<1>("h00") + wire int_timer1_int_hold : UInt<1> + int_timer1_int_hold <= UInt<1>("h00") + wire int_timer0_int_hold : UInt<1> + int_timer0_int_hold <= UInt<1>("h00") + wire mhwakeup_ready : UInt<1> + mhwakeup_ready <= UInt<1>("h00") + wire ext_int_ready : UInt<1> + ext_int_ready <= UInt<1>("h00") + wire ce_int_ready : UInt<1> + ce_int_ready <= UInt<1>("h00") + wire soft_int_ready : UInt<1> + soft_int_ready <= UInt<1>("h00") + wire timer_int_ready : UInt<1> + timer_int_ready <= UInt<1>("h00") + wire ebreak_to_debug_mode_r_d1 : UInt<1> + ebreak_to_debug_mode_r_d1 <= UInt<1>("h00") + wire ebreak_to_debug_mode_r : UInt<1> + ebreak_to_debug_mode_r <= UInt<1>("h00") + wire inst_acc_r : UInt<1> + inst_acc_r <= UInt<1>("h00") + wire inst_acc_r_raw : UInt<1> + inst_acc_r_raw <= UInt<1>("h00") + wire iccm_sbecc_r : UInt<1> + iccm_sbecc_r <= UInt<1>("h00") + wire ic_perr_r : UInt<1> + ic_perr_r <= UInt<1>("h00") + wire fence_i_r : UInt<1> + fence_i_r <= UInt<1>("h00") + wire ebreak_r : UInt<1> + ebreak_r <= UInt<1>("h00") + wire ecall_r : UInt<1> + ecall_r <= UInt<1>("h00") + wire illegal_r : UInt<1> + illegal_r <= UInt<1>("h00") + wire mret_r : UInt<1> + mret_r <= UInt<1>("h00") + wire iccm_repair_state_ns : UInt<1> + iccm_repair_state_ns <= UInt<1>("h00") + wire rfpc_i0_r : UInt<1> + rfpc_i0_r <= UInt<1>("h00") + wire tlu_i0_kill_writeb_r : UInt<1> + tlu_i0_kill_writeb_r <= UInt<1>("h00") + wire lsu_exc_valid_r_d1 : UInt<1> + lsu_exc_valid_r_d1 <= UInt<1>("h00") + wire lsu_i0_exc_r_raw : UInt<1> + lsu_i0_exc_r_raw <= UInt<1>("h00") + wire mdseac_locked_f : UInt<1> + mdseac_locked_f <= UInt<1>("h00") + wire i_cpu_run_req_d1 : UInt<1> + i_cpu_run_req_d1 <= UInt<1>("h00") + wire cpu_run_ack : UInt<1> + cpu_run_ack <= UInt<1>("h00") + wire cpu_halt_status : UInt<1> + cpu_halt_status <= UInt<1>("h00") + wire cpu_halt_ack : UInt<1> + cpu_halt_ack <= UInt<1>("h00") + wire pmu_fw_tlu_halted : UInt<1> + pmu_fw_tlu_halted <= UInt<1>("h00") + wire internal_pmu_fw_halt_mode : UInt<1> + internal_pmu_fw_halt_mode <= UInt<1>("h00") + wire pmu_fw_halt_req_ns : UInt<1> + pmu_fw_halt_req_ns <= UInt<1>("h00") + wire pmu_fw_halt_req_f : UInt<1> + pmu_fw_halt_req_f <= UInt<1>("h00") + wire pmu_fw_tlu_halted_f : UInt<1> + pmu_fw_tlu_halted_f <= UInt<1>("h00") + wire int_timer0_int_hold_f : UInt<1> + int_timer0_int_hold_f <= UInt<1>("h00") + wire int_timer1_int_hold_f : UInt<1> + int_timer1_int_hold_f <= UInt<1>("h00") + wire trigger_hit_dmode_r : UInt<1> + trigger_hit_dmode_r <= UInt<1>("h00") + wire i0_trigger_hit_r : UInt<1> + i0_trigger_hit_r <= UInt<1>("h00") + wire pause_expired_r : UInt<1> + pause_expired_r <= UInt<1>("h00") + wire dec_tlu_pmu_fw_halted : UInt<1> + dec_tlu_pmu_fw_halted <= UInt<1>("h00") + wire dec_tlu_flush_noredir_r_d1 : UInt<1> + dec_tlu_flush_noredir_r_d1 <= UInt<1>("h00") + wire halt_taken_f : UInt<1> + halt_taken_f <= UInt<1>("h00") + wire lsu_idle_any_f : UInt<1> + lsu_idle_any_f <= UInt<1>("h00") + wire ifu_miss_state_idle_f : UInt<1> + ifu_miss_state_idle_f <= UInt<1>("h00") + wire dbg_tlu_halted_f : UInt<1> + dbg_tlu_halted_f <= UInt<1>("h00") + wire debug_halt_req_f : UInt<1> + debug_halt_req_f <= UInt<1>("h00") + wire debug_resume_req_f : UInt<1> + debug_resume_req_f <= UInt<1>("h00") + wire trigger_hit_dmode_r_d1 : UInt<1> + trigger_hit_dmode_r_d1 <= UInt<1>("h00") + wire dcsr_single_step_done_f : UInt<1> + dcsr_single_step_done_f <= UInt<1>("h00") + wire debug_halt_req_d1 : UInt<1> + debug_halt_req_d1 <= UInt<1>("h00") + wire request_debug_mode_r_d1 : UInt<1> + request_debug_mode_r_d1 <= UInt<1>("h00") + wire request_debug_mode_done_f : UInt<1> + request_debug_mode_done_f <= UInt<1>("h00") + wire dcsr_single_step_running_f : UInt<1> + dcsr_single_step_running_f <= UInt<1>("h00") + wire dec_tlu_flush_pause_r_d1 : UInt<1> + dec_tlu_flush_pause_r_d1 <= UInt<1>("h00") + wire dbg_halt_req_held : UInt<1> + dbg_halt_req_held <= UInt<1>("h00") + wire debug_halt_req_ns : UInt<1> + debug_halt_req_ns <= UInt<1>("h00") + wire internal_dbg_halt_mode : UInt<1> + internal_dbg_halt_mode <= UInt<1>("h00") + wire core_empty : UInt<1> + core_empty <= UInt<1>("h00") + wire dbg_halt_req_final : UInt<1> + dbg_halt_req_final <= UInt<1>("h00") + wire debug_brkpt_status_ns : UInt<1> + debug_brkpt_status_ns <= UInt<1>("h00") + wire mpc_debug_halt_ack_ns : UInt<1> + mpc_debug_halt_ack_ns <= UInt<1>("h00") + wire mpc_debug_run_ack_ns : UInt<1> + mpc_debug_run_ack_ns <= UInt<1>("h00") + wire mpc_halt_state_ns : UInt<1> + mpc_halt_state_ns <= UInt<1>("h00") + wire mpc_run_state_ns : UInt<1> + mpc_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_ns : UInt<1> + dbg_halt_state_ns <= UInt<1>("h00") + wire dbg_run_state_ns : UInt<1> + dbg_run_state_ns <= UInt<1>("h00") + wire dbg_halt_state_f : UInt<1> + dbg_halt_state_f <= UInt<1>("h00") + wire mpc_halt_state_f : UInt<1> + mpc_halt_state_f <= UInt<1>("h00") + wire nmi_int_detected : UInt<1> + nmi_int_detected <= UInt<1>("h00") + wire nmi_lsu_load_type : UInt<1> + nmi_lsu_load_type <= UInt<1>("h00") + wire nmi_lsu_store_type : UInt<1> + nmi_lsu_store_type <= UInt<1>("h00") + wire reset_delayed : UInt<1> + reset_delayed <= UInt<1>("h00") + wire debug_mode_status : UInt<1> + debug_mode_status <= UInt<1>("h00") + wire e5_valid : UInt<1> + e5_valid <= UInt<1>("h00") + wire ic_perr_r_d1 : UInt<1> + ic_perr_r_d1 <= UInt<1>("h00") + wire iccm_sbecc_r_d1 : UInt<1> + iccm_sbecc_r_d1 <= UInt<1>("h00") + wire npc_r : UInt<31> + npc_r <= UInt<1>("h00") + wire npc_r_d1 : UInt<31> + npc_r_d1 <= UInt<1>("h00") + wire mie_ns : UInt<6> + mie_ns <= UInt<1>("h00") + wire mepc : UInt<31> + mepc <= UInt<1>("h00") + wire mdseac_locked_ns : UInt<1> + mdseac_locked_ns <= UInt<1>("h00") + wire force_halt : UInt<1> + force_halt <= UInt<1>("h00") + wire dpc : UInt<31> + dpc <= UInt<1>("h00") + wire mstatus_mie_ns : UInt<1> + mstatus_mie_ns <= UInt<1>("h00") + wire dec_csr_wen_r_mod : UInt<1> + dec_csr_wen_r_mod <= UInt<1>("h00") + wire fw_halt_req : UInt<1> + fw_halt_req <= UInt<1>("h00") + wire mstatus : UInt<2> + mstatus <= UInt<1>("h00") + wire dcsr : UInt<16> + dcsr <= UInt<1>("h00") + wire mtvec : UInt<31> + mtvec <= UInt<1>("h00") + wire mip : UInt<6> + mip <= UInt<1>("h00") wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[el2_dec_tlu_ctl.scala 351:41] - wire dec_tlu_mpc_halted_only_ns : UInt<1> @[el2_dec_tlu_ctl.scala 352:41] + wire dec_tlu_mpc_halted_only_ns : UInt<1> + dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") node _T = not(dbg_halt_state_f) @[el2_dec_tlu_ctl.scala 354:33] node _T_1 = and(_T, mpc_halt_state_f) @[el2_dec_tlu_ctl.scala 354:51] dec_tlu_mpc_halted_only_ns <= _T_1 @[el2_dec_tlu_ctl.scala 354:30] @@ -78449,7 +78721,7 @@ circuit el2_swerv_wrapper : lsu_exc_valid_r_d1 <= _T_407 @[el2_dec_tlu_ctl.scala 693:41] reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_tlu_ctl.scala 694:73] lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[el2_dec_tlu_ctl.scala 694:73] - node _T_408 = eq(io.lsu_error_pkt_r.bits.exc_type, UInt<1>("h00")) @[el2_dec_tlu_ctl.scala 695:39] + node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 695:39] node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[el2_dec_tlu_ctl.scala 695:37] node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[el2_dec_tlu_ctl.scala 696:37] node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[el2_dec_tlu_ctl.scala 697:37] @@ -78517,12 +78789,12 @@ circuit el2_swerv_wrapper : node _T_461 = not(io.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 727:118] node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 727:116] node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 727:94] - io.dec_tlu_br0_r_pkt.bits.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:57] - io.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49] - io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:49] + io.dec_tlu_br0_r_pkt.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:49] + io.dec_tlu_br0_r_pkt.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49] + io.dec_tlu_br0_r_pkt.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:41] io.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 733:49] - io.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:57] - io.dec_tlu_br0_r_pkt.bits.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:57] + io.dec_tlu_br0_r_pkt.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:49] + io.dec_tlu_br0_r_pkt.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:49] node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 738:51] node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64] node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90] @@ -79095,28 +79367,28 @@ circuit el2_swerv_wrapper : io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[0].match_ <= csr.io.trigger_pkt_any[0].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[1].match_ <= csr.io.trigger_pkt_any[1].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[2].match_ <= csr.io.trigger_pkt_any[2].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[el2_dec_tlu_ctl.scala 962:40] - io.trigger_pkt_any[3].match_ <= csr.io.trigger_pkt_any[3].match_ @[el2_dec_tlu_ctl.scala 962:40] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[el2_dec_tlu_ctl.scala 962:40] io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[el2_dec_tlu_ctl.scala 962:40] io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[el2_dec_tlu_ctl.scala 963:40] io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[el2_dec_tlu_ctl.scala 964:40] @@ -79432,7 +79704,7 @@ circuit el2_swerv_wrapper : module el2_dec_trigger : input clock : Clock input reset : Reset - output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_i0_pc_d : UInt<31>, dec_i0_trigger_match_d : UInt<4>} node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_dec_trigger.scala 14:63] node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[el2_dec_trigger.scala 14:93] @@ -79716,7 +79988,7 @@ circuit el2_swerv_wrapper : dec_i0_match_data[2] <= _T_110 @[el2_dec_trigger.scala 14:46] dec_i0_match_data[3] <= _T_147 @[el2_dec_trigger.scala 14:46] node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[el2_dec_trigger.scala 15:83] - node _T_149 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_149 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_150 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] node _T_152 = not(_T_151) @[el2_lib.scala 241:39] @@ -80007,7 +80279,7 @@ circuit el2_swerv_wrapper : node _T_405 = cat(_T_404, _T_389) @[el2_lib.scala 245:14] node _T_406 = and(_T_148, _T_405) @[el2_dec_trigger.scala 15:109] node _T_407 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[el2_dec_trigger.scala 15:83] - node _T_408 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_408 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_409 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_410 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] node _T_411 = not(_T_410) @[el2_lib.scala 241:39] @@ -80298,7 +80570,7 @@ circuit el2_swerv_wrapper : node _T_664 = cat(_T_663, _T_648) @[el2_lib.scala 245:14] node _T_665 = and(_T_407, _T_664) @[el2_dec_trigger.scala 15:109] node _T_666 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[el2_dec_trigger.scala 15:83] - node _T_667 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_667 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_668 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_669 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] node _T_670 = not(_T_669) @[el2_lib.scala 241:39] @@ -80589,7 +80861,7 @@ circuit el2_swerv_wrapper : node _T_923 = cat(_T_922, _T_907) @[el2_lib.scala 245:14] node _T_924 = and(_T_666, _T_923) @[el2_dec_trigger.scala 15:109] node _T_925 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[el2_dec_trigger.scala 15:83] - node _T_926 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_dec_trigger.scala 15:213] + node _T_926 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[el2_dec_trigger.scala 15:216] wire _T_927 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_928 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] node _T_929 = not(_T_928) @[el2_lib.scala 241:39] @@ -80887,7 +81159,7 @@ circuit el2_swerv_wrapper : module el2_dec : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>} wire dec_i0_inst_wb1 : UInt<32> dec_i0_inst_wb1 <= UInt<1>("h00") @@ -80923,14 +81195,14 @@ circuit el2_swerv_wrapper : instbuff.io.dbg_cmd_write <= io.dbg_cmd_write @[el2_dec.scala 298:45] instbuff.io.dbg_cmd_type <= io.dbg_cmd_type @[el2_dec.scala 299:45] instbuff.io.dbg_cmd_addr <= io.dbg_cmd_addr @[el2_dec.scala 300:45] - instbuff.io.i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec.scala 301:55] - instbuff.io.i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec.scala 301:55] + instbuff.io.i0_brp.ret <= io.i0_brp.ret @[el2_dec.scala 301:55] + instbuff.io.i0_brp.way <= io.i0_brp.way @[el2_dec.scala 301:55] + instbuff.io.i0_brp.prett <= io.i0_brp.prett @[el2_dec.scala 301:55] + instbuff.io.i0_brp.bank <= io.i0_brp.bank @[el2_dec.scala 301:55] + instbuff.io.i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec.scala 301:55] + instbuff.io.i0_brp.br_error <= io.i0_brp.br_error @[el2_dec.scala 301:55] + instbuff.io.i0_brp.hist <= io.i0_brp.hist @[el2_dec.scala 301:55] + instbuff.io.i0_brp.toffset <= io.i0_brp.toffset @[el2_dec.scala 301:55] instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 301:55] instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 302:35] instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 303:35] @@ -80950,28 +81222,28 @@ circuit el2_swerv_wrapper : dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 321:34] - dec_trigger.io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 321:34] - dec_trigger.io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 321:34] - dec_trigger.io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 321:34] - dec_trigger.io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 321:34] + dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[el2_dec.scala 321:34] dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 321:34] decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[el2_dec.scala 330:48] decode.io.dec_tlu_force_halt <= tlu.io.dec_tlu_force_halt @[el2_dec.scala 331:48] @@ -80997,14 +81269,14 @@ circuit el2_swerv_wrapper : decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 351:48] decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 352:48] decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 353:48] - decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 354:48] - decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.ret <= instbuff.io.dec_i0_brp.ret @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.way <= instbuff.io.dec_i0_brp.way @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.prett <= instbuff.io.dec_i0_brp.prett @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.bank <= instbuff.io.dec_i0_brp.bank @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.br_start_error <= instbuff.io.dec_i0_brp.br_start_error @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.br_error <= instbuff.io.dec_i0_brp.br_error @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.hist <= instbuff.io.dec_i0_brp.hist @[el2_dec.scala 354:48] + decode.io.dec_i0_brp.toffset <= instbuff.io.dec_i0_brp.toffset @[el2_dec.scala 354:48] decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 354:48] decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 355:48] decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 356:48] @@ -81257,28 +81529,28 @@ circuit el2_swerv_wrapper : io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[el2_dec.scala 546:29] io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[el2_dec.scala 546:29] io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[el2_dec.scala 546:29] - io.trigger_pkt_any[0].match_ <= tlu.io.trigger_pkt_any[0].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[el2_dec.scala 546:29] io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[el2_dec.scala 546:29] io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[el2_dec.scala 546:29] io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[el2_dec.scala 546:29] io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[el2_dec.scala 546:29] io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[el2_dec.scala 546:29] io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[el2_dec.scala 546:29] - io.trigger_pkt_any[1].match_ <= tlu.io.trigger_pkt_any[1].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[el2_dec.scala 546:29] io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[el2_dec.scala 546:29] io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[el2_dec.scala 546:29] io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[el2_dec.scala 546:29] io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[el2_dec.scala 546:29] io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[el2_dec.scala 546:29] io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[el2_dec.scala 546:29] - io.trigger_pkt_any[2].match_ <= tlu.io.trigger_pkt_any[2].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[el2_dec.scala 546:29] io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[el2_dec.scala 546:29] io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[el2_dec.scala 546:29] io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[el2_dec.scala 546:29] io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[el2_dec.scala 546:29] io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[el2_dec.scala 546:29] io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[el2_dec.scala 546:29] - io.trigger_pkt_any[3].match_ <= tlu.io.trigger_pkt_any[3].match_ @[el2_dec.scala 546:29] + io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[el2_dec.scala 546:29] io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[el2_dec.scala 546:29] io.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_dec.scala 547:29] io.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_dec.scala 547:29] @@ -81293,11 +81565,11 @@ circuit el2_swerv_wrapper : io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[el2_dec.scala 554:29] io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[el2_dec.scala 555:29] io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[el2_dec.scala 556:29] - io.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.dec_tlu_br0_r_pkt.bits.middle @[el2_dec.scala 557:42] - io.dec_tlu_br0_r_pkt.bits.way <= tlu.io.dec_tlu_br0_r_pkt.bits.way @[el2_dec.scala 557:42] - io.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_dec.scala 557:42] - io.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_dec.scala 557:42] - io.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.dec_tlu_br0_r_pkt.bits.hist @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.middle <= tlu.io.dec_tlu_br0_r_pkt.middle @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.way <= tlu.io.dec_tlu_br0_r_pkt.way @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.br_start_error @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.br_error <= tlu.io.dec_tlu_br0_r_pkt.br_error @[el2_dec.scala 557:42] + io.dec_tlu_br0_r_pkt.hist <= tlu.io.dec_tlu_br0_r_pkt.hist @[el2_dec.scala 557:42] io.dec_tlu_br0_r_pkt.valid <= tlu.io.dec_tlu_br0_r_pkt.valid @[el2_dec.scala 557:42] io.dec_tlu_i0_commit_cmt <= tlu.io.dec_tlu_i0_commit_cmt @[el2_dec.scala 558:34] io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 559:34] @@ -86498,12 +86770,12 @@ circuit el2_swerv_wrapper : module el2_lsu_lsc_ctl : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} + output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>} wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 96:29] wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 97:29] wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[el2_lsu_lsc_ctl.scala 98:29] - wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 99:29] + wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 99:29] node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 101:52] node lsu_rs1_d = mux(_T, io.exu_lsu_rs1_d, io.dma_mem_addr) @[el2_lsu_lsc_ctl.scala 101:28] node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 102:44] @@ -86677,14 +86949,14 @@ circuit el2_swerv_wrapper : node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[el2_lsu_lsc_ctl.scala 185:92] node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[el2_lsu_lsc_ctl.scala 185:44] lsu_fir_error_m <= _T_103 @[el2_lsu_lsc_ctl.scala 185:38] - wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 186:104] - _T_104.bits.addr <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] - _T_104.bits.mscause <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.bits.addr <= UInt<32>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.bits.mscause <= UInt<4>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.exc_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.inst_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.bits.single_ecc_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] _T_104.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] - reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75] + reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.addr <= lsu_error_pkt_m.bits.addr @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.mscause <= lsu_error_pkt_m.bits.mscause @[el2_lsu_lsc_ctl.scala 186:75] _T_105.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[el2_lsu_lsc_ctl.scala 186:75] @@ -92607,7 +92879,7 @@ circuit el2_swerv_wrapper : module el2_lsu_trigger : input clock : Clock input reset : AsyncReset - output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} + output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} node _T = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15] node _T_1 = mux(_T, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] @@ -92665,7 +92937,7 @@ circuit el2_swerv_wrapper : node _T_44 = and(_T_42, _T_43) @[el2_lsu_trigger.scala 19:58] node _T_45 = or(_T_41, _T_44) @[el2_lsu_trigger.scala 18:152] node _T_46 = and(_T_40, _T_45) @[el2_lsu_trigger.scala 18:94] - node _T_47 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_47 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_48 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_49 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] node _T_50 = not(_T_49) @[el2_lib.scala 241:39] @@ -92963,7 +93235,7 @@ circuit el2_swerv_wrapper : node _T_310 = and(_T_308, _T_309) @[el2_lsu_trigger.scala 19:58] node _T_311 = or(_T_307, _T_310) @[el2_lsu_trigger.scala 18:152] node _T_312 = and(_T_306, _T_311) @[el2_lsu_trigger.scala 18:94] - node _T_313 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_313 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_314 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_315 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] node _T_316 = not(_T_315) @[el2_lib.scala 241:39] @@ -93261,7 +93533,7 @@ circuit el2_swerv_wrapper : node _T_576 = and(_T_574, _T_575) @[el2_lsu_trigger.scala 19:58] node _T_577 = or(_T_573, _T_576) @[el2_lsu_trigger.scala 18:152] node _T_578 = and(_T_572, _T_577) @[el2_lsu_trigger.scala 18:94] - node _T_579 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_579 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_580 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_581 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] node _T_582 = not(_T_581) @[el2_lib.scala 241:39] @@ -93559,7 +93831,7 @@ circuit el2_swerv_wrapper : node _T_842 = and(_T_840, _T_841) @[el2_lsu_trigger.scala 19:58] node _T_843 = or(_T_839, _T_842) @[el2_lsu_trigger.scala 18:152] node _T_844 = and(_T_838, _T_843) @[el2_lsu_trigger.scala 18:94] - node _T_845 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + node _T_845 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[el2_lsu_trigger.scala 20:107] wire _T_846 : UInt<1>[32] @[el2_lib.scala 240:24] node _T_847 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] node _T_848 = not(_T_847) @[el2_lib.scala 241:39] @@ -101458,7 +101730,7 @@ circuit el2_swerv_wrapper : module el2_lsu : input clock : Clock input reset : AsyncReset - output io : {flip clk_override : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>, lsu_pmu_misaligned_m : UInt<1>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_trigger_match_m : UInt<4>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, lsu_axi_awvalid : UInt<1>, lsu_axi_awlock : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, lsu_axi_arlock : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rlast : UInt<1>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rid : UInt<3>, flip lsu_bus_clk_en : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_write : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, flip dma_mem_tag : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_wdata : UInt<64>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_ready : UInt<1>, flip scan_mode : UInt<1>, flip free_clk : Clock} + output io : {flip clk_override : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>, lsu_pmu_misaligned_m : UInt<1>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_trigger_match_m : UInt<4>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, lsu_axi_awvalid : UInt<1>, lsu_axi_awlock : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, lsu_axi_arlock : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rlast : UInt<1>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rid : UInt<3>, flip lsu_bus_clk_en : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_write : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, flip dma_mem_tag : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_wdata : UInt<64>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_ready : UInt<1>, flip scan_mode : UInt<1>, flip free_clk : Clock} wire dma_dccm_wdata : UInt<64> dma_dccm_wdata <= UInt<64>("h00") @@ -101830,28 +102102,28 @@ circuit el2_swerv_wrapper : trigger.io.trigger_pkt_any[0].execute <= io.trigger_pkt_any[0].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[0].load <= io.trigger_pkt_any[0].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[0].store <= io.trigger_pkt_any[0].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[0].match_ <= io.trigger_pkt_any[0].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[0].match_pkt <= io.trigger_pkt_any[0].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[0].select <= io.trigger_pkt_any[0].select @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].tdata2 <= io.trigger_pkt_any[1].tdata2 @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].m <= io.trigger_pkt_any[1].m @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].execute <= io.trigger_pkt_any[1].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].load <= io.trigger_pkt_any[1].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].store <= io.trigger_pkt_any[1].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[1].match_ <= io.trigger_pkt_any[1].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[1].match_pkt <= io.trigger_pkt_any[1].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[1].select <= io.trigger_pkt_any[1].select @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].tdata2 <= io.trigger_pkt_any[2].tdata2 @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].m <= io.trigger_pkt_any[2].m @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].execute <= io.trigger_pkt_any[2].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].load <= io.trigger_pkt_any[2].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].store <= io.trigger_pkt_any[2].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[2].match_ <= io.trigger_pkt_any[2].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[2].match_pkt <= io.trigger_pkt_any[2].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[2].select <= io.trigger_pkt_any[2].select @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].tdata2 <= io.trigger_pkt_any[3].tdata2 @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].m <= io.trigger_pkt_any[3].m @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].execute <= io.trigger_pkt_any[3].execute @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].load <= io.trigger_pkt_any[3].load @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].store <= io.trigger_pkt_any[3].store @[el2_lsu.scala 376:50] - trigger.io.trigger_pkt_any[3].match_ <= io.trigger_pkt_any[3].match_ @[el2_lsu.scala 376:50] + trigger.io.trigger_pkt_any[3].match_pkt <= io.trigger_pkt_any[3].match_pkt @[el2_lsu.scala 376:50] trigger.io.trigger_pkt_any[3].select <= io.trigger_pkt_any[3].select @[el2_lsu.scala 376:50] trigger.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[el2_lsu.scala 377:50] trigger.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[el2_lsu.scala 377:50] @@ -108931,11 +109203,11 @@ circuit el2_swerv_wrapper : ifu.io.exu_mp_fghr <= exu.io.exu_mp_fghr @[el2_swerv.scala 384:22] ifu.io.exu_mp_index <= exu.io.exu_mp_index @[el2_swerv.scala 385:23] ifu.io.exu_mp_btag <= exu.io.exu_mp_btag @[el2_swerv.scala 386:22] - ifu.io.dec_tlu_br0_r_pkt.bits.middle <= dec.io.dec_tlu_br0_r_pkt.bits.middle @[el2_swerv.scala 387:28] - ifu.io.dec_tlu_br0_r_pkt.bits.way <= dec.io.dec_tlu_br0_r_pkt.bits.way @[el2_swerv.scala 387:28] - ifu.io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_swerv.scala 387:28] - ifu.io.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_swerv.scala 387:28] - ifu.io.dec_tlu_br0_r_pkt.bits.hist <= dec.io.dec_tlu_br0_r_pkt.bits.hist @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.middle <= dec.io.dec_tlu_br0_r_pkt.middle @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.way <= dec.io.dec_tlu_br0_r_pkt.way @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.br_start_error <= dec.io.dec_tlu_br0_r_pkt.br_start_error @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.br_error <= dec.io.dec_tlu_br0_r_pkt.br_error @[el2_swerv.scala 387:28] + ifu.io.dec_tlu_br0_r_pkt.hist <= dec.io.dec_tlu_br0_r_pkt.hist @[el2_swerv.scala 387:28] ifu.io.dec_tlu_br0_r_pkt.valid <= dec.io.dec_tlu_br0_r_pkt.valid @[el2_swerv.scala 387:28] ifu.io.exu_i0_br_fghr_r <= exu.io.exu_i0_br_fghr_r @[el2_swerv.scala 388:27] ifu.io.exu_i0_br_index_r <= exu.io.exu_i0_br_index_r @[el2_swerv.scala 389:28] @@ -109001,14 +109273,14 @@ circuit el2_swerv_wrapper : dec.io.ifu_i0_icaf_f1 <= ifu.io.ifu_i0_icaf_f1 @[el2_swerv.scala 448:25] dec.io.ifu_i0_dbecc <= ifu.io.ifu_i0_dbecc @[el2_swerv.scala 449:23] dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[el2_swerv.scala 450:23] - dec.io.i0_brp.bits.ret <= ifu.io.i0_brp.bits.ret @[el2_swerv.scala 451:17] - dec.io.i0_brp.bits.way <= ifu.io.i0_brp.bits.way @[el2_swerv.scala 451:17] - dec.io.i0_brp.bits.prett <= ifu.io.i0_brp.bits.prett @[el2_swerv.scala 451:17] - dec.io.i0_brp.bits.bank <= ifu.io.i0_brp.bits.bank @[el2_swerv.scala 451:17] - dec.io.i0_brp.bits.br_start_error <= ifu.io.i0_brp.bits.br_start_error @[el2_swerv.scala 451:17] - dec.io.i0_brp.bits.br_error <= ifu.io.i0_brp.bits.br_error @[el2_swerv.scala 451:17] - dec.io.i0_brp.bits.hist <= ifu.io.i0_brp.bits.hist @[el2_swerv.scala 451:17] - dec.io.i0_brp.bits.toffset <= ifu.io.i0_brp.bits.toffset @[el2_swerv.scala 451:17] + dec.io.i0_brp.ret <= ifu.io.i0_brp.ret @[el2_swerv.scala 451:17] + dec.io.i0_brp.way <= ifu.io.i0_brp.way @[el2_swerv.scala 451:17] + dec.io.i0_brp.prett <= ifu.io.i0_brp.prett @[el2_swerv.scala 451:17] + dec.io.i0_brp.bank <= ifu.io.i0_brp.bank @[el2_swerv.scala 451:17] + dec.io.i0_brp.br_start_error <= ifu.io.i0_brp.br_start_error @[el2_swerv.scala 451:17] + dec.io.i0_brp.br_error <= ifu.io.i0_brp.br_error @[el2_swerv.scala 451:17] + dec.io.i0_brp.hist <= ifu.io.i0_brp.hist @[el2_swerv.scala 451:17] + dec.io.i0_brp.toffset <= ifu.io.i0_brp.toffset @[el2_swerv.scala 451:17] dec.io.i0_brp.valid <= ifu.io.i0_brp.valid @[el2_swerv.scala 451:17] dec.io.ifu_i0_bp_index <= ifu.io.ifu_i0_bp_index @[el2_swerv.scala 452:26] dec.io.ifu_i0_bp_fghr <= ifu.io.ifu_i0_bp_fghr @[el2_swerv.scala 453:25] @@ -109177,28 +109449,28 @@ circuit el2_swerv_wrapper : lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[el2_swerv.scala 551:26] - lsu.io.trigger_pkt_any[0].match_ <= dec.io.trigger_pkt_any[0].match_ @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[el2_swerv.scala 551:26] - lsu.io.trigger_pkt_any[1].match_ <= dec.io.trigger_pkt_any[1].match_ @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[el2_swerv.scala 551:26] - lsu.io.trigger_pkt_any[2].match_ <= dec.io.trigger_pkt_any[2].match_ @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[el2_swerv.scala 551:26] - lsu.io.trigger_pkt_any[3].match_ <= dec.io.trigger_pkt_any[3].match_ @[el2_swerv.scala 551:26] + lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[el2_swerv.scala 551:26] lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[el2_swerv.scala 551:26] lsu.io.dccm_rd_data_lo <= io.dccm_rd_data_lo @[el2_swerv.scala 552:26] lsu.io.dccm_rd_data_hi <= io.dccm_rd_data_hi @[el2_swerv.scala 553:26] diff --git a/el2_swerv_wrapper.v b/el2_swerv_wrapper.v index 462fb7f8..30ea564d 100644 --- a/el2_swerv_wrapper.v +++ b/el2_swerv_wrapper.v @@ -11814,11 +11814,11 @@ module el2_ifu_bp_ctl( input [30:0] io_ifc_fetch_addr_f, input io_ifc_fetch_req_f, input io_dec_tlu_br0_r_pkt_valid, - input [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - input io_dec_tlu_br0_r_pkt_bits_br_error, - input io_dec_tlu_br0_r_pkt_bits_br_start_error, - input io_dec_tlu_br0_r_pkt_bits_way, - input io_dec_tlu_br0_r_pkt_bits_middle, + input [1:0] io_dec_tlu_br0_r_pkt_hist, + input io_dec_tlu_br0_r_pkt_br_error, + input io_dec_tlu_br0_r_pkt_br_start_error, + input io_dec_tlu_br0_r_pkt_way, + input io_dec_tlu_br0_r_pkt_middle, input [7:0] io_exu_i0_br_fghr_r, input [7:0] io_exu_i0_br_index_r, input io_dec_tlu_flush_lower_wb, @@ -15115,7 +15115,7 @@ module el2_ifu_bp_ctl( wire leak_one_f = _T_40 | _T_41; // @[el2_ifu_bp_ctl.scala 135:76] wire _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 72:51] wire exu_mp_valid = io_exu_mp_pkt_bits_misp & _T; // @[el2_ifu_bp_ctl.scala 72:49] - wire dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_bits_br_start_error | io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu_bp_ctl.scala 94:50] + wire dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_br_start_error | io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu_bp_ctl.scala 94:50] wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 191:47] wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 191:85] wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_bp_ctl.scala 102:51] @@ -21046,12 +21046,12 @@ module el2_ifu_bp_ctl( wire exu_mp_valid_write = exu_mp_valid & io_exu_mp_pkt_bits_ataken; // @[el2_ifu_bp_ctl.scala 397:41] wire _T_539 = _T_175 & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 400:39] wire _T_541 = _T_539 & _T_530; // @[el2_ifu_bp_ctl.scala 400:60] - wire _T_542 = ~io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu_bp_ctl.scala 400:87] + wire _T_542 = ~io_dec_tlu_br0_r_pkt_way; // @[el2_ifu_bp_ctl.scala 400:87] wire _T_543 = _T_542 & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 400:104] wire btb_wr_en_way0 = _T_541 | _T_543; // @[el2_ifu_bp_ctl.scala 400:83] wire _T_544 = io_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 401:36] wire _T_546 = _T_544 & _T_530; // @[el2_ifu_bp_ctl.scala 401:57] - wire _T_547 = io_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98] + wire _T_547 = io_dec_tlu_br0_r_pkt_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98] wire btb_wr_en_way1 = _T_546 | _T_547; // @[el2_ifu_bp_ctl.scala 401:80] wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_i0_br_index_r : io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 404:24] wire middle_of_bank = io_exu_mp_pkt_bits_pc4 ^ io_exu_mp_pkt_bits_boffset; // @[el2_ifu_bp_ctl.scala 405:35] @@ -21066,8 +21066,8 @@ module el2_ifu_bp_ctl( wire [1:0] _T_558 = {middle_of_bank,_T_557}; // @[Cat.scala 29:58] wire [1:0] bht_wr_en0 = _T_556 & _T_558; // @[el2_ifu_bp_ctl.scala 408:84] wire [1:0] _T_560 = io_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_561 = ~io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu_bp_ctl.scala 409:75] - wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_bits_middle,_T_561}; // @[Cat.scala 29:58] + wire _T_561 = ~io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu_bp_ctl.scala 409:75] + wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_middle,_T_561}; // @[Cat.scala 29:58] wire [1:0] bht_wr_en2 = _T_560 & _T_562; // @[el2_ifu_bp_ctl.scala 409:46] wire [9:0] _T_563 = {io_exu_mp_index,2'h0}; // @[Cat.scala 29:58] wire [7:0] mp_hashed = _T_563[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 196:35] @@ -35094,7 +35094,7 @@ end // initial if (reset) begin dec_tlu_way_wb_f <= 1'h0; end else begin - dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_bits_way; + dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_way; end end always @(posedge rvclkhdr_266_io_l1clk or posedge reset) begin @@ -36901,7 +36901,7 @@ end // initial bht_bank_rd_data_out_1_0 <= 2'h0; end else if (bht_bank_sel_1_0_0) begin if (_T_8869) begin - bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_0 <= io_exu_mp_pkt_bits_hist; end @@ -36912,7 +36912,7 @@ end // initial bht_bank_rd_data_out_1_1 <= 2'h0; end else if (bht_bank_sel_1_0_1) begin if (_T_8878) begin - bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_1 <= io_exu_mp_pkt_bits_hist; end @@ -36923,7 +36923,7 @@ end // initial bht_bank_rd_data_out_1_2 <= 2'h0; end else if (bht_bank_sel_1_0_2) begin if (_T_8887) begin - bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_2 <= io_exu_mp_pkt_bits_hist; end @@ -36934,7 +36934,7 @@ end // initial bht_bank_rd_data_out_1_3 <= 2'h0; end else if (bht_bank_sel_1_0_3) begin if (_T_8896) begin - bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_3 <= io_exu_mp_pkt_bits_hist; end @@ -36945,7 +36945,7 @@ end // initial bht_bank_rd_data_out_1_4 <= 2'h0; end else if (bht_bank_sel_1_0_4) begin if (_T_8905) begin - bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_4 <= io_exu_mp_pkt_bits_hist; end @@ -36956,7 +36956,7 @@ end // initial bht_bank_rd_data_out_1_5 <= 2'h0; end else if (bht_bank_sel_1_0_5) begin if (_T_8914) begin - bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_5 <= io_exu_mp_pkt_bits_hist; end @@ -36967,7 +36967,7 @@ end // initial bht_bank_rd_data_out_1_6 <= 2'h0; end else if (bht_bank_sel_1_0_6) begin if (_T_8923) begin - bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_6 <= io_exu_mp_pkt_bits_hist; end @@ -36978,7 +36978,7 @@ end // initial bht_bank_rd_data_out_1_7 <= 2'h0; end else if (bht_bank_sel_1_0_7) begin if (_T_8932) begin - bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_7 <= io_exu_mp_pkt_bits_hist; end @@ -36989,7 +36989,7 @@ end // initial bht_bank_rd_data_out_1_8 <= 2'h0; end else if (bht_bank_sel_1_0_8) begin if (_T_8941) begin - bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_8 <= io_exu_mp_pkt_bits_hist; end @@ -37000,7 +37000,7 @@ end // initial bht_bank_rd_data_out_1_9 <= 2'h0; end else if (bht_bank_sel_1_0_9) begin if (_T_8950) begin - bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_9 <= io_exu_mp_pkt_bits_hist; end @@ -37011,7 +37011,7 @@ end // initial bht_bank_rd_data_out_1_10 <= 2'h0; end else if (bht_bank_sel_1_0_10) begin if (_T_8959) begin - bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_10 <= io_exu_mp_pkt_bits_hist; end @@ -37022,7 +37022,7 @@ end // initial bht_bank_rd_data_out_1_11 <= 2'h0; end else if (bht_bank_sel_1_0_11) begin if (_T_8968) begin - bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_11 <= io_exu_mp_pkt_bits_hist; end @@ -37033,7 +37033,7 @@ end // initial bht_bank_rd_data_out_1_12 <= 2'h0; end else if (bht_bank_sel_1_0_12) begin if (_T_8977) begin - bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_12 <= io_exu_mp_pkt_bits_hist; end @@ -37044,7 +37044,7 @@ end // initial bht_bank_rd_data_out_1_13 <= 2'h0; end else if (bht_bank_sel_1_0_13) begin if (_T_8986) begin - bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_13 <= io_exu_mp_pkt_bits_hist; end @@ -37055,7 +37055,7 @@ end // initial bht_bank_rd_data_out_1_14 <= 2'h0; end else if (bht_bank_sel_1_0_14) begin if (_T_8995) begin - bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_14 <= io_exu_mp_pkt_bits_hist; end @@ -37066,7 +37066,7 @@ end // initial bht_bank_rd_data_out_1_15 <= 2'h0; end else if (bht_bank_sel_1_0_15) begin if (_T_9004) begin - bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_15 <= io_exu_mp_pkt_bits_hist; end @@ -37077,7 +37077,7 @@ end // initial bht_bank_rd_data_out_1_16 <= 2'h0; end else if (bht_bank_sel_1_1_0) begin if (_T_9013) begin - bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_16 <= io_exu_mp_pkt_bits_hist; end @@ -37088,7 +37088,7 @@ end // initial bht_bank_rd_data_out_1_17 <= 2'h0; end else if (bht_bank_sel_1_1_1) begin if (_T_9022) begin - bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_17 <= io_exu_mp_pkt_bits_hist; end @@ -37099,7 +37099,7 @@ end // initial bht_bank_rd_data_out_1_18 <= 2'h0; end else if (bht_bank_sel_1_1_2) begin if (_T_9031) begin - bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_18 <= io_exu_mp_pkt_bits_hist; end @@ -37110,7 +37110,7 @@ end // initial bht_bank_rd_data_out_1_19 <= 2'h0; end else if (bht_bank_sel_1_1_3) begin if (_T_9040) begin - bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_19 <= io_exu_mp_pkt_bits_hist; end @@ -37121,7 +37121,7 @@ end // initial bht_bank_rd_data_out_1_20 <= 2'h0; end else if (bht_bank_sel_1_1_4) begin if (_T_9049) begin - bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_20 <= io_exu_mp_pkt_bits_hist; end @@ -37132,7 +37132,7 @@ end // initial bht_bank_rd_data_out_1_21 <= 2'h0; end else if (bht_bank_sel_1_1_5) begin if (_T_9058) begin - bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_21 <= io_exu_mp_pkt_bits_hist; end @@ -37143,7 +37143,7 @@ end // initial bht_bank_rd_data_out_1_22 <= 2'h0; end else if (bht_bank_sel_1_1_6) begin if (_T_9067) begin - bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_22 <= io_exu_mp_pkt_bits_hist; end @@ -37154,7 +37154,7 @@ end // initial bht_bank_rd_data_out_1_23 <= 2'h0; end else if (bht_bank_sel_1_1_7) begin if (_T_9076) begin - bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_23 <= io_exu_mp_pkt_bits_hist; end @@ -37165,7 +37165,7 @@ end // initial bht_bank_rd_data_out_1_24 <= 2'h0; end else if (bht_bank_sel_1_1_8) begin if (_T_9085) begin - bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_24 <= io_exu_mp_pkt_bits_hist; end @@ -37176,7 +37176,7 @@ end // initial bht_bank_rd_data_out_1_25 <= 2'h0; end else if (bht_bank_sel_1_1_9) begin if (_T_9094) begin - bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_25 <= io_exu_mp_pkt_bits_hist; end @@ -37187,7 +37187,7 @@ end // initial bht_bank_rd_data_out_1_26 <= 2'h0; end else if (bht_bank_sel_1_1_10) begin if (_T_9103) begin - bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_26 <= io_exu_mp_pkt_bits_hist; end @@ -37198,7 +37198,7 @@ end // initial bht_bank_rd_data_out_1_27 <= 2'h0; end else if (bht_bank_sel_1_1_11) begin if (_T_9112) begin - bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_27 <= io_exu_mp_pkt_bits_hist; end @@ -37209,7 +37209,7 @@ end // initial bht_bank_rd_data_out_1_28 <= 2'h0; end else if (bht_bank_sel_1_1_12) begin if (_T_9121) begin - bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_28 <= io_exu_mp_pkt_bits_hist; end @@ -37220,7 +37220,7 @@ end // initial bht_bank_rd_data_out_1_29 <= 2'h0; end else if (bht_bank_sel_1_1_13) begin if (_T_9130) begin - bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_29 <= io_exu_mp_pkt_bits_hist; end @@ -37231,7 +37231,7 @@ end // initial bht_bank_rd_data_out_1_30 <= 2'h0; end else if (bht_bank_sel_1_1_14) begin if (_T_9139) begin - bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_30 <= io_exu_mp_pkt_bits_hist; end @@ -37242,7 +37242,7 @@ end // initial bht_bank_rd_data_out_1_31 <= 2'h0; end else if (bht_bank_sel_1_1_15) begin if (_T_9148) begin - bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_31 <= io_exu_mp_pkt_bits_hist; end @@ -37253,7 +37253,7 @@ end // initial bht_bank_rd_data_out_1_32 <= 2'h0; end else if (bht_bank_sel_1_2_0) begin if (_T_9157) begin - bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_32 <= io_exu_mp_pkt_bits_hist; end @@ -37264,7 +37264,7 @@ end // initial bht_bank_rd_data_out_1_33 <= 2'h0; end else if (bht_bank_sel_1_2_1) begin if (_T_9166) begin - bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_33 <= io_exu_mp_pkt_bits_hist; end @@ -37275,7 +37275,7 @@ end // initial bht_bank_rd_data_out_1_34 <= 2'h0; end else if (bht_bank_sel_1_2_2) begin if (_T_9175) begin - bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_34 <= io_exu_mp_pkt_bits_hist; end @@ -37286,7 +37286,7 @@ end // initial bht_bank_rd_data_out_1_35 <= 2'h0; end else if (bht_bank_sel_1_2_3) begin if (_T_9184) begin - bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_35 <= io_exu_mp_pkt_bits_hist; end @@ -37297,7 +37297,7 @@ end // initial bht_bank_rd_data_out_1_36 <= 2'h0; end else if (bht_bank_sel_1_2_4) begin if (_T_9193) begin - bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_36 <= io_exu_mp_pkt_bits_hist; end @@ -37308,7 +37308,7 @@ end // initial bht_bank_rd_data_out_1_37 <= 2'h0; end else if (bht_bank_sel_1_2_5) begin if (_T_9202) begin - bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_37 <= io_exu_mp_pkt_bits_hist; end @@ -37319,7 +37319,7 @@ end // initial bht_bank_rd_data_out_1_38 <= 2'h0; end else if (bht_bank_sel_1_2_6) begin if (_T_9211) begin - bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_38 <= io_exu_mp_pkt_bits_hist; end @@ -37330,7 +37330,7 @@ end // initial bht_bank_rd_data_out_1_39 <= 2'h0; end else if (bht_bank_sel_1_2_7) begin if (_T_9220) begin - bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_39 <= io_exu_mp_pkt_bits_hist; end @@ -37341,7 +37341,7 @@ end // initial bht_bank_rd_data_out_1_40 <= 2'h0; end else if (bht_bank_sel_1_2_8) begin if (_T_9229) begin - bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_40 <= io_exu_mp_pkt_bits_hist; end @@ -37352,7 +37352,7 @@ end // initial bht_bank_rd_data_out_1_41 <= 2'h0; end else if (bht_bank_sel_1_2_9) begin if (_T_9238) begin - bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_41 <= io_exu_mp_pkt_bits_hist; end @@ -37363,7 +37363,7 @@ end // initial bht_bank_rd_data_out_1_42 <= 2'h0; end else if (bht_bank_sel_1_2_10) begin if (_T_9247) begin - bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_42 <= io_exu_mp_pkt_bits_hist; end @@ -37374,7 +37374,7 @@ end // initial bht_bank_rd_data_out_1_43 <= 2'h0; end else if (bht_bank_sel_1_2_11) begin if (_T_9256) begin - bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_43 <= io_exu_mp_pkt_bits_hist; end @@ -37385,7 +37385,7 @@ end // initial bht_bank_rd_data_out_1_44 <= 2'h0; end else if (bht_bank_sel_1_2_12) begin if (_T_9265) begin - bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_44 <= io_exu_mp_pkt_bits_hist; end @@ -37396,7 +37396,7 @@ end // initial bht_bank_rd_data_out_1_45 <= 2'h0; end else if (bht_bank_sel_1_2_13) begin if (_T_9274) begin - bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_45 <= io_exu_mp_pkt_bits_hist; end @@ -37407,7 +37407,7 @@ end // initial bht_bank_rd_data_out_1_46 <= 2'h0; end else if (bht_bank_sel_1_2_14) begin if (_T_9283) begin - bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_46 <= io_exu_mp_pkt_bits_hist; end @@ -37418,7 +37418,7 @@ end // initial bht_bank_rd_data_out_1_47 <= 2'h0; end else if (bht_bank_sel_1_2_15) begin if (_T_9292) begin - bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_47 <= io_exu_mp_pkt_bits_hist; end @@ -37429,7 +37429,7 @@ end // initial bht_bank_rd_data_out_1_48 <= 2'h0; end else if (bht_bank_sel_1_3_0) begin if (_T_9301) begin - bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_48 <= io_exu_mp_pkt_bits_hist; end @@ -37440,7 +37440,7 @@ end // initial bht_bank_rd_data_out_1_49 <= 2'h0; end else if (bht_bank_sel_1_3_1) begin if (_T_9310) begin - bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_49 <= io_exu_mp_pkt_bits_hist; end @@ -37451,7 +37451,7 @@ end // initial bht_bank_rd_data_out_1_50 <= 2'h0; end else if (bht_bank_sel_1_3_2) begin if (_T_9319) begin - bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_50 <= io_exu_mp_pkt_bits_hist; end @@ -37462,7 +37462,7 @@ end // initial bht_bank_rd_data_out_1_51 <= 2'h0; end else if (bht_bank_sel_1_3_3) begin if (_T_9328) begin - bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_51 <= io_exu_mp_pkt_bits_hist; end @@ -37473,7 +37473,7 @@ end // initial bht_bank_rd_data_out_1_52 <= 2'h0; end else if (bht_bank_sel_1_3_4) begin if (_T_9337) begin - bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_52 <= io_exu_mp_pkt_bits_hist; end @@ -37484,7 +37484,7 @@ end // initial bht_bank_rd_data_out_1_53 <= 2'h0; end else if (bht_bank_sel_1_3_5) begin if (_T_9346) begin - bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_53 <= io_exu_mp_pkt_bits_hist; end @@ -37495,7 +37495,7 @@ end // initial bht_bank_rd_data_out_1_54 <= 2'h0; end else if (bht_bank_sel_1_3_6) begin if (_T_9355) begin - bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_54 <= io_exu_mp_pkt_bits_hist; end @@ -37506,7 +37506,7 @@ end // initial bht_bank_rd_data_out_1_55 <= 2'h0; end else if (bht_bank_sel_1_3_7) begin if (_T_9364) begin - bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_55 <= io_exu_mp_pkt_bits_hist; end @@ -37517,7 +37517,7 @@ end // initial bht_bank_rd_data_out_1_56 <= 2'h0; end else if (bht_bank_sel_1_3_8) begin if (_T_9373) begin - bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_56 <= io_exu_mp_pkt_bits_hist; end @@ -37528,7 +37528,7 @@ end // initial bht_bank_rd_data_out_1_57 <= 2'h0; end else if (bht_bank_sel_1_3_9) begin if (_T_9382) begin - bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_57 <= io_exu_mp_pkt_bits_hist; end @@ -37539,7 +37539,7 @@ end // initial bht_bank_rd_data_out_1_58 <= 2'h0; end else if (bht_bank_sel_1_3_10) begin if (_T_9391) begin - bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_58 <= io_exu_mp_pkt_bits_hist; end @@ -37550,7 +37550,7 @@ end // initial bht_bank_rd_data_out_1_59 <= 2'h0; end else if (bht_bank_sel_1_3_11) begin if (_T_9400) begin - bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_59 <= io_exu_mp_pkt_bits_hist; end @@ -37561,7 +37561,7 @@ end // initial bht_bank_rd_data_out_1_60 <= 2'h0; end else if (bht_bank_sel_1_3_12) begin if (_T_9409) begin - bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_60 <= io_exu_mp_pkt_bits_hist; end @@ -37572,7 +37572,7 @@ end // initial bht_bank_rd_data_out_1_61 <= 2'h0; end else if (bht_bank_sel_1_3_13) begin if (_T_9418) begin - bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_61 <= io_exu_mp_pkt_bits_hist; end @@ -37583,7 +37583,7 @@ end // initial bht_bank_rd_data_out_1_62 <= 2'h0; end else if (bht_bank_sel_1_3_14) begin if (_T_9427) begin - bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_62 <= io_exu_mp_pkt_bits_hist; end @@ -37594,7 +37594,7 @@ end // initial bht_bank_rd_data_out_1_63 <= 2'h0; end else if (bht_bank_sel_1_3_15) begin if (_T_9436) begin - bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_63 <= io_exu_mp_pkt_bits_hist; end @@ -37605,7 +37605,7 @@ end // initial bht_bank_rd_data_out_1_64 <= 2'h0; end else if (bht_bank_sel_1_4_0) begin if (_T_9445) begin - bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_64 <= io_exu_mp_pkt_bits_hist; end @@ -37616,7 +37616,7 @@ end // initial bht_bank_rd_data_out_1_65 <= 2'h0; end else if (bht_bank_sel_1_4_1) begin if (_T_9454) begin - bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_65 <= io_exu_mp_pkt_bits_hist; end @@ -37627,7 +37627,7 @@ end // initial bht_bank_rd_data_out_1_66 <= 2'h0; end else if (bht_bank_sel_1_4_2) begin if (_T_9463) begin - bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_66 <= io_exu_mp_pkt_bits_hist; end @@ -37638,7 +37638,7 @@ end // initial bht_bank_rd_data_out_1_67 <= 2'h0; end else if (bht_bank_sel_1_4_3) begin if (_T_9472) begin - bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_67 <= io_exu_mp_pkt_bits_hist; end @@ -37649,7 +37649,7 @@ end // initial bht_bank_rd_data_out_1_68 <= 2'h0; end else if (bht_bank_sel_1_4_4) begin if (_T_9481) begin - bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_68 <= io_exu_mp_pkt_bits_hist; end @@ -37660,7 +37660,7 @@ end // initial bht_bank_rd_data_out_1_69 <= 2'h0; end else if (bht_bank_sel_1_4_5) begin if (_T_9490) begin - bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_69 <= io_exu_mp_pkt_bits_hist; end @@ -37671,7 +37671,7 @@ end // initial bht_bank_rd_data_out_1_70 <= 2'h0; end else if (bht_bank_sel_1_4_6) begin if (_T_9499) begin - bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_70 <= io_exu_mp_pkt_bits_hist; end @@ -37682,7 +37682,7 @@ end // initial bht_bank_rd_data_out_1_71 <= 2'h0; end else if (bht_bank_sel_1_4_7) begin if (_T_9508) begin - bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_71 <= io_exu_mp_pkt_bits_hist; end @@ -37693,7 +37693,7 @@ end // initial bht_bank_rd_data_out_1_72 <= 2'h0; end else if (bht_bank_sel_1_4_8) begin if (_T_9517) begin - bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_72 <= io_exu_mp_pkt_bits_hist; end @@ -37704,7 +37704,7 @@ end // initial bht_bank_rd_data_out_1_73 <= 2'h0; end else if (bht_bank_sel_1_4_9) begin if (_T_9526) begin - bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_73 <= io_exu_mp_pkt_bits_hist; end @@ -37715,7 +37715,7 @@ end // initial bht_bank_rd_data_out_1_74 <= 2'h0; end else if (bht_bank_sel_1_4_10) begin if (_T_9535) begin - bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_74 <= io_exu_mp_pkt_bits_hist; end @@ -37726,7 +37726,7 @@ end // initial bht_bank_rd_data_out_1_75 <= 2'h0; end else if (bht_bank_sel_1_4_11) begin if (_T_9544) begin - bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_75 <= io_exu_mp_pkt_bits_hist; end @@ -37737,7 +37737,7 @@ end // initial bht_bank_rd_data_out_1_76 <= 2'h0; end else if (bht_bank_sel_1_4_12) begin if (_T_9553) begin - bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_76 <= io_exu_mp_pkt_bits_hist; end @@ -37748,7 +37748,7 @@ end // initial bht_bank_rd_data_out_1_77 <= 2'h0; end else if (bht_bank_sel_1_4_13) begin if (_T_9562) begin - bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_77 <= io_exu_mp_pkt_bits_hist; end @@ -37759,7 +37759,7 @@ end // initial bht_bank_rd_data_out_1_78 <= 2'h0; end else if (bht_bank_sel_1_4_14) begin if (_T_9571) begin - bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_78 <= io_exu_mp_pkt_bits_hist; end @@ -37770,7 +37770,7 @@ end // initial bht_bank_rd_data_out_1_79 <= 2'h0; end else if (bht_bank_sel_1_4_15) begin if (_T_9580) begin - bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_79 <= io_exu_mp_pkt_bits_hist; end @@ -37781,7 +37781,7 @@ end // initial bht_bank_rd_data_out_1_80 <= 2'h0; end else if (bht_bank_sel_1_5_0) begin if (_T_9589) begin - bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_80 <= io_exu_mp_pkt_bits_hist; end @@ -37792,7 +37792,7 @@ end // initial bht_bank_rd_data_out_1_81 <= 2'h0; end else if (bht_bank_sel_1_5_1) begin if (_T_9598) begin - bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_81 <= io_exu_mp_pkt_bits_hist; end @@ -37803,7 +37803,7 @@ end // initial bht_bank_rd_data_out_1_82 <= 2'h0; end else if (bht_bank_sel_1_5_2) begin if (_T_9607) begin - bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_82 <= io_exu_mp_pkt_bits_hist; end @@ -37814,7 +37814,7 @@ end // initial bht_bank_rd_data_out_1_83 <= 2'h0; end else if (bht_bank_sel_1_5_3) begin if (_T_9616) begin - bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_83 <= io_exu_mp_pkt_bits_hist; end @@ -37825,7 +37825,7 @@ end // initial bht_bank_rd_data_out_1_84 <= 2'h0; end else if (bht_bank_sel_1_5_4) begin if (_T_9625) begin - bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_84 <= io_exu_mp_pkt_bits_hist; end @@ -37836,7 +37836,7 @@ end // initial bht_bank_rd_data_out_1_85 <= 2'h0; end else if (bht_bank_sel_1_5_5) begin if (_T_9634) begin - bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_85 <= io_exu_mp_pkt_bits_hist; end @@ -37847,7 +37847,7 @@ end // initial bht_bank_rd_data_out_1_86 <= 2'h0; end else if (bht_bank_sel_1_5_6) begin if (_T_9643) begin - bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_86 <= io_exu_mp_pkt_bits_hist; end @@ -37858,7 +37858,7 @@ end // initial bht_bank_rd_data_out_1_87 <= 2'h0; end else if (bht_bank_sel_1_5_7) begin if (_T_9652) begin - bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_87 <= io_exu_mp_pkt_bits_hist; end @@ -37869,7 +37869,7 @@ end // initial bht_bank_rd_data_out_1_88 <= 2'h0; end else if (bht_bank_sel_1_5_8) begin if (_T_9661) begin - bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_88 <= io_exu_mp_pkt_bits_hist; end @@ -37880,7 +37880,7 @@ end // initial bht_bank_rd_data_out_1_89 <= 2'h0; end else if (bht_bank_sel_1_5_9) begin if (_T_9670) begin - bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_89 <= io_exu_mp_pkt_bits_hist; end @@ -37891,7 +37891,7 @@ end // initial bht_bank_rd_data_out_1_90 <= 2'h0; end else if (bht_bank_sel_1_5_10) begin if (_T_9679) begin - bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_90 <= io_exu_mp_pkt_bits_hist; end @@ -37902,7 +37902,7 @@ end // initial bht_bank_rd_data_out_1_91 <= 2'h0; end else if (bht_bank_sel_1_5_11) begin if (_T_9688) begin - bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_91 <= io_exu_mp_pkt_bits_hist; end @@ -37913,7 +37913,7 @@ end // initial bht_bank_rd_data_out_1_92 <= 2'h0; end else if (bht_bank_sel_1_5_12) begin if (_T_9697) begin - bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_92 <= io_exu_mp_pkt_bits_hist; end @@ -37924,7 +37924,7 @@ end // initial bht_bank_rd_data_out_1_93 <= 2'h0; end else if (bht_bank_sel_1_5_13) begin if (_T_9706) begin - bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_93 <= io_exu_mp_pkt_bits_hist; end @@ -37935,7 +37935,7 @@ end // initial bht_bank_rd_data_out_1_94 <= 2'h0; end else if (bht_bank_sel_1_5_14) begin if (_T_9715) begin - bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_94 <= io_exu_mp_pkt_bits_hist; end @@ -37946,7 +37946,7 @@ end // initial bht_bank_rd_data_out_1_95 <= 2'h0; end else if (bht_bank_sel_1_5_15) begin if (_T_9724) begin - bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_95 <= io_exu_mp_pkt_bits_hist; end @@ -37957,7 +37957,7 @@ end // initial bht_bank_rd_data_out_1_96 <= 2'h0; end else if (bht_bank_sel_1_6_0) begin if (_T_9733) begin - bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_96 <= io_exu_mp_pkt_bits_hist; end @@ -37968,7 +37968,7 @@ end // initial bht_bank_rd_data_out_1_97 <= 2'h0; end else if (bht_bank_sel_1_6_1) begin if (_T_9742) begin - bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_97 <= io_exu_mp_pkt_bits_hist; end @@ -37979,7 +37979,7 @@ end // initial bht_bank_rd_data_out_1_98 <= 2'h0; end else if (bht_bank_sel_1_6_2) begin if (_T_9751) begin - bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_98 <= io_exu_mp_pkt_bits_hist; end @@ -37990,7 +37990,7 @@ end // initial bht_bank_rd_data_out_1_99 <= 2'h0; end else if (bht_bank_sel_1_6_3) begin if (_T_9760) begin - bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_99 <= io_exu_mp_pkt_bits_hist; end @@ -38001,7 +38001,7 @@ end // initial bht_bank_rd_data_out_1_100 <= 2'h0; end else if (bht_bank_sel_1_6_4) begin if (_T_9769) begin - bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_100 <= io_exu_mp_pkt_bits_hist; end @@ -38012,7 +38012,7 @@ end // initial bht_bank_rd_data_out_1_101 <= 2'h0; end else if (bht_bank_sel_1_6_5) begin if (_T_9778) begin - bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_101 <= io_exu_mp_pkt_bits_hist; end @@ -38023,7 +38023,7 @@ end // initial bht_bank_rd_data_out_1_102 <= 2'h0; end else if (bht_bank_sel_1_6_6) begin if (_T_9787) begin - bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_102 <= io_exu_mp_pkt_bits_hist; end @@ -38034,7 +38034,7 @@ end // initial bht_bank_rd_data_out_1_103 <= 2'h0; end else if (bht_bank_sel_1_6_7) begin if (_T_9796) begin - bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_103 <= io_exu_mp_pkt_bits_hist; end @@ -38045,7 +38045,7 @@ end // initial bht_bank_rd_data_out_1_104 <= 2'h0; end else if (bht_bank_sel_1_6_8) begin if (_T_9805) begin - bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_104 <= io_exu_mp_pkt_bits_hist; end @@ -38056,7 +38056,7 @@ end // initial bht_bank_rd_data_out_1_105 <= 2'h0; end else if (bht_bank_sel_1_6_9) begin if (_T_9814) begin - bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_105 <= io_exu_mp_pkt_bits_hist; end @@ -38067,7 +38067,7 @@ end // initial bht_bank_rd_data_out_1_106 <= 2'h0; end else if (bht_bank_sel_1_6_10) begin if (_T_9823) begin - bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_106 <= io_exu_mp_pkt_bits_hist; end @@ -38078,7 +38078,7 @@ end // initial bht_bank_rd_data_out_1_107 <= 2'h0; end else if (bht_bank_sel_1_6_11) begin if (_T_9832) begin - bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_107 <= io_exu_mp_pkt_bits_hist; end @@ -38089,7 +38089,7 @@ end // initial bht_bank_rd_data_out_1_108 <= 2'h0; end else if (bht_bank_sel_1_6_12) begin if (_T_9841) begin - bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_108 <= io_exu_mp_pkt_bits_hist; end @@ -38100,7 +38100,7 @@ end // initial bht_bank_rd_data_out_1_109 <= 2'h0; end else if (bht_bank_sel_1_6_13) begin if (_T_9850) begin - bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_109 <= io_exu_mp_pkt_bits_hist; end @@ -38111,7 +38111,7 @@ end // initial bht_bank_rd_data_out_1_110 <= 2'h0; end else if (bht_bank_sel_1_6_14) begin if (_T_9859) begin - bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_110 <= io_exu_mp_pkt_bits_hist; end @@ -38122,7 +38122,7 @@ end // initial bht_bank_rd_data_out_1_111 <= 2'h0; end else if (bht_bank_sel_1_6_15) begin if (_T_9868) begin - bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_111 <= io_exu_mp_pkt_bits_hist; end @@ -38133,7 +38133,7 @@ end // initial bht_bank_rd_data_out_1_112 <= 2'h0; end else if (bht_bank_sel_1_7_0) begin if (_T_9877) begin - bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_112 <= io_exu_mp_pkt_bits_hist; end @@ -38144,7 +38144,7 @@ end // initial bht_bank_rd_data_out_1_113 <= 2'h0; end else if (bht_bank_sel_1_7_1) begin if (_T_9886) begin - bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_113 <= io_exu_mp_pkt_bits_hist; end @@ -38155,7 +38155,7 @@ end // initial bht_bank_rd_data_out_1_114 <= 2'h0; end else if (bht_bank_sel_1_7_2) begin if (_T_9895) begin - bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_114 <= io_exu_mp_pkt_bits_hist; end @@ -38166,7 +38166,7 @@ end // initial bht_bank_rd_data_out_1_115 <= 2'h0; end else if (bht_bank_sel_1_7_3) begin if (_T_9904) begin - bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_115 <= io_exu_mp_pkt_bits_hist; end @@ -38177,7 +38177,7 @@ end // initial bht_bank_rd_data_out_1_116 <= 2'h0; end else if (bht_bank_sel_1_7_4) begin if (_T_9913) begin - bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_116 <= io_exu_mp_pkt_bits_hist; end @@ -38188,7 +38188,7 @@ end // initial bht_bank_rd_data_out_1_117 <= 2'h0; end else if (bht_bank_sel_1_7_5) begin if (_T_9922) begin - bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_117 <= io_exu_mp_pkt_bits_hist; end @@ -38199,7 +38199,7 @@ end // initial bht_bank_rd_data_out_1_118 <= 2'h0; end else if (bht_bank_sel_1_7_6) begin if (_T_9931) begin - bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_118 <= io_exu_mp_pkt_bits_hist; end @@ -38210,7 +38210,7 @@ end // initial bht_bank_rd_data_out_1_119 <= 2'h0; end else if (bht_bank_sel_1_7_7) begin if (_T_9940) begin - bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_119 <= io_exu_mp_pkt_bits_hist; end @@ -38221,7 +38221,7 @@ end // initial bht_bank_rd_data_out_1_120 <= 2'h0; end else if (bht_bank_sel_1_7_8) begin if (_T_9949) begin - bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_120 <= io_exu_mp_pkt_bits_hist; end @@ -38232,7 +38232,7 @@ end // initial bht_bank_rd_data_out_1_121 <= 2'h0; end else if (bht_bank_sel_1_7_9) begin if (_T_9958) begin - bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_121 <= io_exu_mp_pkt_bits_hist; end @@ -38243,7 +38243,7 @@ end // initial bht_bank_rd_data_out_1_122 <= 2'h0; end else if (bht_bank_sel_1_7_10) begin if (_T_9967) begin - bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_122 <= io_exu_mp_pkt_bits_hist; end @@ -38254,7 +38254,7 @@ end // initial bht_bank_rd_data_out_1_123 <= 2'h0; end else if (bht_bank_sel_1_7_11) begin if (_T_9976) begin - bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_123 <= io_exu_mp_pkt_bits_hist; end @@ -38265,7 +38265,7 @@ end // initial bht_bank_rd_data_out_1_124 <= 2'h0; end else if (bht_bank_sel_1_7_12) begin if (_T_9985) begin - bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_124 <= io_exu_mp_pkt_bits_hist; end @@ -38276,7 +38276,7 @@ end // initial bht_bank_rd_data_out_1_125 <= 2'h0; end else if (bht_bank_sel_1_7_13) begin if (_T_9994) begin - bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_125 <= io_exu_mp_pkt_bits_hist; end @@ -38287,7 +38287,7 @@ end // initial bht_bank_rd_data_out_1_126 <= 2'h0; end else if (bht_bank_sel_1_7_14) begin if (_T_10003) begin - bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_126 <= io_exu_mp_pkt_bits_hist; end @@ -38298,7 +38298,7 @@ end // initial bht_bank_rd_data_out_1_127 <= 2'h0; end else if (bht_bank_sel_1_7_15) begin if (_T_10012) begin - bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_127 <= io_exu_mp_pkt_bits_hist; end @@ -38309,7 +38309,7 @@ end // initial bht_bank_rd_data_out_1_128 <= 2'h0; end else if (bht_bank_sel_1_8_0) begin if (_T_10021) begin - bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_128 <= io_exu_mp_pkt_bits_hist; end @@ -38320,7 +38320,7 @@ end // initial bht_bank_rd_data_out_1_129 <= 2'h0; end else if (bht_bank_sel_1_8_1) begin if (_T_10030) begin - bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_129 <= io_exu_mp_pkt_bits_hist; end @@ -38331,7 +38331,7 @@ end // initial bht_bank_rd_data_out_1_130 <= 2'h0; end else if (bht_bank_sel_1_8_2) begin if (_T_10039) begin - bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_130 <= io_exu_mp_pkt_bits_hist; end @@ -38342,7 +38342,7 @@ end // initial bht_bank_rd_data_out_1_131 <= 2'h0; end else if (bht_bank_sel_1_8_3) begin if (_T_10048) begin - bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_131 <= io_exu_mp_pkt_bits_hist; end @@ -38353,7 +38353,7 @@ end // initial bht_bank_rd_data_out_1_132 <= 2'h0; end else if (bht_bank_sel_1_8_4) begin if (_T_10057) begin - bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_132 <= io_exu_mp_pkt_bits_hist; end @@ -38364,7 +38364,7 @@ end // initial bht_bank_rd_data_out_1_133 <= 2'h0; end else if (bht_bank_sel_1_8_5) begin if (_T_10066) begin - bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_133 <= io_exu_mp_pkt_bits_hist; end @@ -38375,7 +38375,7 @@ end // initial bht_bank_rd_data_out_1_134 <= 2'h0; end else if (bht_bank_sel_1_8_6) begin if (_T_10075) begin - bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_134 <= io_exu_mp_pkt_bits_hist; end @@ -38386,7 +38386,7 @@ end // initial bht_bank_rd_data_out_1_135 <= 2'h0; end else if (bht_bank_sel_1_8_7) begin if (_T_10084) begin - bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_135 <= io_exu_mp_pkt_bits_hist; end @@ -38397,7 +38397,7 @@ end // initial bht_bank_rd_data_out_1_136 <= 2'h0; end else if (bht_bank_sel_1_8_8) begin if (_T_10093) begin - bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_136 <= io_exu_mp_pkt_bits_hist; end @@ -38408,7 +38408,7 @@ end // initial bht_bank_rd_data_out_1_137 <= 2'h0; end else if (bht_bank_sel_1_8_9) begin if (_T_10102) begin - bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_137 <= io_exu_mp_pkt_bits_hist; end @@ -38419,7 +38419,7 @@ end // initial bht_bank_rd_data_out_1_138 <= 2'h0; end else if (bht_bank_sel_1_8_10) begin if (_T_10111) begin - bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_138 <= io_exu_mp_pkt_bits_hist; end @@ -38430,7 +38430,7 @@ end // initial bht_bank_rd_data_out_1_139 <= 2'h0; end else if (bht_bank_sel_1_8_11) begin if (_T_10120) begin - bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_139 <= io_exu_mp_pkt_bits_hist; end @@ -38441,7 +38441,7 @@ end // initial bht_bank_rd_data_out_1_140 <= 2'h0; end else if (bht_bank_sel_1_8_12) begin if (_T_10129) begin - bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_140 <= io_exu_mp_pkt_bits_hist; end @@ -38452,7 +38452,7 @@ end // initial bht_bank_rd_data_out_1_141 <= 2'h0; end else if (bht_bank_sel_1_8_13) begin if (_T_10138) begin - bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_141 <= io_exu_mp_pkt_bits_hist; end @@ -38463,7 +38463,7 @@ end // initial bht_bank_rd_data_out_1_142 <= 2'h0; end else if (bht_bank_sel_1_8_14) begin if (_T_10147) begin - bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_142 <= io_exu_mp_pkt_bits_hist; end @@ -38474,7 +38474,7 @@ end // initial bht_bank_rd_data_out_1_143 <= 2'h0; end else if (bht_bank_sel_1_8_15) begin if (_T_10156) begin - bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_143 <= io_exu_mp_pkt_bits_hist; end @@ -38485,7 +38485,7 @@ end // initial bht_bank_rd_data_out_1_144 <= 2'h0; end else if (bht_bank_sel_1_9_0) begin if (_T_10165) begin - bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_144 <= io_exu_mp_pkt_bits_hist; end @@ -38496,7 +38496,7 @@ end // initial bht_bank_rd_data_out_1_145 <= 2'h0; end else if (bht_bank_sel_1_9_1) begin if (_T_10174) begin - bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_145 <= io_exu_mp_pkt_bits_hist; end @@ -38507,7 +38507,7 @@ end // initial bht_bank_rd_data_out_1_146 <= 2'h0; end else if (bht_bank_sel_1_9_2) begin if (_T_10183) begin - bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_146 <= io_exu_mp_pkt_bits_hist; end @@ -38518,7 +38518,7 @@ end // initial bht_bank_rd_data_out_1_147 <= 2'h0; end else if (bht_bank_sel_1_9_3) begin if (_T_10192) begin - bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_147 <= io_exu_mp_pkt_bits_hist; end @@ -38529,7 +38529,7 @@ end // initial bht_bank_rd_data_out_1_148 <= 2'h0; end else if (bht_bank_sel_1_9_4) begin if (_T_10201) begin - bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_148 <= io_exu_mp_pkt_bits_hist; end @@ -38540,7 +38540,7 @@ end // initial bht_bank_rd_data_out_1_149 <= 2'h0; end else if (bht_bank_sel_1_9_5) begin if (_T_10210) begin - bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_149 <= io_exu_mp_pkt_bits_hist; end @@ -38551,7 +38551,7 @@ end // initial bht_bank_rd_data_out_1_150 <= 2'h0; end else if (bht_bank_sel_1_9_6) begin if (_T_10219) begin - bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_150 <= io_exu_mp_pkt_bits_hist; end @@ -38562,7 +38562,7 @@ end // initial bht_bank_rd_data_out_1_151 <= 2'h0; end else if (bht_bank_sel_1_9_7) begin if (_T_10228) begin - bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_151 <= io_exu_mp_pkt_bits_hist; end @@ -38573,7 +38573,7 @@ end // initial bht_bank_rd_data_out_1_152 <= 2'h0; end else if (bht_bank_sel_1_9_8) begin if (_T_10237) begin - bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_152 <= io_exu_mp_pkt_bits_hist; end @@ -38584,7 +38584,7 @@ end // initial bht_bank_rd_data_out_1_153 <= 2'h0; end else if (bht_bank_sel_1_9_9) begin if (_T_10246) begin - bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_153 <= io_exu_mp_pkt_bits_hist; end @@ -38595,7 +38595,7 @@ end // initial bht_bank_rd_data_out_1_154 <= 2'h0; end else if (bht_bank_sel_1_9_10) begin if (_T_10255) begin - bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_154 <= io_exu_mp_pkt_bits_hist; end @@ -38606,7 +38606,7 @@ end // initial bht_bank_rd_data_out_1_155 <= 2'h0; end else if (bht_bank_sel_1_9_11) begin if (_T_10264) begin - bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_155 <= io_exu_mp_pkt_bits_hist; end @@ -38617,7 +38617,7 @@ end // initial bht_bank_rd_data_out_1_156 <= 2'h0; end else if (bht_bank_sel_1_9_12) begin if (_T_10273) begin - bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_156 <= io_exu_mp_pkt_bits_hist; end @@ -38628,7 +38628,7 @@ end // initial bht_bank_rd_data_out_1_157 <= 2'h0; end else if (bht_bank_sel_1_9_13) begin if (_T_10282) begin - bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_157 <= io_exu_mp_pkt_bits_hist; end @@ -38639,7 +38639,7 @@ end // initial bht_bank_rd_data_out_1_158 <= 2'h0; end else if (bht_bank_sel_1_9_14) begin if (_T_10291) begin - bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_158 <= io_exu_mp_pkt_bits_hist; end @@ -38650,7 +38650,7 @@ end // initial bht_bank_rd_data_out_1_159 <= 2'h0; end else if (bht_bank_sel_1_9_15) begin if (_T_10300) begin - bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_159 <= io_exu_mp_pkt_bits_hist; end @@ -38661,7 +38661,7 @@ end // initial bht_bank_rd_data_out_1_160 <= 2'h0; end else if (bht_bank_sel_1_10_0) begin if (_T_10309) begin - bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_160 <= io_exu_mp_pkt_bits_hist; end @@ -38672,7 +38672,7 @@ end // initial bht_bank_rd_data_out_1_161 <= 2'h0; end else if (bht_bank_sel_1_10_1) begin if (_T_10318) begin - bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_161 <= io_exu_mp_pkt_bits_hist; end @@ -38683,7 +38683,7 @@ end // initial bht_bank_rd_data_out_1_162 <= 2'h0; end else if (bht_bank_sel_1_10_2) begin if (_T_10327) begin - bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_162 <= io_exu_mp_pkt_bits_hist; end @@ -38694,7 +38694,7 @@ end // initial bht_bank_rd_data_out_1_163 <= 2'h0; end else if (bht_bank_sel_1_10_3) begin if (_T_10336) begin - bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_163 <= io_exu_mp_pkt_bits_hist; end @@ -38705,7 +38705,7 @@ end // initial bht_bank_rd_data_out_1_164 <= 2'h0; end else if (bht_bank_sel_1_10_4) begin if (_T_10345) begin - bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_164 <= io_exu_mp_pkt_bits_hist; end @@ -38716,7 +38716,7 @@ end // initial bht_bank_rd_data_out_1_165 <= 2'h0; end else if (bht_bank_sel_1_10_5) begin if (_T_10354) begin - bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_165 <= io_exu_mp_pkt_bits_hist; end @@ -38727,7 +38727,7 @@ end // initial bht_bank_rd_data_out_1_166 <= 2'h0; end else if (bht_bank_sel_1_10_6) begin if (_T_10363) begin - bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_166 <= io_exu_mp_pkt_bits_hist; end @@ -38738,7 +38738,7 @@ end // initial bht_bank_rd_data_out_1_167 <= 2'h0; end else if (bht_bank_sel_1_10_7) begin if (_T_10372) begin - bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_167 <= io_exu_mp_pkt_bits_hist; end @@ -38749,7 +38749,7 @@ end // initial bht_bank_rd_data_out_1_168 <= 2'h0; end else if (bht_bank_sel_1_10_8) begin if (_T_10381) begin - bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_168 <= io_exu_mp_pkt_bits_hist; end @@ -38760,7 +38760,7 @@ end // initial bht_bank_rd_data_out_1_169 <= 2'h0; end else if (bht_bank_sel_1_10_9) begin if (_T_10390) begin - bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_169 <= io_exu_mp_pkt_bits_hist; end @@ -38771,7 +38771,7 @@ end // initial bht_bank_rd_data_out_1_170 <= 2'h0; end else if (bht_bank_sel_1_10_10) begin if (_T_10399) begin - bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_170 <= io_exu_mp_pkt_bits_hist; end @@ -38782,7 +38782,7 @@ end // initial bht_bank_rd_data_out_1_171 <= 2'h0; end else if (bht_bank_sel_1_10_11) begin if (_T_10408) begin - bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_171 <= io_exu_mp_pkt_bits_hist; end @@ -38793,7 +38793,7 @@ end // initial bht_bank_rd_data_out_1_172 <= 2'h0; end else if (bht_bank_sel_1_10_12) begin if (_T_10417) begin - bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_172 <= io_exu_mp_pkt_bits_hist; end @@ -38804,7 +38804,7 @@ end // initial bht_bank_rd_data_out_1_173 <= 2'h0; end else if (bht_bank_sel_1_10_13) begin if (_T_10426) begin - bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_173 <= io_exu_mp_pkt_bits_hist; end @@ -38815,7 +38815,7 @@ end // initial bht_bank_rd_data_out_1_174 <= 2'h0; end else if (bht_bank_sel_1_10_14) begin if (_T_10435) begin - bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_174 <= io_exu_mp_pkt_bits_hist; end @@ -38826,7 +38826,7 @@ end // initial bht_bank_rd_data_out_1_175 <= 2'h0; end else if (bht_bank_sel_1_10_15) begin if (_T_10444) begin - bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_175 <= io_exu_mp_pkt_bits_hist; end @@ -38837,7 +38837,7 @@ end // initial bht_bank_rd_data_out_1_176 <= 2'h0; end else if (bht_bank_sel_1_11_0) begin if (_T_10453) begin - bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_176 <= io_exu_mp_pkt_bits_hist; end @@ -38848,7 +38848,7 @@ end // initial bht_bank_rd_data_out_1_177 <= 2'h0; end else if (bht_bank_sel_1_11_1) begin if (_T_10462) begin - bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_177 <= io_exu_mp_pkt_bits_hist; end @@ -38859,7 +38859,7 @@ end // initial bht_bank_rd_data_out_1_178 <= 2'h0; end else if (bht_bank_sel_1_11_2) begin if (_T_10471) begin - bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_178 <= io_exu_mp_pkt_bits_hist; end @@ -38870,7 +38870,7 @@ end // initial bht_bank_rd_data_out_1_179 <= 2'h0; end else if (bht_bank_sel_1_11_3) begin if (_T_10480) begin - bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_179 <= io_exu_mp_pkt_bits_hist; end @@ -38881,7 +38881,7 @@ end // initial bht_bank_rd_data_out_1_180 <= 2'h0; end else if (bht_bank_sel_1_11_4) begin if (_T_10489) begin - bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_180 <= io_exu_mp_pkt_bits_hist; end @@ -38892,7 +38892,7 @@ end // initial bht_bank_rd_data_out_1_181 <= 2'h0; end else if (bht_bank_sel_1_11_5) begin if (_T_10498) begin - bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_181 <= io_exu_mp_pkt_bits_hist; end @@ -38903,7 +38903,7 @@ end // initial bht_bank_rd_data_out_1_182 <= 2'h0; end else if (bht_bank_sel_1_11_6) begin if (_T_10507) begin - bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_182 <= io_exu_mp_pkt_bits_hist; end @@ -38914,7 +38914,7 @@ end // initial bht_bank_rd_data_out_1_183 <= 2'h0; end else if (bht_bank_sel_1_11_7) begin if (_T_10516) begin - bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_183 <= io_exu_mp_pkt_bits_hist; end @@ -38925,7 +38925,7 @@ end // initial bht_bank_rd_data_out_1_184 <= 2'h0; end else if (bht_bank_sel_1_11_8) begin if (_T_10525) begin - bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_184 <= io_exu_mp_pkt_bits_hist; end @@ -38936,7 +38936,7 @@ end // initial bht_bank_rd_data_out_1_185 <= 2'h0; end else if (bht_bank_sel_1_11_9) begin if (_T_10534) begin - bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_185 <= io_exu_mp_pkt_bits_hist; end @@ -38947,7 +38947,7 @@ end // initial bht_bank_rd_data_out_1_186 <= 2'h0; end else if (bht_bank_sel_1_11_10) begin if (_T_10543) begin - bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_186 <= io_exu_mp_pkt_bits_hist; end @@ -38958,7 +38958,7 @@ end // initial bht_bank_rd_data_out_1_187 <= 2'h0; end else if (bht_bank_sel_1_11_11) begin if (_T_10552) begin - bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_187 <= io_exu_mp_pkt_bits_hist; end @@ -38969,7 +38969,7 @@ end // initial bht_bank_rd_data_out_1_188 <= 2'h0; end else if (bht_bank_sel_1_11_12) begin if (_T_10561) begin - bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_188 <= io_exu_mp_pkt_bits_hist; end @@ -38980,7 +38980,7 @@ end // initial bht_bank_rd_data_out_1_189 <= 2'h0; end else if (bht_bank_sel_1_11_13) begin if (_T_10570) begin - bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_189 <= io_exu_mp_pkt_bits_hist; end @@ -38991,7 +38991,7 @@ end // initial bht_bank_rd_data_out_1_190 <= 2'h0; end else if (bht_bank_sel_1_11_14) begin if (_T_10579) begin - bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_190 <= io_exu_mp_pkt_bits_hist; end @@ -39002,7 +39002,7 @@ end // initial bht_bank_rd_data_out_1_191 <= 2'h0; end else if (bht_bank_sel_1_11_15) begin if (_T_10588) begin - bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_191 <= io_exu_mp_pkt_bits_hist; end @@ -39013,7 +39013,7 @@ end // initial bht_bank_rd_data_out_1_192 <= 2'h0; end else if (bht_bank_sel_1_12_0) begin if (_T_10597) begin - bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_192 <= io_exu_mp_pkt_bits_hist; end @@ -39024,7 +39024,7 @@ end // initial bht_bank_rd_data_out_1_193 <= 2'h0; end else if (bht_bank_sel_1_12_1) begin if (_T_10606) begin - bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_193 <= io_exu_mp_pkt_bits_hist; end @@ -39035,7 +39035,7 @@ end // initial bht_bank_rd_data_out_1_194 <= 2'h0; end else if (bht_bank_sel_1_12_2) begin if (_T_10615) begin - bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_194 <= io_exu_mp_pkt_bits_hist; end @@ -39046,7 +39046,7 @@ end // initial bht_bank_rd_data_out_1_195 <= 2'h0; end else if (bht_bank_sel_1_12_3) begin if (_T_10624) begin - bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_195 <= io_exu_mp_pkt_bits_hist; end @@ -39057,7 +39057,7 @@ end // initial bht_bank_rd_data_out_1_196 <= 2'h0; end else if (bht_bank_sel_1_12_4) begin if (_T_10633) begin - bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_196 <= io_exu_mp_pkt_bits_hist; end @@ -39068,7 +39068,7 @@ end // initial bht_bank_rd_data_out_1_197 <= 2'h0; end else if (bht_bank_sel_1_12_5) begin if (_T_10642) begin - bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_197 <= io_exu_mp_pkt_bits_hist; end @@ -39079,7 +39079,7 @@ end // initial bht_bank_rd_data_out_1_198 <= 2'h0; end else if (bht_bank_sel_1_12_6) begin if (_T_10651) begin - bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_198 <= io_exu_mp_pkt_bits_hist; end @@ -39090,7 +39090,7 @@ end // initial bht_bank_rd_data_out_1_199 <= 2'h0; end else if (bht_bank_sel_1_12_7) begin if (_T_10660) begin - bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_199 <= io_exu_mp_pkt_bits_hist; end @@ -39101,7 +39101,7 @@ end // initial bht_bank_rd_data_out_1_200 <= 2'h0; end else if (bht_bank_sel_1_12_8) begin if (_T_10669) begin - bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_200 <= io_exu_mp_pkt_bits_hist; end @@ -39112,7 +39112,7 @@ end // initial bht_bank_rd_data_out_1_201 <= 2'h0; end else if (bht_bank_sel_1_12_9) begin if (_T_10678) begin - bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_201 <= io_exu_mp_pkt_bits_hist; end @@ -39123,7 +39123,7 @@ end // initial bht_bank_rd_data_out_1_202 <= 2'h0; end else if (bht_bank_sel_1_12_10) begin if (_T_10687) begin - bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_202 <= io_exu_mp_pkt_bits_hist; end @@ -39134,7 +39134,7 @@ end // initial bht_bank_rd_data_out_1_203 <= 2'h0; end else if (bht_bank_sel_1_12_11) begin if (_T_10696) begin - bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_203 <= io_exu_mp_pkt_bits_hist; end @@ -39145,7 +39145,7 @@ end // initial bht_bank_rd_data_out_1_204 <= 2'h0; end else if (bht_bank_sel_1_12_12) begin if (_T_10705) begin - bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_204 <= io_exu_mp_pkt_bits_hist; end @@ -39156,7 +39156,7 @@ end // initial bht_bank_rd_data_out_1_205 <= 2'h0; end else if (bht_bank_sel_1_12_13) begin if (_T_10714) begin - bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_205 <= io_exu_mp_pkt_bits_hist; end @@ -39167,7 +39167,7 @@ end // initial bht_bank_rd_data_out_1_206 <= 2'h0; end else if (bht_bank_sel_1_12_14) begin if (_T_10723) begin - bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_206 <= io_exu_mp_pkt_bits_hist; end @@ -39178,7 +39178,7 @@ end // initial bht_bank_rd_data_out_1_207 <= 2'h0; end else if (bht_bank_sel_1_12_15) begin if (_T_10732) begin - bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_207 <= io_exu_mp_pkt_bits_hist; end @@ -39189,7 +39189,7 @@ end // initial bht_bank_rd_data_out_1_208 <= 2'h0; end else if (bht_bank_sel_1_13_0) begin if (_T_10741) begin - bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_208 <= io_exu_mp_pkt_bits_hist; end @@ -39200,7 +39200,7 @@ end // initial bht_bank_rd_data_out_1_209 <= 2'h0; end else if (bht_bank_sel_1_13_1) begin if (_T_10750) begin - bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_209 <= io_exu_mp_pkt_bits_hist; end @@ -39211,7 +39211,7 @@ end // initial bht_bank_rd_data_out_1_210 <= 2'h0; end else if (bht_bank_sel_1_13_2) begin if (_T_10759) begin - bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_210 <= io_exu_mp_pkt_bits_hist; end @@ -39222,7 +39222,7 @@ end // initial bht_bank_rd_data_out_1_211 <= 2'h0; end else if (bht_bank_sel_1_13_3) begin if (_T_10768) begin - bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_211 <= io_exu_mp_pkt_bits_hist; end @@ -39233,7 +39233,7 @@ end // initial bht_bank_rd_data_out_1_212 <= 2'h0; end else if (bht_bank_sel_1_13_4) begin if (_T_10777) begin - bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_212 <= io_exu_mp_pkt_bits_hist; end @@ -39244,7 +39244,7 @@ end // initial bht_bank_rd_data_out_1_213 <= 2'h0; end else if (bht_bank_sel_1_13_5) begin if (_T_10786) begin - bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_213 <= io_exu_mp_pkt_bits_hist; end @@ -39255,7 +39255,7 @@ end // initial bht_bank_rd_data_out_1_214 <= 2'h0; end else if (bht_bank_sel_1_13_6) begin if (_T_10795) begin - bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_214 <= io_exu_mp_pkt_bits_hist; end @@ -39266,7 +39266,7 @@ end // initial bht_bank_rd_data_out_1_215 <= 2'h0; end else if (bht_bank_sel_1_13_7) begin if (_T_10804) begin - bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_215 <= io_exu_mp_pkt_bits_hist; end @@ -39277,7 +39277,7 @@ end // initial bht_bank_rd_data_out_1_216 <= 2'h0; end else if (bht_bank_sel_1_13_8) begin if (_T_10813) begin - bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_216 <= io_exu_mp_pkt_bits_hist; end @@ -39288,7 +39288,7 @@ end // initial bht_bank_rd_data_out_1_217 <= 2'h0; end else if (bht_bank_sel_1_13_9) begin if (_T_10822) begin - bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_217 <= io_exu_mp_pkt_bits_hist; end @@ -39299,7 +39299,7 @@ end // initial bht_bank_rd_data_out_1_218 <= 2'h0; end else if (bht_bank_sel_1_13_10) begin if (_T_10831) begin - bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_218 <= io_exu_mp_pkt_bits_hist; end @@ -39310,7 +39310,7 @@ end // initial bht_bank_rd_data_out_1_219 <= 2'h0; end else if (bht_bank_sel_1_13_11) begin if (_T_10840) begin - bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_219 <= io_exu_mp_pkt_bits_hist; end @@ -39321,7 +39321,7 @@ end // initial bht_bank_rd_data_out_1_220 <= 2'h0; end else if (bht_bank_sel_1_13_12) begin if (_T_10849) begin - bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_220 <= io_exu_mp_pkt_bits_hist; end @@ -39332,7 +39332,7 @@ end // initial bht_bank_rd_data_out_1_221 <= 2'h0; end else if (bht_bank_sel_1_13_13) begin if (_T_10858) begin - bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_221 <= io_exu_mp_pkt_bits_hist; end @@ -39343,7 +39343,7 @@ end // initial bht_bank_rd_data_out_1_222 <= 2'h0; end else if (bht_bank_sel_1_13_14) begin if (_T_10867) begin - bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_222 <= io_exu_mp_pkt_bits_hist; end @@ -39354,7 +39354,7 @@ end // initial bht_bank_rd_data_out_1_223 <= 2'h0; end else if (bht_bank_sel_1_13_15) begin if (_T_10876) begin - bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_223 <= io_exu_mp_pkt_bits_hist; end @@ -39365,7 +39365,7 @@ end // initial bht_bank_rd_data_out_1_224 <= 2'h0; end else if (bht_bank_sel_1_14_0) begin if (_T_10885) begin - bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_224 <= io_exu_mp_pkt_bits_hist; end @@ -39376,7 +39376,7 @@ end // initial bht_bank_rd_data_out_1_225 <= 2'h0; end else if (bht_bank_sel_1_14_1) begin if (_T_10894) begin - bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_225 <= io_exu_mp_pkt_bits_hist; end @@ -39387,7 +39387,7 @@ end // initial bht_bank_rd_data_out_1_226 <= 2'h0; end else if (bht_bank_sel_1_14_2) begin if (_T_10903) begin - bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_226 <= io_exu_mp_pkt_bits_hist; end @@ -39398,7 +39398,7 @@ end // initial bht_bank_rd_data_out_1_227 <= 2'h0; end else if (bht_bank_sel_1_14_3) begin if (_T_10912) begin - bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_227 <= io_exu_mp_pkt_bits_hist; end @@ -39409,7 +39409,7 @@ end // initial bht_bank_rd_data_out_1_228 <= 2'h0; end else if (bht_bank_sel_1_14_4) begin if (_T_10921) begin - bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_228 <= io_exu_mp_pkt_bits_hist; end @@ -39420,7 +39420,7 @@ end // initial bht_bank_rd_data_out_1_229 <= 2'h0; end else if (bht_bank_sel_1_14_5) begin if (_T_10930) begin - bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_229 <= io_exu_mp_pkt_bits_hist; end @@ -39431,7 +39431,7 @@ end // initial bht_bank_rd_data_out_1_230 <= 2'h0; end else if (bht_bank_sel_1_14_6) begin if (_T_10939) begin - bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_230 <= io_exu_mp_pkt_bits_hist; end @@ -39442,7 +39442,7 @@ end // initial bht_bank_rd_data_out_1_231 <= 2'h0; end else if (bht_bank_sel_1_14_7) begin if (_T_10948) begin - bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_231 <= io_exu_mp_pkt_bits_hist; end @@ -39453,7 +39453,7 @@ end // initial bht_bank_rd_data_out_1_232 <= 2'h0; end else if (bht_bank_sel_1_14_8) begin if (_T_10957) begin - bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_232 <= io_exu_mp_pkt_bits_hist; end @@ -39464,7 +39464,7 @@ end // initial bht_bank_rd_data_out_1_233 <= 2'h0; end else if (bht_bank_sel_1_14_9) begin if (_T_10966) begin - bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_233 <= io_exu_mp_pkt_bits_hist; end @@ -39475,7 +39475,7 @@ end // initial bht_bank_rd_data_out_1_234 <= 2'h0; end else if (bht_bank_sel_1_14_10) begin if (_T_10975) begin - bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_234 <= io_exu_mp_pkt_bits_hist; end @@ -39486,7 +39486,7 @@ end // initial bht_bank_rd_data_out_1_235 <= 2'h0; end else if (bht_bank_sel_1_14_11) begin if (_T_10984) begin - bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_235 <= io_exu_mp_pkt_bits_hist; end @@ -39497,7 +39497,7 @@ end // initial bht_bank_rd_data_out_1_236 <= 2'h0; end else if (bht_bank_sel_1_14_12) begin if (_T_10993) begin - bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_236 <= io_exu_mp_pkt_bits_hist; end @@ -39508,7 +39508,7 @@ end // initial bht_bank_rd_data_out_1_237 <= 2'h0; end else if (bht_bank_sel_1_14_13) begin if (_T_11002) begin - bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_237 <= io_exu_mp_pkt_bits_hist; end @@ -39519,7 +39519,7 @@ end // initial bht_bank_rd_data_out_1_238 <= 2'h0; end else if (bht_bank_sel_1_14_14) begin if (_T_11011) begin - bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_238 <= io_exu_mp_pkt_bits_hist; end @@ -39530,7 +39530,7 @@ end // initial bht_bank_rd_data_out_1_239 <= 2'h0; end else if (bht_bank_sel_1_14_15) begin if (_T_11020) begin - bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_239 <= io_exu_mp_pkt_bits_hist; end @@ -39541,7 +39541,7 @@ end // initial bht_bank_rd_data_out_1_240 <= 2'h0; end else if (bht_bank_sel_1_15_0) begin if (_T_11029) begin - bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_240 <= io_exu_mp_pkt_bits_hist; end @@ -39552,7 +39552,7 @@ end // initial bht_bank_rd_data_out_1_241 <= 2'h0; end else if (bht_bank_sel_1_15_1) begin if (_T_11038) begin - bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_241 <= io_exu_mp_pkt_bits_hist; end @@ -39563,7 +39563,7 @@ end // initial bht_bank_rd_data_out_1_242 <= 2'h0; end else if (bht_bank_sel_1_15_2) begin if (_T_11047) begin - bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_242 <= io_exu_mp_pkt_bits_hist; end @@ -39574,7 +39574,7 @@ end // initial bht_bank_rd_data_out_1_243 <= 2'h0; end else if (bht_bank_sel_1_15_3) begin if (_T_11056) begin - bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_243 <= io_exu_mp_pkt_bits_hist; end @@ -39585,7 +39585,7 @@ end // initial bht_bank_rd_data_out_1_244 <= 2'h0; end else if (bht_bank_sel_1_15_4) begin if (_T_11065) begin - bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_244 <= io_exu_mp_pkt_bits_hist; end @@ -39596,7 +39596,7 @@ end // initial bht_bank_rd_data_out_1_245 <= 2'h0; end else if (bht_bank_sel_1_15_5) begin if (_T_11074) begin - bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_245 <= io_exu_mp_pkt_bits_hist; end @@ -39607,7 +39607,7 @@ end // initial bht_bank_rd_data_out_1_246 <= 2'h0; end else if (bht_bank_sel_1_15_6) begin if (_T_11083) begin - bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_246 <= io_exu_mp_pkt_bits_hist; end @@ -39618,7 +39618,7 @@ end // initial bht_bank_rd_data_out_1_247 <= 2'h0; end else if (bht_bank_sel_1_15_7) begin if (_T_11092) begin - bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_247 <= io_exu_mp_pkt_bits_hist; end @@ -39629,7 +39629,7 @@ end // initial bht_bank_rd_data_out_1_248 <= 2'h0; end else if (bht_bank_sel_1_15_8) begin if (_T_11101) begin - bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_248 <= io_exu_mp_pkt_bits_hist; end @@ -39640,7 +39640,7 @@ end // initial bht_bank_rd_data_out_1_249 <= 2'h0; end else if (bht_bank_sel_1_15_9) begin if (_T_11110) begin - bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_249 <= io_exu_mp_pkt_bits_hist; end @@ -39651,7 +39651,7 @@ end // initial bht_bank_rd_data_out_1_250 <= 2'h0; end else if (bht_bank_sel_1_15_10) begin if (_T_11119) begin - bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_250 <= io_exu_mp_pkt_bits_hist; end @@ -39662,7 +39662,7 @@ end // initial bht_bank_rd_data_out_1_251 <= 2'h0; end else if (bht_bank_sel_1_15_11) begin if (_T_11128) begin - bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_251 <= io_exu_mp_pkt_bits_hist; end @@ -39673,7 +39673,7 @@ end // initial bht_bank_rd_data_out_1_252 <= 2'h0; end else if (bht_bank_sel_1_15_12) begin if (_T_11137) begin - bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_252 <= io_exu_mp_pkt_bits_hist; end @@ -39684,7 +39684,7 @@ end // initial bht_bank_rd_data_out_1_253 <= 2'h0; end else if (bht_bank_sel_1_15_13) begin if (_T_11146) begin - bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_253 <= io_exu_mp_pkt_bits_hist; end @@ -39695,7 +39695,7 @@ end // initial bht_bank_rd_data_out_1_254 <= 2'h0; end else if (bht_bank_sel_1_15_14) begin if (_T_11155) begin - bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_254 <= io_exu_mp_pkt_bits_hist; end @@ -39706,7 +39706,7 @@ end // initial bht_bank_rd_data_out_1_255 <= 2'h0; end else if (bht_bank_sel_1_15_15) begin if (_T_11164) begin - bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_1_255 <= io_exu_mp_pkt_bits_hist; end @@ -39717,7 +39717,7 @@ end // initial bht_bank_rd_data_out_0_0 <= 2'h0; end else if (bht_bank_sel_0_0_0) begin if (_T_6565) begin - bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_0 <= io_exu_mp_pkt_bits_hist; end @@ -39728,7 +39728,7 @@ end // initial bht_bank_rd_data_out_0_1 <= 2'h0; end else if (bht_bank_sel_0_0_1) begin if (_T_6574) begin - bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_1 <= io_exu_mp_pkt_bits_hist; end @@ -39739,7 +39739,7 @@ end // initial bht_bank_rd_data_out_0_2 <= 2'h0; end else if (bht_bank_sel_0_0_2) begin if (_T_6583) begin - bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_2 <= io_exu_mp_pkt_bits_hist; end @@ -39750,7 +39750,7 @@ end // initial bht_bank_rd_data_out_0_3 <= 2'h0; end else if (bht_bank_sel_0_0_3) begin if (_T_6592) begin - bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_3 <= io_exu_mp_pkt_bits_hist; end @@ -39761,7 +39761,7 @@ end // initial bht_bank_rd_data_out_0_4 <= 2'h0; end else if (bht_bank_sel_0_0_4) begin if (_T_6601) begin - bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_4 <= io_exu_mp_pkt_bits_hist; end @@ -39772,7 +39772,7 @@ end // initial bht_bank_rd_data_out_0_5 <= 2'h0; end else if (bht_bank_sel_0_0_5) begin if (_T_6610) begin - bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_5 <= io_exu_mp_pkt_bits_hist; end @@ -39783,7 +39783,7 @@ end // initial bht_bank_rd_data_out_0_6 <= 2'h0; end else if (bht_bank_sel_0_0_6) begin if (_T_6619) begin - bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_6 <= io_exu_mp_pkt_bits_hist; end @@ -39794,7 +39794,7 @@ end // initial bht_bank_rd_data_out_0_7 <= 2'h0; end else if (bht_bank_sel_0_0_7) begin if (_T_6628) begin - bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_7 <= io_exu_mp_pkt_bits_hist; end @@ -39805,7 +39805,7 @@ end // initial bht_bank_rd_data_out_0_8 <= 2'h0; end else if (bht_bank_sel_0_0_8) begin if (_T_6637) begin - bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_8 <= io_exu_mp_pkt_bits_hist; end @@ -39816,7 +39816,7 @@ end // initial bht_bank_rd_data_out_0_9 <= 2'h0; end else if (bht_bank_sel_0_0_9) begin if (_T_6646) begin - bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_9 <= io_exu_mp_pkt_bits_hist; end @@ -39827,7 +39827,7 @@ end // initial bht_bank_rd_data_out_0_10 <= 2'h0; end else if (bht_bank_sel_0_0_10) begin if (_T_6655) begin - bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_10 <= io_exu_mp_pkt_bits_hist; end @@ -39838,7 +39838,7 @@ end // initial bht_bank_rd_data_out_0_11 <= 2'h0; end else if (bht_bank_sel_0_0_11) begin if (_T_6664) begin - bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_11 <= io_exu_mp_pkt_bits_hist; end @@ -39849,7 +39849,7 @@ end // initial bht_bank_rd_data_out_0_12 <= 2'h0; end else if (bht_bank_sel_0_0_12) begin if (_T_6673) begin - bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_12 <= io_exu_mp_pkt_bits_hist; end @@ -39860,7 +39860,7 @@ end // initial bht_bank_rd_data_out_0_13 <= 2'h0; end else if (bht_bank_sel_0_0_13) begin if (_T_6682) begin - bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_13 <= io_exu_mp_pkt_bits_hist; end @@ -39871,7 +39871,7 @@ end // initial bht_bank_rd_data_out_0_14 <= 2'h0; end else if (bht_bank_sel_0_0_14) begin if (_T_6691) begin - bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_14 <= io_exu_mp_pkt_bits_hist; end @@ -39882,7 +39882,7 @@ end // initial bht_bank_rd_data_out_0_15 <= 2'h0; end else if (bht_bank_sel_0_0_15) begin if (_T_6700) begin - bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_15 <= io_exu_mp_pkt_bits_hist; end @@ -39893,7 +39893,7 @@ end // initial bht_bank_rd_data_out_0_16 <= 2'h0; end else if (bht_bank_sel_0_1_0) begin if (_T_6709) begin - bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_16 <= io_exu_mp_pkt_bits_hist; end @@ -39904,7 +39904,7 @@ end // initial bht_bank_rd_data_out_0_17 <= 2'h0; end else if (bht_bank_sel_0_1_1) begin if (_T_6718) begin - bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_17 <= io_exu_mp_pkt_bits_hist; end @@ -39915,7 +39915,7 @@ end // initial bht_bank_rd_data_out_0_18 <= 2'h0; end else if (bht_bank_sel_0_1_2) begin if (_T_6727) begin - bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_18 <= io_exu_mp_pkt_bits_hist; end @@ -39926,7 +39926,7 @@ end // initial bht_bank_rd_data_out_0_19 <= 2'h0; end else if (bht_bank_sel_0_1_3) begin if (_T_6736) begin - bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_19 <= io_exu_mp_pkt_bits_hist; end @@ -39937,7 +39937,7 @@ end // initial bht_bank_rd_data_out_0_20 <= 2'h0; end else if (bht_bank_sel_0_1_4) begin if (_T_6745) begin - bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_20 <= io_exu_mp_pkt_bits_hist; end @@ -39948,7 +39948,7 @@ end // initial bht_bank_rd_data_out_0_21 <= 2'h0; end else if (bht_bank_sel_0_1_5) begin if (_T_6754) begin - bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_21 <= io_exu_mp_pkt_bits_hist; end @@ -39959,7 +39959,7 @@ end // initial bht_bank_rd_data_out_0_22 <= 2'h0; end else if (bht_bank_sel_0_1_6) begin if (_T_6763) begin - bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_22 <= io_exu_mp_pkt_bits_hist; end @@ -39970,7 +39970,7 @@ end // initial bht_bank_rd_data_out_0_23 <= 2'h0; end else if (bht_bank_sel_0_1_7) begin if (_T_6772) begin - bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_23 <= io_exu_mp_pkt_bits_hist; end @@ -39981,7 +39981,7 @@ end // initial bht_bank_rd_data_out_0_24 <= 2'h0; end else if (bht_bank_sel_0_1_8) begin if (_T_6781) begin - bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_24 <= io_exu_mp_pkt_bits_hist; end @@ -39992,7 +39992,7 @@ end // initial bht_bank_rd_data_out_0_25 <= 2'h0; end else if (bht_bank_sel_0_1_9) begin if (_T_6790) begin - bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_25 <= io_exu_mp_pkt_bits_hist; end @@ -40003,7 +40003,7 @@ end // initial bht_bank_rd_data_out_0_26 <= 2'h0; end else if (bht_bank_sel_0_1_10) begin if (_T_6799) begin - bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_26 <= io_exu_mp_pkt_bits_hist; end @@ -40014,7 +40014,7 @@ end // initial bht_bank_rd_data_out_0_27 <= 2'h0; end else if (bht_bank_sel_0_1_11) begin if (_T_6808) begin - bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_27 <= io_exu_mp_pkt_bits_hist; end @@ -40025,7 +40025,7 @@ end // initial bht_bank_rd_data_out_0_28 <= 2'h0; end else if (bht_bank_sel_0_1_12) begin if (_T_6817) begin - bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_28 <= io_exu_mp_pkt_bits_hist; end @@ -40036,7 +40036,7 @@ end // initial bht_bank_rd_data_out_0_29 <= 2'h0; end else if (bht_bank_sel_0_1_13) begin if (_T_6826) begin - bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_29 <= io_exu_mp_pkt_bits_hist; end @@ -40047,7 +40047,7 @@ end // initial bht_bank_rd_data_out_0_30 <= 2'h0; end else if (bht_bank_sel_0_1_14) begin if (_T_6835) begin - bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_30 <= io_exu_mp_pkt_bits_hist; end @@ -40058,7 +40058,7 @@ end // initial bht_bank_rd_data_out_0_31 <= 2'h0; end else if (bht_bank_sel_0_1_15) begin if (_T_6844) begin - bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_31 <= io_exu_mp_pkt_bits_hist; end @@ -40069,7 +40069,7 @@ end // initial bht_bank_rd_data_out_0_32 <= 2'h0; end else if (bht_bank_sel_0_2_0) begin if (_T_6853) begin - bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_32 <= io_exu_mp_pkt_bits_hist; end @@ -40080,7 +40080,7 @@ end // initial bht_bank_rd_data_out_0_33 <= 2'h0; end else if (bht_bank_sel_0_2_1) begin if (_T_6862) begin - bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_33 <= io_exu_mp_pkt_bits_hist; end @@ -40091,7 +40091,7 @@ end // initial bht_bank_rd_data_out_0_34 <= 2'h0; end else if (bht_bank_sel_0_2_2) begin if (_T_6871) begin - bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_34 <= io_exu_mp_pkt_bits_hist; end @@ -40102,7 +40102,7 @@ end // initial bht_bank_rd_data_out_0_35 <= 2'h0; end else if (bht_bank_sel_0_2_3) begin if (_T_6880) begin - bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_35 <= io_exu_mp_pkt_bits_hist; end @@ -40113,7 +40113,7 @@ end // initial bht_bank_rd_data_out_0_36 <= 2'h0; end else if (bht_bank_sel_0_2_4) begin if (_T_6889) begin - bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_36 <= io_exu_mp_pkt_bits_hist; end @@ -40124,7 +40124,7 @@ end // initial bht_bank_rd_data_out_0_37 <= 2'h0; end else if (bht_bank_sel_0_2_5) begin if (_T_6898) begin - bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_37 <= io_exu_mp_pkt_bits_hist; end @@ -40135,7 +40135,7 @@ end // initial bht_bank_rd_data_out_0_38 <= 2'h0; end else if (bht_bank_sel_0_2_6) begin if (_T_6907) begin - bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_38 <= io_exu_mp_pkt_bits_hist; end @@ -40146,7 +40146,7 @@ end // initial bht_bank_rd_data_out_0_39 <= 2'h0; end else if (bht_bank_sel_0_2_7) begin if (_T_6916) begin - bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_39 <= io_exu_mp_pkt_bits_hist; end @@ -40157,7 +40157,7 @@ end // initial bht_bank_rd_data_out_0_40 <= 2'h0; end else if (bht_bank_sel_0_2_8) begin if (_T_6925) begin - bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_40 <= io_exu_mp_pkt_bits_hist; end @@ -40168,7 +40168,7 @@ end // initial bht_bank_rd_data_out_0_41 <= 2'h0; end else if (bht_bank_sel_0_2_9) begin if (_T_6934) begin - bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_41 <= io_exu_mp_pkt_bits_hist; end @@ -40179,7 +40179,7 @@ end // initial bht_bank_rd_data_out_0_42 <= 2'h0; end else if (bht_bank_sel_0_2_10) begin if (_T_6943) begin - bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_42 <= io_exu_mp_pkt_bits_hist; end @@ -40190,7 +40190,7 @@ end // initial bht_bank_rd_data_out_0_43 <= 2'h0; end else if (bht_bank_sel_0_2_11) begin if (_T_6952) begin - bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_43 <= io_exu_mp_pkt_bits_hist; end @@ -40201,7 +40201,7 @@ end // initial bht_bank_rd_data_out_0_44 <= 2'h0; end else if (bht_bank_sel_0_2_12) begin if (_T_6961) begin - bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_44 <= io_exu_mp_pkt_bits_hist; end @@ -40212,7 +40212,7 @@ end // initial bht_bank_rd_data_out_0_45 <= 2'h0; end else if (bht_bank_sel_0_2_13) begin if (_T_6970) begin - bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_45 <= io_exu_mp_pkt_bits_hist; end @@ -40223,7 +40223,7 @@ end // initial bht_bank_rd_data_out_0_46 <= 2'h0; end else if (bht_bank_sel_0_2_14) begin if (_T_6979) begin - bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_46 <= io_exu_mp_pkt_bits_hist; end @@ -40234,7 +40234,7 @@ end // initial bht_bank_rd_data_out_0_47 <= 2'h0; end else if (bht_bank_sel_0_2_15) begin if (_T_6988) begin - bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_47 <= io_exu_mp_pkt_bits_hist; end @@ -40245,7 +40245,7 @@ end // initial bht_bank_rd_data_out_0_48 <= 2'h0; end else if (bht_bank_sel_0_3_0) begin if (_T_6997) begin - bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_48 <= io_exu_mp_pkt_bits_hist; end @@ -40256,7 +40256,7 @@ end // initial bht_bank_rd_data_out_0_49 <= 2'h0; end else if (bht_bank_sel_0_3_1) begin if (_T_7006) begin - bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_49 <= io_exu_mp_pkt_bits_hist; end @@ -40267,7 +40267,7 @@ end // initial bht_bank_rd_data_out_0_50 <= 2'h0; end else if (bht_bank_sel_0_3_2) begin if (_T_7015) begin - bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_50 <= io_exu_mp_pkt_bits_hist; end @@ -40278,7 +40278,7 @@ end // initial bht_bank_rd_data_out_0_51 <= 2'h0; end else if (bht_bank_sel_0_3_3) begin if (_T_7024) begin - bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_51 <= io_exu_mp_pkt_bits_hist; end @@ -40289,7 +40289,7 @@ end // initial bht_bank_rd_data_out_0_52 <= 2'h0; end else if (bht_bank_sel_0_3_4) begin if (_T_7033) begin - bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_52 <= io_exu_mp_pkt_bits_hist; end @@ -40300,7 +40300,7 @@ end // initial bht_bank_rd_data_out_0_53 <= 2'h0; end else if (bht_bank_sel_0_3_5) begin if (_T_7042) begin - bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_53 <= io_exu_mp_pkt_bits_hist; end @@ -40311,7 +40311,7 @@ end // initial bht_bank_rd_data_out_0_54 <= 2'h0; end else if (bht_bank_sel_0_3_6) begin if (_T_7051) begin - bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_54 <= io_exu_mp_pkt_bits_hist; end @@ -40322,7 +40322,7 @@ end // initial bht_bank_rd_data_out_0_55 <= 2'h0; end else if (bht_bank_sel_0_3_7) begin if (_T_7060) begin - bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_55 <= io_exu_mp_pkt_bits_hist; end @@ -40333,7 +40333,7 @@ end // initial bht_bank_rd_data_out_0_56 <= 2'h0; end else if (bht_bank_sel_0_3_8) begin if (_T_7069) begin - bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_56 <= io_exu_mp_pkt_bits_hist; end @@ -40344,7 +40344,7 @@ end // initial bht_bank_rd_data_out_0_57 <= 2'h0; end else if (bht_bank_sel_0_3_9) begin if (_T_7078) begin - bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_57 <= io_exu_mp_pkt_bits_hist; end @@ -40355,7 +40355,7 @@ end // initial bht_bank_rd_data_out_0_58 <= 2'h0; end else if (bht_bank_sel_0_3_10) begin if (_T_7087) begin - bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_58 <= io_exu_mp_pkt_bits_hist; end @@ -40366,7 +40366,7 @@ end // initial bht_bank_rd_data_out_0_59 <= 2'h0; end else if (bht_bank_sel_0_3_11) begin if (_T_7096) begin - bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_59 <= io_exu_mp_pkt_bits_hist; end @@ -40377,7 +40377,7 @@ end // initial bht_bank_rd_data_out_0_60 <= 2'h0; end else if (bht_bank_sel_0_3_12) begin if (_T_7105) begin - bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_60 <= io_exu_mp_pkt_bits_hist; end @@ -40388,7 +40388,7 @@ end // initial bht_bank_rd_data_out_0_61 <= 2'h0; end else if (bht_bank_sel_0_3_13) begin if (_T_7114) begin - bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_61 <= io_exu_mp_pkt_bits_hist; end @@ -40399,7 +40399,7 @@ end // initial bht_bank_rd_data_out_0_62 <= 2'h0; end else if (bht_bank_sel_0_3_14) begin if (_T_7123) begin - bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_62 <= io_exu_mp_pkt_bits_hist; end @@ -40410,7 +40410,7 @@ end // initial bht_bank_rd_data_out_0_63 <= 2'h0; end else if (bht_bank_sel_0_3_15) begin if (_T_7132) begin - bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_63 <= io_exu_mp_pkt_bits_hist; end @@ -40421,7 +40421,7 @@ end // initial bht_bank_rd_data_out_0_64 <= 2'h0; end else if (bht_bank_sel_0_4_0) begin if (_T_7141) begin - bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_64 <= io_exu_mp_pkt_bits_hist; end @@ -40432,7 +40432,7 @@ end // initial bht_bank_rd_data_out_0_65 <= 2'h0; end else if (bht_bank_sel_0_4_1) begin if (_T_7150) begin - bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_65 <= io_exu_mp_pkt_bits_hist; end @@ -40443,7 +40443,7 @@ end // initial bht_bank_rd_data_out_0_66 <= 2'h0; end else if (bht_bank_sel_0_4_2) begin if (_T_7159) begin - bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_66 <= io_exu_mp_pkt_bits_hist; end @@ -40454,7 +40454,7 @@ end // initial bht_bank_rd_data_out_0_67 <= 2'h0; end else if (bht_bank_sel_0_4_3) begin if (_T_7168) begin - bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_67 <= io_exu_mp_pkt_bits_hist; end @@ -40465,7 +40465,7 @@ end // initial bht_bank_rd_data_out_0_68 <= 2'h0; end else if (bht_bank_sel_0_4_4) begin if (_T_7177) begin - bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_68 <= io_exu_mp_pkt_bits_hist; end @@ -40476,7 +40476,7 @@ end // initial bht_bank_rd_data_out_0_69 <= 2'h0; end else if (bht_bank_sel_0_4_5) begin if (_T_7186) begin - bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_69 <= io_exu_mp_pkt_bits_hist; end @@ -40487,7 +40487,7 @@ end // initial bht_bank_rd_data_out_0_70 <= 2'h0; end else if (bht_bank_sel_0_4_6) begin if (_T_7195) begin - bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_70 <= io_exu_mp_pkt_bits_hist; end @@ -40498,7 +40498,7 @@ end // initial bht_bank_rd_data_out_0_71 <= 2'h0; end else if (bht_bank_sel_0_4_7) begin if (_T_7204) begin - bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_71 <= io_exu_mp_pkt_bits_hist; end @@ -40509,7 +40509,7 @@ end // initial bht_bank_rd_data_out_0_72 <= 2'h0; end else if (bht_bank_sel_0_4_8) begin if (_T_7213) begin - bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_72 <= io_exu_mp_pkt_bits_hist; end @@ -40520,7 +40520,7 @@ end // initial bht_bank_rd_data_out_0_73 <= 2'h0; end else if (bht_bank_sel_0_4_9) begin if (_T_7222) begin - bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_73 <= io_exu_mp_pkt_bits_hist; end @@ -40531,7 +40531,7 @@ end // initial bht_bank_rd_data_out_0_74 <= 2'h0; end else if (bht_bank_sel_0_4_10) begin if (_T_7231) begin - bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_74 <= io_exu_mp_pkt_bits_hist; end @@ -40542,7 +40542,7 @@ end // initial bht_bank_rd_data_out_0_75 <= 2'h0; end else if (bht_bank_sel_0_4_11) begin if (_T_7240) begin - bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_75 <= io_exu_mp_pkt_bits_hist; end @@ -40553,7 +40553,7 @@ end // initial bht_bank_rd_data_out_0_76 <= 2'h0; end else if (bht_bank_sel_0_4_12) begin if (_T_7249) begin - bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_76 <= io_exu_mp_pkt_bits_hist; end @@ -40564,7 +40564,7 @@ end // initial bht_bank_rd_data_out_0_77 <= 2'h0; end else if (bht_bank_sel_0_4_13) begin if (_T_7258) begin - bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_77 <= io_exu_mp_pkt_bits_hist; end @@ -40575,7 +40575,7 @@ end // initial bht_bank_rd_data_out_0_78 <= 2'h0; end else if (bht_bank_sel_0_4_14) begin if (_T_7267) begin - bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_78 <= io_exu_mp_pkt_bits_hist; end @@ -40586,7 +40586,7 @@ end // initial bht_bank_rd_data_out_0_79 <= 2'h0; end else if (bht_bank_sel_0_4_15) begin if (_T_7276) begin - bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_79 <= io_exu_mp_pkt_bits_hist; end @@ -40597,7 +40597,7 @@ end // initial bht_bank_rd_data_out_0_80 <= 2'h0; end else if (bht_bank_sel_0_5_0) begin if (_T_7285) begin - bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_80 <= io_exu_mp_pkt_bits_hist; end @@ -40608,7 +40608,7 @@ end // initial bht_bank_rd_data_out_0_81 <= 2'h0; end else if (bht_bank_sel_0_5_1) begin if (_T_7294) begin - bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_81 <= io_exu_mp_pkt_bits_hist; end @@ -40619,7 +40619,7 @@ end // initial bht_bank_rd_data_out_0_82 <= 2'h0; end else if (bht_bank_sel_0_5_2) begin if (_T_7303) begin - bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_82 <= io_exu_mp_pkt_bits_hist; end @@ -40630,7 +40630,7 @@ end // initial bht_bank_rd_data_out_0_83 <= 2'h0; end else if (bht_bank_sel_0_5_3) begin if (_T_7312) begin - bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_83 <= io_exu_mp_pkt_bits_hist; end @@ -40641,7 +40641,7 @@ end // initial bht_bank_rd_data_out_0_84 <= 2'h0; end else if (bht_bank_sel_0_5_4) begin if (_T_7321) begin - bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_84 <= io_exu_mp_pkt_bits_hist; end @@ -40652,7 +40652,7 @@ end // initial bht_bank_rd_data_out_0_85 <= 2'h0; end else if (bht_bank_sel_0_5_5) begin if (_T_7330) begin - bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_85 <= io_exu_mp_pkt_bits_hist; end @@ -40663,7 +40663,7 @@ end // initial bht_bank_rd_data_out_0_86 <= 2'h0; end else if (bht_bank_sel_0_5_6) begin if (_T_7339) begin - bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_86 <= io_exu_mp_pkt_bits_hist; end @@ -40674,7 +40674,7 @@ end // initial bht_bank_rd_data_out_0_87 <= 2'h0; end else if (bht_bank_sel_0_5_7) begin if (_T_7348) begin - bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_87 <= io_exu_mp_pkt_bits_hist; end @@ -40685,7 +40685,7 @@ end // initial bht_bank_rd_data_out_0_88 <= 2'h0; end else if (bht_bank_sel_0_5_8) begin if (_T_7357) begin - bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_88 <= io_exu_mp_pkt_bits_hist; end @@ -40696,7 +40696,7 @@ end // initial bht_bank_rd_data_out_0_89 <= 2'h0; end else if (bht_bank_sel_0_5_9) begin if (_T_7366) begin - bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_89 <= io_exu_mp_pkt_bits_hist; end @@ -40707,7 +40707,7 @@ end // initial bht_bank_rd_data_out_0_90 <= 2'h0; end else if (bht_bank_sel_0_5_10) begin if (_T_7375) begin - bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_90 <= io_exu_mp_pkt_bits_hist; end @@ -40718,7 +40718,7 @@ end // initial bht_bank_rd_data_out_0_91 <= 2'h0; end else if (bht_bank_sel_0_5_11) begin if (_T_7384) begin - bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_91 <= io_exu_mp_pkt_bits_hist; end @@ -40729,7 +40729,7 @@ end // initial bht_bank_rd_data_out_0_92 <= 2'h0; end else if (bht_bank_sel_0_5_12) begin if (_T_7393) begin - bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_92 <= io_exu_mp_pkt_bits_hist; end @@ -40740,7 +40740,7 @@ end // initial bht_bank_rd_data_out_0_93 <= 2'h0; end else if (bht_bank_sel_0_5_13) begin if (_T_7402) begin - bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_93 <= io_exu_mp_pkt_bits_hist; end @@ -40751,7 +40751,7 @@ end // initial bht_bank_rd_data_out_0_94 <= 2'h0; end else if (bht_bank_sel_0_5_14) begin if (_T_7411) begin - bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_94 <= io_exu_mp_pkt_bits_hist; end @@ -40762,7 +40762,7 @@ end // initial bht_bank_rd_data_out_0_95 <= 2'h0; end else if (bht_bank_sel_0_5_15) begin if (_T_7420) begin - bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_95 <= io_exu_mp_pkt_bits_hist; end @@ -40773,7 +40773,7 @@ end // initial bht_bank_rd_data_out_0_96 <= 2'h0; end else if (bht_bank_sel_0_6_0) begin if (_T_7429) begin - bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_96 <= io_exu_mp_pkt_bits_hist; end @@ -40784,7 +40784,7 @@ end // initial bht_bank_rd_data_out_0_97 <= 2'h0; end else if (bht_bank_sel_0_6_1) begin if (_T_7438) begin - bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_97 <= io_exu_mp_pkt_bits_hist; end @@ -40795,7 +40795,7 @@ end // initial bht_bank_rd_data_out_0_98 <= 2'h0; end else if (bht_bank_sel_0_6_2) begin if (_T_7447) begin - bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_98 <= io_exu_mp_pkt_bits_hist; end @@ -40806,7 +40806,7 @@ end // initial bht_bank_rd_data_out_0_99 <= 2'h0; end else if (bht_bank_sel_0_6_3) begin if (_T_7456) begin - bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_99 <= io_exu_mp_pkt_bits_hist; end @@ -40817,7 +40817,7 @@ end // initial bht_bank_rd_data_out_0_100 <= 2'h0; end else if (bht_bank_sel_0_6_4) begin if (_T_7465) begin - bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_100 <= io_exu_mp_pkt_bits_hist; end @@ -40828,7 +40828,7 @@ end // initial bht_bank_rd_data_out_0_101 <= 2'h0; end else if (bht_bank_sel_0_6_5) begin if (_T_7474) begin - bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_101 <= io_exu_mp_pkt_bits_hist; end @@ -40839,7 +40839,7 @@ end // initial bht_bank_rd_data_out_0_102 <= 2'h0; end else if (bht_bank_sel_0_6_6) begin if (_T_7483) begin - bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_102 <= io_exu_mp_pkt_bits_hist; end @@ -40850,7 +40850,7 @@ end // initial bht_bank_rd_data_out_0_103 <= 2'h0; end else if (bht_bank_sel_0_6_7) begin if (_T_7492) begin - bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_103 <= io_exu_mp_pkt_bits_hist; end @@ -40861,7 +40861,7 @@ end // initial bht_bank_rd_data_out_0_104 <= 2'h0; end else if (bht_bank_sel_0_6_8) begin if (_T_7501) begin - bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_104 <= io_exu_mp_pkt_bits_hist; end @@ -40872,7 +40872,7 @@ end // initial bht_bank_rd_data_out_0_105 <= 2'h0; end else if (bht_bank_sel_0_6_9) begin if (_T_7510) begin - bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_105 <= io_exu_mp_pkt_bits_hist; end @@ -40883,7 +40883,7 @@ end // initial bht_bank_rd_data_out_0_106 <= 2'h0; end else if (bht_bank_sel_0_6_10) begin if (_T_7519) begin - bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_106 <= io_exu_mp_pkt_bits_hist; end @@ -40894,7 +40894,7 @@ end // initial bht_bank_rd_data_out_0_107 <= 2'h0; end else if (bht_bank_sel_0_6_11) begin if (_T_7528) begin - bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_107 <= io_exu_mp_pkt_bits_hist; end @@ -40905,7 +40905,7 @@ end // initial bht_bank_rd_data_out_0_108 <= 2'h0; end else if (bht_bank_sel_0_6_12) begin if (_T_7537) begin - bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_108 <= io_exu_mp_pkt_bits_hist; end @@ -40916,7 +40916,7 @@ end // initial bht_bank_rd_data_out_0_109 <= 2'h0; end else if (bht_bank_sel_0_6_13) begin if (_T_7546) begin - bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_109 <= io_exu_mp_pkt_bits_hist; end @@ -40927,7 +40927,7 @@ end // initial bht_bank_rd_data_out_0_110 <= 2'h0; end else if (bht_bank_sel_0_6_14) begin if (_T_7555) begin - bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_110 <= io_exu_mp_pkt_bits_hist; end @@ -40938,7 +40938,7 @@ end // initial bht_bank_rd_data_out_0_111 <= 2'h0; end else if (bht_bank_sel_0_6_15) begin if (_T_7564) begin - bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_111 <= io_exu_mp_pkt_bits_hist; end @@ -40949,7 +40949,7 @@ end // initial bht_bank_rd_data_out_0_112 <= 2'h0; end else if (bht_bank_sel_0_7_0) begin if (_T_7573) begin - bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_112 <= io_exu_mp_pkt_bits_hist; end @@ -40960,7 +40960,7 @@ end // initial bht_bank_rd_data_out_0_113 <= 2'h0; end else if (bht_bank_sel_0_7_1) begin if (_T_7582) begin - bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_113 <= io_exu_mp_pkt_bits_hist; end @@ -40971,7 +40971,7 @@ end // initial bht_bank_rd_data_out_0_114 <= 2'h0; end else if (bht_bank_sel_0_7_2) begin if (_T_7591) begin - bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_114 <= io_exu_mp_pkt_bits_hist; end @@ -40982,7 +40982,7 @@ end // initial bht_bank_rd_data_out_0_115 <= 2'h0; end else if (bht_bank_sel_0_7_3) begin if (_T_7600) begin - bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_115 <= io_exu_mp_pkt_bits_hist; end @@ -40993,7 +40993,7 @@ end // initial bht_bank_rd_data_out_0_116 <= 2'h0; end else if (bht_bank_sel_0_7_4) begin if (_T_7609) begin - bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_116 <= io_exu_mp_pkt_bits_hist; end @@ -41004,7 +41004,7 @@ end // initial bht_bank_rd_data_out_0_117 <= 2'h0; end else if (bht_bank_sel_0_7_5) begin if (_T_7618) begin - bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_117 <= io_exu_mp_pkt_bits_hist; end @@ -41015,7 +41015,7 @@ end // initial bht_bank_rd_data_out_0_118 <= 2'h0; end else if (bht_bank_sel_0_7_6) begin if (_T_7627) begin - bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_118 <= io_exu_mp_pkt_bits_hist; end @@ -41026,7 +41026,7 @@ end // initial bht_bank_rd_data_out_0_119 <= 2'h0; end else if (bht_bank_sel_0_7_7) begin if (_T_7636) begin - bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_119 <= io_exu_mp_pkt_bits_hist; end @@ -41037,7 +41037,7 @@ end // initial bht_bank_rd_data_out_0_120 <= 2'h0; end else if (bht_bank_sel_0_7_8) begin if (_T_7645) begin - bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_120 <= io_exu_mp_pkt_bits_hist; end @@ -41048,7 +41048,7 @@ end // initial bht_bank_rd_data_out_0_121 <= 2'h0; end else if (bht_bank_sel_0_7_9) begin if (_T_7654) begin - bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_121 <= io_exu_mp_pkt_bits_hist; end @@ -41059,7 +41059,7 @@ end // initial bht_bank_rd_data_out_0_122 <= 2'h0; end else if (bht_bank_sel_0_7_10) begin if (_T_7663) begin - bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_122 <= io_exu_mp_pkt_bits_hist; end @@ -41070,7 +41070,7 @@ end // initial bht_bank_rd_data_out_0_123 <= 2'h0; end else if (bht_bank_sel_0_7_11) begin if (_T_7672) begin - bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_123 <= io_exu_mp_pkt_bits_hist; end @@ -41081,7 +41081,7 @@ end // initial bht_bank_rd_data_out_0_124 <= 2'h0; end else if (bht_bank_sel_0_7_12) begin if (_T_7681) begin - bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_124 <= io_exu_mp_pkt_bits_hist; end @@ -41092,7 +41092,7 @@ end // initial bht_bank_rd_data_out_0_125 <= 2'h0; end else if (bht_bank_sel_0_7_13) begin if (_T_7690) begin - bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_125 <= io_exu_mp_pkt_bits_hist; end @@ -41103,7 +41103,7 @@ end // initial bht_bank_rd_data_out_0_126 <= 2'h0; end else if (bht_bank_sel_0_7_14) begin if (_T_7699) begin - bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_126 <= io_exu_mp_pkt_bits_hist; end @@ -41114,7 +41114,7 @@ end // initial bht_bank_rd_data_out_0_127 <= 2'h0; end else if (bht_bank_sel_0_7_15) begin if (_T_7708) begin - bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_127 <= io_exu_mp_pkt_bits_hist; end @@ -41125,7 +41125,7 @@ end // initial bht_bank_rd_data_out_0_128 <= 2'h0; end else if (bht_bank_sel_0_8_0) begin if (_T_7717) begin - bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_128 <= io_exu_mp_pkt_bits_hist; end @@ -41136,7 +41136,7 @@ end // initial bht_bank_rd_data_out_0_129 <= 2'h0; end else if (bht_bank_sel_0_8_1) begin if (_T_7726) begin - bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_129 <= io_exu_mp_pkt_bits_hist; end @@ -41147,7 +41147,7 @@ end // initial bht_bank_rd_data_out_0_130 <= 2'h0; end else if (bht_bank_sel_0_8_2) begin if (_T_7735) begin - bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_130 <= io_exu_mp_pkt_bits_hist; end @@ -41158,7 +41158,7 @@ end // initial bht_bank_rd_data_out_0_131 <= 2'h0; end else if (bht_bank_sel_0_8_3) begin if (_T_7744) begin - bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_131 <= io_exu_mp_pkt_bits_hist; end @@ -41169,7 +41169,7 @@ end // initial bht_bank_rd_data_out_0_132 <= 2'h0; end else if (bht_bank_sel_0_8_4) begin if (_T_7753) begin - bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_132 <= io_exu_mp_pkt_bits_hist; end @@ -41180,7 +41180,7 @@ end // initial bht_bank_rd_data_out_0_133 <= 2'h0; end else if (bht_bank_sel_0_8_5) begin if (_T_7762) begin - bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_133 <= io_exu_mp_pkt_bits_hist; end @@ -41191,7 +41191,7 @@ end // initial bht_bank_rd_data_out_0_134 <= 2'h0; end else if (bht_bank_sel_0_8_6) begin if (_T_7771) begin - bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_134 <= io_exu_mp_pkt_bits_hist; end @@ -41202,7 +41202,7 @@ end // initial bht_bank_rd_data_out_0_135 <= 2'h0; end else if (bht_bank_sel_0_8_7) begin if (_T_7780) begin - bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_135 <= io_exu_mp_pkt_bits_hist; end @@ -41213,7 +41213,7 @@ end // initial bht_bank_rd_data_out_0_136 <= 2'h0; end else if (bht_bank_sel_0_8_8) begin if (_T_7789) begin - bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_136 <= io_exu_mp_pkt_bits_hist; end @@ -41224,7 +41224,7 @@ end // initial bht_bank_rd_data_out_0_137 <= 2'h0; end else if (bht_bank_sel_0_8_9) begin if (_T_7798) begin - bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_137 <= io_exu_mp_pkt_bits_hist; end @@ -41235,7 +41235,7 @@ end // initial bht_bank_rd_data_out_0_138 <= 2'h0; end else if (bht_bank_sel_0_8_10) begin if (_T_7807) begin - bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_138 <= io_exu_mp_pkt_bits_hist; end @@ -41246,7 +41246,7 @@ end // initial bht_bank_rd_data_out_0_139 <= 2'h0; end else if (bht_bank_sel_0_8_11) begin if (_T_7816) begin - bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_139 <= io_exu_mp_pkt_bits_hist; end @@ -41257,7 +41257,7 @@ end // initial bht_bank_rd_data_out_0_140 <= 2'h0; end else if (bht_bank_sel_0_8_12) begin if (_T_7825) begin - bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_140 <= io_exu_mp_pkt_bits_hist; end @@ -41268,7 +41268,7 @@ end // initial bht_bank_rd_data_out_0_141 <= 2'h0; end else if (bht_bank_sel_0_8_13) begin if (_T_7834) begin - bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_141 <= io_exu_mp_pkt_bits_hist; end @@ -41279,7 +41279,7 @@ end // initial bht_bank_rd_data_out_0_142 <= 2'h0; end else if (bht_bank_sel_0_8_14) begin if (_T_7843) begin - bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_142 <= io_exu_mp_pkt_bits_hist; end @@ -41290,7 +41290,7 @@ end // initial bht_bank_rd_data_out_0_143 <= 2'h0; end else if (bht_bank_sel_0_8_15) begin if (_T_7852) begin - bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_143 <= io_exu_mp_pkt_bits_hist; end @@ -41301,7 +41301,7 @@ end // initial bht_bank_rd_data_out_0_144 <= 2'h0; end else if (bht_bank_sel_0_9_0) begin if (_T_7861) begin - bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_144 <= io_exu_mp_pkt_bits_hist; end @@ -41312,7 +41312,7 @@ end // initial bht_bank_rd_data_out_0_145 <= 2'h0; end else if (bht_bank_sel_0_9_1) begin if (_T_7870) begin - bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_145 <= io_exu_mp_pkt_bits_hist; end @@ -41323,7 +41323,7 @@ end // initial bht_bank_rd_data_out_0_146 <= 2'h0; end else if (bht_bank_sel_0_9_2) begin if (_T_7879) begin - bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_146 <= io_exu_mp_pkt_bits_hist; end @@ -41334,7 +41334,7 @@ end // initial bht_bank_rd_data_out_0_147 <= 2'h0; end else if (bht_bank_sel_0_9_3) begin if (_T_7888) begin - bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_147 <= io_exu_mp_pkt_bits_hist; end @@ -41345,7 +41345,7 @@ end // initial bht_bank_rd_data_out_0_148 <= 2'h0; end else if (bht_bank_sel_0_9_4) begin if (_T_7897) begin - bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_148 <= io_exu_mp_pkt_bits_hist; end @@ -41356,7 +41356,7 @@ end // initial bht_bank_rd_data_out_0_149 <= 2'h0; end else if (bht_bank_sel_0_9_5) begin if (_T_7906) begin - bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_149 <= io_exu_mp_pkt_bits_hist; end @@ -41367,7 +41367,7 @@ end // initial bht_bank_rd_data_out_0_150 <= 2'h0; end else if (bht_bank_sel_0_9_6) begin if (_T_7915) begin - bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_150 <= io_exu_mp_pkt_bits_hist; end @@ -41378,7 +41378,7 @@ end // initial bht_bank_rd_data_out_0_151 <= 2'h0; end else if (bht_bank_sel_0_9_7) begin if (_T_7924) begin - bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_151 <= io_exu_mp_pkt_bits_hist; end @@ -41389,7 +41389,7 @@ end // initial bht_bank_rd_data_out_0_152 <= 2'h0; end else if (bht_bank_sel_0_9_8) begin if (_T_7933) begin - bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_152 <= io_exu_mp_pkt_bits_hist; end @@ -41400,7 +41400,7 @@ end // initial bht_bank_rd_data_out_0_153 <= 2'h0; end else if (bht_bank_sel_0_9_9) begin if (_T_7942) begin - bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_153 <= io_exu_mp_pkt_bits_hist; end @@ -41411,7 +41411,7 @@ end // initial bht_bank_rd_data_out_0_154 <= 2'h0; end else if (bht_bank_sel_0_9_10) begin if (_T_7951) begin - bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_154 <= io_exu_mp_pkt_bits_hist; end @@ -41422,7 +41422,7 @@ end // initial bht_bank_rd_data_out_0_155 <= 2'h0; end else if (bht_bank_sel_0_9_11) begin if (_T_7960) begin - bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_155 <= io_exu_mp_pkt_bits_hist; end @@ -41433,7 +41433,7 @@ end // initial bht_bank_rd_data_out_0_156 <= 2'h0; end else if (bht_bank_sel_0_9_12) begin if (_T_7969) begin - bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_156 <= io_exu_mp_pkt_bits_hist; end @@ -41444,7 +41444,7 @@ end // initial bht_bank_rd_data_out_0_157 <= 2'h0; end else if (bht_bank_sel_0_9_13) begin if (_T_7978) begin - bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_157 <= io_exu_mp_pkt_bits_hist; end @@ -41455,7 +41455,7 @@ end // initial bht_bank_rd_data_out_0_158 <= 2'h0; end else if (bht_bank_sel_0_9_14) begin if (_T_7987) begin - bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_158 <= io_exu_mp_pkt_bits_hist; end @@ -41466,7 +41466,7 @@ end // initial bht_bank_rd_data_out_0_159 <= 2'h0; end else if (bht_bank_sel_0_9_15) begin if (_T_7996) begin - bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_159 <= io_exu_mp_pkt_bits_hist; end @@ -41477,7 +41477,7 @@ end // initial bht_bank_rd_data_out_0_160 <= 2'h0; end else if (bht_bank_sel_0_10_0) begin if (_T_8005) begin - bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_160 <= io_exu_mp_pkt_bits_hist; end @@ -41488,7 +41488,7 @@ end // initial bht_bank_rd_data_out_0_161 <= 2'h0; end else if (bht_bank_sel_0_10_1) begin if (_T_8014) begin - bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_161 <= io_exu_mp_pkt_bits_hist; end @@ -41499,7 +41499,7 @@ end // initial bht_bank_rd_data_out_0_162 <= 2'h0; end else if (bht_bank_sel_0_10_2) begin if (_T_8023) begin - bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_162 <= io_exu_mp_pkt_bits_hist; end @@ -41510,7 +41510,7 @@ end // initial bht_bank_rd_data_out_0_163 <= 2'h0; end else if (bht_bank_sel_0_10_3) begin if (_T_8032) begin - bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_163 <= io_exu_mp_pkt_bits_hist; end @@ -41521,7 +41521,7 @@ end // initial bht_bank_rd_data_out_0_164 <= 2'h0; end else if (bht_bank_sel_0_10_4) begin if (_T_8041) begin - bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_164 <= io_exu_mp_pkt_bits_hist; end @@ -41532,7 +41532,7 @@ end // initial bht_bank_rd_data_out_0_165 <= 2'h0; end else if (bht_bank_sel_0_10_5) begin if (_T_8050) begin - bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_165 <= io_exu_mp_pkt_bits_hist; end @@ -41543,7 +41543,7 @@ end // initial bht_bank_rd_data_out_0_166 <= 2'h0; end else if (bht_bank_sel_0_10_6) begin if (_T_8059) begin - bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_166 <= io_exu_mp_pkt_bits_hist; end @@ -41554,7 +41554,7 @@ end // initial bht_bank_rd_data_out_0_167 <= 2'h0; end else if (bht_bank_sel_0_10_7) begin if (_T_8068) begin - bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_167 <= io_exu_mp_pkt_bits_hist; end @@ -41565,7 +41565,7 @@ end // initial bht_bank_rd_data_out_0_168 <= 2'h0; end else if (bht_bank_sel_0_10_8) begin if (_T_8077) begin - bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_168 <= io_exu_mp_pkt_bits_hist; end @@ -41576,7 +41576,7 @@ end // initial bht_bank_rd_data_out_0_169 <= 2'h0; end else if (bht_bank_sel_0_10_9) begin if (_T_8086) begin - bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_169 <= io_exu_mp_pkt_bits_hist; end @@ -41587,7 +41587,7 @@ end // initial bht_bank_rd_data_out_0_170 <= 2'h0; end else if (bht_bank_sel_0_10_10) begin if (_T_8095) begin - bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_170 <= io_exu_mp_pkt_bits_hist; end @@ -41598,7 +41598,7 @@ end // initial bht_bank_rd_data_out_0_171 <= 2'h0; end else if (bht_bank_sel_0_10_11) begin if (_T_8104) begin - bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_171 <= io_exu_mp_pkt_bits_hist; end @@ -41609,7 +41609,7 @@ end // initial bht_bank_rd_data_out_0_172 <= 2'h0; end else if (bht_bank_sel_0_10_12) begin if (_T_8113) begin - bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_172 <= io_exu_mp_pkt_bits_hist; end @@ -41620,7 +41620,7 @@ end // initial bht_bank_rd_data_out_0_173 <= 2'h0; end else if (bht_bank_sel_0_10_13) begin if (_T_8122) begin - bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_173 <= io_exu_mp_pkt_bits_hist; end @@ -41631,7 +41631,7 @@ end // initial bht_bank_rd_data_out_0_174 <= 2'h0; end else if (bht_bank_sel_0_10_14) begin if (_T_8131) begin - bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_174 <= io_exu_mp_pkt_bits_hist; end @@ -41642,7 +41642,7 @@ end // initial bht_bank_rd_data_out_0_175 <= 2'h0; end else if (bht_bank_sel_0_10_15) begin if (_T_8140) begin - bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_175 <= io_exu_mp_pkt_bits_hist; end @@ -41653,7 +41653,7 @@ end // initial bht_bank_rd_data_out_0_176 <= 2'h0; end else if (bht_bank_sel_0_11_0) begin if (_T_8149) begin - bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_176 <= io_exu_mp_pkt_bits_hist; end @@ -41664,7 +41664,7 @@ end // initial bht_bank_rd_data_out_0_177 <= 2'h0; end else if (bht_bank_sel_0_11_1) begin if (_T_8158) begin - bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_177 <= io_exu_mp_pkt_bits_hist; end @@ -41675,7 +41675,7 @@ end // initial bht_bank_rd_data_out_0_178 <= 2'h0; end else if (bht_bank_sel_0_11_2) begin if (_T_8167) begin - bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_178 <= io_exu_mp_pkt_bits_hist; end @@ -41686,7 +41686,7 @@ end // initial bht_bank_rd_data_out_0_179 <= 2'h0; end else if (bht_bank_sel_0_11_3) begin if (_T_8176) begin - bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_179 <= io_exu_mp_pkt_bits_hist; end @@ -41697,7 +41697,7 @@ end // initial bht_bank_rd_data_out_0_180 <= 2'h0; end else if (bht_bank_sel_0_11_4) begin if (_T_8185) begin - bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_180 <= io_exu_mp_pkt_bits_hist; end @@ -41708,7 +41708,7 @@ end // initial bht_bank_rd_data_out_0_181 <= 2'h0; end else if (bht_bank_sel_0_11_5) begin if (_T_8194) begin - bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_181 <= io_exu_mp_pkt_bits_hist; end @@ -41719,7 +41719,7 @@ end // initial bht_bank_rd_data_out_0_182 <= 2'h0; end else if (bht_bank_sel_0_11_6) begin if (_T_8203) begin - bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_182 <= io_exu_mp_pkt_bits_hist; end @@ -41730,7 +41730,7 @@ end // initial bht_bank_rd_data_out_0_183 <= 2'h0; end else if (bht_bank_sel_0_11_7) begin if (_T_8212) begin - bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_183 <= io_exu_mp_pkt_bits_hist; end @@ -41741,7 +41741,7 @@ end // initial bht_bank_rd_data_out_0_184 <= 2'h0; end else if (bht_bank_sel_0_11_8) begin if (_T_8221) begin - bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_184 <= io_exu_mp_pkt_bits_hist; end @@ -41752,7 +41752,7 @@ end // initial bht_bank_rd_data_out_0_185 <= 2'h0; end else if (bht_bank_sel_0_11_9) begin if (_T_8230) begin - bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_185 <= io_exu_mp_pkt_bits_hist; end @@ -41763,7 +41763,7 @@ end // initial bht_bank_rd_data_out_0_186 <= 2'h0; end else if (bht_bank_sel_0_11_10) begin if (_T_8239) begin - bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_186 <= io_exu_mp_pkt_bits_hist; end @@ -41774,7 +41774,7 @@ end // initial bht_bank_rd_data_out_0_187 <= 2'h0; end else if (bht_bank_sel_0_11_11) begin if (_T_8248) begin - bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_187 <= io_exu_mp_pkt_bits_hist; end @@ -41785,7 +41785,7 @@ end // initial bht_bank_rd_data_out_0_188 <= 2'h0; end else if (bht_bank_sel_0_11_12) begin if (_T_8257) begin - bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_188 <= io_exu_mp_pkt_bits_hist; end @@ -41796,7 +41796,7 @@ end // initial bht_bank_rd_data_out_0_189 <= 2'h0; end else if (bht_bank_sel_0_11_13) begin if (_T_8266) begin - bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_189 <= io_exu_mp_pkt_bits_hist; end @@ -41807,7 +41807,7 @@ end // initial bht_bank_rd_data_out_0_190 <= 2'h0; end else if (bht_bank_sel_0_11_14) begin if (_T_8275) begin - bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_190 <= io_exu_mp_pkt_bits_hist; end @@ -41818,7 +41818,7 @@ end // initial bht_bank_rd_data_out_0_191 <= 2'h0; end else if (bht_bank_sel_0_11_15) begin if (_T_8284) begin - bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_191 <= io_exu_mp_pkt_bits_hist; end @@ -41829,7 +41829,7 @@ end // initial bht_bank_rd_data_out_0_192 <= 2'h0; end else if (bht_bank_sel_0_12_0) begin if (_T_8293) begin - bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_192 <= io_exu_mp_pkt_bits_hist; end @@ -41840,7 +41840,7 @@ end // initial bht_bank_rd_data_out_0_193 <= 2'h0; end else if (bht_bank_sel_0_12_1) begin if (_T_8302) begin - bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_193 <= io_exu_mp_pkt_bits_hist; end @@ -41851,7 +41851,7 @@ end // initial bht_bank_rd_data_out_0_194 <= 2'h0; end else if (bht_bank_sel_0_12_2) begin if (_T_8311) begin - bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_194 <= io_exu_mp_pkt_bits_hist; end @@ -41862,7 +41862,7 @@ end // initial bht_bank_rd_data_out_0_195 <= 2'h0; end else if (bht_bank_sel_0_12_3) begin if (_T_8320) begin - bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_195 <= io_exu_mp_pkt_bits_hist; end @@ -41873,7 +41873,7 @@ end // initial bht_bank_rd_data_out_0_196 <= 2'h0; end else if (bht_bank_sel_0_12_4) begin if (_T_8329) begin - bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_196 <= io_exu_mp_pkt_bits_hist; end @@ -41884,7 +41884,7 @@ end // initial bht_bank_rd_data_out_0_197 <= 2'h0; end else if (bht_bank_sel_0_12_5) begin if (_T_8338) begin - bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_197 <= io_exu_mp_pkt_bits_hist; end @@ -41895,7 +41895,7 @@ end // initial bht_bank_rd_data_out_0_198 <= 2'h0; end else if (bht_bank_sel_0_12_6) begin if (_T_8347) begin - bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_198 <= io_exu_mp_pkt_bits_hist; end @@ -41906,7 +41906,7 @@ end // initial bht_bank_rd_data_out_0_199 <= 2'h0; end else if (bht_bank_sel_0_12_7) begin if (_T_8356) begin - bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_199 <= io_exu_mp_pkt_bits_hist; end @@ -41917,7 +41917,7 @@ end // initial bht_bank_rd_data_out_0_200 <= 2'h0; end else if (bht_bank_sel_0_12_8) begin if (_T_8365) begin - bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_200 <= io_exu_mp_pkt_bits_hist; end @@ -41928,7 +41928,7 @@ end // initial bht_bank_rd_data_out_0_201 <= 2'h0; end else if (bht_bank_sel_0_12_9) begin if (_T_8374) begin - bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_201 <= io_exu_mp_pkt_bits_hist; end @@ -41939,7 +41939,7 @@ end // initial bht_bank_rd_data_out_0_202 <= 2'h0; end else if (bht_bank_sel_0_12_10) begin if (_T_8383) begin - bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_202 <= io_exu_mp_pkt_bits_hist; end @@ -41950,7 +41950,7 @@ end // initial bht_bank_rd_data_out_0_203 <= 2'h0; end else if (bht_bank_sel_0_12_11) begin if (_T_8392) begin - bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_203 <= io_exu_mp_pkt_bits_hist; end @@ -41961,7 +41961,7 @@ end // initial bht_bank_rd_data_out_0_204 <= 2'h0; end else if (bht_bank_sel_0_12_12) begin if (_T_8401) begin - bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_204 <= io_exu_mp_pkt_bits_hist; end @@ -41972,7 +41972,7 @@ end // initial bht_bank_rd_data_out_0_205 <= 2'h0; end else if (bht_bank_sel_0_12_13) begin if (_T_8410) begin - bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_205 <= io_exu_mp_pkt_bits_hist; end @@ -41983,7 +41983,7 @@ end // initial bht_bank_rd_data_out_0_206 <= 2'h0; end else if (bht_bank_sel_0_12_14) begin if (_T_8419) begin - bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_206 <= io_exu_mp_pkt_bits_hist; end @@ -41994,7 +41994,7 @@ end // initial bht_bank_rd_data_out_0_207 <= 2'h0; end else if (bht_bank_sel_0_12_15) begin if (_T_8428) begin - bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_207 <= io_exu_mp_pkt_bits_hist; end @@ -42005,7 +42005,7 @@ end // initial bht_bank_rd_data_out_0_208 <= 2'h0; end else if (bht_bank_sel_0_13_0) begin if (_T_8437) begin - bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_208 <= io_exu_mp_pkt_bits_hist; end @@ -42016,7 +42016,7 @@ end // initial bht_bank_rd_data_out_0_209 <= 2'h0; end else if (bht_bank_sel_0_13_1) begin if (_T_8446) begin - bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_209 <= io_exu_mp_pkt_bits_hist; end @@ -42027,7 +42027,7 @@ end // initial bht_bank_rd_data_out_0_210 <= 2'h0; end else if (bht_bank_sel_0_13_2) begin if (_T_8455) begin - bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_210 <= io_exu_mp_pkt_bits_hist; end @@ -42038,7 +42038,7 @@ end // initial bht_bank_rd_data_out_0_211 <= 2'h0; end else if (bht_bank_sel_0_13_3) begin if (_T_8464) begin - bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_211 <= io_exu_mp_pkt_bits_hist; end @@ -42049,7 +42049,7 @@ end // initial bht_bank_rd_data_out_0_212 <= 2'h0; end else if (bht_bank_sel_0_13_4) begin if (_T_8473) begin - bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_212 <= io_exu_mp_pkt_bits_hist; end @@ -42060,7 +42060,7 @@ end // initial bht_bank_rd_data_out_0_213 <= 2'h0; end else if (bht_bank_sel_0_13_5) begin if (_T_8482) begin - bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_213 <= io_exu_mp_pkt_bits_hist; end @@ -42071,7 +42071,7 @@ end // initial bht_bank_rd_data_out_0_214 <= 2'h0; end else if (bht_bank_sel_0_13_6) begin if (_T_8491) begin - bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_214 <= io_exu_mp_pkt_bits_hist; end @@ -42082,7 +42082,7 @@ end // initial bht_bank_rd_data_out_0_215 <= 2'h0; end else if (bht_bank_sel_0_13_7) begin if (_T_8500) begin - bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_215 <= io_exu_mp_pkt_bits_hist; end @@ -42093,7 +42093,7 @@ end // initial bht_bank_rd_data_out_0_216 <= 2'h0; end else if (bht_bank_sel_0_13_8) begin if (_T_8509) begin - bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_216 <= io_exu_mp_pkt_bits_hist; end @@ -42104,7 +42104,7 @@ end // initial bht_bank_rd_data_out_0_217 <= 2'h0; end else if (bht_bank_sel_0_13_9) begin if (_T_8518) begin - bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_217 <= io_exu_mp_pkt_bits_hist; end @@ -42115,7 +42115,7 @@ end // initial bht_bank_rd_data_out_0_218 <= 2'h0; end else if (bht_bank_sel_0_13_10) begin if (_T_8527) begin - bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_218 <= io_exu_mp_pkt_bits_hist; end @@ -42126,7 +42126,7 @@ end // initial bht_bank_rd_data_out_0_219 <= 2'h0; end else if (bht_bank_sel_0_13_11) begin if (_T_8536) begin - bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_219 <= io_exu_mp_pkt_bits_hist; end @@ -42137,7 +42137,7 @@ end // initial bht_bank_rd_data_out_0_220 <= 2'h0; end else if (bht_bank_sel_0_13_12) begin if (_T_8545) begin - bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_220 <= io_exu_mp_pkt_bits_hist; end @@ -42148,7 +42148,7 @@ end // initial bht_bank_rd_data_out_0_221 <= 2'h0; end else if (bht_bank_sel_0_13_13) begin if (_T_8554) begin - bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_221 <= io_exu_mp_pkt_bits_hist; end @@ -42159,7 +42159,7 @@ end // initial bht_bank_rd_data_out_0_222 <= 2'h0; end else if (bht_bank_sel_0_13_14) begin if (_T_8563) begin - bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_222 <= io_exu_mp_pkt_bits_hist; end @@ -42170,7 +42170,7 @@ end // initial bht_bank_rd_data_out_0_223 <= 2'h0; end else if (bht_bank_sel_0_13_15) begin if (_T_8572) begin - bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_223 <= io_exu_mp_pkt_bits_hist; end @@ -42181,7 +42181,7 @@ end // initial bht_bank_rd_data_out_0_224 <= 2'h0; end else if (bht_bank_sel_0_14_0) begin if (_T_8581) begin - bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_224 <= io_exu_mp_pkt_bits_hist; end @@ -42192,7 +42192,7 @@ end // initial bht_bank_rd_data_out_0_225 <= 2'h0; end else if (bht_bank_sel_0_14_1) begin if (_T_8590) begin - bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_225 <= io_exu_mp_pkt_bits_hist; end @@ -42203,7 +42203,7 @@ end // initial bht_bank_rd_data_out_0_226 <= 2'h0; end else if (bht_bank_sel_0_14_2) begin if (_T_8599) begin - bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_226 <= io_exu_mp_pkt_bits_hist; end @@ -42214,7 +42214,7 @@ end // initial bht_bank_rd_data_out_0_227 <= 2'h0; end else if (bht_bank_sel_0_14_3) begin if (_T_8608) begin - bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_227 <= io_exu_mp_pkt_bits_hist; end @@ -42225,7 +42225,7 @@ end // initial bht_bank_rd_data_out_0_228 <= 2'h0; end else if (bht_bank_sel_0_14_4) begin if (_T_8617) begin - bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_228 <= io_exu_mp_pkt_bits_hist; end @@ -42236,7 +42236,7 @@ end // initial bht_bank_rd_data_out_0_229 <= 2'h0; end else if (bht_bank_sel_0_14_5) begin if (_T_8626) begin - bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_229 <= io_exu_mp_pkt_bits_hist; end @@ -42247,7 +42247,7 @@ end // initial bht_bank_rd_data_out_0_230 <= 2'h0; end else if (bht_bank_sel_0_14_6) begin if (_T_8635) begin - bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_230 <= io_exu_mp_pkt_bits_hist; end @@ -42258,7 +42258,7 @@ end // initial bht_bank_rd_data_out_0_231 <= 2'h0; end else if (bht_bank_sel_0_14_7) begin if (_T_8644) begin - bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_231 <= io_exu_mp_pkt_bits_hist; end @@ -42269,7 +42269,7 @@ end // initial bht_bank_rd_data_out_0_232 <= 2'h0; end else if (bht_bank_sel_0_14_8) begin if (_T_8653) begin - bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_232 <= io_exu_mp_pkt_bits_hist; end @@ -42280,7 +42280,7 @@ end // initial bht_bank_rd_data_out_0_233 <= 2'h0; end else if (bht_bank_sel_0_14_9) begin if (_T_8662) begin - bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_233 <= io_exu_mp_pkt_bits_hist; end @@ -42291,7 +42291,7 @@ end // initial bht_bank_rd_data_out_0_234 <= 2'h0; end else if (bht_bank_sel_0_14_10) begin if (_T_8671) begin - bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_234 <= io_exu_mp_pkt_bits_hist; end @@ -42302,7 +42302,7 @@ end // initial bht_bank_rd_data_out_0_235 <= 2'h0; end else if (bht_bank_sel_0_14_11) begin if (_T_8680) begin - bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_235 <= io_exu_mp_pkt_bits_hist; end @@ -42313,7 +42313,7 @@ end // initial bht_bank_rd_data_out_0_236 <= 2'h0; end else if (bht_bank_sel_0_14_12) begin if (_T_8689) begin - bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_236 <= io_exu_mp_pkt_bits_hist; end @@ -42324,7 +42324,7 @@ end // initial bht_bank_rd_data_out_0_237 <= 2'h0; end else if (bht_bank_sel_0_14_13) begin if (_T_8698) begin - bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_237 <= io_exu_mp_pkt_bits_hist; end @@ -42335,7 +42335,7 @@ end // initial bht_bank_rd_data_out_0_238 <= 2'h0; end else if (bht_bank_sel_0_14_14) begin if (_T_8707) begin - bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_238 <= io_exu_mp_pkt_bits_hist; end @@ -42346,7 +42346,7 @@ end // initial bht_bank_rd_data_out_0_239 <= 2'h0; end else if (bht_bank_sel_0_14_15) begin if (_T_8716) begin - bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_239 <= io_exu_mp_pkt_bits_hist; end @@ -42357,7 +42357,7 @@ end // initial bht_bank_rd_data_out_0_240 <= 2'h0; end else if (bht_bank_sel_0_15_0) begin if (_T_8725) begin - bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_240 <= io_exu_mp_pkt_bits_hist; end @@ -42368,7 +42368,7 @@ end // initial bht_bank_rd_data_out_0_241 <= 2'h0; end else if (bht_bank_sel_0_15_1) begin if (_T_8734) begin - bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_241 <= io_exu_mp_pkt_bits_hist; end @@ -42379,7 +42379,7 @@ end // initial bht_bank_rd_data_out_0_242 <= 2'h0; end else if (bht_bank_sel_0_15_2) begin if (_T_8743) begin - bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_242 <= io_exu_mp_pkt_bits_hist; end @@ -42390,7 +42390,7 @@ end // initial bht_bank_rd_data_out_0_243 <= 2'h0; end else if (bht_bank_sel_0_15_3) begin if (_T_8752) begin - bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_243 <= io_exu_mp_pkt_bits_hist; end @@ -42401,7 +42401,7 @@ end // initial bht_bank_rd_data_out_0_244 <= 2'h0; end else if (bht_bank_sel_0_15_4) begin if (_T_8761) begin - bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_244 <= io_exu_mp_pkt_bits_hist; end @@ -42412,7 +42412,7 @@ end // initial bht_bank_rd_data_out_0_245 <= 2'h0; end else if (bht_bank_sel_0_15_5) begin if (_T_8770) begin - bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_245 <= io_exu_mp_pkt_bits_hist; end @@ -42423,7 +42423,7 @@ end // initial bht_bank_rd_data_out_0_246 <= 2'h0; end else if (bht_bank_sel_0_15_6) begin if (_T_8779) begin - bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_246 <= io_exu_mp_pkt_bits_hist; end @@ -42434,7 +42434,7 @@ end // initial bht_bank_rd_data_out_0_247 <= 2'h0; end else if (bht_bank_sel_0_15_7) begin if (_T_8788) begin - bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_247 <= io_exu_mp_pkt_bits_hist; end @@ -42445,7 +42445,7 @@ end // initial bht_bank_rd_data_out_0_248 <= 2'h0; end else if (bht_bank_sel_0_15_8) begin if (_T_8797) begin - bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_248 <= io_exu_mp_pkt_bits_hist; end @@ -42456,7 +42456,7 @@ end // initial bht_bank_rd_data_out_0_249 <= 2'h0; end else if (bht_bank_sel_0_15_9) begin if (_T_8806) begin - bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_249 <= io_exu_mp_pkt_bits_hist; end @@ -42467,7 +42467,7 @@ end // initial bht_bank_rd_data_out_0_250 <= 2'h0; end else if (bht_bank_sel_0_15_10) begin if (_T_8815) begin - bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_250 <= io_exu_mp_pkt_bits_hist; end @@ -42478,7 +42478,7 @@ end // initial bht_bank_rd_data_out_0_251 <= 2'h0; end else if (bht_bank_sel_0_15_11) begin if (_T_8824) begin - bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_251 <= io_exu_mp_pkt_bits_hist; end @@ -42489,7 +42489,7 @@ end // initial bht_bank_rd_data_out_0_252 <= 2'h0; end else if (bht_bank_sel_0_15_12) begin if (_T_8833) begin - bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_252 <= io_exu_mp_pkt_bits_hist; end @@ -42500,7 +42500,7 @@ end // initial bht_bank_rd_data_out_0_253 <= 2'h0; end else if (bht_bank_sel_0_15_13) begin if (_T_8842) begin - bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_253 <= io_exu_mp_pkt_bits_hist; end @@ -42511,7 +42511,7 @@ end // initial bht_bank_rd_data_out_0_254 <= 2'h0; end else if (bht_bank_sel_0_15_14) begin if (_T_8851) begin - bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_254 <= io_exu_mp_pkt_bits_hist; end @@ -42522,7 +42522,7 @@ end // initial bht_bank_rd_data_out_0_255 <= 2'h0; end else if (bht_bank_sel_0_15_15) begin if (_T_8860) begin - bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_bits_hist; + bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_hist; end else begin bht_bank_rd_data_out_0_255 <= io_exu_mp_pkt_bits_hist; end @@ -43161,13 +43161,13 @@ module el2_ifu_aln_ctl( output io_ifu_pmu_instr_aligned, output [15:0] io_ifu_i0_cinst, output io_i0_brp_valid, - output [11:0] io_i0_brp_bits_toffset, - output [1:0] io_i0_brp_bits_hist, - output io_i0_brp_bits_br_error, - output io_i0_brp_bits_br_start_error, - output [30:0] io_i0_brp_bits_prett, - output io_i0_brp_bits_way, - output io_i0_brp_bits_ret + output [11:0] io_i0_brp_toffset, + output [1:0] io_i0_brp_hist, + output io_i0_brp_br_error, + output io_i0_brp_br_start_error, + output [30:0] io_i0_brp_prett, + output io_i0_brp_way, + output io_i0_brp_ret ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -43606,24 +43606,24 @@ module el2_ifu_aln_ctl( wire _T_721 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 378:58] wire _T_722 = _T_719 | _T_721; // @[el2_ifu_aln_ctl.scala 378:47] wire _T_726 = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:100] - wire _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:34] - wire _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:60] + wire _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:29] + wire _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:55] wire _T_734 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 382:29] wire _T_736 = first4B & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 382:55] wire i0_brp_pc4 = _T_734 | _T_736; // @[el2_ifu_aln_ctl.scala 382:44] - wire _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:38] - wire _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:39] - wire _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:67] - wire _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:56] + wire _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:33] + wire _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:34] + wire _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:62] + wire _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:51] wire _T_749 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 387:14] wire _T_751 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42] wire _T_752 = _T_749 | _T_751; // @[el2_ifu_aln_ctl.scala 387:31] wire i0_ends_f1 = first4B & _T_515; // @[el2_ifu_aln_ctl.scala 389:28] - wire _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:47] - wire _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:61] - wire _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:94] - wire _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:92] - wire _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:106] + wire _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42] + wire _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:56] + wire _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89] + wire _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:87] + wire _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:101] rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -43716,13 +43716,13 @@ module el2_ifu_aln_ctl( assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_785; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28] assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 61:19 el2_ifu_aln_ctl.scala 346:19] assign io_i0_brp_valid = _T_722 | _T_726; // @[el2_ifu_aln_ctl.scala 378:19] - assign io_i0_brp_bits_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:26] - assign io_i0_brp_bits_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:23] - assign io_i0_brp_bits_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:27] - assign io_i0_brp_bits_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:34] - assign io_i0_brp_bits_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:24] - assign io_i0_brp_bits_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:22] - assign io_i0_brp_bits_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:22] + assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:21] + assign io_i0_brp_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:18] + assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22] + assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29] + assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19] + assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17] + assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_en = _T_354 | _T_358; // @[el2_lib.scala 511:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] @@ -44448,13 +44448,13 @@ module el2_ifu( output io_ifu_i0_pc4, output io_ifu_miss_state_idle, output io_i0_brp_valid, - output [11:0] io_i0_brp_bits_toffset, - output [1:0] io_i0_brp_bits_hist, - output io_i0_brp_bits_br_error, - output io_i0_brp_bits_br_start_error, - output [30:0] io_i0_brp_bits_prett, - output io_i0_brp_bits_way, - output io_i0_brp_bits_ret, + output [11:0] io_i0_brp_toffset, + output [1:0] io_i0_brp_hist, + output io_i0_brp_br_error, + output io_i0_brp_br_start_error, + output [30:0] io_i0_brp_prett, + output io_i0_brp_way, + output io_i0_brp_ret, output [7:0] io_ifu_i0_bp_index, output [7:0] io_ifu_i0_bp_fghr, output [4:0] io_ifu_i0_bp_btag, @@ -44473,11 +44473,11 @@ module el2_ifu( input [7:0] io_exu_mp_index, input [4:0] io_exu_mp_btag, input io_dec_tlu_br0_r_pkt_valid, - input [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - input io_dec_tlu_br0_r_pkt_bits_br_error, - input io_dec_tlu_br0_r_pkt_bits_br_start_error, - input io_dec_tlu_br0_r_pkt_bits_way, - input io_dec_tlu_br0_r_pkt_bits_middle, + input [1:0] io_dec_tlu_br0_r_pkt_hist, + input io_dec_tlu_br0_r_pkt_br_error, + input io_dec_tlu_br0_r_pkt_br_start_error, + input io_dec_tlu_br0_r_pkt_way, + input io_dec_tlu_br0_r_pkt_middle, input [7:0] io_exu_i0_br_fghr_r, input [7:0] io_exu_i0_br_index_r, input io_dec_tlu_flush_lower_wb, @@ -44596,11 +44596,11 @@ module el2_ifu( wire [30:0] bp_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 147:25] - wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 147:25] - wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 147:25] + wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 147:25] + wire bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 147:25] wire [7:0] bp_ctl_ch_io_exu_i0_br_fghr_r; // @[el2_ifu.scala 147:25] wire [7:0] bp_ctl_ch_io_exu_i0_br_index_r; // @[el2_ifu.scala 147:25] wire bp_ctl_ch_io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 147:25] @@ -44671,13 +44671,13 @@ module el2_ifu( wire aln_ctl_ch_io_ifu_pmu_instr_aligned; // @[el2_ifu.scala 148:26] wire [15:0] aln_ctl_ch_io_ifu_i0_cinst; // @[el2_ifu.scala 148:26] wire aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 148:26] - wire [11:0] aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 148:26] - wire [1:0] aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 148:26] - wire [30:0] aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 148:26] - wire aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 148:26] + wire [11:0] aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 148:26] + wire [1:0] aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 148:26] + wire [30:0] aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 148:26] + wire aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 148:26] wire ifc_ctl_ch_clock; // @[el2_ifu.scala 149:26] wire ifc_ctl_ch_reset; // @[el2_ifu.scala 149:26] wire ifc_ctl_ch_io_free_clk; // @[el2_ifu.scala 149:26] @@ -44814,11 +44814,11 @@ module el2_ifu( .io_ifc_fetch_addr_f(bp_ctl_ch_io_ifc_fetch_addr_f), .io_ifc_fetch_req_f(bp_ctl_ch_io_ifc_fetch_req_f), .io_dec_tlu_br0_r_pkt_valid(bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle), .io_exu_i0_br_fghr_r(bp_ctl_ch_io_exu_i0_br_fghr_r), .io_exu_i0_br_index_r(bp_ctl_ch_io_exu_i0_br_index_r), .io_dec_tlu_flush_lower_wb(bp_ctl_ch_io_dec_tlu_flush_lower_wb), @@ -44891,13 +44891,13 @@ module el2_ifu( .io_ifu_pmu_instr_aligned(aln_ctl_ch_io_ifu_pmu_instr_aligned), .io_ifu_i0_cinst(aln_ctl_ch_io_ifu_i0_cinst), .io_i0_brp_valid(aln_ctl_ch_io_i0_brp_valid), - .io_i0_brp_bits_toffset(aln_ctl_ch_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(aln_ctl_ch_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(aln_ctl_ch_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(aln_ctl_ch_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_prett(aln_ctl_ch_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(aln_ctl_ch_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(aln_ctl_ch_io_i0_brp_bits_ret) + .io_i0_brp_toffset(aln_ctl_ch_io_i0_brp_toffset), + .io_i0_brp_hist(aln_ctl_ch_io_i0_brp_hist), + .io_i0_brp_br_error(aln_ctl_ch_io_i0_brp_br_error), + .io_i0_brp_br_start_error(aln_ctl_ch_io_i0_brp_br_start_error), + .io_i0_brp_prett(aln_ctl_ch_io_i0_brp_prett), + .io_i0_brp_way(aln_ctl_ch_io_i0_brp_way), + .io_i0_brp_ret(aln_ctl_ch_io_i0_brp_ret) ); el2_ifu_ifc_ctl ifc_ctl_ch ( // @[el2_ifu.scala 149:26] .clock(ifc_ctl_ch_clock), @@ -44978,13 +44978,13 @@ module el2_ifu( assign io_ifu_i0_pc4 = aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 328:17] assign io_ifu_miss_state_idle = mem_ctl_ch_io_ifu_miss_state_idle; // @[el2_ifu.scala 329:26] assign io_i0_brp_valid = aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_toffset = aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_hist = aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_br_error = aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_br_start_error = aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_prett = aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_way = aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 331:13] - assign io_i0_brp_bits_ret = aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 331:13] + assign io_i0_brp_toffset = aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 331:13] + assign io_i0_brp_hist = aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 331:13] + assign io_i0_brp_br_error = aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 331:13] + assign io_i0_brp_br_start_error = aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 331:13] + assign io_i0_brp_prett = aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 331:13] + assign io_i0_brp_way = aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 331:13] + assign io_i0_brp_ret = aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 331:13] assign io_ifu_i0_bp_index = aln_ctl_ch_io_ifu_i0_bp_index; // @[el2_ifu.scala 332:22] assign io_ifu_i0_bp_fghr = aln_ctl_ch_io_ifu_i0_bp_fghr; // @[el2_ifu.scala 333:21] assign io_ifu_i0_bp_btag = aln_ctl_ch_io_ifu_i0_bp_btag; // @[el2_ifu.scala 334:21] @@ -45045,11 +45045,11 @@ module el2_ifu( assign bp_ctl_ch_io_ifc_fetch_addr_f = ifc_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 196:33] assign bp_ctl_ch_io_ifc_fetch_req_f = ifc_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 197:32] assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid = io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist = io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error = io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error = io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way = io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 198:34] - assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle = io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist = io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error = io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error = io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_way = io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 198:34] + assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle = io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 198:34] assign bp_ctl_ch_io_exu_i0_br_fghr_r = io_exu_i0_br_fghr_r; // @[el2_ifu.scala 199:33] assign bp_ctl_ch_io_exu_i0_br_index_r = io_exu_i0_br_index_r; // @[el2_ifu.scala 200:34] assign bp_ctl_ch_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 201:39] @@ -45118,13 +45118,13 @@ module el2_dec_ib_ctl( input [1:0] io_dbg_cmd_type, input [31:0] io_dbg_cmd_addr, input io_i0_brp_valid, - input [11:0] io_i0_brp_bits_toffset, - input [1:0] io_i0_brp_bits_hist, - input io_i0_brp_bits_br_error, - input io_i0_brp_bits_br_start_error, - input [30:0] io_i0_brp_bits_prett, - input io_i0_brp_bits_way, - input io_i0_brp_bits_ret, + input [11:0] io_i0_brp_toffset, + input [1:0] io_i0_brp_hist, + input io_i0_brp_br_error, + input io_i0_brp_br_start_error, + input [30:0] io_i0_brp_prett, + input io_i0_brp_way, + input io_i0_brp_ret, input [7:0] io_ifu_i0_bp_index, input [7:0] io_ifu_i0_bp_fghr, input [4:0] io_ifu_i0_bp_btag, @@ -45142,13 +45142,13 @@ module el2_dec_ib_ctl( output [30:0] io_dec_i0_pc_d, output io_dec_i0_pc4_d, output io_dec_i0_brp_valid, - output [11:0] io_dec_i0_brp_bits_toffset, - output [1:0] io_dec_i0_brp_bits_hist, - output io_dec_i0_brp_bits_br_error, - output io_dec_i0_brp_bits_br_start_error, - output [30:0] io_dec_i0_brp_bits_prett, - output io_dec_i0_brp_bits_way, - output io_dec_i0_brp_bits_ret, + output [11:0] io_dec_i0_brp_toffset, + output [1:0] io_dec_i0_brp_hist, + output io_dec_i0_brp_br_error, + output io_dec_i0_brp_br_start_error, + output [30:0] io_dec_i0_brp_prett, + output io_dec_i0_brp_way, + output io_dec_i0_brp_ret, output [7:0] io_dec_i0_bp_index, output [7:0] io_dec_i0_bp_fghr, output [4:0] io_dec_i0_bp_btag, @@ -45158,52 +45158,55 @@ module el2_dec_ib_ctl( output io_dec_debug_wdata_rs1_d, output io_dec_debug_fence_d ); - wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 66:60] - wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 66:41] - wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 67:38] - wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 67:36] - wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 68:36] - wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 70:55] - wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 70:37] - wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 71:37] - wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 72:55] - wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 72:37] - wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 73:37] - wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 75:40] - wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 76:40] + wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 31:60] + wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 31:41] + wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 32:38] + wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 32:36] + wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 33:36] + wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 35:55] + wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 35:37] + wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 36:37] + wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 37:55] + wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 37:37] + wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 38:37] + wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 40:40] + wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 41:40] wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58] - wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58] - wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58] - wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58] + wire [13:0] _T_12 = {3'h6,dreg,6'h33}; // @[Cat.scala 29:58] + wire [25:0] _T_14 = {dcsr,14'h2073}; // @[Cat.scala 29:58] + wire [24:0] _T_16 = {dcsr,13'h1073}; // @[Cat.scala 29:58] wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] - wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] - wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72] - wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 89:51] - assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 91:22] - assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 48:31] - assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 92:22] - assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 46:31] - assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 47:31] - assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec_ib_ctl.scala 49:31] - assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 50:31] - assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 51:31] - assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 52:31] - assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 45:31] - assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 43:31] - assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 44:31] - assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 86:28] - assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 89:24] + wire [13:0] _T_18 = debug_write_gpr ? _T_12 : 14'h0; // @[Mux.scala 27:72] + wire [25:0] _T_19 = debug_read_csr ? _T_14 : 26'h0; // @[Mux.scala 27:72] + wire [24:0] _T_20 = debug_write_csr ? _T_16 : 25'h0; // @[Mux.scala 27:72] + wire [31:0] _GEN_0 = {{18'd0}, _T_18}; // @[Mux.scala 27:72] + wire [31:0] _T_21 = _T_17 | _GEN_0; // @[Mux.scala 27:72] + wire [31:0] _GEN_1 = {{6'd0}, _T_19}; // @[Mux.scala 27:72] + wire [31:0] _T_22 = _T_21 | _GEN_1; // @[Mux.scala 27:72] + wire [31:0] _GEN_2 = {{7'd0}, _T_20}; // @[Mux.scala 27:72] + wire [31:0] ib0_debug_in = _T_22 | _GEN_2; // @[Mux.scala 27:72] + wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 54:51] + assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 56:22] + assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 13:31] + assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 57:22] + assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31] + assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31] + assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 14:31] + assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31] + assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31] + assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31] + assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 10:31] + assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 8:31] + assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 9:31] + assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 51:28] + assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 54:24] endmodule module el2_dec_dec_ctl( input [31:0] io_ins, @@ -45258,654 +45261,661 @@ module el2_dec_dec_ctl( output io_out_pm_alu, output io_out_legal ); - wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 72:27] - wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 72:42] - wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:53] - wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 72:39] - wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 72:68] - wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:78] - wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 73:51] - wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 73:51] - wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 73:90] - wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 73:90] - wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 73:55] - wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 74:37] - wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 74:37] - wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 73:94] - wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 74:76] - wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 74:76] - wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 74:41] - wire _T_45 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_49 = _T_45 & io_ins[13]; // @[el2_dec_dec_ctl.scala 75:38] - wire _T_50 = _T_49 & _T_18; // @[el2_dec_dec_ctl.scala 75:38] - wire _T_51 = _T_43 | _T_50; // @[el2_dec_dec_ctl.scala 74:80] - wire _T_57 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 75:76] - wire _T_58 = _T_57 & _T_18; // @[el2_dec_dec_ctl.scala 75:76] - wire _T_59 = _T_51 | _T_58; // @[el2_dec_dec_ctl.scala 75:42] - wire _T_64 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 76:37] - wire _T_65 = _T_64 & _T_18; // @[el2_dec_dec_ctl.scala 76:37] - wire _T_66 = _T_59 | _T_65; // @[el2_dec_dec_ctl.scala 75:80] - wire _T_72 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 76:75] - wire _T_73 = _T_72 & _T_18; // @[el2_dec_dec_ctl.scala 76:75] - wire _T_74 = _T_66 | _T_73; // @[el2_dec_dec_ctl.scala 76:41] - wire _T_79 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 77:37] - wire _T_80 = _T_79 & _T_18; // @[el2_dec_dec_ctl.scala 77:37] - wire _T_81 = _T_74 | _T_80; // @[el2_dec_dec_ctl.scala 76:79] - wire _T_87 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 77:75] - wire _T_88 = _T_87 & _T_18; // @[el2_dec_dec_ctl.scala 77:75] - wire _T_89 = _T_81 | _T_88; // @[el2_dec_dec_ctl.scala 77:41] - wire _T_94 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 78:37] - wire _T_95 = _T_94 & _T_18; // @[el2_dec_dec_ctl.scala 78:37] - wire _T_96 = _T_89 | _T_95; // @[el2_dec_dec_ctl.scala 77:79] - wire _T_98 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_100 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_101 = _T_98 & _T_100; // @[el2_dec_dec_ctl.scala 78:71] - wire _T_102 = _T_96 | _T_101; // @[el2_dec_dec_ctl.scala 78:41] - wire _T_104 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_107 = _T_104 & _T_18; // @[el2_dec_dec_ctl.scala 78:106] - wire _T_114 = io_ins[5] & _T_98; // @[el2_dec_dec_ctl.scala 79:48] - wire _T_115 = _T_114 & _T_18; // @[el2_dec_dec_ctl.scala 79:48] - wire _T_121 = _T_104 & io_ins[5]; // @[el2_dec_dec_ctl.scala 79:85] - wire _T_122 = _T_121 & _T_18; // @[el2_dec_dec_ctl.scala 79:85] - wire _T_130 = _T_101 & io_ins[2]; // @[el2_dec_dec_ctl.scala 80:50] - wire _T_137 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 80:90] - wire _T_138 = _T_137 & io_ins[4]; // @[el2_dec_dec_ctl.scala 80:90] - wire _T_139 = _T_138 & _T_18; // @[el2_dec_dec_ctl.scala 80:90] - wire _T_140 = _T_130 | _T_139; // @[el2_dec_dec_ctl.scala 80:54] - wire _T_144 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_147 = _T_16 & _T_144; // @[el2_dec_dec_ctl.scala 81:40] - wire _T_148 = _T_147 & io_ins[6]; // @[el2_dec_dec_ctl.scala 81:40] - wire _T_149 = _T_148 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:40] - wire _T_150 = _T_140 | _T_149; // @[el2_dec_dec_ctl.scala 80:94] - wire _T_158 = _T_144 & _T_9; // @[el2_dec_dec_ctl.scala 81:81] - wire _T_159 = _T_158 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:81] - wire _T_160 = _T_159 & _T_18; // @[el2_dec_dec_ctl.scala 81:81] - wire _T_166 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 82:28] - wire _T_169 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 82:55] - wire _T_170 = _T_166 | _T_169; // @[el2_dec_dec_ctl.scala 82:42] - wire _T_181 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 83:58] - wire _T_182 = _T_181 & _T_9; // @[el2_dec_dec_ctl.scala 83:58] - wire _T_183 = _T_182 & io_ins[4]; // @[el2_dec_dec_ctl.scala 83:58] - wire _T_187 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 84:29] - wire _T_190 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 84:53] - wire _T_196 = _T_9 & _T_100; // @[el2_dec_dec_ctl.scala 85:28] - wire _T_198 = _T_196 & io_ins[2]; // @[el2_dec_dec_ctl.scala 85:41] - wire _T_209 = _T_9 & _T_98; // @[el2_dec_dec_ctl.scala 86:50] - wire _T_224 = _T_104 & _T_98; // @[el2_dec_dec_ctl.scala 88:49] - wire _T_236 = _T_19 & _T_144; // @[el2_dec_dec_ctl.scala 89:57] - wire _T_237 = _T_236 & _T_9; // @[el2_dec_dec_ctl.scala 89:57] - wire _T_238 = _T_237 & io_ins[4]; // @[el2_dec_dec_ctl.scala 89:57] - wire _T_246 = _T_238 | _T_198; // @[el2_dec_dec_ctl.scala 89:61] - wire _T_248 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_262 = _T_248 & _T_4; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_263 = _T_262 & _T_14; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_264 = _T_263 & _T_16; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_265 = _T_264 & _T_144; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_266 = _T_265 & _T_104; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_267 = _T_266 & io_ins[4]; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_268 = _T_267 & _T_18; // @[el2_dec_dec_ctl.scala 90:56] - wire _T_279 = io_ins[30] & _T_144; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_280 = _T_279 & _T_104; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_281 = _T_280 & io_ins[5]; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_282 = _T_281 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_283 = _T_282 & _T_18; // @[el2_dec_dec_ctl.scala 91:57] - wire _T_294 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_295 = _T_294 & io_ins[13]; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_296 = _T_295 & _T_104; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_297 = _T_296 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_298 = _T_297 & _T_18; // @[el2_dec_dec_ctl.scala 91:105] - wire _T_299 = _T_283 | _T_298; // @[el2_dec_dec_ctl.scala 91:61] - wire _T_308 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_309 = _T_308 & _T_9; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_310 = _T_309 & io_ins[4]; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_311 = _T_310 & _T_18; // @[el2_dec_dec_ctl.scala 92:43] - wire _T_312 = _T_299 | _T_311; // @[el2_dec_dec_ctl.scala 91:109] - wire _T_318 = io_ins[6] & _T_98; // @[el2_dec_dec_ctl.scala 92:80] - wire _T_319 = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 92:80] - wire _T_328 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_329 = _T_328 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_330 = _T_329 & _T_9; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_331 = _T_330 & _T_18; // @[el2_dec_dec_ctl.scala 93:56] - wire _T_341 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_342 = _T_341 & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_343 = _T_342 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_344 = _T_343 & _T_104; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_345 = _T_344 & _T_18; // @[el2_dec_dec_ctl.scala 93:104] - wire _T_350 = _T_104 & io_ins[3]; // @[el2_dec_dec_ctl.scala 94:45] - wire _T_363 = _T_342 & _T_144; // @[el2_dec_dec_ctl.scala 94:94] - wire _T_364 = _T_363 & _T_104; // @[el2_dec_dec_ctl.scala 94:94] - wire _T_365 = _T_364 & _T_18; // @[el2_dec_dec_ctl.scala 94:94] - wire _T_366 = _T_350 | _T_365; // @[el2_dec_dec_ctl.scala 94:49] - wire _T_370 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 95:34] - wire _T_371 = _T_370 & io_ins[2]; // @[el2_dec_dec_ctl.scala 95:34] - wire _T_372 = _T_366 | _T_371; // @[el2_dec_dec_ctl.scala 94:98] - wire _T_382 = _T_372 | _T_149; // @[el2_dec_dec_ctl.scala 95:38] - wire _T_392 = _T_328 & _T_144; // @[el2_dec_dec_ctl.scala 96:44] - wire _T_393 = _T_392 & _T_9; // @[el2_dec_dec_ctl.scala 96:44] - wire _T_394 = _T_393 & _T_18; // @[el2_dec_dec_ctl.scala 96:44] - wire _T_407 = _T_341 & _T_16; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_408 = _T_407 & _T_144; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_409 = _T_408 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_410 = _T_409 & _T_18; // @[el2_dec_dec_ctl.scala 97:61] - wire _T_421 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_422 = _T_421 & _T_144; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_423 = _T_422 & _T_9; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_424 = _T_423 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_425 = _T_424 & _T_18; // @[el2_dec_dec_ctl.scala 97:109] - wire _T_440 = _T_294 & _T_16; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_441 = _T_440 & io_ins[12]; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_442 = _T_441 & _T_104; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_443 = _T_442 & io_ins[4]; // @[el2_dec_dec_ctl.scala 98:63] - wire _T_454 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_455 = _T_454 & io_ins[12]; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_456 = _T_455 & _T_104; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_457 = _T_456 & io_ins[4]; // @[el2_dec_dec_ctl.scala 99:58] - wire _T_473 = _T_262 & io_ins[14]; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_474 = _T_473 & _T_16; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_475 = _T_474 & io_ins[12]; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_476 = _T_475 & _T_104; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_477 = _T_476 & io_ins[4]; // @[el2_dec_dec_ctl.scala 100:66] - wire _T_492 = _T_295 & io_ins[12]; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_493 = _T_492 & _T_104; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_494 = _T_493 & io_ins[4]; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_495 = _T_494 & _T_18; // @[el2_dec_dec_ctl.scala 101:62] - wire _T_518 = _T_308 & io_ins[12]; // @[el2_dec_dec_ctl.scala 102:59] - wire _T_519 = _T_518 & _T_9; // @[el2_dec_dec_ctl.scala 102:59] - wire _T_520 = _T_519 & _T_18; // @[el2_dec_dec_ctl.scala 102:59] - wire _T_527 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 102:99] - wire _T_528 = _T_527 & _T_98; // @[el2_dec_dec_ctl.scala 102:99] - wire _T_529 = _T_528 & _T_18; // @[el2_dec_dec_ctl.scala 102:99] - wire _T_530 = _T_520 | _T_529; // @[el2_dec_dec_ctl.scala 102:63] - wire _T_536 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 103:37] - wire _T_537 = _T_536 & _T_98; // @[el2_dec_dec_ctl.scala 103:37] - wire _T_538 = _T_530 | _T_537; // @[el2_dec_dec_ctl.scala 102:103] - wire _T_553 = _T_493 & _T_18; // @[el2_dec_dec_ctl.scala 103:86] - wire _T_554 = _T_538 | _T_553; // @[el2_dec_dec_ctl.scala 103:41] - wire _T_563 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_564 = _T_563 & io_ins[12]; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_565 = _T_564 & _T_104; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_566 = _T_565 & io_ins[5]; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_567 = _T_566 & _T_18; // @[el2_dec_dec_ctl.scala 104:45] - wire _T_585 = _T_14 & _T_144; // @[el2_dec_dec_ctl.scala 106:56] - wire _T_586 = _T_585 & io_ins[6]; // @[el2_dec_dec_ctl.scala 106:56] - wire _T_587 = _T_586 & _T_98; // @[el2_dec_dec_ctl.scala 106:56] - wire _T_597 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 107:55] - wire _T_598 = _T_597 & io_ins[6]; // @[el2_dec_dec_ctl.scala 107:55] - wire _T_599 = _T_598 & _T_98; // @[el2_dec_dec_ctl.scala 107:55] - wire _T_608 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 108:54] - wire _T_609 = _T_608 & io_ins[5]; // @[el2_dec_dec_ctl.scala 108:54] - wire _T_610 = _T_609 & _T_98; // @[el2_dec_dec_ctl.scala 108:54] - wire _T_620 = io_ins[14] & _T_144; // @[el2_dec_dec_ctl.scala 109:55] - wire _T_621 = _T_620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 109:55] - wire _T_622 = _T_621 & _T_98; // @[el2_dec_dec_ctl.scala 109:55] - wire _T_638 = _T_147 & _T_104; // @[el2_dec_dec_ctl.scala 111:56] - wire _T_639 = _T_638 & _T_98; // @[el2_dec_dec_ctl.scala 111:56] - wire _T_648 = io_ins[12] & _T_104; // @[el2_dec_dec_ctl.scala 112:53] - wire _T_649 = _T_648 & _T_98; // @[el2_dec_dec_ctl.scala 112:53] - wire _T_656 = io_ins[13] & _T_104; // @[el2_dec_dec_ctl.scala 113:50] - wire _T_662 = _T_527 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:52] - wire _T_666 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 114:87] - wire _T_667 = _T_666 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:87] - wire _T_668 = _T_662 | _T_667; // @[el2_dec_dec_ctl.scala 114:56] - wire _T_672 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:34] - wire _T_673 = _T_672 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:34] - wire _T_674 = _T_668 | _T_673; // @[el2_dec_dec_ctl.scala 114:91] - wire _T_678 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:69] - wire _T_679 = _T_678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:69] - wire _T_680 = _T_674 | _T_679; // @[el2_dec_dec_ctl.scala 115:38] - wire _T_684 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:105] - wire _T_685 = _T_684 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:105] - wire _T_686 = _T_680 | _T_685; // @[el2_dec_dec_ctl.scala 115:73] - wire _T_690 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 116:35] - wire _T_691 = _T_690 & io_ins[4]; // @[el2_dec_dec_ctl.scala 116:35] - wire _T_699 = _T_94 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:57] - wire _T_700 = _T_699 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:57] - wire _T_701 = _T_700 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:57] - wire _T_708 = _T_79 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:99] - wire _T_709 = _T_708 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:99] - wire _T_710 = _T_709 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:99] - wire _T_711 = _T_701 | _T_710; // @[el2_dec_dec_ctl.scala 117:61] - wire _T_718 = _T_64 & io_ins[12]; // @[el2_dec_dec_ctl.scala 118:41] - wire _T_719 = _T_718 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:41] - wire _T_720 = _T_719 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:41] - wire _T_721 = _T_711 | _T_720; // @[el2_dec_dec_ctl.scala 117:103] - wire _T_727 = io_ins[18] & _T_144; // @[el2_dec_dec_ctl.scala 118:81] - wire _T_728 = _T_727 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:81] - wire _T_729 = _T_728 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:81] - wire _T_730 = _T_721 | _T_729; // @[el2_dec_dec_ctl.scala 118:45] - wire _T_736 = io_ins[19] & _T_144; // @[el2_dec_dec_ctl.scala 119:39] - wire _T_737 = _T_736 & io_ins[6]; // @[el2_dec_dec_ctl.scala 119:39] - wire _T_738 = _T_737 & io_ins[4]; // @[el2_dec_dec_ctl.scala 119:39] - wire _T_746 = _T_181 & io_ins[6]; // @[el2_dec_dec_ctl.scala 120:57] - wire _T_754 = _T_421 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:55] - wire _T_755 = _T_754 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:55] - wire _T_760 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 121:94] - wire _T_761 = _T_760 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:94] - wire _T_762 = _T_761 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:94] - wire _T_763 = _T_755 | _T_762; // @[el2_dec_dec_ctl.scala 121:59] - wire _T_768 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:38] - wire _T_769 = _T_768 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:38] - wire _T_770 = _T_769 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:38] - wire _T_771 = _T_763 | _T_770; // @[el2_dec_dec_ctl.scala 121:98] - wire _T_776 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:77] - wire _T_777 = _T_776 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:77] - wire _T_778 = _T_777 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:77] - wire _T_779 = _T_771 | _T_778; // @[el2_dec_dec_ctl.scala 122:42] - wire _T_784 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:38] - wire _T_785 = _T_784 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:38] - wire _T_786 = _T_785 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:38] - wire _T_787 = _T_779 | _T_786; // @[el2_dec_dec_ctl.scala 122:81] - wire _T_792 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:77] - wire _T_793 = _T_792 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:77] - wire _T_794 = _T_793 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:77] - wire _T_801 = io_ins[15] & _T_144; // @[el2_dec_dec_ctl.scala 124:55] - wire _T_802 = _T_801 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:55] - wire _T_803 = _T_802 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:55] - wire _T_809 = io_ins[16] & _T_144; // @[el2_dec_dec_ctl.scala 124:95] - wire _T_810 = _T_809 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:95] - wire _T_811 = _T_810 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:95] - wire _T_812 = _T_803 | _T_811; // @[el2_dec_dec_ctl.scala 124:59] - wire _T_818 = io_ins[17] & _T_144; // @[el2_dec_dec_ctl.scala 125:39] - wire _T_819 = _T_818 & io_ins[6]; // @[el2_dec_dec_ctl.scala 125:39] - wire _T_820 = _T_819 & io_ins[4]; // @[el2_dec_dec_ctl.scala 125:39] - wire _T_821 = _T_812 | _T_820; // @[el2_dec_dec_ctl.scala 124:99] - wire _T_830 = _T_821 | _T_729; // @[el2_dec_dec_ctl.scala 125:43] - wire _T_841 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_849 = _T_841 & io_ins[20]; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_850 = _T_849 & _T_16; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_851 = _T_850 & _T_144; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_852 = _T_851 & io_ins[6]; // @[el2_dec_dec_ctl.scala 127:62] - wire _T_855 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_857 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_864 = _T_855 & _T_857; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_865 = _T_864 & _T_16; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_866 = _T_865 & _T_144; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_867 = _T_866 & io_ins[6]; // @[el2_dec_dec_ctl.scala 128:62] - wire _T_876 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 129:56] - wire _T_877 = _T_876 & _T_144; // @[el2_dec_dec_ctl.scala 129:56] - wire _T_878 = _T_877 & io_ins[6]; // @[el2_dec_dec_ctl.scala 129:56] - wire _T_889 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_890 = _T_889 & _T_104; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_891 = _T_890 & io_ins[5]; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_892 = _T_891 & io_ins[4]; // @[el2_dec_dec_ctl.scala 130:57] - wire _T_907 = _T_889 & io_ins[13]; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_908 = _T_907 & _T_144; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_909 = _T_908 & _T_104; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_910 = _T_909 & io_ins[5]; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_911 = _T_910 & io_ins[4]; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_912 = _T_911 & _T_18; // @[el2_dec_dec_ctl.scala 131:69] - wire _T_925 = _T_889 & _T_16; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_926 = _T_925 & io_ins[12]; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_927 = _T_926 & _T_104; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_928 = _T_927 & io_ins[4]; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_929 = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 132:50] - wire _T_961 = _T_925 & _T_144; // @[el2_dec_dec_ctl.scala 134:62] - wire _T_962 = _T_961 & io_ins[5]; // @[el2_dec_dec_ctl.scala 134:62] - wire _T_963 = _T_962 & io_ins[4]; // @[el2_dec_dec_ctl.scala 134:62] - wire _T_973 = _T_563 & _T_104; // @[el2_dec_dec_ctl.scala 135:54] - wire _T_974 = _T_973 & io_ins[5]; // @[el2_dec_dec_ctl.scala 135:54] - wire _T_985 = _T_563 & io_ins[13]; // @[el2_dec_dec_ctl.scala 136:57] - wire _T_986 = _T_985 & _T_104; // @[el2_dec_dec_ctl.scala 136:57] - wire _T_987 = _T_986 & io_ins[5]; // @[el2_dec_dec_ctl.scala 136:57] - wire _T_992 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:47] - wire _T_997 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 138:52] - wire _T_998 = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:52] - wire _T_1006 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1007 = _T_1006 & _T_16; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1008 = _T_1007 & _T_144; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1009 = _T_1008 & io_ins[4]; // @[el2_dec_dec_ctl.scala 139:59] - wire _T_1013 = _T_1009 | _T_190; // @[el2_dec_dec_ctl.scala 139:63] - wire _T_1019 = _T_4 & _T_104; // @[el2_dec_dec_ctl.scala 140:37] - wire _T_1020 = _T_1019 & io_ins[4]; // @[el2_dec_dec_ctl.scala 140:37] - wire _T_1021 = _T_1013 | _T_1020; // @[el2_dec_dec_ctl.scala 139:96] - wire _T_1037 = _T_87 & io_ins[6]; // @[el2_dec_dec_ctl.scala 141:88] - wire _T_1038 = _T_1037 & io_ins[4]; // @[el2_dec_dec_ctl.scala 141:88] - wire _T_1039 = _T_992 | _T_1038; // @[el2_dec_dec_ctl.scala 141:53] - wire _T_1046 = _T_72 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:38] - wire _T_1047 = _T_1046 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:38] - wire _T_1048 = _T_1039 | _T_1047; // @[el2_dec_dec_ctl.scala 141:92] - wire _T_1055 = _T_57 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:77] - wire _T_1056 = _T_1055 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:77] - wire _T_1057 = _T_1048 | _T_1056; // @[el2_dec_dec_ctl.scala 142:42] - wire _T_1066 = _T_1057 | _T_1056; // @[el2_dec_dec_ctl.scala 142:81] - wire _T_1073 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 143:78] - wire _T_1074 = _T_1073 & io_ins[4]; // @[el2_dec_dec_ctl.scala 143:78] - wire _T_1075 = _T_1066 | _T_1074; // @[el2_dec_dec_ctl.scala 143:42] - wire _T_1082 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:39] - wire _T_1083 = _T_1082 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:39] - wire _T_1084 = _T_1075 | _T_1083; // @[el2_dec_dec_ctl.scala 143:82] - wire _T_1090 = _T_94 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:78] - wire _T_1091 = _T_1090 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:78] - wire _T_1092 = _T_1084 | _T_1091; // @[el2_dec_dec_ctl.scala 144:43] - wire _T_1098 = _T_79 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:38] - wire _T_1099 = _T_1098 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:38] - wire _T_1100 = _T_1092 | _T_1099; // @[el2_dec_dec_ctl.scala 144:82] - wire _T_1106 = _T_64 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:77] - wire _T_1107 = _T_1106 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:77] - wire _T_1108 = _T_1100 | _T_1107; // @[el2_dec_dec_ctl.scala 145:42] - wire _T_1113 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 146:38] - wire _T_1114 = _T_1113 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:38] - wire _T_1115 = _T_1114 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:38] - wire _T_1116 = _T_1108 | _T_1115; // @[el2_dec_dec_ctl.scala 145:81] - wire _T_1122 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:77] - wire _T_1123 = _T_1122 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:77] - wire _T_1139 = _T_841 & _T_16; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1140 = _T_1139 & _T_144; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1141 = _T_1140 & io_ins[6]; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1142 = _T_1141 & io_ins[4]; // @[el2_dec_dec_ctl.scala 147:98] - wire _T_1143 = _T_998 | _T_1142; // @[el2_dec_dec_ctl.scala 147:57] - wire _T_1152 = _T_1143 | _T_1038; // @[el2_dec_dec_ctl.scala 147:102] - wire _T_1161 = _T_1152 | _T_1047; // @[el2_dec_dec_ctl.scala 148:42] - wire _T_1170 = _T_1161 | _T_1056; // @[el2_dec_dec_ctl.scala 148:81] - wire _T_1179 = _T_1170 | _T_1074; // @[el2_dec_dec_ctl.scala 149:42] - wire _T_1188 = _T_1179 | _T_1083; // @[el2_dec_dec_ctl.scala 149:82] - wire _T_1196 = _T_1188 | _T_1091; // @[el2_dec_dec_ctl.scala 150:43] - wire _T_1204 = _T_1196 | _T_1099; // @[el2_dec_dec_ctl.scala 150:82] - wire _T_1212 = _T_1204 | _T_1107; // @[el2_dec_dec_ctl.scala 151:42] - wire _T_1220 = _T_1212 | _T_1115; // @[el2_dec_dec_ctl.scala 151:81] - wire _T_1230 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1236 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1238 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1242 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1244 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1251 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1255 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1257 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1259 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1263 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1265 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1267 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1269 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1271 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1281 = ~io_ins[0]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1282 = _T_1230 & _T_248; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1283 = _T_1282 & io_ins[29]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1284 = _T_1283 & io_ins[28]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1285 = _T_1284 & _T_1236; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1286 = _T_1285 & _T_1238; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1287 = _T_1286 & _T_4; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1288 = _T_1287 & _T_1242; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1289 = _T_1288 & _T_1244; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1290 = _T_1289 & _T_841; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1291 = _T_1290 & io_ins[21]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1292 = _T_1291 & _T_857; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1293 = _T_1292 & _T_1251; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1294 = _T_1293 & _T_45; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1295 = _T_1294 & _T_1255; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1296 = _T_1295 & _T_1257; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1297 = _T_1296 & _T_1259; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1298 = _T_1297 & _T_14; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1299 = _T_1298 & _T_1263; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1300 = _T_1299 & _T_1265; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1301 = _T_1300 & _T_1267; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1302 = _T_1301 & _T_1269; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1303 = _T_1302 & _T_1271; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1304 = _T_1303 & io_ins[6]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1305 = _T_1304 & io_ins[5]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1306 = _T_1305 & io_ins[4]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1307 = _T_1306 & _T_100; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1308 = _T_1307 & _T_18; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1309 = _T_1308 & io_ins[1]; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1310 = _T_1309 & _T_1281; // @[el2_dec_dec_ctl.scala 153:144] - wire _T_1316 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1365 = _T_1282 & _T_1316; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1366 = _T_1365 & io_ins[28]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1367 = _T_1366 & _T_1236; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1368 = _T_1367 & _T_1238; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1369 = _T_1368 & _T_4; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1370 = _T_1369 & _T_1242; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1371 = _T_1370 & _T_1244; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1372 = _T_1371 & io_ins[22]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1373 = _T_1372 & _T_855; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1374 = _T_1373 & io_ins[20]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1375 = _T_1374 & _T_1251; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1376 = _T_1375 & _T_45; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1377 = _T_1376 & _T_1255; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1378 = _T_1377 & _T_1257; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1379 = _T_1378 & _T_1259; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1380 = _T_1379 & _T_14; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1381 = _T_1380 & _T_1263; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1382 = _T_1381 & _T_1265; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1383 = _T_1382 & _T_1267; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1384 = _T_1383 & _T_1269; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1385 = _T_1384 & _T_1271; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1386 = _T_1385 & io_ins[6]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1387 = _T_1386 & io_ins[5]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1388 = _T_1387 & io_ins[4]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1389 = _T_1388 & _T_100; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1390 = _T_1389 & _T_18; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1391 = _T_1390 & io_ins[1]; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1392 = _T_1391 & _T_1281; // @[el2_dec_dec_ctl.scala 154:130] - wire _T_1393 = _T_1310 | _T_1392; // @[el2_dec_dec_ctl.scala 153:148] - wire _T_1401 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 67:45] - wire _T_1449 = _T_1365 & _T_1401; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1450 = _T_1449 & _T_1236; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1451 = _T_1450 & _T_1238; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1452 = _T_1451 & _T_4; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1453 = _T_1452 & _T_1242; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1454 = _T_1453 & _T_1244; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1455 = _T_1454 & _T_841; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1456 = _T_1455 & _T_855; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1457 = _T_1456 & _T_1251; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1458 = _T_1457 & _T_45; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1459 = _T_1458 & _T_1255; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1460 = _T_1459 & _T_1257; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1461 = _T_1460 & _T_1259; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1462 = _T_1461 & _T_14; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1463 = _T_1462 & _T_1263; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1464 = _T_1463 & _T_1265; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1465 = _T_1464 & _T_1267; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1466 = _T_1465 & _T_1269; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1467 = _T_1466 & _T_1271; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1468 = _T_1467 & io_ins[5]; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1469 = _T_1468 & io_ins[4]; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1470 = _T_1469 & _T_100; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1471 = _T_1470 & _T_18; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1472 = _T_1471 & io_ins[1]; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1473 = _T_1472 & _T_1281; // @[el2_dec_dec_ctl.scala 155:127] - wire _T_1474 = _T_1393 | _T_1473; // @[el2_dec_dec_ctl.scala 154:134] - wire _T_1503 = _T_1452 & _T_104; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1504 = _T_1503 & io_ins[4]; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1505 = _T_1504 & _T_100; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1506 = _T_1505 & io_ins[1]; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1507 = _T_1506 & _T_1281; // @[el2_dec_dec_ctl.scala 156:68] - wire _T_1508 = _T_1474 | _T_1507; // @[el2_dec_dec_ctl.scala 155:131] - wire _T_1536 = _T_1230 & _T_1316; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1537 = _T_1536 & _T_1401; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1538 = _T_1537 & _T_1236; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1539 = _T_1538 & _T_1238; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1540 = _T_1539 & _T_4; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1541 = _T_1540 & _T_14; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1542 = _T_1541 & _T_16; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1543 = _T_1542 & _T_144; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1544 = _T_1543 & _T_104; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1545 = _T_1544 & _T_100; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1546 = _T_1545 & _T_18; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1547 = _T_1546 & io_ins[1]; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1548 = _T_1547 & _T_1281; // @[el2_dec_dec_ctl.scala 157:77] - wire _T_1549 = _T_1508 | _T_1548; // @[el2_dec_dec_ctl.scala 156:72] - wire _T_1579 = _T_1540 & io_ins[14]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1580 = _T_1579 & _T_16; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1581 = _T_1580 & io_ins[12]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1582 = _T_1581 & _T_104; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1583 = _T_1582 & io_ins[4]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1584 = _T_1583 & _T_100; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1585 = _T_1584 & io_ins[1]; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1586 = _T_1585 & _T_1281; // @[el2_dec_dec_ctl.scala 158:74] - wire _T_1587 = _T_1549 | _T_1586; // @[el2_dec_dec_ctl.scala 157:81] - wire _T_1614 = _T_1451 & _T_104; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1615 = _T_1614 & io_ins[5]; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1616 = _T_1615 & io_ins[4]; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1617 = _T_1616 & _T_100; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1618 = _T_1617 & io_ins[1]; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1619 = _T_1618 & _T_1281; // @[el2_dec_dec_ctl.scala 159:66] - wire _T_1620 = _T_1587 | _T_1619; // @[el2_dec_dec_ctl.scala 158:78] - wire _T_1638 = _T_236 & io_ins[6]; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1640 = _T_1639 & _T_98; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1641 = _T_1640 & _T_100; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1642 = _T_1641 & io_ins[1]; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1643 = _T_1642 & _T_1281; // @[el2_dec_dec_ctl.scala 160:54] - wire _T_1644 = _T_1620 | _T_1643; // @[el2_dec_dec_ctl.scala 159:70] - wire _T_1657 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1658 = _T_1657 & io_ins[5]; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1659 = _T_1658 & _T_98; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1660 = _T_1659 & _T_100; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1661 = _T_1660 & _T_18; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1662 = _T_1661 & io_ins[1]; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1663 = _T_1662 & _T_1281; // @[el2_dec_dec_ctl.scala 161:48] - wire _T_1664 = _T_1644 | _T_1663; // @[el2_dec_dec_ctl.scala 160:58] - wire _T_1677 = _T_144 & _T_104; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1678 = _T_1677 & _T_9; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1679 = _T_1678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1680 = _T_1679 & _T_100; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1681 = _T_1680 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1682 = _T_1681 & _T_1281; // @[el2_dec_dec_ctl.scala 162:47] - wire _T_1683 = _T_1664 | _T_1682; // @[el2_dec_dec_ctl.scala 161:52] - wire _T_1699 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1700 = _T_1699 & _T_98; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1701 = _T_1700 & _T_100; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1702 = _T_1701 & _T_18; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1703 = _T_1702 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1704 = _T_1703 & _T_1281; // @[el2_dec_dec_ctl.scala 162:99] - wire _T_1705 = _T_1683 | _T_1704; // @[el2_dec_dec_ctl.scala 162:51] - wire _T_1717 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1718 = _T_1717 & io_ins[5]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1719 = _T_1718 & io_ins[4]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1720 = _T_1719 & _T_100; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1721 = _T_1720 & _T_18; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1722 = _T_1721 & io_ins[1]; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1723 = _T_1722 & _T_1281; // @[el2_dec_dec_ctl.scala 163:47] - wire _T_1724 = _T_1705 | _T_1723; // @[el2_dec_dec_ctl.scala 162:103] - wire _T_1796 = _T_1456 & _T_857; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1797 = _T_1796 & _T_1251; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1798 = _T_1797 & _T_45; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1799 = _T_1798 & _T_1255; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1800 = _T_1799 & _T_1257; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1801 = _T_1800 & _T_1259; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1802 = _T_1801 & _T_14; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1803 = _T_1802 & _T_16; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1804 = _T_1803 & _T_144; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1805 = _T_1804 & _T_1263; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1806 = _T_1805 & _T_1265; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1807 = _T_1806 & _T_1267; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1808 = _T_1807 & _T_1269; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1809 = _T_1808 & _T_1271; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1810 = _T_1809 & _T_104; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1811 = _T_1810 & _T_9; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1812 = _T_1811 & _T_98; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1813 = _T_1812 & io_ins[3]; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1814 = _T_1813 & io_ins[2]; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1815 = _T_1814 & io_ins[1]; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1816 = _T_1815 & _T_1281; // @[el2_dec_dec_ctl.scala 164:142] - wire _T_1817 = _T_1724 | _T_1816; // @[el2_dec_dec_ctl.scala 163:51] - wire _T_1866 = _T_1449 & _T_1251; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1867 = _T_1866 & _T_45; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1868 = _T_1867 & _T_1255; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1869 = _T_1868 & _T_1257; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1870 = _T_1869 & _T_1259; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1871 = _T_1870 & _T_14; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1872 = _T_1871 & _T_16; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1873 = _T_1872 & _T_144; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1874 = _T_1873 & _T_1263; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1875 = _T_1874 & _T_1265; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1876 = _T_1875 & _T_1267; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1877 = _T_1876 & _T_1269; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1878 = _T_1877 & _T_1271; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1879 = _T_1878 & _T_104; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1880 = _T_1879 & _T_9; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1881 = _T_1880 & _T_98; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1882 = _T_1881 & io_ins[3]; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1883 = _T_1882 & io_ins[2]; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1884 = _T_1883 & io_ins[1]; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1885 = _T_1884 & _T_1281; // @[el2_dec_dec_ctl.scala 165:110] - wire _T_1886 = _T_1817 | _T_1885; // @[el2_dec_dec_ctl.scala 164:146] - wire _T_1902 = _T_16 & _T_104; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1903 = _T_1902 & _T_9; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1904 = _T_1903 & _T_98; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1905 = _T_1904 & _T_100; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1906 = _T_1905 & _T_18; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1907 = _T_1906 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1908 = _T_1907 & _T_1281; // @[el2_dec_dec_ctl.scala 166:51] - wire _T_1909 = _T_1886 | _T_1908; // @[el2_dec_dec_ctl.scala 165:114] - wire _T_1919 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1920 = _T_1919 & _T_98; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1921 = _T_1920 & io_ins[3]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1922 = _T_1921 & io_ins[2]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1923 = _T_1922 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1924 = _T_1923 & _T_1281; // @[el2_dec_dec_ctl.scala 166:95] - wire _T_1925 = _T_1909 | _T_1924; // @[el2_dec_dec_ctl.scala 166:55] - wire _T_1938 = _T_656 & _T_9; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1939 = _T_1938 & io_ins[4]; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1940 = _T_1939 & _T_100; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1941 = _T_1940 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1942 = _T_1941 & _T_1281; // @[el2_dec_dec_ctl.scala 167:46] - wire _T_1943 = _T_1925 | _T_1942; // @[el2_dec_dec_ctl.scala 166:99] - wire _T_1960 = _T_585 & _T_104; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1961 = _T_1960 & _T_98; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1962 = _T_1961 & _T_100; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1963 = _T_1962 & _T_18; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99] - wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50] - wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43] - wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43] - assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14] - assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14] - assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14] - assign io_out_imm12 = _T_150 | _T_160; // @[el2_dec_dec_ctl.scala 80:16] - assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13] - assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17] - assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16] - assign io_out_pc = _T_198 | _T_187; // @[el2_dec_dec_ctl.scala 85:13] - assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15] - assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16] - assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14] - assign io_out_add = _T_246 | _T_268; // @[el2_dec_dec_ctl.scala 89:14] - assign io_out_sub = _T_312 | _T_319; // @[el2_dec_dec_ctl.scala 91:14] - assign io_out_land = _T_331 | _T_345; // @[el2_dec_dec_ctl.scala 93:15] - assign io_out_lor = _T_382 | _T_394; // @[el2_dec_dec_ctl.scala 94:14] - assign io_out_lxor = _T_410 | _T_425; // @[el2_dec_dec_ctl.scala 97:15] - assign io_out_sll = _T_443 & _T_18; // @[el2_dec_dec_ctl.scala 98:14] - assign io_out_sra = _T_457 & _T_18; // @[el2_dec_dec_ctl.scala 99:14] - assign io_out_srl = _T_477 & _T_18; // @[el2_dec_dec_ctl.scala 100:14] - assign io_out_slt = _T_495 | _T_311; // @[el2_dec_dec_ctl.scala 101:14] - assign io_out_unsign = _T_554 | _T_567; // @[el2_dec_dec_ctl.scala 102:17] - assign io_out_condbr = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 105:17] - assign io_out_beq = _T_587 & _T_18; // @[el2_dec_dec_ctl.scala 106:14] - assign io_out_bne = _T_599 & _T_18; // @[el2_dec_dec_ctl.scala 107:14] - assign io_out_bge = _T_610 & _T_18; // @[el2_dec_dec_ctl.scala 108:14] - assign io_out_blt = _T_622 & _T_18; // @[el2_dec_dec_ctl.scala 109:14] - assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 110:14] - assign io_out_by = _T_639 & _T_18; // @[el2_dec_dec_ctl.scala 111:13] - assign io_out_half = _T_649 & _T_18; // @[el2_dec_dec_ctl.scala 112:15] - assign io_out_word = _T_656 & _T_98; // @[el2_dec_dec_ctl.scala 113:15] - assign io_out_csr_read = _T_686 | _T_691; // @[el2_dec_dec_ctl.scala 114:19] - assign io_out_csr_clr = _T_730 | _T_738; // @[el2_dec_dec_ctl.scala 117:18] - assign io_out_csr_set = _T_830 | _T_738; // @[el2_dec_dec_ctl.scala 124:18] - assign io_out_csr_write = _T_746 & io_ins[4]; // @[el2_dec_dec_ctl.scala 120:20] - assign io_out_csr_imm = _T_787 | _T_794; // @[el2_dec_dec_ctl.scala 121:18] - assign io_out_presync = _T_1116 | _T_1123; // @[el2_dec_dec_ctl.scala 141:18] - assign io_out_postsync = _T_1220 | _T_1123; // @[el2_dec_dec_ctl.scala 147:19] - assign io_out_ebreak = _T_852 & io_ins[4]; // @[el2_dec_dec_ctl.scala 127:17] - assign io_out_ecall = _T_867 & io_ins[4]; // @[el2_dec_dec_ctl.scala 128:16] - assign io_out_mret = _T_878 & io_ins[4]; // @[el2_dec_dec_ctl.scala 129:15] - assign io_out_mul = _T_892 & _T_18; // @[el2_dec_dec_ctl.scala 130:14] - assign io_out_rs1_sign = _T_912 | _T_929; // @[el2_dec_dec_ctl.scala 131:19] - assign io_out_rs2_sign = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 133:19] - assign io_out_low = _T_963 & _T_18; // @[el2_dec_dec_ctl.scala 134:14] - assign io_out_div = _T_974 & _T_18; // @[el2_dec_dec_ctl.scala 135:14] - assign io_out_rem = _T_987 & _T_18; // @[el2_dec_dec_ctl.scala 136:14] - assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16] - assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18] - assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17] - assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16] + wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 20:27] + wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 20:42] + wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:53] + wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 20:39] + wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 20:68] + wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 20:78] + wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 21:43] + wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 21:70] + wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 22:29] + wire _T_48 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_49 = _T_48 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_50 = _T_43 | _T_49; // @[el2_dec_dec_ctl.scala 22:56] + wire _T_56 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_57 = _T_56 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_58 = _T_50 | _T_57; // @[el2_dec_dec_ctl.scala 23:29] + wire _T_63 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_64 = _T_63 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_65 = _T_58 | _T_64; // @[el2_dec_dec_ctl.scala 23:55] + wire _T_71 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_72 = _T_71 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_73 = _T_65 | _T_72; // @[el2_dec_dec_ctl.scala 24:29] + wire _T_78 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_79 = _T_78 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_80 = _T_73 | _T_79; // @[el2_dec_dec_ctl.scala 24:55] + wire _T_86 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_87 = _T_86 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_88 = _T_80 | _T_87; // @[el2_dec_dec_ctl.scala 25:29] + wire _T_93 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_94 = _T_93 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_95 = _T_88 | _T_94; // @[el2_dec_dec_ctl.scala 25:55] + wire _T_97 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_99 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_100 = _T_97 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_101 = _T_95 | _T_100; // @[el2_dec_dec_ctl.scala 26:29] + wire _T_103 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_106 = _T_103 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_113 = io_ins[5] & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_114 = _T_113 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_120 = _T_103 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_121 = _T_120 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_129 = _T_100 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_136 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_137 = _T_136 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_138 = _T_137 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_139 = _T_129 | _T_138; // @[el2_dec_dec_ctl.scala 28:42] + wire _T_143 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_146 = _T_16 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_147 = _T_146 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_148 = _T_147 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_149 = _T_139 | _T_148; // @[el2_dec_dec_ctl.scala 28:70] + wire _T_157 = _T_143 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_158 = _T_157 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_159 = _T_158 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_165 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 30:28] + wire _T_168 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 30:55] + wire _T_169 = _T_165 | _T_168; // @[el2_dec_dec_ctl.scala 30:42] + wire _T_180 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_181 = _T_180 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_182 = _T_181 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_186 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 32:29] + wire _T_189 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 32:53] + wire _T_195 = _T_9 & _T_99; // @[el2_dec_dec_ctl.scala 33:28] + wire _T_197 = _T_195 & io_ins[2]; // @[el2_dec_dec_ctl.scala 33:41] + wire _T_208 = _T_9 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_223 = _T_103 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_235 = _T_19 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_236 = _T_235 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_237 = _T_236 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_245 = _T_237 | _T_197; // @[el2_dec_dec_ctl.scala 37:49] + wire _T_247 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_261 = _T_247 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_262 = _T_261 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_263 = _T_262 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_264 = _T_263 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_265 = _T_264 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_266 = _T_265 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_267 = _T_266 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_278 = io_ins[30] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_279 = _T_278 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_280 = _T_279 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_281 = _T_280 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_282 = _T_281 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_293 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_294 = _T_293 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_295 = _T_294 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_296 = _T_295 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_297 = _T_296 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_298 = _T_282 | _T_297; // @[el2_dec_dec_ctl.scala 39:49] + wire _T_307 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_308 = _T_307 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_309 = _T_308 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_310 = _T_309 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_311 = _T_298 | _T_310; // @[el2_dec_dec_ctl.scala 39:85] + wire _T_317 = io_ins[6] & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_318 = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_327 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_328 = _T_327 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_329 = _T_328 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_330 = _T_329 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_340 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_341 = _T_340 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_342 = _T_341 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_343 = _T_342 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_344 = _T_343 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_349 = _T_103 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_362 = _T_341 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_363 = _T_362 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_364 = _T_363 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_365 = _T_349 | _T_364; // @[el2_dec_dec_ctl.scala 42:37] + wire _T_369 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_370 = _T_369 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_371 = _T_365 | _T_370; // @[el2_dec_dec_ctl.scala 42:74] + wire _T_381 = _T_371 | _T_148; // @[el2_dec_dec_ctl.scala 43:26] + wire _T_391 = _T_327 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_392 = _T_391 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_393 = _T_392 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_406 = _T_340 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_407 = _T_406 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_408 = _T_407 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_409 = _T_408 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_420 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_421 = _T_420 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_422 = _T_421 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_423 = _T_422 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_424 = _T_423 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_439 = _T_293 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_440 = _T_439 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_441 = _T_440 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_442 = _T_441 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_453 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_454 = _T_453 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_455 = _T_454 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_456 = _T_455 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_472 = _T_261 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_473 = _T_472 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_474 = _T_473 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_475 = _T_474 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_476 = _T_475 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_515 = _T_307 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_516 = _T_515 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_517 = _T_516 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_524 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_525 = _T_524 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_526 = _T_525 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_527 = _T_517 | _T_526; // @[el2_dec_dec_ctl.scala 50:51] + wire _T_533 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_534 = _T_533 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_535 = _T_527 | _T_534; // @[el2_dec_dec_ctl.scala 50:79] + wire _T_548 = _T_294 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_549 = _T_548 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_550 = _T_549 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_551 = _T_535 | _T_550; // @[el2_dec_dec_ctl.scala 51:29] + wire _T_560 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_561 = _T_560 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_562 = _T_561 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_563 = _T_562 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_564 = _T_563 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_582 = _T_14 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_583 = _T_582 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_584 = _T_583 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_594 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_595 = _T_594 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_596 = _T_595 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_605 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_606 = _T_605 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_607 = _T_606 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_617 = io_ins[14] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_618 = _T_617 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_619 = _T_618 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_635 = _T_146 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_636 = _T_635 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_645 = io_ins[12] & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_646 = _T_645 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_653 = io_ins[13] & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_659 = _T_524 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_663 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_664 = _T_663 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_665 = _T_659 | _T_664; // @[el2_dec_dec_ctl.scala 62:44] + wire _T_669 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_670 = _T_669 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_671 = _T_665 | _T_670; // @[el2_dec_dec_ctl.scala 62:67] + wire _T_675 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_676 = _T_675 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_677 = _T_671 | _T_676; // @[el2_dec_dec_ctl.scala 63:26] + wire _T_681 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_682 = _T_681 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_683 = _T_677 | _T_682; // @[el2_dec_dec_ctl.scala 63:49] + wire _T_687 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_688 = _T_687 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_696 = _T_93 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_697 = _T_696 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_698 = _T_697 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_705 = _T_78 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_706 = _T_705 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_707 = _T_706 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_708 = _T_698 | _T_707; // @[el2_dec_dec_ctl.scala 65:49] + wire _T_715 = _T_63 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_716 = _T_715 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_717 = _T_716 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_718 = _T_708 | _T_717; // @[el2_dec_dec_ctl.scala 65:79] + wire _T_725 = _T_48 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_726 = _T_725 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_727 = _T_726 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_728 = _T_718 | _T_727; // @[el2_dec_dec_ctl.scala 66:33] + wire _T_735 = _T_33 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_736 = _T_735 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_737 = _T_736 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_745 = _T_180 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_753 = _T_420 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_754 = _T_753 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_759 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_760 = _T_759 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_761 = _T_760 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_762 = _T_754 | _T_761; // @[el2_dec_dec_ctl.scala 69:47] + wire _T_767 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_768 = _T_767 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_769 = _T_768 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_770 = _T_762 | _T_769; // @[el2_dec_dec_ctl.scala 69:74] + wire _T_775 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_776 = _T_775 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_777 = _T_776 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_778 = _T_770 | _T_777; // @[el2_dec_dec_ctl.scala 70:30] + wire _T_783 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_784 = _T_783 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_785 = _T_784 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_786 = _T_778 | _T_785; // @[el2_dec_dec_ctl.scala 70:57] + wire _T_791 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_792 = _T_791 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_793 = _T_792 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_800 = io_ins[15] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_801 = _T_800 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_802 = _T_801 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_808 = io_ins[16] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_809 = _T_808 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_810 = _T_809 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_811 = _T_802 | _T_810; // @[el2_dec_dec_ctl.scala 72:47] + wire _T_817 = io_ins[17] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_818 = _T_817 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_819 = _T_818 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_820 = _T_811 | _T_819; // @[el2_dec_dec_ctl.scala 72:75] + wire _T_826 = io_ins[18] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_827 = _T_826 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_828 = _T_827 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_829 = _T_820 | _T_828; // @[el2_dec_dec_ctl.scala 73:31] + wire _T_835 = io_ins[19] & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_836 = _T_835 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_837 = _T_836 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_840 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_848 = _T_840 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_849 = _T_848 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_850 = _T_849 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_851 = _T_850 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_854 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_856 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_863 = _T_854 & _T_856; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_864 = _T_863 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_865 = _T_864 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_866 = _T_865 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_875 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_876 = _T_875 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_877 = _T_876 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_888 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_889 = _T_888 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_890 = _T_889 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_891 = _T_890 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_906 = _T_888 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_907 = _T_906 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_908 = _T_907 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_909 = _T_908 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_910 = _T_909 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_911 = _T_910 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_924 = _T_888 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_925 = _T_924 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_926 = _T_925 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_927 = _T_926 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_928 = _T_927 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_960 = _T_924 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_961 = _T_960 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_962 = _T_961 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_972 = _T_560 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_973 = _T_972 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_984 = _T_560 & io_ins[13]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_985 = _T_984 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_986 = _T_985 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_991 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_996 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_997 = _T_996 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1005 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1006 = _T_1005 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1007 = _T_1006 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1008 = _T_1007 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1012 = _T_1008 | _T_189; // @[el2_dec_dec_ctl.scala 87:51] + wire _T_1018 = _T_4 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1019 = _T_1018 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1020 = _T_1012 | _T_1019; // @[el2_dec_dec_ctl.scala 87:72] + wire _T_1036 = _T_86 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1037 = _T_1036 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1038 = _T_991 | _T_1037; // @[el2_dec_dec_ctl.scala 89:41] + wire _T_1045 = _T_71 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1046 = _T_1045 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1047 = _T_1038 | _T_1046; // @[el2_dec_dec_ctl.scala 89:68] + wire _T_1054 = _T_56 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1055 = _T_1054 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1056 = _T_1047 | _T_1055; // @[el2_dec_dec_ctl.scala 90:30] + wire _T_1063 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1064 = _T_1063 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1065 = _T_1056 | _T_1064; // @[el2_dec_dec_ctl.scala 90:57] + wire _T_1072 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1073 = _T_1072 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1074 = _T_1065 | _T_1073; // @[el2_dec_dec_ctl.scala 91:31] + wire _T_1080 = _T_93 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1081 = _T_1080 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1082 = _T_1074 | _T_1081; // @[el2_dec_dec_ctl.scala 91:59] + wire _T_1088 = _T_78 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1089 = _T_1088 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1090 = _T_1082 | _T_1089; // @[el2_dec_dec_ctl.scala 92:30] + wire _T_1096 = _T_63 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1097 = _T_1096 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1098 = _T_1090 | _T_1097; // @[el2_dec_dec_ctl.scala 92:57] + wire _T_1104 = _T_48 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1105 = _T_1104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1106 = _T_1098 | _T_1105; // @[el2_dec_dec_ctl.scala 93:30] + wire _T_1112 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1113 = _T_1112 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1129 = _T_840 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1130 = _T_1129 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1131 = _T_1130 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1132 = _T_1131 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1133 = _T_997 | _T_1132; // @[el2_dec_dec_ctl.scala 95:45] + wire _T_1142 = _T_1133 | _T_1037; // @[el2_dec_dec_ctl.scala 95:78] + wire _T_1151 = _T_1142 | _T_1046; // @[el2_dec_dec_ctl.scala 96:30] + wire _T_1160 = _T_1151 | _T_1055; // @[el2_dec_dec_ctl.scala 96:57] + wire _T_1169 = _T_1160 | _T_1064; // @[el2_dec_dec_ctl.scala 97:30] + wire _T_1178 = _T_1169 | _T_1073; // @[el2_dec_dec_ctl.scala 97:58] + wire _T_1186 = _T_1178 | _T_1081; // @[el2_dec_dec_ctl.scala 98:31] + wire _T_1194 = _T_1186 | _T_1089; // @[el2_dec_dec_ctl.scala 98:58] + wire _T_1202 = _T_1194 | _T_1097; // @[el2_dec_dec_ctl.scala 99:30] + wire _T_1210 = _T_1202 | _T_1105; // @[el2_dec_dec_ctl.scala 99:57] + wire _T_1220 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1226 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1228 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1232 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1234 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1241 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1243 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1245 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1247 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1249 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1253 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1255 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1257 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1259 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1261 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1271 = _T_1220 & _T_247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1272 = _T_1271 & io_ins[29]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1273 = _T_1272 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1274 = _T_1273 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1275 = _T_1274 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1276 = _T_1275 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1277 = _T_1276 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1278 = _T_1277 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1279 = _T_1278 & _T_840; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1280 = _T_1279 & io_ins[21]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1281 = _T_1280 & _T_856; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1282 = _T_1281 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1283 = _T_1282 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1284 = _T_1283 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1285 = _T_1284 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1286 = _T_1285 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1287 = _T_1286 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1288 = _T_1287 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1289 = _T_1288 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1290 = _T_1289 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1291 = _T_1290 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1292 = _T_1291 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1293 = _T_1292 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1294 = _T_1293 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1295 = _T_1294 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1296 = _T_1295 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1297 = _T_1296 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1298 = _T_1297 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1299 = _T_1298 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1305 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1353 = _T_1271 & _T_1305; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1354 = _T_1353 & io_ins[28]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1355 = _T_1354 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1356 = _T_1355 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1357 = _T_1356 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1358 = _T_1357 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1359 = _T_1358 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1360 = _T_1359 & io_ins[22]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1361 = _T_1360 & _T_854; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1362 = _T_1361 & io_ins[20]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1363 = _T_1362 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1364 = _T_1363 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1365 = _T_1364 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1366 = _T_1365 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1367 = _T_1366 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1368 = _T_1367 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1369 = _T_1368 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1370 = _T_1369 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1371 = _T_1370 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1372 = _T_1371 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1373 = _T_1372 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1374 = _T_1373 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1375 = _T_1374 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1376 = _T_1375 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1377 = _T_1376 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1378 = _T_1377 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1379 = _T_1378 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1380 = _T_1379 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1381 = _T_1299 | _T_1380; // @[el2_dec_dec_ctl.scala 101:136] + wire _T_1389 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 15:46] + wire _T_1436 = _T_1353 & _T_1389; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1437 = _T_1436 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1438 = _T_1437 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1439 = _T_1438 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1440 = _T_1439 & _T_1232; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1441 = _T_1440 & _T_1234; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1442 = _T_1441 & _T_840; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1443 = _T_1442 & _T_854; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1444 = _T_1443 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1445 = _T_1444 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1446 = _T_1445 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1447 = _T_1446 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1448 = _T_1447 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1449 = _T_1448 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1450 = _T_1449 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1451 = _T_1450 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1452 = _T_1451 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1453 = _T_1452 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1454 = _T_1453 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1455 = _T_1454 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1456 = _T_1455 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1457 = _T_1456 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1458 = _T_1457 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1459 = _T_1458 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1460 = _T_1459 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1461 = _T_1381 | _T_1460; // @[el2_dec_dec_ctl.scala 102:122] + wire _T_1489 = _T_1439 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1490 = _T_1489 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1491 = _T_1490 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1492 = _T_1491 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1493 = _T_1492 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1494 = _T_1461 | _T_1493; // @[el2_dec_dec_ctl.scala 103:119] + wire _T_1521 = _T_1220 & _T_1305; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1522 = _T_1521 & _T_1389; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1523 = _T_1522 & _T_1226; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1524 = _T_1523 & _T_1228; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1525 = _T_1524 & _T_4; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1526 = _T_1525 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1527 = _T_1526 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1528 = _T_1527 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1529 = _T_1528 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1530 = _T_1529 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1531 = _T_1530 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1532 = _T_1531 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1533 = _T_1532 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1534 = _T_1494 | _T_1533; // @[el2_dec_dec_ctl.scala 104:60] + wire _T_1563 = _T_1525 & io_ins[14]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1564 = _T_1563 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1565 = _T_1564 & io_ins[12]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1566 = _T_1565 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1567 = _T_1566 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1568 = _T_1567 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1569 = _T_1568 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1570 = _T_1569 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1571 = _T_1534 | _T_1570; // @[el2_dec_dec_ctl.scala 105:69] + wire _T_1597 = _T_1438 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1598 = _T_1597 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1599 = _T_1598 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1600 = _T_1599 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1601 = _T_1600 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1602 = _T_1601 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1603 = _T_1571 | _T_1602; // @[el2_dec_dec_ctl.scala 106:66] + wire _T_1620 = _T_235 & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1621 = _T_1620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1622 = _T_1621 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1623 = _T_1622 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1624 = _T_1623 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1625 = _T_1624 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1626 = _T_1603 | _T_1625; // @[el2_dec_dec_ctl.scala 107:58] + wire _T_1638 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1640 = _T_1639 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1641 = _T_1640 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1642 = _T_1641 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1643 = _T_1642 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1644 = _T_1643 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1645 = _T_1626 | _T_1644; // @[el2_dec_dec_ctl.scala 108:46] + wire _T_1657 = _T_143 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1658 = _T_1657 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1659 = _T_1658 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1660 = _T_1659 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1661 = _T_1660 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1662 = _T_1661 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1663 = _T_1645 | _T_1662; // @[el2_dec_dec_ctl.scala 109:40] + wire _T_1678 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1679 = _T_1678 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1680 = _T_1679 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1681 = _T_1680 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1682 = _T_1681 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1683 = _T_1682 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1684 = _T_1663 | _T_1683; // @[el2_dec_dec_ctl.scala 110:39] + wire _T_1695 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1696 = _T_1695 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1697 = _T_1696 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1698 = _T_1697 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1699 = _T_1698 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1700 = _T_1699 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1701 = _T_1700 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1702 = _T_1684 | _T_1701; // @[el2_dec_dec_ctl.scala 111:43] + wire _T_1771 = _T_1443 & _T_856; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1772 = _T_1771 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1773 = _T_1772 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1774 = _T_1773 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1775 = _T_1774 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1776 = _T_1775 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1777 = _T_1776 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1778 = _T_1777 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1779 = _T_1778 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1780 = _T_1779 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1781 = _T_1780 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1782 = _T_1781 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1783 = _T_1782 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1784 = _T_1783 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1785 = _T_1784 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1786 = _T_1785 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1787 = _T_1786 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1788 = _T_1787 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1789 = _T_1788 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1790 = _T_1789 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1791 = _T_1702 | _T_1790; // @[el2_dec_dec_ctl.scala 112:39] + wire _T_1839 = _T_1436 & _T_1241; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1840 = _T_1839 & _T_1243; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1841 = _T_1840 & _T_1245; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1842 = _T_1841 & _T_1247; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1843 = _T_1842 & _T_1249; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1844 = _T_1843 & _T_14; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1845 = _T_1844 & _T_16; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1846 = _T_1845 & _T_143; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1847 = _T_1846 & _T_1253; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1848 = _T_1847 & _T_1255; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1849 = _T_1848 & _T_1257; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1850 = _T_1849 & _T_1259; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1851 = _T_1850 & _T_1261; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1852 = _T_1851 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1853 = _T_1852 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1854 = _T_1853 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1855 = _T_1854 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1856 = _T_1855 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1857 = _T_1856 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1858 = _T_1857 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1859 = _T_1791 | _T_1858; // @[el2_dec_dec_ctl.scala 113:130] + wire _T_1871 = _T_524 & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1872 = _T_1871 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1873 = _T_1872 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1874 = _T_1873 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1875 = _T_1874 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1876 = _T_1875 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1877 = _T_1859 | _T_1876; // @[el2_dec_dec_ctl.scala 114:102] + wire _T_1892 = _T_16 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1893 = _T_1892 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1894 = _T_1893 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1895 = _T_1894 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1896 = _T_1895 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1897 = _T_1896 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1898 = _T_1897 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1899 = _T_1877 | _T_1898; // @[el2_dec_dec_ctl.scala 115:39] + wire _T_1908 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1909 = _T_1908 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1910 = _T_1909 & io_ins[3]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1911 = _T_1910 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1912 = _T_1911 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1913 = _T_1912 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1914 = _T_1899 | _T_1913; // @[el2_dec_dec_ctl.scala 116:43] + wire _T_1926 = _T_653 & _T_9; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1927 = _T_1926 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1928 = _T_1927 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1929 = _T_1928 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1930 = _T_1929 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1931 = _T_1914 | _T_1930; // @[el2_dec_dec_ctl.scala 117:35] + wire _T_1947 = _T_582 & _T_103; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1948 = _T_1947 & _T_97; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1949 = _T_1948 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1950 = _T_1949 & _T_18; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1951 = _T_1950 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1952 = _T_1951 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1953 = _T_1931 | _T_1952; // @[el2_dec_dec_ctl.scala 118:38] + wire _T_1962 = _T_103 & io_ins[4]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1963 = _T_1962 & _T_99; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1964 = _T_1963 & io_ins[2]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1965 = _T_1964 & io_ins[1]; // @[el2_dec_dec_ctl.scala 17:17] + wire _T_1966 = _T_1965 & io_ins[0]; // @[el2_dec_dec_ctl.scala 17:17] + assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 20:14] + assign io_out_rs1 = _T_101 | _T_106; // @[el2_dec_dec_ctl.scala 21:14] + assign io_out_rs2 = _T_114 | _T_121; // @[el2_dec_dec_ctl.scala 27:14] + assign io_out_imm12 = _T_149 | _T_159; // @[el2_dec_dec_ctl.scala 28:16] + assign io_out_rd = _T_169 | io_ins[4]; // @[el2_dec_dec_ctl.scala 30:13] + assign io_out_shimm5 = _T_182 & _T_18; // @[el2_dec_dec_ctl.scala 31:17] + assign io_out_imm20 = _T_186 | _T_189; // @[el2_dec_dec_ctl.scala 32:16] + assign io_out_pc = _T_197 | _T_186; // @[el2_dec_dec_ctl.scala 33:13] + assign io_out_load = _T_208 & _T_18; // @[el2_dec_dec_ctl.scala 34:15] + assign io_out_store = _T_120 & _T_97; // @[el2_dec_dec_ctl.scala 35:16] + assign io_out_lsu = _T_223 & _T_18; // @[el2_dec_dec_ctl.scala 36:14] + assign io_out_add = _T_245 | _T_267; // @[el2_dec_dec_ctl.scala 37:14] + assign io_out_sub = _T_311 | _T_318; // @[el2_dec_dec_ctl.scala 39:14] + assign io_out_land = _T_330 | _T_344; // @[el2_dec_dec_ctl.scala 41:15] + assign io_out_lor = _T_381 | _T_393; // @[el2_dec_dec_ctl.scala 42:14] + assign io_out_lxor = _T_409 | _T_424; // @[el2_dec_dec_ctl.scala 45:15] + assign io_out_sll = _T_442 & _T_18; // @[el2_dec_dec_ctl.scala 46:14] + assign io_out_sra = _T_456 & _T_18; // @[el2_dec_dec_ctl.scala 47:14] + assign io_out_srl = _T_476 & _T_18; // @[el2_dec_dec_ctl.scala 48:14] + assign io_out_slt = _T_297 | _T_310; // @[el2_dec_dec_ctl.scala 49:14] + assign io_out_unsign = _T_551 | _T_564; // @[el2_dec_dec_ctl.scala 50:17] + assign io_out_condbr = _T_317 & _T_18; // @[el2_dec_dec_ctl.scala 53:17] + assign io_out_beq = _T_584 & _T_18; // @[el2_dec_dec_ctl.scala 54:14] + assign io_out_bne = _T_596 & _T_18; // @[el2_dec_dec_ctl.scala 55:14] + assign io_out_bge = _T_607 & _T_18; // @[el2_dec_dec_ctl.scala 56:14] + assign io_out_blt = _T_619 & _T_18; // @[el2_dec_dec_ctl.scala 57:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 58:14] + assign io_out_by = _T_636 & _T_18; // @[el2_dec_dec_ctl.scala 59:13] + assign io_out_half = _T_646 & _T_18; // @[el2_dec_dec_ctl.scala 60:15] + assign io_out_word = _T_653 & _T_97; // @[el2_dec_dec_ctl.scala 61:15] + assign io_out_csr_read = _T_683 | _T_688; // @[el2_dec_dec_ctl.scala 62:19] + assign io_out_csr_clr = _T_728 | _T_737; // @[el2_dec_dec_ctl.scala 65:18] + assign io_out_csr_set = _T_829 | _T_837; // @[el2_dec_dec_ctl.scala 72:18] + assign io_out_csr_write = _T_745 & io_ins[4]; // @[el2_dec_dec_ctl.scala 68:20] + assign io_out_csr_imm = _T_786 | _T_793; // @[el2_dec_dec_ctl.scala 69:18] + assign io_out_presync = _T_1106 | _T_1113; // @[el2_dec_dec_ctl.scala 89:18] + assign io_out_postsync = _T_1210 | _T_1113; // @[el2_dec_dec_ctl.scala 95:19] + assign io_out_ebreak = _T_851 & io_ins[4]; // @[el2_dec_dec_ctl.scala 75:17] + assign io_out_ecall = _T_866 & io_ins[4]; // @[el2_dec_dec_ctl.scala 76:16] + assign io_out_mret = _T_877 & io_ins[4]; // @[el2_dec_dec_ctl.scala 77:15] + assign io_out_mul = _T_891 & _T_18; // @[el2_dec_dec_ctl.scala 78:14] + assign io_out_rs1_sign = _T_911 | _T_928; // @[el2_dec_dec_ctl.scala 79:19] + assign io_out_rs2_sign = _T_927 & _T_18; // @[el2_dec_dec_ctl.scala 81:19] + assign io_out_low = _T_962 & _T_18; // @[el2_dec_dec_ctl.scala 82:14] + assign io_out_div = _T_973 & _T_18; // @[el2_dec_dec_ctl.scala 83:14] + assign io_out_rem = _T_986 & _T_18; // @[el2_dec_dec_ctl.scala 84:14] + assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 85:16] + assign io_out_fence_i = _T_996 & io_ins[3]; // @[el2_dec_dec_ctl.scala 86:18] + assign io_out_pm_alu = _T_1020 | _T_11; // @[el2_dec_dec_ctl.scala 87:17] + assign io_out_legal = _T_1953 | _T_1966; // @[el2_dec_dec_ctl.scala 101:16] endmodule module el2_dec_decode_ctl( input clock, @@ -45938,13 +45948,13 @@ module el2_dec_decode_ctl( input [1:0] io_dec_i0_icaf_type_d, input io_dec_i0_dbecc_d, input io_dec_i0_brp_valid, - input [11:0] io_dec_i0_brp_bits_toffset, - input [1:0] io_dec_i0_brp_bits_hist, - input io_dec_i0_brp_bits_br_error, - input io_dec_i0_brp_bits_br_start_error, - input [30:0] io_dec_i0_brp_bits_prett, - input io_dec_i0_brp_bits_way, - input io_dec_i0_brp_bits_ret, + input [11:0] io_dec_i0_brp_toffset, + input [1:0] io_dec_i0_brp_hist, + input io_dec_i0_brp_br_error, + input io_dec_i0_brp_br_start_error, + input [30:0] io_dec_i0_brp_prett, + input io_dec_i0_brp_way, + input io_dec_i0_brp_ret, input [7:0] io_dec_i0_bp_index, input [7:0] io_dec_i0_bp_fghr, input [4:0] io_dec_i0_bp_btag, @@ -46368,21 +46378,21 @@ module el2_dec_decode_ctl( wire _T_22 = _T_21 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 237:103] wire _T_23 = ~_T_22; // @[el2_dec_decode_ctl.scala 237:56] wire i0_notbr_error = i0_brp_valid & _T_23; // @[el2_dec_decode_ctl.scala 237:54] - wire _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:62] - wire _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[el2_dec_decode_ctl.scala 240:47] + wire _T_31 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:57] + wire _T_25 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 240:47] wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 415:41] wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 415:26] - wire _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:106] - wire _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:76] - wire _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:126] - wire i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:124] - wire _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:79] - wire _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[el2_dec_decode_ctl.scala 241:47] - wire i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:72] - wire i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:101] - wire _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[el2_dec_decode_ctl.scala 247:47] - wire i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:84] + wire _T_26 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:96] + wire _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:71] + wire _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:116] + wire i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:114] + wire _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:74] + wire _T_29 = i0_brp_valid & io_dec_i0_brp_ret; // @[el2_dec_decode_ctl.scala 241:47] + wire i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:67] + wire i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:96] + wire _T_39 = i0_br_error | io_dec_i0_brp_br_start_error; // @[el2_dec_decode_ctl.scala 247:47] + wire i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:79] wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 256:36] wire _T_41 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 260:25] wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] @@ -46411,8 +46421,8 @@ module el2_dec_decode_ctl( wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 570:54] wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 570:39] reg postsync_stall; // @[el2_dec_decode_ctl.scala 568:53] - reg x_d_valid; // @[el2_lib.scala 524:16] - wire _T_507 = postsync_stall & x_d_valid; // @[el2_dec_decode_ctl.scala 570:88] + reg x_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 570:88] wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 570:69] wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] @@ -46427,7 +46437,7 @@ module el2_dec_decode_ctl( wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32] wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 644:46] wire _T_33 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 243:72] - wire _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:94] + wire _T_36 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:89] wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 260:50] wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12] @@ -46504,42 +46514,42 @@ module el2_dec_decode_ctl( wire _T_45 = _T_44 | i0_pja; // @[el2_dec_decode_ctl.scala 274:49] wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 419:32] wire i0_predict_br = _T_45 | i0_pret; // @[el2_dec_decode_ctl.scala 274:58] - wire _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:55] + wire _T_47 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:50] wire _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26] wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20] wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63] - reg [2:0] cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] + reg [2:0] cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 347:47] wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 322:67] - wire _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + wire _T_94 = _GEN_123 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_95 = cam_data_reset & _T_94; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 322:83] wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_51 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 303:78] - reg [2:0] cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + reg [2:0] cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_120 = _GEN_123 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_121 = cam_data_reset & _T_120; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 322:83] wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_54 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 303:78] wire _T_57 = cam_0_valid & _T_54; // @[el2_dec_decode_ctl.scala 303:126] wire [1:0] _T_59 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 303:158] - reg [2:0] cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + reg [2:0] cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_146 = _GEN_123 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_147 = cam_data_reset & _T_146; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 322:83] wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_60 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 303:78] wire _T_63 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 303:126] wire _T_66 = _T_63 & _T_60; // @[el2_dec_decode_ctl.scala 303:126] wire [2:0] _T_68 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 303:158] - reg [2:0] cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 322:67] + reg [2:0] cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_172 = _GEN_123 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 322:67] wire _T_173 = cam_data_reset & _T_172; // @[el2_dec_decode_ctl.scala 322:45] reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 347:47] - wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:88] + wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 322:83] wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:39] wire _T_69 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 303:78] wire _T_75 = _T_63 & cam_2_valid; // @[el2_dec_decode_ctl.scala 303:126] @@ -46555,89 +46565,89 @@ module el2_dec_decode_ctl( wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72] wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72] wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] - reg x_d_bits_i0load; // @[el2_lib.scala 524:16] - reg [4:0] x_d_bits_i0rd; // @[el2_lib.scala 524:16] - wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] + reg x_d_i0load; // @[el2_lib.scala 524:16] + reg [4:0] x_d_i0rd; // @[el2_lib.scala 524:16] + wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 314:31] reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 652:72] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 655:49] wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 655:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] - reg r_d_bits_i0load; // @[el2_lib.scala 524:16] - wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 319:56] + reg r_d_i0load; // @[el2_lib.scala 524:16] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 319:56] wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 321:66] - wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_91 = _GEN_130 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_92 = io_lsu_nonblock_load_inv_r & _T_91; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg r_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:51] - wire r_d_in_bits_i0v = r_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:49] - wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:47] - wire i0_wen_r = r_d_in_bits_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:45] - reg [4:0] r_d_bits_i0rd; // @[el2_lib.scala 524:16] - reg [4:0] cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg r_d_i0v; // @[el2_lib.scala 524:16] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 687:41] + wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 687:39] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 695:42] + wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 695:40] + reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16] + reg [4:0] cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_103 = r_d_i0rd == cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_104 = i0_wen_r & _T_103; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + reg cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_106 = _T_104 & cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:95] wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 334:116] wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 329:28] wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:100] - wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_112 = _T_110 & cam_0_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_117 = _GEN_130 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_118 = io_lsu_nonblock_load_inv_r & _T_117; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg [4:0] cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg [4:0] cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_129 = r_d_i0rd == cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_130 = i0_wen_r & _T_129; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + reg cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_132 = _T_130 & cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:95] wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 334:116] wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 329:28] wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:100] - wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_138 = _T_136 & cam_1_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_143 = _GEN_130 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_144 = io_lsu_nonblock_load_inv_r & _T_143; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg [4:0] cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg [4:0] cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_155 = r_d_i0rd == cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_156 = i0_wen_r & _T_155; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + reg cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_158 = _T_156 & cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:95] wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 334:116] wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 329:28] wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:100] - wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[el2_dec_decode_ctl.scala 321:66] + wire _T_164 = _T_162 & cam_2_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_169 = _GEN_130 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 321:66] wire _T_170 = io_lsu_nonblock_load_inv_r & _T_169; // @[el2_dec_decode_ctl.scala 321:45] - wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:87] - reg [4:0] cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 334:85] + wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[el2_dec_decode_ctl.scala 321:82] + reg [4:0] cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_181 = r_d_i0rd == cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 334:80] wire _T_182 = i0_wen_r & _T_181; // @[el2_dec_decode_ctl.scala 334:64] - reg cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 347:47] - wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:105] + reg cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 347:47] + wire _T_184 = _T_182 & cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:95] wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[el2_dec_decode_ctl.scala 334:44] - wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:131] - wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[el2_dec_decode_ctl.scala 334:131] + wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 334:116] + wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 334:116] wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 329:28] wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 329:28] wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[el2_dec_decode_ctl.scala 339:44] - wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:100] - wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:71] - wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:49] - wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:81] + wire _T_190 = _T_188 & cam_3_valid; // @[el2_dec_decode_ctl.scala 339:95] + wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 348:66] + wire _T_195 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 353:44] + wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[el2_dec_decode_ctl.scala 353:76] wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 354:95] wire _T_197 = _T_196 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 354:95] wire _T_198 = _T_197 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 354:95] @@ -46652,37 +46662,37 @@ module el2_dec_decode_ctl( wire _T_208 = _T_207 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 355:180] wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[el2_dec_decode_ctl.scala 355:118] wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:126] - wire _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] - wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:141] - wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:192] - wire _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] - wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_211 = _T_210 & cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_212 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_213 = cam_raw_0_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_214 = _T_212 & _T_213; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_215 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_216 = cam_raw_0_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_217 = _T_215 & _T_216; // @[el2_dec_decode_ctl.scala 359:197] wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:126] - wire _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] - wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:141] - wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:192] - wire _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] - wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_220 = _T_219 & cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_221 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_222 = cam_raw_1_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_223 = _T_221 & _T_222; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_224 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_225 = cam_raw_1_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_226 = _T_224 & _T_225; // @[el2_dec_decode_ctl.scala 359:197] wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:126] - wire _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] - wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:141] - wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:192] - wire _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] - wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_229 = _T_228 & cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_230 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_231 = cam_raw_2_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_232 = _T_230 & _T_231; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_233 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_234 = cam_raw_2_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_235 = _T_233 & _T_234; // @[el2_dec_decode_ctl.scala 359:197] wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[el2_dec_decode_ctl.scala 359:88] - wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:126] - wire _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:159] - wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:141] - wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:192] - wire _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:225] - wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:207] + wire [4:0] _T_238 = _T_237 & cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 359:88] + wire _T_239 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:121] + wire _T_240 = cam_raw_3_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_241 = _T_239 & _T_240; // @[el2_dec_decode_ctl.scala 359:136] + wire _T_242 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 359:182] + wire _T_243 = cam_raw_3_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:210] + wire _T_244 = _T_242 & _T_243; // @[el2_dec_decode_ctl.scala 359:197] wire [4:0] _T_245 = _T_211 | _T_220; // @[el2_dec_decode_ctl.scala 360:69] wire [4:0] _T_246 = _T_245 | _T_229; // @[el2_dec_decode_ctl.scala 360:69] wire _T_247 = _T_214 | _T_223; // @[el2_dec_decode_ctl.scala 360:102] @@ -46724,13 +46734,13 @@ module el2_dec_decode_ctl( reg _T_339; // @[el2_dec_decode_ctl.scala 432:58] wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 574:40] wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 788:43] - reg x_d_bits_i0v; // @[el2_lib.scala 524:16] - wire _T_876 = io_dec_i0_rs1_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 768:48] - wire _T_877 = x_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:80] - wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:63] - wire _T_878 = io_dec_i0_rs1_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 769:48] - wire _T_879 = r_d_bits_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:80] - wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:63] + reg x_d_i0v; // @[el2_lib.scala 524:16] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 768:48] + wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 768:70] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 768:58] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 769:48] + wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 769:70] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 769:58] wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 775:63] wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 775:24] wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 788:58] @@ -46739,12 +46749,12 @@ module el2_dec_decode_ctl( wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 774:61] wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 774:24] wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 788:78] - wire _T_880 = io_dec_i0_rs2_en_d & x_d_bits_i0v; // @[el2_dec_decode_ctl.scala 771:48] - wire _T_881 = x_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:80] - wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:63] - wire _T_882 = io_dec_i0_rs2_en_d & r_d_bits_i0v; // @[el2_dec_decode_ctl.scala 772:48] - wire _T_883 = r_d_bits_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:80] - wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:63] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 771:48] + wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 771:70] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 771:58] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 772:70] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 772:58] wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 777:63] wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 777:24] wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 789:43] @@ -46752,16 +46762,16 @@ module el2_dec_decode_ctl( wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 776:24] wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 789:63] wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 463:42] - reg r_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg r_d_valid; // @[el2_lib.scala 524:16] - wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[el2_dec_decode_ctl.scala 471:39] - reg [11:0] r_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:50] - wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:85] - wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:64] - wire _T_358 = _T_357 & r_d_bits_csrwen; // @[el2_dec_decode_ctl.scala 474:100] - wire _T_359 = _T_358 & r_d_valid; // @[el2_dec_decode_ctl.scala 474:118] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:132] + reg r_d_csrwen; // @[el2_lib.scala 524:16] + reg r_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 471:34] + reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 474:45] + wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 474:75] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 474:59] + wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 474:90] + wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 474:103] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 474:119] reg csr_read_x; // @[el2_dec_decode_ctl.scala 476:52] reg csr_clr_x; // @[el2_dec_decode_ctl.scala 477:51] reg csr_set_x; // @[el2_dec_decode_ctl.scala 478:51] @@ -46791,14 +46801,14 @@ module el2_dec_decode_ctl( wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 507:46] wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 507:61] wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 507:75] - reg r_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_764 = r_d_bits_i0v & r_d_bits_i0load; // @[el2_dec_decode_ctl.scala 710:42] + reg r_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 710:37] reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 710:27] - reg x_d_bits_csrwonly; // @[el2_lib.scala 524:16] - wire _T_432 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:43] - reg wbd_bits_csrwonly; // @[el2_lib.scala 524:16] - wire prior_csr_write = _T_432 | wbd_bits_csrwonly; // @[el2_dec_decode_ctl.scala 516:63] + reg x_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 516:38] + reg wbd_csrwonly; // @[el2_lib.scala 524:16] + wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 516:53] wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 519:48] wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 520:40] wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 523:34] @@ -46815,8 +46825,8 @@ module el2_dec_decode_ctl( wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 541:95] wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 542:20] wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 542:45] - wire prior_inflight = x_d_valid | r_d_valid; // @[el2_dec_decode_ctl.scala 564:41] - wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] + wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 564:41] + wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 565:31] wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 567:37] wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 542:62] wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 543:19] @@ -46872,13 +46882,13 @@ module el2_dec_decode_ctl( reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 602:36] reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 603:37] - reg r_d_bits_i0store; // @[el2_lib.scala 524:16] - wire _T_536 = r_d_bits_i0load | r_d_bits_i0store; // @[el2_dec_decode_ctl.scala 607:61] + reg r_d_i0store; // @[el2_lib.scala 524:16] + wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 607:56] wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] - wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:82] - wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:105] - reg r_d_bits_i0div; // @[el2_lib.scala 524:16] - wire _T_545 = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 613:58] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 607:72] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 607:95] + reg r_d_i0div; // @[el2_lib.scala 524:16] + wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 613:53] wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 624:49] wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 625:49] wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 626:48] @@ -46914,34 +46924,34 @@ module el2_dec_decode_ctl( reg i0_r_c_alu; // @[Reg.scala 15:16] wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 656:49] wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 658:50] - reg x_d_bits_i0store; // @[el2_lib.scala 524:16] - reg x_d_bits_i0div; // @[el2_lib.scala 524:16] - reg x_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg [11:0] x_d_bits_csrwaddr; // @[el2_lib.scala 524:16] - wire _T_733 = x_d_bits_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:47] - wire _T_737 = x_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 681:33] - wire _T_756 = ~r_d_bits_i0div; // @[el2_dec_decode_ctl.scala 696:49] + reg x_d_i0store; // @[el2_lib.scala 524:16] + reg x_d_i0div; // @[el2_lib.scala 524:16] + reg x_d_csrwen; // @[el2_lib.scala 524:16] + reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 680:37] + wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 681:37] + wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 696:49] wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 696:47] - wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:70] - wire _T_761 = x_d_bits_i0v & x_d_bits_i0load; // @[el2_dec_decode_ctl.scala 705:47] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 696:65] + wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 705:42] wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 711:52] wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] - wire _T_799 = x_d_bits_i0div & x_d_valid; // @[el2_dec_decode_ctl.scala 719:45] - wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:58] - wire _T_802 = x_d_bits_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:77] - wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:60] - wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:33] - wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:94] - wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:33] - wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:60] - wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:62] + wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 719:40] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 719:55] + wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 721:69] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 721:57] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 722:30] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 721:86] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 723:30] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 723:57] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 722:59] wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 727:51] wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 728:26] wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 728:24] - wire _T_813 = r_d_bits_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:56] + wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 728:51] wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 728:39] - wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:77] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 728:72] wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 727:65] wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 731:55] wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 733:62] @@ -47240,7 +47250,7 @@ module el2_dec_decode_ctl( assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 572:26] assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 807:31] assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 812:31] - assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[el2_dec_decode_ctl.scala 694:27] + assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 694:27] assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 696:32] assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 697:26] assign io_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 271:25] @@ -47272,10 +47282,10 @@ module el2_dec_decode_ctl( assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 529:24] assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 466:24] assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 471:20] - assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] - assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] + assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 467:23] + assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 514:24] assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 474:27] - assign io_dec_tlu_i0_valid_r = r_d_valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] + assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 578:29] assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 612:39] @@ -47284,22 +47294,22 @@ module el2_dec_decode_ctl( assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 612:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 612:39 el2_dec_decode_ctl.scala 613:39] assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 612:39] assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 759:27] assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 536:23] assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 764:25] assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 236:38] assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 234:43] - assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[el2_dec_decode_ctl.scala 235:43] + assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_hist; // @[el2_dec_decode_ctl.scala 235:43] assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 248:49] assign io_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[el2_dec_decode_ctl.scala 243:56] assign io_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[el2_dec_decode_ctl.scala 244:56] - assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[el2_dec_decode_ctl.scala 233:43] + assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_prett; // @[el2_dec_decode_ctl.scala 233:43] assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 230:43] assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 232:43] assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 231:43] - assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[el2_dec_decode_ctl.scala 250:56] + assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_way; // @[el2_dec_decode_ctl.scala 250:56] assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 249:32] assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 245:32] assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 246:32] @@ -47425,73 +47435,73 @@ initial begin _RAND_6 = {1{`RANDOM}}; postsync_stall = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - x_d_valid = _RAND_7[0:0]; + x_d_i0valid = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; flush_final_r = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; illegal_lockout = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; - cam_raw_0_bits_tag = _RAND_10[2:0]; + cam_raw_0_tag = _RAND_10[2:0]; _RAND_11 = {1{`RANDOM}}; cam_raw_0_valid = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - cam_raw_1_bits_tag = _RAND_12[2:0]; + cam_raw_1_tag = _RAND_12[2:0]; _RAND_13 = {1{`RANDOM}}; cam_raw_1_valid = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - cam_raw_2_bits_tag = _RAND_14[2:0]; + cam_raw_2_tag = _RAND_14[2:0]; _RAND_15 = {1{`RANDOM}}; cam_raw_2_valid = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - cam_raw_3_bits_tag = _RAND_16[2:0]; + cam_raw_3_tag = _RAND_16[2:0]; _RAND_17 = {1{`RANDOM}}; cam_raw_3_valid = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - x_d_bits_i0load = _RAND_18[0:0]; + x_d_i0load = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - x_d_bits_i0rd = _RAND_19[4:0]; + x_d_i0rd = _RAND_19[4:0]; _RAND_20 = {1{`RANDOM}}; _T_701 = _RAND_20[2:0]; _RAND_21 = {1{`RANDOM}}; nonblock_load_valid_m_delay = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - r_d_bits_i0load = _RAND_22[0:0]; + r_d_i0load = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - r_d_bits_i0v = _RAND_23[0:0]; + r_d_i0v = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - r_d_bits_i0rd = _RAND_24[4:0]; + r_d_i0rd = _RAND_24[4:0]; _RAND_25 = {1{`RANDOM}}; - cam_raw_0_bits_rd = _RAND_25[4:0]; + cam_raw_0_rd = _RAND_25[4:0]; _RAND_26 = {1{`RANDOM}}; - cam_raw_0_bits_wb = _RAND_26[0:0]; + cam_raw_0_wb = _RAND_26[0:0]; _RAND_27 = {1{`RANDOM}}; - cam_raw_1_bits_rd = _RAND_27[4:0]; + cam_raw_1_rd = _RAND_27[4:0]; _RAND_28 = {1{`RANDOM}}; - cam_raw_1_bits_wb = _RAND_28[0:0]; + cam_raw_1_wb = _RAND_28[0:0]; _RAND_29 = {1{`RANDOM}}; - cam_raw_2_bits_rd = _RAND_29[4:0]; + cam_raw_2_rd = _RAND_29[4:0]; _RAND_30 = {1{`RANDOM}}; - cam_raw_2_bits_wb = _RAND_30[0:0]; + cam_raw_2_wb = _RAND_30[0:0]; _RAND_31 = {1{`RANDOM}}; - cam_raw_3_bits_rd = _RAND_31[4:0]; + cam_raw_3_rd = _RAND_31[4:0]; _RAND_32 = {1{`RANDOM}}; - cam_raw_3_bits_wb = _RAND_32[0:0]; + cam_raw_3_wb = _RAND_32[0:0]; _RAND_33 = {1{`RANDOM}}; lsu_idle = _RAND_33[0:0]; _RAND_34 = {1{`RANDOM}}; _T_339 = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - x_d_bits_i0v = _RAND_35[0:0]; + x_d_i0v = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; i0_x_c_load = _RAND_36[0:0]; _RAND_37 = {1{`RANDOM}}; i0_r_c_load = _RAND_37[0:0]; _RAND_38 = {1{`RANDOM}}; - r_d_bits_csrwen = _RAND_38[0:0]; + r_d_csrwen = _RAND_38[0:0]; _RAND_39 = {1{`RANDOM}}; - r_d_valid = _RAND_39[0:0]; + r_d_i0valid = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - r_d_bits_csrwaddr = _RAND_40[11:0]; + r_d_csrwaddr = _RAND_40[11:0]; _RAND_41 = {1{`RANDOM}}; csr_read_x = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; @@ -47507,13 +47517,13 @@ initial begin _RAND_47 = {1{`RANDOM}}; csr_rddata_x = _RAND_47[31:0]; _RAND_48 = {1{`RANDOM}}; - r_d_bits_csrwonly = _RAND_48[0:0]; + r_d_csrwonly = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; i0_result_r_raw = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; - x_d_bits_csrwonly = _RAND_50[0:0]; + x_d_csrwonly = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - wbd_bits_csrwonly = _RAND_51[0:0]; + wbd_csrwonly = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; _T_465 = _RAND_52[31:0]; _RAND_53 = {1{`RANDOM}}; @@ -47553,9 +47563,9 @@ initial begin _RAND_70 = {1{`RANDOM}}; lsu_pmu_misaligned_r = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - r_d_bits_i0store = _RAND_71[0:0]; + r_d_i0store = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - r_d_bits_i0div = _RAND_72[0:0]; + r_d_i0div = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; i0_x_c_mul = _RAND_73[0:0]; _RAND_74 = {1{`RANDOM}}; @@ -47565,13 +47575,13 @@ initial begin _RAND_76 = {1{`RANDOM}}; i0_r_c_alu = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - x_d_bits_i0store = _RAND_77[0:0]; + x_d_i0store = _RAND_77[0:0]; _RAND_78 = {1{`RANDOM}}; - x_d_bits_i0div = _RAND_78[0:0]; + x_d_i0div = _RAND_78[0:0]; _RAND_79 = {1{`RANDOM}}; - x_d_bits_csrwen = _RAND_79[0:0]; + x_d_csrwen = _RAND_79[0:0]; _RAND_80 = {1{`RANDOM}}; - x_d_bits_csrwaddr = _RAND_80[11:0]; + x_d_csrwaddr = _RAND_80[11:0]; _RAND_81 = {1{`RANDOM}}; last_br_immed_x = _RAND_81[11:0]; _RAND_82 = {1{`RANDOM}}; @@ -47615,7 +47625,7 @@ initial begin postsync_stall = 1'h0; end if (reset) begin - x_d_valid = 1'h0; + x_d_i0valid = 1'h0; end if (reset) begin flush_final_r = 1'h0; @@ -47624,34 +47634,34 @@ initial begin illegal_lockout = 1'h0; end if (reset) begin - cam_raw_0_bits_tag = 3'h0; + cam_raw_0_tag = 3'h0; end if (reset) begin cam_raw_0_valid = 1'h0; end if (reset) begin - cam_raw_1_bits_tag = 3'h0; + cam_raw_1_tag = 3'h0; end if (reset) begin cam_raw_1_valid = 1'h0; end if (reset) begin - cam_raw_2_bits_tag = 3'h0; + cam_raw_2_tag = 3'h0; end if (reset) begin cam_raw_2_valid = 1'h0; end if (reset) begin - cam_raw_3_bits_tag = 3'h0; + cam_raw_3_tag = 3'h0; end if (reset) begin cam_raw_3_valid = 1'h0; end if (reset) begin - x_d_bits_i0load = 1'h0; + x_d_i0load = 1'h0; end if (reset) begin - x_d_bits_i0rd = 5'h0; + x_d_i0rd = 5'h0; end if (reset) begin _T_701 = 3'h0; @@ -47660,37 +47670,37 @@ initial begin nonblock_load_valid_m_delay = 1'h0; end if (reset) begin - r_d_bits_i0load = 1'h0; + r_d_i0load = 1'h0; end if (reset) begin - r_d_bits_i0v = 1'h0; + r_d_i0v = 1'h0; end if (reset) begin - r_d_bits_i0rd = 5'h0; + r_d_i0rd = 5'h0; end if (reset) begin - cam_raw_0_bits_rd = 5'h0; + cam_raw_0_rd = 5'h0; end if (reset) begin - cam_raw_0_bits_wb = 1'h0; + cam_raw_0_wb = 1'h0; end if (reset) begin - cam_raw_1_bits_rd = 5'h0; + cam_raw_1_rd = 5'h0; end if (reset) begin - cam_raw_1_bits_wb = 1'h0; + cam_raw_1_wb = 1'h0; end if (reset) begin - cam_raw_2_bits_rd = 5'h0; + cam_raw_2_rd = 5'h0; end if (reset) begin - cam_raw_2_bits_wb = 1'h0; + cam_raw_2_wb = 1'h0; end if (reset) begin - cam_raw_3_bits_rd = 5'h0; + cam_raw_3_rd = 5'h0; end if (reset) begin - cam_raw_3_bits_wb = 1'h0; + cam_raw_3_wb = 1'h0; end if (reset) begin lsu_idle = 1'h0; @@ -47699,16 +47709,16 @@ initial begin _T_339 = 1'h0; end if (reset) begin - x_d_bits_i0v = 1'h0; + x_d_i0v = 1'h0; end if (reset) begin - r_d_bits_csrwen = 1'h0; + r_d_csrwen = 1'h0; end if (reset) begin - r_d_valid = 1'h0; + r_d_i0valid = 1'h0; end if (reset) begin - r_d_bits_csrwaddr = 12'h0; + r_d_csrwaddr = 12'h0; end if (reset) begin csr_read_x = 1'h0; @@ -47732,16 +47742,16 @@ initial begin csr_rddata_x = 32'h0; end if (reset) begin - r_d_bits_csrwonly = 1'h0; + r_d_csrwonly = 1'h0; end if (reset) begin i0_result_r_raw = 32'h0; end if (reset) begin - x_d_bits_csrwonly = 1'h0; + x_d_csrwonly = 1'h0; end if (reset) begin - wbd_bits_csrwonly = 1'h0; + wbd_csrwonly = 1'h0; end if (reset) begin _T_465 = 32'h0; @@ -47801,22 +47811,22 @@ initial begin lsu_pmu_misaligned_r = 1'h0; end if (reset) begin - r_d_bits_i0store = 1'h0; + r_d_i0store = 1'h0; end if (reset) begin - r_d_bits_i0div = 1'h0; + r_d_i0div = 1'h0; end if (reset) begin - x_d_bits_i0store = 1'h0; + x_d_i0store = 1'h0; end if (reset) begin - x_d_bits_i0div = 1'h0; + x_d_i0div = 1'h0; end if (reset) begin - x_d_bits_csrwen = 1'h0; + x_d_csrwen = 1'h0; end if (reset) begin - x_d_bits_csrwaddr = 12'h0; + x_d_csrwaddr = 12'h0; end if (reset) begin last_br_immed_x = 12'h0; @@ -47929,9 +47939,9 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_valid <= 1'h0; + x_d_i0valid <= 1'h0; end else begin - x_d_valid <= io_dec_i0_decode_d; + x_d_i0valid <= io_dec_i0_decode_d; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -47950,11 +47960,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_bits_tag <= 3'h0; + cam_raw_0_tag <= 3'h0; end else if (cam_wen[0]) begin - cam_raw_0_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_0_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_107) begin - cam_raw_0_bits_tag <= 3'h0; + cam_raw_0_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -47968,11 +47978,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_bits_tag <= 3'h0; + cam_raw_1_tag <= 3'h0; end else if (cam_wen[1]) begin - cam_raw_1_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_1_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_133) begin - cam_raw_1_bits_tag <= 3'h0; + cam_raw_1_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -47986,11 +47996,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_bits_tag <= 3'h0; + cam_raw_2_tag <= 3'h0; end else if (cam_wen[2]) begin - cam_raw_2_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_2_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_159) begin - cam_raw_2_bits_tag <= 3'h0; + cam_raw_2_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -48004,11 +48014,11 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_bits_tag <= 3'h0; + cam_raw_3_tag <= 3'h0; end else if (cam_wen[3]) begin - cam_raw_3_bits_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + cam_raw_3_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; end else if (_T_185) begin - cam_raw_3_bits_tag <= 3'h0; + cam_raw_3_tag <= 3'h0; end end always @(posedge io_free_clk or posedge reset) begin @@ -48022,16 +48032,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0load <= 1'h0; + x_d_i0load <= 1'h0; end else begin - x_d_bits_i0load <= i0_dp_load & i0_legal_decode_d; + x_d_i0load <= i0_dp_load & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0rd <= 5'h0; + x_d_i0rd <= 5'h0; end else begin - x_d_bits_i0rd <= io_dec_i0_instr_d[11:7]; + x_d_i0rd <= io_dec_i0_instr_d[11:7]; end end always @(posedge io_active_clk or posedge reset) begin @@ -48050,103 +48060,103 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0load <= 1'h0; + r_d_i0load <= 1'h0; end else begin - r_d_bits_i0load <= x_d_bits_i0load; + r_d_i0load <= x_d_i0load; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0v <= 1'h0; + r_d_i0v <= 1'h0; end else begin - r_d_bits_i0v <= _T_733 & _T_280; + r_d_i0v <= _T_733 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0rd <= 5'h0; + r_d_i0rd <= 5'h0; end else begin - r_d_bits_i0rd <= x_d_bits_i0rd; + r_d_i0rd <= x_d_i0rd; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_bits_rd <= 5'h0; + cam_raw_0_rd <= 5'h0; end else if (cam_wen[0]) begin - if (x_d_bits_i0load) begin - cam_raw_0_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_0_rd <= x_d_i0rd; end else begin - cam_raw_0_bits_rd <= 5'h0; + cam_raw_0_rd <= 5'h0; end end else if (_T_107) begin - cam_raw_0_bits_rd <= 5'h0; + cam_raw_0_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_0_bits_wb <= 1'h0; + cam_raw_0_wb <= 1'h0; end else begin - cam_raw_0_bits_wb <= _T_112 | _GEN_57; + cam_raw_0_wb <= _T_112 | _GEN_57; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_bits_rd <= 5'h0; + cam_raw_1_rd <= 5'h0; end else if (cam_wen[1]) begin - if (x_d_bits_i0load) begin - cam_raw_1_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_1_rd <= x_d_i0rd; end else begin - cam_raw_1_bits_rd <= 5'h0; + cam_raw_1_rd <= 5'h0; end end else if (_T_133) begin - cam_raw_1_bits_rd <= 5'h0; + cam_raw_1_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_1_bits_wb <= 1'h0; + cam_raw_1_wb <= 1'h0; end else begin - cam_raw_1_bits_wb <= _T_138 | _GEN_68; + cam_raw_1_wb <= _T_138 | _GEN_68; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_bits_rd <= 5'h0; + cam_raw_2_rd <= 5'h0; end else if (cam_wen[2]) begin - if (x_d_bits_i0load) begin - cam_raw_2_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_2_rd <= x_d_i0rd; end else begin - cam_raw_2_bits_rd <= 5'h0; + cam_raw_2_rd <= 5'h0; end end else if (_T_159) begin - cam_raw_2_bits_rd <= 5'h0; + cam_raw_2_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_2_bits_wb <= 1'h0; + cam_raw_2_wb <= 1'h0; end else begin - cam_raw_2_bits_wb <= _T_164 | _GEN_79; + cam_raw_2_wb <= _T_164 | _GEN_79; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_bits_rd <= 5'h0; + cam_raw_3_rd <= 5'h0; end else if (cam_wen[3]) begin - if (x_d_bits_i0load) begin - cam_raw_3_bits_rd <= x_d_bits_i0rd; + if (x_d_i0load) begin + cam_raw_3_rd <= x_d_i0rd; end else begin - cam_raw_3_bits_rd <= 5'h0; + cam_raw_3_rd <= 5'h0; end end else if (_T_185) begin - cam_raw_3_bits_rd <= 5'h0; + cam_raw_3_rd <= 5'h0; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - cam_raw_3_bits_wb <= 1'h0; + cam_raw_3_wb <= 1'h0; end else begin - cam_raw_3_bits_wb <= _T_190 | _GEN_90; + cam_raw_3_wb <= _T_190 | _GEN_90; end end always @(posedge io_active_clk or posedge reset) begin @@ -48165,30 +48175,30 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0v <= 1'h0; + x_d_i0v <= 1'h0; end else begin - x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d; + x_d_i0v <= i0_rd_en_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwen <= 1'h0; + r_d_csrwen <= 1'h0; end else begin - r_d_bits_csrwen <= x_d_bits_csrwen; + r_d_csrwen <= x_d_csrwen; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_valid <= 1'h0; + r_d_i0valid <= 1'h0; end else begin - r_d_valid <= _T_737 & _T_280; + r_d_i0valid <= _T_737 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwaddr <= 12'h0; + r_d_csrwaddr <= 12'h0; end else begin - r_d_bits_csrwaddr <= x_d_bits_csrwaddr; + r_d_csrwaddr <= x_d_csrwaddr; end end always @(posedge io_active_clk or posedge reset) begin @@ -48244,9 +48254,9 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_csrwonly <= 1'h0; + r_d_csrwonly <= 1'h0; end else begin - r_d_bits_csrwonly <= x_d_bits_csrwonly; + r_d_csrwonly <= x_d_csrwonly; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin @@ -48260,16 +48270,16 @@ end // initial end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwonly <= 1'h0; + x_d_csrwonly <= 1'h0; end else begin - x_d_bits_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; + x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin - wbd_bits_csrwonly <= 1'h0; + wbd_csrwonly <= 1'h0; end else begin - wbd_bits_csrwonly <= r_d_bits_csrwonly; + wbd_csrwonly <= r_d_csrwonly; end end always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin @@ -48409,44 +48419,44 @@ end // initial end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0store <= 1'h0; + r_d_i0store <= 1'h0; end else begin - r_d_bits_i0store <= x_d_bits_i0store; + r_d_i0store <= x_d_i0store; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin - r_d_bits_i0div <= 1'h0; + r_d_i0div <= 1'h0; end else begin - r_d_bits_i0div <= x_d_bits_i0div; + r_d_i0div <= x_d_i0div; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0store <= 1'h0; + x_d_i0store <= 1'h0; end else begin - x_d_bits_i0store <= i0_dp_store & i0_legal_decode_d; + x_d_i0store <= i0_dp_store & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_i0div <= 1'h0; + x_d_i0div <= 1'h0; end else begin - x_d_bits_i0div <= i0_dp_div & i0_legal_decode_d; + x_d_i0div <= i0_dp_div & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwen <= 1'h0; + x_d_csrwen <= 1'h0; end else begin - x_d_bits_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; + x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin - x_d_bits_csrwaddr <= 12'h0; + x_d_csrwaddr <= 12'h0; end else begin - x_d_bits_csrwaddr <= io_dec_i0_instr_d[31:20]; + x_d_csrwaddr <= io_dec_i0_instr_d[31:20]; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -48701,423 +48711,423 @@ module el2_dec_gpr_ctl( wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23] wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23] wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23] - wire _T_95 = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_1 = io_wen0 & _T_95; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_112 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_2 = io_wen0 & _T_112; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_129 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_3 = io_wen0 & _T_129; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_146 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_4 = io_wen0 & _T_146; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_163 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_5 = io_wen0 & _T_163; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_180 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_6 = io_wen0 & _T_180; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_197 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_7 = io_wen0 & _T_197; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_214 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_8 = io_wen0 & _T_214; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_231 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_9 = io_wen0 & _T_231; // @[el2_dec_gpr_ctl.scala 26:28] - wire [9:0] _T_8 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] - wire _T_248 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_10 = io_wen0 & _T_248; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_265 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_11 = io_wen0 & _T_265; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_282 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_12 = io_wen0 & _T_282; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_299 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_13 = io_wen0 & _T_299; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_316 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_14 = io_wen0 & _T_316; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_333 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_15 = io_wen0 & _T_333; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_350 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_16 = io_wen0 & _T_350; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_367 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_17 = io_wen0 & _T_367; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_384 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_18 = io_wen0 & _T_384; // @[el2_dec_gpr_ctl.scala 26:28] - wire [18:0] _T_17 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_8}; // @[Cat.scala 29:58] - wire _T_401 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_19 = io_wen0 & _T_401; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_418 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_20 = io_wen0 & _T_418; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_435 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_21 = io_wen0 & _T_435; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_452 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_22 = io_wen0 & _T_452; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_469 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_23 = io_wen0 & _T_469; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_486 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_24 = io_wen0 & _T_486; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_503 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_25 = io_wen0 & _T_503; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_520 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_26 = io_wen0 & _T_520; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_537 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_27 = io_wen0 & _T_537; // @[el2_dec_gpr_ctl.scala 26:28] - wire [27:0] _T_26 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_17}; // @[Cat.scala 29:58] - wire _T_554 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_28 = io_wen0 & _T_554; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_571 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_29 = io_wen0 & _T_571; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_588 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_30 = io_wen0 & _T_588; // @[el2_dec_gpr_ctl.scala 26:28] - wire _T_605 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 26:40] - wire w0v_31 = io_wen0 & _T_605; // @[el2_dec_gpr_ctl.scala 26:28] - wire [31:0] _T_30 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_26}; // @[Cat.scala 29:58] - wire _T_97 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_1 = io_wen1 & _T_97; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_114 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_2 = io_wen1 & _T_114; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_131 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_3 = io_wen1 & _T_131; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_148 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_4 = io_wen1 & _T_148; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_165 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_5 = io_wen1 & _T_165; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_182 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_6 = io_wen1 & _T_182; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_199 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_7 = io_wen1 & _T_199; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_216 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_8 = io_wen1 & _T_216; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_233 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_9 = io_wen1 & _T_233; // @[el2_dec_gpr_ctl.scala 27:28] - wire [9:0] _T_39 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] - wire _T_250 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_10 = io_wen1 & _T_250; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_267 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_11 = io_wen1 & _T_267; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_284 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_12 = io_wen1 & _T_284; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_301 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_13 = io_wen1 & _T_301; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_318 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_14 = io_wen1 & _T_318; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_335 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_15 = io_wen1 & _T_335; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_352 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_16 = io_wen1 & _T_352; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_369 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_17 = io_wen1 & _T_369; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_386 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_18 = io_wen1 & _T_386; // @[el2_dec_gpr_ctl.scala 27:28] - wire [18:0] _T_48 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_39}; // @[Cat.scala 29:58] - wire _T_403 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_19 = io_wen1 & _T_403; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_420 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_20 = io_wen1 & _T_420; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_437 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_21 = io_wen1 & _T_437; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_454 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_22 = io_wen1 & _T_454; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_471 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_23 = io_wen1 & _T_471; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_488 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_24 = io_wen1 & _T_488; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_505 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_25 = io_wen1 & _T_505; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_522 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_26 = io_wen1 & _T_522; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_539 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_27 = io_wen1 & _T_539; // @[el2_dec_gpr_ctl.scala 27:28] - wire [27:0] _T_57 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_48}; // @[Cat.scala 29:58] - wire _T_556 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_28 = io_wen1 & _T_556; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_573 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_29 = io_wen1 & _T_573; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_590 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_30 = io_wen1 & _T_590; // @[el2_dec_gpr_ctl.scala 27:28] - wire _T_607 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 27:40] - wire w1v_31 = io_wen1 & _T_607; // @[el2_dec_gpr_ctl.scala 27:28] - wire [31:0] _T_61 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_57}; // @[Cat.scala 29:58] - wire [31:0] _T_62 = _T_30 | _T_61; // @[el2_dec_gpr_ctl.scala 23:51] - wire _T_99 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_1 = io_wen2 & _T_99; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_116 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_2 = io_wen2 & _T_116; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_133 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_3 = io_wen2 & _T_133; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_150 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_4 = io_wen2 & _T_150; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_167 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_5 = io_wen2 & _T_167; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_184 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_6 = io_wen2 & _T_184; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_201 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_7 = io_wen2 & _T_201; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_218 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_8 = io_wen2 & _T_218; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_235 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_9 = io_wen2 & _T_235; // @[el2_dec_gpr_ctl.scala 28:28] - wire [9:0] _T_71 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] - wire _T_252 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_10 = io_wen2 & _T_252; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_269 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_11 = io_wen2 & _T_269; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_286 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_12 = io_wen2 & _T_286; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_303 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_13 = io_wen2 & _T_303; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_320 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_14 = io_wen2 & _T_320; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_337 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_15 = io_wen2 & _T_337; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_354 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_16 = io_wen2 & _T_354; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_371 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_17 = io_wen2 & _T_371; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_388 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_18 = io_wen2 & _T_388; // @[el2_dec_gpr_ctl.scala 28:28] - wire [18:0] _T_80 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_71}; // @[Cat.scala 29:58] - wire _T_405 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_19 = io_wen2 & _T_405; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_422 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_20 = io_wen2 & _T_422; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_439 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_21 = io_wen2 & _T_439; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_456 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_22 = io_wen2 & _T_456; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_473 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_23 = io_wen2 & _T_473; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_490 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_24 = io_wen2 & _T_490; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_507 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_25 = io_wen2 & _T_507; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_524 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_26 = io_wen2 & _T_524; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_541 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_27 = io_wen2 & _T_541; // @[el2_dec_gpr_ctl.scala 28:28] - wire [27:0] _T_89 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_80}; // @[Cat.scala 29:58] - wire _T_558 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_28 = io_wen2 & _T_558; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_575 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_29 = io_wen2 & _T_575; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_592 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_30 = io_wen2 & _T_592; // @[el2_dec_gpr_ctl.scala 28:28] - wire _T_609 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 28:40] - wire w2v_31 = io_wen2 & _T_609; // @[el2_dec_gpr_ctl.scala 28:28] - wire [31:0] _T_93 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_89}; // @[Cat.scala 29:58] - wire [31:0] gpr_wr_en = _T_62 | _T_93; // @[el2_dec_gpr_ctl.scala 23:89] - wire [31:0] _T_102 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_103 = _T_102 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_105 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_106 = _T_105 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_107 = _T_103 | _T_106; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_109 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_110 = _T_109 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_119 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_120 = _T_119 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_122 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_123 = _T_122 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_124 = _T_120 | _T_123; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_126 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_127 = _T_126 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_136 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_137 = _T_136 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_139 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_140 = _T_139 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_141 = _T_137 | _T_140; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_143 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_144 = _T_143 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_153 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_154 = _T_153 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_156 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_157 = _T_156 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_158 = _T_154 | _T_157; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_160 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_161 = _T_160 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_170 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_171 = _T_170 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_173 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_174 = _T_173 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_175 = _T_171 | _T_174; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_177 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_178 = _T_177 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_187 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_188 = _T_187 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_190 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_191 = _T_190 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_192 = _T_188 | _T_191; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_194 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_195 = _T_194 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_204 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_205 = _T_204 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_207 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_208 = _T_207 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_209 = _T_205 | _T_208; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_211 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_212 = _T_211 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_221 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_222 = _T_221 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_224 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_225 = _T_224 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_226 = _T_222 | _T_225; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_228 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_229 = _T_228 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_238 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_239 = _T_238 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_241 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_242 = _T_241 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_243 = _T_239 | _T_242; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_245 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_246 = _T_245 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_255 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_256 = _T_255 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_258 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_259 = _T_258 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_260 = _T_256 | _T_259; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_262 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_263 = _T_262 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_272 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_273 = _T_272 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_275 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_276 = _T_275 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_277 = _T_273 | _T_276; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_279 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_280 = _T_279 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_289 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_290 = _T_289 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_292 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_293 = _T_292 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_294 = _T_290 | _T_293; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_296 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_297 = _T_296 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_306 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_307 = _T_306 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_309 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_310 = _T_309 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_311 = _T_307 | _T_310; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_313 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_314 = _T_313 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_323 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_324 = _T_323 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_326 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_327 = _T_326 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_328 = _T_324 | _T_327; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_330 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_331 = _T_330 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_340 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_341 = _T_340 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_343 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_344 = _T_343 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_345 = _T_341 | _T_344; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_347 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_348 = _T_347 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_357 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_358 = _T_357 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_360 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_361 = _T_360 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_362 = _T_358 | _T_361; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_364 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_365 = _T_364 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_374 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_375 = _T_374 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_377 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_378 = _T_377 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_379 = _T_375 | _T_378; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_381 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_382 = _T_381 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_391 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_392 = _T_391 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_394 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_395 = _T_394 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_396 = _T_392 | _T_395; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_398 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_399 = _T_398 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_408 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_409 = _T_408 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_411 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_412 = _T_411 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_413 = _T_409 | _T_412; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_415 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_416 = _T_415 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_425 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_426 = _T_425 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_428 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_429 = _T_428 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_430 = _T_426 | _T_429; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_432 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_433 = _T_432 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_442 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_443 = _T_442 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_445 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_446 = _T_445 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_447 = _T_443 | _T_446; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_449 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_450 = _T_449 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_459 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_460 = _T_459 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_462 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_463 = _T_462 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_464 = _T_460 | _T_463; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_466 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_467 = _T_466 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_476 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_477 = _T_476 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_479 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_480 = _T_479 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_481 = _T_477 | _T_480; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_483 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_484 = _T_483 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_493 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_494 = _T_493 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_496 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_497 = _T_496 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_498 = _T_494 | _T_497; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_500 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_501 = _T_500 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_510 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_511 = _T_510 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_513 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_514 = _T_513 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_515 = _T_511 | _T_514; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_517 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_518 = _T_517 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_527 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_528 = _T_527 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_530 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_531 = _T_530 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_532 = _T_528 | _T_531; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_534 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_535 = _T_534 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_544 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_545 = _T_544 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_547 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_548 = _T_547 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_549 = _T_545 | _T_548; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_551 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_552 = _T_551 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_561 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_562 = _T_561 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_564 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_565 = _T_564 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_566 = _T_562 | _T_565; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_568 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_569 = _T_568 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_578 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_579 = _T_578 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_581 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_582 = _T_581 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_583 = _T_579 | _T_582; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_585 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_586 = _T_585 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_595 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_596 = _T_595 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_598 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_599 = _T_598 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_600 = _T_596 | _T_599; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_602 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_603 = _T_602 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] - wire [31:0] _T_612 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_613 = _T_612 & io_wd0; // @[el2_dec_gpr_ctl.scala 29:37] - wire [31:0] _T_615 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_616 = _T_615 & io_wd1; // @[el2_dec_gpr_ctl.scala 29:66] - wire [31:0] _T_617 = _T_613 | _T_616; // @[el2_dec_gpr_ctl.scala 29:47] - wire [31:0] _T_619 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_620 = _T_619 & io_wd2; // @[el2_dec_gpr_ctl.scala 29:95] + wire _T = io_waddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_1 = io_wen0 & _T; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_2 = io_waddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_1 = io_wen1 & _T_2; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_4 = io_waddr2 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_1 = io_wen2 & _T_4; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_7 = w0v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_8 = _T_7 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_10 = w1v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_11 = _T_10 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_12 = _T_8 | _T_11; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_14 = w2v_1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_15 = _T_14 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_17 = io_waddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_2 = io_wen0 & _T_17; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_19 = io_waddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_2 = io_wen1 & _T_19; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_21 = io_waddr2 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_2 = io_wen2 & _T_21; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_24 = w0v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_25 = _T_24 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_27 = w1v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_28 = _T_27 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_29 = _T_25 | _T_28; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_31 = w2v_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_32 = _T_31 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_34 = io_waddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_3 = io_wen0 & _T_34; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_36 = io_waddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_3 = io_wen1 & _T_36; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_38 = io_waddr2 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_3 = io_wen2 & _T_38; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_41 = w0v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_42 = _T_41 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_44 = w1v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_45 = _T_44 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_46 = _T_42 | _T_45; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_48 = w2v_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_49 = _T_48 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_51 = io_waddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_4 = io_wen0 & _T_51; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_53 = io_waddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_4 = io_wen1 & _T_53; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_55 = io_waddr2 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_4 = io_wen2 & _T_55; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_58 = w0v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_59 = _T_58 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_61 = w1v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_62 = _T_61 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_63 = _T_59 | _T_62; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_65 = w2v_4 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_66 = _T_65 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_68 = io_waddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_5 = io_wen0 & _T_68; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_70 = io_waddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_5 = io_wen1 & _T_70; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_72 = io_waddr2 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_5 = io_wen2 & _T_72; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_75 = w0v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_76 = _T_75 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_78 = w1v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_79 = _T_78 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_80 = _T_76 | _T_79; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_82 = w2v_5 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_83 = _T_82 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_85 = io_waddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_6 = io_wen0 & _T_85; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_87 = io_waddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_6 = io_wen1 & _T_87; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_89 = io_waddr2 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_6 = io_wen2 & _T_89; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_92 = w0v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_93 = _T_92 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_95 = w1v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_96 = _T_95 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_97 = _T_93 | _T_96; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_99 = w2v_6 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_100 = _T_99 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_102 = io_waddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_7 = io_wen0 & _T_102; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_104 = io_waddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_7 = io_wen1 & _T_104; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_106 = io_waddr2 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_7 = io_wen2 & _T_106; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_109 = w0v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_110 = _T_109 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_112 = w1v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_113 = _T_112 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_114 = _T_110 | _T_113; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_116 = w2v_7 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_117 = _T_116 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_119 = io_waddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_8 = io_wen0 & _T_119; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_121 = io_waddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_8 = io_wen1 & _T_121; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_123 = io_waddr2 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_8 = io_wen2 & _T_123; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_126 = w0v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_127 = _T_126 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_129 = w1v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_130 = _T_129 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_131 = _T_127 | _T_130; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_133 = w2v_8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_134 = _T_133 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_136 = io_waddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_9 = io_wen0 & _T_136; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_138 = io_waddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_9 = io_wen1 & _T_138; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_140 = io_waddr2 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_9 = io_wen2 & _T_140; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_143 = w0v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_144 = _T_143 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_146 = w1v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_147 = _T_146 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_148 = _T_144 | _T_147; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_150 = w2v_9 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_151 = _T_150 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_153 = io_waddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_10 = io_wen0 & _T_153; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_155 = io_waddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_10 = io_wen1 & _T_155; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_157 = io_waddr2 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_10 = io_wen2 & _T_157; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_160 = w0v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_161 = _T_160 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_163 = w1v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_164 = _T_163 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_165 = _T_161 | _T_164; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_167 = w2v_10 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_168 = _T_167 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_170 = io_waddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_11 = io_wen0 & _T_170; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_172 = io_waddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_11 = io_wen1 & _T_172; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_174 = io_waddr2 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_11 = io_wen2 & _T_174; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_177 = w0v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = _T_177 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_180 = w1v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_181 = _T_180 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_182 = _T_178 | _T_181; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_184 = w2v_11 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_185 = _T_184 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_187 = io_waddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_12 = io_wen0 & _T_187; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_189 = io_waddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_12 = io_wen1 & _T_189; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_191 = io_waddr2 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_12 = io_wen2 & _T_191; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_194 = w0v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = _T_194 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_197 = w1v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_198 = _T_197 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_199 = _T_195 | _T_198; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_201 = w2v_12 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_202 = _T_201 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_204 = io_waddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_13 = io_wen0 & _T_204; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_206 = io_waddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_13 = io_wen1 & _T_206; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_208 = io_waddr2 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_13 = io_wen2 & _T_208; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_211 = w0v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_211 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_214 = w1v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_215 = _T_214 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_216 = _T_212 | _T_215; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_218 = w2v_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_219 = _T_218 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_221 = io_waddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_14 = io_wen0 & _T_221; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_223 = io_waddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_14 = io_wen1 & _T_223; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_225 = io_waddr2 == 5'he; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_14 = io_wen2 & _T_225; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_228 = w0v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_229 = _T_228 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_231 = w1v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_232 = _T_231 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_233 = _T_229 | _T_232; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_235 = w2v_14 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_236 = _T_235 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_238 = io_waddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_15 = io_wen0 & _T_238; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_240 = io_waddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_15 = io_wen1 & _T_240; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_242 = io_waddr2 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_15 = io_wen2 & _T_242; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_245 = w0v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = _T_245 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_248 = w1v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_249 = _T_248 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_250 = _T_246 | _T_249; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_252 = w2v_15 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_253 = _T_252 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_255 = io_waddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_16 = io_wen0 & _T_255; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_257 = io_waddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_16 = io_wen1 & _T_257; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_259 = io_waddr2 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_16 = io_wen2 & _T_259; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_262 = w0v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_263 = _T_262 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_265 = w1v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_266 = _T_265 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_267 = _T_263 | _T_266; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_269 = w2v_16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_270 = _T_269 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_272 = io_waddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_17 = io_wen0 & _T_272; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_274 = io_waddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_17 = io_wen1 & _T_274; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_276 = io_waddr2 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_17 = io_wen2 & _T_276; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_279 = w0v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_280 = _T_279 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_282 = w1v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_283 = _T_282 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_284 = _T_280 | _T_283; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_286 = w2v_17 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_287 = _T_286 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_289 = io_waddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_18 = io_wen0 & _T_289; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_291 = io_waddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_18 = io_wen1 & _T_291; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_293 = io_waddr2 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_18 = io_wen2 & _T_293; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_296 = w0v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_297 = _T_296 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_299 = w1v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_300 = _T_299 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_301 = _T_297 | _T_300; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_303 = w2v_18 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_304 = _T_303 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_306 = io_waddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_19 = io_wen0 & _T_306; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_308 = io_waddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_19 = io_wen1 & _T_308; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_310 = io_waddr2 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_19 = io_wen2 & _T_310; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_313 = w0v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_314 = _T_313 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_316 = w1v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_317 = _T_316 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_318 = _T_314 | _T_317; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_320 = w2v_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_321 = _T_320 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_323 = io_waddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_20 = io_wen0 & _T_323; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_325 = io_waddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_20 = io_wen1 & _T_325; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_327 = io_waddr2 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_20 = io_wen2 & _T_327; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_330 = w0v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_331 = _T_330 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_333 = w1v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_334 = _T_333 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_335 = _T_331 | _T_334; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_337 = w2v_20 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_338 = _T_337 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_340 = io_waddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_21 = io_wen0 & _T_340; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_342 = io_waddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_21 = io_wen1 & _T_342; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_344 = io_waddr2 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_21 = io_wen2 & _T_344; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_347 = w0v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_348 = _T_347 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_350 = w1v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_351 = _T_350 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_352 = _T_348 | _T_351; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_354 = w2v_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_355 = _T_354 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_357 = io_waddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_22 = io_wen0 & _T_357; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_359 = io_waddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_22 = io_wen1 & _T_359; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_361 = io_waddr2 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_22 = io_wen2 & _T_361; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_364 = w0v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_365 = _T_364 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_367 = w1v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_368 = _T_367 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_369 = _T_365 | _T_368; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_371 = w2v_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_372 = _T_371 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_374 = io_waddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_23 = io_wen0 & _T_374; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_376 = io_waddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_23 = io_wen1 & _T_376; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_378 = io_waddr2 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_23 = io_wen2 & _T_378; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_381 = w0v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_382 = _T_381 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_384 = w1v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_385 = _T_384 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_386 = _T_382 | _T_385; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_388 = w2v_23 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_389 = _T_388 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_391 = io_waddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_24 = io_wen0 & _T_391; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_393 = io_waddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_24 = io_wen1 & _T_393; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_395 = io_waddr2 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_24 = io_wen2 & _T_395; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_398 = w0v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_399 = _T_398 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_401 = w1v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_402 = _T_401 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_403 = _T_399 | _T_402; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_405 = w2v_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_406 = _T_405 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_408 = io_waddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_25 = io_wen0 & _T_408; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_410 = io_waddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_25 = io_wen1 & _T_410; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_412 = io_waddr2 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_25 = io_wen2 & _T_412; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_415 = w0v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_416 = _T_415 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_418 = w1v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_419 = _T_418 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_420 = _T_416 | _T_419; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_422 = w2v_25 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_423 = _T_422 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_425 = io_waddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_26 = io_wen0 & _T_425; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_427 = io_waddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_26 = io_wen1 & _T_427; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_429 = io_waddr2 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_26 = io_wen2 & _T_429; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_432 = w0v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_433 = _T_432 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_435 = w1v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_436 = _T_435 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_437 = _T_433 | _T_436; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_439 = w2v_26 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_440 = _T_439 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_442 = io_waddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_27 = io_wen0 & _T_442; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_444 = io_waddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_27 = io_wen1 & _T_444; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_446 = io_waddr2 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_27 = io_wen2 & _T_446; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_449 = w0v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_450 = _T_449 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_452 = w1v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_453 = _T_452 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_454 = _T_450 | _T_453; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_456 = w2v_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_457 = _T_456 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_459 = io_waddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_28 = io_wen0 & _T_459; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_461 = io_waddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_28 = io_wen1 & _T_461; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_463 = io_waddr2 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_28 = io_wen2 & _T_463; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_466 = w0v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_467 = _T_466 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_469 = w1v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_470 = _T_469 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_471 = _T_467 | _T_470; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_473 = w2v_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_474 = _T_473 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_476 = io_waddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_29 = io_wen0 & _T_476; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_478 = io_waddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_29 = io_wen1 & _T_478; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_480 = io_waddr2 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_29 = io_wen2 & _T_480; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_483 = w0v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_484 = _T_483 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_486 = w1v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_487 = _T_486 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_488 = _T_484 | _T_487; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_490 = w2v_29 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_491 = _T_490 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_493 = io_waddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_30 = io_wen0 & _T_493; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_495 = io_waddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_30 = io_wen1 & _T_495; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_497 = io_waddr2 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_30 = io_wen2 & _T_497; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_500 = w0v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_501 = _T_500 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_503 = w1v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_504 = _T_503 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_505 = _T_501 | _T_504; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_507 = w2v_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_508 = _T_507 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire _T_510 = io_waddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 35:40] + wire w0v_31 = io_wen0 & _T_510; // @[el2_dec_gpr_ctl.scala 35:28] + wire _T_512 = io_waddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:40] + wire w1v_31 = io_wen1 & _T_512; // @[el2_dec_gpr_ctl.scala 36:28] + wire _T_514 = io_waddr2 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:40] + wire w2v_31 = io_wen2 & _T_514; // @[el2_dec_gpr_ctl.scala 37:28] + wire [31:0] _T_517 = w0v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_518 = _T_517 & io_wd0; // @[el2_dec_gpr_ctl.scala 38:37] + wire [31:0] _T_520 = w1v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_521 = _T_520 & io_wd1; // @[el2_dec_gpr_ctl.scala 38:66] + wire [31:0] _T_522 = _T_518 | _T_521; // @[el2_dec_gpr_ctl.scala 38:47] + wire [31:0] _T_524 = w2v_31 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_525 = _T_524 & io_wd2; // @[el2_dec_gpr_ctl.scala 38:95] + wire [9:0] _T_535 = {w0v_9,w0v_8,w0v_7,w0v_6,w0v_5,w0v_4,w0v_3,w0v_2,w0v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_544 = {w0v_18,w0v_17,w0v_16,w0v_15,w0v_14,w0v_13,w0v_12,w0v_11,w0v_10,_T_535}; // @[Cat.scala 29:58] + wire [27:0] _T_553 = {w0v_27,w0v_26,w0v_25,w0v_24,w0v_23,w0v_22,w0v_21,w0v_20,w0v_19,_T_544}; // @[Cat.scala 29:58] + wire [31:0] _T_557 = {w0v_31,w0v_30,w0v_29,w0v_28,_T_553}; // @[Cat.scala 29:58] + wire [9:0] _T_566 = {w1v_9,w1v_8,w1v_7,w1v_6,w1v_5,w1v_4,w1v_3,w1v_2,w1v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_575 = {w1v_18,w1v_17,w1v_16,w1v_15,w1v_14,w1v_13,w1v_12,w1v_11,w1v_10,_T_566}; // @[Cat.scala 29:58] + wire [27:0] _T_584 = {w1v_27,w1v_26,w1v_25,w1v_24,w1v_23,w1v_22,w1v_21,w1v_20,w1v_19,_T_575}; // @[Cat.scala 29:58] + wire [31:0] _T_588 = {w1v_31,w1v_30,w1v_29,w1v_28,_T_584}; // @[Cat.scala 29:58] + wire [31:0] _T_589 = _T_557 | _T_588; // @[el2_dec_gpr_ctl.scala 40:51] + wire [9:0] _T_598 = {w2v_9,w2v_8,w2v_7,w2v_6,w2v_5,w2v_4,w2v_3,w2v_2,w2v_1,1'h0}; // @[Cat.scala 29:58] + wire [18:0] _T_607 = {w2v_18,w2v_17,w2v_16,w2v_15,w2v_14,w2v_13,w2v_12,w2v_11,w2v_10,_T_598}; // @[Cat.scala 29:58] + wire [27:0] _T_616 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_607}; // @[Cat.scala 29:58] + wire [31:0] _T_620 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_616}; // @[Cat.scala 29:58] + wire [31:0] gpr_wr_en = _T_589 | _T_620; // @[el2_dec_gpr_ctl.scala 40:89] reg [31:0] gpr_out_1; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_2; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_3; // @[el2_lib.scala 514:16] @@ -49149,37 +49159,37 @@ module el2_dec_gpr_ctl( reg [31:0] gpr_out_29; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_30; // @[el2_lib.scala 514:16] reg [31:0] gpr_out_31; // @[el2_lib.scala 514:16] - wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 36:49] - wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 36:49] + wire _T_684 = io_raddr0 == 5'h1; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_686 = io_raddr0 == 5'h2; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_688 = io_raddr0 == 5'h3; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_690 = io_raddr0 == 5'h4; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_692 = io_raddr0 == 5'h5; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_694 = io_raddr0 == 5'h6; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_696 = io_raddr0 == 5'h7; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_698 = io_raddr0 == 5'h8; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_700 = io_raddr0 == 5'h9; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_702 = io_raddr0 == 5'ha; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_704 = io_raddr0 == 5'hb; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_706 = io_raddr0 == 5'hc; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_708 = io_raddr0 == 5'hd; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_710 = io_raddr0 == 5'he; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_712 = io_raddr0 == 5'hf; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_714 = io_raddr0 == 5'h10; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_716 = io_raddr0 == 5'h11; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_718 = io_raddr0 == 5'h12; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_720 = io_raddr0 == 5'h13; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_722 = io_raddr0 == 5'h14; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_724 = io_raddr0 == 5'h15; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_726 = io_raddr0 == 5'h16; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_728 = io_raddr0 == 5'h17; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_730 = io_raddr0 == 5'h18; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_732 = io_raddr0 == 5'h19; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_734 = io_raddr0 == 5'h1a; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_736 = io_raddr0 == 5'h1b; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_738 = io_raddr0 == 5'h1c; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_740 = io_raddr0 == 5'h1d; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_742 = io_raddr0 == 5'h1e; // @[el2_dec_gpr_ctl.scala 47:49] + wire _T_744 = io_raddr0 == 5'h1f; // @[el2_dec_gpr_ctl.scala 47:49] wire [31:0] _T_746 = _T_684 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_747 = _T_686 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_748 = _T_688 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] @@ -49240,37 +49250,37 @@ module el2_dec_gpr_ctl( wire [31:0] _T_803 = _T_802 | _T_773; // @[Mux.scala 27:72] wire [31:0] _T_804 = _T_803 | _T_774; // @[Mux.scala 27:72] wire [31:0] _T_805 = _T_804 | _T_775; // @[Mux.scala 27:72] - wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 37:49] - wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 37:49] + wire _T_808 = io_raddr1 == 5'h1; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_810 = io_raddr1 == 5'h2; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_812 = io_raddr1 == 5'h3; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_814 = io_raddr1 == 5'h4; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_816 = io_raddr1 == 5'h5; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_818 = io_raddr1 == 5'h6; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_820 = io_raddr1 == 5'h7; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_822 = io_raddr1 == 5'h8; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_824 = io_raddr1 == 5'h9; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_826 = io_raddr1 == 5'ha; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_828 = io_raddr1 == 5'hb; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_830 = io_raddr1 == 5'hc; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_832 = io_raddr1 == 5'hd; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_834 = io_raddr1 == 5'he; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_836 = io_raddr1 == 5'hf; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_838 = io_raddr1 == 5'h10; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_840 = io_raddr1 == 5'h11; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_842 = io_raddr1 == 5'h12; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_844 = io_raddr1 == 5'h13; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_846 = io_raddr1 == 5'h14; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_848 = io_raddr1 == 5'h15; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_850 = io_raddr1 == 5'h16; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_852 = io_raddr1 == 5'h17; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_854 = io_raddr1 == 5'h18; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_856 = io_raddr1 == 5'h19; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_858 = io_raddr1 == 5'h1a; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_860 = io_raddr1 == 5'h1b; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_862 = io_raddr1 == 5'h1c; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_864 = io_raddr1 == 5'h1d; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_866 = io_raddr1 == 5'h1e; // @[el2_dec_gpr_ctl.scala 48:49] + wire _T_868 = io_raddr1 == 5'h1f; // @[el2_dec_gpr_ctl.scala 48:49] wire [31:0] _T_870 = _T_808 ? gpr_out_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_871 = _T_810 ? gpr_out_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_872 = _T_812 ? gpr_out_3 : 32'h0; // @[Mux.scala 27:72] @@ -49517,8 +49527,8 @@ module el2_dec_gpr_ctl( .io_en(rvclkhdr_30_io_en), .io_scan_mode(rvclkhdr_30_io_scan_mode) ); - assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 21:9 el2_dec_gpr_ctl.scala 36:9] - assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 22:9 el2_dec_gpr_ctl.scala 37:9] + assign io_rd0 = _T_805 | _T_776; // @[el2_dec_gpr_ctl.scala 31:9 el2_dec_gpr_ctl.scala 47:9] + assign io_rd1 = _T_929 | _T_900; // @[el2_dec_gpr_ctl.scala 32:9 el2_dec_gpr_ctl.scala 48:9] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_io_en = gpr_wr_en[1]; // @[el2_lib.scala 511:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] @@ -49813,217 +49823,217 @@ end // initial if (reset) begin gpr_out_1 <= 32'h0; end else begin - gpr_out_1 <= _T_107 | _T_110; + gpr_out_1 <= _T_12 | _T_15; end end always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin gpr_out_2 <= 32'h0; end else begin - gpr_out_2 <= _T_124 | _T_127; + gpr_out_2 <= _T_29 | _T_32; end end always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin gpr_out_3 <= 32'h0; end else begin - gpr_out_3 <= _T_141 | _T_144; + gpr_out_3 <= _T_46 | _T_49; end end always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin gpr_out_4 <= 32'h0; end else begin - gpr_out_4 <= _T_158 | _T_161; + gpr_out_4 <= _T_63 | _T_66; end end always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin if (reset) begin gpr_out_5 <= 32'h0; end else begin - gpr_out_5 <= _T_175 | _T_178; + gpr_out_5 <= _T_80 | _T_83; end end always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin gpr_out_6 <= 32'h0; end else begin - gpr_out_6 <= _T_192 | _T_195; + gpr_out_6 <= _T_97 | _T_100; end end always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin gpr_out_7 <= 32'h0; end else begin - gpr_out_7 <= _T_209 | _T_212; + gpr_out_7 <= _T_114 | _T_117; end end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin gpr_out_8 <= 32'h0; end else begin - gpr_out_8 <= _T_226 | _T_229; + gpr_out_8 <= _T_131 | _T_134; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin gpr_out_9 <= 32'h0; end else begin - gpr_out_9 <= _T_243 | _T_246; + gpr_out_9 <= _T_148 | _T_151; end end always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin gpr_out_10 <= 32'h0; end else begin - gpr_out_10 <= _T_260 | _T_263; + gpr_out_10 <= _T_165 | _T_168; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin gpr_out_11 <= 32'h0; end else begin - gpr_out_11 <= _T_277 | _T_280; + gpr_out_11 <= _T_182 | _T_185; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin if (reset) begin gpr_out_12 <= 32'h0; end else begin - gpr_out_12 <= _T_294 | _T_297; + gpr_out_12 <= _T_199 | _T_202; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin gpr_out_13 <= 32'h0; end else begin - gpr_out_13 <= _T_311 | _T_314; + gpr_out_13 <= _T_216 | _T_219; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin gpr_out_14 <= 32'h0; end else begin - gpr_out_14 <= _T_328 | _T_331; + gpr_out_14 <= _T_233 | _T_236; end end always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin if (reset) begin gpr_out_15 <= 32'h0; end else begin - gpr_out_15 <= _T_345 | _T_348; + gpr_out_15 <= _T_250 | _T_253; end end always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin if (reset) begin gpr_out_16 <= 32'h0; end else begin - gpr_out_16 <= _T_362 | _T_365; + gpr_out_16 <= _T_267 | _T_270; end end always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin if (reset) begin gpr_out_17 <= 32'h0; end else begin - gpr_out_17 <= _T_379 | _T_382; + gpr_out_17 <= _T_284 | _T_287; end end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin gpr_out_18 <= 32'h0; end else begin - gpr_out_18 <= _T_396 | _T_399; + gpr_out_18 <= _T_301 | _T_304; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin gpr_out_19 <= 32'h0; end else begin - gpr_out_19 <= _T_413 | _T_416; + gpr_out_19 <= _T_318 | _T_321; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin gpr_out_20 <= 32'h0; end else begin - gpr_out_20 <= _T_430 | _T_433; + gpr_out_20 <= _T_335 | _T_338; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin if (reset) begin gpr_out_21 <= 32'h0; end else begin - gpr_out_21 <= _T_447 | _T_450; + gpr_out_21 <= _T_352 | _T_355; end end always @(posedge rvclkhdr_21_io_l1clk or posedge reset) begin if (reset) begin gpr_out_22 <= 32'h0; end else begin - gpr_out_22 <= _T_464 | _T_467; + gpr_out_22 <= _T_369 | _T_372; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin if (reset) begin gpr_out_23 <= 32'h0; end else begin - gpr_out_23 <= _T_481 | _T_484; + gpr_out_23 <= _T_386 | _T_389; end end always @(posedge rvclkhdr_23_io_l1clk or posedge reset) begin if (reset) begin gpr_out_24 <= 32'h0; end else begin - gpr_out_24 <= _T_498 | _T_501; + gpr_out_24 <= _T_403 | _T_406; end end always @(posedge rvclkhdr_24_io_l1clk or posedge reset) begin if (reset) begin gpr_out_25 <= 32'h0; end else begin - gpr_out_25 <= _T_515 | _T_518; + gpr_out_25 <= _T_420 | _T_423; end end always @(posedge rvclkhdr_25_io_l1clk or posedge reset) begin if (reset) begin gpr_out_26 <= 32'h0; end else begin - gpr_out_26 <= _T_532 | _T_535; + gpr_out_26 <= _T_437 | _T_440; end end always @(posedge rvclkhdr_26_io_l1clk or posedge reset) begin if (reset) begin gpr_out_27 <= 32'h0; end else begin - gpr_out_27 <= _T_549 | _T_552; + gpr_out_27 <= _T_454 | _T_457; end end always @(posedge rvclkhdr_27_io_l1clk or posedge reset) begin if (reset) begin gpr_out_28 <= 32'h0; end else begin - gpr_out_28 <= _T_566 | _T_569; + gpr_out_28 <= _T_471 | _T_474; end end always @(posedge rvclkhdr_28_io_l1clk or posedge reset) begin if (reset) begin gpr_out_29 <= 32'h0; end else begin - gpr_out_29 <= _T_583 | _T_586; + gpr_out_29 <= _T_488 | _T_491; end end always @(posedge rvclkhdr_29_io_l1clk or posedge reset) begin if (reset) begin gpr_out_30 <= 32'h0; end else begin - gpr_out_30 <= _T_600 | _T_603; + gpr_out_30 <= _T_505 | _T_508; end end always @(posedge rvclkhdr_30_io_l1clk or posedge reset) begin if (reset) begin gpr_out_31 <= 32'h0; end else begin - gpr_out_31 <= _T_617 | _T_620; + gpr_out_31 <= _T_522 | _T_525; end end endmodule @@ -50098,7 +50108,7 @@ module el2_dec_timer_ctl( wire _T_10 = ~io_internal_dbg_halt_timers; // @[el2_dec_tlu_ctl.scala 2765:167] wire mitcnt0_inc_ok = _T_9 & _T_10; // @[el2_dec_tlu_ctl.scala 2765:165] wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[el2_dec_tlu_ctl.scala 2766:29] - wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:60] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[el2_dec_tlu_ctl.scala 2768:59] wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[el2_dec_tlu_ctl.scala 2775:66] wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[el2_dec_tlu_ctl.scala 2775:43] reg [2:0] _T_66; // @[el2_dec_tlu_ctl.scala 2830:46] @@ -50343,28 +50353,28 @@ module csr_tlu( output io_dec_tlu_ic_diag_pkt_icache_wr_valid, input io_ifu_ic_debug_rd_data_valid, output io_trigger_pkt_any_0_select, - output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_match_pkt, output io_trigger_pkt_any_0_store, output io_trigger_pkt_any_0_load, output io_trigger_pkt_any_0_execute, output io_trigger_pkt_any_0_m, output [31:0] io_trigger_pkt_any_0_tdata2, output io_trigger_pkt_any_1_select, - output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_match_pkt, output io_trigger_pkt_any_1_store, output io_trigger_pkt_any_1_load, output io_trigger_pkt_any_1_execute, output io_trigger_pkt_any_1_m, output [31:0] io_trigger_pkt_any_1_tdata2, output io_trigger_pkt_any_2_select, - output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_match_pkt, output io_trigger_pkt_any_2_store, output io_trigger_pkt_any_2_load, output io_trigger_pkt_any_2_execute, output io_trigger_pkt_any_2_m, output [31:0] io_trigger_pkt_any_2_tdata2, output io_trigger_pkt_any_3_select, - output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_match_pkt, output io_trigger_pkt_any_3_store, output io_trigger_pkt_any_3_load, output io_trigger_pkt_any_3_execute, @@ -50441,7 +50451,7 @@ module csr_tlu( output io_dec_tlu_external_ldfwd_disable, output [2:0] io_dec_tlu_dma_qos_prty, input [31:0] io_dec_illegal_inst, - input io_lsu_error_pkt_r_bits_mscause, + input [3:0] io_lsu_error_pkt_r_bits_mscause, input io_mexintpend, input [30:0] io_exu_npc_r, input io_mpc_reset_run_req, @@ -50877,7 +50887,7 @@ module csr_tlu( wire [31:0] _T_533 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] wire [31:0] _GEN_12 = {{31'd0}, _T_531}; // @[el2_dec_tlu_ctl.scala 1946:61] wire [31:0] _T_534 = _GEN_12 & _T_533; // @[el2_dec_tlu_ctl.scala 1946:61] - wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1455:41 el2_dec_tlu_ctl.scala 1946:15] + wire mice_ce_req = _T_534[0]; // @[el2_dec_tlu_ctl.scala 1946:15] wire ce_int = _T_61 | mice_ce_req; // @[el2_dec_tlu_ctl.scala 1570:47] wire [2:0] _T_63 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_65 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] @@ -51007,14 +51017,14 @@ module csr_tlu( wire _T_237 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[el2_dec_tlu_ctl.scala 1741:57] wire [3:0] _T_238 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] wire [3:0] ifu_mscause = _T_237 ? 4'h9 : _T_238; // @[el2_dec_tlu_ctl.scala 1741:25] - wire _T_243 = io_lsu_i0_exc_r & io_lsu_error_pkt_r_bits_mscause; // @[Mux.scala 27:72] + wire [3:0] _T_243 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] wire [1:0] _T_245 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [3:0] _T_246 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] - wire _T_247 = _T_243 | io_i0_trigger_hit_r; // @[Mux.scala 27:72] - wire [1:0] _GEN_13 = {{1'd0}, _T_247}; // @[Mux.scala 27:72] - wire [1:0] _T_248 = _GEN_13 | _T_245; // @[Mux.scala 27:72] - wire [3:0] _GEN_14 = {{2'd0}, _T_248}; // @[Mux.scala 27:72] - wire [3:0] mscause_type = _GEN_14 | _T_246; // @[Mux.scala 27:72] + wire [3:0] _GEN_13 = {{3'd0}, io_i0_trigger_hit_r}; // @[Mux.scala 27:72] + wire [3:0] _T_247 = _T_243 | _GEN_13; // @[Mux.scala 27:72] + wire [3:0] _GEN_14 = {{2'd0}, _T_245}; // @[Mux.scala 27:72] + wire [3:0] _T_248 = _T_247 | _GEN_14; // @[Mux.scala 27:72] + wire [3:0] mscause_type = _T_248 | _T_246; // @[Mux.scala 27:72] wire _T_252 = wr_mscause_r & _T_15; // @[el2_dec_tlu_ctl.scala 1752:19] wire _T_255 = ~wr_mscause_r; // @[el2_dec_tlu_ctl.scala 1753:6] wire _T_257 = _T_255 & _T_15; // @[el2_dec_tlu_ctl.scala 1753:20] @@ -52550,28 +52560,28 @@ module csr_tlu( assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[el2_dec_tlu_ctl.scala 2243:42] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[el2_dec_tlu_ctl.scala 2244:42] assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_0_match_ = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[el2_dec_tlu_ctl.scala 2312:36] assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[el2_dec_tlu_ctl.scala 2313:36] assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[el2_dec_tlu_ctl.scala 2326:53] assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_1_match_ = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[el2_dec_tlu_ctl.scala 2312:36] assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[el2_dec_tlu_ctl.scala 2313:36] assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[el2_dec_tlu_ctl.scala 2326:53] assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_2_match_ = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[el2_dec_tlu_ctl.scala 2312:36] assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[el2_dec_tlu_ctl.scala 2313:36] assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[el2_dec_tlu_ctl.scala 2326:53] assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[el2_dec_tlu_ctl.scala 2308:36] - assign io_trigger_pkt_any_3_match_ = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:36] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[el2_dec_tlu_ctl.scala 2309:39] assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[el2_dec_tlu_ctl.scala 2310:36] assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[el2_dec_tlu_ctl.scala 2311:36] assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[el2_dec_tlu_ctl.scala 2312:36] @@ -54219,8 +54229,8 @@ module el2_dec_tlu_ctl( input io_lsu_error_pkt_r_bits_single_ecc_error, input io_lsu_error_pkt_r_bits_inst_type, input io_lsu_error_pkt_r_bits_exc_type, - input io_lsu_error_pkt_r_bits_mscause, - input io_lsu_error_pkt_r_bits_addr, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, input io_lsu_single_ecc_error_incr, input io_dec_pause_state, input io_lsu_imprecise_error_store_any, @@ -54273,28 +54283,28 @@ module el2_dec_tlu_ctl( input io_lsu_idle_any, input io_dec_div_active, output io_trigger_pkt_any_0_select, - output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_match_pkt, output io_trigger_pkt_any_0_store, output io_trigger_pkt_any_0_load, output io_trigger_pkt_any_0_execute, output io_trigger_pkt_any_0_m, output [31:0] io_trigger_pkt_any_0_tdata2, output io_trigger_pkt_any_1_select, - output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_match_pkt, output io_trigger_pkt_any_1_store, output io_trigger_pkt_any_1_load, output io_trigger_pkt_any_1_execute, output io_trigger_pkt_any_1_m, output [31:0] io_trigger_pkt_any_1_tdata2, output io_trigger_pkt_any_2_select, - output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_match_pkt, output io_trigger_pkt_any_2_store, output io_trigger_pkt_any_2_load, output io_trigger_pkt_any_2_execute, output io_trigger_pkt_any_2_m, output [31:0] io_trigger_pkt_any_2_tdata2, output io_trigger_pkt_any_3_select, - output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_match_pkt, output io_trigger_pkt_any_3_store, output io_trigger_pkt_any_3_load, output io_trigger_pkt_any_3_execute, @@ -54330,11 +54340,11 @@ module el2_dec_tlu_ctl( output [31:0] io_dec_csr_rddata_d, output io_dec_csr_legal_d, output io_dec_tlu_br0_r_pkt_valid, - output [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - output io_dec_tlu_br0_r_pkt_bits_br_error, - output io_dec_tlu_br0_r_pkt_bits_br_start_error, - output io_dec_tlu_br0_r_pkt_bits_way, - output io_dec_tlu_br0_r_pkt_bits_middle, + output [1:0] io_dec_tlu_br0_r_pkt_hist, + output io_dec_tlu_br0_r_pkt_br_error, + output io_dec_tlu_br0_r_pkt_br_start_error, + output io_dec_tlu_br0_r_pkt_way, + output io_dec_tlu_br0_r_pkt_middle, output io_dec_tlu_i0_kill_writeb_wb, output io_dec_tlu_flush_lower_wb, output io_dec_tlu_i0_commit_cmt, @@ -54500,28 +54510,28 @@ module el2_dec_tlu_ctl( wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_ifu_ic_debug_rd_data_valid; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 897:17] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 897:17] @@ -54598,7 +54608,7 @@ module el2_dec_tlu_ctl( wire csr_io_dec_tlu_external_ldfwd_disable; // @[el2_dec_tlu_ctl.scala 897:17] wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[el2_dec_tlu_ctl.scala 897:17] wire [31:0] csr_io_dec_illegal_inst; // @[el2_dec_tlu_ctl.scala 897:17] - wire csr_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 897:17] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_mexintpend; // @[el2_dec_tlu_ctl.scala 897:17] wire [30:0] csr_io_exu_npc_r; // @[el2_dec_tlu_ctl.scala 897:17] wire csr_io_mpc_reset_run_req; // @[el2_dec_tlu_ctl.scala 897:17] @@ -54834,7 +54844,7 @@ module el2_dec_tlu_ctl( wire i_cpu_run_req_sync = syncro_ff[2]; // @[el2_dec_tlu_ctl.scala 386:59] wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[el2_dec_tlu_ctl.scala 387:51] wire mpc_debug_run_req_sync = syncro_ff[0]; // @[el2_dec_tlu_ctl.scala 388:51] - wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 345:41 el2_dec_tlu_ctl.scala 1083:31] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[el2_dec_tlu_ctl.scala 1083:31] reg lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 693:74] wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[el2_dec_tlu_ctl.scala 392:61] reg e5_valid; // @[el2_dec_tlu_ctl.scala 404:89] @@ -54859,11 +54869,11 @@ module el2_dec_tlu_ctl( wire _T_44 = take_ext_int_start_d3 & _T_43; // @[el2_dec_tlu_ctl.scala 429:140] wire nmi_int_detected = _T_42 | _T_44; // @[el2_dec_tlu_ctl.scala 429:116] wire _T_631 = ~io_dec_csr_stall_int_ff; // @[el2_dec_tlu_ctl.scala 803:22] - wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 344:41 el2_dec_tlu_ctl.scala 1082:31] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 1082:31] wire _T_632 = _T_631 & mstatus_mie_ns; // @[el2_dec_tlu_ctl.scala 803:47] - wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 350:41 el2_dec_tlu_ctl.scala 1088:31] + wire [5:0] mip = csr_io_mip; // @[el2_dec_tlu_ctl.scala 1088:31] wire _T_634 = _T_632 & mip[1]; // @[el2_dec_tlu_ctl.scala 803:64] - wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 339:41 el2_dec_tlu_ctl.scala 1077:31] + wire [5:0] mie_ns = csr_io_mie_ns; // @[el2_dec_tlu_ctl.scala 1077:31] wire timer_int_ready = _T_634 & mie_ns[1]; // @[el2_dec_tlu_ctl.scala 803:82] wire _T_391 = nmi_int_detected | timer_int_ready; // @[el2_dec_tlu_ctl.scala 680:65] wire _T_628 = _T_632 & mip[0]; // @[el2_dec_tlu_ctl.scala 802:64] @@ -54919,7 +54929,7 @@ module el2_dec_tlu_ctl( reg ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 752:58] wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[el2_dec_tlu_ctl.scala 503:126] reg debug_halt_req_f; // @[el2_dec_tlu_ctl.scala 535:81] - wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 342:57 el2_dec_tlu_ctl.scala 1080:31] + wire force_halt = csr_io_force_halt; // @[el2_dec_tlu_ctl.scala 1080:31] reg lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 531:89] wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[el2_dec_tlu_ctl.scala 497:47] wire _T_143 = _T_142 & io_ifu_miss_state_idle; // @[el2_dec_tlu_ctl.scala 497:64] @@ -54960,7 +54970,7 @@ module el2_dec_tlu_ctl( wire _T_167 = ~dbg_tlu_halted; // @[el2_dec_tlu_ctl.scala 514:67] wire _T_168 = debug_halt_req_f & _T_167; // @[el2_dec_tlu_ctl.scala 514:65] wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[el2_dec_tlu_ctl.scala 514:45] - wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 348:41 el2_dec_tlu_ctl.scala 1086:31] + wire [15:0] dcsr = csr_io_dcsr; // @[el2_dec_tlu_ctl.scala 1086:31] wire _T_157 = ~dcsr[2]; // @[el2_dec_tlu_ctl.scala 506:100] wire _T_158 = debug_resume_req_f & _T_157; // @[el2_dec_tlu_ctl.scala 506:98] wire _T_159 = ~_T_158; // @[el2_dec_tlu_ctl.scala 506:77] @@ -54978,7 +54988,7 @@ module el2_dec_tlu_ctl( wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[el2_dec_tlu_ctl.scala 649:54] wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[el2_dec_tlu_ctl.scala 649:79] wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[el2_dec_tlu_ctl.scala 665:49] - wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 346:41 el2_dec_tlu_ctl.scala 1084:31] + wire fw_halt_req = csr_io_fw_halt_req; // @[el2_dec_tlu_ctl.scala 1084:31] wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[el2_dec_tlu_ctl.scala 666:47] reg pmu_fw_halt_req_f; // @[el2_dec_tlu_ctl.scala 658:73] wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[el2_dec_tlu_ctl.scala 671:44] @@ -55037,7 +55047,7 @@ module el2_dec_tlu_ctl( wire [3:0] _T_290 = _T_287 & _T_289; // @[el2_dec_tlu_ctl.scala 593:65] wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[el2_dec_tlu_ctl.scala 593:34] wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[el2_dec_tlu_ctl.scala 598:118] - wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 347:41 el2_dec_tlu_ctl.scala 1085:31] + wire [1:0] mstatus = csr_io_mstatus; // @[el2_dec_tlu_ctl.scala 1085:31] wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:62] wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[el2_dec_tlu_ctl.scala 587:86] wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[el2_dec_tlu_ctl.scala 587:150] @@ -55429,7 +55439,7 @@ module el2_dec_tlu_ctl( wire _T_682 = _T_681 | take_ext_int_start_d2; // @[el2_dec_tlu_ctl.scala 830:66] wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[el2_dec_tlu_ctl.scala 351:41 el2_dec_tlu_ctl.scala 1092:10] wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[el2_dec_tlu_ctl.scala 832:45] - wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 349:41 el2_dec_tlu_ctl.scala 1087:31] + wire [30:0] mtvec = csr_io_mtvec; // @[el2_dec_tlu_ctl.scala 1087:31] wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] wire [30:0] vectored_path = _T_769 + _T_771; // @[el2_dec_tlu_ctl.scala 860:50] @@ -55460,16 +55470,16 @@ module el2_dec_tlu_ctl( wire _T_833 = _T_529 & debug_resume_req_f; // @[el2_dec_tlu_ctl.scala 875:16] wire _T_836 = _T_529 & sel_npc_resume; // @[el2_dec_tlu_ctl.scala 876:16] wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 337:41 el2_dec_tlu_ctl.scala 1075:31] + wire [30:0] npc_r = csr_io_npc_r; // @[el2_dec_tlu_ctl.scala 1075:31] wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] - wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 340:41 el2_dec_tlu_ctl.scala 1078:31] + wire [30:0] mepc = csr_io_mepc; // @[el2_dec_tlu_ctl.scala 1078:31] wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 343:41 el2_dec_tlu_ctl.scala 1081:31] + wire [30:0] dpc = csr_io_dpc; // @[el2_dec_tlu_ctl.scala 1081:31] wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 338:41 el2_dec_tlu_ctl.scala 1076:31] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[el2_dec_tlu_ctl.scala 1076:31] wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] @@ -55588,28 +55598,28 @@ module el2_dec_tlu_ctl( .io_dec_tlu_ic_diag_pkt_icache_wr_valid(csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid), .io_ifu_ic_debug_rd_data_valid(csr_io_ifu_ic_debug_rd_data_valid), .io_trigger_pkt_any_0_select(csr_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(csr_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(csr_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(csr_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(csr_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_execute(csr_io_trigger_pkt_any_0_execute), .io_trigger_pkt_any_0_m(csr_io_trigger_pkt_any_0_m), .io_trigger_pkt_any_0_tdata2(csr_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(csr_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(csr_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(csr_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(csr_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(csr_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_execute(csr_io_trigger_pkt_any_1_execute), .io_trigger_pkt_any_1_m(csr_io_trigger_pkt_any_1_m), .io_trigger_pkt_any_1_tdata2(csr_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(csr_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(csr_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(csr_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(csr_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(csr_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_execute(csr_io_trigger_pkt_any_2_execute), .io_trigger_pkt_any_2_m(csr_io_trigger_pkt_any_2_m), .io_trigger_pkt_any_2_tdata2(csr_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(csr_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(csr_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(csr_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(csr_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(csr_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_execute(csr_io_trigger_pkt_any_3_execute), @@ -55926,28 +55936,28 @@ module el2_dec_tlu_ctl( assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[el2_dec_tlu_ctl.scala 557:27] assign io_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[el2_dec_tlu_ctl.scala 956:44] assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_0_match_ = csr_io_trigger_pkt_any_0_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_1_match_ = csr_io_trigger_pkt_any_1_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_2_match_ = csr_io_trigger_pkt_any_2_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[el2_dec_tlu_ctl.scala 962:40] - assign io_trigger_pkt_any_3_match_ = csr_io_trigger_pkt_any_3_match_; // @[el2_dec_tlu_ctl.scala 962:40] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[el2_dec_tlu_ctl.scala 962:40] assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[el2_dec_tlu_ctl.scala 962:40] @@ -55969,11 +55979,11 @@ module el2_dec_tlu_ctl( assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40] assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22] assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49] - assign io_dec_tlu_br0_r_pkt_bits_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:57] - assign io_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49] - assign io_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:49] - assign io_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:57] - assign io_dec_tlu_br0_r_pkt_bits_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:57] + assign io_dec_tlu_br0_r_pkt_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:49] + assign io_dec_tlu_br0_r_pkt_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49] + assign io_dec_tlu_br0_r_pkt_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:41] + assign io_dec_tlu_br0_r_pkt_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:49] + assign io_dec_tlu_br0_r_pkt_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:49] assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33] assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33] assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28] @@ -56125,7 +56135,7 @@ module el2_dec_tlu_ctl( assign csr_io_inst_acc_r = _T_511 & _T_465; // @[el2_dec_tlu_ctl.scala 1021:39] assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[el2_dec_tlu_ctl.scala 1022:39] assign csr_io_take_nmi = _T_756 & _T_760; // @[el2_dec_tlu_ctl.scala 1023:39] - assign csr_io_lsu_error_pkt_addr_r = {{31'd0}, io_lsu_error_pkt_r_bits_addr}; // @[el2_dec_tlu_ctl.scala 1024:39] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[el2_dec_tlu_ctl.scala 1024:39] assign csr_io_exc_cause_r = _T_603 | _T_591; // @[el2_dec_tlu_ctl.scala 1025:39] assign csr_io_i0_valid_wb = i0_valid_wb; // @[el2_dec_tlu_ctl.scala 1026:39] assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[el2_dec_tlu_ctl.scala 1027:39] @@ -57177,22 +57187,22 @@ end // initial endmodule module el2_dec_trigger( input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_execute, input io_trigger_pkt_any_0_m, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_execute, input io_trigger_pkt_any_1_m, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_execute, input io_trigger_pkt_any_2_m, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_execute, input io_trigger_pkt_any_3_m, input [31:0] io_trigger_pkt_any_3_tdata2, @@ -57234,7 +57244,7 @@ module el2_dec_trigger( wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83] wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] wire _T_152 = ~_T_151; // @[el2_lib.scala 241:39] - wire _T_153 = io_trigger_pkt_any_0_match_ & _T_152; // @[el2_lib.scala 241:37] + wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[el2_lib.scala 241:37] wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 242:52] wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 242:41] wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] @@ -57370,7 +57380,7 @@ module el2_dec_trigger( wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83] wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] wire _T_411 = ~_T_410; // @[el2_lib.scala 241:39] - wire _T_412 = io_trigger_pkt_any_1_match_ & _T_411; // @[el2_lib.scala 241:37] + wire _T_412 = io_trigger_pkt_any_1_match_pkt & _T_411; // @[el2_lib.scala 241:37] wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 242:52] wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 242:41] wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] @@ -57506,7 +57516,7 @@ module el2_dec_trigger( wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83] wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] wire _T_670 = ~_T_669; // @[el2_lib.scala 241:39] - wire _T_671 = io_trigger_pkt_any_2_match_ & _T_670; // @[el2_lib.scala 241:37] + wire _T_671 = io_trigger_pkt_any_2_match_pkt & _T_670; // @[el2_lib.scala 241:37] wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 242:52] wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 242:41] wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] @@ -57642,7 +57652,7 @@ module el2_dec_trigger( wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83] wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] wire _T_929 = ~_T_928; // @[el2_lib.scala 241:39] - wire _T_930 = io_trigger_pkt_any_3_match_ & _T_929; // @[el2_lib.scala 241:37] + wire _T_930 = io_trigger_pkt_any_3_match_pkt & _T_929; // @[el2_lib.scala 241:37] wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 242:52] wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 242:41] wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] @@ -57847,13 +57857,13 @@ module el2_dec( input io_ifu_i0_dbecc, input io_lsu_idle_any, input io_i0_brp_valid, - input [11:0] io_i0_brp_bits_toffset, - input [1:0] io_i0_brp_bits_hist, - input io_i0_brp_bits_br_error, - input io_i0_brp_bits_br_start_error, - input [30:0] io_i0_brp_bits_prett, - input io_i0_brp_bits_way, - input io_i0_brp_bits_ret, + input [11:0] io_i0_brp_toffset, + input [1:0] io_i0_brp_hist, + input io_i0_brp_br_error, + input io_i0_brp_br_start_error, + input [30:0] io_i0_brp_prett, + input io_i0_brp_way, + input io_i0_brp_ret, input [7:0] io_ifu_i0_bp_index, input [7:0] io_ifu_i0_bp_fghr, input [4:0] io_ifu_i0_bp_btag, @@ -57861,8 +57871,8 @@ module el2_dec( input io_lsu_error_pkt_r_bits_single_ecc_error, input io_lsu_error_pkt_r_bits_inst_type, input io_lsu_error_pkt_r_bits_exc_type, - input io_lsu_error_pkt_r_bits_mscause, - input io_lsu_error_pkt_r_bits_addr, + input [3:0] io_lsu_error_pkt_r_bits_mscause, + input [31:0] io_lsu_error_pkt_r_bits_addr, input io_lsu_single_ecc_error_incr, input io_lsu_imprecise_error_load_any, input io_lsu_imprecise_error_store_any, @@ -57915,22 +57925,22 @@ module el2_dec( output io_dec_dbg_cmd_done, output io_dec_dbg_cmd_fail, output io_trigger_pkt_any_0_select, - output io_trigger_pkt_any_0_match_, + output io_trigger_pkt_any_0_match_pkt, output io_trigger_pkt_any_0_store, output io_trigger_pkt_any_0_load, output [31:0] io_trigger_pkt_any_0_tdata2, output io_trigger_pkt_any_1_select, - output io_trigger_pkt_any_1_match_, + output io_trigger_pkt_any_1_match_pkt, output io_trigger_pkt_any_1_store, output io_trigger_pkt_any_1_load, output [31:0] io_trigger_pkt_any_1_tdata2, output io_trigger_pkt_any_2_select, - output io_trigger_pkt_any_2_match_, + output io_trigger_pkt_any_2_match_pkt, output io_trigger_pkt_any_2_store, output io_trigger_pkt_any_2_load, output [31:0] io_trigger_pkt_any_2_tdata2, output io_trigger_pkt_any_3_select, - output io_trigger_pkt_any_3_match_, + output io_trigger_pkt_any_3_match_pkt, output io_trigger_pkt_any_3_store, output io_trigger_pkt_any_3_load, output [31:0] io_trigger_pkt_any_3_tdata2, @@ -58000,11 +58010,11 @@ module el2_dec( output io_dec_tlu_fence_i_r, output [30:0] io_pred_correct_npc_x, output io_dec_tlu_br0_r_pkt_valid, - output [1:0] io_dec_tlu_br0_r_pkt_bits_hist, - output io_dec_tlu_br0_r_pkt_bits_br_error, - output io_dec_tlu_br0_r_pkt_bits_br_start_error, - output io_dec_tlu_br0_r_pkt_bits_way, - output io_dec_tlu_br0_r_pkt_bits_middle, + output [1:0] io_dec_tlu_br0_r_pkt_hist, + output io_dec_tlu_br0_r_pkt_br_error, + output io_dec_tlu_br0_r_pkt_br_start_error, + output io_dec_tlu_br0_r_pkt_way, + output io_dec_tlu_br0_r_pkt_middle, output io_dec_tlu_perfcnt0, output io_dec_tlu_perfcnt1, output io_dec_tlu_perfcnt2, @@ -58054,13 +58064,13 @@ module el2_dec( wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 285:24] wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 285:24] wire instbuff_io_i0_brp_valid; // @[el2_dec.scala 285:24] - wire [11:0] instbuff_io_i0_brp_bits_toffset; // @[el2_dec.scala 285:24] - wire [1:0] instbuff_io_i0_brp_bits_hist; // @[el2_dec.scala 285:24] - wire instbuff_io_i0_brp_bits_br_error; // @[el2_dec.scala 285:24] - wire instbuff_io_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24] - wire [30:0] instbuff_io_i0_brp_bits_prett; // @[el2_dec.scala 285:24] - wire instbuff_io_i0_brp_bits_way; // @[el2_dec.scala 285:24] - wire instbuff_io_i0_brp_bits_ret; // @[el2_dec.scala 285:24] + wire [11:0] instbuff_io_i0_brp_toffset; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_i0_brp_hist; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_br_error; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_br_start_error; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_i0_brp_prett; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_way; // @[el2_dec.scala 285:24] + wire instbuff_io_i0_brp_ret; // @[el2_dec.scala 285:24] wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 285:24] wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 285:24] wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 285:24] @@ -58078,13 +58088,13 @@ module el2_dec( wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 285:24] wire instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 285:24] wire instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 285:24] - wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 285:24] - wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 285:24] - wire instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 285:24] - wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24] - wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 285:24] - wire instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 285:24] - wire instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 285:24] + wire [11:0] instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 285:24] + wire [1:0] instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 285:24] + wire [30:0] instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 285:24] + wire instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 285:24] wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 285:24] wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 285:24] wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 285:24] @@ -58123,13 +58133,13 @@ module el2_dec( wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 286:22] wire decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 286:22] wire decode_io_dec_i0_brp_valid; // @[el2_dec.scala 286:22] - wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 286:22] - wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 286:22] - wire decode_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 286:22] - wire decode_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 286:22] - wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 286:22] - wire decode_io_dec_i0_brp_bits_way; // @[el2_dec.scala 286:22] - wire decode_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 286:22] + wire [11:0] decode_io_dec_i0_brp_toffset; // @[el2_dec.scala 286:22] + wire [1:0] decode_io_dec_i0_brp_hist; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_br_error; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 286:22] + wire [30:0] decode_io_dec_i0_brp_prett; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_way; // @[el2_dec.scala 286:22] + wire decode_io_dec_i0_brp_ret; // @[el2_dec.scala 286:22] wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 286:22] wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 286:22] wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 286:22] @@ -58324,8 +58334,8 @@ module el2_dec( wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_dec.scala 288:19] wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_dec.scala 288:19] wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_dec.scala 288:19] - wire tlu_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 288:19] - wire tlu_io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 288:19] + wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[el2_dec.scala 288:19] + wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[el2_dec.scala 288:19] wire tlu_io_lsu_single_ecc_error_incr; // @[el2_dec.scala 288:19] wire tlu_io_dec_pause_state; // @[el2_dec.scala 288:19] wire tlu_io_lsu_imprecise_error_store_any; // @[el2_dec.scala 288:19] @@ -58378,28 +58388,28 @@ module el2_dec( wire tlu_io_lsu_idle_any; // @[el2_dec.scala 288:19] wire tlu_io_dec_div_active; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 288:19] - wire tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 288:19] wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 288:19] - wire tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 288:19] wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 288:19] - wire tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 288:19] wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 288:19] - wire tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 288:19] + wire tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 288:19] wire tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 288:19] @@ -58435,11 +58445,11 @@ module el2_dec( wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 288:19] wire tlu_io_dec_csr_legal_d; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 288:19] - wire [1:0] tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 288:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 288:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 288:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 288:19] - wire tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 288:19] + wire [1:0] tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 288:19] + wire tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 288:19] @@ -58476,22 +58486,22 @@ module el2_dec( wire tlu_io_dec_tlu_dccm_clk_override; // @[el2_dec.scala 288:19] wire tlu_io_dec_tlu_icm_clk_override; // @[el2_dec.scala 288:19] wire dec_trigger_io_trigger_pkt_any_0_select; // @[el2_dec.scala 289:27] - wire dec_trigger_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_0_m; // @[el2_dec.scala 289:27] wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_1_select; // @[el2_dec.scala 289:27] - wire dec_trigger_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_1_m; // @[el2_dec.scala 289:27] wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_2_select; // @[el2_dec.scala 289:27] - wire dec_trigger_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_2_m; // @[el2_dec.scala 289:27] wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_3_select; // @[el2_dec.scala 289:27] - wire dec_trigger_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 289:27] + wire dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 289:27] wire dec_trigger_io_trigger_pkt_any_3_m; // @[el2_dec.scala 289:27] wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 289:27] @@ -58504,13 +58514,13 @@ module el2_dec( .io_dbg_cmd_type(instbuff_io_dbg_cmd_type), .io_dbg_cmd_addr(instbuff_io_dbg_cmd_addr), .io_i0_brp_valid(instbuff_io_i0_brp_valid), - .io_i0_brp_bits_toffset(instbuff_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(instbuff_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(instbuff_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(instbuff_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_prett(instbuff_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(instbuff_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(instbuff_io_i0_brp_bits_ret), + .io_i0_brp_toffset(instbuff_io_i0_brp_toffset), + .io_i0_brp_hist(instbuff_io_i0_brp_hist), + .io_i0_brp_br_error(instbuff_io_i0_brp_br_error), + .io_i0_brp_br_start_error(instbuff_io_i0_brp_br_start_error), + .io_i0_brp_prett(instbuff_io_i0_brp_prett), + .io_i0_brp_way(instbuff_io_i0_brp_way), + .io_i0_brp_ret(instbuff_io_i0_brp_ret), .io_ifu_i0_bp_index(instbuff_io_ifu_i0_bp_index), .io_ifu_i0_bp_fghr(instbuff_io_ifu_i0_bp_fghr), .io_ifu_i0_bp_btag(instbuff_io_ifu_i0_bp_btag), @@ -58528,13 +58538,13 @@ module el2_dec( .io_dec_i0_pc_d(instbuff_io_dec_i0_pc_d), .io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d), .io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid), - .io_dec_i0_brp_bits_toffset(instbuff_io_dec_i0_brp_bits_toffset), - .io_dec_i0_brp_bits_hist(instbuff_io_dec_i0_brp_bits_hist), - .io_dec_i0_brp_bits_br_error(instbuff_io_dec_i0_brp_bits_br_error), - .io_dec_i0_brp_bits_br_start_error(instbuff_io_dec_i0_brp_bits_br_start_error), - .io_dec_i0_brp_bits_prett(instbuff_io_dec_i0_brp_bits_prett), - .io_dec_i0_brp_bits_way(instbuff_io_dec_i0_brp_bits_way), - .io_dec_i0_brp_bits_ret(instbuff_io_dec_i0_brp_bits_ret), + .io_dec_i0_brp_toffset(instbuff_io_dec_i0_brp_toffset), + .io_dec_i0_brp_hist(instbuff_io_dec_i0_brp_hist), + .io_dec_i0_brp_br_error(instbuff_io_dec_i0_brp_br_error), + .io_dec_i0_brp_br_start_error(instbuff_io_dec_i0_brp_br_start_error), + .io_dec_i0_brp_prett(instbuff_io_dec_i0_brp_prett), + .io_dec_i0_brp_way(instbuff_io_dec_i0_brp_way), + .io_dec_i0_brp_ret(instbuff_io_dec_i0_brp_ret), .io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index), .io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr), .io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag), @@ -58575,13 +58585,13 @@ module el2_dec( .io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d), .io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d), .io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid), - .io_dec_i0_brp_bits_toffset(decode_io_dec_i0_brp_bits_toffset), - .io_dec_i0_brp_bits_hist(decode_io_dec_i0_brp_bits_hist), - .io_dec_i0_brp_bits_br_error(decode_io_dec_i0_brp_bits_br_error), - .io_dec_i0_brp_bits_br_start_error(decode_io_dec_i0_brp_bits_br_start_error), - .io_dec_i0_brp_bits_prett(decode_io_dec_i0_brp_bits_prett), - .io_dec_i0_brp_bits_way(decode_io_dec_i0_brp_bits_way), - .io_dec_i0_brp_bits_ret(decode_io_dec_i0_brp_bits_ret), + .io_dec_i0_brp_toffset(decode_io_dec_i0_brp_toffset), + .io_dec_i0_brp_hist(decode_io_dec_i0_brp_hist), + .io_dec_i0_brp_br_error(decode_io_dec_i0_brp_br_error), + .io_dec_i0_brp_br_start_error(decode_io_dec_i0_brp_br_start_error), + .io_dec_i0_brp_prett(decode_io_dec_i0_brp_prett), + .io_dec_i0_brp_way(decode_io_dec_i0_brp_way), + .io_dec_i0_brp_ret(decode_io_dec_i0_brp_ret), .io_dec_i0_bp_index(decode_io_dec_i0_bp_index), .io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr), .io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag), @@ -58834,28 +58844,28 @@ module el2_dec( .io_lsu_idle_any(tlu_io_lsu_idle_any), .io_dec_div_active(tlu_io_dec_div_active), .io_trigger_pkt_any_0_select(tlu_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(tlu_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(tlu_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(tlu_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(tlu_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_execute(tlu_io_trigger_pkt_any_0_execute), .io_trigger_pkt_any_0_m(tlu_io_trigger_pkt_any_0_m), .io_trigger_pkt_any_0_tdata2(tlu_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(tlu_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(tlu_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(tlu_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(tlu_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(tlu_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_execute(tlu_io_trigger_pkt_any_1_execute), .io_trigger_pkt_any_1_m(tlu_io_trigger_pkt_any_1_m), .io_trigger_pkt_any_1_tdata2(tlu_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(tlu_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(tlu_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(tlu_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(tlu_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(tlu_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_execute(tlu_io_trigger_pkt_any_2_execute), .io_trigger_pkt_any_2_m(tlu_io_trigger_pkt_any_2_m), .io_trigger_pkt_any_2_tdata2(tlu_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(tlu_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(tlu_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(tlu_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(tlu_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(tlu_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_execute(tlu_io_trigger_pkt_any_3_execute), @@ -58891,11 +58901,11 @@ module el2_dec( .io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d), .io_dec_csr_legal_d(tlu_io_dec_csr_legal_d), .io_dec_tlu_br0_r_pkt_valid(tlu_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(tlu_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(tlu_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(tlu_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(tlu_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(tlu_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(tlu_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(tlu_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(tlu_io_dec_tlu_br0_r_pkt_middle), .io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb), .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb), .io_dec_tlu_i0_commit_cmt(tlu_io_dec_tlu_i0_commit_cmt), @@ -58934,22 +58944,22 @@ module el2_dec( ); el2_dec_trigger dec_trigger ( // @[el2_dec.scala 289:27] .io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(dec_trigger_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(dec_trigger_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute), .io_trigger_pkt_any_0_m(dec_trigger_io_trigger_pkt_any_0_m), .io_trigger_pkt_any_0_tdata2(dec_trigger_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(dec_trigger_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(dec_trigger_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(dec_trigger_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_execute(dec_trigger_io_trigger_pkt_any_1_execute), .io_trigger_pkt_any_1_m(dec_trigger_io_trigger_pkt_any_1_m), .io_trigger_pkt_any_1_tdata2(dec_trigger_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(dec_trigger_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(dec_trigger_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(dec_trigger_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_execute(dec_trigger_io_trigger_pkt_any_2_execute), .io_trigger_pkt_any_2_m(dec_trigger_io_trigger_pkt_any_2_m), .io_trigger_pkt_any_2_tdata2(dec_trigger_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(dec_trigger_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(dec_trigger_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(dec_trigger_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_execute(dec_trigger_io_trigger_pkt_any_3_execute), .io_trigger_pkt_any_3_m(dec_trigger_io_trigger_pkt_any_3_m), .io_trigger_pkt_any_3_tdata2(dec_trigger_io_trigger_pkt_any_3_tdata2), @@ -58985,22 +58995,22 @@ module el2_dec( assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[el2_dec.scala 536:28] assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[el2_dec.scala 537:28] assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 546:29] - assign io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 546:29] - assign io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 546:29] - assign io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 546:29] - assign io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 546:29] + assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[el2_dec.scala 546:29] assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 546:29] @@ -59063,11 +59073,11 @@ module el2_dec( assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 562:34] assign io_pred_correct_npc_x = decode_io_pred_correct_npc_x; // @[el2_dec.scala 411:40] assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_hist = tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_way = tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 557:42] - assign io_dec_tlu_br0_r_pkt_bits_middle = tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_hist = tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_br_error = tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_br_start_error = tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_way = tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 557:42] + assign io_dec_tlu_br0_r_pkt_middle = tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 557:42] assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 565:29] assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 566:29] assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 567:29] @@ -59114,13 +59124,13 @@ module el2_dec( assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 299:45] assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 300:45] assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec.scala 301:55] - assign instbuff_io_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_hist = io_i0_brp_hist; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_prett = io_i0_brp_prett; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_way = io_i0_brp_way; // @[el2_dec.scala 301:55] + assign instbuff_io_i0_brp_ret = io_i0_brp_ret; // @[el2_dec.scala 301:55] assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec.scala 302:35] assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 303:35] assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 304:35] @@ -59159,13 +59169,13 @@ module el2_dec( assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 352:48] assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:48] assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 354:48] - assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_toffset = instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_hist = instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_br_error = instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_br_start_error = instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_prett = instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_way = instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 354:48] + assign decode_io_dec_i0_brp_ret = instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 354:48] assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 355:48] assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 356:48] assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 357:48] @@ -59311,22 +59321,22 @@ module el2_dec( assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[el2_dec.scala 533:45] assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[el2_dec.scala 534:45] assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[el2_dec.scala 321:34] - assign dec_trigger_io_trigger_pkt_any_0_match_ = tlu_io_trigger_pkt_any_0_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[el2_dec.scala 321:34] - assign dec_trigger_io_trigger_pkt_any_1_match_ = tlu_io_trigger_pkt_any_1_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[el2_dec.scala 321:34] - assign dec_trigger_io_trigger_pkt_any_2_match_ = tlu_io_trigger_pkt_any_2_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[el2_dec.scala 321:34] - assign dec_trigger_io_trigger_pkt_any_3_match_ = tlu_io_trigger_pkt_any_3_match_; // @[el2_dec.scala 321:34] + assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[el2_dec.scala 321:34] assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[el2_dec.scala 321:34] @@ -63056,8 +63066,8 @@ module el2_lsu_lsc_ctl( output io_lsu_error_pkt_r_bits_single_ecc_error, output io_lsu_error_pkt_r_bits_inst_type, output io_lsu_error_pkt_r_bits_exc_type, - output io_lsu_error_pkt_r_bits_mscause, - output io_lsu_error_pkt_r_bits_addr, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, output [30:0] io_lsu_fir_addr, output [1:0] io_lsu_fir_error, output io_addr_in_dccm_d, @@ -63235,14 +63245,13 @@ module el2_lsu_lsc_ctl( wire _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 183:78] wire _T_91 = ~access_fault_m; // @[el2_lsu_lsc_ctl.scala 183:102] wire _T_92 = _T_90 & _T_91; // @[el2_lsu_lsc_ctl.scala 183:100] - wire [3:0] _T_95 = _T_92 ? 4'h1 : exc_mscause_m; // @[el2_lsu_lsc_ctl.scala 183:49] wire _T_99 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 185:166] reg _T_105_valid; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_inst_type; // @[el2_lsu_lsc_ctl.scala 186:75] reg _T_105_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 186:75] - reg _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75] - reg _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75] + reg [3:0] _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75] + reg [31:0] _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75] reg [1:0] _T_106; // @[el2_lsu_lsc_ctl.scala 187:75] wire dma_pkt_d_bits_load = ~io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 194:30] wire dma_pkt_d_bits_by = io_dma_mem_sz == 3'h0; // @[el2_lsu_lsc_ctl.scala 195:50] @@ -63505,9 +63514,9 @@ initial begin _RAND_8 = {1{`RANDOM}}; _T_105_bits_exc_type = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - _T_105_bits_mscause = _RAND_9[0:0]; + _T_105_bits_mscause = _RAND_9[3:0]; _RAND_10 = {1{`RANDOM}}; - _T_105_bits_addr = _RAND_10[0:0]; + _T_105_bits_addr = _RAND_10[31:0]; _RAND_11 = {1{`RANDOM}}; _T_106 = _RAND_11[1:0]; _RAND_12 = {1{`RANDOM}}; @@ -63603,10 +63612,10 @@ initial begin _T_105_bits_exc_type = 1'h0; end if (reset) begin - _T_105_bits_mscause = 1'h0; + _T_105_bits_mscause = 4'h0; end if (reset) begin - _T_105_bits_addr = 1'h0; + _T_105_bits_addr = 32'h0; end if (reset) begin _T_106 = 2'h0; @@ -63778,16 +63787,18 @@ end // initial end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_105_bits_mscause <= 1'h0; + _T_105_bits_mscause <= 4'h0; + end else if (_T_92) begin + _T_105_bits_mscause <= 4'h1; end else begin - _T_105_bits_mscause <= _T_95[0]; + _T_105_bits_mscause <= exc_mscause_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_105_bits_addr <= 1'h0; + _T_105_bits_addr <= 32'h0; end else begin - _T_105_bits_addr <= io_lsu_addr_m[0]; + _T_105_bits_addr <= io_lsu_addr_m; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin @@ -66979,22 +66990,22 @@ end // initial endmodule module el2_lsu_trigger( input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_store, input io_trigger_pkt_any_0_load, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_store, input io_trigger_pkt_any_1_load, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_store, input io_trigger_pkt_any_2_load, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_store, input io_trigger_pkt_any_3_load, input [31:0] io_trigger_pkt_any_3_tdata2, @@ -67043,7 +67054,7 @@ module el2_lsu_trigger( wire _T_46 = _T_40 & _T_45; // @[el2_lsu_trigger.scala 18:94] wire _T_49 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] wire _T_50 = ~_T_49; // @[el2_lib.scala 241:39] - wire _T_51 = io_trigger_pkt_any_0_match_ & _T_50; // @[el2_lib.scala 241:37] + wire _T_51 = io_trigger_pkt_any_0_match_pkt & _T_50; // @[el2_lib.scala 241:37] wire _T_54 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[el2_lib.scala 242:52] wire _T_55 = _T_51 | _T_54; // @[el2_lib.scala 242:41] wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] @@ -67183,7 +67194,7 @@ module el2_lsu_trigger( wire _T_312 = _T_40 & _T_311; // @[el2_lsu_trigger.scala 18:94] wire _T_315 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] wire _T_316 = ~_T_315; // @[el2_lib.scala 241:39] - wire _T_317 = io_trigger_pkt_any_1_match_ & _T_316; // @[el2_lib.scala 241:37] + wire _T_317 = io_trigger_pkt_any_1_match_pkt & _T_316; // @[el2_lib.scala 241:37] wire _T_320 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[el2_lib.scala 242:52] wire _T_321 = _T_317 | _T_320; // @[el2_lib.scala 242:41] wire _T_323 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] @@ -67323,7 +67334,7 @@ module el2_lsu_trigger( wire _T_578 = _T_40 & _T_577; // @[el2_lsu_trigger.scala 18:94] wire _T_581 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] wire _T_582 = ~_T_581; // @[el2_lib.scala 241:39] - wire _T_583 = io_trigger_pkt_any_2_match_ & _T_582; // @[el2_lib.scala 241:37] + wire _T_583 = io_trigger_pkt_any_2_match_pkt & _T_582; // @[el2_lib.scala 241:37] wire _T_586 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[el2_lib.scala 242:52] wire _T_587 = _T_583 | _T_586; // @[el2_lib.scala 242:41] wire _T_589 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] @@ -67463,7 +67474,7 @@ module el2_lsu_trigger( wire _T_844 = _T_40 & _T_843; // @[el2_lsu_trigger.scala 18:94] wire _T_847 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] wire _T_848 = ~_T_847; // @[el2_lib.scala 241:39] - wire _T_849 = io_trigger_pkt_any_3_match_ & _T_848; // @[el2_lib.scala 241:37] + wire _T_849 = io_trigger_pkt_any_3_match_pkt & _T_848; // @[el2_lib.scala 241:37] wire _T_852 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[el2_lib.scala 242:52] wire _T_853 = _T_849 | _T_852; // @[el2_lib.scala 242:41] wire _T_855 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] @@ -73153,22 +73164,22 @@ module el2_lsu( input io_lsu_p_bits_store_data_bypass_d, input io_lsu_p_bits_load_ldst_bypass_d, input io_trigger_pkt_any_0_select, - input io_trigger_pkt_any_0_match_, + input io_trigger_pkt_any_0_match_pkt, input io_trigger_pkt_any_0_store, input io_trigger_pkt_any_0_load, input [31:0] io_trigger_pkt_any_0_tdata2, input io_trigger_pkt_any_1_select, - input io_trigger_pkt_any_1_match_, + input io_trigger_pkt_any_1_match_pkt, input io_trigger_pkt_any_1_store, input io_trigger_pkt_any_1_load, input [31:0] io_trigger_pkt_any_1_tdata2, input io_trigger_pkt_any_2_select, - input io_trigger_pkt_any_2_match_, + input io_trigger_pkt_any_2_match_pkt, input io_trigger_pkt_any_2_store, input io_trigger_pkt_any_2_load, input [31:0] io_trigger_pkt_any_2_tdata2, input io_trigger_pkt_any_3_select, - input io_trigger_pkt_any_3_match_, + input io_trigger_pkt_any_3_match_pkt, input io_trigger_pkt_any_3_store, input io_trigger_pkt_any_3_load, input [31:0] io_trigger_pkt_any_3_tdata2, @@ -73187,8 +73198,8 @@ module el2_lsu( output io_lsu_error_pkt_r_bits_single_ecc_error, output io_lsu_error_pkt_r_bits_inst_type, output io_lsu_error_pkt_r_bits_exc_type, - output io_lsu_error_pkt_r_bits_mscause, - output io_lsu_error_pkt_r_bits_addr, + output [3:0] io_lsu_error_pkt_r_bits_mscause, + output [31:0] io_lsu_error_pkt_r_bits_addr, output io_lsu_imprecise_error_load_any, output io_lsu_imprecise_error_store_any, output [31:0] io_lsu_imprecise_error_addr_any, @@ -73316,8 +73327,8 @@ module el2_lsu( wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_lsu.scala 154:30] wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[el2_lsu.scala 154:30] wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[el2_lsu.scala 154:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[el2_lsu.scala 154:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[el2_lsu.scala 154:30] + wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[el2_lsu.scala 154:30] wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[el2_lsu.scala 154:30] wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[el2_lsu.scala 154:30] wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 154:30] @@ -73557,22 +73568,22 @@ module el2_lsu( wire ecc_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 159:30] wire ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 159:30] wire trigger_io_trigger_pkt_any_0_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_0_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_0_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_0_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_0_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_1_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_1_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_1_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_1_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_1_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_2_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_2_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_2_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_2_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_2_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_3_select; // @[el2_lsu.scala 160:30] - wire trigger_io_trigger_pkt_any_3_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_3_match_pkt; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_3_store; // @[el2_lsu.scala 160:30] wire trigger_io_trigger_pkt_any_3_load; // @[el2_lsu.scala 160:30] wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 160:30] @@ -74032,22 +74043,22 @@ module el2_lsu( ); el2_lsu_trigger trigger ( // @[el2_lsu.scala 160:30] .io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(trigger_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(trigger_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(trigger_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_tdata2(trigger_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(trigger_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(trigger_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(trigger_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(trigger_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(trigger_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_tdata2(trigger_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(trigger_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(trigger_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(trigger_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(trigger_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(trigger_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_tdata2(trigger_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(trigger_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(trigger_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(trigger_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(trigger_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(trigger_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_tdata2(trigger_io_trigger_pkt_any_3_tdata2), @@ -74415,22 +74426,22 @@ module el2_lsu( assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[el2_lsu.scala 371:50] assign ecc_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 372:50] assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_0_match_ = io_trigger_pkt_any_0_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_1_match_ = io_trigger_pkt_any_1_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_2_match_ = io_trigger_pkt_any_2_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[el2_lsu.scala 376:50] - assign trigger_io_trigger_pkt_any_3_match_ = io_trigger_pkt_any_3_match_; // @[el2_lsu.scala 376:50] + assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 376:50] @@ -80398,13 +80409,13 @@ module el2_swerv( wire ifu_io_ifu_i0_pc4; // @[el2_swerv.scala 321:19] wire ifu_io_ifu_miss_state_idle; // @[el2_swerv.scala 321:19] wire ifu_io_i0_brp_valid; // @[el2_swerv.scala 321:19] - wire [11:0] ifu_io_i0_brp_bits_toffset; // @[el2_swerv.scala 321:19] - wire [1:0] ifu_io_i0_brp_bits_hist; // @[el2_swerv.scala 321:19] - wire ifu_io_i0_brp_bits_br_error; // @[el2_swerv.scala 321:19] - wire ifu_io_i0_brp_bits_br_start_error; // @[el2_swerv.scala 321:19] - wire [30:0] ifu_io_i0_brp_bits_prett; // @[el2_swerv.scala 321:19] - wire ifu_io_i0_brp_bits_way; // @[el2_swerv.scala 321:19] - wire ifu_io_i0_brp_bits_ret; // @[el2_swerv.scala 321:19] + wire [11:0] ifu_io_i0_brp_toffset; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_i0_brp_hist; // @[el2_swerv.scala 321:19] + wire ifu_io_i0_brp_br_error; // @[el2_swerv.scala 321:19] + wire ifu_io_i0_brp_br_start_error; // @[el2_swerv.scala 321:19] + wire [30:0] ifu_io_i0_brp_prett; // @[el2_swerv.scala 321:19] + wire ifu_io_i0_brp_way; // @[el2_swerv.scala 321:19] + wire ifu_io_i0_brp_ret; // @[el2_swerv.scala 321:19] wire [7:0] ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 321:19] wire [7:0] ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 321:19] wire [4:0] ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 321:19] @@ -80423,11 +80434,11 @@ module el2_swerv( wire [7:0] ifu_io_exu_mp_index; // @[el2_swerv.scala 321:19] wire [4:0] ifu_io_exu_mp_btag; // @[el2_swerv.scala 321:19] wire ifu_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 321:19] - wire [1:0] ifu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 321:19] - wire ifu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 321:19] - wire ifu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_swerv.scala 321:19] - wire ifu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_swerv.scala 321:19] - wire ifu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_swerv.scala 321:19] + wire [1:0] ifu_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 321:19] + wire ifu_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 321:19] wire [7:0] ifu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 321:19] wire [7:0] ifu_io_exu_i0_br_index_r; // @[el2_swerv.scala 321:19] wire ifu_io_dec_tlu_flush_lower_wb; // @[el2_swerv.scala 321:19] @@ -80508,13 +80519,13 @@ module el2_swerv( wire dec_io_ifu_i0_dbecc; // @[el2_swerv.scala 322:19] wire dec_io_lsu_idle_any; // @[el2_swerv.scala 322:19] wire dec_io_i0_brp_valid; // @[el2_swerv.scala 322:19] - wire [11:0] dec_io_i0_brp_bits_toffset; // @[el2_swerv.scala 322:19] - wire [1:0] dec_io_i0_brp_bits_hist; // @[el2_swerv.scala 322:19] - wire dec_io_i0_brp_bits_br_error; // @[el2_swerv.scala 322:19] - wire dec_io_i0_brp_bits_br_start_error; // @[el2_swerv.scala 322:19] - wire [30:0] dec_io_i0_brp_bits_prett; // @[el2_swerv.scala 322:19] - wire dec_io_i0_brp_bits_way; // @[el2_swerv.scala 322:19] - wire dec_io_i0_brp_bits_ret; // @[el2_swerv.scala 322:19] + wire [11:0] dec_io_i0_brp_toffset; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_i0_brp_hist; // @[el2_swerv.scala 322:19] + wire dec_io_i0_brp_br_error; // @[el2_swerv.scala 322:19] + wire dec_io_i0_brp_br_start_error; // @[el2_swerv.scala 322:19] + wire [30:0] dec_io_i0_brp_prett; // @[el2_swerv.scala 322:19] + wire dec_io_i0_brp_way; // @[el2_swerv.scala 322:19] + wire dec_io_i0_brp_ret; // @[el2_swerv.scala 322:19] wire [7:0] dec_io_ifu_i0_bp_index; // @[el2_swerv.scala 322:19] wire [7:0] dec_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 322:19] wire [4:0] dec_io_ifu_i0_bp_btag; // @[el2_swerv.scala 322:19] @@ -80522,8 +80533,8 @@ module el2_swerv( wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 322:19] wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 322:19] wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 322:19] - wire dec_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 322:19] - wire dec_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 322:19] + wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 322:19] + wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 322:19] wire dec_io_lsu_single_ecc_error_incr; // @[el2_swerv.scala 322:19] wire dec_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 322:19] wire dec_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 322:19] @@ -80576,22 +80587,22 @@ module el2_swerv( wire dec_io_dec_dbg_cmd_done; // @[el2_swerv.scala 322:19] wire dec_io_dec_dbg_cmd_fail; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 322:19] - wire dec_io_trigger_pkt_any_0_match_; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_0_match_pkt; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 322:19] - wire dec_io_trigger_pkt_any_1_match_; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_1_match_pkt; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 322:19] - wire dec_io_trigger_pkt_any_2_match_; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_2_match_pkt; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 322:19] - wire dec_io_trigger_pkt_any_3_match_; // @[el2_swerv.scala 322:19] + wire dec_io_trigger_pkt_any_3_match_pkt; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 322:19] wire dec_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 322:19] wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 322:19] @@ -80661,11 +80672,11 @@ module el2_swerv( wire dec_io_dec_tlu_fence_i_r; // @[el2_swerv.scala 322:19] wire [30:0] dec_io_pred_correct_npc_x; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 322:19] - wire [1:0] dec_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 322:19] - wire dec_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 322:19] - wire dec_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_swerv.scala 322:19] - wire dec_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_swerv.scala 322:19] - wire dec_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_swerv.scala 322:19] + wire [1:0] dec_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 322:19] + wire dec_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_perfcnt0; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_perfcnt1; // @[el2_swerv.scala 322:19] wire dec_io_dec_tlu_perfcnt2; // @[el2_swerv.scala 322:19] @@ -80885,22 +80896,22 @@ module el2_swerv( wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 325:19] wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 325:19] - wire lsu_io_trigger_pkt_any_0_match_; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_0_match_pkt; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 325:19] wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 325:19] - wire lsu_io_trigger_pkt_any_1_match_; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_1_match_pkt; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 325:19] wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 325:19] - wire lsu_io_trigger_pkt_any_2_match_; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_2_match_pkt; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 325:19] wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 325:19] - wire lsu_io_trigger_pkt_any_3_match_; // @[el2_swerv.scala 325:19] + wire lsu_io_trigger_pkt_any_3_match_pkt; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 325:19] wire lsu_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 325:19] wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 325:19] @@ -80919,8 +80930,8 @@ module el2_swerv( wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[el2_swerv.scala 325:19] wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[el2_swerv.scala 325:19] wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[el2_swerv.scala 325:19] - wire lsu_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 325:19] - wire lsu_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 325:19] + wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[el2_swerv.scala 325:19] + wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[el2_swerv.scala 325:19] wire lsu_io_lsu_imprecise_error_load_any; // @[el2_swerv.scala 325:19] wire lsu_io_lsu_imprecise_error_store_any; // @[el2_swerv.scala 325:19] wire [31:0] lsu_io_lsu_imprecise_error_addr_any; // @[el2_swerv.scala 325:19] @@ -81177,13 +81188,13 @@ module el2_swerv( .io_ifu_i0_pc4(ifu_io_ifu_i0_pc4), .io_ifu_miss_state_idle(ifu_io_ifu_miss_state_idle), .io_i0_brp_valid(ifu_io_i0_brp_valid), - .io_i0_brp_bits_toffset(ifu_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(ifu_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(ifu_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(ifu_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_prett(ifu_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(ifu_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(ifu_io_i0_brp_bits_ret), + .io_i0_brp_toffset(ifu_io_i0_brp_toffset), + .io_i0_brp_hist(ifu_io_i0_brp_hist), + .io_i0_brp_br_error(ifu_io_i0_brp_br_error), + .io_i0_brp_br_start_error(ifu_io_i0_brp_br_start_error), + .io_i0_brp_prett(ifu_io_i0_brp_prett), + .io_i0_brp_way(ifu_io_i0_brp_way), + .io_i0_brp_ret(ifu_io_i0_brp_ret), .io_ifu_i0_bp_index(ifu_io_ifu_i0_bp_index), .io_ifu_i0_bp_fghr(ifu_io_ifu_i0_bp_fghr), .io_ifu_i0_bp_btag(ifu_io_ifu_i0_bp_btag), @@ -81202,11 +81213,11 @@ module el2_swerv( .io_exu_mp_index(ifu_io_exu_mp_index), .io_exu_mp_btag(ifu_io_exu_mp_btag), .io_dec_tlu_br0_r_pkt_valid(ifu_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(ifu_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(ifu_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(ifu_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(ifu_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(ifu_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(ifu_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(ifu_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(ifu_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(ifu_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(ifu_io_dec_tlu_br0_r_pkt_middle), .io_exu_i0_br_fghr_r(ifu_io_exu_i0_br_fghr_r), .io_exu_i0_br_index_r(ifu_io_exu_i0_br_index_r), .io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb), @@ -81289,13 +81300,13 @@ module el2_swerv( .io_ifu_i0_dbecc(dec_io_ifu_i0_dbecc), .io_lsu_idle_any(dec_io_lsu_idle_any), .io_i0_brp_valid(dec_io_i0_brp_valid), - .io_i0_brp_bits_toffset(dec_io_i0_brp_bits_toffset), - .io_i0_brp_bits_hist(dec_io_i0_brp_bits_hist), - .io_i0_brp_bits_br_error(dec_io_i0_brp_bits_br_error), - .io_i0_brp_bits_br_start_error(dec_io_i0_brp_bits_br_start_error), - .io_i0_brp_bits_prett(dec_io_i0_brp_bits_prett), - .io_i0_brp_bits_way(dec_io_i0_brp_bits_way), - .io_i0_brp_bits_ret(dec_io_i0_brp_bits_ret), + .io_i0_brp_toffset(dec_io_i0_brp_toffset), + .io_i0_brp_hist(dec_io_i0_brp_hist), + .io_i0_brp_br_error(dec_io_i0_brp_br_error), + .io_i0_brp_br_start_error(dec_io_i0_brp_br_start_error), + .io_i0_brp_prett(dec_io_i0_brp_prett), + .io_i0_brp_way(dec_io_i0_brp_way), + .io_i0_brp_ret(dec_io_i0_brp_ret), .io_ifu_i0_bp_index(dec_io_ifu_i0_bp_index), .io_ifu_i0_bp_fghr(dec_io_ifu_i0_bp_fghr), .io_ifu_i0_bp_btag(dec_io_ifu_i0_bp_btag), @@ -81357,22 +81368,22 @@ module el2_swerv( .io_dec_dbg_cmd_done(dec_io_dec_dbg_cmd_done), .io_dec_dbg_cmd_fail(dec_io_dec_dbg_cmd_fail), .io_trigger_pkt_any_0_select(dec_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(dec_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(dec_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(dec_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(dec_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_tdata2(dec_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(dec_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(dec_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(dec_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(dec_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(dec_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_tdata2(dec_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(dec_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(dec_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(dec_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(dec_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(dec_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_tdata2(dec_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(dec_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(dec_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(dec_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(dec_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(dec_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_tdata2(dec_io_trigger_pkt_any_3_tdata2), @@ -81442,11 +81453,11 @@ module el2_swerv( .io_dec_tlu_fence_i_r(dec_io_dec_tlu_fence_i_r), .io_pred_correct_npc_x(dec_io_pred_correct_npc_x), .io_dec_tlu_br0_r_pkt_valid(dec_io_dec_tlu_br0_r_pkt_valid), - .io_dec_tlu_br0_r_pkt_bits_hist(dec_io_dec_tlu_br0_r_pkt_bits_hist), - .io_dec_tlu_br0_r_pkt_bits_br_error(dec_io_dec_tlu_br0_r_pkt_bits_br_error), - .io_dec_tlu_br0_r_pkt_bits_br_start_error(dec_io_dec_tlu_br0_r_pkt_bits_br_start_error), - .io_dec_tlu_br0_r_pkt_bits_way(dec_io_dec_tlu_br0_r_pkt_bits_way), - .io_dec_tlu_br0_r_pkt_bits_middle(dec_io_dec_tlu_br0_r_pkt_bits_middle), + .io_dec_tlu_br0_r_pkt_hist(dec_io_dec_tlu_br0_r_pkt_hist), + .io_dec_tlu_br0_r_pkt_br_error(dec_io_dec_tlu_br0_r_pkt_br_error), + .io_dec_tlu_br0_r_pkt_br_start_error(dec_io_dec_tlu_br0_r_pkt_br_start_error), + .io_dec_tlu_br0_r_pkt_way(dec_io_dec_tlu_br0_r_pkt_way), + .io_dec_tlu_br0_r_pkt_middle(dec_io_dec_tlu_br0_r_pkt_middle), .io_dec_tlu_perfcnt0(dec_io_dec_tlu_perfcnt0), .io_dec_tlu_perfcnt1(dec_io_dec_tlu_perfcnt1), .io_dec_tlu_perfcnt2(dec_io_dec_tlu_perfcnt2), @@ -81672,22 +81683,22 @@ module el2_swerv( .io_lsu_p_bits_store_data_bypass_d(lsu_io_lsu_p_bits_store_data_bypass_d), .io_lsu_p_bits_load_ldst_bypass_d(lsu_io_lsu_p_bits_load_ldst_bypass_d), .io_trigger_pkt_any_0_select(lsu_io_trigger_pkt_any_0_select), - .io_trigger_pkt_any_0_match_(lsu_io_trigger_pkt_any_0_match_), + .io_trigger_pkt_any_0_match_pkt(lsu_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_store(lsu_io_trigger_pkt_any_0_store), .io_trigger_pkt_any_0_load(lsu_io_trigger_pkt_any_0_load), .io_trigger_pkt_any_0_tdata2(lsu_io_trigger_pkt_any_0_tdata2), .io_trigger_pkt_any_1_select(lsu_io_trigger_pkt_any_1_select), - .io_trigger_pkt_any_1_match_(lsu_io_trigger_pkt_any_1_match_), + .io_trigger_pkt_any_1_match_pkt(lsu_io_trigger_pkt_any_1_match_pkt), .io_trigger_pkt_any_1_store(lsu_io_trigger_pkt_any_1_store), .io_trigger_pkt_any_1_load(lsu_io_trigger_pkt_any_1_load), .io_trigger_pkt_any_1_tdata2(lsu_io_trigger_pkt_any_1_tdata2), .io_trigger_pkt_any_2_select(lsu_io_trigger_pkt_any_2_select), - .io_trigger_pkt_any_2_match_(lsu_io_trigger_pkt_any_2_match_), + .io_trigger_pkt_any_2_match_pkt(lsu_io_trigger_pkt_any_2_match_pkt), .io_trigger_pkt_any_2_store(lsu_io_trigger_pkt_any_2_store), .io_trigger_pkt_any_2_load(lsu_io_trigger_pkt_any_2_load), .io_trigger_pkt_any_2_tdata2(lsu_io_trigger_pkt_any_2_tdata2), .io_trigger_pkt_any_3_select(lsu_io_trigger_pkt_any_3_select), - .io_trigger_pkt_any_3_match_(lsu_io_trigger_pkt_any_3_match_), + .io_trigger_pkt_any_3_match_pkt(lsu_io_trigger_pkt_any_3_match_pkt), .io_trigger_pkt_any_3_store(lsu_io_trigger_pkt_any_3_store), .io_trigger_pkt_any_3_load(lsu_io_trigger_pkt_any_3_load), .io_trigger_pkt_any_3_tdata2(lsu_io_trigger_pkt_any_3_tdata2), @@ -82025,11 +82036,11 @@ module el2_swerv( assign ifu_io_exu_mp_index = exu_io_exu_mp_index; // @[el2_swerv.scala 385:23] assign ifu_io_exu_mp_btag = exu_io_exu_mp_btag; // @[el2_swerv.scala 386:22] assign ifu_io_dec_tlu_br0_r_pkt_valid = dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 387:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_hist = dec_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 387:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_br_error = dec_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 387:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_swerv.scala 387:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_way = dec_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_swerv.scala 387:28] - assign ifu_io_dec_tlu_br0_r_pkt_bits_middle = dec_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_hist = dec_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_br_error = dec_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_br_start_error = dec_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_way = dec_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 387:28] + assign ifu_io_dec_tlu_br0_r_pkt_middle = dec_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 387:28] assign ifu_io_exu_i0_br_fghr_r = exu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 388:27] assign ifu_io_exu_i0_br_index_r = exu_io_exu_i0_br_index_r; // @[el2_swerv.scala 389:28] assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 390:33] @@ -82096,13 +82107,13 @@ module el2_swerv( assign dec_io_ifu_i0_dbecc = ifu_io_ifu_i0_dbecc; // @[el2_swerv.scala 449:23] assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[el2_swerv.scala 450:23] assign dec_io_i0_brp_valid = ifu_io_i0_brp_valid; // @[el2_swerv.scala 451:17] - assign dec_io_i0_brp_bits_toffset = ifu_io_i0_brp_bits_toffset; // @[el2_swerv.scala 451:17] - assign dec_io_i0_brp_bits_hist = ifu_io_i0_brp_bits_hist; // @[el2_swerv.scala 451:17] - assign dec_io_i0_brp_bits_br_error = ifu_io_i0_brp_bits_br_error; // @[el2_swerv.scala 451:17] - assign dec_io_i0_brp_bits_br_start_error = ifu_io_i0_brp_bits_br_start_error; // @[el2_swerv.scala 451:17] - assign dec_io_i0_brp_bits_prett = ifu_io_i0_brp_bits_prett; // @[el2_swerv.scala 451:17] - assign dec_io_i0_brp_bits_way = ifu_io_i0_brp_bits_way; // @[el2_swerv.scala 451:17] - assign dec_io_i0_brp_bits_ret = ifu_io_i0_brp_bits_ret; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_toffset = ifu_io_i0_brp_toffset; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_hist = ifu_io_i0_brp_hist; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_br_error = ifu_io_i0_brp_br_error; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_br_start_error = ifu_io_i0_brp_br_start_error; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_prett = ifu_io_i0_brp_prett; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_way = ifu_io_i0_brp_way; // @[el2_swerv.scala 451:17] + assign dec_io_i0_brp_ret = ifu_io_i0_brp_ret; // @[el2_swerv.scala 451:17] assign dec_io_ifu_i0_bp_index = ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 452:26] assign dec_io_ifu_i0_bp_fghr = ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 453:25] assign dec_io_ifu_i0_bp_btag = ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 454:25] @@ -82271,22 +82282,22 @@ module el2_swerv( assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[el2_swerv.scala 548:16] assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[el2_swerv.scala 548:16] assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[el2_swerv.scala 551:26] - assign lsu_io_trigger_pkt_any_0_match_ = dec_io_trigger_pkt_any_0_match_; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[el2_swerv.scala 551:26] - assign lsu_io_trigger_pkt_any_1_match_ = dec_io_trigger_pkt_any_1_match_; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[el2_swerv.scala 551:26] - assign lsu_io_trigger_pkt_any_2_match_ = dec_io_trigger_pkt_any_2_match_; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[el2_swerv.scala 551:26] - assign lsu_io_trigger_pkt_any_3_match_ = dec_io_trigger_pkt_any_3_match_; // @[el2_swerv.scala 551:26] + assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[el2_swerv.scala 551:26] assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[el2_swerv.scala 551:26] diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index 4ec29fe7..bde2aec4 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1 +1,3 @@ -/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v \ No newline at end of file +/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v +/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv +/home/laraibkhan/Desktop/SweRV-Chislified/el2_mem.sv \ No newline at end of file diff --git a/src/main/scala/dec/el2_dec.scala b/src/main/scala/dec/el2_dec.scala index 4d898696..5bafa63e 100644 --- a/src/main/scala/dec/el2_dec.scala +++ b/src/main/scala/dec/el2_dec.scala @@ -96,7 +96,7 @@ class el2_dec_IO extends Bundle with el2_lib { val lsu_idle_any = Input(Bool()) // lsu idle for halting - val i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet + val i0_brp = Input(new el2_br_pkt_t) // branch packet val ifu_i0_bp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // BP index val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag @@ -223,7 +223,7 @@ class el2_dec_IO extends Bundle with el2_lib { val pred_correct_npc_x = Output(UInt(31.W)) // npc if prediction is correct at e2 stage - val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet + val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc @@ -599,6 +599,6 @@ class el2_dec extends Module with param with RequireAsyncReset{ // debug command read data io.dec_dbg_rddata := decode.io.dec_i0_wdata_r } -object decode extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec())) +object dec_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog( new el2_dec())) } \ No newline at end of file diff --git a/src/main/scala/dec/el2_dec_dec_ctl.scala b/src/main/scala/dec/el2_dec_dec_ctl.scala index 0a0d95f4..31a33a93 100644 --- a/src/main/scala/dec/el2_dec_dec_ctl.scala +++ b/src/main/scala/dec/el2_dec_dec_ctl.scala @@ -1,173 +1,125 @@ package dec import chisel3._ -import chisel3.util._ +import include._ +import lib._ -class el2_dec_pkt_t extends Bundle{ - val alu = Bool() - val rs1 = Bool() - val rs2 = Bool() - val imm12 = Bool() - val rd = Bool() - val shimm5 = Bool() - val imm20 = Bool() - val pc = Bool() - val load = Bool() - val store = Bool() - val lsu = Bool() - val add = Bool() - val sub = Bool() - val land = Bool() - val lor = Bool() - val lxor = Bool() - val sll = Bool() - val sra = Bool() - val srl = Bool() - val slt = Bool() - val unsign = Bool() - val condbr = Bool() - val beq = Bool() - val bne = Bool() - val bge = Bool() - val blt = Bool() - val jal = Bool() - val by = Bool() - val half = Bool() - val word = Bool() - val csr_read = Bool() - val csr_clr = Bool() - val csr_set = Bool() - val csr_write = Bool() - val csr_imm = Bool() - val presync = Bool() - val postsync = Bool() - val ebreak = Bool() - val ecall = Bool() - val mret = Bool() - val mul = Bool() - val rs1_sign = Bool() - val rs2_sign = Bool() - val low = Bool() - val div = Bool() - val rem = Bool() - val fence = Bool() - val fence_i = Bool() - val pm_alu = Bool() - val legal = Bool() -} - -class el2_dec_dec_ctl extends Module{ +class el2_dec_dec_ctl extends Module with el2_lib{ val io = IO (new Bundle{ val ins = Input(UInt(32.W)) val out = Output(new el2_dec_pkt_t) }) - def pattern(y : List[Int]) : Array[UInt] = { + def pattern(y : List[Int]) : UInt = { val pat : Array[UInt] = new Array[UInt](y.size) for (i <- 0 until y.size){ - pat(i) = if(y(i)>0) io.ins(y(i)) else !io.ins(y(i).abs) + pat(i) = if(y(i)>=0) io.ins(y(i)) else !io.ins(y(i).abs) } - pat + pat.reduce(_&_) } io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4)) - io.out.rs1 := pattern(List(-14,-13,-2)).reduce(_&_) | pattern(List(-13,11,-2)).reduce(_&_) | - pattern(List(19,13,-2)).reduce(_&_) | pattern(List(-13,10,-2)).reduce(_&_) | - pattern(List(-18,13,-2)).reduce(_&_) | pattern(List(-13,9,-2)).reduce(_&_) | - pattern(List(17,13,-2)).reduce(_&_) | pattern(List(-13,8,-2)).reduce(_&_) | - pattern(List(16,13,-2)).reduce(_&_) | pattern(List(-13,7,-2)).reduce(_&_) | - pattern(List(15,13,-2)).reduce(_&_) |pattern(List(-4,-3)).reduce(_&_) | pattern(List(-6,-2)).reduce(_&_) - io.out.rs2 := pattern(List(5,-4,-2)).reduce(_&_) | pattern(List(-6,5,-2)).reduce(_&_) - io.out.imm12 := pattern(List(-4,-3,2)).reduce(_&_) | pattern(List(13,-5,4,-2)).reduce(_&_) | - pattern(List(-13,-12,6,4)).reduce(_&_) | pattern(List(-12,-5,4,-2)).reduce(_&_) + io.out.rs1 := pattern(List(-14,-13,-2)) | pattern(List(-13,11,-2)) | + pattern(List(19,13,-2)) | pattern(List(-13,10,-2)) | + pattern(List(18,13,-2)) | pattern(List(-13,9,-2)) | + pattern(List(17,13,-2)) | pattern(List(-13,8,-2)) | + pattern(List(16,13,-2)) | pattern(List(-13,7,-2)) | + pattern(List(15,13,-2)) |pattern(List(-4,-3)) | pattern(List(-6,-2)) + io.out.rs2 := pattern(List(5,-4,-2)) | pattern(List(-6,5,-2)) + io.out.imm12 := pattern(List(-4,-3,2)) | pattern(List(13,-5,4,-2)) | + pattern(List(-13,-12,6,4)) | pattern(List(-12,-5,4,-2)) io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4) - io.out.shimm5 := pattern(List(-13,12,-5,4,-2)).reduce(_&_) + io.out.shimm5 := pattern(List(-13,12,-5,4,-2)) io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2)) io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3)) - io.out.load := pattern(List(-5,-4,-2)).reduce(_&_) - io.out.store := pattern(List(-6,5,-4)).reduce(_&_) - io.out.lsu := pattern(List(-6,-4,-2)).reduce(_&_) - io.out.add := pattern(List(-14,-13,-12,-5,4)).reduce(_&_) | pattern(List(-5,-3,2)).reduce(_&_) | - pattern(List(-30,-25,-14,-13,-12,-6,4,-2)).reduce(_&_) - io.out.sub := pattern(List(30,-12,-6,5,4,-2)).reduce(_&_) | pattern(List(-25,-14,13,-6,4,-2)).reduce(_&_) | - pattern(List(-14,13,-5,4,-2)).reduce(_&_) | pattern(List(6,-4,-2)).reduce(_&_) - io.out.land := pattern(List(14,13,12,-5,-2)).reduce(_&_) | pattern(List(-25,14,13,12,-6,-2)).reduce(_&_) - io.out.lor := pattern(List(-6,3)).reduce(_&_) | pattern(List(-25,14,13,-12,-6,-2)).reduce(_&_) | - pattern(List(5,4,2)).reduce(_&_) | pattern(List(-13,-12,6,4)).reduce(_&_) | - pattern(List(14,13,-12,-5,-2)).reduce(_&_) - io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)).reduce(_&_) | pattern(List(14,-13,-12,-5,4,-2)).reduce(_&_) - io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2)).reduce(_&_) - io.out.sra := pattern(List(30,-13,12,-6,4,-2)).reduce(_&_) - io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2)).reduce(_&_) - io.out.slt := pattern(List(-25,-14,13,12,-6,4,-2)).reduce(_&_) | pattern(List(-14,13,-5,4,-2)).reduce(_&_) - io.out.unsign := pattern(List(-14,13,12,-5,-2)).reduce(_&_) | pattern(List(13,6,-4,-2)).reduce(_&_) | - pattern(List(14,-5,-4)).reduce(_&_) | pattern(List(-25,-14,13,12,-6,-2)).reduce(_&_) | - pattern(List(25,14,12,-6,5,-2)).reduce(_&_) - io.out.condbr := pattern(List(6,-4,-2)).reduce(_&_) - io.out.beq := pattern(List(-14,-12,6,-4,-2)).reduce(_&_) - io.out.bne := pattern(List(-14,12,6,-4,-2)).reduce(_&_) - io.out.bge := pattern(List(14,12,5,-4,-2)).reduce(_&_) - io.out.blt := pattern(List(14,-12,5,-4,-2)).reduce(_&_) - io.out.jal := pattern(List(6,2)).reduce(_&_) - io.out.by := pattern(List(-13,-12,-6,-4,-2)).reduce(_&_) - io.out.half := pattern(List(12,-6,-4,-2)).reduce(_&_) - io.out.word := pattern(List(13,-6,-4)).reduce(_&_) - io.out.csr_read := pattern(List(13,6,4)).reduce(_&_) | pattern(List(7,6,4)).reduce(_&_) | - pattern(List(8,6,4)).reduce(_&_) | pattern(List(9,6,4)).reduce(_&_) | pattern(List(10,6,4)).reduce(_&_) | - pattern(List(11,6,4)).reduce(_&_) - io.out.csr_clr := pattern(List(15,13,12,6,4)).reduce(_&_) | pattern(List(16,13,12,6,4)).reduce(_&_) | - pattern(List(17,13,12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) | - pattern(List(19,-12,6,4)).reduce(_&_) - io.out.csr_write := pattern(List(-13,12,6,4)).reduce(_&_) - io.out.csr_imm := pattern(List(14,-13,6,4)).reduce(_&_) | pattern(List(15,14,6,4)).reduce(_&_) | - pattern(List(16,14,6,4)).reduce(_&_) | pattern(List(17,14,6,4)).reduce(_&_) | - pattern(List(18,14,6,4)).reduce(_&_) | pattern(List(19,14,6,4)).reduce(_&_) - io.out.csr_set := pattern(List(15,-12,6,4)).reduce(_&_) | pattern(List(16,-12,6,4)).reduce(_&_) | - pattern(List(17,-12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) | - pattern(List(19,-12,6,4)).reduce(_&_) - io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)).reduce(_&_) - io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)).reduce(_&_) - io.out.mret := pattern(List(29,-13,-12,6,4)).reduce(_&_) - io.out.mul := pattern(List(25,-14,-6,5,4,-2)).reduce(_&_) - io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)).reduce(_&_) | - pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_) - io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_) - io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)).reduce(_&_) - io.out.div := pattern(List(25,14,-6,5,-2)).reduce(_&_) - io.out.rem := pattern(List(25,14,13,-6,5,-2)).reduce(_&_) - io.out.fence := pattern(List(-5,3)).reduce(_&_) - io.out.fence_i := pattern(List(12,-5,3)).reduce(_&_) - io.out.pm_alu := pattern(List(28,22,-13,-12,4)).reduce(_&_) | pattern(List(4,2)).reduce(_&_) | - pattern(List(-25,-6,4)).reduce(_&_) | pattern(List(-5,4)).reduce(_&_) - io.out.presync := pattern(List(-5,3)).reduce(_&_) | pattern(List(-13,7,6,4)).reduce(_&_) | - pattern(List(-13,8,6,4)).reduce(_&_) | pattern(List(-13,9,6,4)).reduce(_&_) | - pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) | - pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) | - pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) | - pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_) - io.out.postsync := pattern(List(12,-5,3)).reduce(_&_) | pattern(List(-22,-13,-12,6,4)).reduce(_&_) | - pattern(List(-13,7,6,4)).reduce(_&_) | pattern(List(-13,8,6,4)).reduce(_&_) | - pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) | - pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) | - pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) | - pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_) - io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) | - pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) | - pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)).reduce(_&_) | - pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)).reduce(_&_) | - pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)).reduce(_&_) | - pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)).reduce(_&_) | - pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)).reduce(_&_) | - pattern(List(-14,-13,-12,6,5,-4,-3,1,0)).reduce(_&_) | - pattern(List(14,6,5,-4,-3,-2,1,0)).reduce(_&_) | - pattern(List(-12,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-13,5,-4,-3,-2,1,0)).reduce(_&_) | - pattern(List(12,6,5,4,-3,-2,1,0)).reduce(_&_) | - pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) | - pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) | - pattern(List(-13,-6,-5,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(6,5,-4,3,2,1,0)).reduce(_&_) | - pattern(List(13,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)).reduce(_&_) | - pattern(List(-6,4,-3,-2,1,0)).reduce(_&_) + io.out.load := pattern(List(-5,-4,-2)) + io.out.store := pattern(List(-6,5,-4)) + io.out.lsu := pattern(List(-6,-4,-2)) + io.out.add := pattern(List(-14,-13,-12,-5,4)) | pattern(List(-5,-3,2)) | + pattern(List(-30,-25,-14,-13,-12,-6,4,-2)) + io.out.sub := pattern(List(30,-12,-6,5,4,-2)) | pattern(List(-25,-14,13,-6,4,-2)) | + pattern(List(-14,13,-5,4,-2)) | pattern(List(6,-4,-2)) + io.out.land := pattern(List(14,13,12,-5,-2)) | pattern(List(-25,14,13,12,-6,-2)) + io.out.lor := pattern(List(-6,3)) | pattern(List(-25,14,13,-12,-6,-2)) | + pattern(List(5,4,2)) | pattern(List(-13,-12,6,4)) | + pattern(List(14,13,-12,-5,-2)) + io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)) | pattern(List(14,-13,-12,-5,4,-2)) + io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2)) + io.out.sra := pattern(List(30,-13,12,-6,4,-2)) + io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2)) + io.out.slt := pattern(List(-25,-14,13,-6,4,-2)) | pattern(List(-14,13,-5,4,-2)) + io.out.unsign := pattern(List(-14,13,12,-5,-2)) | pattern(List(13,6,-4,-2)) | + pattern(List(14,-5,-4)) | pattern(List(-25,-14,13,12,-6,-2)) | + pattern(List(25,14,12,-6,5,-2)) + io.out.condbr := pattern(List(6,-4,-2)) + io.out.beq := pattern(List(-14,-12,6,-4,-2)) + io.out.bne := pattern(List(-14,12,6,-4,-2)) + io.out.bge := pattern(List(14,12,5,-4,-2)) + io.out.blt := pattern(List(14,-12,5,-4,-2)) + io.out.jal := pattern(List(6,2)) + io.out.by := pattern(List(-13,-12,-6,-4,-2)) + io.out.half := pattern(List(12,-6,-4,-2)) + io.out.word := pattern(List(13,-6,-4)) + io.out.csr_read := pattern(List(13,6,4)) | pattern(List(7,6,4)) | + pattern(List(8,6,4)) | pattern(List(9,6,4)) | pattern(List(10,6,4)) | + pattern(List(11,6,4)) + io.out.csr_clr := pattern(List(15,13,12,6,4)) | pattern(List(16,13,12,6,4)) | + pattern(List(17,13,12,6,4)) | pattern(List(18,13,12,6,4)) | + pattern(List(19,13,12,6,4)) + io.out.csr_write := pattern(List(-13,12,6,4)) + io.out.csr_imm := pattern(List(14,-13,6,4)) | pattern(List(15,14,6,4)) | + pattern(List(16,14,6,4)) | pattern(List(17,14,6,4)) | + pattern(List(18,14,6,4)) | pattern(List(19,14,6,4)) + io.out.csr_set := pattern(List(15,-12,6,4)) | pattern(List(16,-12,6,4)) | + pattern(List(17,-12,6,4)) | pattern(List(18,-12,6,4)) | + pattern(List(19,-12,6,4)) + io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)) + io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)) + io.out.mret := pattern(List(29,-13,-12,6,4)) + io.out.mul := pattern(List(25,-14,-6,5,4,-2)) + io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)) | + pattern(List(25,-14,-13,12,-6,4,-2)) + io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2)) + io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)) + io.out.div := pattern(List(25,14,-6,5,-2)) + io.out.rem := pattern(List(25,14,13,-6,5,-2)) + io.out.fence := pattern(List(-5,3)) + io.out.fence_i := pattern(List(12,-5,3)) + io.out.pm_alu := pattern(List(28,22,-13,-12,4)) | pattern(List(4,2)) | + pattern(List(-25,-6,4)) | pattern(List(-5,4)) + io.out.presync := pattern(List(-5,3)) | pattern(List(-13,7,6,4)) | + pattern(List(-13,8,6,4)) | pattern(List(-13,9,6,4)) | + pattern(List(-13,10,6,4)) | pattern(List(-13,11,6,4)) | + pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) | + pattern(List(17,13,6,4)) | pattern(List(18,13,6,4)) | + pattern(List(19,13,6,4)) + io.out.postsync := pattern(List(12,-5,3)) | pattern(List(-22,-13,-12,6,4)) | + pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) | + pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) | + pattern(List(-13,11,6,4)) | pattern(List(15,13,6,4)) | + pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) | + pattern(List(18,13,6,4)) | pattern(List(19,13,6,4)) + io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) | + pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) | + pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)) | + pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)) | + pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)) | + pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)) | + pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)) | + pattern(List(-14,-13,-12,6,5,-4,-3,1,0)) | + pattern(List(14,6,5,-4,-3,-2,1,0)) | + pattern(List(-12,-6,-5,4,-3,1,0)) | + pattern(List(-14,-13,5,-4,-3,-2,1,0)) | + pattern(List(12,6,5,4,-3,-2,1,0)) | + pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) | + pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) | + pattern(List(13,6,5,4,-3,-2,1,0)) | + pattern(List(-13,-6,-5,-4,-3,-2,1,0)) | + pattern(List(6,5,-4,3,2,1,0)) | + pattern(List(13,-6,-5,4,-3,1,0)) | + pattern(List(-14,-12,-6,-4,-3,-2,1,0)) | + pattern(List(-6,4,-3,2,1,0)) } -//object dec extends App { -// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_dec_ctl())) -//} +object dec_dec_ctl extends App { + chisel3.Driver execute(args, () => new el2_dec_dec_ctl()) +} diff --git a/src/main/scala/dec/el2_dec_decode_ctl.scala b/src/main/scala/dec/el2_dec_decode_ctl.scala index 65912352..4b9c91c4 100644 --- a/src/main/scala/dec/el2_dec_decode_ctl.scala +++ b/src/main/scala/dec/el2_dec_decode_ctl.scala @@ -35,7 +35,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error - val dec_i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet + val dec_i0_brp = Input(new el2_br_pkt_t) // branch packet val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag @@ -144,13 +144,13 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ val i0_rs1_depth_d = WireInit(UInt(2.W),0.U) val i0_rs2_depth_d = WireInit(UInt(2.W),0.U) val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) - val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t))) + val cam = Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t)) val cam_write=WireInit(UInt(1.W), 0.U) val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) - val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t))) - val cam_in =Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t))) + val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t)) + val cam_in =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t)) //val i0_temp = Wire(new el2_inst_pkt_t) val i0_dp= Wire(new el2_dec_pkt_t) val i0_dp_raw= Wire(new el2_dec_pkt_t) @@ -230,24 +230,24 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ io.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error io.dec_i0_predict_p_d.bits.pja := i0_pja io.dec_i0_predict_p_d.bits.pret := i0_pret - io.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett + io.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.prett io.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d - io.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist + io.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.hist io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw) // no toffset error for a pret - val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw - val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw; - val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error + val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw + val i0_ret_error = i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw; + val i0_br_error = io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error io.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode - io.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode + io.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode io.i0_predict_index_d := io.dec_i0_bp_index io.i0_predict_btag_d := io.dec_i0_bp_btag - val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode + val i0_br_error_all = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode io.dec_i0_predict_p_d.bits.toffset := i0_br_offset io.i0_predict_fghr_d := io.dec_i0_bp_fghr - io.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way + io.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.way // end // on br error turn anything into a nop @@ -273,8 +273,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ // branches that can be predicted val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; - val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br - val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br + val i0_predict_nt = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br + val i0_predict_t = (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br val i0_ap_pc2 = !io.dec_i0_pc4_d val i0_ap_pc4 = io.dec_i0_pc4_d io.i0_ap.predict_nt := i0_predict_nt @@ -318,8 +318,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load for(i <- 0 until LSU_NUM_NBLOAD){ - cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid - cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid + cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).tag) & cam(i).valid + cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).tag) & cam_raw(i).valid cam_in(i):=0.U.asTypeOf(cam(0)) cam(i):=cam_raw(i) @@ -328,16 +328,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ } when(cam_wen(i).asBool){ cam_in(i).valid := 1.U(1.W) - cam_in(i).bits.wb := 0.U(1.W) - cam_in(i).bits.tag := cam_write_tag - cam_in(i).bits.rd := nonblock_load_rd - }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){ + cam_in(i).wb := 0.U(1.W) + cam_in(i).tag := cam_write_tag + cam_in(i).rd := nonblock_load_rd + }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).rd) && cam(i).wb.asBool)){ cam_in(i).valid := 0.U }.otherwise{ cam_in(i) := cam(i) } - when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).bits.tag) && cam(i).valid===1.U){ - cam_in(i).bits.wb := 1.U + when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).tag) && cam(i).valid===1.U){ + cam_in(i).wb := 1.U } // force debug halt forces cam valids to 0; highest priority when(io.dec_tlu_force_halt){ @@ -345,7 +345,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ } cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))} - nonblock_load_write(i) := (load_data_tag === cam_raw(i).bits.tag) & cam_raw(i).valid + nonblock_load_write(i) := (load_data_tag === cam_raw(i).tag) & cam_raw(i).valid } io.dec_nonblock_load_waddr:=0.U(5.W) @@ -356,7 +356,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ i0_nonblock_load_stall := i0_nonblock_boundary_stall - val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).bits.rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs2)) + val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).rd === i0r.rs2)) val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) ) io.dec_nonblock_load_waddr:=waddr i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall @@ -819,6 +819,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ (!io.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20), (!io.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7)))) } -object decode_ctrl extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_decode_ctl())) + +object dec_decode extends App{ + chisel3.Driver.emitVerilog(new el2_dec_decode_ctl) } diff --git a/src/main/scala/dec/el2_dec_gpr_ctl.scala b/src/main/scala/dec/el2_dec_gpr_ctl.scala index b37f7f0e..6dfc2509 100644 --- a/src/main/scala/dec/el2_dec_gpr_ctl.scala +++ b/src/main/scala/dec/el2_dec_gpr_ctl.scala @@ -5,14 +5,24 @@ import chisel3.util._ import include._ import lib._ -class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib { +class el2_dec_gpr_ctl extends Module with el2_lib with RequireAsyncReset{ val io =IO(new el2_dec_gpr_ctl_IO) val w0v =Wire(Vec(32,UInt(1.W))) + w0v := (0 until 32).map(i => 0.U) + val w1v =Wire(Vec(32,UInt(1.W))) + w1v := (0 until 32).map(i => 0.U) + val w2v =Wire(Vec(32,UInt(1.W))) + w2v := (0 until 32).map(i => 0.U) + val gpr_in =Wire(Vec(32,UInt(32.W))) + gpr_in := (0 until 32).map(i => 0.U) + val gpr_out =Wire(Vec(32,UInt(32.W))) - val gpr_wr_en =Wire(UInt(32.W)) + gpr_out := (0 until 32).map(i => 0.U) + + val gpr_wr_en =WireInit(UInt(32.W),0.U) w0v(0):=0.U w1v(0):=0.U w2v(0):=0.U @@ -20,7 +30,6 @@ class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib { gpr_in(0):=0.U io.rd0:=0.U io.rd1:=0.U - gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_)) // GPR Write logic for (j <-1 until 32){ w0v(j) := io.wen0 & (io.waddr0===j.asUInt) @@ -28,6 +37,8 @@ class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib { w2v(j) := io.wen2 & (io.waddr2===j.asUInt) gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2) } + gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_)) + // GPR Write Enables for power savings for (j <-1 until 32){ gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode) @@ -54,5 +65,5 @@ class el2_dec_gpr_ctl_IO extends Bundle{ val scan_mode=Input(Bool()) } object gpr_gen extends App{ - println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_gpr_ctl))) + println(chisel3.Driver.emitVerilog(new el2_dec_gpr_ctl)) } diff --git a/src/main/scala/dec/el2_dec_ib_ctl.scala b/src/main/scala/dec/el2_dec_ib_ctl.scala index 81f14ddb..89d73c8a 100644 --- a/src/main/scala/dec/el2_dec_ib_ctl.scala +++ b/src/main/scala/dec/el2_dec_ib_ctl.scala @@ -3,41 +3,6 @@ import include._ import chisel3._ import chisel3.util._ import lib._ - -class el2_dec_ib_ctl_IO extends Bundle with param{ - val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd - val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write - val dbg_cmd_type =Input(UInt(2.W)) // dbg type - val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0 - val i0_brp =Flipped(Valid(new el2_br_pkt_t)) // i0 branch packet from aligner - val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size) - val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR - val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag - val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B - val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu - val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault - val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type - val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group - val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error - val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner - val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner - - val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid - val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type - val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode - val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode - val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B - val dec_i0_brp =Valid(new el2_br_pkt_t) // i0 branch packet at decode - val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index - val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR - val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag - val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode - val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group - val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode - val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted - val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst -} - class el2_dec_ib_ctl extends Module with param{ val io=IO(new el2_dec_ib_ctl_IO) io.dec_i0_icaf_f1_d :=io.ifu_i0_icaf_f1 @@ -46,7 +11,7 @@ class el2_dec_ib_ctl extends Module with param{ io.dec_i0_pc_d :=io.ifu_i0_pc io.dec_i0_pc4_d :=io.ifu_i0_pc4 io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type - io.dec_i0_brp <>io.i0_brp + io.dec_i0_brp :=io.i0_brp io.dec_i0_bp_index :=io.ifu_i0_bp_index io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr io.dec_i0_bp_btag :=io.ifu_i0_bp_btag @@ -77,9 +42,9 @@ class el2_dec_ib_ctl extends Module with param{ val ib0_debug_in =Mux1H(Seq( debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U), - debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)), - debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)), - debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W)) + debug_write_gpr.asBool -> Cat("b00000000000000000110".U,dreg,"b0110011".U), + debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U), + debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U) )) // machine is in halted state, pipe empty, write will always happen next cycle @@ -93,7 +58,39 @@ class el2_dec_ib_ctl extends Module with param{ } +class el2_dec_ib_ctl_IO extends Bundle with param{ + val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd + val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write + val dbg_cmd_type =Input(UInt(2.W)) // dbg type + val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0 + val i0_brp =Input(new el2_br_pkt_t) // i0 branch packet from aligner + val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size) + val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR + val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag + val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B + val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu + val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault + val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type + val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group + val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error + val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner + val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner -object ib_gen extends App{ - println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_ib_ctl))) + val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid + val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type + val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode + val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode + val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B + val dec_i0_brp =Output(new el2_br_pkt_t) // i0 branch packet at decode + val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index + val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR + val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag + val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode + val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group + val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode + val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted + val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst +} +object ib_gen extends App{ + chisel3.Driver.emitVerilog(new el2_dec_ib_ctl) } diff --git a/src/main/scala/dec/el2_dec_tlu_ctl.scala b/src/main/scala/dec/el2_dec_tlu_ctl.scala index c5555887..ba15f177 100644 --- a/src/main/scala/dec/el2_dec_tlu_ctl.scala +++ b/src/main/scala/dec/el2_dec_tlu_ctl.scala @@ -188,7 +188,7 @@ class el2_dec_tlu_ctl_IO extends Bundle with el2_lib { val dec_tlu_meipt = Output(UInt(4.W)) // to PIC val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation - val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // branch pkt to bp + val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // branch pkt to bp val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state val dec_tlu_flush_lower_wb = Output(UInt(1.W)) // commit has a flush (exception, int, mispredict at e4) val dec_tlu_i0_commit_cmt = Output(UInt(1.W)) // committed an instruction @@ -234,122 +234,122 @@ class el2_dec_tlu_ctl_IO extends Bundle with el2_lib { class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CSR_VAL{ val io = IO(new el2_dec_tlu_ctl_IO) val mtdata1_t = Wire(Vec(4,UInt(10.W))) - val pause_expired_wb =Wire(UInt(1.W)) - val take_nmi_r_d1 =Wire(UInt(1.W)) - val exc_or_int_valid_r_d1 =Wire(UInt(1.W)) - val interrupt_valid_r_d1 =Wire(UInt(1.W)) - val tlu_flush_lower_r =Wire(UInt(1.W)) - val synchronous_flush_r =Wire(UInt(1.W)) - val interrupt_valid_r =Wire(UInt(1.W)) - val take_nmi =Wire(UInt(1.W)) - val take_reset =Wire(UInt(1.W)) - val take_int_timer1_int =Wire(UInt(1.W)) - val take_int_timer0_int =Wire(UInt(1.W)) - val take_timer_int =Wire(UInt(1.W)) - val take_soft_int =Wire(UInt(1.W)) - val take_ce_int =Wire(UInt(1.W)) - val take_ext_int_start =Wire(UInt(1.W)) - val ext_int_freeze =Wire(UInt(1.W)) - val ext_int_freeze_d1 =Wire(UInt(1.W)) - val take_ext_int_start_d1 =Wire(UInt(1.W)) - val take_ext_int_start_d2 =Wire(UInt(1.W)) - val take_ext_int_start_d3 =Wire(UInt(1.W)) - val fast_int_meicpct =Wire(UInt(1.W)) - val ignore_ext_int_due_to_lsu_stall =Wire(UInt(1.W)) - val take_ext_int =Wire(UInt(1.W)) - val internal_dbg_halt_timers =Wire(UInt(1.W)) - val int_timer1_int_hold =Wire(UInt(1.W)) - val int_timer0_int_hold =Wire(UInt(1.W)) - val mhwakeup_ready =Wire(UInt(1.W)) - val ext_int_ready =Wire(UInt(1.W)) - val ce_int_ready =Wire(UInt(1.W)) - val soft_int_ready =Wire(UInt(1.W)) - val timer_int_ready =Wire(UInt(1.W)) - val ebreak_to_debug_mode_r_d1 =Wire(UInt(1.W)) - val ebreak_to_debug_mode_r =Wire(UInt(1.W)) - val inst_acc_r =Wire(UInt(1.W)) - val inst_acc_r_raw =Wire(UInt(1.W)) - val iccm_sbecc_r =Wire(UInt(1.W)) - val ic_perr_r =Wire(UInt(1.W)) - val fence_i_r =Wire(UInt(1.W)) - val ebreak_r =Wire(UInt(1.W)) - val ecall_r =Wire(UInt(1.W)) - val illegal_r =Wire(UInt(1.W)) - val mret_r =Wire(UInt(1.W)) - val iccm_repair_state_ns =Wire(UInt(1.W)) - val rfpc_i0_r =Wire(UInt(1.W)) - val tlu_i0_kill_writeb_r =Wire(UInt(1.W)) - val lsu_exc_valid_r_d1 =Wire(UInt(1.W)) - val lsu_i0_exc_r_raw =Wire(UInt(1.W)) - val mdseac_locked_f =Wire(UInt(1.W)) - val i_cpu_run_req_d1 =Wire(UInt(1.W)) - val cpu_run_ack =Wire(UInt(1.W)) - val cpu_halt_status =Wire(UInt(1.W)) - val cpu_halt_ack =Wire(UInt(1.W)) - val pmu_fw_tlu_halted =Wire(UInt(1.W)) - val internal_pmu_fw_halt_mode =Wire(UInt(1.W)) - val pmu_fw_halt_req_ns =Wire(UInt(1.W)) - val pmu_fw_halt_req_f =Wire(UInt(1.W)) - val pmu_fw_tlu_halted_f =Wire(UInt(1.W)) - val int_timer0_int_hold_f =Wire(UInt(1.W)) - val int_timer1_int_hold_f =Wire(UInt(1.W)) - val trigger_hit_dmode_r =Wire(UInt(1.W)) - val i0_trigger_hit_r =Wire(UInt(1.W)) - val pause_expired_r =Wire(UInt(1.W)) - val dec_tlu_pmu_fw_halted =Wire(UInt(1.W)) - val dec_tlu_flush_noredir_r_d1 =Wire(UInt(1.W)) - val halt_taken_f =Wire(UInt(1.W)) - val lsu_idle_any_f =Wire(UInt(1.W)) - val ifu_miss_state_idle_f =Wire(UInt(1.W)) - val dbg_tlu_halted_f =Wire(UInt(1.W)) - val debug_halt_req_f =Wire(UInt(1.W)) - val debug_resume_req_f =Wire(UInt(1.W)) - val trigger_hit_dmode_r_d1 =Wire(UInt(1.W)) - val dcsr_single_step_done_f =Wire(UInt(1.W)) - val debug_halt_req_d1 =Wire(UInt(1.W)) - val request_debug_mode_r_d1 =Wire(UInt(1.W)) - val request_debug_mode_done_f =Wire(UInt(1.W)) - val dcsr_single_step_running_f =Wire(UInt(1.W)) - val dec_tlu_flush_pause_r_d1 =Wire(UInt(1.W)) - val dbg_halt_req_held =Wire(UInt(1.W)) - val debug_halt_req_ns =Wire(UInt(1.W)) - val internal_dbg_halt_mode =Wire(UInt(1.W)) - val core_empty =Wire(UInt(1.W)) - val dbg_halt_req_final =Wire(UInt(1.W)) - val debug_brkpt_status_ns =Wire(UInt(1.W)) - val mpc_debug_halt_ack_ns =Wire(UInt(1.W)) - val mpc_debug_run_ack_ns =Wire(UInt(1.W)) - val mpc_halt_state_ns =Wire(UInt(1.W)) - val mpc_run_state_ns =Wire(UInt(1.W)) - val dbg_halt_state_ns =Wire(UInt(1.W)) - val dbg_run_state_ns =Wire(UInt(1.W)) - val dbg_halt_state_f =Wire(UInt(1.W)) - val mpc_halt_state_f =Wire(UInt(1.W)) - val nmi_int_detected =Wire(UInt(1.W)) - val nmi_lsu_load_type =Wire(UInt(1.W)) - val nmi_lsu_store_type =Wire(UInt(1.W)) - val reset_delayed =Wire(UInt(1.W)) - val internal_dbg_halt_mode_f =Wire(UInt(1.W)) - val e5_valid =Wire(UInt(1.W)) - val ic_perr_r_d1 =Wire(UInt(1.W)) - val iccm_sbecc_r_d1 =Wire(UInt(1.W)) + val pause_expired_wb =WireInit(UInt(1.W), 0.U) + val take_nmi_r_d1 =WireInit(UInt(1.W),0.U) + val exc_or_int_valid_r_d1 =WireInit(UInt(1.W),0.U) + val interrupt_valid_r_d1 =WireInit(UInt(1.W),0.U) + val tlu_flush_lower_r =WireInit(UInt(1.W),0.U) + val synchronous_flush_r =WireInit(UInt(1.W),0.U) + val interrupt_valid_r =WireInit(UInt(1.W),0.U) + val take_nmi =WireInit(UInt(1.W),0.U) + val take_reset =WireInit(UInt(1.W),0.U) + val take_int_timer1_int =WireInit(UInt(1.W),0.U) + val take_int_timer0_int =WireInit(UInt(1.W),0.U) + val take_timer_int =WireInit(UInt(1.W),0.U) + val take_soft_int =WireInit(UInt(1.W),0.U) + val take_ce_int =WireInit(UInt(1.W),0.U) + val take_ext_int_start =WireInit(UInt(1.W),0.U) + val ext_int_freeze =WireInit(UInt(1.W),0.U) + val ext_int_freeze_d1 =WireInit(UInt(1.W),0.U) + val take_ext_int_start_d1 =WireInit(UInt(1.W),0.U) + val take_ext_int_start_d2 =WireInit(UInt(1.W),0.U) + val take_ext_int_start_d3 =WireInit(UInt(1.W),0.U) + val fast_int_meicpct =WireInit(UInt(1.W),0.U) + val ignore_ext_int_due_to_lsu_stall =WireInit(UInt(1.W),0.U) + val take_ext_int =WireInit(UInt(1.W),0.U) + val internal_dbg_halt_timers =WireInit(UInt(1.W),0.U) + val int_timer1_int_hold =WireInit(UInt(1.W),0.U) + val int_timer0_int_hold =WireInit(UInt(1.W),0.U) + val mhwakeup_ready =WireInit(UInt(1.W),0.U) + val ext_int_ready =WireInit(UInt(1.W),0.U) + val ce_int_ready =WireInit(UInt(1.W),0.U) + val soft_int_ready =WireInit(UInt(1.W),0.U) + val timer_int_ready =WireInit(UInt(1.W),0.U) + val ebreak_to_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) + val ebreak_to_debug_mode_r =WireInit(UInt(1.W),0.U) + val inst_acc_r =WireInit(UInt(1.W),0.U) + val inst_acc_r_raw =WireInit(UInt(1.W),0.U) + val iccm_sbecc_r =WireInit(UInt(1.W),0.U) + val ic_perr_r =WireInit(UInt(1.W),0.U) + val fence_i_r =WireInit(UInt(1.W),0.U) + val ebreak_r =WireInit(UInt(1.W),0.U) + val ecall_r =WireInit(UInt(1.W),0.U) + val illegal_r =WireInit(UInt(1.W),0.U) + val mret_r =WireInit(UInt(1.W),0.U) + val iccm_repair_state_ns =WireInit(UInt(1.W),0.U) + val rfpc_i0_r =WireInit(UInt(1.W),0.U) + val tlu_i0_kill_writeb_r =WireInit(UInt(1.W),0.U) + val lsu_exc_valid_r_d1 =WireInit(UInt(1.W),0.U) + val lsu_i0_exc_r_raw =WireInit(UInt(1.W),0.U) + val mdseac_locked_f =WireInit(UInt(1.W),0.U) + val i_cpu_run_req_d1 =WireInit(UInt(1.W),0.U) + val cpu_run_ack =WireInit(UInt(1.W),0.U) + val cpu_halt_status =WireInit(UInt(1.W),0.U) + val cpu_halt_ack =WireInit(UInt(1.W),0.U) + val pmu_fw_tlu_halted =WireInit(UInt(1.W),0.U) + val internal_pmu_fw_halt_mode =WireInit(UInt(1.W),0.U) + val pmu_fw_halt_req_ns =WireInit(UInt(1.W),0.U) + val pmu_fw_halt_req_f =WireInit(UInt(1.W),0.U) + val pmu_fw_tlu_halted_f =WireInit(UInt(1.W),0.U) + val int_timer0_int_hold_f =WireInit(UInt(1.W),0.U) + val int_timer1_int_hold_f =WireInit(UInt(1.W),0.U) + val trigger_hit_dmode_r =WireInit(UInt(1.W),0.U) + val i0_trigger_hit_r =WireInit(UInt(1.W),0.U) + val pause_expired_r =WireInit(UInt(1.W),0.U) + val dec_tlu_pmu_fw_halted =WireInit(UInt(1.W),0.U) + val dec_tlu_flush_noredir_r_d1 =WireInit(UInt(1.W),0.U) + val halt_taken_f =WireInit(UInt(1.W),0.U) + val lsu_idle_any_f =WireInit(UInt(1.W),0.U) + val ifu_miss_state_idle_f =WireInit(UInt(1.W),0.U) + val dbg_tlu_halted_f =WireInit(UInt(1.W),0.U) + val debug_halt_req_f =WireInit(UInt(1.W),0.U) + val debug_resume_req_f =WireInit(UInt(1.W),0.U) + val trigger_hit_dmode_r_d1 =WireInit(UInt(1.W),0.U) + val dcsr_single_step_done_f =WireInit(UInt(1.W),0.U) + val debug_halt_req_d1 =WireInit(UInt(1.W),0.U) + val request_debug_mode_r_d1 =WireInit(UInt(1.W),0.U) + val request_debug_mode_done_f =WireInit(UInt(1.W),0.U) + val dcsr_single_step_running_f =WireInit(UInt(1.W),0.U) + val dec_tlu_flush_pause_r_d1 =WireInit(UInt(1.W),0.U) + val dbg_halt_req_held =WireInit(UInt(1.W),0.U) + val debug_halt_req_ns =WireInit(UInt(1.W),0.U) + val internal_dbg_halt_mode =WireInit(UInt(1.W),0.U) + val core_empty =WireInit(UInt(1.W),0.U) + val dbg_halt_req_final =WireInit(UInt(1.W),0.U) + val debug_brkpt_status_ns =WireInit(UInt(1.W),0.U) + val mpc_debug_halt_ack_ns =WireInit(UInt(1.W),0.U) + val mpc_debug_run_ack_ns =WireInit(UInt(1.W),0.U) + val mpc_halt_state_ns =WireInit(UInt(1.W),0.U) + val mpc_run_state_ns =WireInit(UInt(1.W),0.U) + val dbg_halt_state_ns =WireInit(UInt(1.W),0.U) + val dbg_run_state_ns =WireInit(UInt(1.W),0.U) + val dbg_halt_state_f =WireInit(UInt(1.W),0.U) + val mpc_halt_state_f =WireInit(UInt(1.W),0.U) + val nmi_int_detected =WireInit(UInt(1.W),0.U) + val nmi_lsu_load_type =WireInit(UInt(1.W),0.U) + val nmi_lsu_store_type =WireInit(UInt(1.W),0.U) + val reset_delayed =WireInit(UInt(1.W),0.U) + val internal_dbg_halt_mode_f =WireInit(UInt(1.W),0.U) + val e5_valid =WireInit(UInt(1.W),0.U) + val ic_perr_r_d1 =WireInit(UInt(1.W),0.U) + val iccm_sbecc_r_d1 =WireInit(UInt(1.W),0.U) - val npc_r = Wire(UInt(31.W)) - val npc_r_d1 = Wire(UInt(31.W)) - val mie_ns = Wire(UInt(6.W)) - val mepc = Wire(UInt(31.W)) - val mdseac_locked_ns = Wire(UInt(1.W)) - val force_halt = Wire(UInt(1.W)) - val dpc = Wire(UInt(31.W)) - val mstatus_mie_ns = Wire(UInt(1.W)) - val dec_csr_wen_r_mod = Wire(UInt(1.W)) - val fw_halt_req = Wire(UInt(1.W)) - val mstatus = Wire(UInt(2.W)) - val dcsr = Wire(UInt(16.W)) - val mtvec = Wire(UInt(31.W)) - val mip = Wire(UInt(6.W)) + val npc_r = WireInit(UInt(31.W),0.U) + val npc_r_d1 = WireInit(UInt(31.W),0.U) + val mie_ns = WireInit(UInt(6.W),0.U) + val mepc = WireInit(UInt(31.W),0.U) + val mdseac_locked_ns = WireInit(UInt(1.W),0.U) + val force_halt = WireInit(UInt(1.W),0.U) + val dpc = WireInit(UInt(31.W),0.U) + val mstatus_mie_ns = WireInit(UInt(1.W),0.U) + val dec_csr_wen_r_mod = WireInit(UInt(1.W),0.U) + val fw_halt_req = WireInit(UInt(1.W),0.U) + val mstatus = WireInit(UInt(2.W),0.U) + val dcsr = WireInit(UInt(16.W),0.U) + val mtvec = WireInit(UInt(31.W),0.U) + val mip = WireInit(UInt(6.W),0.U) val csr_pkt = Wire(new el2_dec_tlu_csr_pkt) - val dec_tlu_mpc_halted_only_ns = Wire(UInt(1.W)) + val dec_tlu_mpc_halted_only_ns = WireInit(UInt(1.W),0.U) // tell dbg we are only MPC halted dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f val int_timers=Module(new el2_dec_timer_ctl) @@ -692,7 +692,7 @@ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CS val lsu_exc_valid_r = lsu_i0_exc_r lsu_exc_valid_r_d1 :=withClock(lsu_r_wb_clk){RegNext(lsu_exc_valid_r,0.U)} val lsu_i0_exc_r_d1 =withClock(lsu_r_wb_clk){RegNext(lsu_i0_exc_r,0.U)} - val lsu_exc_ma_r = lsu_i0_exc_r & !io.lsu_error_pkt_r.bits.exc_type + val lsu_exc_ma_r = lsu_i0_exc_r & ~io.lsu_error_pkt_r.bits.exc_type val lsu_exc_acc_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.exc_type val lsu_exc_st_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.inst_type @@ -727,12 +727,12 @@ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CS val dec_tlu_br0_v_r = io.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.exu_i0_br_mp_r | ~io.exu_pmu_i0_br_ataken) - io.dec_tlu_br0_r_pkt.bits.hist := io.exu_i0_br_hist_r - io.dec_tlu_br0_r_pkt.bits.br_error := dec_tlu_br0_error_r - io.dec_tlu_br0_r_pkt.bits.br_start_error := dec_tlu_br0_start_error_r + io.dec_tlu_br0_r_pkt.hist := io.exu_i0_br_hist_r + io.dec_tlu_br0_r_pkt.br_error := dec_tlu_br0_error_r + io.dec_tlu_br0_r_pkt.br_start_error := dec_tlu_br0_start_error_r io.dec_tlu_br0_r_pkt.valid := dec_tlu_br0_v_r - io.dec_tlu_br0_r_pkt.bits.way := io.exu_i0_br_way_r - io.dec_tlu_br0_r_pkt.bits.middle := io.exu_i0_br_middle_r + io.dec_tlu_br0_r_pkt.way := io.exu_i0_br_way_r + io.dec_tlu_br0_r_pkt.middle := io.exu_i0_br_middle_r ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r @@ -1447,16 +1447,16 @@ class el2_CSR_IO extends Bundle with el2_lib { val mtdata1_t = Output(Vec(4,UInt(10.W))) } -class csr_tlu extends Module with el2_lib with CSRs { +class csr_tlu extends Module with el2_lib with CSRs with RequireAsyncReset { val io = IO(new el2_CSR_IO) ////////////////////////////////wires/////////////////////////////// - val miccme_ce_req = Wire(UInt(1.W)) - val mice_ce_req = Wire(UInt(1.W)) - val mdccme_ce_req = Wire(UInt(1.W)) - val pc_r_d1 = Wire(UInt(31.W)) - val mpmc_b_ns = Wire(UInt(1.W)) - val mpmc_b = Wire(UInt(1.W)) + val miccme_ce_req = WireInit(UInt(1.W),0.U) + val mice_ce_req = WireInit(UInt(1.W),0.U) + val mdccme_ce_req = WireInit(UInt(1.W),0.U) + val pc_r_d1 = WireInit(UInt(31.W),0.U) + val mpmc_b_ns = WireInit(UInt(1.W),0.U) + val mpmc_b = WireInit(UInt(1.W),0.U) val wr_mcycleh_r = WireInit(UInt(1.W), 0.U) val mcycleh = WireInit(UInt(32.W),0.U) val minstretl_inc = WireInit(UInt(33.W),0.U) @@ -2306,7 +2306,7 @@ class csr_tlu extends Module with el2_lib with CSRs { val mtdata1_tsel_out = Mux1H((0 until 4).map(i => (mtsel === i.U(2.W)) -> Cat(2.U(4.W), io.mtdata1_t(i)(9), "b011111".U(6.W), io.mtdata1_t(i)(8,7), 0.U(6.W), io.mtdata1_t(i)(6,5), 0.U(3.W), io.mtdata1_t(i)(4,3), 0.U(3.W), io.mtdata1_t(i)(2,0)))) for(i <- 0 until 4 ){ io.trigger_pkt_any(i).select := io.mtdata1_t(i)(MTDATA1_SEL) - io.trigger_pkt_any(i).match_ := io.mtdata1_t(i)(MTDATA1_MATCH) + io.trigger_pkt_any(i).match_pkt := io.mtdata1_t(i)(MTDATA1_MATCH) io.trigger_pkt_any(i).store := io.mtdata1_t(i)(MTDATA1_ST) io.trigger_pkt_any(i).load := io.mtdata1_t(i)(MTDATA1_LD) io.trigger_pkt_any(i).execute := io.mtdata1_t(i)(MTDATA1_EXE) @@ -2637,12 +2637,12 @@ class csr_tlu extends Module with el2_lib with CSRs { } -class el2_dec_decode_csr_read_IO extends Bundle with el2_lib { +class el2_dec_decode_csr_read_IO extends Bundle{ val dec_csr_rdaddr_d=Input(UInt(12.W)) val csr_pkt=Output(new el2_dec_tlu_csr_pkt) } -class el2_dec_decode_csr_read extends Module with el2_lib { +class el2_dec_decode_csr_read extends Module with RequireAsyncReset{ val io=IO(new el2_dec_decode_csr_read_IO) def pattern(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0 & y(i)!='z') io.dec_csr_rdaddr_d(y(i)) else if(y(i)<0) !io.dec_csr_rdaddr_d(y(i).abs) else !io.dec_csr_rdaddr_d(0)).reduce(_&_) @@ -2736,18 +2736,18 @@ class el2_dec_decode_csr_read extends Module with el2_lib { } -class el2_dec_timer_ctl extends Module with el2_lib { +class el2_dec_timer_ctl extends Module with el2_lib with RequireAsyncReset{ val io=IO(new el2_dec_timer_ctl_IO) val MITCTL_ENABLE=0 val MITCTL_ENABLE_HALTED=1 val MITCTL_ENABLE_PAUSED=2 - val mitctl1=Wire(UInt(4.W)) - val mitctl0=Wire(UInt(3.W)) - val mitb1 =Wire(UInt(32.W)) - val mitb0 =Wire(UInt(32.W)) - val mitcnt1=Wire(UInt(32.W)) - val mitcnt0=Wire(UInt(32.W)) + val mitctl1=WireInit(UInt(4.W),0.U) + val mitctl0=WireInit(UInt(3.W),0.U) + val mitb1 =WireInit(UInt(32.W),0.U) + val mitb0 =WireInit(UInt(32.W),0.U) + val mitcnt1=WireInit(UInt(32.W),0.U) + val mitcnt0=WireInit(UInt(32.W),0.U) val mit0_match_ns=(mitcnt0 >= mitb0).asUInt val mit1_match_ns=(mitcnt1 >= mitb1).asUInt @@ -2765,7 +2765,7 @@ class el2_dec_timer_ctl extends Module with el2_lib { val mitcnt0_inc_ok = mitctl0(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl0(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl0(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers val mitcnt0_inc = mitcnt0 + 1.U(32.W) val mitcnt0_ns =Mux(mit0_match_ns.asBool, 0.U, Mux(wr_mitcnt0_r.asBool, io.dec_csr_wrdata_r, mitcnt0_inc)) - mitcnt0 := rvdffe(mitcnt0_ns,(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns).asBool,clock,io.scan_mode) + mitcnt0 :=rvdffe(mitcnt0_ns,(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns).asBool,clock,io.scan_mode) // ---------------------------------------------------------------------- // MITCNT1 (RW) @@ -2796,7 +2796,7 @@ class el2_dec_timer_ctl extends Module with el2_lib { val MITB1 =0x7d6.U(12.W) val wr_mitb1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r=== MITB1) - val mitb1_b = rvdffe(~io.dec_csr_wrdata_r,wr_mitb1_r.asBool,clock,io.scan_mode) + val mitb1_b=rvdffe((~io.dec_csr_wrdata_r),wr_mitb1_r.asBool,clock,io.scan_mode) mitb1 := ~mitb1_b // ---------------------------------------------------------------------- @@ -2868,5 +2868,5 @@ class el2_dec_timer_ctl_IO extends Bundle{ } object tlu_gen extends App{ - println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_tlu_ctl()))) + println(chisel3.Driver.emitVerilog(new el2_dec_tlu_ctl)) } diff --git a/src/main/scala/dec/el2_dec_trigger.scala b/src/main/scala/dec/el2_dec_trigger.scala index 171579e8..72cb224f 100644 --- a/src/main/scala/dec/el2_dec_trigger.scala +++ b/src/main/scala/dec/el2_dec_trigger.scala @@ -12,9 +12,9 @@ class el2_dec_trigger extends Module with el2_lib { val dec_i0_trigger_match_d = Output(UInt(4.W)) }) val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0))) - io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_.asBool())).reverse.reduce(Cat(_,_)) + io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_pkt.asBool())).reverse.reduce(Cat(_,_)) } object dec_trig extends App { - println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_trigger()))) + chisel3.Driver execute(args, () => new el2_dec_trigger()) } diff --git a/src/main/scala/el2_swerv.scala b/src/main/scala/el2_swerv.scala index 40df1be9..45f381da 100644 --- a/src/main/scala/el2_swerv.scala +++ b/src/main/scala/el2_swerv.scala @@ -384,7 +384,7 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib { ifu.io.exu_mp_fghr := exu.io.exu_mp_fghr ifu.io.exu_mp_index := exu.io.exu_mp_index ifu.io.exu_mp_btag := exu.io.exu_mp_btag - ifu.io.dec_tlu_br0_r_pkt <> dec.io.dec_tlu_br0_r_pkt + ifu.io.dec_tlu_br0_r_pkt := dec.io.dec_tlu_br0_r_pkt ifu.io.exu_i0_br_fghr_r := exu.io.exu_i0_br_fghr_r ifu.io.exu_i0_br_index_r := exu.io.exu_i0_br_index_r ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_tlu_flush_lower_r diff --git a/src/main/scala/ifu/el2_ifu.scala b/src/main/scala/ifu/el2_ifu.scala index 583fabef..50b79db4 100644 --- a/src/main/scala/ifu/el2_ifu.scala +++ b/src/main/scala/ifu/el2_ifu.scala @@ -122,7 +122,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset { val ifu_i0_pc4 = Output(Bool()) val ifu_miss_state_idle = Output(Bool()) // Aligner branch data - val i0_brp = Valid(new el2_br_pkt_t) + val i0_brp = Output(new el2_br_pkt_t) val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W)) val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) @@ -132,7 +132,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset { val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W)) val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W)) - val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t)) + val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t) val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) val dec_tlu_flush_lower_wb = Input(Bool()) @@ -195,7 +195,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset { bp_ctl_ch.io.ic_hit_f := mem_ctl_ch.io.ic_hit_f bp_ctl_ch.io.ifc_fetch_addr_f := ifc_ctl_ch.io.ifc_fetch_addr_f bp_ctl_ch.io.ifc_fetch_req_f := ifc_ctl_ch.io.ifc_fetch_req_f - bp_ctl_ch.io.dec_tlu_br0_r_pkt <> io.dec_tlu_br0_r_pkt + bp_ctl_ch.io.dec_tlu_br0_r_pkt := io.dec_tlu_br0_r_pkt bp_ctl_ch.io.exu_i0_br_fghr_r := io.exu_i0_br_fghr_r bp_ctl_ch.io.exu_i0_br_index_r := io.exu_i0_br_index_r bp_ctl_ch.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala index ac2ea554..c3b64aeb 100644 --- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala @@ -42,7 +42,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset { val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) val ifu_pmu_instr_aligned = Output(Bool()) val ifu_i0_cinst = Output(UInt(16.W)) - val i0_brp = Valid(new el2_br_pkt_t) + val i0_brp = Output(new el2_br_pkt_t) }) io.ifu_i0_valid := 0.U io.ifu_i0_icaf := 0.U @@ -377,25 +377,25 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset { io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0)) - io.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1)) + io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1)) val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1)) - io.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1)) + io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1)) - io.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)), + io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)), (first2B & alignhist0(0)) | (first4B & alignhist0(1))) val i0_ends_f1 = first4B & alignfromf1 - io.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset) + io.i0_brp.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset) - io.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett) + io.i0_brp.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett) - io.i0_brp.bits.br_start_error := (first4B & alignval(1) & alignbrend(0)) + io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0)) - io.i0_brp.bits.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0)) + io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0)) - io.i0_brp.bits.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B) + io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B) io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash) diff --git a/src/main/scala/ifu/el2_ifu_bp_ctl.scala b/src/main/scala/ifu/el2_ifu_bp_ctl.scala index a8ed6f98..53a0e3fc 100644 --- a/src/main/scala/ifu/el2_ifu_bp_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_bp_ctl.scala @@ -13,7 +13,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset { val ifc_fetch_addr_f = Input(UInt(31.W)) val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC // Decode packet containing information if its a brnach or not - val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t)) + val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t) val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit val dec_tlu_flush_lower_wb = Input(Bool()) @@ -83,12 +83,12 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset { // Its a commit or update packet val dec_tlu_br0_v_wb = io.dec_tlu_br0_r_pkt.valid - val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.bits.hist + val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.hist val dec_tlu_br0_addr_wb = io.exu_i0_br_index_r - val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.bits.br_error - val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.bits.middle - val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.bits.way - val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.bits.br_start_error + val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.br_error + val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.middle + val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.way + val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.br_start_error val exu_i0_br_fghr_wb = io.exu_i0_br_fghr_r dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb @@ -281,7 +281,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset { val bht_bank1_rd_data_f =WireInit(UInt(2.W), 0.U) val bht_bank0_rd_data_f =WireInit(UInt(2.W), 0.U) val bht_bank0_rd_data_p1_f =WireInit(UInt(2.W), 0.U) - + // Depending on pc make the virtual bank as commented above val bht_vbank0_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->bht_bank0_rd_data_f, io.ifc_fetch_addr_f(0).asBool->bht_bank1_rd_data_f)) diff --git a/src/main/scala/include/el2_bundle.scala b/src/main/scala/include/el2_bundle.scala index 11ebd30f..be9c652c 100644 --- a/src/main/scala/include/el2_bundle.scala +++ b/src/main/scala/include/el2_bundle.scala @@ -36,6 +36,7 @@ object el2_inst_pkt_t extends Enumeration{ } class el2_load_cam_pkt_t extends Bundle { + val valid = UInt(1.W) val wb = UInt(1.W) val tag = UInt(3.W) val rd = UInt(5.W) @@ -48,6 +49,7 @@ class el2_rets_pkt_t extends Bundle { } class el2_br_pkt_t extends Bundle { + val valid = UInt(1.W) val toffset = UInt(12.W) val hist = UInt(2.W) val br_error = UInt(1.W) @@ -60,6 +62,7 @@ class el2_br_pkt_t extends Bundle { class el2_br_tlu_pkt_t extends Bundle { + val valid = UInt(1.W) val hist = UInt(2.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) @@ -74,6 +77,7 @@ class el2_predict_pkt_t extends Bundle { val pc4 = UInt(1.W) val hist = UInt(2.W) val toffset = UInt(12.W) + // val valid = UInt(1.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) val prett = UInt(31.W) @@ -157,14 +161,16 @@ class el2_lsu_pkt_t extends Bundle { val store_data_bypass_d = Bool() val load_ldst_bypass_d = Bool() val store_data_bypass_m = Bool() +// val valid = Bool() } class el2_lsu_error_pkt_t extends Bundle { + // val exc_valid = UInt(1.W) val single_ecc_error = UInt(1.W) val inst_type = UInt(1.W) //0: Load, 1: Store val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault - val mscause = UInt(1.W) - val addr = UInt(1.W) + val mscause = UInt(4.W) + val addr = UInt(32.W) } class el2_dec_pkt_t extends Bundle { @@ -221,6 +227,7 @@ class el2_dec_pkt_t extends Bundle { } class el2_mul_pkt_t extends Bundle { + // val valid = UInt(1.W) val rs1_sign = UInt(1.W) val rs2_sign = UInt(1.W) val low = UInt(1.W) @@ -242,6 +249,7 @@ class el2_mul_pkt_t extends Bundle { } class el2_div_pkt_t extends Bundle { + // val valid = UInt(1.W) val unsign = UInt(1.W) val rem = UInt(1.W) } @@ -250,6 +258,7 @@ class el2_ccm_ext_in_pkt_t extends Bundle { val TEST1 = UInt(1.W) val RME = UInt(1.W) val RM = UInt(4.W) + val LS = UInt(1.W) val DS = UInt(1.W) val SD = UInt(1.W) @@ -297,7 +306,7 @@ class el2_ic_tag_ext_in_pkt_t extends Bundle { class el2_trigger_pkt_t extends Bundle { val select = UInt(1.W) - val match_ = UInt(1.W) + val match_pkt = UInt(1.W) val store = UInt(1.W) val load = UInt(1.W) val execute = UInt(1.W) diff --git a/src/main/scala/lsu/el2_lsu_trigger.scala b/src/main/scala/lsu/el2_lsu_trigger.scala index 91bc413b..7d9a6402 100644 --- a/src/main/scala/lsu/el2_lsu_trigger.scala +++ b/src/main/scala/lsu/el2_lsu_trigger.scala @@ -17,7 +17,7 @@ class el2_lsu_trigger extends Module with RequireAsyncReset with el2_lib { val lsu_match_data = (0 until 4).map(i=>Mux1H(Seq(!io.trigger_pkt_any(i).select.asBool->io.lsu_addr_m, (io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).store).asBool->store_data_trigger_m))) io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)| (io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )& - rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_.asBool())).reverse.reduce(Cat(_,_)) + rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_pkt.asBool())).reverse.reduce(Cat(_,_)) } diff --git a/target/scala-2.12/classes/dec/csr_tlu.class b/target/scala-2.12/classes/dec/csr_tlu.class index 748d1b9b..807e9fde 100644 Binary files a/target/scala-2.12/classes/dec/csr_tlu.class and b/target/scala-2.12/classes/dec/csr_tlu.class differ diff --git a/target/scala-2.12/classes/dec/dec_dec_ctl$.class b/target/scala-2.12/classes/dec/dec_dec_ctl$.class new file mode 100644 index 00000000..fe14d8f4 Binary files /dev/null and b/target/scala-2.12/classes/dec/dec_dec_ctl$.class differ diff --git a/target/scala-2.12/classes/dec/dec_dec_ctl$delayedInit$body.class b/target/scala-2.12/classes/dec/dec_dec_ctl$delayedInit$body.class new file mode 100644 index 00000000..e1a142d3 Binary files /dev/null and b/target/scala-2.12/classes/dec/dec_dec_ctl$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/dec/decode_ctrl.class b/target/scala-2.12/classes/dec/dec_dec_ctl.class similarity index 56% rename from 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