diff --git a/el2_ifu_aln_ctl.fir b/el2_ifu_aln_ctl.fir
index 7522a1aa..a3adff11 100644
--- a/el2_ifu_aln_ctl.fir
+++ b/el2_ifu_aln_ctl.fir
@@ -1998,6 +1998,21 @@ circuit el2_ifu_aln_ctl :
     input reset : UInt<1>
     output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}
     
+    io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19]
+    io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18]
+    io.ifu_i0_icaf_type <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 49:23]
+    io.ifu_i0_icaf_f1 <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 50:21]
+    io.ifu_i0_dbecc <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 51:19]
+    io.ifu_i0_instr <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 52:19]
+    io.ifu_i0_pc <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 53:16]
+    io.ifu_i0_pc4 <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 54:17]
+    io.ifu_fb_consume1 <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 55:22]
+    io.ifu_fb_consume2 <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 56:22]
+    io.ifu_i0_bp_index <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 57:22]
+    io.ifu_i0_bp_fghr <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 58:21]
+    io.ifu_i0_bp_btag <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 59:21]
+    io.ifu_pmu_instr_aligned <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 60:28]
+    io.ifu_i0_cinst <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 61:19]
     wire error_stall_in : UInt<1>
     error_stall_in <= UInt<1>("h00")
     wire alignval : UInt<2>
@@ -2096,157 +2111,157 @@ circuit el2_ifu_aln_ctl :
     shift_2B <= UInt<1>("h00")
     wire f0_shift_2B : UInt<1>
     f0_shift_2B <= UInt<1>("h00")
-    node _T = or(error_stall, io.ifu_async_error_start) @[el2_ifu_aln_ctl.scala 110:34]
-    node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 110:64]
-    node _T_2 = and(_T, _T_1) @[el2_ifu_aln_ctl.scala 110:62]
-    error_stall_in <= _T_2 @[el2_ifu_aln_ctl.scala 110:18]
-    reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 112:51]
-    _T_3 <= error_stall_in @[el2_ifu_aln_ctl.scala 112:51]
-    error_stall <= _T_3 @[el2_ifu_aln_ctl.scala 112:15]
-    reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 113:48]
-    wrptr <= wrptr_in @[el2_ifu_aln_ctl.scala 113:48]
-    reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 114:48]
-    rdptr <= rdptr_in @[el2_ifu_aln_ctl.scala 114:48]
-    reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 116:48]
-    f2val <= f2val_in @[el2_ifu_aln_ctl.scala 116:48]
-    reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 117:48]
-    f1val <= f1val_in @[el2_ifu_aln_ctl.scala 117:48]
-    reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 118:48]
-    f0val <= f0val_in @[el2_ifu_aln_ctl.scala 118:48]
-    reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 120:48]
-    q2off <= q2off_in @[el2_ifu_aln_ctl.scala 120:48]
-    reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 121:48]
-    q1off <= q1off_in @[el2_ifu_aln_ctl.scala 121:48]
-    reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 122:48]
-    q0off <= q0off_in @[el2_ifu_aln_ctl.scala 122:48]
-    node _T_4 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 124:55]
+    node _T = or(error_stall, io.ifu_async_error_start) @[el2_ifu_aln_ctl.scala 126:34]
+    node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 126:64]
+    node _T_2 = and(_T, _T_1) @[el2_ifu_aln_ctl.scala 126:62]
+    error_stall_in <= _T_2 @[el2_ifu_aln_ctl.scala 126:18]
+    reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 128:51]
+    _T_3 <= error_stall_in @[el2_ifu_aln_ctl.scala 128:51]
+    error_stall <= _T_3 @[el2_ifu_aln_ctl.scala 128:15]
+    reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 129:48]
+    wrptr <= wrptr_in @[el2_ifu_aln_ctl.scala 129:48]
+    reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 130:48]
+    rdptr <= rdptr_in @[el2_ifu_aln_ctl.scala 130:48]
+    reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 132:48]
+    f2val <= f2val_in @[el2_ifu_aln_ctl.scala 132:48]
+    reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 133:48]
+    f1val <= f1val_in @[el2_ifu_aln_ctl.scala 133:48]
+    reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 134:48]
+    f0val <= f0val_in @[el2_ifu_aln_ctl.scala 134:48]
+    reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 136:48]
+    q2off <= q2off_in @[el2_ifu_aln_ctl.scala 136:48]
+    reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 137:48]
+    q1off <= q1off_in @[el2_ifu_aln_ctl.scala 137:48]
+    reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 138:48]
+    q0off <= q0off_in @[el2_ifu_aln_ctl.scala 138:48]
+    node _T_4 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 140:55]
     reg f2pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4 : @[Reg.scala 28:19]
       f2pc <= io.ifu_fetch_pc @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_5 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 125:53]
+    node _T_5 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 141:53]
     reg f1pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_5 : @[Reg.scala 28:19]
       f1pc <= f1pc_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_6 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 126:53]
+    node _T_6 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 142:53]
     reg f0pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_6 : @[Reg.scala 28:19]
       f0pc <= f0pc_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_7 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 128:44]
+    node _T_7 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 144:44]
     reg _T_8 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_7 : @[Reg.scala 28:19]
       _T_8 <= brdata_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    brdata2 <= _T_8 @[el2_ifu_aln_ctl.scala 128:11]
-    node _T_9 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 129:44]
+    brdata2 <= _T_8 @[el2_ifu_aln_ctl.scala 144:11]
+    node _T_9 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 145:44]
     reg _T_10 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_9 : @[Reg.scala 28:19]
       _T_10 <= brdata_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    brdata1 <= _T_10 @[el2_ifu_aln_ctl.scala 129:11]
-    node _T_11 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 130:44]
+    brdata1 <= _T_10 @[el2_ifu_aln_ctl.scala 145:11]
+    node _T_11 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 146:44]
     reg _T_12 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_11 : @[Reg.scala 28:19]
       _T_12 <= brdata_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    brdata0 <= _T_12 @[el2_ifu_aln_ctl.scala 130:11]
-    node _T_13 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 132:45]
+    brdata0 <= _T_12 @[el2_ifu_aln_ctl.scala 146:11]
+    node _T_13 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 148:45]
     reg _T_14 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_13 : @[Reg.scala 28:19]
       _T_14 <= misc_data_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    misc2 <= _T_14 @[el2_ifu_aln_ctl.scala 132:9]
-    node _T_15 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 133:45]
+    misc2 <= _T_14 @[el2_ifu_aln_ctl.scala 148:9]
+    node _T_15 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 149:45]
     reg _T_16 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_15 : @[Reg.scala 28:19]
       _T_16 <= misc_data_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    misc1 <= _T_16 @[el2_ifu_aln_ctl.scala 133:9]
-    node _T_17 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 134:45]
+    misc1 <= _T_16 @[el2_ifu_aln_ctl.scala 149:9]
+    node _T_17 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 150:45]
     reg _T_18 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_17 : @[Reg.scala 28:19]
       _T_18 <= misc_data_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    misc0 <= _T_18 @[el2_ifu_aln_ctl.scala 134:9]
-    node _T_19 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 136:49]
+    misc0 <= _T_18 @[el2_ifu_aln_ctl.scala 150:9]
+    node _T_19 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 152:49]
     reg _T_20 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_19 : @[Reg.scala 28:19]
       _T_20 <= io.ifu_fetch_data_f @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    q2 <= _T_20 @[el2_ifu_aln_ctl.scala 136:6]
-    node _T_21 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 137:49]
+    q2 <= _T_20 @[el2_ifu_aln_ctl.scala 152:6]
+    node _T_21 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 153:49]
     reg _T_22 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_21 : @[Reg.scala 28:19]
       _T_22 <= io.ifu_fetch_data_f @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    q1 <= _T_22 @[el2_ifu_aln_ctl.scala 137:6]
-    node _T_23 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 138:49]
+    q1 <= _T_22 @[el2_ifu_aln_ctl.scala 153:6]
+    node _T_23 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 154:49]
     reg _T_24 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_23 : @[Reg.scala 28:19]
       _T_24 <= io.ifu_fetch_data_f @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    q0 <= _T_24 @[el2_ifu_aln_ctl.scala 138:6]
-    f2_wr_en <= fetch_to_f2 @[el2_ifu_aln_ctl.scala 140:18]
-    node _T_25 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 141:33]
-    node _T_26 = or(_T_25, f1_shift_2B) @[el2_ifu_aln_ctl.scala 141:47]
-    f1_shift_wr_en <= _T_26 @[el2_ifu_aln_ctl.scala 141:18]
-    node _T_27 = or(fetch_to_f0, shift_f2_f0) @[el2_ifu_aln_ctl.scala 142:33]
-    node _T_28 = or(_T_27, shift_f1_f0) @[el2_ifu_aln_ctl.scala 142:47]
-    node _T_29 = or(_T_28, shift_2B) @[el2_ifu_aln_ctl.scala 142:61]
-    node _T_30 = or(_T_29, shift_4B) @[el2_ifu_aln_ctl.scala 142:72]
-    f0_shift_wr_en <= _T_30 @[el2_ifu_aln_ctl.scala 142:18]
-    node _T_31 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 144:24]
-    node _T_32 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 144:39]
-    node _T_33 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 144:54]
+    q0 <= _T_24 @[el2_ifu_aln_ctl.scala 154:6]
+    f2_wr_en <= fetch_to_f2 @[el2_ifu_aln_ctl.scala 156:18]
+    node _T_25 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 157:33]
+    node _T_26 = or(_T_25, f1_shift_2B) @[el2_ifu_aln_ctl.scala 157:47]
+    f1_shift_wr_en <= _T_26 @[el2_ifu_aln_ctl.scala 157:18]
+    node _T_27 = or(fetch_to_f0, shift_f2_f0) @[el2_ifu_aln_ctl.scala 158:33]
+    node _T_28 = or(_T_27, shift_f1_f0) @[el2_ifu_aln_ctl.scala 158:47]
+    node _T_29 = or(_T_28, shift_2B) @[el2_ifu_aln_ctl.scala 158:61]
+    node _T_30 = or(_T_29, shift_4B) @[el2_ifu_aln_ctl.scala 158:72]
+    f0_shift_wr_en <= _T_30 @[el2_ifu_aln_ctl.scala 158:18]
+    node _T_31 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 160:24]
+    node _T_32 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 160:39]
+    node _T_33 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:54]
     node _T_34 = cat(_T_31, _T_32) @[Cat.scala 29:58]
     node qren = cat(_T_34, _T_33) @[Cat.scala 29:58]
-    node _T_35 = eq(wrptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 145:21]
-    node _T_36 = and(_T_35, ifvalid) @[el2_ifu_aln_ctl.scala 145:29]
-    node _T_37 = eq(wrptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 145:46]
-    node _T_38 = and(_T_37, ifvalid) @[el2_ifu_aln_ctl.scala 145:54]
-    node _T_39 = eq(wrptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 145:71]
-    node _T_40 = and(_T_39, ifvalid) @[el2_ifu_aln_ctl.scala 145:79]
+    node _T_35 = eq(wrptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 161:21]
+    node _T_36 = and(_T_35, ifvalid) @[el2_ifu_aln_ctl.scala 161:29]
+    node _T_37 = eq(wrptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 161:46]
+    node _T_38 = and(_T_37, ifvalid) @[el2_ifu_aln_ctl.scala 161:54]
+    node _T_39 = eq(wrptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 161:71]
+    node _T_40 = and(_T_39, ifvalid) @[el2_ifu_aln_ctl.scala 161:79]
     node _T_41 = cat(_T_36, _T_38) @[Cat.scala 29:58]
     node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58]
-    qwen <= _T_42 @[el2_ifu_aln_ctl.scala 145:8]
-    node _T_43 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 147:30]
-    node _T_44 = and(_T_43, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 147:34]
-    node _T_45 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 147:57]
-    node _T_46 = and(_T_44, _T_45) @[el2_ifu_aln_ctl.scala 147:55]
-    node _T_47 = bits(_T_46, 0, 0) @[el2_ifu_aln_ctl.scala 147:78]
-    node _T_48 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 148:10]
-    node _T_49 = and(_T_48, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 148:14]
-    node _T_50 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 148:37]
-    node _T_51 = and(_T_49, _T_50) @[el2_ifu_aln_ctl.scala 148:35]
-    node _T_52 = bits(_T_51, 0, 0) @[el2_ifu_aln_ctl.scala 148:58]
-    node _T_53 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 149:10]
-    node _T_54 = and(_T_53, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 149:14]
-    node _T_55 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 149:37]
-    node _T_56 = and(_T_54, _T_55) @[el2_ifu_aln_ctl.scala 149:35]
-    node _T_57 = bits(_T_56, 0, 0) @[el2_ifu_aln_ctl.scala 149:58]
-    node _T_58 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 150:10]
-    node _T_59 = and(_T_58, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 150:14]
-    node _T_60 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 150:37]
-    node _T_61 = and(_T_59, _T_60) @[el2_ifu_aln_ctl.scala 150:35]
-    node _T_62 = bits(_T_61, 0, 0) @[el2_ifu_aln_ctl.scala 150:58]
-    node _T_63 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 151:10]
-    node _T_64 = and(_T_63, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 151:14]
-    node _T_65 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 151:37]
-    node _T_66 = and(_T_64, _T_65) @[el2_ifu_aln_ctl.scala 151:35]
-    node _T_67 = bits(_T_66, 0, 0) @[el2_ifu_aln_ctl.scala 151:58]
-    node _T_68 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 152:10]
-    node _T_69 = and(_T_68, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 152:14]
-    node _T_70 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 152:37]
-    node _T_71 = and(_T_69, _T_70) @[el2_ifu_aln_ctl.scala 152:35]
-    node _T_72 = bits(_T_71, 0, 0) @[el2_ifu_aln_ctl.scala 152:58]
-    node _T_73 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:6]
-    node _T_74 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:28]
-    node _T_75 = and(_T_73, _T_74) @[el2_ifu_aln_ctl.scala 153:26]
-    node _T_76 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:50]
-    node _T_77 = and(_T_75, _T_76) @[el2_ifu_aln_ctl.scala 153:48]
-    node _T_78 = bits(_T_77, 0, 0) @[el2_ifu_aln_ctl.scala 153:71]
+    qwen <= _T_42 @[el2_ifu_aln_ctl.scala 161:8]
+    node _T_43 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 163:30]
+    node _T_44 = and(_T_43, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 163:34]
+    node _T_45 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 163:57]
+    node _T_46 = and(_T_44, _T_45) @[el2_ifu_aln_ctl.scala 163:55]
+    node _T_47 = bits(_T_46, 0, 0) @[el2_ifu_aln_ctl.scala 163:78]
+    node _T_48 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 164:10]
+    node _T_49 = and(_T_48, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 164:14]
+    node _T_50 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:37]
+    node _T_51 = and(_T_49, _T_50) @[el2_ifu_aln_ctl.scala 164:35]
+    node _T_52 = bits(_T_51, 0, 0) @[el2_ifu_aln_ctl.scala 164:58]
+    node _T_53 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 165:10]
+    node _T_54 = and(_T_53, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 165:14]
+    node _T_55 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 165:37]
+    node _T_56 = and(_T_54, _T_55) @[el2_ifu_aln_ctl.scala 165:35]
+    node _T_57 = bits(_T_56, 0, 0) @[el2_ifu_aln_ctl.scala 165:58]
+    node _T_58 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 166:10]
+    node _T_59 = and(_T_58, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 166:14]
+    node _T_60 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 166:37]
+    node _T_61 = and(_T_59, _T_60) @[el2_ifu_aln_ctl.scala 166:35]
+    node _T_62 = bits(_T_61, 0, 0) @[el2_ifu_aln_ctl.scala 166:58]
+    node _T_63 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 167:10]
+    node _T_64 = and(_T_63, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 167:14]
+    node _T_65 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 167:37]
+    node _T_66 = and(_T_64, _T_65) @[el2_ifu_aln_ctl.scala 167:35]
+    node _T_67 = bits(_T_66, 0, 0) @[el2_ifu_aln_ctl.scala 167:58]
+    node _T_68 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 168:10]
+    node _T_69 = and(_T_68, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 168:14]
+    node _T_70 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:37]
+    node _T_71 = and(_T_69, _T_70) @[el2_ifu_aln_ctl.scala 168:35]
+    node _T_72 = bits(_T_71, 0, 0) @[el2_ifu_aln_ctl.scala 168:58]
+    node _T_73 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 169:6]
+    node _T_74 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 169:28]
+    node _T_75 = and(_T_73, _T_74) @[el2_ifu_aln_ctl.scala 169:26]
+    node _T_76 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 169:50]
+    node _T_77 = and(_T_75, _T_76) @[el2_ifu_aln_ctl.scala 169:48]
+    node _T_78 = bits(_T_77, 0, 0) @[el2_ifu_aln_ctl.scala 169:71]
     node _T_79 = mux(_T_47, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_80 = mux(_T_52, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_81 = mux(_T_57, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2262,23 +2277,23 @@ circuit el2_ifu_aln_ctl :
     node _T_91 = or(_T_90, _T_85) @[Mux.scala 27:72]
     wire _T_92 : UInt @[Mux.scala 27:72]
     _T_92 <= _T_91 @[Mux.scala 27:72]
-    rdptr_in <= _T_92 @[el2_ifu_aln_ctl.scala 147:12]
-    node _T_93 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 155:30]
-    node _T_94 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:36]
-    node _T_95 = and(_T_93, _T_94) @[el2_ifu_aln_ctl.scala 155:34]
-    node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_aln_ctl.scala 155:57]
-    node _T_97 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 156:10]
-    node _T_98 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 156:16]
-    node _T_99 = and(_T_97, _T_98) @[el2_ifu_aln_ctl.scala 156:14]
-    node _T_100 = bits(_T_99, 0, 0) @[el2_ifu_aln_ctl.scala 156:37]
-    node _T_101 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 157:10]
-    node _T_102 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 157:16]
-    node _T_103 = and(_T_101, _T_102) @[el2_ifu_aln_ctl.scala 157:14]
-    node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_aln_ctl.scala 157:37]
-    node _T_105 = eq(ifvalid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 158:6]
-    node _T_106 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 158:17]
-    node _T_107 = and(_T_105, _T_106) @[el2_ifu_aln_ctl.scala 158:15]
-    node _T_108 = bits(_T_107, 0, 0) @[el2_ifu_aln_ctl.scala 158:38]
+    rdptr_in <= _T_92 @[el2_ifu_aln_ctl.scala 163:12]
+    node _T_93 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 171:30]
+    node _T_94 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 171:36]
+    node _T_95 = and(_T_93, _T_94) @[el2_ifu_aln_ctl.scala 171:34]
+    node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_aln_ctl.scala 171:57]
+    node _T_97 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 172:10]
+    node _T_98 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 172:16]
+    node _T_99 = and(_T_97, _T_98) @[el2_ifu_aln_ctl.scala 172:14]
+    node _T_100 = bits(_T_99, 0, 0) @[el2_ifu_aln_ctl.scala 172:37]
+    node _T_101 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 173:10]
+    node _T_102 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 173:16]
+    node _T_103 = and(_T_101, _T_102) @[el2_ifu_aln_ctl.scala 173:14]
+    node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_aln_ctl.scala 173:37]
+    node _T_105 = eq(ifvalid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 174:6]
+    node _T_106 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 174:17]
+    node _T_107 = and(_T_105, _T_106) @[el2_ifu_aln_ctl.scala 174:15]
+    node _T_108 = bits(_T_107, 0, 0) @[el2_ifu_aln_ctl.scala 174:38]
     node _T_109 = mux(_T_96, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_110 = mux(_T_100, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_111 = mux(_T_104, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2288,24 +2303,24 @@ circuit el2_ifu_aln_ctl :
     node _T_115 = or(_T_114, _T_112) @[Mux.scala 27:72]
     wire _T_116 : UInt @[Mux.scala 27:72]
     _T_116 <= _T_115 @[Mux.scala 27:72]
-    wrptr_in <= _T_116 @[el2_ifu_aln_ctl.scala 155:12]
-    node _T_117 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 160:31]
-    node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:26]
-    node _T_119 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 160:43]
-    node _T_120 = and(_T_118, _T_119) @[el2_ifu_aln_ctl.scala 160:35]
-    node _T_121 = bits(_T_120, 0, 0) @[el2_ifu_aln_ctl.scala 160:52]
-    node _T_122 = or(q2off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 160:74]
-    node _T_123 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 161:11]
-    node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 161:6]
-    node _T_125 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 161:23]
-    node _T_126 = and(_T_124, _T_125) @[el2_ifu_aln_ctl.scala 161:15]
-    node _T_127 = bits(_T_126, 0, 0) @[el2_ifu_aln_ctl.scala 161:32]
-    node _T_128 = or(q2off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 161:54]
-    node _T_129 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 162:11]
-    node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 162:6]
-    node _T_131 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 162:23]
-    node _T_132 = and(_T_130, _T_131) @[el2_ifu_aln_ctl.scala 162:15]
-    node _T_133 = bits(_T_132, 0, 0) @[el2_ifu_aln_ctl.scala 162:32]
+    wrptr_in <= _T_116 @[el2_ifu_aln_ctl.scala 171:12]
+    node _T_117 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 176:31]
+    node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 176:26]
+    node _T_119 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 176:43]
+    node _T_120 = and(_T_118, _T_119) @[el2_ifu_aln_ctl.scala 176:35]
+    node _T_121 = bits(_T_120, 0, 0) @[el2_ifu_aln_ctl.scala 176:52]
+    node _T_122 = or(q2off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 176:74]
+    node _T_123 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 177:11]
+    node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 177:6]
+    node _T_125 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 177:23]
+    node _T_126 = and(_T_124, _T_125) @[el2_ifu_aln_ctl.scala 177:15]
+    node _T_127 = bits(_T_126, 0, 0) @[el2_ifu_aln_ctl.scala 177:32]
+    node _T_128 = or(q2off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 177:54]
+    node _T_129 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 178:11]
+    node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 178:6]
+    node _T_131 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 178:23]
+    node _T_132 = and(_T_130, _T_131) @[el2_ifu_aln_ctl.scala 178:15]
+    node _T_133 = bits(_T_132, 0, 0) @[el2_ifu_aln_ctl.scala 178:32]
     node _T_134 = mux(_T_121, _T_122, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_135 = mux(_T_127, _T_128, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_136 = mux(_T_133, q2off, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2313,24 +2328,24 @@ circuit el2_ifu_aln_ctl :
     node _T_138 = or(_T_137, _T_136) @[Mux.scala 27:72]
     wire _T_139 : UInt @[Mux.scala 27:72]
     _T_139 <= _T_138 @[Mux.scala 27:72]
-    q2off_in <= _T_139 @[el2_ifu_aln_ctl.scala 160:12]
-    node _T_140 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 164:31]
-    node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:26]
-    node _T_142 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 164:43]
-    node _T_143 = and(_T_141, _T_142) @[el2_ifu_aln_ctl.scala 164:35]
-    node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_aln_ctl.scala 164:52]
-    node _T_145 = or(q1off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 164:74]
-    node _T_146 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 165:11]
-    node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 165:6]
-    node _T_148 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 165:23]
-    node _T_149 = and(_T_147, _T_148) @[el2_ifu_aln_ctl.scala 165:15]
-    node _T_150 = bits(_T_149, 0, 0) @[el2_ifu_aln_ctl.scala 165:32]
-    node _T_151 = or(q1off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 165:54]
-    node _T_152 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 166:11]
-    node _T_153 = eq(_T_152, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 166:6]
-    node _T_154 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 166:23]
-    node _T_155 = and(_T_153, _T_154) @[el2_ifu_aln_ctl.scala 166:15]
-    node _T_156 = bits(_T_155, 0, 0) @[el2_ifu_aln_ctl.scala 166:32]
+    q2off_in <= _T_139 @[el2_ifu_aln_ctl.scala 176:12]
+    node _T_140 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 180:31]
+    node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 180:26]
+    node _T_142 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 180:43]
+    node _T_143 = and(_T_141, _T_142) @[el2_ifu_aln_ctl.scala 180:35]
+    node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_aln_ctl.scala 180:52]
+    node _T_145 = or(q1off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 180:74]
+    node _T_146 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 181:11]
+    node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 181:6]
+    node _T_148 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 181:23]
+    node _T_149 = and(_T_147, _T_148) @[el2_ifu_aln_ctl.scala 181:15]
+    node _T_150 = bits(_T_149, 0, 0) @[el2_ifu_aln_ctl.scala 181:32]
+    node _T_151 = or(q1off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 181:54]
+    node _T_152 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 182:11]
+    node _T_153 = eq(_T_152, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 182:6]
+    node _T_154 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 182:23]
+    node _T_155 = and(_T_153, _T_154) @[el2_ifu_aln_ctl.scala 182:15]
+    node _T_156 = bits(_T_155, 0, 0) @[el2_ifu_aln_ctl.scala 182:32]
     node _T_157 = mux(_T_144, _T_145, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_158 = mux(_T_150, _T_151, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_159 = mux(_T_156, q1off, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2338,24 +2353,24 @@ circuit el2_ifu_aln_ctl :
     node _T_161 = or(_T_160, _T_159) @[Mux.scala 27:72]
     wire _T_162 : UInt @[Mux.scala 27:72]
     _T_162 <= _T_161 @[Mux.scala 27:72]
-    q1off_in <= _T_162 @[el2_ifu_aln_ctl.scala 164:12]
-    node _T_163 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 168:31]
-    node _T_164 = eq(_T_163, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:26]
-    node _T_165 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:43]
-    node _T_166 = and(_T_164, _T_165) @[el2_ifu_aln_ctl.scala 168:35]
-    node _T_167 = bits(_T_166, 0, 0) @[el2_ifu_aln_ctl.scala 168:52]
-    node _T_168 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 168:76]
-    node _T_169 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 169:11]
-    node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 169:6]
-    node _T_171 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 169:23]
-    node _T_172 = and(_T_170, _T_171) @[el2_ifu_aln_ctl.scala 169:15]
-    node _T_173 = bits(_T_172, 0, 0) @[el2_ifu_aln_ctl.scala 169:32]
-    node _T_174 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 169:56]
-    node _T_175 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 170:11]
-    node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 170:6]
-    node _T_177 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 170:23]
-    node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 170:15]
-    node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 170:32]
+    q1off_in <= _T_162 @[el2_ifu_aln_ctl.scala 180:12]
+    node _T_163 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 184:31]
+    node _T_164 = eq(_T_163, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 184:26]
+    node _T_165 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 184:43]
+    node _T_166 = and(_T_164, _T_165) @[el2_ifu_aln_ctl.scala 184:35]
+    node _T_167 = bits(_T_166, 0, 0) @[el2_ifu_aln_ctl.scala 184:52]
+    node _T_168 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 184:76]
+    node _T_169 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 185:11]
+    node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 185:6]
+    node _T_171 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 185:23]
+    node _T_172 = and(_T_170, _T_171) @[el2_ifu_aln_ctl.scala 185:15]
+    node _T_173 = bits(_T_172, 0, 0) @[el2_ifu_aln_ctl.scala 185:32]
+    node _T_174 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 185:56]
+    node _T_175 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 186:11]
+    node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 186:6]
+    node _T_177 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 186:23]
+    node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 186:15]
+    node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 186:32]
     node _T_180 = mux(_T_167, _T_168, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_181 = mux(_T_173, _T_174, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_182 = mux(_T_179, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2363,10 +2378,10 @@ circuit el2_ifu_aln_ctl :
     node _T_184 = or(_T_183, _T_182) @[Mux.scala 27:72]
     wire _T_185 : UInt @[Mux.scala 27:72]
     _T_185 <= _T_184 @[Mux.scala 27:72]
-    q0off_in <= _T_185 @[el2_ifu_aln_ctl.scala 168:12]
-    node _T_186 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 172:31]
-    node _T_187 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 173:11]
-    node _T_188 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 174:11]
+    q0off_in <= _T_185 @[el2_ifu_aln_ctl.scala 184:12]
+    node _T_186 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 188:31]
+    node _T_187 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 189:11]
+    node _T_188 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 190:11]
     node _T_189 = mux(_T_186, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_190 = mux(_T_187, q1off, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_191 = mux(_T_188, q2off, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2374,9 +2389,9 @@ circuit el2_ifu_aln_ctl :
     node _T_193 = or(_T_192, _T_191) @[Mux.scala 27:72]
     wire q0ptr : UInt @[Mux.scala 27:72]
     q0ptr <= _T_193 @[Mux.scala 27:72]
-    node _T_194 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 176:32]
-    node _T_195 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 176:57]
-    node _T_196 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 176:83]
+    node _T_194 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 192:32]
+    node _T_195 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 192:57]
+    node _T_196 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 192:83]
     node _T_197 = mux(_T_194, q1off, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_198 = mux(_T_195, q2off, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_199 = mux(_T_196, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2384,25 +2399,25 @@ circuit el2_ifu_aln_ctl :
     node _T_201 = or(_T_200, _T_199) @[Mux.scala 27:72]
     wire q1ptr : UInt @[Mux.scala 27:72]
     q1ptr <= _T_201 @[Mux.scala 27:72]
-    node _T_202 = eq(q0ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 178:26]
+    node _T_202 = eq(q0ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 194:26]
     node q0sel = cat(q0ptr, _T_202) @[Cat.scala 29:58]
-    node _T_203 = eq(q1ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 180:26]
+    node _T_203 = eq(q1ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 196:26]
     node q1sel = cat(q1ptr, _T_203) @[Cat.scala 29:58]
-    node _T_204 = bits(io.ifu_bp_btb_target_f, 31, 1) @[el2_ifu_aln_ctl.scala 183:27]
+    node _T_204 = bits(io.ifu_bp_btb_target_f, 31, 1) @[el2_ifu_aln_ctl.scala 199:27]
     node _T_205 = cat(_T_204, io.ifu_bp_poffset_f) @[Cat.scala 29:58]
     node _T_206 = cat(_T_205, io.ifu_bp_fghr_f) @[Cat.scala 29:58]
     node _T_207 = cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f) @[Cat.scala 29:58]
     node _T_208 = cat(_T_207, io.ic_access_fault_type_f) @[Cat.scala 29:58]
     node _T_209 = cat(_T_208, _T_206) @[Cat.scala 29:58]
-    misc_data_in <= _T_209 @[el2_ifu_aln_ctl.scala 182:16]
-    node _T_210 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 185:31]
-    node _T_211 = bits(_T_210, 0, 0) @[el2_ifu_aln_ctl.scala 185:41]
+    misc_data_in <= _T_209 @[el2_ifu_aln_ctl.scala 198:16]
+    node _T_210 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 201:31]
+    node _T_211 = bits(_T_210, 0, 0) @[el2_ifu_aln_ctl.scala 201:41]
     node _T_212 = cat(misc1, misc0) @[Cat.scala 29:58]
-    node _T_213 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 186:9]
-    node _T_214 = bits(_T_213, 0, 0) @[el2_ifu_aln_ctl.scala 186:19]
+    node _T_213 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 202:9]
+    node _T_214 = bits(_T_213, 0, 0) @[el2_ifu_aln_ctl.scala 202:19]
     node _T_215 = cat(misc2, misc1) @[Cat.scala 29:58]
-    node _T_216 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 187:9]
-    node _T_217 = bits(_T_216, 0, 0) @[el2_ifu_aln_ctl.scala 187:19]
+    node _T_216 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 203:9]
+    node _T_217 = bits(_T_216, 0, 0) @[el2_ifu_aln_ctl.scala 203:19]
     node _T_218 = cat(misc0, misc2) @[Cat.scala 29:58]
     node _T_219 = mux(_T_211, _T_212, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_220 = mux(_T_214, _T_215, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2411,34 +2426,34 @@ circuit el2_ifu_aln_ctl :
     node _T_223 = or(_T_222, _T_221) @[Mux.scala 27:72]
     wire misceff : UInt<108> @[Mux.scala 27:72]
     misceff <= _T_223 @[Mux.scala 27:72]
-    node misc1eff = bits(misceff, 107, 55) @[el2_ifu_aln_ctl.scala 189:25]
-    node misc0eff = bits(misceff, 54, 0) @[el2_ifu_aln_ctl.scala 190:25]
-    node f1dbecc = bits(misc1eff, 52, 52) @[el2_ifu_aln_ctl.scala 193:25]
-    node _T_224 = bits(misc1eff, 51, 51) @[el2_ifu_aln_ctl.scala 194:21]
-    f1icaf <= _T_224 @[el2_ifu_aln_ctl.scala 194:10]
-    node f1ictype = bits(misc1eff, 50, 49) @[el2_ifu_aln_ctl.scala 195:26]
-    node f1prett = bits(misc1eff, 48, 18) @[el2_ifu_aln_ctl.scala 196:25]
-    node f1poffset = bits(misc1eff, 19, 8) @[el2_ifu_aln_ctl.scala 197:27]
-    node f1fghr = bits(misc1eff, 7, 0) @[el2_ifu_aln_ctl.scala 198:24]
-    node f0dbecc = bits(misc0eff, 54, 54) @[el2_ifu_aln_ctl.scala 200:25]
-    node _T_225 = bits(misc0eff, 53, 53) @[el2_ifu_aln_ctl.scala 201:21]
-    f0icaf <= _T_225 @[el2_ifu_aln_ctl.scala 201:10]
-    node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 202:26]
-    node f0prett = bits(misc0eff, 50, 20) @[el2_ifu_aln_ctl.scala 203:25]
-    node f0poffset = bits(misc0eff, 19, 8) @[el2_ifu_aln_ctl.scala 204:27]
-    node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 205:24]
-    node _T_226 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:37]
-    node _T_227 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:58]
-    node _T_228 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:77]
-    node _T_229 = bits(io.ifu_bp_way_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:96]
-    node _T_230 = bits(io.ifu_bp_valid_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:117]
-    node _T_231 = bits(io.ifu_bp_ret_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:20]
-    node _T_232 = bits(io.ifu_bp_hist1_f, 0, 0) @[el2_ifu_aln_ctl.scala 208:42]
-    node _T_233 = bits(io.ifu_bp_hist0_f, 0, 0) @[el2_ifu_aln_ctl.scala 208:63]
-    node _T_234 = bits(io.ifu_bp_pc4_f, 0, 0) @[el2_ifu_aln_ctl.scala 208:82]
-    node _T_235 = bits(io.ifu_bp_way_f, 0, 0) @[el2_ifu_aln_ctl.scala 208:101]
-    node _T_236 = bits(io.ifu_bp_valid_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:22]
-    node _T_237 = bits(io.ifu_bp_ret_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:41]
+    node misc1eff = bits(misceff, 107, 55) @[el2_ifu_aln_ctl.scala 205:25]
+    node misc0eff = bits(misceff, 54, 0) @[el2_ifu_aln_ctl.scala 206:25]
+    node f1dbecc = bits(misc1eff, 52, 52) @[el2_ifu_aln_ctl.scala 209:25]
+    node _T_224 = bits(misc1eff, 51, 51) @[el2_ifu_aln_ctl.scala 210:21]
+    f1icaf <= _T_224 @[el2_ifu_aln_ctl.scala 210:10]
+    node f1ictype = bits(misc1eff, 50, 49) @[el2_ifu_aln_ctl.scala 211:26]
+    node f1prett = bits(misc1eff, 48, 18) @[el2_ifu_aln_ctl.scala 212:25]
+    node f1poffset = bits(misc1eff, 19, 8) @[el2_ifu_aln_ctl.scala 213:27]
+    node f1fghr = bits(misc1eff, 7, 0) @[el2_ifu_aln_ctl.scala 214:24]
+    node f0dbecc = bits(misc0eff, 54, 54) @[el2_ifu_aln_ctl.scala 216:25]
+    node _T_225 = bits(misc0eff, 53, 53) @[el2_ifu_aln_ctl.scala 217:21]
+    f0icaf <= _T_225 @[el2_ifu_aln_ctl.scala 217:10]
+    node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 218:26]
+    node f0prett = bits(misc0eff, 50, 20) @[el2_ifu_aln_ctl.scala 219:25]
+    node f0poffset = bits(misc0eff, 19, 8) @[el2_ifu_aln_ctl.scala 220:27]
+    node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 221:24]
+    node _T_226 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:37]
+    node _T_227 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:58]
+    node _T_228 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:77]
+    node _T_229 = bits(io.ifu_bp_way_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:96]
+    node _T_230 = bits(io.ifu_bp_valid_f, 1, 1) @[el2_ifu_aln_ctl.scala 223:117]
+    node _T_231 = bits(io.ifu_bp_ret_f, 1, 1) @[el2_ifu_aln_ctl.scala 224:20]
+    node _T_232 = bits(io.ifu_bp_hist1_f, 0, 0) @[el2_ifu_aln_ctl.scala 224:42]
+    node _T_233 = bits(io.ifu_bp_hist0_f, 0, 0) @[el2_ifu_aln_ctl.scala 224:63]
+    node _T_234 = bits(io.ifu_bp_pc4_f, 0, 0) @[el2_ifu_aln_ctl.scala 224:82]
+    node _T_235 = bits(io.ifu_bp_way_f, 0, 0) @[el2_ifu_aln_ctl.scala 224:101]
+    node _T_236 = bits(io.ifu_bp_valid_f, 0, 0) @[el2_ifu_aln_ctl.scala 225:22]
+    node _T_237 = bits(io.ifu_bp_ret_f, 0, 0) @[el2_ifu_aln_ctl.scala 225:41]
     node _T_238 = cat(_T_235, _T_236) @[Cat.scala 29:58]
     node _T_239 = cat(_T_238, _T_237) @[Cat.scala 29:58]
     node _T_240 = cat(_T_232, _T_233) @[Cat.scala 29:58]
@@ -2450,15 +2465,15 @@ circuit el2_ifu_aln_ctl :
     node _T_246 = cat(_T_245, _T_228) @[Cat.scala 29:58]
     node _T_247 = cat(_T_246, _T_244) @[Cat.scala 29:58]
     node _T_248 = cat(_T_247, _T_242) @[Cat.scala 29:58]
-    brdata_in <= _T_248 @[el2_ifu_aln_ctl.scala 207:13]
-    node _T_249 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 211:33]
-    node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_aln_ctl.scala 211:37]
+    brdata_in <= _T_248 @[el2_ifu_aln_ctl.scala 223:13]
+    node _T_249 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 227:33]
+    node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_aln_ctl.scala 227:37]
     node _T_251 = cat(brdata1, brdata0) @[Cat.scala 29:58]
-    node _T_252 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 212:9]
-    node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_aln_ctl.scala 212:13]
+    node _T_252 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 228:9]
+    node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_aln_ctl.scala 228:13]
     node _T_254 = cat(brdata2, brdata1) @[Cat.scala 29:58]
-    node _T_255 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 213:9]
-    node _T_256 = bits(_T_255, 0, 0) @[el2_ifu_aln_ctl.scala 213:13]
+    node _T_255 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 229:9]
+    node _T_256 = bits(_T_255, 0, 0) @[el2_ifu_aln_ctl.scala 229:13]
     node _T_257 = cat(brdata0, brdata2) @[Cat.scala 29:58]
     node _T_258 = mux(_T_250, _T_251, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_259 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2467,154 +2482,154 @@ circuit el2_ifu_aln_ctl :
     node _T_262 = or(_T_261, _T_260) @[Mux.scala 27:72]
     wire brdataeff : UInt<24> @[Mux.scala 27:72]
     brdataeff <= _T_262 @[Mux.scala 27:72]
-    node brdata0eff = bits(brdataeff, 11, 0) @[el2_ifu_aln_ctl.scala 215:43]
-    node brdata1eff = bits(brdataeff, 23, 12) @[el2_ifu_aln_ctl.scala 215:61]
-    node _T_263 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 217:37]
-    node _T_264 = bits(_T_263, 0, 0) @[el2_ifu_aln_ctl.scala 217:41]
-    node _T_265 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 217:68]
-    node _T_266 = bits(_T_265, 0, 0) @[el2_ifu_aln_ctl.scala 217:72]
-    node _T_267 = bits(brdata0eff, 11, 6) @[el2_ifu_aln_ctl.scala 217:92]
+    node brdata0eff = bits(brdataeff, 11, 0) @[el2_ifu_aln_ctl.scala 231:43]
+    node brdata1eff = bits(brdataeff, 23, 12) @[el2_ifu_aln_ctl.scala 231:61]
+    node _T_263 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 233:37]
+    node _T_264 = bits(_T_263, 0, 0) @[el2_ifu_aln_ctl.scala 233:41]
+    node _T_265 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 233:68]
+    node _T_266 = bits(_T_265, 0, 0) @[el2_ifu_aln_ctl.scala 233:72]
+    node _T_267 = bits(brdata0eff, 11, 6) @[el2_ifu_aln_ctl.scala 233:92]
     node _T_268 = mux(_T_264, brdata0eff, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_269 = mux(_T_266, _T_267, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_270 = or(_T_268, _T_269) @[Mux.scala 27:72]
     wire brdata0final : UInt<12> @[Mux.scala 27:72]
     brdata0final <= _T_270 @[Mux.scala 27:72]
-    node _T_271 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 218:37]
-    node _T_272 = bits(_T_271, 0, 0) @[el2_ifu_aln_ctl.scala 218:41]
-    node _T_273 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 218:68]
-    node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_aln_ctl.scala 218:72]
-    node _T_275 = bits(brdata1eff, 11, 6) @[el2_ifu_aln_ctl.scala 218:92]
+    node _T_271 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 234:37]
+    node _T_272 = bits(_T_271, 0, 0) @[el2_ifu_aln_ctl.scala 234:41]
+    node _T_273 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 234:68]
+    node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_aln_ctl.scala 234:72]
+    node _T_275 = bits(brdata1eff, 11, 6) @[el2_ifu_aln_ctl.scala 234:92]
     node _T_276 = mux(_T_272, brdata1eff, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_277 = mux(_T_274, _T_275, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_278 = or(_T_276, _T_277) @[Mux.scala 27:72]
     wire brdata1final : UInt<12> @[Mux.scala 27:72]
     brdata1final <= _T_278 @[Mux.scala 27:72]
-    node _T_279 = bits(brdata0final, 6, 6) @[el2_ifu_aln_ctl.scala 220:31]
-    node _T_280 = bits(brdata0final, 0, 0) @[el2_ifu_aln_ctl.scala 220:47]
+    node _T_279 = bits(brdata0final, 6, 6) @[el2_ifu_aln_ctl.scala 236:31]
+    node _T_280 = bits(brdata0final, 0, 0) @[el2_ifu_aln_ctl.scala 236:47]
     node f0ret = cat(_T_279, _T_280) @[Cat.scala 29:58]
-    node _T_281 = bits(brdata0final, 7, 7) @[el2_ifu_aln_ctl.scala 221:33]
-    node _T_282 = bits(brdata0final, 1, 1) @[el2_ifu_aln_ctl.scala 221:49]
+    node _T_281 = bits(brdata0final, 7, 7) @[el2_ifu_aln_ctl.scala 237:33]
+    node _T_282 = bits(brdata0final, 1, 1) @[el2_ifu_aln_ctl.scala 237:49]
     node f0brend = cat(_T_281, _T_282) @[Cat.scala 29:58]
-    node _T_283 = bits(brdata0final, 8, 8) @[el2_ifu_aln_ctl.scala 222:31]
-    node _T_284 = bits(brdata0final, 2, 2) @[el2_ifu_aln_ctl.scala 222:47]
+    node _T_283 = bits(brdata0final, 8, 8) @[el2_ifu_aln_ctl.scala 238:31]
+    node _T_284 = bits(brdata0final, 2, 2) @[el2_ifu_aln_ctl.scala 238:47]
     node f0way = cat(_T_283, _T_284) @[Cat.scala 29:58]
-    node _T_285 = bits(brdata0final, 9, 9) @[el2_ifu_aln_ctl.scala 223:31]
-    node _T_286 = bits(brdata0final, 3, 3) @[el2_ifu_aln_ctl.scala 223:47]
+    node _T_285 = bits(brdata0final, 9, 9) @[el2_ifu_aln_ctl.scala 239:31]
+    node _T_286 = bits(brdata0final, 3, 3) @[el2_ifu_aln_ctl.scala 239:47]
     node f0pc4 = cat(_T_285, _T_286) @[Cat.scala 29:58]
-    node _T_287 = bits(brdata0final, 10, 10) @[el2_ifu_aln_ctl.scala 224:33]
-    node _T_288 = bits(brdata0final, 4, 4) @[el2_ifu_aln_ctl.scala 224:50]
+    node _T_287 = bits(brdata0final, 10, 10) @[el2_ifu_aln_ctl.scala 240:33]
+    node _T_288 = bits(brdata0final, 4, 4) @[el2_ifu_aln_ctl.scala 240:50]
     node f0hist0 = cat(_T_287, _T_288) @[Cat.scala 29:58]
-    node _T_289 = bits(brdata0final, 11, 11) @[el2_ifu_aln_ctl.scala 225:33]
-    node _T_290 = bits(brdata0final, 5, 5) @[el2_ifu_aln_ctl.scala 225:50]
+    node _T_289 = bits(brdata0final, 11, 11) @[el2_ifu_aln_ctl.scala 241:33]
+    node _T_290 = bits(brdata0final, 5, 5) @[el2_ifu_aln_ctl.scala 241:50]
     node f0hist1 = cat(_T_289, _T_290) @[Cat.scala 29:58]
-    node _T_291 = bits(brdata1final, 6, 6) @[el2_ifu_aln_ctl.scala 227:31]
-    node _T_292 = bits(brdata1final, 0, 0) @[el2_ifu_aln_ctl.scala 227:47]
+    node _T_291 = bits(brdata1final, 6, 6) @[el2_ifu_aln_ctl.scala 243:31]
+    node _T_292 = bits(brdata1final, 0, 0) @[el2_ifu_aln_ctl.scala 243:47]
     node f1ret = cat(_T_291, _T_292) @[Cat.scala 29:58]
-    node _T_293 = bits(brdata1final, 7, 7) @[el2_ifu_aln_ctl.scala 228:33]
-    node _T_294 = bits(brdata1final, 1, 1) @[el2_ifu_aln_ctl.scala 228:49]
+    node _T_293 = bits(brdata1final, 7, 7) @[el2_ifu_aln_ctl.scala 244:33]
+    node _T_294 = bits(brdata1final, 1, 1) @[el2_ifu_aln_ctl.scala 244:49]
     node f1brend = cat(_T_293, _T_294) @[Cat.scala 29:58]
-    node _T_295 = bits(brdata1final, 8, 8) @[el2_ifu_aln_ctl.scala 229:31]
-    node _T_296 = bits(brdata1final, 2, 2) @[el2_ifu_aln_ctl.scala 229:47]
+    node _T_295 = bits(brdata1final, 8, 8) @[el2_ifu_aln_ctl.scala 245:31]
+    node _T_296 = bits(brdata1final, 2, 2) @[el2_ifu_aln_ctl.scala 245:47]
     node f1way = cat(_T_295, _T_296) @[Cat.scala 29:58]
-    node _T_297 = bits(brdata1final, 9, 9) @[el2_ifu_aln_ctl.scala 230:31]
-    node _T_298 = bits(brdata1final, 3, 3) @[el2_ifu_aln_ctl.scala 230:47]
+    node _T_297 = bits(brdata1final, 9, 9) @[el2_ifu_aln_ctl.scala 246:31]
+    node _T_298 = bits(brdata1final, 3, 3) @[el2_ifu_aln_ctl.scala 246:47]
     node f1pc4 = cat(_T_297, _T_298) @[Cat.scala 29:58]
-    node _T_299 = bits(brdata1final, 10, 10) @[el2_ifu_aln_ctl.scala 231:33]
-    node _T_300 = bits(brdata1final, 4, 4) @[el2_ifu_aln_ctl.scala 231:50]
+    node _T_299 = bits(brdata1final, 10, 10) @[el2_ifu_aln_ctl.scala 247:33]
+    node _T_300 = bits(brdata1final, 4, 4) @[el2_ifu_aln_ctl.scala 247:50]
     node f1hist0 = cat(_T_299, _T_300) @[Cat.scala 29:58]
-    node _T_301 = bits(brdata1final, 11, 11) @[el2_ifu_aln_ctl.scala 232:33]
-    node _T_302 = bits(brdata1final, 5, 5) @[el2_ifu_aln_ctl.scala 232:50]
+    node _T_301 = bits(brdata1final, 11, 11) @[el2_ifu_aln_ctl.scala 248:33]
+    node _T_302 = bits(brdata1final, 5, 5) @[el2_ifu_aln_ctl.scala 248:50]
     node f1hist1 = cat(_T_301, _T_302) @[Cat.scala 29:58]
-    node _T_303 = bits(f2val, 0, 0) @[el2_ifu_aln_ctl.scala 235:20]
-    f2_valid <= _T_303 @[el2_ifu_aln_ctl.scala 235:12]
-    node _T_304 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 236:22]
-    sf1_valid <= _T_304 @[el2_ifu_aln_ctl.scala 236:13]
-    node _T_305 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 237:22]
-    sf0_valid <= _T_305 @[el2_ifu_aln_ctl.scala 237:13]
-    node _T_306 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 239:28]
-    node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 239:21]
-    node _T_308 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 239:39]
-    node consume_fb0 = and(_T_307, _T_308) @[el2_ifu_aln_ctl.scala 239:32]
-    node _T_309 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 240:28]
-    node _T_310 = eq(_T_309, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 240:21]
-    node _T_311 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 240:39]
-    node consume_fb1 = and(_T_310, _T_311) @[el2_ifu_aln_ctl.scala 240:32]
-    node _T_312 = eq(consume_fb1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 242:39]
-    node _T_313 = and(consume_fb0, _T_312) @[el2_ifu_aln_ctl.scala 242:37]
-    node _T_314 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 242:54]
-    node _T_315 = and(_T_313, _T_314) @[el2_ifu_aln_ctl.scala 242:52]
-    io.ifu_fb_consume1 <= _T_315 @[el2_ifu_aln_ctl.scala 242:22]
-    node _T_316 = and(consume_fb0, consume_fb1) @[el2_ifu_aln_ctl.scala 243:37]
-    node _T_317 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 243:54]
-    node _T_318 = and(_T_316, _T_317) @[el2_ifu_aln_ctl.scala 243:52]
-    io.ifu_fb_consume2 <= _T_318 @[el2_ifu_aln_ctl.scala 243:22]
-    node _T_319 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_aln_ctl.scala 245:30]
-    ifvalid <= _T_319 @[el2_ifu_aln_ctl.scala 245:11]
-    node _T_320 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 247:18]
-    node _T_321 = and(_T_320, sf1_valid) @[el2_ifu_aln_ctl.scala 247:29]
-    shift_f1_f0 <= _T_321 @[el2_ifu_aln_ctl.scala 247:15]
-    node _T_322 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 248:18]
-    node _T_323 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 248:31]
-    node _T_324 = and(_T_322, _T_323) @[el2_ifu_aln_ctl.scala 248:29]
-    node _T_325 = and(_T_324, f2_valid) @[el2_ifu_aln_ctl.scala 248:42]
-    shift_f2_f0 <= _T_325 @[el2_ifu_aln_ctl.scala 248:15]
-    node _T_326 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 249:18]
-    node _T_327 = and(_T_326, sf1_valid) @[el2_ifu_aln_ctl.scala 249:29]
-    node _T_328 = and(_T_327, f2_valid) @[el2_ifu_aln_ctl.scala 249:42]
-    shift_f2_f1 <= _T_328 @[el2_ifu_aln_ctl.scala 249:15]
-    node _T_329 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:26]
-    node _T_330 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:39]
-    node _T_331 = and(_T_329, _T_330) @[el2_ifu_aln_ctl.scala 251:37]
-    node _T_332 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:52]
-    node _T_333 = and(_T_331, _T_332) @[el2_ifu_aln_ctl.scala 251:50]
-    node _T_334 = and(_T_333, ifvalid) @[el2_ifu_aln_ctl.scala 251:62]
-    fetch_to_f0 <= _T_334 @[el2_ifu_aln_ctl.scala 251:22]
-    node _T_335 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 252:26]
-    node _T_336 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 252:39]
-    node _T_337 = and(_T_335, _T_336) @[el2_ifu_aln_ctl.scala 252:37]
-    node _T_338 = and(_T_337, f2_valid) @[el2_ifu_aln_ctl.scala 252:50]
-    node _T_339 = and(_T_338, ifvalid) @[el2_ifu_aln_ctl.scala 252:62]
-    node _T_340 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:6]
-    node _T_341 = and(_T_340, sf1_valid) @[el2_ifu_aln_ctl.scala 253:17]
-    node _T_342 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:32]
-    node _T_343 = and(_T_341, _T_342) @[el2_ifu_aln_ctl.scala 253:30]
-    node _T_344 = and(_T_343, ifvalid) @[el2_ifu_aln_ctl.scala 253:42]
-    node _T_345 = or(_T_339, _T_344) @[el2_ifu_aln_ctl.scala 252:74]
-    node _T_346 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 254:19]
-    node _T_347 = and(sf0_valid, _T_346) @[el2_ifu_aln_ctl.scala 254:17]
-    node _T_348 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 254:32]
-    node _T_349 = and(_T_347, _T_348) @[el2_ifu_aln_ctl.scala 254:30]
-    node _T_350 = and(_T_349, ifvalid) @[el2_ifu_aln_ctl.scala 254:42]
-    node _T_351 = or(_T_345, _T_350) @[el2_ifu_aln_ctl.scala 253:54]
-    fetch_to_f1 <= _T_351 @[el2_ifu_aln_ctl.scala 252:22]
-    node _T_352 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 256:26]
-    node _T_353 = and(_T_352, sf1_valid) @[el2_ifu_aln_ctl.scala 256:37]
-    node _T_354 = and(_T_353, f2_valid) @[el2_ifu_aln_ctl.scala 256:50]
-    node _T_355 = and(_T_354, ifvalid) @[el2_ifu_aln_ctl.scala 256:62]
-    node _T_356 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 257:17]
-    node _T_357 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 257:32]
-    node _T_358 = and(_T_356, _T_357) @[el2_ifu_aln_ctl.scala 257:30]
-    node _T_359 = and(_T_358, ifvalid) @[el2_ifu_aln_ctl.scala 257:42]
-    node _T_360 = or(_T_355, _T_359) @[el2_ifu_aln_ctl.scala 256:74]
-    fetch_to_f2 <= _T_360 @[el2_ifu_aln_ctl.scala 256:22]
-    node _T_361 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 259:25]
-    node f0pc_plus1 = tail(_T_361, 1) @[el2_ifu_aln_ctl.scala 259:25]
-    node _T_362 = add(f1pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 261:25]
-    node f1pc_plus1 = tail(_T_362, 1) @[el2_ifu_aln_ctl.scala 261:25]
+    node _T_303 = bits(f2val, 0, 0) @[el2_ifu_aln_ctl.scala 251:20]
+    f2_valid <= _T_303 @[el2_ifu_aln_ctl.scala 251:12]
+    node _T_304 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 252:22]
+    sf1_valid <= _T_304 @[el2_ifu_aln_ctl.scala 252:13]
+    node _T_305 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 253:22]
+    sf0_valid <= _T_305 @[el2_ifu_aln_ctl.scala 253:13]
+    node _T_306 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 255:28]
+    node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 255:21]
+    node _T_308 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 255:39]
+    node consume_fb0 = and(_T_307, _T_308) @[el2_ifu_aln_ctl.scala 255:32]
+    node _T_309 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 256:28]
+    node _T_310 = eq(_T_309, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 256:21]
+    node _T_311 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 256:39]
+    node consume_fb1 = and(_T_310, _T_311) @[el2_ifu_aln_ctl.scala 256:32]
+    node _T_312 = eq(consume_fb1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 258:39]
+    node _T_313 = and(consume_fb0, _T_312) @[el2_ifu_aln_ctl.scala 258:37]
+    node _T_314 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 258:54]
+    node _T_315 = and(_T_313, _T_314) @[el2_ifu_aln_ctl.scala 258:52]
+    io.ifu_fb_consume1 <= _T_315 @[el2_ifu_aln_ctl.scala 258:22]
+    node _T_316 = and(consume_fb0, consume_fb1) @[el2_ifu_aln_ctl.scala 259:37]
+    node _T_317 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 259:54]
+    node _T_318 = and(_T_316, _T_317) @[el2_ifu_aln_ctl.scala 259:52]
+    io.ifu_fb_consume2 <= _T_318 @[el2_ifu_aln_ctl.scala 259:22]
+    node _T_319 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_aln_ctl.scala 261:30]
+    ifvalid <= _T_319 @[el2_ifu_aln_ctl.scala 261:11]
+    node _T_320 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 263:18]
+    node _T_321 = and(_T_320, sf1_valid) @[el2_ifu_aln_ctl.scala 263:29]
+    shift_f1_f0 <= _T_321 @[el2_ifu_aln_ctl.scala 263:15]
+    node _T_322 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 264:18]
+    node _T_323 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 264:31]
+    node _T_324 = and(_T_322, _T_323) @[el2_ifu_aln_ctl.scala 264:29]
+    node _T_325 = and(_T_324, f2_valid) @[el2_ifu_aln_ctl.scala 264:42]
+    shift_f2_f0 <= _T_325 @[el2_ifu_aln_ctl.scala 264:15]
+    node _T_326 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 265:18]
+    node _T_327 = and(_T_326, sf1_valid) @[el2_ifu_aln_ctl.scala 265:29]
+    node _T_328 = and(_T_327, f2_valid) @[el2_ifu_aln_ctl.scala 265:42]
+    shift_f2_f1 <= _T_328 @[el2_ifu_aln_ctl.scala 265:15]
+    node _T_329 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:26]
+    node _T_330 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:39]
+    node _T_331 = and(_T_329, _T_330) @[el2_ifu_aln_ctl.scala 267:37]
+    node _T_332 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:52]
+    node _T_333 = and(_T_331, _T_332) @[el2_ifu_aln_ctl.scala 267:50]
+    node _T_334 = and(_T_333, ifvalid) @[el2_ifu_aln_ctl.scala 267:62]
+    fetch_to_f0 <= _T_334 @[el2_ifu_aln_ctl.scala 267:22]
+    node _T_335 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 268:26]
+    node _T_336 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 268:39]
+    node _T_337 = and(_T_335, _T_336) @[el2_ifu_aln_ctl.scala 268:37]
+    node _T_338 = and(_T_337, f2_valid) @[el2_ifu_aln_ctl.scala 268:50]
+    node _T_339 = and(_T_338, ifvalid) @[el2_ifu_aln_ctl.scala 268:62]
+    node _T_340 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 269:6]
+    node _T_341 = and(_T_340, sf1_valid) @[el2_ifu_aln_ctl.scala 269:17]
+    node _T_342 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 269:32]
+    node _T_343 = and(_T_341, _T_342) @[el2_ifu_aln_ctl.scala 269:30]
+    node _T_344 = and(_T_343, ifvalid) @[el2_ifu_aln_ctl.scala 269:42]
+    node _T_345 = or(_T_339, _T_344) @[el2_ifu_aln_ctl.scala 268:74]
+    node _T_346 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 270:19]
+    node _T_347 = and(sf0_valid, _T_346) @[el2_ifu_aln_ctl.scala 270:17]
+    node _T_348 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 270:32]
+    node _T_349 = and(_T_347, _T_348) @[el2_ifu_aln_ctl.scala 270:30]
+    node _T_350 = and(_T_349, ifvalid) @[el2_ifu_aln_ctl.scala 270:42]
+    node _T_351 = or(_T_345, _T_350) @[el2_ifu_aln_ctl.scala 269:54]
+    fetch_to_f1 <= _T_351 @[el2_ifu_aln_ctl.scala 268:22]
+    node _T_352 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:26]
+    node _T_353 = and(_T_352, sf1_valid) @[el2_ifu_aln_ctl.scala 272:37]
+    node _T_354 = and(_T_353, f2_valid) @[el2_ifu_aln_ctl.scala 272:50]
+    node _T_355 = and(_T_354, ifvalid) @[el2_ifu_aln_ctl.scala 272:62]
+    node _T_356 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 273:17]
+    node _T_357 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 273:32]
+    node _T_358 = and(_T_356, _T_357) @[el2_ifu_aln_ctl.scala 273:30]
+    node _T_359 = and(_T_358, ifvalid) @[el2_ifu_aln_ctl.scala 273:42]
+    node _T_360 = or(_T_355, _T_359) @[el2_ifu_aln_ctl.scala 272:74]
+    fetch_to_f2 <= _T_360 @[el2_ifu_aln_ctl.scala 272:22]
+    node _T_361 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 275:25]
+    node f0pc_plus1 = tail(_T_361, 1) @[el2_ifu_aln_ctl.scala 275:25]
+    node _T_362 = add(f1pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 277:25]
+    node f1pc_plus1 = tail(_T_362, 1) @[el2_ifu_aln_ctl.scala 277:25]
     node _T_363 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15]
     node _T_364 = mux(_T_363, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
-    node _T_365 = and(_T_364, f0pc_plus1) @[el2_ifu_aln_ctl.scala 263:38]
-    node _T_366 = eq(f1_shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 263:64]
+    node _T_365 = and(_T_364, f0pc_plus1) @[el2_ifu_aln_ctl.scala 279:38]
+    node _T_366 = eq(f1_shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:64]
     node _T_367 = bits(_T_366, 0, 0) @[Bitwise.scala 72:15]
     node _T_368 = mux(_T_367, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
-    node _T_369 = and(_T_368, f0pc) @[el2_ifu_aln_ctl.scala 263:78]
-    node sf1pc = or(_T_365, _T_369) @[el2_ifu_aln_ctl.scala 263:52]
-    node _T_370 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 265:36]
-    node _T_371 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 266:17]
-    node _T_372 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:6]
-    node _T_373 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:21]
-    node _T_374 = and(_T_372, _T_373) @[el2_ifu_aln_ctl.scala 267:19]
-    node _T_375 = bits(_T_374, 0, 0) @[el2_ifu_aln_ctl.scala 267:35]
+    node _T_369 = and(_T_368, f0pc) @[el2_ifu_aln_ctl.scala 279:78]
+    node sf1pc = or(_T_365, _T_369) @[el2_ifu_aln_ctl.scala 279:52]
+    node _T_370 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 281:36]
+    node _T_371 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 282:17]
+    node _T_372 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 283:6]
+    node _T_373 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 283:21]
+    node _T_374 = and(_T_372, _T_373) @[el2_ifu_aln_ctl.scala 283:19]
+    node _T_375 = bits(_T_374, 0, 0) @[el2_ifu_aln_ctl.scala 283:35]
     node _T_376 = mux(_T_370, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_377 = mux(_T_371, f2pc, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_378 = mux(_T_375, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2622,16 +2637,16 @@ circuit el2_ifu_aln_ctl :
     node _T_380 = or(_T_379, _T_378) @[Mux.scala 27:72]
     wire _T_381 : UInt @[Mux.scala 27:72]
     _T_381 <= _T_380 @[Mux.scala 27:72]
-    f1pc_in <= _T_381 @[el2_ifu_aln_ctl.scala 265:11]
-    node _T_382 = bits(fetch_to_f0, 0, 0) @[el2_ifu_aln_ctl.scala 269:36]
-    node _T_383 = bits(shift_f2_f0, 0, 0) @[el2_ifu_aln_ctl.scala 270:36]
-    node _T_384 = bits(shift_f1_f0, 0, 0) @[el2_ifu_aln_ctl.scala 271:36]
-    node _T_385 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:24]
-    node _T_386 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:39]
-    node _T_387 = and(_T_385, _T_386) @[el2_ifu_aln_ctl.scala 272:37]
-    node _T_388 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:54]
-    node _T_389 = and(_T_387, _T_388) @[el2_ifu_aln_ctl.scala 272:52]
-    node _T_390 = bits(_T_389, 0, 0) @[el2_ifu_aln_ctl.scala 272:68]
+    f1pc_in <= _T_381 @[el2_ifu_aln_ctl.scala 281:11]
+    node _T_382 = bits(fetch_to_f0, 0, 0) @[el2_ifu_aln_ctl.scala 285:36]
+    node _T_383 = bits(shift_f2_f0, 0, 0) @[el2_ifu_aln_ctl.scala 286:36]
+    node _T_384 = bits(shift_f1_f0, 0, 0) @[el2_ifu_aln_ctl.scala 287:36]
+    node _T_385 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 288:24]
+    node _T_386 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 288:39]
+    node _T_387 = and(_T_385, _T_386) @[el2_ifu_aln_ctl.scala 288:37]
+    node _T_388 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 288:54]
+    node _T_389 = and(_T_387, _T_388) @[el2_ifu_aln_ctl.scala 288:52]
+    node _T_390 = bits(_T_389, 0, 0) @[el2_ifu_aln_ctl.scala 288:68]
     node _T_391 = mux(_T_382, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_392 = mux(_T_383, f2pc, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_393 = mux(_T_384, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2641,48 +2656,48 @@ circuit el2_ifu_aln_ctl :
     node _T_397 = or(_T_396, _T_394) @[Mux.scala 27:72]
     wire _T_398 : UInt @[Mux.scala 27:72]
     _T_398 <= _T_397 @[Mux.scala 27:72]
-    f0pc_in <= _T_398 @[el2_ifu_aln_ctl.scala 269:11]
-    node _T_399 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 274:40]
-    node _T_400 = and(fetch_to_f2, _T_399) @[el2_ifu_aln_ctl.scala 274:38]
-    node _T_401 = bits(_T_400, 0, 0) @[el2_ifu_aln_ctl.scala 274:61]
-    node _T_402 = eq(fetch_to_f2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 275:6]
-    node _T_403 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 275:21]
-    node _T_404 = and(_T_402, _T_403) @[el2_ifu_aln_ctl.scala 275:19]
-    node _T_405 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 275:36]
-    node _T_406 = and(_T_404, _T_405) @[el2_ifu_aln_ctl.scala 275:34]
-    node _T_407 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 275:51]
-    node _T_408 = and(_T_406, _T_407) @[el2_ifu_aln_ctl.scala 275:49]
-    node _T_409 = bits(_T_408, 0, 0) @[el2_ifu_aln_ctl.scala 275:72]
+    f0pc_in <= _T_398 @[el2_ifu_aln_ctl.scala 285:11]
+    node _T_399 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 290:40]
+    node _T_400 = and(fetch_to_f2, _T_399) @[el2_ifu_aln_ctl.scala 290:38]
+    node _T_401 = bits(_T_400, 0, 0) @[el2_ifu_aln_ctl.scala 290:61]
+    node _T_402 = eq(fetch_to_f2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:6]
+    node _T_403 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:21]
+    node _T_404 = and(_T_402, _T_403) @[el2_ifu_aln_ctl.scala 291:19]
+    node _T_405 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:36]
+    node _T_406 = and(_T_404, _T_405) @[el2_ifu_aln_ctl.scala 291:34]
+    node _T_407 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:51]
+    node _T_408 = and(_T_406, _T_407) @[el2_ifu_aln_ctl.scala 291:49]
+    node _T_409 = bits(_T_408, 0, 0) @[el2_ifu_aln_ctl.scala 291:72]
     node _T_410 = mux(_T_401, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_411 = mux(_T_409, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_412 = or(_T_410, _T_411) @[Mux.scala 27:72]
     wire _T_413 : UInt @[Mux.scala 27:72]
     _T_413 <= _T_412 @[Mux.scala 27:72]
-    f2val_in <= _T_413 @[el2_ifu_aln_ctl.scala 274:12]
-    node _T_414 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 277:35]
-    node _T_415 = bits(f1val, 1, 1) @[el2_ifu_aln_ctl.scala 277:48]
-    node _T_416 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 277:66]
-    node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 277:53]
+    f2val_in <= _T_413 @[el2_ifu_aln_ctl.scala 290:12]
+    node _T_414 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 293:35]
+    node _T_415 = bits(f1val, 1, 1) @[el2_ifu_aln_ctl.scala 293:48]
+    node _T_416 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 293:66]
+    node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 293:53]
     node _T_418 = mux(_T_414, _T_415, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_419 = mux(_T_417, f1val, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_420 = or(_T_418, _T_419) @[Mux.scala 27:72]
     wire _T_421 : UInt @[Mux.scala 27:72]
     _T_421 <= _T_420 @[Mux.scala 27:72]
-    sf1val <= _T_421 @[el2_ifu_aln_ctl.scala 277:10]
-    node _T_422 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:40]
-    node _T_423 = and(fetch_to_f1, _T_422) @[el2_ifu_aln_ctl.scala 279:38]
-    node _T_424 = bits(_T_423, 0, 0) @[el2_ifu_aln_ctl.scala 279:61]
-    node _T_425 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 280:20]
-    node _T_426 = and(shift_f2_f1, _T_425) @[el2_ifu_aln_ctl.scala 280:18]
-    node _T_427 = bits(_T_426, 0, 0) @[el2_ifu_aln_ctl.scala 280:41]
-    node _T_428 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:6]
-    node _T_429 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:21]
-    node _T_430 = and(_T_428, _T_429) @[el2_ifu_aln_ctl.scala 281:19]
-    node _T_431 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:36]
-    node _T_432 = and(_T_430, _T_431) @[el2_ifu_aln_ctl.scala 281:34]
-    node _T_433 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:51]
-    node _T_434 = and(_T_432, _T_433) @[el2_ifu_aln_ctl.scala 281:49]
-    node _T_435 = bits(_T_434, 0, 0) @[el2_ifu_aln_ctl.scala 281:72]
+    sf1val <= _T_421 @[el2_ifu_aln_ctl.scala 293:10]
+    node _T_422 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 295:40]
+    node _T_423 = and(fetch_to_f1, _T_422) @[el2_ifu_aln_ctl.scala 295:38]
+    node _T_424 = bits(_T_423, 0, 0) @[el2_ifu_aln_ctl.scala 295:61]
+    node _T_425 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 296:20]
+    node _T_426 = and(shift_f2_f1, _T_425) @[el2_ifu_aln_ctl.scala 296:18]
+    node _T_427 = bits(_T_426, 0, 0) @[el2_ifu_aln_ctl.scala 296:41]
+    node _T_428 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:6]
+    node _T_429 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:21]
+    node _T_430 = and(_T_428, _T_429) @[el2_ifu_aln_ctl.scala 297:19]
+    node _T_431 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:36]
+    node _T_432 = and(_T_430, _T_431) @[el2_ifu_aln_ctl.scala 297:34]
+    node _T_433 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 297:51]
+    node _T_434 = and(_T_432, _T_433) @[el2_ifu_aln_ctl.scala 297:49]
+    node _T_435 = bits(_T_434, 0, 0) @[el2_ifu_aln_ctl.scala 297:72]
     node _T_436 = mux(_T_424, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_437 = mux(_T_427, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_438 = mux(_T_435, sf1val, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2690,37 +2705,37 @@ circuit el2_ifu_aln_ctl :
     node _T_440 = or(_T_439, _T_438) @[Mux.scala 27:72]
     wire _T_441 : UInt @[Mux.scala 27:72]
     _T_441 <= _T_440 @[Mux.scala 27:72]
-    f1val_in <= _T_441 @[el2_ifu_aln_ctl.scala 279:12]
-    node _T_442 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 283:32]
-    node _T_443 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 283:54]
+    f1val_in <= _T_441 @[el2_ifu_aln_ctl.scala 295:12]
+    node _T_442 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 299:32]
+    node _T_443 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 299:54]
     node _T_444 = cat(UInt<1>("h00"), _T_443) @[Cat.scala 29:58]
-    node _T_445 = eq(shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 284:6]
-    node _T_446 = eq(shift_4B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 284:18]
-    node _T_447 = and(_T_445, _T_446) @[el2_ifu_aln_ctl.scala 284:16]
-    node _T_448 = bits(_T_447, 0, 0) @[el2_ifu_aln_ctl.scala 284:29]
+    node _T_445 = eq(shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 300:6]
+    node _T_446 = eq(shift_4B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 300:18]
+    node _T_447 = and(_T_445, _T_446) @[el2_ifu_aln_ctl.scala 300:16]
+    node _T_448 = bits(_T_447, 0, 0) @[el2_ifu_aln_ctl.scala 300:29]
     node _T_449 = mux(_T_442, _T_444, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_450 = mux(_T_448, f1val, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_451 = or(_T_449, _T_450) @[Mux.scala 27:72]
     wire _T_452 : UInt @[Mux.scala 27:72]
     _T_452 <= _T_451 @[Mux.scala 27:72]
-    sf0val <= _T_452 @[el2_ifu_aln_ctl.scala 283:10]
-    node _T_453 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 286:40]
-    node _T_454 = and(fetch_to_f0, _T_453) @[el2_ifu_aln_ctl.scala 286:38]
-    node _T_455 = bits(_T_454, 0, 0) @[el2_ifu_aln_ctl.scala 286:61]
-    node _T_456 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 287:20]
-    node _T_457 = and(shift_f2_f0, _T_456) @[el2_ifu_aln_ctl.scala 287:18]
-    node _T_458 = bits(_T_457, 0, 0) @[el2_ifu_aln_ctl.scala 287:41]
-    node _T_459 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 288:20]
-    node _T_460 = and(shift_f1_f0, _T_459) @[el2_ifu_aln_ctl.scala 288:18]
-    node _T_461 = bits(_T_460, 0, 0) @[el2_ifu_aln_ctl.scala 288:47]
-    node _T_462 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:6]
-    node _T_463 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:21]
-    node _T_464 = and(_T_462, _T_463) @[el2_ifu_aln_ctl.scala 289:19]
-    node _T_465 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:36]
-    node _T_466 = and(_T_464, _T_465) @[el2_ifu_aln_ctl.scala 289:34]
-    node _T_467 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:51]
-    node _T_468 = and(_T_466, _T_467) @[el2_ifu_aln_ctl.scala 289:49]
-    node _T_469 = bits(_T_468, 0, 0) @[el2_ifu_aln_ctl.scala 289:72]
+    sf0val <= _T_452 @[el2_ifu_aln_ctl.scala 299:10]
+    node _T_453 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 302:40]
+    node _T_454 = and(fetch_to_f0, _T_453) @[el2_ifu_aln_ctl.scala 302:38]
+    node _T_455 = bits(_T_454, 0, 0) @[el2_ifu_aln_ctl.scala 302:61]
+    node _T_456 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 303:20]
+    node _T_457 = and(shift_f2_f0, _T_456) @[el2_ifu_aln_ctl.scala 303:18]
+    node _T_458 = bits(_T_457, 0, 0) @[el2_ifu_aln_ctl.scala 303:41]
+    node _T_459 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 304:20]
+    node _T_460 = and(shift_f1_f0, _T_459) @[el2_ifu_aln_ctl.scala 304:18]
+    node _T_461 = bits(_T_460, 0, 0) @[el2_ifu_aln_ctl.scala 304:47]
+    node _T_462 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:6]
+    node _T_463 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:21]
+    node _T_464 = and(_T_462, _T_463) @[el2_ifu_aln_ctl.scala 305:19]
+    node _T_465 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:36]
+    node _T_466 = and(_T_464, _T_465) @[el2_ifu_aln_ctl.scala 305:34]
+    node _T_467 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 305:51]
+    node _T_468 = and(_T_466, _T_467) @[el2_ifu_aln_ctl.scala 305:49]
+    node _T_469 = bits(_T_468, 0, 0) @[el2_ifu_aln_ctl.scala 305:72]
     node _T_470 = mux(_T_455, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_471 = mux(_T_458, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_472 = mux(_T_461, sf1val, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2730,15 +2745,15 @@ circuit el2_ifu_aln_ctl :
     node _T_476 = or(_T_475, _T_473) @[Mux.scala 27:72]
     wire _T_477 : UInt @[Mux.scala 27:72]
     _T_477 <= _T_476 @[Mux.scala 27:72]
-    f0val_in <= _T_477 @[el2_ifu_aln_ctl.scala 286:12]
-    node _T_478 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 291:28]
-    node _T_479 = bits(_T_478, 0, 0) @[el2_ifu_aln_ctl.scala 291:32]
+    f0val_in <= _T_477 @[el2_ifu_aln_ctl.scala 302:12]
+    node _T_478 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 307:28]
+    node _T_479 = bits(_T_478, 0, 0) @[el2_ifu_aln_ctl.scala 307:32]
     node _T_480 = cat(q1, q0) @[Cat.scala 29:58]
-    node _T_481 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 292:9]
-    node _T_482 = bits(_T_481, 0, 0) @[el2_ifu_aln_ctl.scala 292:13]
+    node _T_481 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 308:9]
+    node _T_482 = bits(_T_481, 0, 0) @[el2_ifu_aln_ctl.scala 308:13]
     node _T_483 = cat(q2, q1) @[Cat.scala 29:58]
-    node _T_484 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 293:9]
-    node _T_485 = bits(_T_484, 0, 0) @[el2_ifu_aln_ctl.scala 293:13]
+    node _T_484 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 309:9]
+    node _T_485 = bits(_T_484, 0, 0) @[el2_ifu_aln_ctl.scala 309:13]
     node _T_486 = cat(q0, q2) @[Cat.scala 29:58]
     node _T_487 = mux(_T_479, _T_480, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_488 = mux(_T_482, _T_483, UInt<1>("h00")) @[Mux.scala 27:72]
@@ -2747,261 +2762,261 @@ circuit el2_ifu_aln_ctl :
     node _T_491 = or(_T_490, _T_489) @[Mux.scala 27:72]
     wire qeff : UInt<64> @[Mux.scala 27:72]
     qeff <= _T_491 @[Mux.scala 27:72]
-    node q1eff = bits(qeff, 63, 32) @[el2_ifu_aln_ctl.scala 294:29]
-    node q0eff = bits(qeff, 31, 0) @[el2_ifu_aln_ctl.scala 294:42]
-    node _T_492 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 296:29]
-    node _T_493 = bits(_T_492, 0, 0) @[el2_ifu_aln_ctl.scala 296:33]
-    node _T_494 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 296:53]
-    node _T_495 = bits(_T_494, 0, 0) @[el2_ifu_aln_ctl.scala 296:57]
-    node _T_496 = bits(q0eff, 31, 16) @[el2_ifu_aln_ctl.scala 296:70]
+    node q1eff = bits(qeff, 63, 32) @[el2_ifu_aln_ctl.scala 310:29]
+    node q0eff = bits(qeff, 31, 0) @[el2_ifu_aln_ctl.scala 310:42]
+    node _T_492 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 312:29]
+    node _T_493 = bits(_T_492, 0, 0) @[el2_ifu_aln_ctl.scala 312:33]
+    node _T_494 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 312:53]
+    node _T_495 = bits(_T_494, 0, 0) @[el2_ifu_aln_ctl.scala 312:57]
+    node _T_496 = bits(q0eff, 31, 16) @[el2_ifu_aln_ctl.scala 312:70]
     node _T_497 = mux(_T_493, q0eff, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_498 = mux(_T_495, _T_496, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_499 = or(_T_497, _T_498) @[Mux.scala 27:72]
     wire _T_500 : UInt<32> @[Mux.scala 27:72]
     _T_500 <= _T_499 @[Mux.scala 27:72]
-    q0final <= _T_500 @[el2_ifu_aln_ctl.scala 296:11]
-    node _T_501 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 298:29]
-    node _T_502 = bits(_T_501, 0, 0) @[el2_ifu_aln_ctl.scala 298:33]
-    node _T_503 = bits(q1eff, 15, 0) @[el2_ifu_aln_ctl.scala 298:46]
-    node _T_504 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 298:59]
-    node _T_505 = bits(_T_504, 0, 0) @[el2_ifu_aln_ctl.scala 298:63]
-    node _T_506 = bits(q1eff, 31, 16) @[el2_ifu_aln_ctl.scala 298:76]
+    q0final <= _T_500 @[el2_ifu_aln_ctl.scala 312:11]
+    node _T_501 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 314:29]
+    node _T_502 = bits(_T_501, 0, 0) @[el2_ifu_aln_ctl.scala 314:33]
+    node _T_503 = bits(q1eff, 15, 0) @[el2_ifu_aln_ctl.scala 314:46]
+    node _T_504 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 314:59]
+    node _T_505 = bits(_T_504, 0, 0) @[el2_ifu_aln_ctl.scala 314:63]
+    node _T_506 = bits(q1eff, 31, 16) @[el2_ifu_aln_ctl.scala 314:76]
     node _T_507 = mux(_T_502, _T_503, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_508 = mux(_T_505, _T_506, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_509 = or(_T_507, _T_508) @[Mux.scala 27:72]
     wire _T_510 : UInt<16> @[Mux.scala 27:72]
     _T_510 <= _T_509 @[Mux.scala 27:72]
-    q1final <= _T_510 @[el2_ifu_aln_ctl.scala 298:11]
-    node _T_511 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 300:34]
-    node _T_512 = bits(_T_511, 0, 0) @[el2_ifu_aln_ctl.scala 300:38]
-    node _T_513 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:64]
-    node _T_514 = not(_T_513) @[el2_ifu_aln_ctl.scala 300:58]
-    node _T_515 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 300:75]
-    node _T_516 = and(_T_514, _T_515) @[el2_ifu_aln_ctl.scala 300:68]
-    node _T_517 = bits(_T_516, 0, 0) @[el2_ifu_aln_ctl.scala 300:80]
+    q1final <= _T_510 @[el2_ifu_aln_ctl.scala 314:11]
+    node _T_511 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 316:34]
+    node _T_512 = bits(_T_511, 0, 0) @[el2_ifu_aln_ctl.scala 316:38]
+    node _T_513 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 316:64]
+    node _T_514 = not(_T_513) @[el2_ifu_aln_ctl.scala 316:58]
+    node _T_515 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 316:75]
+    node _T_516 = and(_T_514, _T_515) @[el2_ifu_aln_ctl.scala 316:68]
+    node _T_517 = bits(_T_516, 0, 0) @[el2_ifu_aln_ctl.scala 316:80]
     node _T_518 = cat(q1final, q0final) @[Cat.scala 29:58]
     node _T_519 = mux(_T_512, q0final, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_520 = mux(_T_517, _T_518, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_521 = or(_T_519, _T_520) @[Mux.scala 27:72]
     wire aligndata : UInt<48> @[Mux.scala 27:72]
     aligndata <= _T_521 @[Mux.scala 27:72]
-    node _T_522 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:30]
-    node _T_523 = bits(_T_522, 0, 0) @[el2_ifu_aln_ctl.scala 302:34]
-    node _T_524 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:54]
-    node _T_525 = eq(_T_524, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 302:48]
-    node _T_526 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 302:65]
-    node _T_527 = and(_T_525, _T_526) @[el2_ifu_aln_ctl.scala 302:58]
-    node _T_528 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 302:82]
+    node _T_522 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:30]
+    node _T_523 = bits(_T_522, 0, 0) @[el2_ifu_aln_ctl.scala 318:34]
+    node _T_524 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:54]
+    node _T_525 = eq(_T_524, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 318:48]
+    node _T_526 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 318:65]
+    node _T_527 = and(_T_525, _T_526) @[el2_ifu_aln_ctl.scala 318:58]
+    node _T_528 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 318:82]
     node _T_529 = cat(_T_528, UInt<1>("h01")) @[Cat.scala 29:58]
     node _T_530 = mux(_T_523, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_531 = mux(_T_527, _T_529, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_532 = or(_T_530, _T_531) @[Mux.scala 27:72]
     wire _T_533 : UInt<2> @[Mux.scala 27:72]
     _T_533 <= _T_532 @[Mux.scala 27:72]
-    alignval <= _T_533 @[el2_ifu_aln_ctl.scala 302:12]
-    node _T_534 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:34]
-    node _T_535 = bits(_T_534, 0, 0) @[el2_ifu_aln_ctl.scala 304:38]
-    node _T_536 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:63]
-    node _T_537 = not(_T_536) @[el2_ifu_aln_ctl.scala 304:57]
-    node _T_538 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 304:74]
-    node _T_539 = and(_T_537, _T_538) @[el2_ifu_aln_ctl.scala 304:67]
-    node _T_540 = bits(_T_539, 0, 0) @[el2_ifu_aln_ctl.scala 304:79]
+    alignval <= _T_533 @[el2_ifu_aln_ctl.scala 318:12]
+    node _T_534 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 320:34]
+    node _T_535 = bits(_T_534, 0, 0) @[el2_ifu_aln_ctl.scala 320:38]
+    node _T_536 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 320:63]
+    node _T_537 = not(_T_536) @[el2_ifu_aln_ctl.scala 320:57]
+    node _T_538 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 320:74]
+    node _T_539 = and(_T_537, _T_538) @[el2_ifu_aln_ctl.scala 320:67]
+    node _T_540 = bits(_T_539, 0, 0) @[el2_ifu_aln_ctl.scala 320:79]
     node _T_541 = cat(f1icaf, f0icaf) @[Cat.scala 29:58]
     node _T_542 = mux(_T_535, f0icaf, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_543 = mux(_T_540, _T_541, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_544 = or(_T_542, _T_543) @[Mux.scala 27:72]
     wire alignicaf : UInt<2> @[Mux.scala 27:72]
     alignicaf <= _T_544 @[Mux.scala 27:72]
-    node _T_545 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:35]
-    node _T_546 = bits(_T_545, 0, 0) @[el2_ifu_aln_ctl.scala 306:39]
+    node _T_545 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 322:35]
+    node _T_546 = bits(_T_545, 0, 0) @[el2_ifu_aln_ctl.scala 322:39]
     node _T_547 = bits(f0dbecc, 0, 0) @[Bitwise.scala 72:15]
     node _T_548 = mux(_T_547, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_549 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:73]
-    node _T_550 = eq(_T_549, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 306:67]
-    node _T_551 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 306:84]
-    node _T_552 = and(_T_550, _T_551) @[el2_ifu_aln_ctl.scala 306:77]
-    node _T_553 = bits(_T_552, 0, 0) @[el2_ifu_aln_ctl.scala 306:89]
+    node _T_549 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 322:73]
+    node _T_550 = eq(_T_549, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 322:67]
+    node _T_551 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 322:84]
+    node _T_552 = and(_T_550, _T_551) @[el2_ifu_aln_ctl.scala 322:77]
+    node _T_553 = bits(_T_552, 0, 0) @[el2_ifu_aln_ctl.scala 322:89]
     node _T_554 = cat(f1dbecc, f0dbecc) @[Cat.scala 29:58]
     node _T_555 = mux(_T_546, _T_548, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_556 = mux(_T_553, _T_554, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_557 = or(_T_555, _T_556) @[Mux.scala 27:72]
     wire aligndbecc : UInt<2> @[Mux.scala 27:72]
     aligndbecc <= _T_557 @[Mux.scala 27:72]
-    node _T_558 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:35]
-    node _T_559 = bits(_T_558, 0, 0) @[el2_ifu_aln_ctl.scala 308:45]
-    node _T_560 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:65]
-    node _T_561 = eq(_T_560, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 308:59]
-    node _T_562 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 308:76]
-    node _T_563 = and(_T_561, _T_562) @[el2_ifu_aln_ctl.scala 308:69]
-    node _T_564 = bits(_T_563, 0, 0) @[el2_ifu_aln_ctl.scala 308:81]
-    node _T_565 = bits(f1brend, 0, 0) @[el2_ifu_aln_ctl.scala 308:100]
-    node _T_566 = bits(f0brend, 0, 0) @[el2_ifu_aln_ctl.scala 308:111]
+    node _T_558 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 324:35]
+    node _T_559 = bits(_T_558, 0, 0) @[el2_ifu_aln_ctl.scala 324:45]
+    node _T_560 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 324:65]
+    node _T_561 = eq(_T_560, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:59]
+    node _T_562 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 324:76]
+    node _T_563 = and(_T_561, _T_562) @[el2_ifu_aln_ctl.scala 324:69]
+    node _T_564 = bits(_T_563, 0, 0) @[el2_ifu_aln_ctl.scala 324:81]
+    node _T_565 = bits(f1brend, 0, 0) @[el2_ifu_aln_ctl.scala 324:100]
+    node _T_566 = bits(f0brend, 0, 0) @[el2_ifu_aln_ctl.scala 324:111]
     node _T_567 = cat(_T_565, _T_566) @[Cat.scala 29:58]
     node _T_568 = mux(_T_559, f0brend, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_569 = mux(_T_564, _T_567, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_570 = or(_T_568, _T_569) @[Mux.scala 27:72]
     wire alignbrend : UInt<2> @[Mux.scala 27:72]
     alignbrend <= _T_570 @[Mux.scala 27:72]
-    node _T_571 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:33]
-    node _T_572 = bits(_T_571, 0, 0) @[el2_ifu_aln_ctl.scala 310:43]
-    node _T_573 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:61]
-    node _T_574 = eq(_T_573, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 310:55]
-    node _T_575 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 310:72]
-    node _T_576 = and(_T_574, _T_575) @[el2_ifu_aln_ctl.scala 310:65]
-    node _T_577 = bits(_T_576, 0, 0) @[el2_ifu_aln_ctl.scala 310:77]
-    node _T_578 = bits(f1pc4, 0, 0) @[el2_ifu_aln_ctl.scala 310:94]
-    node _T_579 = bits(f0pc4, 0, 0) @[el2_ifu_aln_ctl.scala 310:103]
+    node _T_571 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 326:33]
+    node _T_572 = bits(_T_571, 0, 0) @[el2_ifu_aln_ctl.scala 326:43]
+    node _T_573 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 326:61]
+    node _T_574 = eq(_T_573, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 326:55]
+    node _T_575 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 326:72]
+    node _T_576 = and(_T_574, _T_575) @[el2_ifu_aln_ctl.scala 326:65]
+    node _T_577 = bits(_T_576, 0, 0) @[el2_ifu_aln_ctl.scala 326:77]
+    node _T_578 = bits(f1pc4, 0, 0) @[el2_ifu_aln_ctl.scala 326:94]
+    node _T_579 = bits(f0pc4, 0, 0) @[el2_ifu_aln_ctl.scala 326:103]
     node _T_580 = cat(_T_578, _T_579) @[Cat.scala 29:58]
     node _T_581 = mux(_T_572, f0pc4, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_582 = mux(_T_577, _T_580, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_583 = or(_T_581, _T_582) @[Mux.scala 27:72]
     wire alignpc4 : UInt<2> @[Mux.scala 27:72]
     alignpc4 <= _T_583 @[Mux.scala 27:72]
-    node _T_584 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:33]
-    node _T_585 = bits(_T_584, 0, 0) @[el2_ifu_aln_ctl.scala 312:43]
-    node _T_586 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:61]
-    node _T_587 = eq(_T_586, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 312:55]
-    node _T_588 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 312:72]
-    node _T_589 = and(_T_587, _T_588) @[el2_ifu_aln_ctl.scala 312:65]
-    node _T_590 = bits(_T_589, 0, 0) @[el2_ifu_aln_ctl.scala 312:77]
-    node _T_591 = bits(f1ret, 0, 0) @[el2_ifu_aln_ctl.scala 312:94]
-    node _T_592 = bits(f0ret, 0, 0) @[el2_ifu_aln_ctl.scala 312:103]
+    node _T_584 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 328:33]
+    node _T_585 = bits(_T_584, 0, 0) @[el2_ifu_aln_ctl.scala 328:43]
+    node _T_586 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 328:61]
+    node _T_587 = eq(_T_586, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 328:55]
+    node _T_588 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 328:72]
+    node _T_589 = and(_T_587, _T_588) @[el2_ifu_aln_ctl.scala 328:65]
+    node _T_590 = bits(_T_589, 0, 0) @[el2_ifu_aln_ctl.scala 328:77]
+    node _T_591 = bits(f1ret, 0, 0) @[el2_ifu_aln_ctl.scala 328:94]
+    node _T_592 = bits(f0ret, 0, 0) @[el2_ifu_aln_ctl.scala 328:103]
     node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58]
     node _T_594 = mux(_T_585, f0ret, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_595 = mux(_T_590, _T_593, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_596 = or(_T_594, _T_595) @[Mux.scala 27:72]
     wire alignret : UInt<2> @[Mux.scala 27:72]
     alignret <= _T_596 @[Mux.scala 27:72]
-    node _T_597 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 314:33]
-    node _T_598 = bits(_T_597, 0, 0) @[el2_ifu_aln_ctl.scala 314:43]
-    node _T_599 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 314:61]
-    node _T_600 = eq(_T_599, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 314:55]
-    node _T_601 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 314:72]
-    node _T_602 = and(_T_600, _T_601) @[el2_ifu_aln_ctl.scala 314:65]
-    node _T_603 = bits(_T_602, 0, 0) @[el2_ifu_aln_ctl.scala 314:77]
-    node _T_604 = bits(f1way, 0, 0) @[el2_ifu_aln_ctl.scala 314:94]
-    node _T_605 = bits(f0way, 0, 0) @[el2_ifu_aln_ctl.scala 314:103]
+    node _T_597 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 330:33]
+    node _T_598 = bits(_T_597, 0, 0) @[el2_ifu_aln_ctl.scala 330:43]
+    node _T_599 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 330:61]
+    node _T_600 = eq(_T_599, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 330:55]
+    node _T_601 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 330:72]
+    node _T_602 = and(_T_600, _T_601) @[el2_ifu_aln_ctl.scala 330:65]
+    node _T_603 = bits(_T_602, 0, 0) @[el2_ifu_aln_ctl.scala 330:77]
+    node _T_604 = bits(f1way, 0, 0) @[el2_ifu_aln_ctl.scala 330:94]
+    node _T_605 = bits(f0way, 0, 0) @[el2_ifu_aln_ctl.scala 330:103]
     node _T_606 = cat(_T_604, _T_605) @[Cat.scala 29:58]
     node _T_607 = mux(_T_598, f0way, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_608 = mux(_T_603, _T_606, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_609 = or(_T_607, _T_608) @[Mux.scala 27:72]
     wire alignway : UInt<2> @[Mux.scala 27:72]
     alignway <= _T_609 @[Mux.scala 27:72]
-    node _T_610 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 316:35]
-    node _T_611 = bits(_T_610, 0, 0) @[el2_ifu_aln_ctl.scala 316:45]
-    node _T_612 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 316:65]
-    node _T_613 = eq(_T_612, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 316:59]
-    node _T_614 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 316:76]
-    node _T_615 = and(_T_613, _T_614) @[el2_ifu_aln_ctl.scala 316:69]
-    node _T_616 = bits(_T_615, 0, 0) @[el2_ifu_aln_ctl.scala 316:81]
-    node _T_617 = bits(f1hist1, 0, 0) @[el2_ifu_aln_ctl.scala 316:100]
-    node _T_618 = bits(f0hist1, 0, 0) @[el2_ifu_aln_ctl.scala 316:111]
+    node _T_610 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 332:35]
+    node _T_611 = bits(_T_610, 0, 0) @[el2_ifu_aln_ctl.scala 332:45]
+    node _T_612 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 332:65]
+    node _T_613 = eq(_T_612, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 332:59]
+    node _T_614 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 332:76]
+    node _T_615 = and(_T_613, _T_614) @[el2_ifu_aln_ctl.scala 332:69]
+    node _T_616 = bits(_T_615, 0, 0) @[el2_ifu_aln_ctl.scala 332:81]
+    node _T_617 = bits(f1hist1, 0, 0) @[el2_ifu_aln_ctl.scala 332:100]
+    node _T_618 = bits(f0hist1, 0, 0) @[el2_ifu_aln_ctl.scala 332:111]
     node _T_619 = cat(_T_617, _T_618) @[Cat.scala 29:58]
     node _T_620 = mux(_T_611, f0hist1, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_621 = mux(_T_616, _T_619, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_622 = or(_T_620, _T_621) @[Mux.scala 27:72]
     wire alignhist1 : UInt<2> @[Mux.scala 27:72]
     alignhist1 <= _T_622 @[Mux.scala 27:72]
-    node _T_623 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:35]
-    node _T_624 = bits(_T_623, 0, 0) @[el2_ifu_aln_ctl.scala 318:45]
-    node _T_625 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:65]
-    node _T_626 = eq(_T_625, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 318:59]
-    node _T_627 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 318:76]
-    node _T_628 = and(_T_626, _T_627) @[el2_ifu_aln_ctl.scala 318:69]
-    node _T_629 = bits(_T_628, 0, 0) @[el2_ifu_aln_ctl.scala 318:81]
-    node _T_630 = bits(f1hist0, 0, 0) @[el2_ifu_aln_ctl.scala 318:100]
-    node _T_631 = bits(f0hist0, 0, 0) @[el2_ifu_aln_ctl.scala 318:111]
+    node _T_623 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 334:35]
+    node _T_624 = bits(_T_623, 0, 0) @[el2_ifu_aln_ctl.scala 334:45]
+    node _T_625 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 334:65]
+    node _T_626 = eq(_T_625, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 334:59]
+    node _T_627 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 334:76]
+    node _T_628 = and(_T_626, _T_627) @[el2_ifu_aln_ctl.scala 334:69]
+    node _T_629 = bits(_T_628, 0, 0) @[el2_ifu_aln_ctl.scala 334:81]
+    node _T_630 = bits(f1hist0, 0, 0) @[el2_ifu_aln_ctl.scala 334:100]
+    node _T_631 = bits(f0hist0, 0, 0) @[el2_ifu_aln_ctl.scala 334:111]
     node _T_632 = cat(_T_630, _T_631) @[Cat.scala 29:58]
     node _T_633 = mux(_T_624, f0hist0, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_634 = mux(_T_629, _T_632, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_635 = or(_T_633, _T_634) @[Mux.scala 27:72]
     wire alignhist0 : UInt<2> @[Mux.scala 27:72]
     alignhist0 <= _T_635 @[Mux.scala 27:72]
-    node _T_636 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 320:27]
-    node _T_637 = eq(_T_636, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 320:21]
-    node _T_638 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 320:38]
-    node alignfromf1 = and(_T_637, _T_638) @[el2_ifu_aln_ctl.scala 320:31]
-    node _T_639 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 322:33]
-    node _T_640 = bits(_T_639, 0, 0) @[el2_ifu_aln_ctl.scala 322:43]
-    node _T_641 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 322:67]
-    node _T_642 = eq(_T_641, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 322:61]
-    node _T_643 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 322:78]
-    node _T_644 = and(_T_642, _T_643) @[el2_ifu_aln_ctl.scala 322:71]
-    node _T_645 = bits(_T_644, 0, 0) @[el2_ifu_aln_ctl.scala 322:83]
+    node _T_636 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 336:27]
+    node _T_637 = eq(_T_636, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 336:21]
+    node _T_638 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 336:38]
+    node alignfromf1 = and(_T_637, _T_638) @[el2_ifu_aln_ctl.scala 336:31]
+    node _T_639 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 338:33]
+    node _T_640 = bits(_T_639, 0, 0) @[el2_ifu_aln_ctl.scala 338:43]
+    node _T_641 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 338:67]
+    node _T_642 = eq(_T_641, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 338:61]
+    node _T_643 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 338:78]
+    node _T_644 = and(_T_642, _T_643) @[el2_ifu_aln_ctl.scala 338:71]
+    node _T_645 = bits(_T_644, 0, 0) @[el2_ifu_aln_ctl.scala 338:83]
     node _T_646 = mux(_T_640, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_647 = mux(_T_645, f1pc, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_648 = or(_T_646, _T_647) @[Mux.scala 27:72]
     wire secondpc : UInt @[Mux.scala 27:72]
     secondpc <= _T_648 @[Mux.scala 27:72]
-    io.ifu_i0_pc <= f0pc @[el2_ifu_aln_ctl.scala 324:16]
-    io.ifu_i0_pc4 <= first4B @[el2_ifu_aln_ctl.scala 328:17]
-    node _T_649 = bits(aligndata, 15, 0) @[el2_ifu_aln_ctl.scala 330:31]
-    io.ifu_i0_cinst <= _T_649 @[el2_ifu_aln_ctl.scala 330:19]
-    node _T_650 = bits(aligndata, 1, 0) @[el2_ifu_aln_ctl.scala 332:23]
-    node _T_651 = eq(_T_650, UInt<2>("h03")) @[el2_ifu_aln_ctl.scala 332:29]
-    first4B <= _T_651 @[el2_ifu_aln_ctl.scala 332:11]
-    node first2B = not(first4B) @[el2_ifu_aln_ctl.scala 334:17]
-    node _T_652 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 336:40]
-    node _T_653 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 336:58]
-    node _T_654 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 336:71]
-    node _T_655 = bits(alignval, 0, 0) @[el2_ifu_aln_ctl.scala 336:89]
+    io.ifu_i0_pc <= f0pc @[el2_ifu_aln_ctl.scala 340:16]
+    io.ifu_i0_pc4 <= first4B @[el2_ifu_aln_ctl.scala 344:17]
+    node _T_649 = bits(aligndata, 15, 0) @[el2_ifu_aln_ctl.scala 346:31]
+    io.ifu_i0_cinst <= _T_649 @[el2_ifu_aln_ctl.scala 346:19]
+    node _T_650 = bits(aligndata, 1, 0) @[el2_ifu_aln_ctl.scala 348:23]
+    node _T_651 = eq(_T_650, UInt<2>("h03")) @[el2_ifu_aln_ctl.scala 348:29]
+    first4B <= _T_651 @[el2_ifu_aln_ctl.scala 348:11]
+    node first2B = not(first4B) @[el2_ifu_aln_ctl.scala 350:17]
+    node _T_652 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 352:40]
+    node _T_653 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 352:58]
+    node _T_654 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 352:71]
+    node _T_655 = bits(alignval, 0, 0) @[el2_ifu_aln_ctl.scala 352:89]
     node _T_656 = mux(_T_652, _T_653, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_657 = mux(_T_654, _T_655, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_658 = or(_T_656, _T_657) @[Mux.scala 27:72]
     wire _T_659 : UInt<1> @[Mux.scala 27:72]
     _T_659 <= _T_658 @[Mux.scala 27:72]
-    io.ifu_i0_valid <= _T_659 @[el2_ifu_aln_ctl.scala 336:19]
-    node _T_660 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 338:39]
-    node _T_661 = orr(alignicaf) @[el2_ifu_aln_ctl.scala 338:59]
-    node _T_662 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 338:72]
-    node _T_663 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 338:91]
+    io.ifu_i0_valid <= _T_659 @[el2_ifu_aln_ctl.scala 352:19]
+    node _T_660 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 354:39]
+    node _T_661 = orr(alignicaf) @[el2_ifu_aln_ctl.scala 354:59]
+    node _T_662 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 354:72]
+    node _T_663 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 354:91]
     node _T_664 = mux(_T_660, _T_661, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_665 = mux(_T_662, _T_663, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_666 = or(_T_664, _T_665) @[Mux.scala 27:72]
     wire _T_667 : UInt<1> @[Mux.scala 27:72]
     _T_667 <= _T_666 @[Mux.scala 27:72]
-    io.ifu_i0_icaf <= _T_667 @[el2_ifu_aln_ctl.scala 338:18]
-    node _T_668 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 340:47]
-    node _T_669 = eq(_T_668, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 340:41]
-    node _T_670 = and(first4B, _T_669) @[el2_ifu_aln_ctl.scala 340:39]
-    node _T_671 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 340:58]
-    node _T_672 = and(_T_670, _T_671) @[el2_ifu_aln_ctl.scala 340:51]
-    node _T_673 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 340:74]
-    node _T_674 = eq(_T_673, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 340:64]
-    node _T_675 = and(_T_672, _T_674) @[el2_ifu_aln_ctl.scala 340:62]
-    node _T_676 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 340:91]
-    node _T_677 = eq(_T_676, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 340:80]
-    node _T_678 = and(_T_675, _T_677) @[el2_ifu_aln_ctl.scala 340:78]
-    node _T_679 = bits(_T_678, 0, 0) @[el2_ifu_aln_ctl.scala 340:96]
-    node _T_680 = mux(_T_679, f1ictype, f0ictype) @[el2_ifu_aln_ctl.scala 340:29]
-    io.ifu_i0_icaf_type <= _T_680 @[el2_ifu_aln_ctl.scala 340:23]
-    node _T_681 = bits(alignicaf, 1, 1) @[el2_ifu_aln_ctl.scala 342:27]
-    node _T_682 = bits(aligndbecc, 1, 1) @[el2_ifu_aln_ctl.scala 342:43]
-    node icaf_eff = or(_T_681, _T_682) @[el2_ifu_aln_ctl.scala 342:31]
-    node _T_683 = and(first4B, icaf_eff) @[el2_ifu_aln_ctl.scala 344:32]
-    node _T_684 = and(_T_683, alignfromf1) @[el2_ifu_aln_ctl.scala 344:43]
-    io.ifu_i0_icaf_f1 <= _T_684 @[el2_ifu_aln_ctl.scala 344:21]
-    node _T_685 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 346:40]
-    node _T_686 = orr(aligndbecc) @[el2_ifu_aln_ctl.scala 346:59]
-    node _T_687 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 346:72]
-    node _T_688 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 346:90]
+    io.ifu_i0_icaf <= _T_667 @[el2_ifu_aln_ctl.scala 354:18]
+    node _T_668 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 356:47]
+    node _T_669 = eq(_T_668, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 356:41]
+    node _T_670 = and(first4B, _T_669) @[el2_ifu_aln_ctl.scala 356:39]
+    node _T_671 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 356:58]
+    node _T_672 = and(_T_670, _T_671) @[el2_ifu_aln_ctl.scala 356:51]
+    node _T_673 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 356:74]
+    node _T_674 = eq(_T_673, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 356:64]
+    node _T_675 = and(_T_672, _T_674) @[el2_ifu_aln_ctl.scala 356:62]
+    node _T_676 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 356:91]
+    node _T_677 = eq(_T_676, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 356:80]
+    node _T_678 = and(_T_675, _T_677) @[el2_ifu_aln_ctl.scala 356:78]
+    node _T_679 = bits(_T_678, 0, 0) @[el2_ifu_aln_ctl.scala 356:96]
+    node _T_680 = mux(_T_679, f1ictype, f0ictype) @[el2_ifu_aln_ctl.scala 356:29]
+    io.ifu_i0_icaf_type <= _T_680 @[el2_ifu_aln_ctl.scala 356:23]
+    node _T_681 = bits(alignicaf, 1, 1) @[el2_ifu_aln_ctl.scala 358:27]
+    node _T_682 = bits(aligndbecc, 1, 1) @[el2_ifu_aln_ctl.scala 358:43]
+    node icaf_eff = or(_T_681, _T_682) @[el2_ifu_aln_ctl.scala 358:31]
+    node _T_683 = and(first4B, icaf_eff) @[el2_ifu_aln_ctl.scala 360:32]
+    node _T_684 = and(_T_683, alignfromf1) @[el2_ifu_aln_ctl.scala 360:43]
+    io.ifu_i0_icaf_f1 <= _T_684 @[el2_ifu_aln_ctl.scala 360:21]
+    node _T_685 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 362:40]
+    node _T_686 = orr(aligndbecc) @[el2_ifu_aln_ctl.scala 362:59]
+    node _T_687 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 362:72]
+    node _T_688 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 362:90]
     node _T_689 = mux(_T_685, _T_686, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_690 = mux(_T_687, _T_688, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_691 = or(_T_689, _T_690) @[Mux.scala 27:72]
     wire _T_692 : UInt<1> @[Mux.scala 27:72]
     _T_692 <= _T_691 @[Mux.scala 27:72]
-    io.ifu_i0_dbecc <= _T_692 @[el2_ifu_aln_ctl.scala 346:19]
-    inst decompressed of el2_ifu_compress_ctl @[el2_ifu_aln_ctl.scala 350:28]
+    io.ifu_i0_dbecc <= _T_692 @[el2_ifu_aln_ctl.scala 362:19]
+    inst decompressed of el2_ifu_compress_ctl @[el2_ifu_aln_ctl.scala 366:28]
     decompressed.clock <= clock
     decompressed.reset <= reset
-    node _T_693 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 352:40]
-    node _T_694 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 352:66]
+    node _T_693 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 368:40]
+    node _T_694 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 368:66]
     node _T_695 = mux(_T_693, aligndata, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_696 = mux(_T_694, decompressed.io.dout, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_697 = or(_T_695, _T_696) @[Mux.scala 27:72]
     wire _T_698 : UInt<48> @[Mux.scala 27:72]
     _T_698 <= _T_697 @[Mux.scala 27:72]
-    io.ifu_i0_instr <= _T_698 @[el2_ifu_aln_ctl.scala 352:19]
+    io.ifu_i0_instr <= _T_698 @[el2_ifu_aln_ctl.scala 368:19]
     node _T_699 = bits(f0pc, 8, 1) @[el2_lib.scala 191:12]
     node _T_700 = bits(f0pc, 16, 9) @[el2_lib.scala 191:50]
     node _T_701 = xor(_T_699, _T_700) @[el2_lib.scala 191:46]
@@ -3030,112 +3045,112 @@ circuit el2_ifu_aln_ctl :
     _T_715[2] <= _T_714 @[el2_lib.scala 182:24]
     node _T_716 = xor(_T_715[0], _T_715[1]) @[el2_lib.scala 182:111]
     node secondbrtag_hash = xor(_T_716, _T_715[2]) @[el2_lib.scala 182:111]
-    node _T_717 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 362:42]
-    node _T_718 = and(first2B, _T_717) @[el2_ifu_aln_ctl.scala 362:30]
-    node _T_719 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 362:70]
-    node _T_720 = and(first4B, _T_719) @[el2_ifu_aln_ctl.scala 362:58]
-    node _T_721 = or(_T_718, _T_720) @[el2_ifu_aln_ctl.scala 362:47]
-    node _T_722 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 362:96]
-    node _T_723 = and(first4B, _T_722) @[el2_ifu_aln_ctl.scala 362:86]
-    node _T_724 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 362:112]
-    node _T_725 = and(_T_723, _T_724) @[el2_ifu_aln_ctl.scala 362:100]
-    node _T_726 = or(_T_721, _T_725) @[el2_ifu_aln_ctl.scala 362:75]
-    io.i0_brp.valid <= _T_726 @[el2_ifu_aln_ctl.scala 362:19]
-    node _T_727 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 364:39]
-    node _T_728 = and(first2B, _T_727) @[el2_ifu_aln_ctl.scala 364:29]
-    node _T_729 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 364:65]
-    node _T_730 = and(first4B, _T_729) @[el2_ifu_aln_ctl.scala 364:55]
-    node _T_731 = or(_T_728, _T_730) @[el2_ifu_aln_ctl.scala 364:44]
-    io.i0_brp.ret <= _T_731 @[el2_ifu_aln_ctl.scala 364:17]
-    node _T_732 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 366:39]
-    node _T_733 = and(first2B, _T_732) @[el2_ifu_aln_ctl.scala 366:29]
-    node _T_734 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 366:65]
-    node _T_735 = and(first4B, _T_734) @[el2_ifu_aln_ctl.scala 366:55]
-    node i0_brp_pc4 = or(_T_733, _T_735) @[el2_ifu_aln_ctl.scala 366:44]
-    node _T_736 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 368:45]
-    node _T_737 = or(first2B, _T_736) @[el2_ifu_aln_ctl.scala 368:33]
-    node _T_738 = bits(_T_737, 0, 0) @[el2_ifu_aln_ctl.scala 368:50]
-    node _T_739 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 368:66]
-    node _T_740 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 368:80]
-    node _T_741 = mux(_T_738, _T_739, _T_740) @[el2_ifu_aln_ctl.scala 368:23]
-    io.i0_brp.way <= _T_741 @[el2_ifu_aln_ctl.scala 368:17]
-    node _T_742 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 370:46]
-    node _T_743 = and(first2B, _T_742) @[el2_ifu_aln_ctl.scala 370:34]
-    node _T_744 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 370:74]
-    node _T_745 = and(first4B, _T_744) @[el2_ifu_aln_ctl.scala 370:62]
-    node _T_746 = or(_T_743, _T_745) @[el2_ifu_aln_ctl.scala 370:51]
-    node _T_747 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 371:26]
-    node _T_748 = and(first2B, _T_747) @[el2_ifu_aln_ctl.scala 371:14]
-    node _T_749 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 371:54]
-    node _T_750 = and(first4B, _T_749) @[el2_ifu_aln_ctl.scala 371:42]
-    node _T_751 = or(_T_748, _T_750) @[el2_ifu_aln_ctl.scala 371:31]
+    node _T_717 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 378:42]
+    node _T_718 = and(first2B, _T_717) @[el2_ifu_aln_ctl.scala 378:30]
+    node _T_719 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 378:70]
+    node _T_720 = and(first4B, _T_719) @[el2_ifu_aln_ctl.scala 378:58]
+    node _T_721 = or(_T_718, _T_720) @[el2_ifu_aln_ctl.scala 378:47]
+    node _T_722 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 378:96]
+    node _T_723 = and(first4B, _T_722) @[el2_ifu_aln_ctl.scala 378:86]
+    node _T_724 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 378:112]
+    node _T_725 = and(_T_723, _T_724) @[el2_ifu_aln_ctl.scala 378:100]
+    node _T_726 = or(_T_721, _T_725) @[el2_ifu_aln_ctl.scala 378:75]
+    io.i0_brp.valid <= _T_726 @[el2_ifu_aln_ctl.scala 378:19]
+    node _T_727 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:39]
+    node _T_728 = and(first2B, _T_727) @[el2_ifu_aln_ctl.scala 380:29]
+    node _T_729 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:65]
+    node _T_730 = and(first4B, _T_729) @[el2_ifu_aln_ctl.scala 380:55]
+    node _T_731 = or(_T_728, _T_730) @[el2_ifu_aln_ctl.scala 380:44]
+    io.i0_brp.ret <= _T_731 @[el2_ifu_aln_ctl.scala 380:17]
+    node _T_732 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 382:39]
+    node _T_733 = and(first2B, _T_732) @[el2_ifu_aln_ctl.scala 382:29]
+    node _T_734 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 382:65]
+    node _T_735 = and(first4B, _T_734) @[el2_ifu_aln_ctl.scala 382:55]
+    node i0_brp_pc4 = or(_T_733, _T_735) @[el2_ifu_aln_ctl.scala 382:44]
+    node _T_736 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:45]
+    node _T_737 = or(first2B, _T_736) @[el2_ifu_aln_ctl.scala 384:33]
+    node _T_738 = bits(_T_737, 0, 0) @[el2_ifu_aln_ctl.scala 384:50]
+    node _T_739 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:66]
+    node _T_740 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:80]
+    node _T_741 = mux(_T_738, _T_739, _T_740) @[el2_ifu_aln_ctl.scala 384:23]
+    io.i0_brp.way <= _T_741 @[el2_ifu_aln_ctl.scala 384:17]
+    node _T_742 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:46]
+    node _T_743 = and(first2B, _T_742) @[el2_ifu_aln_ctl.scala 386:34]
+    node _T_744 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:74]
+    node _T_745 = and(first4B, _T_744) @[el2_ifu_aln_ctl.scala 386:62]
+    node _T_746 = or(_T_743, _T_745) @[el2_ifu_aln_ctl.scala 386:51]
+    node _T_747 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 387:26]
+    node _T_748 = and(first2B, _T_747) @[el2_ifu_aln_ctl.scala 387:14]
+    node _T_749 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 387:54]
+    node _T_750 = and(first4B, _T_749) @[el2_ifu_aln_ctl.scala 387:42]
+    node _T_751 = or(_T_748, _T_750) @[el2_ifu_aln_ctl.scala 387:31]
     node _T_752 = cat(_T_746, _T_751) @[Cat.scala 29:58]
-    io.i0_brp.hist <= _T_752 @[el2_ifu_aln_ctl.scala 370:18]
-    node i0_ends_f1 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 373:28]
-    node _T_753 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 374:39]
-    node _T_754 = mux(_T_753, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 374:27]
-    io.i0_brp.toffset <= _T_754 @[el2_ifu_aln_ctl.scala 374:21]
-    node _T_755 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 376:37]
-    node _T_756 = mux(_T_755, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 376:25]
-    io.i0_brp.prett <= _T_756 @[el2_ifu_aln_ctl.scala 376:19]
-    node _T_757 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 378:51]
-    node _T_758 = and(first4B, _T_757) @[el2_ifu_aln_ctl.scala 378:41]
-    node _T_759 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 378:67]
-    node _T_760 = and(_T_758, _T_759) @[el2_ifu_aln_ctl.scala 378:55]
-    io.i0_brp.br_start_error <= _T_760 @[el2_ifu_aln_ctl.scala 378:29]
-    node _T_761 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 380:57]
-    node _T_762 = or(first2B, _T_761) @[el2_ifu_aln_ctl.scala 380:45]
-    node _T_763 = bits(_T_762, 0, 0) @[el2_ifu_aln_ctl.scala 380:62]
-    node _T_764 = bits(f0pc, 1, 1) @[el2_ifu_aln_ctl.scala 380:77]
-    node _T_765 = bits(secondpc, 1, 1) @[el2_ifu_aln_ctl.scala 380:90]
-    node _T_766 = mux(_T_763, _T_764, _T_765) @[el2_ifu_aln_ctl.scala 380:35]
-    io.i0_brp.bank <= _T_766 @[el2_ifu_aln_ctl.scala 380:29]
-    node _T_767 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 382:42]
-    node _T_768 = and(_T_767, first2B) @[el2_ifu_aln_ctl.scala 382:56]
-    node _T_769 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 382:89]
-    node _T_770 = and(io.i0_brp.valid, _T_769) @[el2_ifu_aln_ctl.scala 382:87]
-    node _T_771 = and(_T_770, first4B) @[el2_ifu_aln_ctl.scala 382:101]
-    node _T_772 = or(_T_768, _T_771) @[el2_ifu_aln_ctl.scala 382:68]
-    io.i0_brp.br_error <= _T_772 @[el2_ifu_aln_ctl.scala 382:22]
-    node _T_773 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:50]
-    node _T_774 = or(first2B, _T_773) @[el2_ifu_aln_ctl.scala 384:38]
-    node _T_775 = bits(_T_774, 0, 0) @[el2_ifu_aln_ctl.scala 384:55]
-    node _T_776 = mux(_T_775, firstpc_hash, secondpc_hash) @[el2_ifu_aln_ctl.scala 384:28]
-    io.ifu_i0_bp_index <= _T_776 @[el2_ifu_aln_ctl.scala 384:22]
-    node _T_777 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 386:37]
-    node _T_778 = bits(_T_777, 0, 0) @[el2_ifu_aln_ctl.scala 386:52]
-    node _T_779 = mux(_T_778, f1fghr, f0fghr) @[el2_ifu_aln_ctl.scala 386:27]
-    io.ifu_i0_bp_fghr <= _T_779 @[el2_ifu_aln_ctl.scala 386:21]
-    node _T_780 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 388:49]
-    node _T_781 = or(first2B, _T_780) @[el2_ifu_aln_ctl.scala 388:37]
-    node _T_782 = bits(_T_781, 0, 0) @[el2_ifu_aln_ctl.scala 388:54]
-    node _T_783 = mux(_T_782, firstbrtag_hash, secondbrtag_hash) @[el2_ifu_aln_ctl.scala 388:27]
-    io.ifu_i0_bp_btag <= _T_783 @[el2_ifu_aln_ctl.scala 388:21]
-    decompressed.io.din <= aligndata @[el2_ifu_aln_ctl.scala 390:23]
-    node _T_784 = not(error_stall) @[el2_ifu_aln_ctl.scala 392:39]
-    node i0_shift = and(io.dec_i0_decode_d, _T_784) @[el2_ifu_aln_ctl.scala 392:37]
-    io.ifu_pmu_instr_aligned <= i0_shift @[el2_ifu_aln_ctl.scala 394:28]
-    node _T_785 = and(i0_shift, first2B) @[el2_ifu_aln_ctl.scala 396:24]
-    shift_2B <= _T_785 @[el2_ifu_aln_ctl.scala 396:12]
-    node _T_786 = and(i0_shift, first4B) @[el2_ifu_aln_ctl.scala 397:24]
-    shift_4B <= _T_786 @[el2_ifu_aln_ctl.scala 397:12]
-    node _T_787 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 399:37]
-    node _T_788 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 399:52]
-    node _T_789 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 399:66]
-    node _T_790 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 399:83]
-    node _T_791 = eq(_T_790, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 399:77]
-    node _T_792 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 399:94]
-    node _T_793 = and(_T_791, _T_792) @[el2_ifu_aln_ctl.scala 399:87]
+    io.i0_brp.hist <= _T_752 @[el2_ifu_aln_ctl.scala 386:18]
+    node i0_ends_f1 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 389:28]
+    node _T_753 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:39]
+    node _T_754 = mux(_T_753, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:27]
+    io.i0_brp.toffset <= _T_754 @[el2_ifu_aln_ctl.scala 390:21]
+    node _T_755 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:37]
+    node _T_756 = mux(_T_755, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:25]
+    io.i0_brp.prett <= _T_756 @[el2_ifu_aln_ctl.scala 392:19]
+    node _T_757 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:51]
+    node _T_758 = and(first4B, _T_757) @[el2_ifu_aln_ctl.scala 394:41]
+    node _T_759 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:67]
+    node _T_760 = and(_T_758, _T_759) @[el2_ifu_aln_ctl.scala 394:55]
+    io.i0_brp.br_start_error <= _T_760 @[el2_ifu_aln_ctl.scala 394:29]
+    node _T_761 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:57]
+    node _T_762 = or(first2B, _T_761) @[el2_ifu_aln_ctl.scala 396:45]
+    node _T_763 = bits(_T_762, 0, 0) @[el2_ifu_aln_ctl.scala 396:62]
+    node _T_764 = bits(f0pc, 1, 1) @[el2_ifu_aln_ctl.scala 396:77]
+    node _T_765 = bits(secondpc, 1, 1) @[el2_ifu_aln_ctl.scala 396:90]
+    node _T_766 = mux(_T_763, _T_764, _T_765) @[el2_ifu_aln_ctl.scala 396:35]
+    io.i0_brp.bank <= _T_766 @[el2_ifu_aln_ctl.scala 396:29]
+    node _T_767 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:42]
+    node _T_768 = and(_T_767, first2B) @[el2_ifu_aln_ctl.scala 398:56]
+    node _T_769 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:89]
+    node _T_770 = and(io.i0_brp.valid, _T_769) @[el2_ifu_aln_ctl.scala 398:87]
+    node _T_771 = and(_T_770, first4B) @[el2_ifu_aln_ctl.scala 398:101]
+    node _T_772 = or(_T_768, _T_771) @[el2_ifu_aln_ctl.scala 398:68]
+    io.i0_brp.br_error <= _T_772 @[el2_ifu_aln_ctl.scala 398:22]
+    node _T_773 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 400:50]
+    node _T_774 = or(first2B, _T_773) @[el2_ifu_aln_ctl.scala 400:38]
+    node _T_775 = bits(_T_774, 0, 0) @[el2_ifu_aln_ctl.scala 400:55]
+    node _T_776 = mux(_T_775, firstpc_hash, secondpc_hash) @[el2_ifu_aln_ctl.scala 400:28]
+    io.ifu_i0_bp_index <= _T_776 @[el2_ifu_aln_ctl.scala 400:22]
+    node _T_777 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 402:37]
+    node _T_778 = bits(_T_777, 0, 0) @[el2_ifu_aln_ctl.scala 402:52]
+    node _T_779 = mux(_T_778, f1fghr, f0fghr) @[el2_ifu_aln_ctl.scala 402:27]
+    io.ifu_i0_bp_fghr <= _T_779 @[el2_ifu_aln_ctl.scala 402:21]
+    node _T_780 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 404:49]
+    node _T_781 = or(first2B, _T_780) @[el2_ifu_aln_ctl.scala 404:37]
+    node _T_782 = bits(_T_781, 0, 0) @[el2_ifu_aln_ctl.scala 404:54]
+    node _T_783 = mux(_T_782, firstbrtag_hash, secondbrtag_hash) @[el2_ifu_aln_ctl.scala 404:27]
+    io.ifu_i0_bp_btag <= _T_783 @[el2_ifu_aln_ctl.scala 404:21]
+    decompressed.io.din <= aligndata @[el2_ifu_aln_ctl.scala 406:23]
+    node _T_784 = not(error_stall) @[el2_ifu_aln_ctl.scala 408:39]
+    node i0_shift = and(io.dec_i0_decode_d, _T_784) @[el2_ifu_aln_ctl.scala 408:37]
+    io.ifu_pmu_instr_aligned <= i0_shift @[el2_ifu_aln_ctl.scala 410:28]
+    node _T_785 = and(i0_shift, first2B) @[el2_ifu_aln_ctl.scala 412:24]
+    shift_2B <= _T_785 @[el2_ifu_aln_ctl.scala 412:12]
+    node _T_786 = and(i0_shift, first4B) @[el2_ifu_aln_ctl.scala 413:24]
+    shift_4B <= _T_786 @[el2_ifu_aln_ctl.scala 413:12]
+    node _T_787 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 415:37]
+    node _T_788 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:52]
+    node _T_789 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 415:66]
+    node _T_790 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:83]
+    node _T_791 = eq(_T_790, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 415:77]
+    node _T_792 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:94]
+    node _T_793 = and(_T_791, _T_792) @[el2_ifu_aln_ctl.scala 415:87]
     node _T_794 = mux(_T_787, _T_788, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_795 = mux(_T_789, _T_793, UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_796 = or(_T_794, _T_795) @[Mux.scala 27:72]
     wire _T_797 : UInt<1> @[Mux.scala 27:72]
     _T_797 <= _T_796 @[Mux.scala 27:72]
-    f0_shift_2B <= _T_797 @[el2_ifu_aln_ctl.scala 399:15]
-    node _T_798 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 400:24]
-    node _T_799 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 400:36]
-    node _T_800 = eq(_T_799, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 400:30]
-    node _T_801 = and(_T_798, _T_800) @[el2_ifu_aln_ctl.scala 400:28]
-    node _T_802 = and(_T_801, shift_4B) @[el2_ifu_aln_ctl.scala 400:40]
-    f1_shift_2B <= _T_802 @[el2_ifu_aln_ctl.scala 400:15]
+    f0_shift_2B <= _T_797 @[el2_ifu_aln_ctl.scala 415:15]
+    node _T_798 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 416:24]
+    node _T_799 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 416:36]
+    node _T_800 = eq(_T_799, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 416:30]
+    node _T_801 = and(_T_798, _T_800) @[el2_ifu_aln_ctl.scala 416:28]
+    node _T_802 = and(_T_801, shift_4B) @[el2_ifu_aln_ctl.scala 416:40]
+    f1_shift_2B <= _T_802 @[el2_ifu_aln_ctl.scala 416:15]
     
diff --git a/el2_ifu_aln_ctl.v b/el2_ifu_aln_ctl.v
index 60956567..277c332e 100644
--- a/el2_ifu_aln_ctl.v
+++ b/el2_ifu_aln_ctl.v
@@ -578,31 +578,31 @@ module el2_ifu_aln_ctl(
   reg [63:0] _RAND_19;
   reg [63:0] _RAND_20;
 `endif // RANDOMIZE_REG_INIT
-  wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 350:28]
-  wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 350:28]
-  reg  error_stall; // @[el2_ifu_aln_ctl.scala 112:51]
-  wire  _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 110:34]
-  wire  _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 110:64]
-  wire  error_stall_in = _T & _T_1; // @[el2_ifu_aln_ctl.scala 110:62]
-  reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 113:48]
-  reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 114:48]
-  reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 116:48]
-  reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 117:48]
-  reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 118:48]
-  reg  q2off; // @[el2_ifu_aln_ctl.scala 120:48]
-  reg  q1off; // @[el2_ifu_aln_ctl.scala 121:48]
-  reg  q0off; // @[el2_ifu_aln_ctl.scala 122:48]
-  wire  _T_784 = ~error_stall; // @[el2_ifu_aln_ctl.scala 392:39]
-  wire  i0_shift = io_dec_i0_decode_d & _T_784; // @[el2_ifu_aln_ctl.scala 392:37]
-  wire  _T_186 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 172:31]
+  wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 366:28]
+  wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 366:28]
+  reg  error_stall; // @[el2_ifu_aln_ctl.scala 128:51]
+  wire  _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 126:34]
+  wire  _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 126:64]
+  wire  error_stall_in = _T & _T_1; // @[el2_ifu_aln_ctl.scala 126:62]
+  reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 129:48]
+  reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 130:48]
+  reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 132:48]
+  reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 133:48]
+  reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 134:48]
+  reg  q2off; // @[el2_ifu_aln_ctl.scala 136:48]
+  reg  q1off; // @[el2_ifu_aln_ctl.scala 137:48]
+  reg  q0off; // @[el2_ifu_aln_ctl.scala 138:48]
+  wire  _T_784 = ~error_stall; // @[el2_ifu_aln_ctl.scala 408:39]
+  wire  i0_shift = io_dec_i0_decode_d & _T_784; // @[el2_ifu_aln_ctl.scala 408:37]
+  wire  _T_186 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 188:31]
   wire  _T_189 = _T_186 & q0off; // @[Mux.scala 27:72]
-  wire  _T_187 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 173:11]
+  wire  _T_187 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 189:11]
   wire  _T_190 = _T_187 & q1off; // @[Mux.scala 27:72]
   wire  _T_192 = _T_189 | _T_190; // @[Mux.scala 27:72]
-  wire  _T_188 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 174:11]
+  wire  _T_188 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 190:11]
   wire  _T_191 = _T_188 & q2off; // @[Mux.scala 27:72]
   wire  q0ptr = _T_192 | _T_191; // @[Mux.scala 27:72]
-  wire  _T_202 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 178:26]
+  wire  _T_202 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 194:26]
   wire [1:0] q0sel = {q0ptr,_T_202}; // @[Cat.scala 29:58]
   wire [2:0] qren = {_T_188,_T_187,_T_186}; // @[Cat.scala 29:58]
   reg [31:0] q1; // @[Reg.scala 27:20]
@@ -616,22 +616,22 @@ module el2_ifu_aln_ctl(
   wire [63:0] _T_486 = {q0,q2}; // @[Cat.scala 29:58]
   wire [63:0] _T_489 = qren[2] ? _T_486 : 64'h0; // @[Mux.scala 27:72]
   wire [63:0] qeff = _T_490 | _T_489; // @[Mux.scala 27:72]
-  wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 294:42]
+  wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 310:42]
   wire [31:0] _T_497 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72]
   wire [15:0] _T_498 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72]
   wire [31:0] _GEN_12 = {{16'd0}, _T_498}; // @[Mux.scala 27:72]
   wire [31:0] q0final = _T_497 | _GEN_12; // @[Mux.scala 27:72]
   wire [31:0] _T_519 = f0val[0] ? q0final : 32'h0; // @[Mux.scala 27:72]
-  wire  _T_514 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 300:58]
-  wire  _T_516 = _T_514 & f0val[0]; // @[el2_ifu_aln_ctl.scala 300:68]
+  wire  _T_514 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 316:58]
+  wire  _T_516 = _T_514 & f0val[0]; // @[el2_ifu_aln_ctl.scala 316:68]
   wire  _T_197 = _T_186 & q1off; // @[Mux.scala 27:72]
   wire  _T_198 = _T_187 & q2off; // @[Mux.scala 27:72]
   wire  _T_200 = _T_197 | _T_198; // @[Mux.scala 27:72]
   wire  _T_199 = _T_188 & q0off; // @[Mux.scala 27:72]
   wire  q1ptr = _T_200 | _T_199; // @[Mux.scala 27:72]
-  wire  _T_203 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 180:26]
+  wire  _T_203 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 196:26]
   wire [1:0] q1sel = {q1ptr,_T_203}; // @[Cat.scala 29:58]
-  wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 294:29]
+  wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 310:29]
   wire [15:0] _T_507 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72]
   wire [15:0] _T_508 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72]
   wire [15:0] q1final = _T_507 | _T_508; // @[Mux.scala 27:72]
@@ -639,91 +639,91 @@ module el2_ifu_aln_ctl(
   wire [47:0] _T_520 = _T_516 ? _T_518 : 48'h0; // @[Mux.scala 27:72]
   wire [47:0] _GEN_13 = {{16'd0}, _T_519}; // @[Mux.scala 27:72]
   wire [47:0] aligndata = _GEN_13 | _T_520; // @[Mux.scala 27:72]
-  wire  first4B = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 332:29]
-  wire  first2B = ~first4B; // @[el2_ifu_aln_ctl.scala 334:17]
-  wire  shift_2B = i0_shift & first2B; // @[el2_ifu_aln_ctl.scala 396:24]
+  wire  first4B = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 348:29]
+  wire  first2B = ~first4B; // @[el2_ifu_aln_ctl.scala 350:17]
+  wire  shift_2B = i0_shift & first2B; // @[el2_ifu_aln_ctl.scala 412:24]
   wire [1:0] _T_444 = {1'h0,f0val[1]}; // @[Cat.scala 29:58]
   wire [1:0] _T_449 = shift_2B ? _T_444 : 2'h0; // @[Mux.scala 27:72]
-  wire  _T_445 = ~shift_2B; // @[el2_ifu_aln_ctl.scala 284:6]
-  wire  shift_4B = i0_shift & first4B; // @[el2_ifu_aln_ctl.scala 397:24]
-  wire  _T_446 = ~shift_4B; // @[el2_ifu_aln_ctl.scala 284:18]
-  wire  _T_447 = _T_445 & _T_446; // @[el2_ifu_aln_ctl.scala 284:16]
+  wire  _T_445 = ~shift_2B; // @[el2_ifu_aln_ctl.scala 300:6]
+  wire  shift_4B = i0_shift & first4B; // @[el2_ifu_aln_ctl.scala 413:24]
+  wire  _T_446 = ~shift_4B; // @[el2_ifu_aln_ctl.scala 300:18]
+  wire  _T_447 = _T_445 & _T_446; // @[el2_ifu_aln_ctl.scala 300:16]
   wire [1:0] _T_450 = _T_447 ? f1val : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] sf0val = _T_449 | _T_450; // @[Mux.scala 27:72]
-  wire  sf0_valid = sf0val[0]; // @[el2_ifu_aln_ctl.scala 237:22]
-  wire  _T_352 = ~sf0_valid; // @[el2_ifu_aln_ctl.scala 256:26]
-  wire  _T_801 = f0val[0] & _T_514; // @[el2_ifu_aln_ctl.scala 400:28]
-  wire  f1_shift_2B = _T_801 & shift_4B; // @[el2_ifu_aln_ctl.scala 400:40]
+  wire  sf0_valid = sf0val[0]; // @[el2_ifu_aln_ctl.scala 253:22]
+  wire  _T_352 = ~sf0_valid; // @[el2_ifu_aln_ctl.scala 272:26]
+  wire  _T_801 = f0val[0] & _T_514; // @[el2_ifu_aln_ctl.scala 416:28]
+  wire  f1_shift_2B = _T_801 & shift_4B; // @[el2_ifu_aln_ctl.scala 416:40]
   wire  _T_418 = f1_shift_2B & f1val[1]; // @[Mux.scala 27:72]
-  wire  _T_417 = ~f1_shift_2B; // @[el2_ifu_aln_ctl.scala 277:53]
+  wire  _T_417 = ~f1_shift_2B; // @[el2_ifu_aln_ctl.scala 293:53]
   wire [1:0] _T_419 = _T_417 ? f1val : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _GEN_14 = {{1'd0}, _T_418}; // @[Mux.scala 27:72]
   wire [1:0] sf1val = _GEN_14 | _T_419; // @[Mux.scala 27:72]
-  wire  sf1_valid = sf1val[0]; // @[el2_ifu_aln_ctl.scala 236:22]
-  wire  _T_353 = _T_352 & sf1_valid; // @[el2_ifu_aln_ctl.scala 256:37]
-  wire  f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 235:20]
-  wire  _T_354 = _T_353 & f2_valid; // @[el2_ifu_aln_ctl.scala 256:50]
-  wire  ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 245:30]
-  wire  _T_355 = _T_354 & ifvalid; // @[el2_ifu_aln_ctl.scala 256:62]
-  wire  _T_356 = sf0_valid & sf1_valid; // @[el2_ifu_aln_ctl.scala 257:17]
-  wire  _T_357 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 257:32]
-  wire  _T_358 = _T_356 & _T_357; // @[el2_ifu_aln_ctl.scala 257:30]
-  wire  _T_359 = _T_358 & ifvalid; // @[el2_ifu_aln_ctl.scala 257:42]
-  wire  fetch_to_f2 = _T_355 | _T_359; // @[el2_ifu_aln_ctl.scala 256:74]
+  wire  sf1_valid = sf1val[0]; // @[el2_ifu_aln_ctl.scala 252:22]
+  wire  _T_353 = _T_352 & sf1_valid; // @[el2_ifu_aln_ctl.scala 272:37]
+  wire  f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 251:20]
+  wire  _T_354 = _T_353 & f2_valid; // @[el2_ifu_aln_ctl.scala 272:50]
+  wire  ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 261:30]
+  wire  _T_355 = _T_354 & ifvalid; // @[el2_ifu_aln_ctl.scala 272:62]
+  wire  _T_356 = sf0_valid & sf1_valid; // @[el2_ifu_aln_ctl.scala 273:17]
+  wire  _T_357 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 273:32]
+  wire  _T_358 = _T_356 & _T_357; // @[el2_ifu_aln_ctl.scala 273:30]
+  wire  _T_359 = _T_358 & ifvalid; // @[el2_ifu_aln_ctl.scala 273:42]
+  wire  fetch_to_f2 = _T_355 | _T_359; // @[el2_ifu_aln_ctl.scala 272:74]
   reg [30:0] f2pc; // @[Reg.scala 27:20]
-  wire  _T_336 = ~sf1_valid; // @[el2_ifu_aln_ctl.scala 252:39]
-  wire  _T_337 = _T_352 & _T_336; // @[el2_ifu_aln_ctl.scala 252:37]
-  wire  _T_338 = _T_337 & f2_valid; // @[el2_ifu_aln_ctl.scala 252:50]
-  wire  _T_339 = _T_338 & ifvalid; // @[el2_ifu_aln_ctl.scala 252:62]
-  wire  _T_343 = _T_353 & _T_357; // @[el2_ifu_aln_ctl.scala 253:30]
-  wire  _T_344 = _T_343 & ifvalid; // @[el2_ifu_aln_ctl.scala 253:42]
-  wire  _T_345 = _T_339 | _T_344; // @[el2_ifu_aln_ctl.scala 252:74]
-  wire  _T_347 = sf0_valid & _T_336; // @[el2_ifu_aln_ctl.scala 254:17]
-  wire  _T_349 = _T_347 & _T_357; // @[el2_ifu_aln_ctl.scala 254:30]
-  wire  _T_350 = _T_349 & ifvalid; // @[el2_ifu_aln_ctl.scala 254:42]
-  wire  fetch_to_f1 = _T_345 | _T_350; // @[el2_ifu_aln_ctl.scala 253:54]
-  wire  _T_25 = fetch_to_f1 | _T_354; // @[el2_ifu_aln_ctl.scala 141:33]
-  wire  f1_shift_wr_en = _T_25 | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 141:47]
+  wire  _T_336 = ~sf1_valid; // @[el2_ifu_aln_ctl.scala 268:39]
+  wire  _T_337 = _T_352 & _T_336; // @[el2_ifu_aln_ctl.scala 268:37]
+  wire  _T_338 = _T_337 & f2_valid; // @[el2_ifu_aln_ctl.scala 268:50]
+  wire  _T_339 = _T_338 & ifvalid; // @[el2_ifu_aln_ctl.scala 268:62]
+  wire  _T_343 = _T_353 & _T_357; // @[el2_ifu_aln_ctl.scala 269:30]
+  wire  _T_344 = _T_343 & ifvalid; // @[el2_ifu_aln_ctl.scala 269:42]
+  wire  _T_345 = _T_339 | _T_344; // @[el2_ifu_aln_ctl.scala 268:74]
+  wire  _T_347 = sf0_valid & _T_336; // @[el2_ifu_aln_ctl.scala 270:17]
+  wire  _T_349 = _T_347 & _T_357; // @[el2_ifu_aln_ctl.scala 270:30]
+  wire  _T_350 = _T_349 & ifvalid; // @[el2_ifu_aln_ctl.scala 270:42]
+  wire  fetch_to_f1 = _T_345 | _T_350; // @[el2_ifu_aln_ctl.scala 269:54]
+  wire  _T_25 = fetch_to_f1 | _T_354; // @[el2_ifu_aln_ctl.scala 157:33]
+  wire  f1_shift_wr_en = _T_25 | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 157:47]
   reg [30:0] f1pc; // @[Reg.scala 27:20]
   wire [30:0] _T_376 = fetch_to_f1 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_377 = _T_354 ? f2pc : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_379 = _T_376 | _T_377; // @[Mux.scala 27:72]
-  wire  _T_372 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 267:6]
-  wire  _T_373 = ~_T_354; // @[el2_ifu_aln_ctl.scala 267:21]
-  wire  _T_374 = _T_372 & _T_373; // @[el2_ifu_aln_ctl.scala 267:19]
+  wire  _T_372 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 283:6]
+  wire  _T_373 = ~_T_354; // @[el2_ifu_aln_ctl.scala 283:21]
+  wire  _T_374 = _T_372 & _T_373; // @[el2_ifu_aln_ctl.scala 283:19]
   wire [30:0] _T_364 = f1_shift_2B ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
   reg [30:0] f0pc; // @[Reg.scala 27:20]
-  wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[el2_ifu_aln_ctl.scala 259:25]
-  wire [30:0] _T_365 = _T_364 & f0pc_plus1; // @[el2_ifu_aln_ctl.scala 263:38]
+  wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[el2_ifu_aln_ctl.scala 275:25]
+  wire [30:0] _T_365 = _T_364 & f0pc_plus1; // @[el2_ifu_aln_ctl.scala 279:38]
   wire [30:0] _T_368 = _T_417 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
-  wire [30:0] _T_369 = _T_368 & f0pc; // @[el2_ifu_aln_ctl.scala 263:78]
-  wire [30:0] sf1pc = _T_365 | _T_369; // @[el2_ifu_aln_ctl.scala 263:52]
+  wire [30:0] _T_369 = _T_368 & f0pc; // @[el2_ifu_aln_ctl.scala 279:78]
+  wire [30:0] sf1pc = _T_365 | _T_369; // @[el2_ifu_aln_ctl.scala 279:52]
   wire [30:0] _T_378 = _T_374 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] f1pc_in = _T_379 | _T_378; // @[Mux.scala 27:72]
-  wire  _T_333 = _T_337 & _T_357; // @[el2_ifu_aln_ctl.scala 251:50]
-  wire  fetch_to_f0 = _T_333 & ifvalid; // @[el2_ifu_aln_ctl.scala 251:62]
-  wire  _T_27 = fetch_to_f0 | _T_338; // @[el2_ifu_aln_ctl.scala 142:33]
-  wire  _T_28 = _T_27 | _T_353; // @[el2_ifu_aln_ctl.scala 142:47]
-  wire  _T_29 = _T_28 | shift_2B; // @[el2_ifu_aln_ctl.scala 142:61]
-  wire  f0_shift_wr_en = _T_29 | shift_4B; // @[el2_ifu_aln_ctl.scala 142:72]
+  wire  _T_333 = _T_337 & _T_357; // @[el2_ifu_aln_ctl.scala 267:50]
+  wire  fetch_to_f0 = _T_333 & ifvalid; // @[el2_ifu_aln_ctl.scala 267:62]
+  wire  _T_27 = fetch_to_f0 | _T_338; // @[el2_ifu_aln_ctl.scala 158:33]
+  wire  _T_28 = _T_27 | _T_353; // @[el2_ifu_aln_ctl.scala 158:47]
+  wire  _T_29 = _T_28 | shift_2B; // @[el2_ifu_aln_ctl.scala 158:61]
+  wire  f0_shift_wr_en = _T_29 | shift_4B; // @[el2_ifu_aln_ctl.scala 158:72]
   wire [30:0] _T_391 = fetch_to_f0 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_392 = _T_338 ? f2pc : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_395 = _T_391 | _T_392; // @[Mux.scala 27:72]
   wire [30:0] _T_393 = _T_353 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] _T_396 = _T_395 | _T_393; // @[Mux.scala 27:72]
-  wire  _T_385 = ~fetch_to_f0; // @[el2_ifu_aln_ctl.scala 272:24]
-  wire  _T_386 = ~_T_338; // @[el2_ifu_aln_ctl.scala 272:39]
-  wire  _T_387 = _T_385 & _T_386; // @[el2_ifu_aln_ctl.scala 272:37]
-  wire  _T_388 = ~_T_353; // @[el2_ifu_aln_ctl.scala 272:54]
-  wire  _T_389 = _T_387 & _T_388; // @[el2_ifu_aln_ctl.scala 272:52]
+  wire  _T_385 = ~fetch_to_f0; // @[el2_ifu_aln_ctl.scala 288:24]
+  wire  _T_386 = ~_T_338; // @[el2_ifu_aln_ctl.scala 288:39]
+  wire  _T_387 = _T_385 & _T_386; // @[el2_ifu_aln_ctl.scala 288:37]
+  wire  _T_388 = ~_T_353; // @[el2_ifu_aln_ctl.scala 288:54]
+  wire  _T_389 = _T_387 & _T_388; // @[el2_ifu_aln_ctl.scala 288:52]
   wire [30:0] _T_394 = _T_389 ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72]
   wire [30:0] f0pc_in = _T_396 | _T_394; // @[Mux.scala 27:72]
-  wire  _T_35 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 145:21]
-  wire  _T_36 = _T_35 & ifvalid; // @[el2_ifu_aln_ctl.scala 145:29]
-  wire  _T_37 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 145:46]
-  wire  _T_38 = _T_37 & ifvalid; // @[el2_ifu_aln_ctl.scala 145:54]
-  wire  _T_39 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 145:71]
-  wire  _T_40 = _T_39 & ifvalid; // @[el2_ifu_aln_ctl.scala 145:79]
+  wire  _T_35 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 161:21]
+  wire  _T_36 = _T_35 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:29]
+  wire  _T_37 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 161:46]
+  wire  _T_38 = _T_37 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:54]
+  wire  _T_39 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 161:71]
+  wire  _T_40 = _T_39 & ifvalid; // @[el2_ifu_aln_ctl.scala 161:79]
   wire [2:0] qwen = {_T_36,_T_38,_T_40}; // @[Cat.scala 29:58]
   reg [11:0] brdata2; // @[Reg.scala 27:20]
   wire [5:0] _T_242 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58]
@@ -734,18 +734,18 @@ module el2_ifu_aln_ctl(
   wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f[31:1],io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
   reg [54:0] _T_16; // @[Reg.scala 27:20]
   reg [54:0] _T_18; // @[Reg.scala 27:20]
-  wire  _T_44 = qren[0] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 147:34]
-  wire  _T_46 = _T_44 & _T_1; // @[el2_ifu_aln_ctl.scala 147:55]
-  wire  _T_49 = qren[1] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 148:14]
-  wire  _T_51 = _T_49 & _T_1; // @[el2_ifu_aln_ctl.scala 148:35]
-  wire  _T_59 = qren[0] & io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 150:14]
-  wire  _T_61 = _T_59 & _T_1; // @[el2_ifu_aln_ctl.scala 150:35]
-  wire  _T_69 = qren[2] & io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 152:14]
-  wire  _T_71 = _T_69 & _T_1; // @[el2_ifu_aln_ctl.scala 152:35]
-  wire  _T_73 = ~io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 153:6]
-  wire  _T_74 = ~io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 153:28]
-  wire  _T_75 = _T_73 & _T_74; // @[el2_ifu_aln_ctl.scala 153:26]
-  wire  _T_77 = _T_75 & _T_1; // @[el2_ifu_aln_ctl.scala 153:48]
+  wire  _T_44 = qren[0] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 163:34]
+  wire  _T_46 = _T_44 & _T_1; // @[el2_ifu_aln_ctl.scala 163:55]
+  wire  _T_49 = qren[1] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 164:14]
+  wire  _T_51 = _T_49 & _T_1; // @[el2_ifu_aln_ctl.scala 164:35]
+  wire  _T_59 = qren[0] & io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 166:14]
+  wire  _T_61 = _T_59 & _T_1; // @[el2_ifu_aln_ctl.scala 166:35]
+  wire  _T_69 = qren[2] & io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 168:14]
+  wire  _T_71 = _T_69 & _T_1; // @[el2_ifu_aln_ctl.scala 168:35]
+  wire  _T_73 = ~io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 169:6]
+  wire  _T_74 = ~io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 169:28]
+  wire  _T_75 = _T_73 & _T_74; // @[el2_ifu_aln_ctl.scala 169:26]
+  wire  _T_77 = _T_75 & _T_1; // @[el2_ifu_aln_ctl.scala 169:48]
   wire [1:0] _T_80 = _T_51 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_82 = _T_61 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_85 = _T_77 ? rdptr : 2'h0; // @[Mux.scala 27:72]
@@ -755,57 +755,57 @@ module el2_ifu_aln_ctl(
   wire [1:0] _GEN_16 = {{1'd0}, _T_71}; // @[Mux.scala 27:72]
   wire [1:0] _T_90 = _T_88 | _GEN_16; // @[Mux.scala 27:72]
   wire [1:0] rdptr_in = _T_90 | _T_85; // @[Mux.scala 27:72]
-  wire  _T_95 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 155:34]
-  wire  _T_99 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 156:14]
-  wire  _T_105 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 158:6]
-  wire  _T_107 = _T_105 & _T_1; // @[el2_ifu_aln_ctl.scala 158:15]
+  wire  _T_95 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 171:34]
+  wire  _T_99 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 172:14]
+  wire  _T_105 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 174:6]
+  wire  _T_107 = _T_105 & _T_1; // @[el2_ifu_aln_ctl.scala 174:15]
   wire [1:0] _T_110 = _T_99 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_112 = _T_107 ? wrptr : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _GEN_17 = {{1'd0}, _T_95}; // @[Mux.scala 27:72]
   wire [1:0] _T_113 = _GEN_17 | _T_110; // @[Mux.scala 27:72]
   wire [1:0] wrptr_in = _T_113 | _T_112; // @[Mux.scala 27:72]
-  wire  _T_118 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 160:26]
-  wire  _T_120 = _T_118 & _T_188; // @[el2_ifu_aln_ctl.scala 160:35]
+  wire  _T_118 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 176:26]
+  wire  _T_120 = _T_118 & _T_188; // @[el2_ifu_aln_ctl.scala 176:35]
   wire  _T_794 = shift_2B & f0val[0]; // @[Mux.scala 27:72]
-  wire  _T_791 = ~f0val[0]; // @[el2_ifu_aln_ctl.scala 399:77]
-  wire  _T_793 = _T_791 & f0val[0]; // @[el2_ifu_aln_ctl.scala 399:87]
+  wire  _T_791 = ~f0val[0]; // @[el2_ifu_aln_ctl.scala 415:77]
+  wire  _T_793 = _T_791 & f0val[0]; // @[el2_ifu_aln_ctl.scala 415:87]
   wire  _T_795 = shift_4B & _T_793; // @[Mux.scala 27:72]
   wire  f0_shift_2B = _T_794 | _T_795; // @[Mux.scala 27:72]
-  wire  _T_122 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 160:74]
-  wire  _T_126 = _T_118 & _T_187; // @[el2_ifu_aln_ctl.scala 161:15]
-  wire  _T_128 = q2off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 161:54]
-  wire  _T_132 = _T_118 & _T_186; // @[el2_ifu_aln_ctl.scala 162:15]
+  wire  _T_122 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 176:74]
+  wire  _T_126 = _T_118 & _T_187; // @[el2_ifu_aln_ctl.scala 177:15]
+  wire  _T_128 = q2off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 177:54]
+  wire  _T_132 = _T_118 & _T_186; // @[el2_ifu_aln_ctl.scala 178:15]
   wire  _T_134 = _T_120 & _T_122; // @[Mux.scala 27:72]
   wire  _T_135 = _T_126 & _T_128; // @[Mux.scala 27:72]
   wire  _T_136 = _T_132 & q2off; // @[Mux.scala 27:72]
   wire  _T_137 = _T_134 | _T_135; // @[Mux.scala 27:72]
   wire  q2off_in = _T_137 | _T_136; // @[Mux.scala 27:72]
-  wire  _T_141 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 164:26]
-  wire  _T_143 = _T_141 & _T_187; // @[el2_ifu_aln_ctl.scala 164:35]
-  wire  _T_145 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 164:74]
-  wire  _T_149 = _T_141 & _T_186; // @[el2_ifu_aln_ctl.scala 165:15]
-  wire  _T_151 = q1off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 165:54]
-  wire  _T_155 = _T_141 & _T_188; // @[el2_ifu_aln_ctl.scala 166:15]
+  wire  _T_141 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 180:26]
+  wire  _T_143 = _T_141 & _T_187; // @[el2_ifu_aln_ctl.scala 180:35]
+  wire  _T_145 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 180:74]
+  wire  _T_149 = _T_141 & _T_186; // @[el2_ifu_aln_ctl.scala 181:15]
+  wire  _T_151 = q1off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 181:54]
+  wire  _T_155 = _T_141 & _T_188; // @[el2_ifu_aln_ctl.scala 182:15]
   wire  _T_157 = _T_143 & _T_145; // @[Mux.scala 27:72]
   wire  _T_158 = _T_149 & _T_151; // @[Mux.scala 27:72]
   wire  _T_159 = _T_155 & q1off; // @[Mux.scala 27:72]
   wire  _T_160 = _T_157 | _T_158; // @[Mux.scala 27:72]
   wire  q1off_in = _T_160 | _T_159; // @[Mux.scala 27:72]
-  wire  _T_164 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 168:26]
-  wire  _T_166 = _T_164 & _T_186; // @[el2_ifu_aln_ctl.scala 168:35]
-  wire  _T_168 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 168:76]
-  wire  _T_172 = _T_164 & _T_188; // @[el2_ifu_aln_ctl.scala 169:15]
-  wire  _T_174 = q0off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 169:56]
-  wire  _T_178 = _T_164 & _T_187; // @[el2_ifu_aln_ctl.scala 170:15]
+  wire  _T_164 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 184:26]
+  wire  _T_166 = _T_164 & _T_186; // @[el2_ifu_aln_ctl.scala 184:35]
+  wire  _T_168 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 184:76]
+  wire  _T_172 = _T_164 & _T_188; // @[el2_ifu_aln_ctl.scala 185:15]
+  wire  _T_174 = q0off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 185:56]
+  wire  _T_178 = _T_164 & _T_187; // @[el2_ifu_aln_ctl.scala 186:15]
   wire  _T_180 = _T_166 & _T_168; // @[Mux.scala 27:72]
   wire  _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72]
   wire  _T_182 = _T_178 & q0off; // @[Mux.scala 27:72]
   wire  _T_183 = _T_180 | _T_181; // @[Mux.scala 27:72]
   wire  q0off_in = _T_183 | _T_182; // @[Mux.scala 27:72]
-  wire [53:0] misc1 = _T_16[53:0]; // @[el2_ifu_aln_ctl.scala 133:9]
-  wire [53:0] misc0 = _T_18[53:0]; // @[el2_ifu_aln_ctl.scala 134:9]
+  wire [53:0] misc1 = _T_16[53:0]; // @[el2_ifu_aln_ctl.scala 149:9]
+  wire [53:0] misc0 = _T_18[53:0]; // @[el2_ifu_aln_ctl.scala 150:9]
   wire [107:0] _T_212 = {misc1,misc0}; // @[Cat.scala 29:58]
-  wire [53:0] misc2 = _T_14[53:0]; // @[el2_ifu_aln_ctl.scala 132:9]
+  wire [53:0] misc2 = _T_14[53:0]; // @[el2_ifu_aln_ctl.scala 148:9]
   wire [107:0] _T_215 = {misc2,misc1}; // @[Cat.scala 29:58]
   wire [107:0] _T_218 = {misc0,misc2}; // @[Cat.scala 29:58]
   wire [107:0] _T_219 = qren[0] ? _T_212 : 108'h0; // @[Mux.scala 27:72]
@@ -813,20 +813,20 @@ module el2_ifu_aln_ctl(
   wire [107:0] _T_221 = qren[2] ? _T_218 : 108'h0; // @[Mux.scala 27:72]
   wire [107:0] _T_222 = _T_219 | _T_220; // @[Mux.scala 27:72]
   wire [107:0] misceff = _T_222 | _T_221; // @[Mux.scala 27:72]
-  wire [52:0] misc1eff = misceff[107:55]; // @[el2_ifu_aln_ctl.scala 189:25]
-  wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 190:25]
-  wire  f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 193:25]
-  wire  f1icaf = misc1eff[51]; // @[el2_ifu_aln_ctl.scala 194:21]
-  wire [1:0] f1ictype = misc1eff[50:49]; // @[el2_ifu_aln_ctl.scala 195:26]
-  wire [30:0] f1prett = misc1eff[48:18]; // @[el2_ifu_aln_ctl.scala 196:25]
-  wire [11:0] f1poffset = misc1eff[19:8]; // @[el2_ifu_aln_ctl.scala 197:27]
-  wire [7:0] f1fghr = misc1eff[7:0]; // @[el2_ifu_aln_ctl.scala 198:24]
-  wire  f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 200:25]
-  wire  f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 201:21]
-  wire [1:0] f0ictype = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 202:26]
-  wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 203:25]
-  wire [11:0] f0poffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 204:27]
-  wire [7:0] f0fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 205:24]
+  wire [52:0] misc1eff = misceff[107:55]; // @[el2_ifu_aln_ctl.scala 205:25]
+  wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 206:25]
+  wire  f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 209:25]
+  wire  f1icaf = misc1eff[51]; // @[el2_ifu_aln_ctl.scala 210:21]
+  wire [1:0] f1ictype = misc1eff[50:49]; // @[el2_ifu_aln_ctl.scala 211:26]
+  wire [30:0] f1prett = misc1eff[48:18]; // @[el2_ifu_aln_ctl.scala 212:25]
+  wire [11:0] f1poffset = misc1eff[19:8]; // @[el2_ifu_aln_ctl.scala 213:27]
+  wire [7:0] f1fghr = misc1eff[7:0]; // @[el2_ifu_aln_ctl.scala 214:24]
+  wire  f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 216:25]
+  wire  f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 217:21]
+  wire [1:0] f0ictype = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 218:26]
+  wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 219:25]
+  wire [11:0] f0poffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 220:27]
+  wire [7:0] f0fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 221:24]
   wire [23:0] _T_251 = {brdata1,brdata0}; // @[Cat.scala 29:58]
   wire [23:0] _T_254 = {brdata2,brdata1}; // @[Cat.scala 29:58]
   wire [23:0] _T_257 = {brdata0,brdata2}; // @[Cat.scala 29:58]
@@ -835,8 +835,8 @@ module el2_ifu_aln_ctl(
   wire [23:0] _T_260 = qren[2] ? _T_257 : 24'h0; // @[Mux.scala 27:72]
   wire [23:0] _T_261 = _T_258 | _T_259; // @[Mux.scala 27:72]
   wire [23:0] brdataeff = _T_261 | _T_260; // @[Mux.scala 27:72]
-  wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 215:43]
-  wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 215:61]
+  wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 231:43]
+  wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 231:61]
   wire [11:0] _T_268 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72]
   wire [5:0] _T_269 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72]
   wire [11:0] _GEN_18 = {{6'd0}, _T_269}; // @[Mux.scala 27:72]
@@ -857,32 +857,32 @@ module el2_ifu_aln_ctl(
   wire [1:0] f1pc4 = {brdata1final[9],brdata1final[3]}; // @[Cat.scala 29:58]
   wire [1:0] f1hist0 = {brdata1final[10],brdata1final[4]}; // @[Cat.scala 29:58]
   wire [1:0] f1hist1 = {brdata1final[11],brdata1final[5]}; // @[Cat.scala 29:58]
-  wire  consume_fb0 = _T_352 & f0val[0]; // @[el2_ifu_aln_ctl.scala 239:32]
-  wire  consume_fb1 = _T_336 & f1val[0]; // @[el2_ifu_aln_ctl.scala 240:32]
-  wire  _T_312 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 242:39]
-  wire  _T_313 = consume_fb0 & _T_312; // @[el2_ifu_aln_ctl.scala 242:37]
-  wire  _T_316 = consume_fb0 & consume_fb1; // @[el2_ifu_aln_ctl.scala 243:37]
-  wire  _T_400 = fetch_to_f2 & _T_1; // @[el2_ifu_aln_ctl.scala 274:38]
-  wire  _T_402 = ~fetch_to_f2; // @[el2_ifu_aln_ctl.scala 275:6]
-  wire  _T_404 = _T_402 & _T_373; // @[el2_ifu_aln_ctl.scala 275:19]
-  wire  _T_406 = _T_404 & _T_386; // @[el2_ifu_aln_ctl.scala 275:34]
-  wire  _T_408 = _T_406 & _T_1; // @[el2_ifu_aln_ctl.scala 275:49]
+  wire  consume_fb0 = _T_352 & f0val[0]; // @[el2_ifu_aln_ctl.scala 255:32]
+  wire  consume_fb1 = _T_336 & f1val[0]; // @[el2_ifu_aln_ctl.scala 256:32]
+  wire  _T_312 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 258:39]
+  wire  _T_313 = consume_fb0 & _T_312; // @[el2_ifu_aln_ctl.scala 258:37]
+  wire  _T_316 = consume_fb0 & consume_fb1; // @[el2_ifu_aln_ctl.scala 259:37]
+  wire  _T_400 = fetch_to_f2 & _T_1; // @[el2_ifu_aln_ctl.scala 290:38]
+  wire  _T_402 = ~fetch_to_f2; // @[el2_ifu_aln_ctl.scala 291:6]
+  wire  _T_404 = _T_402 & _T_373; // @[el2_ifu_aln_ctl.scala 291:19]
+  wire  _T_406 = _T_404 & _T_386; // @[el2_ifu_aln_ctl.scala 291:34]
+  wire  _T_408 = _T_406 & _T_1; // @[el2_ifu_aln_ctl.scala 291:49]
   wire [1:0] _T_410 = _T_400 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_411 = _T_408 ? f2val : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] f2val_in = _T_410 | _T_411; // @[Mux.scala 27:72]
-  wire  _T_423 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 279:38]
-  wire  _T_426 = _T_354 & _T_1; // @[el2_ifu_aln_ctl.scala 280:18]
-  wire  _T_432 = _T_374 & _T_388; // @[el2_ifu_aln_ctl.scala 281:34]
-  wire  _T_434 = _T_432 & _T_1; // @[el2_ifu_aln_ctl.scala 281:49]
+  wire  _T_423 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 295:38]
+  wire  _T_426 = _T_354 & _T_1; // @[el2_ifu_aln_ctl.scala 296:18]
+  wire  _T_432 = _T_374 & _T_388; // @[el2_ifu_aln_ctl.scala 297:34]
+  wire  _T_434 = _T_432 & _T_1; // @[el2_ifu_aln_ctl.scala 297:49]
   wire [1:0] _T_436 = _T_423 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_437 = _T_426 ? f2val : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_438 = _T_434 ? sf1val : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_439 = _T_436 | _T_437; // @[Mux.scala 27:72]
   wire [1:0] f1val_in = _T_439 | _T_438; // @[Mux.scala 27:72]
-  wire  _T_454 = fetch_to_f0 & _T_1; // @[el2_ifu_aln_ctl.scala 286:38]
-  wire  _T_457 = _T_338 & _T_1; // @[el2_ifu_aln_ctl.scala 287:18]
-  wire  _T_460 = _T_353 & _T_1; // @[el2_ifu_aln_ctl.scala 288:18]
-  wire  _T_468 = _T_389 & _T_1; // @[el2_ifu_aln_ctl.scala 289:49]
+  wire  _T_454 = fetch_to_f0 & _T_1; // @[el2_ifu_aln_ctl.scala 302:38]
+  wire  _T_457 = _T_338 & _T_1; // @[el2_ifu_aln_ctl.scala 303:18]
+  wire  _T_460 = _T_353 & _T_1; // @[el2_ifu_aln_ctl.scala 304:18]
+  wire  _T_468 = _T_389 & _T_1; // @[el2_ifu_aln_ctl.scala 305:49]
   wire [1:0] _T_470 = _T_454 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_471 = _T_457 ? f2val : 2'h0; // @[Mux.scala 27:72]
   wire [1:0] _T_472 = _T_460 ? sf1val : 2'h0; // @[Mux.scala 27:72]
@@ -933,18 +933,18 @@ module el2_ifu_aln_ctl(
   wire [30:0] secondpc = _T_646 | _T_647; // @[Mux.scala 27:72]
   wire  _T_656 = first4B & alignval[1]; // @[Mux.scala 27:72]
   wire  _T_657 = first2B & alignval[0]; // @[Mux.scala 27:72]
-  wire  _T_661 = |alignicaf; // @[el2_ifu_aln_ctl.scala 338:59]
+  wire  _T_661 = |alignicaf; // @[el2_ifu_aln_ctl.scala 354:59]
   wire  _T_664 = first4B & _T_661; // @[Mux.scala 27:72]
   wire  _T_665 = first2B & alignicaf[0]; // @[Mux.scala 27:72]
-  wire  _T_670 = first4B & _T_514; // @[el2_ifu_aln_ctl.scala 340:39]
-  wire  _T_672 = _T_670 & f0val[0]; // @[el2_ifu_aln_ctl.scala 340:51]
-  wire  _T_674 = ~alignicaf[0]; // @[el2_ifu_aln_ctl.scala 340:64]
-  wire  _T_675 = _T_672 & _T_674; // @[el2_ifu_aln_ctl.scala 340:62]
-  wire  _T_677 = ~aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 340:80]
-  wire  _T_678 = _T_675 & _T_677; // @[el2_ifu_aln_ctl.scala 340:78]
-  wire  icaf_eff = alignicaf[1] | aligndbecc[1]; // @[el2_ifu_aln_ctl.scala 342:31]
-  wire  _T_683 = first4B & icaf_eff; // @[el2_ifu_aln_ctl.scala 344:32]
-  wire  _T_686 = |aligndbecc; // @[el2_ifu_aln_ctl.scala 346:59]
+  wire  _T_670 = first4B & _T_514; // @[el2_ifu_aln_ctl.scala 356:39]
+  wire  _T_672 = _T_670 & f0val[0]; // @[el2_ifu_aln_ctl.scala 356:51]
+  wire  _T_674 = ~alignicaf[0]; // @[el2_ifu_aln_ctl.scala 356:64]
+  wire  _T_675 = _T_672 & _T_674; // @[el2_ifu_aln_ctl.scala 356:62]
+  wire  _T_677 = ~aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 356:80]
+  wire  _T_678 = _T_675 & _T_677; // @[el2_ifu_aln_ctl.scala 356:78]
+  wire  icaf_eff = alignicaf[1] | aligndbecc[1]; // @[el2_ifu_aln_ctl.scala 358:31]
+  wire  _T_683 = first4B & icaf_eff; // @[el2_ifu_aln_ctl.scala 360:32]
+  wire  _T_686 = |aligndbecc; // @[el2_ifu_aln_ctl.scala 362:59]
   wire  _T_689 = first4B & _T_686; // @[Mux.scala 27:72]
   wire  _T_690 = first2B & aligndbecc[0]; // @[Mux.scala 27:72]
   wire [47:0] _T_695 = first4B ? aligndata : 48'h0; // @[Mux.scala 27:72]
@@ -959,58 +959,58 @@ module el2_ifu_aln_ctl(
   wire [4:0] firstbrtag_hash = _T_711 ^ f0pc[23:19]; // @[el2_lib.scala 182:111]
   wire [4:0] _T_716 = secondpc[13:9] ^ secondpc[18:14]; // @[el2_lib.scala 182:111]
   wire [4:0] secondbrtag_hash = _T_716 ^ secondpc[23:19]; // @[el2_lib.scala 182:111]
-  wire  _T_718 = first2B & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 362:30]
-  wire  _T_720 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 362:58]
-  wire  _T_721 = _T_718 | _T_720; // @[el2_ifu_aln_ctl.scala 362:47]
-  wire  _T_725 = _T_656 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 362:100]
-  wire  _T_728 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 364:29]
-  wire  _T_730 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 364:55]
-  wire  _T_733 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 366:29]
-  wire  _T_735 = first4B & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 366:55]
-  wire  i0_brp_pc4 = _T_733 | _T_735; // @[el2_ifu_aln_ctl.scala 366:44]
-  wire  _T_737 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 368:33]
-  wire  _T_743 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 370:34]
-  wire  _T_745 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 370:62]
-  wire  _T_746 = _T_743 | _T_745; // @[el2_ifu_aln_ctl.scala 370:51]
-  wire  _T_748 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 371:14]
-  wire  _T_750 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 371:42]
-  wire  _T_751 = _T_748 | _T_750; // @[el2_ifu_aln_ctl.scala 371:31]
-  wire  i0_ends_f1 = first4B & _T_516; // @[el2_ifu_aln_ctl.scala 373:28]
-  wire  _T_767 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 382:42]
-  wire  _T_768 = _T_767 & first2B; // @[el2_ifu_aln_ctl.scala 382:56]
-  wire  _T_769 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 382:89]
-  wire  _T_770 = io_i0_brp_valid & _T_769; // @[el2_ifu_aln_ctl.scala 382:87]
-  wire  _T_771 = _T_770 & first4B; // @[el2_ifu_aln_ctl.scala 382:101]
-  wire [7:0] _T_776 = _T_737 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 384:28]
-  el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 350:28]
+  wire  _T_718 = first2B & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:30]
+  wire  _T_720 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 378:58]
+  wire  _T_721 = _T_718 | _T_720; // @[el2_ifu_aln_ctl.scala 378:47]
+  wire  _T_725 = _T_656 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:100]
+  wire  _T_728 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:29]
+  wire  _T_730 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:55]
+  wire  _T_733 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 382:29]
+  wire  _T_735 = first4B & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 382:55]
+  wire  i0_brp_pc4 = _T_733 | _T_735; // @[el2_ifu_aln_ctl.scala 382:44]
+  wire  _T_737 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:33]
+  wire  _T_743 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:34]
+  wire  _T_745 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:62]
+  wire  _T_746 = _T_743 | _T_745; // @[el2_ifu_aln_ctl.scala 386:51]
+  wire  _T_748 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 387:14]
+  wire  _T_750 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42]
+  wire  _T_751 = _T_748 | _T_750; // @[el2_ifu_aln_ctl.scala 387:31]
+  wire  i0_ends_f1 = first4B & _T_516; // @[el2_ifu_aln_ctl.scala 389:28]
+  wire  _T_767 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42]
+  wire  _T_768 = _T_767 & first2B; // @[el2_ifu_aln_ctl.scala 398:56]
+  wire  _T_769 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89]
+  wire  _T_770 = io_i0_brp_valid & _T_769; // @[el2_ifu_aln_ctl.scala 398:87]
+  wire  _T_771 = _T_770 & first4B; // @[el2_ifu_aln_ctl.scala 398:101]
+  wire [7:0] _T_776 = _T_737 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 400:28]
+  el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 366:28]
     .io_din(decompressed_io_din),
     .io_dout(decompressed_io_dout)
   );
-  assign io_ifu_i0_valid = _T_656 | _T_657; // @[el2_ifu_aln_ctl.scala 336:19]
-  assign io_ifu_i0_icaf = _T_664 | _T_665; // @[el2_ifu_aln_ctl.scala 338:18]
-  assign io_ifu_i0_icaf_type = _T_678 ? f1ictype : f0ictype; // @[el2_ifu_aln_ctl.scala 340:23]
-  assign io_ifu_i0_icaf_f1 = _T_683 & _T_516; // @[el2_ifu_aln_ctl.scala 344:21]
-  assign io_ifu_i0_dbecc = _T_689 | _T_690; // @[el2_ifu_aln_ctl.scala 346:19]
-  assign io_ifu_i0_instr = _T_697[31:0]; // @[el2_ifu_aln_ctl.scala 352:19]
-  assign io_ifu_i0_pc = {{1'd0}, f0pc}; // @[el2_ifu_aln_ctl.scala 324:16]
-  assign io_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 328:17]
-  assign io_ifu_fb_consume1 = _T_313 & _T_1; // @[el2_ifu_aln_ctl.scala 242:22]
-  assign io_ifu_fb_consume2 = _T_316 & _T_1; // @[el2_ifu_aln_ctl.scala 243:22]
-  assign io_ifu_i0_bp_index = _T_776[6:0]; // @[el2_ifu_aln_ctl.scala 384:22]
-  assign io_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[el2_ifu_aln_ctl.scala 386:21]
-  assign io_ifu_i0_bp_btag = _T_737 ? firstbrtag_hash : secondbrtag_hash; // @[el2_ifu_aln_ctl.scala 388:21]
-  assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_784; // @[el2_ifu_aln_ctl.scala 394:28]
-  assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 330:19]
-  assign io_i0_brp_valid = _T_721 | _T_725; // @[el2_ifu_aln_ctl.scala 362:19]
-  assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 374:21]
-  assign io_i0_brp_hist = {_T_746,_T_751}; // @[el2_ifu_aln_ctl.scala 370:18]
-  assign io_i0_brp_br_error = _T_768 | _T_771; // @[el2_ifu_aln_ctl.scala 382:22]
-  assign io_i0_brp_br_start_error = _T_656 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:29]
-  assign io_i0_brp_bank = _T_737 ? f0pc[1] : secondpc[1]; // @[el2_ifu_aln_ctl.scala 380:29]
-  assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 376:19]
-  assign io_i0_brp_way = _T_737 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 368:17]
-  assign io_i0_brp_ret = _T_728 | _T_730; // @[el2_ifu_aln_ctl.scala 364:17]
-  assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 390:23]
+  assign io_ifu_i0_valid = _T_656 | _T_657; // @[el2_ifu_aln_ctl.scala 47:19 el2_ifu_aln_ctl.scala 352:19]
+  assign io_ifu_i0_icaf = _T_664 | _T_665; // @[el2_ifu_aln_ctl.scala 48:18 el2_ifu_aln_ctl.scala 354:18]
+  assign io_ifu_i0_icaf_type = _T_678 ? f1ictype : f0ictype; // @[el2_ifu_aln_ctl.scala 49:23 el2_ifu_aln_ctl.scala 356:23]
+  assign io_ifu_i0_icaf_f1 = _T_683 & _T_516; // @[el2_ifu_aln_ctl.scala 50:21 el2_ifu_aln_ctl.scala 360:21]
+  assign io_ifu_i0_dbecc = _T_689 | _T_690; // @[el2_ifu_aln_ctl.scala 51:19 el2_ifu_aln_ctl.scala 362:19]
+  assign io_ifu_i0_instr = _T_697[31:0]; // @[el2_ifu_aln_ctl.scala 52:19 el2_ifu_aln_ctl.scala 368:19]
+  assign io_ifu_i0_pc = {{1'd0}, f0pc}; // @[el2_ifu_aln_ctl.scala 53:16 el2_ifu_aln_ctl.scala 340:16]
+  assign io_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 54:17 el2_ifu_aln_ctl.scala 344:17]
+  assign io_ifu_fb_consume1 = _T_313 & _T_1; // @[el2_ifu_aln_ctl.scala 55:22 el2_ifu_aln_ctl.scala 258:22]
+  assign io_ifu_fb_consume2 = _T_316 & _T_1; // @[el2_ifu_aln_ctl.scala 56:22 el2_ifu_aln_ctl.scala 259:22]
+  assign io_ifu_i0_bp_index = _T_776[6:0]; // @[el2_ifu_aln_ctl.scala 57:22 el2_ifu_aln_ctl.scala 400:22]
+  assign io_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[el2_ifu_aln_ctl.scala 58:21 el2_ifu_aln_ctl.scala 402:21]
+  assign io_ifu_i0_bp_btag = _T_737 ? firstbrtag_hash : secondbrtag_hash; // @[el2_ifu_aln_ctl.scala 59:21 el2_ifu_aln_ctl.scala 404:21]
+  assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_784; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28]
+  assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 61:19 el2_ifu_aln_ctl.scala 346:19]
+  assign io_i0_brp_valid = _T_721 | _T_725; // @[el2_ifu_aln_ctl.scala 378:19]
+  assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:21]
+  assign io_i0_brp_hist = {_T_746,_T_751}; // @[el2_ifu_aln_ctl.scala 386:18]
+  assign io_i0_brp_br_error = _T_768 | _T_771; // @[el2_ifu_aln_ctl.scala 398:22]
+  assign io_i0_brp_br_start_error = _T_656 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29]
+  assign io_i0_brp_bank = _T_737 ? f0pc[1] : secondpc[1]; // @[el2_ifu_aln_ctl.scala 396:29]
+  assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19]
+  assign io_i0_brp_way = _T_737 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17]
+  assign io_i0_brp_ret = _T_728 | _T_730; // @[el2_ifu_aln_ctl.scala 380:17]
+  assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 406:23]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
index a3d38af7..ae1dd7c4 100644
--- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
@@ -26,6 +26,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
     val ifu_fetch_data_f        = Input(UInt(32.W))
     val ifu_fetch_val           = Input(UInt(2.W))
     val ifu_fetch_pc            = Input(UInt(31.W))
+   /////////////////////////////////////////////////
     val ifu_i0_valid            = Output(Bool())
     val ifu_i0_icaf             = Output(Bool())
     val ifu_i0_icaf_type        = Output(UInt(2.W))
@@ -43,6 +44,21 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
     val ifu_i0_cinst            = Output(UInt(16.W))
     val i0_brp                  = Output(new el2_br_pkt_t)
   })
+  io.ifu_i0_valid := 0.U
+  io.ifu_i0_icaf := 0.U
+  io.ifu_i0_icaf_type := 0.U
+  io.ifu_i0_icaf_f1 := 0.U
+  io.ifu_i0_dbecc := 0.U
+  io.ifu_i0_instr := 0.U
+  io.ifu_i0_pc := 0.U
+  io.ifu_i0_pc4 := 0.U
+  io.ifu_fb_consume1 := 0.U
+  io.ifu_fb_consume2 := 0.U
+  io.ifu_i0_bp_index := 0.U
+  io.ifu_i0_bp_fghr := 0.U
+  io.ifu_i0_bp_btag := 0.U
+  io.ifu_pmu_instr_aligned := 0.U
+  io.ifu_i0_cinst := 0.U
   val MHI = 46+BHT_GHR_SIZE // 54
   val MSIZE = 47+BHT_GHR_SIZE // 55
   val BRDATA_SIZE = 12
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class
index 33fa224d..bdc81000 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class and b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class differ
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
index 47e7d459..06f6b088 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class differ
diff --git a/target/scala-2.12/classes/ifu/ifu_aln$.class b/target/scala-2.12/classes/ifu/ifu_aln$.class
index bf7d233e..566ff2db 100644
Binary files a/target/scala-2.12/classes/ifu/ifu_aln$.class and b/target/scala-2.12/classes/ifu/ifu_aln$.class differ
diff --git a/target/scala-2.12/classes/ifu/ifu_aln$delayedInit$body.class b/target/scala-2.12/classes/ifu/ifu_aln$delayedInit$body.class
index 091e464d..dcce67b6 100644
Binary files a/target/scala-2.12/classes/ifu/ifu_aln$delayedInit$body.class and b/target/scala-2.12/classes/ifu/ifu_aln$delayedInit$body.class differ