diff --git a/el2_dec.anno.json b/el2_dec.anno.json
index 2a9a9123..4a203e13 100644
--- a/el2_dec.anno.json
+++ b/el2_dec.anno.json
@@ -1,4 +1,23 @@
 [
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_en_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_path_r",
@@ -27,53 +46,7 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_hist",
-    "sources":[
-      "~el2_dec|el2_dec>io_exu_i0_br_hist_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_predict_t",
-    "sources":[
-      "~el2_dec|el2_dec>io_i0_brp_hist",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_toffset"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_immed_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_core_id",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_csr_ren_d",
+    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_half",
     "sources":[
       "~el2_dec|el2_dec>io_ifu_i0_icaf",
       "~el2_dec|el2_dec>io_ifu_i0_dbecc",
@@ -82,12 +55,12 @@
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
@@ -101,60 +74,28 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_lsu_offset_d",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_predict_nt",
     "sources":[
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
       "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_valid",
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_br_immed_d",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_way",
     "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_pc4",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_toffset"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_mul_p_bits_rs1_sign",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_exu_i0_br_way_r"
     ]
   },
   {
@@ -170,7 +111,59 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_bypass_data_d",
+    "sink":"~el2_dec|el2_dec>io_pred_correct_npc_x",
+    "sources":[
+      "~el2_dec|el2_dec>io_exu_i0_pc_x"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_unsign",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_lxor",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_way",
+    "sources":[
+      "~el2_dec|el2_dec>io_i0_brp_bits_way"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_data_d",
     "sources":[
       "~el2_dec|el2_dec>io_lsu_nonblock_load_data",
       "~el2_dec|el2_dec>io_lsu_result_m",
@@ -188,175 +181,12 @@
       "~el2_dec|el2_dec>io_exu_i0_br_error_r",
       "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
       "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_div_p_bits_rem",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_hist",
-    "sources":[
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_pred_correct_npc_x",
-    "sources":[
-      "~el2_dec|el2_dec>io_exu_i0_pc_x"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_slt",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_br_start_error",
-    "sources":[
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_mul_p_valid",
-    "sources":[
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
-      "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
-      "~el2_dec|el2_dec>io_ifu_i0_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_mpc_reset_run_req",
-      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_lsu_fir_error",
-      "~el2_dec|el2_dec>io_mhwakeup",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
-      "~el2_dec|el2_dec>io_dbg_halt_req",
-      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
-      "~el2_dec|el2_dec>io_lsu_idle_any",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
-      "~el2_dec|el2_dec>io_lsu_result_corr_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_prett",
-    "sources":[
-      "~el2_dec|el2_dec>io_i0_brp_prett"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_sub",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_load_ldst_bypass_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_by",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
@@ -380,6 +210,25 @@
       "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_sra",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_dec|el2_dec>io_dec_div_cancel",
@@ -403,104 +252,10 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_en_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_noredir_r",
-    "sources":[
-      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
-      "~el2_dec|el2_dec>io_mpc_reset_run_req",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_lsu_fir_error",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
-      "~el2_dec|el2_dec>io_dbg_halt_req",
-      "~el2_dec|el2_dec>io_mhwakeup",
-      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
-      "~el2_dec|el2_dec>io_lsu_idle_any",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
-      "~el2_dec|el2_dec>io_lsu_result_corr_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_i0_commit_cmt",
-    "sources":[
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_mul_p_bits_low",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_select_pc_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_dbg_rddata",
-    "sources":[
-      "~el2_dec|el2_dec>io_lsu_result_corr_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_bypass_en_d",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_bypass_data_d",
     "sources":[
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data",
+      "~el2_dec|el2_dec>io_lsu_result_m",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
       "~el2_dec|el2_dec>io_ifu_i0_instr",
@@ -515,215 +270,18 @@
       "~el2_dec|el2_dec>io_exu_i0_br_error_r",
       "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
       "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_csr_write",
+    "sink":"~el2_dec|el2_dec>io_div_p_valid",
     "sources":[
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_lor",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_bge",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_br_error",
-    "sources":[
-      "~el2_dec|el2_dec>io_lsu_load_stall_any",
-      "~el2_dec|el2_dec>io_dma_dccm_stall_any",
-      "~el2_dec|el2_dec>io_lsu_store_stall_any",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
-      "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
-      "~el2_dec|el2_dec>io_ifu_i0_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_mpc_reset_run_req",
-      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_lsu_fir_error",
-      "~el2_dec|el2_dec>io_mhwakeup",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
-      "~el2_dec|el2_dec>io_dbg_halt_req",
-      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
-      "~el2_dec|el2_dec>io_lsu_idle_any",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_lsu_result_corr_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_pc_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_pc"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_lsu_valid_raw_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_dma_dccm_stall_any",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
-      "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
-      "~el2_dec|el2_dec>io_ifu_i0_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_leak_one_r",
-    "sources":[
-      "~el2_dec|el2_dec>io_mpc_reset_run_req",
-      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_lsu_fir_error",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
-      "~el2_dec|el2_dec>io_mhwakeup",
-      "~el2_dec|el2_dec>io_dbg_halt_req",
-      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
-      "~el2_dec|el2_dec>io_lsu_idle_any",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
-      "~el2_dec|el2_dec>io_lsu_result_corr_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_err_r",
-    "sources":[
-      "~el2_dec|el2_dec>io_mpc_reset_run_req",
-      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_lsu_fir_error",
-      "~el2_dec|el2_dec>io_mhwakeup",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
-      "~el2_dec|el2_dec>io_dbg_halt_req",
-      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
-      "~el2_dec|el2_dec>io_lsu_idle_any",
-      "~el2_dec|el2_dec>io_lsu_result_corr_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_en_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_data_en",
-    "sources":[
-      "~el2_dec|el2_dec>io_lsu_load_stall_any",
-      "~el2_dec|el2_dec>io_dma_dccm_stall_any",
-      "~el2_dec|el2_dec>io_lsu_store_stall_any",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
       "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
@@ -751,15 +309,34 @@
       "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
       "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pja",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_dec|el2_dec>io_dec_i0_decode_d",
@@ -794,20 +371,147 @@
       "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
       "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_middle",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_noredir_r",
     "sources":[
-      "~el2_dec|el2_dec>io_exu_i0_br_middle_r"
+      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
+      "~el2_dec|el2_dec>io_mpc_reset_run_req",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
+      "~el2_dec|el2_dec>io_lsu_fir_error",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
+      "~el2_dec|el2_dec>io_dbg_halt_req",
+      "~el2_dec|el2_dec>io_mhwakeup",
+      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
+      "~el2_dec|el2_dec>io_lsu_idle_any",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
+      "~el2_dec|el2_dec>io_lsu_result_corr_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pcall",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_lor",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_word",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_i0_commit_cmt",
+    "sources":[
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_add",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_dbg_rddata",
+    "sources":[
+      "~el2_dec|el2_dec>io_lsu_result_corr_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_jal",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
@@ -821,24 +525,322 @@
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_way",
+    "sink":"~el2_dec|el2_dec>io_div_p_bits_unsign",
     "sources":[
-      "~el2_dec|el2_dec>io_exu_i0_br_way_r"
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_div_p_valid",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_sll",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_immed_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_core_id",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_br_start_error",
+    "sources":[
+      "~el2_dec|el2_dec>io_lsu_load_stall_any",
+      "~el2_dec|el2_dec>io_dma_dccm_stall_any",
+      "~el2_dec|el2_dec>io_lsu_store_stall_any",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
+      "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_ifu_i0_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_mpc_reset_run_req",
+      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
+      "~el2_dec|el2_dec>io_lsu_fir_error",
+      "~el2_dec|el2_dec>io_mhwakeup",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
+      "~el2_dec|el2_dec>io_dbg_halt_req",
+      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
+      "~el2_dec|el2_dec>io_lsu_idle_any",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
+      "~el2_dec|el2_dec>io_lsu_result_corr_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_br_immed_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_pc4",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_pc_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_pc"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_hist",
+    "sources":[
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_load",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_leak_one_r",
+    "sources":[
+      "~el2_dec|el2_dec>io_mpc_reset_run_req",
+      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
+      "~el2_dec|el2_dec>io_lsu_fir_error",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
+      "~el2_dec|el2_dec>io_mhwakeup",
+      "~el2_dec|el2_dec>io_dbg_halt_req",
+      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
+      "~el2_dec|el2_dec>io_lsu_idle_any",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
+      "~el2_dec|el2_dec>io_lsu_result_corr_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_en_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_flush_err_r",
+    "sources":[
+      "~el2_dec|el2_dec>io_mpc_reset_run_req",
+      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
+      "~el2_dec|el2_dec>io_lsu_fir_error",
+      "~el2_dec|el2_dec>io_mhwakeup",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
+      "~el2_dec|el2_dec>io_dbg_halt_req",
+      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
+      "~el2_dec|el2_dec>io_lsu_idle_any",
+      "~el2_dec|el2_dec>io_lsu_result_corr_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_store_data_bypass_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_rs1_bypass_en_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_beq",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_lsu_offset_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_alu_decode_d",
     "sources":[
       "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
       "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
@@ -867,18 +869,18 @@
       "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
       "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_land",
+    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_unsign",
     "sources":[
       "~el2_dec|el2_dec>io_ifu_i0_icaf",
       "~el2_dec|el2_dec>io_ifu_i0_dbecc",
@@ -887,73 +889,79 @@
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_sll",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_csr_write",
     "sources":[
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
       "~el2_dec|el2_dec>io_ifu_i0_icaf",
       "~el2_dec|el2_dec>io_ifu_i0_dbecc",
       "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_valid",
+    "sink":"~el2_dec|el2_dec>io_dec_ctl_en",
     "sources":[
-      "~el2_dec|el2_dec>io_exu_i0_br_valid_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_mp_r",
-      "~el2_dec|el2_dec>io_exu_pmu_i0_br_ataken"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_data_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data",
-      "~el2_dec|el2_dec>io_lsu_result_m",
+      "~el2_dec|el2_dec>io_lsu_load_stall_any",
+      "~el2_dec|el2_dec>io_dma_dccm_stall_any",
+      "~el2_dec|el2_dec>io_lsu_store_stall_any",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
+      "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_ifu_i0_valid",
       "~el2_dec|el2_dec>io_dbg_cmd_valid",
       "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_mpc_reset_run_req",
+      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
+      "~el2_dec|el2_dec>io_lsu_fir_error",
+      "~el2_dec|el2_dec>io_mhwakeup",
       "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
+      "~el2_dec|el2_dec>io_dbg_halt_req",
+      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
+      "~el2_dec|el2_dec>io_lsu_idle_any",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
+      "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_blt",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_select_pc_d",
     "sources":[
       "~el2_dec|el2_dec>io_ifu_i0_icaf",
       "~el2_dec|el2_dec>io_ifu_i0_dbecc",
@@ -962,163 +970,12 @@
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pja",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_add",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_lxor",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_store_data_bypass_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_beq",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_jal",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_word",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_fence_i_r",
-    "sources":[
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_way",
-    "sources":[
-      "~el2_dec|el2_dec>io_i0_brp_way"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
@@ -1155,27 +1012,93 @@
       "~el2_dec|el2_dec>io_dbg_halt_req",
       "~el2_dec|el2_dec>io_ifu_miss_state_idle",
       "~el2_dec|el2_dec>io_lsu_idle_any",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
       "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_predict_index_d",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_valid",
     "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_bp_index"
+      "~el2_dec|el2_dec>io_exu_i0_br_valid_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_mp_r",
+      "~el2_dec|el2_dec>io_exu_pmu_i0_br_ataken"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_predict_btag_d",
+    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_load_ldst_bypass_d",
     "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_bp_btag"
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_csr_ren_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+    "sources":[
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_bge",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_br_error",
+    "sources":[
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r"
     ]
   },
   {
@@ -1189,17 +1112,17 @@
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_unsign",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_srl",
     "sources":[
       "~el2_dec|el2_dec>io_ifu_i0_icaf",
       "~el2_dec|el2_dec>io_ifu_i0_dbecc",
@@ -1208,105 +1131,47 @@
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_load",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_fence_i_r",
     "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_br_error",
-    "sources":[
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_toffset",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_alu_decode_d",
-    "sources":[
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
-      "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
-      "~el2_dec|el2_dec>io_ifu_i0_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_mpc_reset_run_req",
-      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
       "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
       "~el2_dec|el2_dec>io_exu_i0_br_error_r",
       "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
       "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_lsu_fir_error",
-      "~el2_dec|el2_dec>io_mhwakeup",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
-      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
-      "~el2_dec|el2_dec>io_dbg_halt_req",
-      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
-      "~el2_dec|el2_dec>io_lsu_idle_any",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
-      "~el2_dec|el2_dec>io_lsu_result_corr_r"
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_gpr_i0_rs2_d",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_en_d",
     "sources":[
       "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_valid",
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write"
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_store",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_sub",
     "sources":[
       "~el2_dec|el2_dec>io_ifu_i0_icaf",
       "~el2_dec|el2_dec>io_ifu_i0_dbecc",
@@ -1315,12 +1180,38 @@
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_slt",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_predict_index_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_bp_index"
     ]
   },
   {
@@ -1358,27 +1249,68 @@
       "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
       "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_br_start_error",
+    "sink":"~el2_dec|el2_dec>io_dec_lsu_valid_raw_d",
     "sources":[
-      "~el2_dec|el2_dec>io_lsu_load_stall_any",
       "~el2_dec|el2_dec>io_dma_dccm_stall_any",
-      "~el2_dec|el2_dec>io_lsu_store_stall_any",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
       "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error",
       "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
+      "~el2_dec|el2_dec>io_ifu_i0_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_by",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_mul_p_valid",
+    "sources":[
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
+      "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
       "~el2_dec|el2_dec>io_ifu_i0_valid",
       "~el2_dec|el2_dec>io_dbg_cmd_valid",
       "~el2_dec|el2_dec>io_dbg_cmd_type",
@@ -1401,17 +1333,18 @@
       "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
       "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_unsign",
+    "sink":"~el2_dec|el2_dec>io_div_p_bits_rem",
     "sources":[
       "~el2_dec|el2_dec>io_ifu_i0_icaf",
       "~el2_dec|el2_dec>io_ifu_i0_dbecc",
@@ -1420,12 +1353,143 @@
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_predict_btag_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_bp_btag"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_predict_t",
+    "sources":[
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_prett",
+    "sources":[
+      "~el2_dec|el2_dec>io_i0_brp_bits_prett"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_store",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_toffset",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_gpr_i0_rs2_d",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_blt",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_i0_ap_land",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_mul_p_bits_rs2_sign",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
@@ -1437,40 +1501,45 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_div_p_bits_unsign",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_br_error",
     "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_lsu_load_stall_any",
+      "~el2_dec|el2_dec>io_dma_dccm_stall_any",
+      "~el2_dec|el2_dec>io_lsu_store_stall_any",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_valid_m",
+      "~el2_dec|el2_dec>io_dbg_cmd_wrdata",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_error",
+      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
+      "~el2_dec|el2_dec>io_ifu_i0_valid",
       "~el2_dec|el2_dec>io_dbg_cmd_valid",
       "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_mpc_reset_run_req",
+      "~el2_dec|el2_dec>io_lsu_fastint_stall_any",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
+      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
+      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
+      "~el2_dec|el2_dec>io_lsu_fir_error",
+      "~el2_dec|el2_dec>io_mhwakeup",
+      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_load_any",
+      "~el2_dec|el2_dec>io_lsu_imprecise_error_store_any",
+      "~el2_dec|el2_dec>io_dbg_halt_req",
+      "~el2_dec|el2_dec>io_ifu_miss_state_idle",
+      "~el2_dec|el2_dec>io_lsu_idle_any",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pret",
-    "sources":[
       "~el2_dec|el2_dec>io_ifu_i0_icaf",
       "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
   {
@@ -1484,25 +1553,6 @@
       "~el2_dec|el2_dec>io_dbg_cmd_write"
     ]
   },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_predict_nt",
-    "sources":[
-      "~el2_dec|el2_dec>io_i0_brp_hist",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_toffset"
-    ]
-  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_dec|el2_dec>io_dec_dbg_cmd_fail",
@@ -1516,45 +1566,14 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_lsu_p_bits_half",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_hist",
     "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_exu_i0_br_hist_r"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_srl",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_ctl_en",
+    "sink":"~el2_dec|el2_dec>io_dec_data_en",
     "sources":[
       "~el2_dec|el2_dec>io_lsu_load_stall_any",
       "~el2_dec|el2_dec>io_dma_dccm_stall_any",
@@ -1586,15 +1605,34 @@
       "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist",
       "~el2_dec|el2_dec>io_lsu_result_corr_r"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dec|el2_dec>io_mul_p_bits_low",
+    "sources":[
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
+      "~el2_dec|el2_dec>io_ifu_i0_instr",
+      "~el2_dec|el2_dec>io_dbg_cmd_valid",
+      "~el2_dec|el2_dec>io_dbg_cmd_type",
+      "~el2_dec|el2_dec>io_dbg_cmd_addr",
+      "~el2_dec|el2_dec>io_dbg_cmd_write",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
+      "~el2_dec|el2_dec>io_i0_brp_valid",
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pc4",
@@ -1604,7 +1642,7 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pcall",
+    "sink":"~el2_dec|el2_dec>io_mul_p_bits_rs1_sign",
     "sources":[
       "~el2_dec|el2_dec>io_ifu_i0_icaf",
       "~el2_dec|el2_dec>io_ifu_i0_dbecc",
@@ -1613,76 +1651,38 @@
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_dec_i0_rs2_bypass_en_d",
+    "sink":"~el2_dec|el2_dec>io_dec_i0_predict_p_d_bits_pret",
     "sources":[
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_valid",
-      "~el2_dec|el2_dec>io_lsu_nonblock_load_data_tag",
+      "~el2_dec|el2_dec>io_ifu_i0_icaf",
+      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
       "~el2_dec|el2_dec>io_ifu_i0_instr",
       "~el2_dec|el2_dec>io_dbg_cmd_valid",
       "~el2_dec|el2_dec>io_dbg_cmd_type",
       "~el2_dec|el2_dec>io_dbg_cmd_addr",
       "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_valid",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_single_ecc_error",
-      "~el2_dec|el2_dec>io_exu_i0_br_error_r",
-      "~el2_dec|el2_dec>io_exu_i0_br_start_error_r",
-      "~el2_dec|el2_dec>io_lsu_error_pkt_r_bits_inst_type",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_start_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_br_error",
+      "~el2_dec|el2_dec>io_i0_brp_bits_ret",
       "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_i0_brp_bits_toffset",
+      "~el2_dec|el2_dec>io_i0_brp_bits_hist"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_mul_p_bits_rs2_sign",
+    "sink":"~el2_dec|el2_dec>io_dec_tlu_br0_r_pkt_bits_middle",
     "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_dec|el2_dec>io_i0_ap_sra",
-    "sources":[
-      "~el2_dec|el2_dec>io_ifu_i0_icaf",
-      "~el2_dec|el2_dec>io_ifu_i0_dbecc",
-      "~el2_dec|el2_dec>io_ifu_i0_instr",
-      "~el2_dec|el2_dec>io_dbg_cmd_valid",
-      "~el2_dec|el2_dec>io_dbg_cmd_type",
-      "~el2_dec|el2_dec>io_dbg_cmd_addr",
-      "~el2_dec|el2_dec>io_dbg_cmd_write",
-      "~el2_dec|el2_dec>io_i0_brp_br_start_error",
-      "~el2_dec|el2_dec>io_i0_brp_br_error",
-      "~el2_dec|el2_dec>io_i0_brp_ret",
-      "~el2_dec|el2_dec>io_i0_brp_valid",
-      "~el2_dec|el2_dec>io_i0_brp_toffset",
-      "~el2_dec|el2_dec>io_i0_brp_hist"
+      "~el2_dec|el2_dec>io_exu_i0_br_middle_r"
     ]
   },
   {
diff --git a/el2_dec.fir b/el2_dec.fir
index c15f6299..c713d335 100644
--- a/el2_dec.fir
+++ b/el2_dec.fir
@@ -3,7 +3,7 @@ circuit el2_dec :
   module el2_dec_ib_ctl : 
     input clock : Clock
     input reset : Reset
-    output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>}
+    output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>}
     
     io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 8:31]
     io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 9:31]
@@ -11,14 +11,15 @@ circuit el2_dec :
     io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 11:31]
     io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 12:31]
     io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 13:31]
-    io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.valid <= io.i0_brp.bits.valid @[el2_dec_ib_ctl.scala 14:31]
     io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 14:31]
     io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 15:31]
     io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 16:31]
@@ -2576,7 +2577,7 @@ circuit el2_dec :
   module el2_dec_decode_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>}
     
     wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[el2_dec_decode_ctl.scala 126:27]
     _T.bits.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
@@ -2785,9 +2786,9 @@ circuit el2_dec :
     io.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 230:43]
     io.dec_i0_predict_p_d.bits.pja <= i0_pja @[el2_dec_decode_ctl.scala 231:43]
     io.dec_i0_predict_p_d.bits.pret <= i0_pret @[el2_dec_decode_ctl.scala 232:43]
-    io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.prett @[el2_dec_decode_ctl.scala 233:43]
+    io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[el2_dec_decode_ctl.scala 233:43]
     io.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 234:43]
-    io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.hist @[el2_dec_decode_ctl.scala 235:43]
+    io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[el2_dec_decode_ctl.scala 235:43]
     node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 236:55]
     io.dec_i0_predict_p_d.valid <= _T_19 @[el2_dec_decode_ctl.scala 236:38]
     node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 237:75]
@@ -2795,34 +2796,34 @@ circuit el2_dec :
     node _T_22 = or(_T_21, i0_pret_raw) @[el2_dec_decode_ctl.scala 237:103]
     node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 237:56]
     node i0_notbr_error = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 237:54]
-    node _T_24 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:67]
+    node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:72]
     node _T_25 = and(i0_brp_valid, _T_24) @[el2_dec_decode_ctl.scala 240:47]
-    node _T_26 = neq(io.dec_i0_brp.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:96]
-    node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:71]
-    node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:116]
-    node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:114]
-    node _T_29 = and(i0_brp_valid, io.dec_i0_brp.ret) @[el2_dec_decode_ctl.scala 241:47]
-    node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:69]
-    node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:67]
-    node _T_31 = or(io.dec_i0_brp.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:57]
-    node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:74]
-    node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:96]
+    node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:106]
+    node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:76]
+    node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:126]
+    node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:124]
+    node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[el2_dec_decode_ctl.scala 241:47]
+    node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:74]
+    node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:72]
+    node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:62]
+    node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:79]
+    node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:101]
     node _T_33 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 243:72]
     node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 243:94]
     node _T_35 = and(_T_33, _T_34) @[el2_dec_decode_ctl.scala 243:92]
     io.dec_i0_predict_p_d.bits.br_error <= _T_35 @[el2_dec_decode_ctl.scala 243:56]
-    node _T_36 = and(io.dec_i0_brp.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:89]
-    node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:111]
-    node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:109]
+    node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:94]
+    node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:116]
+    node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:114]
     io.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[el2_dec_decode_ctl.scala 244:56]
     io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 245:32]
     io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 246:32]
-    node _T_39 = or(i0_br_error, io.dec_i0_brp.br_start_error) @[el2_dec_decode_ctl.scala 247:47]
-    node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:81]
-    node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:79]
+    node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[el2_dec_decode_ctl.scala 247:47]
+    node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:86]
+    node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:84]
     io.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 248:49]
     io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 249:32]
-    io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.way @[el2_dec_decode_ctl.scala 250:56]
+    io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[el2_dec_decode_ctl.scala 250:56]
     node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 256:36]
     i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 259:9]
     i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 259:9]
@@ -2989,13 +2990,13 @@ circuit el2_dec :
     node _T_44 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 274:38]
     node _T_45 = or(_T_44, i0_pja) @[el2_dec_decode_ctl.scala 274:49]
     node i0_predict_br = or(_T_45, i0_pret) @[el2_dec_decode_ctl.scala 274:58]
-    node _T_46 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:46]
-    node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:50]
+    node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:51]
+    node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:55]
     node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 276:26]
-    node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:66]
-    node _T_49 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:46]
-    node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:50]
-    node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:66]
+    node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:71]
+    node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:51]
+    node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:55]
+    node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:71]
     node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 278:20]
     io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 280:26]
     io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 281:26]
@@ -13598,7 +13599,7 @@ circuit el2_dec :
   module el2_dec_tlu_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>}
+    output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>}
     
     wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 236:59]
     wire pause_expired_wb : UInt<1>
@@ -14561,12 +14562,12 @@ circuit el2_dec :
     node _T_461 = not(io.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 727:118]
     node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 727:116]
     node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 727:94]
-    io.dec_tlu_br0_r_pkt.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:49]
-    io.dec_tlu_br0_r_pkt.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49]
-    io.dec_tlu_br0_r_pkt.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:41]
+    io.dec_tlu_br0_r_pkt.bits.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:57]
+    io.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49]
+    io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:49]
     io.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 733:49]
-    io.dec_tlu_br0_r_pkt.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:49]
-    io.dec_tlu_br0_r_pkt.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:49]
+    io.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:57]
+    io.dec_tlu_br0_r_pkt.bits.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:57]
     node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 738:51]
     node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64]
     node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90]
@@ -16931,7 +16932,7 @@ circuit el2_dec :
   module el2_dec : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>}
     
     wire dec_i0_inst_wb1 : UInt<32>
     dec_i0_inst_wb1 <= UInt<1>("h00")
@@ -16967,14 +16968,15 @@ circuit el2_dec :
     instbuff.io.dbg_cmd_write <= io.dbg_cmd_write @[el2_dec.scala 298:45]
     instbuff.io.dbg_cmd_type <= io.dbg_cmd_type @[el2_dec.scala 299:45]
     instbuff.io.dbg_cmd_addr <= io.dbg_cmd_addr @[el2_dec.scala 300:45]
-    instbuff.io.i0_brp.ret <= io.i0_brp.ret @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.way <= io.i0_brp.way @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.prett <= io.i0_brp.prett @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.bank <= io.i0_brp.bank @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.br_error <= io.i0_brp.br_error @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.hist <= io.i0_brp.hist @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.toffset <= io.i0_brp.toffset @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.valid <= io.i0_brp.bits.valid @[el2_dec.scala 301:55]
     instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 301:55]
     instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 302:35]
     instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 303:35]
@@ -17041,14 +17043,15 @@ circuit el2_dec :
     decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 351:48]
     decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 352:48]
     decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 353:48]
-    decode.io.dec_i0_brp.ret <= instbuff.io.dec_i0_brp.ret @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.way <= instbuff.io.dec_i0_brp.way @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.prett <= instbuff.io.dec_i0_brp.prett @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.bank <= instbuff.io.dec_i0_brp.bank @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.br_start_error <= instbuff.io.dec_i0_brp.br_start_error @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.br_error <= instbuff.io.dec_i0_brp.br_error @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.hist <= instbuff.io.dec_i0_brp.hist @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.toffset <= instbuff.io.dec_i0_brp.toffset @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.valid <= instbuff.io.dec_i0_brp.bits.valid @[el2_dec.scala 354:48]
     decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 354:48]
     decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 355:48]
     decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 356:48]
@@ -17337,11 +17340,11 @@ circuit el2_dec :
     io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[el2_dec.scala 554:29]
     io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[el2_dec.scala 555:29]
     io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[el2_dec.scala 556:29]
-    io.dec_tlu_br0_r_pkt.middle <= tlu.io.dec_tlu_br0_r_pkt.middle @[el2_dec.scala 557:42]
-    io.dec_tlu_br0_r_pkt.way <= tlu.io.dec_tlu_br0_r_pkt.way @[el2_dec.scala 557:42]
-    io.dec_tlu_br0_r_pkt.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.br_start_error @[el2_dec.scala 557:42]
-    io.dec_tlu_br0_r_pkt.br_error <= tlu.io.dec_tlu_br0_r_pkt.br_error @[el2_dec.scala 557:42]
-    io.dec_tlu_br0_r_pkt.hist <= tlu.io.dec_tlu_br0_r_pkt.hist @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.dec_tlu_br0_r_pkt.bits.middle @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.way <= tlu.io.dec_tlu_br0_r_pkt.bits.way @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.dec_tlu_br0_r_pkt.bits.hist @[el2_dec.scala 557:42]
     io.dec_tlu_br0_r_pkt.valid <= tlu.io.dec_tlu_br0_r_pkt.valid @[el2_dec.scala 557:42]
     io.dec_tlu_i0_commit_cmt <= tlu.io.dec_tlu_i0_commit_cmt @[el2_dec.scala 558:34]
     io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 559:34]
diff --git a/el2_dec.v b/el2_dec.v
index 0049f99a..f93b195c 100644
--- a/el2_dec.v
+++ b/el2_dec.v
@@ -4,13 +4,13 @@ module el2_dec_ib_ctl(
   input  [1:0]  io_dbg_cmd_type,
   input  [31:0] io_dbg_cmd_addr,
   input         io_i0_brp_valid,
-  input  [11:0] io_i0_brp_toffset,
-  input  [1:0]  io_i0_brp_hist,
-  input         io_i0_brp_br_error,
-  input         io_i0_brp_br_start_error,
-  input  [30:0] io_i0_brp_prett,
-  input         io_i0_brp_way,
-  input         io_i0_brp_ret,
+  input  [11:0] io_i0_brp_bits_toffset,
+  input  [1:0]  io_i0_brp_bits_hist,
+  input         io_i0_brp_bits_br_error,
+  input         io_i0_brp_bits_br_start_error,
+  input  [30:0] io_i0_brp_bits_prett,
+  input         io_i0_brp_bits_way,
+  input         io_i0_brp_bits_ret,
   input  [7:0]  io_ifu_i0_bp_index,
   input  [7:0]  io_ifu_i0_bp_fghr,
   input  [4:0]  io_ifu_i0_bp_btag,
@@ -28,13 +28,13 @@ module el2_dec_ib_ctl(
   output [30:0] io_dec_i0_pc_d,
   output        io_dec_i0_pc4_d,
   output        io_dec_i0_brp_valid,
-  output [11:0] io_dec_i0_brp_toffset,
-  output [1:0]  io_dec_i0_brp_hist,
-  output        io_dec_i0_brp_br_error,
-  output        io_dec_i0_brp_br_start_error,
-  output [30:0] io_dec_i0_brp_prett,
-  output        io_dec_i0_brp_way,
-  output        io_dec_i0_brp_ret,
+  output [11:0] io_dec_i0_brp_bits_toffset,
+  output [1:0]  io_dec_i0_brp_bits_hist,
+  output        io_dec_i0_brp_bits_br_error,
+  output        io_dec_i0_brp_bits_br_start_error,
+  output [30:0] io_dec_i0_brp_bits_prett,
+  output        io_dec_i0_brp_bits_way,
+  output        io_dec_i0_brp_bits_ret,
   output [7:0]  io_dec_i0_bp_index,
   output [7:0]  io_dec_i0_bp_fghr,
   output [4:0]  io_dec_i0_bp_btag,
@@ -78,13 +78,13 @@ module el2_dec_ib_ctl(
   assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31]
   assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31]
   assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec_ib_ctl.scala 14:31]
   assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31]
   assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31]
   assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31]
@@ -855,13 +855,13 @@ module el2_dec_decode_ctl(
   input  [1:0]  io_dec_i0_icaf_type_d,
   input         io_dec_i0_dbecc_d,
   input         io_dec_i0_brp_valid,
-  input  [11:0] io_dec_i0_brp_toffset,
-  input  [1:0]  io_dec_i0_brp_hist,
-  input         io_dec_i0_brp_br_error,
-  input         io_dec_i0_brp_br_start_error,
-  input  [30:0] io_dec_i0_brp_prett,
-  input         io_dec_i0_brp_way,
-  input         io_dec_i0_brp_ret,
+  input  [11:0] io_dec_i0_brp_bits_toffset,
+  input  [1:0]  io_dec_i0_brp_bits_hist,
+  input         io_dec_i0_brp_bits_br_error,
+  input         io_dec_i0_brp_bits_br_start_error,
+  input  [30:0] io_dec_i0_brp_bits_prett,
+  input         io_dec_i0_brp_bits_way,
+  input         io_dec_i0_brp_bits_ret,
   input  [7:0]  io_dec_i0_bp_index,
   input  [7:0]  io_dec_i0_bp_fghr,
   input  [4:0]  io_dec_i0_bp_btag,
@@ -1285,21 +1285,21 @@ module el2_dec_decode_ctl(
   wire  _T_22 = _T_21 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 237:103]
   wire  _T_23 = ~_T_22; // @[el2_dec_decode_ctl.scala 237:56]
   wire  i0_notbr_error = i0_brp_valid & _T_23; // @[el2_dec_decode_ctl.scala 237:54]
-  wire  _T_31 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:57]
-  wire  _T_25 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 240:47]
+  wire  _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:62]
+  wire  _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[el2_dec_decode_ctl.scala 240:47]
   wire  _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 415:41]
   wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58]
   wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 415:26]
-  wire  _T_26 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:96]
-  wire  _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:71]
-  wire  _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:116]
-  wire  i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:114]
-  wire  _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:74]
-  wire  _T_29 = i0_brp_valid & io_dec_i0_brp_ret; // @[el2_dec_decode_ctl.scala 241:47]
-  wire  i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:67]
-  wire  i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:96]
-  wire  _T_39 = i0_br_error | io_dec_i0_brp_br_start_error; // @[el2_dec_decode_ctl.scala 247:47]
-  wire  i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:79]
+  wire  _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:106]
+  wire  _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:76]
+  wire  _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:126]
+  wire  i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:124]
+  wire  _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:79]
+  wire  _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[el2_dec_decode_ctl.scala 241:47]
+  wire  i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:72]
+  wire  i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:101]
+  wire  _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[el2_dec_decode_ctl.scala 247:47]
+  wire  i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:84]
   wire  i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 256:36]
   wire  _T_41 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 260:25]
   wire  i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
@@ -1344,7 +1344,7 @@ module el2_dec_decode_ctl(
   wire  _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32]
   wire  i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 644:46]
   wire  _T_33 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 243:72]
-  wire  _T_36 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:89]
+  wire  _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:94]
   wire  i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
   wire  i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 260:50]
   wire  i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
@@ -1421,7 +1421,7 @@ module el2_dec_decode_ctl(
   wire  _T_45 = _T_44 | i0_pja; // @[el2_dec_decode_ctl.scala 274:49]
   wire  i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 419:32]
   wire  i0_predict_br = _T_45 | i0_pret; // @[el2_dec_decode_ctl.scala 274:58]
-  wire  _T_47 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:50]
+  wire  _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:55]
   wire  _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26]
   wire  i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20]
   wire  cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63]
@@ -2208,15 +2208,15 @@ module el2_dec_decode_ctl(
   assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 764:25]
   assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 236:38]
   assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 234:43]
-  assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_hist; // @[el2_dec_decode_ctl.scala 235:43]
+  assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[el2_dec_decode_ctl.scala 235:43]
   assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 248:49]
   assign io_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[el2_dec_decode_ctl.scala 243:56]
   assign io_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[el2_dec_decode_ctl.scala 244:56]
-  assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_prett; // @[el2_dec_decode_ctl.scala 233:43]
+  assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[el2_dec_decode_ctl.scala 233:43]
   assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 230:43]
   assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 232:43]
   assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 231:43]
-  assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_way; // @[el2_dec_decode_ctl.scala 250:56]
+  assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[el2_dec_decode_ctl.scala 250:56]
   assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 249:32]
   assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 245:32]
   assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 246:32]
@@ -9251,11 +9251,11 @@ module el2_dec_tlu_ctl(
   output [31:0] io_dec_csr_rddata_d,
   output        io_dec_csr_legal_d,
   output        io_dec_tlu_br0_r_pkt_valid,
-  output [1:0]  io_dec_tlu_br0_r_pkt_hist,
-  output        io_dec_tlu_br0_r_pkt_br_error,
-  output        io_dec_tlu_br0_r_pkt_br_start_error,
-  output        io_dec_tlu_br0_r_pkt_way,
-  output        io_dec_tlu_br0_r_pkt_middle,
+  output [1:0]  io_dec_tlu_br0_r_pkt_bits_hist,
+  output        io_dec_tlu_br0_r_pkt_bits_br_error,
+  output        io_dec_tlu_br0_r_pkt_bits_br_start_error,
+  output        io_dec_tlu_br0_r_pkt_bits_way,
+  output        io_dec_tlu_br0_r_pkt_bits_middle,
   output        io_dec_tlu_i0_kill_writeb_wb,
   output        io_dec_tlu_flush_lower_wb,
   output        io_dec_tlu_i0_commit_cmt,
@@ -10896,11 +10896,11 @@ module el2_dec_tlu_ctl(
   assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40]
   assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22]
   assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49]
-  assign io_dec_tlu_br0_r_pkt_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:49]
-  assign io_dec_tlu_br0_r_pkt_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49]
-  assign io_dec_tlu_br0_r_pkt_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:41]
-  assign io_dec_tlu_br0_r_pkt_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:49]
-  assign io_dec_tlu_br0_r_pkt_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:49]
+  assign io_dec_tlu_br0_r_pkt_bits_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:57]
+  assign io_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49]
+  assign io_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:49]
+  assign io_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:57]
+  assign io_dec_tlu_br0_r_pkt_bits_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:57]
   assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33]
   assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33]
   assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28]
@@ -12777,14 +12777,15 @@ module el2_dec(
   input         io_ifu_i0_dbecc,
   input         io_lsu_idle_any,
   input         io_i0_brp_valid,
-  input  [11:0] io_i0_brp_toffset,
-  input  [1:0]  io_i0_brp_hist,
-  input         io_i0_brp_br_error,
-  input         io_i0_brp_br_start_error,
-  input         io_i0_brp_bank,
-  input  [30:0] io_i0_brp_prett,
-  input         io_i0_brp_way,
-  input         io_i0_brp_ret,
+  input         io_i0_brp_bits_valid,
+  input  [11:0] io_i0_brp_bits_toffset,
+  input  [1:0]  io_i0_brp_bits_hist,
+  input         io_i0_brp_bits_br_error,
+  input         io_i0_brp_bits_br_start_error,
+  input         io_i0_brp_bits_bank,
+  input  [30:0] io_i0_brp_bits_prett,
+  input         io_i0_brp_bits_way,
+  input         io_i0_brp_bits_ret,
   input  [7:0]  io_ifu_i0_bp_index,
   input  [7:0]  io_ifu_i0_bp_fghr,
   input  [4:0]  io_ifu_i0_bp_btag,
@@ -12957,11 +12958,11 @@ module el2_dec(
   output        io_dec_tlu_fence_i_r,
   output [30:0] io_pred_correct_npc_x,
   output        io_dec_tlu_br0_r_pkt_valid,
-  output [1:0]  io_dec_tlu_br0_r_pkt_hist,
-  output        io_dec_tlu_br0_r_pkt_br_error,
-  output        io_dec_tlu_br0_r_pkt_br_start_error,
-  output        io_dec_tlu_br0_r_pkt_way,
-  output        io_dec_tlu_br0_r_pkt_middle,
+  output [1:0]  io_dec_tlu_br0_r_pkt_bits_hist,
+  output        io_dec_tlu_br0_r_pkt_bits_br_error,
+  output        io_dec_tlu_br0_r_pkt_bits_br_start_error,
+  output        io_dec_tlu_br0_r_pkt_bits_way,
+  output        io_dec_tlu_br0_r_pkt_bits_middle,
   output        io_dec_tlu_perfcnt0,
   output        io_dec_tlu_perfcnt1,
   output        io_dec_tlu_perfcnt2,
@@ -13016,13 +13017,13 @@ module el2_dec(
   wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 285:24]
   wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 285:24]
   wire  instbuff_io_i0_brp_valid; // @[el2_dec.scala 285:24]
-  wire [11:0] instbuff_io_i0_brp_toffset; // @[el2_dec.scala 285:24]
-  wire [1:0] instbuff_io_i0_brp_hist; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_i0_brp_br_error; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_i0_brp_br_start_error; // @[el2_dec.scala 285:24]
-  wire [30:0] instbuff_io_i0_brp_prett; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_i0_brp_way; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_i0_brp_ret; // @[el2_dec.scala 285:24]
+  wire [11:0] instbuff_io_i0_brp_bits_toffset; // @[el2_dec.scala 285:24]
+  wire [1:0] instbuff_io_i0_brp_bits_hist; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_i0_brp_bits_br_error; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24]
+  wire [30:0] instbuff_io_i0_brp_bits_prett; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_i0_brp_bits_way; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_i0_brp_bits_ret; // @[el2_dec.scala 285:24]
   wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 285:24]
   wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 285:24]
   wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 285:24]
@@ -13040,13 +13041,13 @@ module el2_dec(
   wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 285:24]
   wire  instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 285:24]
   wire  instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 285:24]
-  wire [11:0] instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 285:24]
-  wire [1:0] instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 285:24]
-  wire [30:0] instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 285:24]
+  wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 285:24]
+  wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24]
+  wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 285:24]
   wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 285:24]
   wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 285:24]
   wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 285:24]
@@ -13085,13 +13086,13 @@ module el2_dec(
   wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 286:22]
   wire  decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 286:22]
   wire  decode_io_dec_i0_brp_valid; // @[el2_dec.scala 286:22]
-  wire [11:0] decode_io_dec_i0_brp_toffset; // @[el2_dec.scala 286:22]
-  wire [1:0] decode_io_dec_i0_brp_hist; // @[el2_dec.scala 286:22]
-  wire  decode_io_dec_i0_brp_br_error; // @[el2_dec.scala 286:22]
-  wire  decode_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 286:22]
-  wire [30:0] decode_io_dec_i0_brp_prett; // @[el2_dec.scala 286:22]
-  wire  decode_io_dec_i0_brp_way; // @[el2_dec.scala 286:22]
-  wire  decode_io_dec_i0_brp_ret; // @[el2_dec.scala 286:22]
+  wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 286:22]
+  wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 286:22]
+  wire  decode_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 286:22]
+  wire  decode_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 286:22]
+  wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 286:22]
+  wire  decode_io_dec_i0_brp_bits_way; // @[el2_dec.scala 286:22]
+  wire  decode_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 286:22]
   wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 286:22]
   wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 286:22]
   wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 286:22]
@@ -13397,11 +13398,11 @@ module el2_dec(
   wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_csr_legal_d; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 288:19]
-  wire [1:0] tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 288:19]
-  wire  tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 288:19]
-  wire  tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 288:19]
-  wire  tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 288:19]
-  wire  tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 288:19]
+  wire [1:0] tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 288:19]
+  wire  tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 288:19]
+  wire  tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 288:19]
+  wire  tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 288:19]
+  wire  tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 288:19]
@@ -13468,13 +13469,13 @@ module el2_dec(
     .io_dbg_cmd_type(instbuff_io_dbg_cmd_type),
     .io_dbg_cmd_addr(instbuff_io_dbg_cmd_addr),
     .io_i0_brp_valid(instbuff_io_i0_brp_valid),
-    .io_i0_brp_toffset(instbuff_io_i0_brp_toffset),
-    .io_i0_brp_hist(instbuff_io_i0_brp_hist),
-    .io_i0_brp_br_error(instbuff_io_i0_brp_br_error),
-    .io_i0_brp_br_start_error(instbuff_io_i0_brp_br_start_error),
-    .io_i0_brp_prett(instbuff_io_i0_brp_prett),
-    .io_i0_brp_way(instbuff_io_i0_brp_way),
-    .io_i0_brp_ret(instbuff_io_i0_brp_ret),
+    .io_i0_brp_bits_toffset(instbuff_io_i0_brp_bits_toffset),
+    .io_i0_brp_bits_hist(instbuff_io_i0_brp_bits_hist),
+    .io_i0_brp_bits_br_error(instbuff_io_i0_brp_bits_br_error),
+    .io_i0_brp_bits_br_start_error(instbuff_io_i0_brp_bits_br_start_error),
+    .io_i0_brp_bits_prett(instbuff_io_i0_brp_bits_prett),
+    .io_i0_brp_bits_way(instbuff_io_i0_brp_bits_way),
+    .io_i0_brp_bits_ret(instbuff_io_i0_brp_bits_ret),
     .io_ifu_i0_bp_index(instbuff_io_ifu_i0_bp_index),
     .io_ifu_i0_bp_fghr(instbuff_io_ifu_i0_bp_fghr),
     .io_ifu_i0_bp_btag(instbuff_io_ifu_i0_bp_btag),
@@ -13492,13 +13493,13 @@ module el2_dec(
     .io_dec_i0_pc_d(instbuff_io_dec_i0_pc_d),
     .io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d),
     .io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid),
-    .io_dec_i0_brp_toffset(instbuff_io_dec_i0_brp_toffset),
-    .io_dec_i0_brp_hist(instbuff_io_dec_i0_brp_hist),
-    .io_dec_i0_brp_br_error(instbuff_io_dec_i0_brp_br_error),
-    .io_dec_i0_brp_br_start_error(instbuff_io_dec_i0_brp_br_start_error),
-    .io_dec_i0_brp_prett(instbuff_io_dec_i0_brp_prett),
-    .io_dec_i0_brp_way(instbuff_io_dec_i0_brp_way),
-    .io_dec_i0_brp_ret(instbuff_io_dec_i0_brp_ret),
+    .io_dec_i0_brp_bits_toffset(instbuff_io_dec_i0_brp_bits_toffset),
+    .io_dec_i0_brp_bits_hist(instbuff_io_dec_i0_brp_bits_hist),
+    .io_dec_i0_brp_bits_br_error(instbuff_io_dec_i0_brp_bits_br_error),
+    .io_dec_i0_brp_bits_br_start_error(instbuff_io_dec_i0_brp_bits_br_start_error),
+    .io_dec_i0_brp_bits_prett(instbuff_io_dec_i0_brp_bits_prett),
+    .io_dec_i0_brp_bits_way(instbuff_io_dec_i0_brp_bits_way),
+    .io_dec_i0_brp_bits_ret(instbuff_io_dec_i0_brp_bits_ret),
     .io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index),
     .io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr),
     .io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag),
@@ -13539,13 +13540,13 @@ module el2_dec(
     .io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d),
     .io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d),
     .io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid),
-    .io_dec_i0_brp_toffset(decode_io_dec_i0_brp_toffset),
-    .io_dec_i0_brp_hist(decode_io_dec_i0_brp_hist),
-    .io_dec_i0_brp_br_error(decode_io_dec_i0_brp_br_error),
-    .io_dec_i0_brp_br_start_error(decode_io_dec_i0_brp_br_start_error),
-    .io_dec_i0_brp_prett(decode_io_dec_i0_brp_prett),
-    .io_dec_i0_brp_way(decode_io_dec_i0_brp_way),
-    .io_dec_i0_brp_ret(decode_io_dec_i0_brp_ret),
+    .io_dec_i0_brp_bits_toffset(decode_io_dec_i0_brp_bits_toffset),
+    .io_dec_i0_brp_bits_hist(decode_io_dec_i0_brp_bits_hist),
+    .io_dec_i0_brp_bits_br_error(decode_io_dec_i0_brp_bits_br_error),
+    .io_dec_i0_brp_bits_br_start_error(decode_io_dec_i0_brp_bits_br_start_error),
+    .io_dec_i0_brp_bits_prett(decode_io_dec_i0_brp_bits_prett),
+    .io_dec_i0_brp_bits_way(decode_io_dec_i0_brp_bits_way),
+    .io_dec_i0_brp_bits_ret(decode_io_dec_i0_brp_bits_ret),
     .io_dec_i0_bp_index(decode_io_dec_i0_bp_index),
     .io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr),
     .io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag),
@@ -13855,11 +13856,11 @@ module el2_dec(
     .io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d),
     .io_dec_csr_legal_d(tlu_io_dec_csr_legal_d),
     .io_dec_tlu_br0_r_pkt_valid(tlu_io_dec_tlu_br0_r_pkt_valid),
-    .io_dec_tlu_br0_r_pkt_hist(tlu_io_dec_tlu_br0_r_pkt_hist),
-    .io_dec_tlu_br0_r_pkt_br_error(tlu_io_dec_tlu_br0_r_pkt_br_error),
-    .io_dec_tlu_br0_r_pkt_br_start_error(tlu_io_dec_tlu_br0_r_pkt_br_start_error),
-    .io_dec_tlu_br0_r_pkt_way(tlu_io_dec_tlu_br0_r_pkt_way),
-    .io_dec_tlu_br0_r_pkt_middle(tlu_io_dec_tlu_br0_r_pkt_middle),
+    .io_dec_tlu_br0_r_pkt_bits_hist(tlu_io_dec_tlu_br0_r_pkt_bits_hist),
+    .io_dec_tlu_br0_r_pkt_bits_br_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_error),
+    .io_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error),
+    .io_dec_tlu_br0_r_pkt_bits_way(tlu_io_dec_tlu_br0_r_pkt_bits_way),
+    .io_dec_tlu_br0_r_pkt_bits_middle(tlu_io_dec_tlu_br0_r_pkt_bits_middle),
     .io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb),
     .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb),
     .io_dec_tlu_i0_commit_cmt(tlu_io_dec_tlu_i0_commit_cmt),
@@ -14055,11 +14056,11 @@ module el2_dec(
   assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 562:34]
   assign io_pred_correct_npc_x = decode_io_pred_correct_npc_x; // @[el2_dec.scala 411:40]
   assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_hist = tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_br_error = tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_br_start_error = tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_way = tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_middle = tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_hist = tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_way = tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_middle = tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 557:42]
   assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 565:29]
   assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 566:29]
   assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 567:29]
@@ -14111,13 +14112,13 @@ module el2_dec(
   assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 299:45]
   assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 300:45]
   assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_hist = io_i0_brp_hist; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_prett = io_i0_brp_prett; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_way = io_i0_brp_way; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_ret = io_i0_brp_ret; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec.scala 301:55]
   assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec.scala 302:35]
   assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 303:35]
   assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 304:35]
@@ -14156,13 +14157,13 @@ module el2_dec(
   assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 352:48]
   assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:48]
   assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_toffset = instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_hist = instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_br_error = instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_br_start_error = instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_prett = instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_way = instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_ret = instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 354:48]
   assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 355:48]
   assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 356:48]
   assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 357:48]
diff --git a/el2_ifu.anno.json b/el2_ifu.anno.json
index 9d6b4228..c879cc05 100644
--- a/el2_ifu.anno.json
+++ b/el2_ifu.anno.json
@@ -1,28 +1,88 @@
 [
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall",
+    "sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error",
     "sources":[
+      "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
+      "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
       "~el2_ifu|el2_ifu>io_exu_flush_final",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
-      "~el2_ifu|el2_ifu>io_ic_rd_data",
-      "~el2_ifu|el2_ifu>io_dec_i0_decode_d",
       "~el2_ifu|el2_ifu>io_ic_rd_hit",
       "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
       "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_iccm_wren",
+    "sink":"~el2_ifu|el2_ifu>io_ic_rd_en",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_exu_flush_final",
+      "~el2_ifu|el2_ifu>io_dec_tlu_force_halt",
+      "~el2_ifu|el2_ifu>io_ic_rd_hit",
+      "~el2_ifu|el2_ifu>io_exu_flush_path_final",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff",
+      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
+      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
+      "~el2_ifu|el2_ifu>io_ic_rd_data",
+      "~el2_ifu|el2_ifu>io_dec_i0_decode_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_iccm_rden",
     "sources":[
-      "~el2_ifu|el2_ifu>io_dma_mem_write",
       "~el2_ifu|el2_ifu>io_dma_iccm_req",
+      "~el2_ifu|el2_ifu>io_dma_mem_write",
+      "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
+      "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
+      "~el2_ifu|el2_ifu>io_exu_flush_final",
+      "~el2_ifu|el2_ifu>io_ic_rd_hit",
+      "~el2_ifu|el2_ifu>io_exu_flush_path_final",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
+      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
+      "~el2_ifu|el2_ifu>io_ic_rd_data",
+      "~el2_ifu|el2_ifu>io_dec_i0_decode_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_iccm_rd_data",
+      "~el2_ifu|el2_ifu>io_exu_flush_final",
+      "~el2_ifu|el2_ifu>io_ic_rd_hit",
+      "~el2_ifu|el2_ifu>io_ifu_axi_rid",
+      "~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
+      "~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
+      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
+      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_iccm_ready",
+    "sources":[
       "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
       "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
       "~el2_ifu|el2_ifu>io_exu_flush_final",
@@ -32,8 +92,8 @@
       "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
       "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
       "~el2_ifu|el2_ifu>io_dec_i0_decode_d",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
@@ -62,6 +122,58 @@
       "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_rd_valid"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
+      "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
+      "~el2_ifu|el2_ifu>io_exu_flush_final",
+      "~el2_ifu|el2_ifu>io_ic_rd_hit",
+      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
+      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_ic_eccerr",
+      "~el2_ifu|el2_ifu>io_ic_tag_perr",
+      "~el2_ifu|el2_ifu>io_ic_rd_hit",
+      "~el2_ifu|el2_ifu>io_exu_flush_final",
+      "~el2_ifu|el2_ifu>io_ifu_axi_rid",
+      "~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
+      "~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
+      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
+      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_exu_flush_final",
+      "~el2_ifu|el2_ifu>io_ic_rd_hit",
+      "~el2_ifu|el2_ifu>io_ifu_axi_rid",
+      "~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
+      "~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
+      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
+      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu|el2_ifu>io_iccm_wr_data",
@@ -77,8 +189,8 @@
       "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
       "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
       "~el2_ifu|el2_ifu>io_dec_i0_decode_d",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
@@ -101,173 +213,6 @@
       "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wr_valid"
     ]
   },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_ic_eccerr",
-      "~el2_ifu|el2_ifu>io_ic_tag_perr",
-      "~el2_ifu|el2_ifu>io_ic_rd_hit",
-      "~el2_ifu|el2_ifu>io_exu_flush_final",
-      "~el2_ifu|el2_ifu>io_ifu_axi_rid",
-      "~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
-      "~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
-      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
-      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
-      "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
-      "~el2_ifu|el2_ifu>io_exu_flush_final",
-      "~el2_ifu|el2_ifu>io_ic_rd_hit",
-      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
-      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_iccm_rden",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_dma_iccm_req",
-      "~el2_ifu|el2_ifu>io_dma_mem_write",
-      "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
-      "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
-      "~el2_ifu|el2_ifu>io_exu_flush_final",
-      "~el2_ifu|el2_ifu>io_ic_rd_hit",
-      "~el2_ifu|el2_ifu>io_exu_flush_path_final",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
-      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
-      "~el2_ifu|el2_ifu>io_ic_rd_data",
-      "~el2_ifu|el2_ifu>io_dec_i0_decode_d"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ifu_pmu_instr_aligned",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_dec_i0_decode_d"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
-      "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
-      "~el2_ifu|el2_ifu>io_exu_flush_final",
-      "~el2_ifu|el2_ifu>io_ic_rd_hit",
-      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
-      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_iccm_rd_data",
-      "~el2_ifu|el2_ifu>io_exu_flush_final",
-      "~el2_ifu|el2_ifu>io_ic_rd_hit",
-      "~el2_ifu|el2_ifu>io_ifu_axi_rid",
-      "~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
-      "~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
-      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
-      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ic_rw_addr",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_exu_flush_path_final",
-      "~el2_ifu|el2_ifu>io_exu_flush_final",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
-      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
-      "~el2_ifu|el2_ifu>io_ic_rd_hit",
-      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_exu_flush_final",
-      "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
-      "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
-      "~el2_ifu|el2_ifu>io_ic_rd_hit",
-      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
-      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ic_tag_valid",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_exu_flush_final"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ic_rd_en",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_exu_flush_final",
-      "~el2_ifu|el2_ifu>io_dec_tlu_force_halt",
-      "~el2_ifu|el2_ifu>io_ic_rd_hit",
-      "~el2_ifu|el2_ifu>io_exu_flush_path_final",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff",
-      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
-      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
-      "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
-      "~el2_ifu|el2_ifu>io_ic_rd_data",
-      "~el2_ifu|el2_ifu>io_dec_i0_decode_d"
-    ]
-  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr",
@@ -283,8 +228,8 @@
       "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
       "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
       "~el2_ifu|el2_ifu>io_dec_i0_decode_d",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
@@ -294,15 +239,10 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_data",
-    "sources":[
-      "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_iccm_ready",
+    "sink":"~el2_ifu|el2_ifu>io_iccm_wren",
     "sources":[
+      "~el2_ifu|el2_ifu>io_dma_mem_write",
+      "~el2_ifu|el2_ifu>io_dma_iccm_req",
       "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
       "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
       "~el2_ifu|el2_ifu>io_exu_flush_final",
@@ -312,8 +252,8 @@
       "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
       "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
       "~el2_ifu|el2_ifu>io_dec_i0_decode_d",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
@@ -323,21 +263,81 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
+    "sink":"~el2_ifu|el2_ifu>io_ifu_pmu_instr_aligned",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_dec_i0_decode_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err",
     "sources":[
       "~el2_ifu|el2_ifu>io_exu_flush_final",
+      "~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
+      "~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
       "~el2_ifu|el2_ifu>io_ic_rd_hit",
-      "~el2_ifu|el2_ifu>io_ifu_axi_rid",
-      "~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
-      "~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
       "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
       "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
-      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
       "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_exu_flush_final",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
+      "~el2_ifu|el2_ifu>io_ic_rd_data",
+      "~el2_ifu|el2_ifu>io_dec_i0_decode_d",
+      "~el2_ifu|el2_ifu>io_ic_rd_hit",
+      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
+      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_ic_tag_valid",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_exu_flush_final"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_ic_rw_addr",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_exu_flush_path_final",
+      "~el2_ifu|el2_ifu>io_exu_flush_final",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
+      "~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
+      "~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
+      "~el2_ifu|el2_ifu>io_ic_rd_hit",
+      "~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_data",
+    "sources":[
+      "~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata"
+    ]
+  },
   {
     "class":"firrtl.EmitCircuitAnnotation",
     "emitter":"firrtl.VerilogEmitter"
diff --git a/el2_ifu.fir b/el2_ifu.fir
index b37a29ee..3217e507 100644
--- a/el2_ifu.fir
+++ b/el2_ifu.fir
@@ -28977,7 +28977,7 @@ circuit el2_ifu :
   module el2_ifu_bp_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt}
+    output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt}
     
     wire leak_one_f : UInt<1>
     leak_one_f <= UInt<1>("h00")
@@ -29004,10 +29004,10 @@ circuit el2_ifu :
     dec_tlu_way_wb <= UInt<1>("h00")
     node _T = eq(leak_one_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 72:51]
     node exu_mp_valid = and(io.exu_mp_pkt.bits.misp, _T) @[el2_ifu_bp_ctl.scala 72:49]
-    node _T_1 = or(io.dec_tlu_br0_r_pkt.br_start_error, io.dec_tlu_br0_r_pkt.br_error) @[el2_ifu_bp_ctl.scala 94:50]
+    node _T_1 = or(io.dec_tlu_br0_r_pkt.bits.br_start_error, io.dec_tlu_br0_r_pkt.bits.br_error) @[el2_ifu_bp_ctl.scala 94:50]
     dec_tlu_error_wb <= _T_1 @[el2_ifu_bp_ctl.scala 94:20]
     btb_error_addr_wb <= io.exu_i0_br_index_r @[el2_ifu_bp_ctl.scala 95:21]
-    dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.way @[el2_ifu_bp_ctl.scala 96:18]
+    dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu_bp_ctl.scala 96:18]
     node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 191:13]
     node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 191:51]
     node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 191:47]
@@ -29814,8 +29814,8 @@ circuit el2_ifu :
     node bht_wr_en0 = and(_T_556, _T_558) @[el2_ifu_bp_ctl.scala 408:84]
     node _T_559 = bits(io.dec_tlu_br0_r_pkt.valid, 0, 0) @[Bitwise.scala 72:15]
     node _T_560 = mux(_T_559, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_561 = not(io.dec_tlu_br0_r_pkt.middle) @[el2_ifu_bp_ctl.scala 409:75]
-    node _T_562 = cat(io.dec_tlu_br0_r_pkt.middle, _T_561) @[Cat.scala 29:58]
+    node _T_561 = not(io.dec_tlu_br0_r_pkt.bits.middle) @[el2_ifu_bp_ctl.scala 409:75]
+    node _T_562 = cat(io.dec_tlu_br0_r_pkt.bits.middle, _T_561) @[Cat.scala 29:58]
     node bht_wr_en2 = and(_T_560, _T_562) @[el2_ifu_bp_ctl.scala 409:46]
     node _T_563 = cat(io.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58]
     node _T_564 = bits(_T_563, 9, 2) @[el2_lib.scala 196:16]
@@ -40155,7 +40155,7 @@ circuit el2_ifu :
     node _T_6565 = and(_T_6562, _T_6564) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6566 = or(_T_6565, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6567 = bits(_T_6566, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6568 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6569 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6570 = eq(_T_6569, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40165,7 +40165,7 @@ circuit el2_ifu :
     node _T_6574 = and(_T_6571, _T_6573) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6575 = or(_T_6574, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6576 = bits(_T_6575, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6577 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6578 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6579 = eq(_T_6578, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40175,7 +40175,7 @@ circuit el2_ifu :
     node _T_6583 = and(_T_6580, _T_6582) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6584 = or(_T_6583, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6585 = bits(_T_6584, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6586 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6587 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6588 = eq(_T_6587, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40185,7 +40185,7 @@ circuit el2_ifu :
     node _T_6592 = and(_T_6589, _T_6591) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6593 = or(_T_6592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6594 = bits(_T_6593, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6595 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6596 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6597 = eq(_T_6596, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40195,7 +40195,7 @@ circuit el2_ifu :
     node _T_6601 = and(_T_6598, _T_6600) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6602 = or(_T_6601, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6603 = bits(_T_6602, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6604 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6605 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6606 = eq(_T_6605, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40205,7 +40205,7 @@ circuit el2_ifu :
     node _T_6610 = and(_T_6607, _T_6609) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6611 = or(_T_6610, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6612 = bits(_T_6611, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6613 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6614 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6615 = eq(_T_6614, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40215,7 +40215,7 @@ circuit el2_ifu :
     node _T_6619 = and(_T_6616, _T_6618) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6620 = or(_T_6619, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6621 = bits(_T_6620, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6622 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6623 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6624 = eq(_T_6623, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40225,7 +40225,7 @@ circuit el2_ifu :
     node _T_6628 = and(_T_6625, _T_6627) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6629 = or(_T_6628, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6630 = bits(_T_6629, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6631 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6632 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6633 = eq(_T_6632, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40235,7 +40235,7 @@ circuit el2_ifu :
     node _T_6637 = and(_T_6634, _T_6636) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6638 = or(_T_6637, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6639 = bits(_T_6638, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6640 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6641 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6642 = eq(_T_6641, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40245,7 +40245,7 @@ circuit el2_ifu :
     node _T_6646 = and(_T_6643, _T_6645) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6647 = or(_T_6646, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6648 = bits(_T_6647, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6649 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6650 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6651 = eq(_T_6650, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40255,7 +40255,7 @@ circuit el2_ifu :
     node _T_6655 = and(_T_6652, _T_6654) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6656 = or(_T_6655, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6657 = bits(_T_6656, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6658 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6659 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6660 = eq(_T_6659, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40265,7 +40265,7 @@ circuit el2_ifu :
     node _T_6664 = and(_T_6661, _T_6663) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6665 = or(_T_6664, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6666 = bits(_T_6665, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6667 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6668 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6669 = eq(_T_6668, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40275,7 +40275,7 @@ circuit el2_ifu :
     node _T_6673 = and(_T_6670, _T_6672) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6674 = or(_T_6673, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6675 = bits(_T_6674, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6676 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6677 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6678 = eq(_T_6677, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40285,7 +40285,7 @@ circuit el2_ifu :
     node _T_6682 = and(_T_6679, _T_6681) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6683 = or(_T_6682, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6684 = bits(_T_6683, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6685 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6686 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6687 = eq(_T_6686, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40295,7 +40295,7 @@ circuit el2_ifu :
     node _T_6691 = and(_T_6688, _T_6690) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6692 = or(_T_6691, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6693 = bits(_T_6692, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6694 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6695 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6696 = eq(_T_6695, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40305,7 +40305,7 @@ circuit el2_ifu :
     node _T_6700 = and(_T_6697, _T_6699) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6701 = or(_T_6700, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6702 = bits(_T_6701, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6703 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6704 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6705 = eq(_T_6704, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40315,7 +40315,7 @@ circuit el2_ifu :
     node _T_6709 = and(_T_6706, _T_6708) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6710 = or(_T_6709, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6711 = bits(_T_6710, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6712 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6713 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6714 = eq(_T_6713, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40325,7 +40325,7 @@ circuit el2_ifu :
     node _T_6718 = and(_T_6715, _T_6717) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6719 = or(_T_6718, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6720 = bits(_T_6719, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6721 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6722 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6723 = eq(_T_6722, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40335,7 +40335,7 @@ circuit el2_ifu :
     node _T_6727 = and(_T_6724, _T_6726) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6728 = or(_T_6727, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6729 = bits(_T_6728, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6730 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6731 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6732 = eq(_T_6731, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40345,7 +40345,7 @@ circuit el2_ifu :
     node _T_6736 = and(_T_6733, _T_6735) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6737 = or(_T_6736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6738 = bits(_T_6737, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6739 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6740 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6741 = eq(_T_6740, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40355,7 +40355,7 @@ circuit el2_ifu :
     node _T_6745 = and(_T_6742, _T_6744) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6746 = or(_T_6745, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6747 = bits(_T_6746, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6748 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6749 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6750 = eq(_T_6749, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40365,7 +40365,7 @@ circuit el2_ifu :
     node _T_6754 = and(_T_6751, _T_6753) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6755 = or(_T_6754, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6756 = bits(_T_6755, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6757 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6758 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6759 = eq(_T_6758, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40375,7 +40375,7 @@ circuit el2_ifu :
     node _T_6763 = and(_T_6760, _T_6762) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6764 = or(_T_6763, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6765 = bits(_T_6764, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6766 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6767 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6768 = eq(_T_6767, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40385,7 +40385,7 @@ circuit el2_ifu :
     node _T_6772 = and(_T_6769, _T_6771) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6773 = or(_T_6772, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6774 = bits(_T_6773, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6775 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6776 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6777 = eq(_T_6776, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40395,7 +40395,7 @@ circuit el2_ifu :
     node _T_6781 = and(_T_6778, _T_6780) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6782 = or(_T_6781, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6783 = bits(_T_6782, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6784 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6785 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6786 = eq(_T_6785, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40405,7 +40405,7 @@ circuit el2_ifu :
     node _T_6790 = and(_T_6787, _T_6789) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6791 = or(_T_6790, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6792 = bits(_T_6791, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6793 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6794 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6795 = eq(_T_6794, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40415,7 +40415,7 @@ circuit el2_ifu :
     node _T_6799 = and(_T_6796, _T_6798) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6800 = or(_T_6799, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6801 = bits(_T_6800, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6802 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6803 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6804 = eq(_T_6803, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40425,7 +40425,7 @@ circuit el2_ifu :
     node _T_6808 = and(_T_6805, _T_6807) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6809 = or(_T_6808, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6810 = bits(_T_6809, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6811 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6812 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6813 = eq(_T_6812, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40435,7 +40435,7 @@ circuit el2_ifu :
     node _T_6817 = and(_T_6814, _T_6816) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6818 = or(_T_6817, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6819 = bits(_T_6818, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6820 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6821 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6822 = eq(_T_6821, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40445,7 +40445,7 @@ circuit el2_ifu :
     node _T_6826 = and(_T_6823, _T_6825) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6827 = or(_T_6826, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6828 = bits(_T_6827, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6829 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6830 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6831 = eq(_T_6830, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40455,7 +40455,7 @@ circuit el2_ifu :
     node _T_6835 = and(_T_6832, _T_6834) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6836 = or(_T_6835, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6837 = bits(_T_6836, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6838 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6839 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6840 = eq(_T_6839, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40465,7 +40465,7 @@ circuit el2_ifu :
     node _T_6844 = and(_T_6841, _T_6843) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6845 = or(_T_6844, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6846 = bits(_T_6845, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6847 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6848 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6849 = eq(_T_6848, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40475,7 +40475,7 @@ circuit el2_ifu :
     node _T_6853 = and(_T_6850, _T_6852) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6854 = or(_T_6853, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6855 = bits(_T_6854, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6856 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6857 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6858 = eq(_T_6857, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40485,7 +40485,7 @@ circuit el2_ifu :
     node _T_6862 = and(_T_6859, _T_6861) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6863 = or(_T_6862, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6864 = bits(_T_6863, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6865 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6866 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6867 = eq(_T_6866, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40495,7 +40495,7 @@ circuit el2_ifu :
     node _T_6871 = and(_T_6868, _T_6870) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6872 = or(_T_6871, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6873 = bits(_T_6872, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6874 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6875 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6876 = eq(_T_6875, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40505,7 +40505,7 @@ circuit el2_ifu :
     node _T_6880 = and(_T_6877, _T_6879) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6881 = or(_T_6880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6882 = bits(_T_6881, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6883 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6884 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6885 = eq(_T_6884, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40515,7 +40515,7 @@ circuit el2_ifu :
     node _T_6889 = and(_T_6886, _T_6888) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6890 = or(_T_6889, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6891 = bits(_T_6890, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6892 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6893 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6894 = eq(_T_6893, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40525,7 +40525,7 @@ circuit el2_ifu :
     node _T_6898 = and(_T_6895, _T_6897) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6899 = or(_T_6898, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6900 = bits(_T_6899, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6901 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6902 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6903 = eq(_T_6902, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40535,7 +40535,7 @@ circuit el2_ifu :
     node _T_6907 = and(_T_6904, _T_6906) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6908 = or(_T_6907, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6909 = bits(_T_6908, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6910 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6911 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6912 = eq(_T_6911, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40545,7 +40545,7 @@ circuit el2_ifu :
     node _T_6916 = and(_T_6913, _T_6915) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6917 = or(_T_6916, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6918 = bits(_T_6917, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6919 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6920 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6921 = eq(_T_6920, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40555,7 +40555,7 @@ circuit el2_ifu :
     node _T_6925 = and(_T_6922, _T_6924) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6926 = or(_T_6925, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6927 = bits(_T_6926, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6928 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6929 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6930 = eq(_T_6929, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40565,7 +40565,7 @@ circuit el2_ifu :
     node _T_6934 = and(_T_6931, _T_6933) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6935 = or(_T_6934, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6936 = bits(_T_6935, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6937 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6938 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6939 = eq(_T_6938, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40575,7 +40575,7 @@ circuit el2_ifu :
     node _T_6943 = and(_T_6940, _T_6942) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6944 = or(_T_6943, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6945 = bits(_T_6944, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6946 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6947 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6948 = eq(_T_6947, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40585,7 +40585,7 @@ circuit el2_ifu :
     node _T_6952 = and(_T_6949, _T_6951) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6953 = or(_T_6952, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6954 = bits(_T_6953, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6955 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6956 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6957 = eq(_T_6956, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40595,7 +40595,7 @@ circuit el2_ifu :
     node _T_6961 = and(_T_6958, _T_6960) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6962 = or(_T_6961, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6963 = bits(_T_6962, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6964 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6965 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6966 = eq(_T_6965, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40605,7 +40605,7 @@ circuit el2_ifu :
     node _T_6970 = and(_T_6967, _T_6969) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6971 = or(_T_6970, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6972 = bits(_T_6971, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6973 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6974 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6975 = eq(_T_6974, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40615,7 +40615,7 @@ circuit el2_ifu :
     node _T_6979 = and(_T_6976, _T_6978) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6980 = or(_T_6979, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6981 = bits(_T_6980, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6982 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6983 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6984 = eq(_T_6983, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40625,7 +40625,7 @@ circuit el2_ifu :
     node _T_6988 = and(_T_6985, _T_6987) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6989 = or(_T_6988, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6990 = bits(_T_6989, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6991 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6992 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6993 = eq(_T_6992, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40635,7 +40635,7 @@ circuit el2_ifu :
     node _T_6997 = and(_T_6994, _T_6996) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6998 = or(_T_6997, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6999 = bits(_T_6998, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7000 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7001 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7002 = eq(_T_7001, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40645,7 +40645,7 @@ circuit el2_ifu :
     node _T_7006 = and(_T_7003, _T_7005) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7007 = or(_T_7006, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7008 = bits(_T_7007, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7009 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7010 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7011 = eq(_T_7010, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40655,7 +40655,7 @@ circuit el2_ifu :
     node _T_7015 = and(_T_7012, _T_7014) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7016 = or(_T_7015, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7017 = bits(_T_7016, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7018 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7019 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7020 = eq(_T_7019, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40665,7 +40665,7 @@ circuit el2_ifu :
     node _T_7024 = and(_T_7021, _T_7023) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7025 = or(_T_7024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7026 = bits(_T_7025, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7027 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7028 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7029 = eq(_T_7028, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40675,7 +40675,7 @@ circuit el2_ifu :
     node _T_7033 = and(_T_7030, _T_7032) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7034 = or(_T_7033, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7035 = bits(_T_7034, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7036 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7037 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7038 = eq(_T_7037, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40685,7 +40685,7 @@ circuit el2_ifu :
     node _T_7042 = and(_T_7039, _T_7041) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7043 = or(_T_7042, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7044 = bits(_T_7043, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7045 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7046 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7047 = eq(_T_7046, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40695,7 +40695,7 @@ circuit el2_ifu :
     node _T_7051 = and(_T_7048, _T_7050) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7052 = or(_T_7051, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7053 = bits(_T_7052, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7054 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7055 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7056 = eq(_T_7055, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40705,7 +40705,7 @@ circuit el2_ifu :
     node _T_7060 = and(_T_7057, _T_7059) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7061 = or(_T_7060, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7062 = bits(_T_7061, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7063 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7064 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7065 = eq(_T_7064, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40715,7 +40715,7 @@ circuit el2_ifu :
     node _T_7069 = and(_T_7066, _T_7068) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7070 = or(_T_7069, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7071 = bits(_T_7070, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7072 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7073 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7074 = eq(_T_7073, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40725,7 +40725,7 @@ circuit el2_ifu :
     node _T_7078 = and(_T_7075, _T_7077) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7079 = or(_T_7078, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7080 = bits(_T_7079, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7081 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7082 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7083 = eq(_T_7082, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40735,7 +40735,7 @@ circuit el2_ifu :
     node _T_7087 = and(_T_7084, _T_7086) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7088 = or(_T_7087, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7089 = bits(_T_7088, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7090 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7091 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7092 = eq(_T_7091, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40745,7 +40745,7 @@ circuit el2_ifu :
     node _T_7096 = and(_T_7093, _T_7095) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7097 = or(_T_7096, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7098 = bits(_T_7097, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7099 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7100 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7101 = eq(_T_7100, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40755,7 +40755,7 @@ circuit el2_ifu :
     node _T_7105 = and(_T_7102, _T_7104) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7106 = or(_T_7105, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7107 = bits(_T_7106, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7108 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7109 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7110 = eq(_T_7109, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40765,7 +40765,7 @@ circuit el2_ifu :
     node _T_7114 = and(_T_7111, _T_7113) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7115 = or(_T_7114, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7116 = bits(_T_7115, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7117 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7118 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7119 = eq(_T_7118, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40775,7 +40775,7 @@ circuit el2_ifu :
     node _T_7123 = and(_T_7120, _T_7122) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7124 = or(_T_7123, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7125 = bits(_T_7124, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7126 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7127 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7128 = eq(_T_7127, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40785,7 +40785,7 @@ circuit el2_ifu :
     node _T_7132 = and(_T_7129, _T_7131) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7133 = or(_T_7132, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7134 = bits(_T_7133, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7135 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7136 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7137 = eq(_T_7136, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40795,7 +40795,7 @@ circuit el2_ifu :
     node _T_7141 = and(_T_7138, _T_7140) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7142 = or(_T_7141, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7143 = bits(_T_7142, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7144 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7145 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7146 = eq(_T_7145, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40805,7 +40805,7 @@ circuit el2_ifu :
     node _T_7150 = and(_T_7147, _T_7149) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7151 = or(_T_7150, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7152 = bits(_T_7151, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7153 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7154 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7155 = eq(_T_7154, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40815,7 +40815,7 @@ circuit el2_ifu :
     node _T_7159 = and(_T_7156, _T_7158) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7160 = or(_T_7159, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7161 = bits(_T_7160, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7162 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7163 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7164 = eq(_T_7163, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40825,7 +40825,7 @@ circuit el2_ifu :
     node _T_7168 = and(_T_7165, _T_7167) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7169 = or(_T_7168, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7170 = bits(_T_7169, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7171 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7172 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7173 = eq(_T_7172, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40835,7 +40835,7 @@ circuit el2_ifu :
     node _T_7177 = and(_T_7174, _T_7176) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7178 = or(_T_7177, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7179 = bits(_T_7178, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7180 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7181 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7182 = eq(_T_7181, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40845,7 +40845,7 @@ circuit el2_ifu :
     node _T_7186 = and(_T_7183, _T_7185) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7187 = or(_T_7186, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7188 = bits(_T_7187, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7189 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7190 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7191 = eq(_T_7190, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40855,7 +40855,7 @@ circuit el2_ifu :
     node _T_7195 = and(_T_7192, _T_7194) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7196 = or(_T_7195, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7197 = bits(_T_7196, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7198 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7199 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7200 = eq(_T_7199, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40865,7 +40865,7 @@ circuit el2_ifu :
     node _T_7204 = and(_T_7201, _T_7203) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7205 = or(_T_7204, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7206 = bits(_T_7205, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7207 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7208 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7209 = eq(_T_7208, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40875,7 +40875,7 @@ circuit el2_ifu :
     node _T_7213 = and(_T_7210, _T_7212) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7214 = or(_T_7213, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7215 = bits(_T_7214, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7216 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7217 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7218 = eq(_T_7217, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40885,7 +40885,7 @@ circuit el2_ifu :
     node _T_7222 = and(_T_7219, _T_7221) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7223 = or(_T_7222, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7224 = bits(_T_7223, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7225 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7226 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7227 = eq(_T_7226, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40895,7 +40895,7 @@ circuit el2_ifu :
     node _T_7231 = and(_T_7228, _T_7230) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7232 = or(_T_7231, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7233 = bits(_T_7232, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7234 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7235 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7236 = eq(_T_7235, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40905,7 +40905,7 @@ circuit el2_ifu :
     node _T_7240 = and(_T_7237, _T_7239) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7241 = or(_T_7240, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7242 = bits(_T_7241, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7243 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7244 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7245 = eq(_T_7244, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40915,7 +40915,7 @@ circuit el2_ifu :
     node _T_7249 = and(_T_7246, _T_7248) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7250 = or(_T_7249, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7251 = bits(_T_7250, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7252 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7253 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7254 = eq(_T_7253, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40925,7 +40925,7 @@ circuit el2_ifu :
     node _T_7258 = and(_T_7255, _T_7257) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7259 = or(_T_7258, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7260 = bits(_T_7259, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7261 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7262 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7263 = eq(_T_7262, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40935,7 +40935,7 @@ circuit el2_ifu :
     node _T_7267 = and(_T_7264, _T_7266) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7268 = or(_T_7267, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7269 = bits(_T_7268, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7270 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7271 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7272 = eq(_T_7271, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40945,7 +40945,7 @@ circuit el2_ifu :
     node _T_7276 = and(_T_7273, _T_7275) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7277 = or(_T_7276, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7278 = bits(_T_7277, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7279 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7280 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7281 = eq(_T_7280, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40955,7 +40955,7 @@ circuit el2_ifu :
     node _T_7285 = and(_T_7282, _T_7284) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7286 = or(_T_7285, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7287 = bits(_T_7286, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7288 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7289 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7290 = eq(_T_7289, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40965,7 +40965,7 @@ circuit el2_ifu :
     node _T_7294 = and(_T_7291, _T_7293) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7295 = or(_T_7294, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7296 = bits(_T_7295, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7297 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7298 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7299 = eq(_T_7298, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40975,7 +40975,7 @@ circuit el2_ifu :
     node _T_7303 = and(_T_7300, _T_7302) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7304 = or(_T_7303, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7305 = bits(_T_7304, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7306 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7307 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7308 = eq(_T_7307, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40985,7 +40985,7 @@ circuit el2_ifu :
     node _T_7312 = and(_T_7309, _T_7311) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7313 = or(_T_7312, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7314 = bits(_T_7313, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7315 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7316 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7317 = eq(_T_7316, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40995,7 +40995,7 @@ circuit el2_ifu :
     node _T_7321 = and(_T_7318, _T_7320) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7322 = or(_T_7321, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7323 = bits(_T_7322, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7324 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7325 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7326 = eq(_T_7325, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41005,7 +41005,7 @@ circuit el2_ifu :
     node _T_7330 = and(_T_7327, _T_7329) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7331 = or(_T_7330, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7332 = bits(_T_7331, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7333 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7334 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7335 = eq(_T_7334, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41015,7 +41015,7 @@ circuit el2_ifu :
     node _T_7339 = and(_T_7336, _T_7338) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7340 = or(_T_7339, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7341 = bits(_T_7340, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7342 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7343 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7344 = eq(_T_7343, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41025,7 +41025,7 @@ circuit el2_ifu :
     node _T_7348 = and(_T_7345, _T_7347) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7349 = or(_T_7348, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7350 = bits(_T_7349, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7351 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7352 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7353 = eq(_T_7352, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41035,7 +41035,7 @@ circuit el2_ifu :
     node _T_7357 = and(_T_7354, _T_7356) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7358 = or(_T_7357, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7359 = bits(_T_7358, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7360 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7361 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7362 = eq(_T_7361, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41045,7 +41045,7 @@ circuit el2_ifu :
     node _T_7366 = and(_T_7363, _T_7365) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7367 = or(_T_7366, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7368 = bits(_T_7367, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7369 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7370 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7371 = eq(_T_7370, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41055,7 +41055,7 @@ circuit el2_ifu :
     node _T_7375 = and(_T_7372, _T_7374) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7376 = or(_T_7375, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7377 = bits(_T_7376, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7378 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7379 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7380 = eq(_T_7379, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41065,7 +41065,7 @@ circuit el2_ifu :
     node _T_7384 = and(_T_7381, _T_7383) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7385 = or(_T_7384, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7386 = bits(_T_7385, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7387 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7388 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7389 = eq(_T_7388, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41075,7 +41075,7 @@ circuit el2_ifu :
     node _T_7393 = and(_T_7390, _T_7392) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7394 = or(_T_7393, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7395 = bits(_T_7394, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7396 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7397 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7398 = eq(_T_7397, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41085,7 +41085,7 @@ circuit el2_ifu :
     node _T_7402 = and(_T_7399, _T_7401) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7403 = or(_T_7402, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7404 = bits(_T_7403, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7405 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7406 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7407 = eq(_T_7406, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41095,7 +41095,7 @@ circuit el2_ifu :
     node _T_7411 = and(_T_7408, _T_7410) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7412 = or(_T_7411, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7413 = bits(_T_7412, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7414 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7415 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7416 = eq(_T_7415, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41105,7 +41105,7 @@ circuit el2_ifu :
     node _T_7420 = and(_T_7417, _T_7419) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7421 = or(_T_7420, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7422 = bits(_T_7421, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7423 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7424 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7425 = eq(_T_7424, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41115,7 +41115,7 @@ circuit el2_ifu :
     node _T_7429 = and(_T_7426, _T_7428) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7430 = or(_T_7429, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7431 = bits(_T_7430, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7432 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7433 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7434 = eq(_T_7433, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41125,7 +41125,7 @@ circuit el2_ifu :
     node _T_7438 = and(_T_7435, _T_7437) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7439 = or(_T_7438, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7440 = bits(_T_7439, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7441 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7442 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7443 = eq(_T_7442, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41135,7 +41135,7 @@ circuit el2_ifu :
     node _T_7447 = and(_T_7444, _T_7446) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7448 = or(_T_7447, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7449 = bits(_T_7448, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7450 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7451 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7452 = eq(_T_7451, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41145,7 +41145,7 @@ circuit el2_ifu :
     node _T_7456 = and(_T_7453, _T_7455) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7457 = or(_T_7456, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7458 = bits(_T_7457, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7459 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7460 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7461 = eq(_T_7460, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41155,7 +41155,7 @@ circuit el2_ifu :
     node _T_7465 = and(_T_7462, _T_7464) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7466 = or(_T_7465, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7467 = bits(_T_7466, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7468 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7469 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7470 = eq(_T_7469, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41165,7 +41165,7 @@ circuit el2_ifu :
     node _T_7474 = and(_T_7471, _T_7473) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7475 = or(_T_7474, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7476 = bits(_T_7475, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7477 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7478 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7479 = eq(_T_7478, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41175,7 +41175,7 @@ circuit el2_ifu :
     node _T_7483 = and(_T_7480, _T_7482) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7484 = or(_T_7483, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7485 = bits(_T_7484, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7486 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7487 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7488 = eq(_T_7487, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41185,7 +41185,7 @@ circuit el2_ifu :
     node _T_7492 = and(_T_7489, _T_7491) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7493 = or(_T_7492, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7494 = bits(_T_7493, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7495 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7496 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7497 = eq(_T_7496, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41195,7 +41195,7 @@ circuit el2_ifu :
     node _T_7501 = and(_T_7498, _T_7500) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7502 = or(_T_7501, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7503 = bits(_T_7502, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7504 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7505 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7506 = eq(_T_7505, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41205,7 +41205,7 @@ circuit el2_ifu :
     node _T_7510 = and(_T_7507, _T_7509) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7511 = or(_T_7510, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7512 = bits(_T_7511, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7513 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7514 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7515 = eq(_T_7514, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41215,7 +41215,7 @@ circuit el2_ifu :
     node _T_7519 = and(_T_7516, _T_7518) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7520 = or(_T_7519, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7521 = bits(_T_7520, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7522 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7523 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7524 = eq(_T_7523, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41225,7 +41225,7 @@ circuit el2_ifu :
     node _T_7528 = and(_T_7525, _T_7527) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7529 = or(_T_7528, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7530 = bits(_T_7529, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7531 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7532 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7533 = eq(_T_7532, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41235,7 +41235,7 @@ circuit el2_ifu :
     node _T_7537 = and(_T_7534, _T_7536) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7538 = or(_T_7537, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7539 = bits(_T_7538, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7540 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7541 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7542 = eq(_T_7541, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41245,7 +41245,7 @@ circuit el2_ifu :
     node _T_7546 = and(_T_7543, _T_7545) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7547 = or(_T_7546, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7548 = bits(_T_7547, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7549 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7550 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7551 = eq(_T_7550, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41255,7 +41255,7 @@ circuit el2_ifu :
     node _T_7555 = and(_T_7552, _T_7554) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7556 = or(_T_7555, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7557 = bits(_T_7556, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7558 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7559 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7560 = eq(_T_7559, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41265,7 +41265,7 @@ circuit el2_ifu :
     node _T_7564 = and(_T_7561, _T_7563) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7565 = or(_T_7564, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7566 = bits(_T_7565, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7567 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7568 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7569 = eq(_T_7568, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41275,7 +41275,7 @@ circuit el2_ifu :
     node _T_7573 = and(_T_7570, _T_7572) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7574 = or(_T_7573, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7575 = bits(_T_7574, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7576 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7577 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7578 = eq(_T_7577, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41285,7 +41285,7 @@ circuit el2_ifu :
     node _T_7582 = and(_T_7579, _T_7581) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7583 = or(_T_7582, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7584 = bits(_T_7583, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7585 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7586 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7587 = eq(_T_7586, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41295,7 +41295,7 @@ circuit el2_ifu :
     node _T_7591 = and(_T_7588, _T_7590) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7592 = or(_T_7591, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7593 = bits(_T_7592, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7594 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7595 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7596 = eq(_T_7595, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41305,7 +41305,7 @@ circuit el2_ifu :
     node _T_7600 = and(_T_7597, _T_7599) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7601 = or(_T_7600, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7602 = bits(_T_7601, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7603 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7604 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7605 = eq(_T_7604, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41315,7 +41315,7 @@ circuit el2_ifu :
     node _T_7609 = and(_T_7606, _T_7608) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7610 = or(_T_7609, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7611 = bits(_T_7610, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7612 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7613 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7614 = eq(_T_7613, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41325,7 +41325,7 @@ circuit el2_ifu :
     node _T_7618 = and(_T_7615, _T_7617) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7619 = or(_T_7618, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7620 = bits(_T_7619, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7621 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7622 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7623 = eq(_T_7622, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41335,7 +41335,7 @@ circuit el2_ifu :
     node _T_7627 = and(_T_7624, _T_7626) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7628 = or(_T_7627, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7629 = bits(_T_7628, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7630 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7631 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7632 = eq(_T_7631, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41345,7 +41345,7 @@ circuit el2_ifu :
     node _T_7636 = and(_T_7633, _T_7635) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7637 = or(_T_7636, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7638 = bits(_T_7637, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7639 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7640 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7641 = eq(_T_7640, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41355,7 +41355,7 @@ circuit el2_ifu :
     node _T_7645 = and(_T_7642, _T_7644) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7646 = or(_T_7645, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7647 = bits(_T_7646, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7648 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7649 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7650 = eq(_T_7649, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41365,7 +41365,7 @@ circuit el2_ifu :
     node _T_7654 = and(_T_7651, _T_7653) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7655 = or(_T_7654, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7656 = bits(_T_7655, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7657 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7658 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7659 = eq(_T_7658, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41375,7 +41375,7 @@ circuit el2_ifu :
     node _T_7663 = and(_T_7660, _T_7662) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7664 = or(_T_7663, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7665 = bits(_T_7664, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7666 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7667 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7668 = eq(_T_7667, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41385,7 +41385,7 @@ circuit el2_ifu :
     node _T_7672 = and(_T_7669, _T_7671) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7673 = or(_T_7672, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7674 = bits(_T_7673, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7675 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7676 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7677 = eq(_T_7676, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41395,7 +41395,7 @@ circuit el2_ifu :
     node _T_7681 = and(_T_7678, _T_7680) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7682 = or(_T_7681, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7683 = bits(_T_7682, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7684 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7685 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7686 = eq(_T_7685, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41405,7 +41405,7 @@ circuit el2_ifu :
     node _T_7690 = and(_T_7687, _T_7689) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7691 = or(_T_7690, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7692 = bits(_T_7691, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7693 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7694 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7695 = eq(_T_7694, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41415,7 +41415,7 @@ circuit el2_ifu :
     node _T_7699 = and(_T_7696, _T_7698) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7700 = or(_T_7699, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7701 = bits(_T_7700, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7702 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7703 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7704 = eq(_T_7703, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41425,7 +41425,7 @@ circuit el2_ifu :
     node _T_7708 = and(_T_7705, _T_7707) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7709 = or(_T_7708, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7710 = bits(_T_7709, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7711 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7712 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7713 = eq(_T_7712, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41435,7 +41435,7 @@ circuit el2_ifu :
     node _T_7717 = and(_T_7714, _T_7716) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7718 = or(_T_7717, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7719 = bits(_T_7718, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7720 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7721 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7722 = eq(_T_7721, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41445,7 +41445,7 @@ circuit el2_ifu :
     node _T_7726 = and(_T_7723, _T_7725) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7727 = or(_T_7726, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7728 = bits(_T_7727, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7729 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7730 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7731 = eq(_T_7730, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41455,7 +41455,7 @@ circuit el2_ifu :
     node _T_7735 = and(_T_7732, _T_7734) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7736 = or(_T_7735, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7737 = bits(_T_7736, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7738 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7739 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7740 = eq(_T_7739, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41465,7 +41465,7 @@ circuit el2_ifu :
     node _T_7744 = and(_T_7741, _T_7743) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7745 = or(_T_7744, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7746 = bits(_T_7745, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7747 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7748 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7749 = eq(_T_7748, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41475,7 +41475,7 @@ circuit el2_ifu :
     node _T_7753 = and(_T_7750, _T_7752) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7754 = or(_T_7753, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7755 = bits(_T_7754, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7756 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7757 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7758 = eq(_T_7757, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41485,7 +41485,7 @@ circuit el2_ifu :
     node _T_7762 = and(_T_7759, _T_7761) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7763 = or(_T_7762, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7764 = bits(_T_7763, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7765 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7766 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7767 = eq(_T_7766, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41495,7 +41495,7 @@ circuit el2_ifu :
     node _T_7771 = and(_T_7768, _T_7770) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7772 = or(_T_7771, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7773 = bits(_T_7772, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7774 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7775 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7776 = eq(_T_7775, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41505,7 +41505,7 @@ circuit el2_ifu :
     node _T_7780 = and(_T_7777, _T_7779) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7781 = or(_T_7780, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7782 = bits(_T_7781, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7783 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7784 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7785 = eq(_T_7784, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41515,7 +41515,7 @@ circuit el2_ifu :
     node _T_7789 = and(_T_7786, _T_7788) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7790 = or(_T_7789, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7791 = bits(_T_7790, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7792 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7793 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7794 = eq(_T_7793, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41525,7 +41525,7 @@ circuit el2_ifu :
     node _T_7798 = and(_T_7795, _T_7797) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7799 = or(_T_7798, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7800 = bits(_T_7799, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7801 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7802 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7803 = eq(_T_7802, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41535,7 +41535,7 @@ circuit el2_ifu :
     node _T_7807 = and(_T_7804, _T_7806) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7808 = or(_T_7807, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7809 = bits(_T_7808, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7810 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7811 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7812 = eq(_T_7811, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41545,7 +41545,7 @@ circuit el2_ifu :
     node _T_7816 = and(_T_7813, _T_7815) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7817 = or(_T_7816, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7818 = bits(_T_7817, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7819 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7820 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7821 = eq(_T_7820, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41555,7 +41555,7 @@ circuit el2_ifu :
     node _T_7825 = and(_T_7822, _T_7824) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7826 = or(_T_7825, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7827 = bits(_T_7826, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7828 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7829 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7830 = eq(_T_7829, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41565,7 +41565,7 @@ circuit el2_ifu :
     node _T_7834 = and(_T_7831, _T_7833) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7835 = or(_T_7834, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7836 = bits(_T_7835, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7837 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7838 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7839 = eq(_T_7838, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41575,7 +41575,7 @@ circuit el2_ifu :
     node _T_7843 = and(_T_7840, _T_7842) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7844 = or(_T_7843, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7845 = bits(_T_7844, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7846 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7847 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7848 = eq(_T_7847, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41585,7 +41585,7 @@ circuit el2_ifu :
     node _T_7852 = and(_T_7849, _T_7851) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7853 = or(_T_7852, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7854 = bits(_T_7853, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7855 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7856 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7857 = eq(_T_7856, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41595,7 +41595,7 @@ circuit el2_ifu :
     node _T_7861 = and(_T_7858, _T_7860) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7862 = or(_T_7861, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7863 = bits(_T_7862, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7864 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7865 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7866 = eq(_T_7865, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41605,7 +41605,7 @@ circuit el2_ifu :
     node _T_7870 = and(_T_7867, _T_7869) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7871 = or(_T_7870, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7872 = bits(_T_7871, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7873 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7874 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7875 = eq(_T_7874, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41615,7 +41615,7 @@ circuit el2_ifu :
     node _T_7879 = and(_T_7876, _T_7878) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7880 = or(_T_7879, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7881 = bits(_T_7880, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7882 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7883 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7884 = eq(_T_7883, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41625,7 +41625,7 @@ circuit el2_ifu :
     node _T_7888 = and(_T_7885, _T_7887) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7889 = or(_T_7888, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7890 = bits(_T_7889, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7891 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7892 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7893 = eq(_T_7892, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41635,7 +41635,7 @@ circuit el2_ifu :
     node _T_7897 = and(_T_7894, _T_7896) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7898 = or(_T_7897, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7899 = bits(_T_7898, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7900 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7901 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7902 = eq(_T_7901, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41645,7 +41645,7 @@ circuit el2_ifu :
     node _T_7906 = and(_T_7903, _T_7905) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7907 = or(_T_7906, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7908 = bits(_T_7907, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7909 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7910 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7911 = eq(_T_7910, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41655,7 +41655,7 @@ circuit el2_ifu :
     node _T_7915 = and(_T_7912, _T_7914) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7916 = or(_T_7915, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7917 = bits(_T_7916, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7918 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7919 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7920 = eq(_T_7919, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41665,7 +41665,7 @@ circuit el2_ifu :
     node _T_7924 = and(_T_7921, _T_7923) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7925 = or(_T_7924, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7926 = bits(_T_7925, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7927 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7928 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7929 = eq(_T_7928, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41675,7 +41675,7 @@ circuit el2_ifu :
     node _T_7933 = and(_T_7930, _T_7932) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7934 = or(_T_7933, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7935 = bits(_T_7934, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7936 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7937 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7938 = eq(_T_7937, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41685,7 +41685,7 @@ circuit el2_ifu :
     node _T_7942 = and(_T_7939, _T_7941) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7943 = or(_T_7942, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7944 = bits(_T_7943, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7945 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7946 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7947 = eq(_T_7946, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41695,7 +41695,7 @@ circuit el2_ifu :
     node _T_7951 = and(_T_7948, _T_7950) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7952 = or(_T_7951, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7953 = bits(_T_7952, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7954 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7955 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7956 = eq(_T_7955, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41705,7 +41705,7 @@ circuit el2_ifu :
     node _T_7960 = and(_T_7957, _T_7959) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7961 = or(_T_7960, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7962 = bits(_T_7961, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7963 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7964 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7965 = eq(_T_7964, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41715,7 +41715,7 @@ circuit el2_ifu :
     node _T_7969 = and(_T_7966, _T_7968) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7970 = or(_T_7969, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7971 = bits(_T_7970, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7972 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7973 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7974 = eq(_T_7973, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41725,7 +41725,7 @@ circuit el2_ifu :
     node _T_7978 = and(_T_7975, _T_7977) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7979 = or(_T_7978, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7980 = bits(_T_7979, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7981 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7982 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7983 = eq(_T_7982, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41735,7 +41735,7 @@ circuit el2_ifu :
     node _T_7987 = and(_T_7984, _T_7986) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7988 = or(_T_7987, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7989 = bits(_T_7988, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7990 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7991 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7992 = eq(_T_7991, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41745,7 +41745,7 @@ circuit el2_ifu :
     node _T_7996 = and(_T_7993, _T_7995) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7997 = or(_T_7996, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7998 = bits(_T_7997, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7999 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8000 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8001 = eq(_T_8000, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41755,7 +41755,7 @@ circuit el2_ifu :
     node _T_8005 = and(_T_8002, _T_8004) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8006 = or(_T_8005, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8007 = bits(_T_8006, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8008 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8009 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8010 = eq(_T_8009, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41765,7 +41765,7 @@ circuit el2_ifu :
     node _T_8014 = and(_T_8011, _T_8013) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8015 = or(_T_8014, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8016 = bits(_T_8015, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8017 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8018 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8019 = eq(_T_8018, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41775,7 +41775,7 @@ circuit el2_ifu :
     node _T_8023 = and(_T_8020, _T_8022) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8024 = or(_T_8023, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8025 = bits(_T_8024, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8026 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8027 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8028 = eq(_T_8027, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41785,7 +41785,7 @@ circuit el2_ifu :
     node _T_8032 = and(_T_8029, _T_8031) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8033 = or(_T_8032, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8034 = bits(_T_8033, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8035 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8036 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8037 = eq(_T_8036, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41795,7 +41795,7 @@ circuit el2_ifu :
     node _T_8041 = and(_T_8038, _T_8040) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8042 = or(_T_8041, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8043 = bits(_T_8042, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8044 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8045 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8046 = eq(_T_8045, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41805,7 +41805,7 @@ circuit el2_ifu :
     node _T_8050 = and(_T_8047, _T_8049) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8051 = or(_T_8050, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8052 = bits(_T_8051, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8053 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8054 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8055 = eq(_T_8054, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41815,7 +41815,7 @@ circuit el2_ifu :
     node _T_8059 = and(_T_8056, _T_8058) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8060 = or(_T_8059, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8061 = bits(_T_8060, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8062 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8063 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8064 = eq(_T_8063, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41825,7 +41825,7 @@ circuit el2_ifu :
     node _T_8068 = and(_T_8065, _T_8067) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8069 = or(_T_8068, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8070 = bits(_T_8069, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8071 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8072 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8073 = eq(_T_8072, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41835,7 +41835,7 @@ circuit el2_ifu :
     node _T_8077 = and(_T_8074, _T_8076) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8078 = or(_T_8077, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8079 = bits(_T_8078, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8080 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8081 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8082 = eq(_T_8081, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41845,7 +41845,7 @@ circuit el2_ifu :
     node _T_8086 = and(_T_8083, _T_8085) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8087 = or(_T_8086, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8088 = bits(_T_8087, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8089 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8090 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8091 = eq(_T_8090, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41855,7 +41855,7 @@ circuit el2_ifu :
     node _T_8095 = and(_T_8092, _T_8094) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8096 = or(_T_8095, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8097 = bits(_T_8096, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8098 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8099 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8100 = eq(_T_8099, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41865,7 +41865,7 @@ circuit el2_ifu :
     node _T_8104 = and(_T_8101, _T_8103) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8105 = or(_T_8104, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8106 = bits(_T_8105, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8107 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8108 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8109 = eq(_T_8108, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41875,7 +41875,7 @@ circuit el2_ifu :
     node _T_8113 = and(_T_8110, _T_8112) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8114 = or(_T_8113, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8115 = bits(_T_8114, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8116 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8117 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8118 = eq(_T_8117, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41885,7 +41885,7 @@ circuit el2_ifu :
     node _T_8122 = and(_T_8119, _T_8121) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8123 = or(_T_8122, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8124 = bits(_T_8123, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8125 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8126 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8127 = eq(_T_8126, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41895,7 +41895,7 @@ circuit el2_ifu :
     node _T_8131 = and(_T_8128, _T_8130) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8132 = or(_T_8131, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8133 = bits(_T_8132, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8134 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8135 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8136 = eq(_T_8135, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41905,7 +41905,7 @@ circuit el2_ifu :
     node _T_8140 = and(_T_8137, _T_8139) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8141 = or(_T_8140, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8142 = bits(_T_8141, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8143 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8144 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8145 = eq(_T_8144, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41915,7 +41915,7 @@ circuit el2_ifu :
     node _T_8149 = and(_T_8146, _T_8148) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8150 = or(_T_8149, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8151 = bits(_T_8150, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8152 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8153 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8154 = eq(_T_8153, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41925,7 +41925,7 @@ circuit el2_ifu :
     node _T_8158 = and(_T_8155, _T_8157) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8159 = or(_T_8158, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8160 = bits(_T_8159, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8161 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8162 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8163 = eq(_T_8162, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41935,7 +41935,7 @@ circuit el2_ifu :
     node _T_8167 = and(_T_8164, _T_8166) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8168 = or(_T_8167, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8169 = bits(_T_8168, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8170 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8171 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8172 = eq(_T_8171, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41945,7 +41945,7 @@ circuit el2_ifu :
     node _T_8176 = and(_T_8173, _T_8175) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8177 = or(_T_8176, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8178 = bits(_T_8177, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8179 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8180 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8181 = eq(_T_8180, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41955,7 +41955,7 @@ circuit el2_ifu :
     node _T_8185 = and(_T_8182, _T_8184) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8186 = or(_T_8185, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8187 = bits(_T_8186, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8188 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8189 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8190 = eq(_T_8189, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41965,7 +41965,7 @@ circuit el2_ifu :
     node _T_8194 = and(_T_8191, _T_8193) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8195 = or(_T_8194, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8196 = bits(_T_8195, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8197 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8198 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8199 = eq(_T_8198, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41975,7 +41975,7 @@ circuit el2_ifu :
     node _T_8203 = and(_T_8200, _T_8202) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8204 = or(_T_8203, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8205 = bits(_T_8204, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8206 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8207 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8208 = eq(_T_8207, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41985,7 +41985,7 @@ circuit el2_ifu :
     node _T_8212 = and(_T_8209, _T_8211) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8213 = or(_T_8212, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8214 = bits(_T_8213, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8215 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8216 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8217 = eq(_T_8216, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41995,7 +41995,7 @@ circuit el2_ifu :
     node _T_8221 = and(_T_8218, _T_8220) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8222 = or(_T_8221, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8223 = bits(_T_8222, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8224 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8225 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8226 = eq(_T_8225, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42005,7 +42005,7 @@ circuit el2_ifu :
     node _T_8230 = and(_T_8227, _T_8229) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8231 = or(_T_8230, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8232 = bits(_T_8231, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8233 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8234 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8235 = eq(_T_8234, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42015,7 +42015,7 @@ circuit el2_ifu :
     node _T_8239 = and(_T_8236, _T_8238) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8240 = or(_T_8239, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8241 = bits(_T_8240, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8242 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8243 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8244 = eq(_T_8243, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42025,7 +42025,7 @@ circuit el2_ifu :
     node _T_8248 = and(_T_8245, _T_8247) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8249 = or(_T_8248, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8250 = bits(_T_8249, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8251 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8252 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8253 = eq(_T_8252, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42035,7 +42035,7 @@ circuit el2_ifu :
     node _T_8257 = and(_T_8254, _T_8256) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8258 = or(_T_8257, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8259 = bits(_T_8258, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8260 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8261 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8262 = eq(_T_8261, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42045,7 +42045,7 @@ circuit el2_ifu :
     node _T_8266 = and(_T_8263, _T_8265) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8267 = or(_T_8266, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8268 = bits(_T_8267, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8269 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8270 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8271 = eq(_T_8270, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42055,7 +42055,7 @@ circuit el2_ifu :
     node _T_8275 = and(_T_8272, _T_8274) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8276 = or(_T_8275, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8277 = bits(_T_8276, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8278 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8279 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8280 = eq(_T_8279, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42065,7 +42065,7 @@ circuit el2_ifu :
     node _T_8284 = and(_T_8281, _T_8283) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8285 = or(_T_8284, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8286 = bits(_T_8285, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8287 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8288 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8289 = eq(_T_8288, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42075,7 +42075,7 @@ circuit el2_ifu :
     node _T_8293 = and(_T_8290, _T_8292) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8294 = or(_T_8293, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8295 = bits(_T_8294, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8296 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8297 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8298 = eq(_T_8297, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42085,7 +42085,7 @@ circuit el2_ifu :
     node _T_8302 = and(_T_8299, _T_8301) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8303 = or(_T_8302, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8304 = bits(_T_8303, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8305 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8306 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8307 = eq(_T_8306, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42095,7 +42095,7 @@ circuit el2_ifu :
     node _T_8311 = and(_T_8308, _T_8310) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8312 = or(_T_8311, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8313 = bits(_T_8312, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8314 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8315 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8316 = eq(_T_8315, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42105,7 +42105,7 @@ circuit el2_ifu :
     node _T_8320 = and(_T_8317, _T_8319) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8321 = or(_T_8320, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8322 = bits(_T_8321, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8323 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8324 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8325 = eq(_T_8324, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42115,7 +42115,7 @@ circuit el2_ifu :
     node _T_8329 = and(_T_8326, _T_8328) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8330 = or(_T_8329, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8331 = bits(_T_8330, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8332 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8333 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8334 = eq(_T_8333, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42125,7 +42125,7 @@ circuit el2_ifu :
     node _T_8338 = and(_T_8335, _T_8337) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8339 = or(_T_8338, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8340 = bits(_T_8339, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8341 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8342 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8343 = eq(_T_8342, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42135,7 +42135,7 @@ circuit el2_ifu :
     node _T_8347 = and(_T_8344, _T_8346) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8348 = or(_T_8347, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8349 = bits(_T_8348, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8350 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8351 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8352 = eq(_T_8351, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42145,7 +42145,7 @@ circuit el2_ifu :
     node _T_8356 = and(_T_8353, _T_8355) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8357 = or(_T_8356, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8358 = bits(_T_8357, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8359 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8360 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8361 = eq(_T_8360, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42155,7 +42155,7 @@ circuit el2_ifu :
     node _T_8365 = and(_T_8362, _T_8364) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8366 = or(_T_8365, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8367 = bits(_T_8366, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8368 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8369 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8370 = eq(_T_8369, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42165,7 +42165,7 @@ circuit el2_ifu :
     node _T_8374 = and(_T_8371, _T_8373) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8375 = or(_T_8374, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8376 = bits(_T_8375, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8377 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8378 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8379 = eq(_T_8378, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42175,7 +42175,7 @@ circuit el2_ifu :
     node _T_8383 = and(_T_8380, _T_8382) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8384 = or(_T_8383, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8385 = bits(_T_8384, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8386 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8387 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8388 = eq(_T_8387, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42185,7 +42185,7 @@ circuit el2_ifu :
     node _T_8392 = and(_T_8389, _T_8391) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8393 = or(_T_8392, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8394 = bits(_T_8393, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8395 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8396 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8397 = eq(_T_8396, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42195,7 +42195,7 @@ circuit el2_ifu :
     node _T_8401 = and(_T_8398, _T_8400) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8402 = or(_T_8401, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8403 = bits(_T_8402, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8404 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8405 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8406 = eq(_T_8405, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42205,7 +42205,7 @@ circuit el2_ifu :
     node _T_8410 = and(_T_8407, _T_8409) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8411 = or(_T_8410, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8412 = bits(_T_8411, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8413 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8414 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8415 = eq(_T_8414, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42215,7 +42215,7 @@ circuit el2_ifu :
     node _T_8419 = and(_T_8416, _T_8418) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8420 = or(_T_8419, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8421 = bits(_T_8420, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8422 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8423 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8424 = eq(_T_8423, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42225,7 +42225,7 @@ circuit el2_ifu :
     node _T_8428 = and(_T_8425, _T_8427) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8429 = or(_T_8428, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8430 = bits(_T_8429, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8431 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8432 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8433 = eq(_T_8432, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42235,7 +42235,7 @@ circuit el2_ifu :
     node _T_8437 = and(_T_8434, _T_8436) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8438 = or(_T_8437, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8439 = bits(_T_8438, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8440 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8441 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8442 = eq(_T_8441, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42245,7 +42245,7 @@ circuit el2_ifu :
     node _T_8446 = and(_T_8443, _T_8445) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8447 = or(_T_8446, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8448 = bits(_T_8447, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8449 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8450 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8451 = eq(_T_8450, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42255,7 +42255,7 @@ circuit el2_ifu :
     node _T_8455 = and(_T_8452, _T_8454) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8456 = or(_T_8455, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8457 = bits(_T_8456, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8458 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8459 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8460 = eq(_T_8459, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42265,7 +42265,7 @@ circuit el2_ifu :
     node _T_8464 = and(_T_8461, _T_8463) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8465 = or(_T_8464, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8466 = bits(_T_8465, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8467 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8468 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8469 = eq(_T_8468, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42275,7 +42275,7 @@ circuit el2_ifu :
     node _T_8473 = and(_T_8470, _T_8472) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8474 = or(_T_8473, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8475 = bits(_T_8474, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8476 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8477 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8478 = eq(_T_8477, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42285,7 +42285,7 @@ circuit el2_ifu :
     node _T_8482 = and(_T_8479, _T_8481) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8483 = or(_T_8482, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8484 = bits(_T_8483, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8485 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8486 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8487 = eq(_T_8486, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42295,7 +42295,7 @@ circuit el2_ifu :
     node _T_8491 = and(_T_8488, _T_8490) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8492 = or(_T_8491, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8493 = bits(_T_8492, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8494 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8495 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8496 = eq(_T_8495, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42305,7 +42305,7 @@ circuit el2_ifu :
     node _T_8500 = and(_T_8497, _T_8499) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8501 = or(_T_8500, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8502 = bits(_T_8501, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8503 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8504 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8505 = eq(_T_8504, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42315,7 +42315,7 @@ circuit el2_ifu :
     node _T_8509 = and(_T_8506, _T_8508) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8510 = or(_T_8509, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8511 = bits(_T_8510, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8512 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8513 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8514 = eq(_T_8513, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42325,7 +42325,7 @@ circuit el2_ifu :
     node _T_8518 = and(_T_8515, _T_8517) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8519 = or(_T_8518, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8520 = bits(_T_8519, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8521 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8522 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8523 = eq(_T_8522, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42335,7 +42335,7 @@ circuit el2_ifu :
     node _T_8527 = and(_T_8524, _T_8526) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8528 = or(_T_8527, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8529 = bits(_T_8528, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8530 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8531 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8532 = eq(_T_8531, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42345,7 +42345,7 @@ circuit el2_ifu :
     node _T_8536 = and(_T_8533, _T_8535) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8537 = or(_T_8536, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8538 = bits(_T_8537, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8539 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8540 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8541 = eq(_T_8540, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42355,7 +42355,7 @@ circuit el2_ifu :
     node _T_8545 = and(_T_8542, _T_8544) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8546 = or(_T_8545, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8547 = bits(_T_8546, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8548 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8549 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8550 = eq(_T_8549, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42365,7 +42365,7 @@ circuit el2_ifu :
     node _T_8554 = and(_T_8551, _T_8553) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8555 = or(_T_8554, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8556 = bits(_T_8555, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8557 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8558 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8559 = eq(_T_8558, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42375,7 +42375,7 @@ circuit el2_ifu :
     node _T_8563 = and(_T_8560, _T_8562) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8564 = or(_T_8563, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8565 = bits(_T_8564, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8566 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8567 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8568 = eq(_T_8567, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42385,7 +42385,7 @@ circuit el2_ifu :
     node _T_8572 = and(_T_8569, _T_8571) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8573 = or(_T_8572, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8574 = bits(_T_8573, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8575 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8576 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8577 = eq(_T_8576, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42395,7 +42395,7 @@ circuit el2_ifu :
     node _T_8581 = and(_T_8578, _T_8580) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8582 = or(_T_8581, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8583 = bits(_T_8582, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8584 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8585 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8586 = eq(_T_8585, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42405,7 +42405,7 @@ circuit el2_ifu :
     node _T_8590 = and(_T_8587, _T_8589) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8591 = or(_T_8590, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8592 = bits(_T_8591, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8593 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8594 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8595 = eq(_T_8594, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42415,7 +42415,7 @@ circuit el2_ifu :
     node _T_8599 = and(_T_8596, _T_8598) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8600 = or(_T_8599, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8601 = bits(_T_8600, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8602 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8603 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8604 = eq(_T_8603, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42425,7 +42425,7 @@ circuit el2_ifu :
     node _T_8608 = and(_T_8605, _T_8607) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8609 = or(_T_8608, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8610 = bits(_T_8609, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8611 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8612 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8613 = eq(_T_8612, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42435,7 +42435,7 @@ circuit el2_ifu :
     node _T_8617 = and(_T_8614, _T_8616) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8618 = or(_T_8617, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8619 = bits(_T_8618, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8620 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8621 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8622 = eq(_T_8621, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42445,7 +42445,7 @@ circuit el2_ifu :
     node _T_8626 = and(_T_8623, _T_8625) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8627 = or(_T_8626, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8628 = bits(_T_8627, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8629 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8630 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8631 = eq(_T_8630, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42455,7 +42455,7 @@ circuit el2_ifu :
     node _T_8635 = and(_T_8632, _T_8634) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8636 = or(_T_8635, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8637 = bits(_T_8636, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8638 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8639 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8640 = eq(_T_8639, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42465,7 +42465,7 @@ circuit el2_ifu :
     node _T_8644 = and(_T_8641, _T_8643) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8645 = or(_T_8644, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8646 = bits(_T_8645, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8647 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8648 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8649 = eq(_T_8648, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42475,7 +42475,7 @@ circuit el2_ifu :
     node _T_8653 = and(_T_8650, _T_8652) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8654 = or(_T_8653, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8655 = bits(_T_8654, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8656 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8657 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8658 = eq(_T_8657, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42485,7 +42485,7 @@ circuit el2_ifu :
     node _T_8662 = and(_T_8659, _T_8661) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8663 = or(_T_8662, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8664 = bits(_T_8663, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8665 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8666 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8667 = eq(_T_8666, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42495,7 +42495,7 @@ circuit el2_ifu :
     node _T_8671 = and(_T_8668, _T_8670) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8672 = or(_T_8671, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8673 = bits(_T_8672, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8674 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8675 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8676 = eq(_T_8675, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42505,7 +42505,7 @@ circuit el2_ifu :
     node _T_8680 = and(_T_8677, _T_8679) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8681 = or(_T_8680, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8682 = bits(_T_8681, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8683 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8684 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8685 = eq(_T_8684, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42515,7 +42515,7 @@ circuit el2_ifu :
     node _T_8689 = and(_T_8686, _T_8688) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8690 = or(_T_8689, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8691 = bits(_T_8690, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8692 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8693 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8694 = eq(_T_8693, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42525,7 +42525,7 @@ circuit el2_ifu :
     node _T_8698 = and(_T_8695, _T_8697) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8699 = or(_T_8698, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8700 = bits(_T_8699, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8701 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8702 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8703 = eq(_T_8702, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42535,7 +42535,7 @@ circuit el2_ifu :
     node _T_8707 = and(_T_8704, _T_8706) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8708 = or(_T_8707, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8709 = bits(_T_8708, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8710 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8711 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8712 = eq(_T_8711, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42545,7 +42545,7 @@ circuit el2_ifu :
     node _T_8716 = and(_T_8713, _T_8715) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8717 = or(_T_8716, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8718 = bits(_T_8717, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8719 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8720 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8721 = eq(_T_8720, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42555,7 +42555,7 @@ circuit el2_ifu :
     node _T_8725 = and(_T_8722, _T_8724) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8726 = or(_T_8725, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8727 = bits(_T_8726, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8728 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8729 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8730 = eq(_T_8729, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42565,7 +42565,7 @@ circuit el2_ifu :
     node _T_8734 = and(_T_8731, _T_8733) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8735 = or(_T_8734, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8736 = bits(_T_8735, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8737 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8738 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8739 = eq(_T_8738, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42575,7 +42575,7 @@ circuit el2_ifu :
     node _T_8743 = and(_T_8740, _T_8742) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8744 = or(_T_8743, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8745 = bits(_T_8744, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8746 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8747 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8748 = eq(_T_8747, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42585,7 +42585,7 @@ circuit el2_ifu :
     node _T_8752 = and(_T_8749, _T_8751) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8753 = or(_T_8752, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8754 = bits(_T_8753, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8755 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8756 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8757 = eq(_T_8756, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42595,7 +42595,7 @@ circuit el2_ifu :
     node _T_8761 = and(_T_8758, _T_8760) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8762 = or(_T_8761, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8763 = bits(_T_8762, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8764 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8765 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8766 = eq(_T_8765, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42605,7 +42605,7 @@ circuit el2_ifu :
     node _T_8770 = and(_T_8767, _T_8769) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8771 = or(_T_8770, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8772 = bits(_T_8771, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8773 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8774 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8775 = eq(_T_8774, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42615,7 +42615,7 @@ circuit el2_ifu :
     node _T_8779 = and(_T_8776, _T_8778) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8780 = or(_T_8779, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8781 = bits(_T_8780, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8782 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8783 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8784 = eq(_T_8783, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42625,7 +42625,7 @@ circuit el2_ifu :
     node _T_8788 = and(_T_8785, _T_8787) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8789 = or(_T_8788, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8790 = bits(_T_8789, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8791 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8792 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8793 = eq(_T_8792, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42635,7 +42635,7 @@ circuit el2_ifu :
     node _T_8797 = and(_T_8794, _T_8796) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8798 = or(_T_8797, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8799 = bits(_T_8798, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8800 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8801 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8802 = eq(_T_8801, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42645,7 +42645,7 @@ circuit el2_ifu :
     node _T_8806 = and(_T_8803, _T_8805) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8807 = or(_T_8806, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8808 = bits(_T_8807, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8809 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8810 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8811 = eq(_T_8810, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42655,7 +42655,7 @@ circuit el2_ifu :
     node _T_8815 = and(_T_8812, _T_8814) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8816 = or(_T_8815, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8817 = bits(_T_8816, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8818 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8819 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8820 = eq(_T_8819, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42665,7 +42665,7 @@ circuit el2_ifu :
     node _T_8824 = and(_T_8821, _T_8823) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8825 = or(_T_8824, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8826 = bits(_T_8825, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8827 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8828 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8829 = eq(_T_8828, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42675,7 +42675,7 @@ circuit el2_ifu :
     node _T_8833 = and(_T_8830, _T_8832) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8834 = or(_T_8833, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8835 = bits(_T_8834, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8836 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8837 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8838 = eq(_T_8837, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42685,7 +42685,7 @@ circuit el2_ifu :
     node _T_8842 = and(_T_8839, _T_8841) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8843 = or(_T_8842, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8844 = bits(_T_8843, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8845 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8846 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8847 = eq(_T_8846, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42695,7 +42695,7 @@ circuit el2_ifu :
     node _T_8851 = and(_T_8848, _T_8850) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8852 = or(_T_8851, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8853 = bits(_T_8852, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8854 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8855 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8856 = eq(_T_8855, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42705,7 +42705,7 @@ circuit el2_ifu :
     node _T_8860 = and(_T_8857, _T_8859) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8861 = or(_T_8860, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8862 = bits(_T_8861, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8863 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8864 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8865 = eq(_T_8864, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42715,7 +42715,7 @@ circuit el2_ifu :
     node _T_8869 = and(_T_8866, _T_8868) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8870 = or(_T_8869, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8871 = bits(_T_8870, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8872 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8873 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8874 = eq(_T_8873, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42725,7 +42725,7 @@ circuit el2_ifu :
     node _T_8878 = and(_T_8875, _T_8877) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8879 = or(_T_8878, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8880 = bits(_T_8879, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8881 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8882 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8883 = eq(_T_8882, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42735,7 +42735,7 @@ circuit el2_ifu :
     node _T_8887 = and(_T_8884, _T_8886) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8888 = or(_T_8887, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8889 = bits(_T_8888, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8890 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8891 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8892 = eq(_T_8891, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42745,7 +42745,7 @@ circuit el2_ifu :
     node _T_8896 = and(_T_8893, _T_8895) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8897 = or(_T_8896, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8898 = bits(_T_8897, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8899 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8900 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8901 = eq(_T_8900, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42755,7 +42755,7 @@ circuit el2_ifu :
     node _T_8905 = and(_T_8902, _T_8904) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8906 = or(_T_8905, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8907 = bits(_T_8906, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8908 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8909 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8910 = eq(_T_8909, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42765,7 +42765,7 @@ circuit el2_ifu :
     node _T_8914 = and(_T_8911, _T_8913) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8915 = or(_T_8914, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8916 = bits(_T_8915, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8917 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8918 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8919 = eq(_T_8918, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42775,7 +42775,7 @@ circuit el2_ifu :
     node _T_8923 = and(_T_8920, _T_8922) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8924 = or(_T_8923, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8925 = bits(_T_8924, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8926 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8927 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8928 = eq(_T_8927, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42785,7 +42785,7 @@ circuit el2_ifu :
     node _T_8932 = and(_T_8929, _T_8931) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8933 = or(_T_8932, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8934 = bits(_T_8933, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8935 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8936 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8937 = eq(_T_8936, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42795,7 +42795,7 @@ circuit el2_ifu :
     node _T_8941 = and(_T_8938, _T_8940) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8942 = or(_T_8941, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8943 = bits(_T_8942, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8944 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8945 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8946 = eq(_T_8945, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42805,7 +42805,7 @@ circuit el2_ifu :
     node _T_8950 = and(_T_8947, _T_8949) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8951 = or(_T_8950, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8952 = bits(_T_8951, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8953 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8954 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8955 = eq(_T_8954, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42815,7 +42815,7 @@ circuit el2_ifu :
     node _T_8959 = and(_T_8956, _T_8958) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8960 = or(_T_8959, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8961 = bits(_T_8960, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8962 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8963 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8964 = eq(_T_8963, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42825,7 +42825,7 @@ circuit el2_ifu :
     node _T_8968 = and(_T_8965, _T_8967) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8969 = or(_T_8968, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8970 = bits(_T_8969, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8971 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8972 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8973 = eq(_T_8972, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42835,7 +42835,7 @@ circuit el2_ifu :
     node _T_8977 = and(_T_8974, _T_8976) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8978 = or(_T_8977, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8979 = bits(_T_8978, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8980 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8981 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8982 = eq(_T_8981, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42845,7 +42845,7 @@ circuit el2_ifu :
     node _T_8986 = and(_T_8983, _T_8985) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8987 = or(_T_8986, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8988 = bits(_T_8987, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8989 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8990 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8991 = eq(_T_8990, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42855,7 +42855,7 @@ circuit el2_ifu :
     node _T_8995 = and(_T_8992, _T_8994) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8996 = or(_T_8995, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8997 = bits(_T_8996, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8998 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8999 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9000 = eq(_T_8999, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42865,7 +42865,7 @@ circuit el2_ifu :
     node _T_9004 = and(_T_9001, _T_9003) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9005 = or(_T_9004, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9006 = bits(_T_9005, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9007 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9008 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9009 = eq(_T_9008, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42875,7 +42875,7 @@ circuit el2_ifu :
     node _T_9013 = and(_T_9010, _T_9012) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9014 = or(_T_9013, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9015 = bits(_T_9014, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9016 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9017 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9018 = eq(_T_9017, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42885,7 +42885,7 @@ circuit el2_ifu :
     node _T_9022 = and(_T_9019, _T_9021) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9023 = or(_T_9022, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9024 = bits(_T_9023, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9025 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9026 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9027 = eq(_T_9026, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42895,7 +42895,7 @@ circuit el2_ifu :
     node _T_9031 = and(_T_9028, _T_9030) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9032 = or(_T_9031, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9033 = bits(_T_9032, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9034 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9035 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9036 = eq(_T_9035, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42905,7 +42905,7 @@ circuit el2_ifu :
     node _T_9040 = and(_T_9037, _T_9039) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9041 = or(_T_9040, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9042 = bits(_T_9041, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9043 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9044 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9045 = eq(_T_9044, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42915,7 +42915,7 @@ circuit el2_ifu :
     node _T_9049 = and(_T_9046, _T_9048) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9050 = or(_T_9049, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9051 = bits(_T_9050, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9052 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9053 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9054 = eq(_T_9053, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42925,7 +42925,7 @@ circuit el2_ifu :
     node _T_9058 = and(_T_9055, _T_9057) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9059 = or(_T_9058, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9060 = bits(_T_9059, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9061 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9062 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9063 = eq(_T_9062, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42935,7 +42935,7 @@ circuit el2_ifu :
     node _T_9067 = and(_T_9064, _T_9066) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9068 = or(_T_9067, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9069 = bits(_T_9068, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9070 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9071 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9072 = eq(_T_9071, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42945,7 +42945,7 @@ circuit el2_ifu :
     node _T_9076 = and(_T_9073, _T_9075) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9077 = or(_T_9076, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9078 = bits(_T_9077, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9079 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9080 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9081 = eq(_T_9080, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42955,7 +42955,7 @@ circuit el2_ifu :
     node _T_9085 = and(_T_9082, _T_9084) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9086 = or(_T_9085, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9087 = bits(_T_9086, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9088 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9089 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9090 = eq(_T_9089, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42965,7 +42965,7 @@ circuit el2_ifu :
     node _T_9094 = and(_T_9091, _T_9093) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9095 = or(_T_9094, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9096 = bits(_T_9095, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9097 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9098 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9099 = eq(_T_9098, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42975,7 +42975,7 @@ circuit el2_ifu :
     node _T_9103 = and(_T_9100, _T_9102) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9104 = or(_T_9103, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9105 = bits(_T_9104, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9106 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9107 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9108 = eq(_T_9107, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42985,7 +42985,7 @@ circuit el2_ifu :
     node _T_9112 = and(_T_9109, _T_9111) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9113 = or(_T_9112, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9114 = bits(_T_9113, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9115 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9116 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9117 = eq(_T_9116, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42995,7 +42995,7 @@ circuit el2_ifu :
     node _T_9121 = and(_T_9118, _T_9120) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9122 = or(_T_9121, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9123 = bits(_T_9122, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9124 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9125 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9126 = eq(_T_9125, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43005,7 +43005,7 @@ circuit el2_ifu :
     node _T_9130 = and(_T_9127, _T_9129) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9131 = or(_T_9130, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9132 = bits(_T_9131, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9133 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9134 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9135 = eq(_T_9134, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43015,7 +43015,7 @@ circuit el2_ifu :
     node _T_9139 = and(_T_9136, _T_9138) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9140 = or(_T_9139, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9141 = bits(_T_9140, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9142 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9143 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9144 = eq(_T_9143, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43025,7 +43025,7 @@ circuit el2_ifu :
     node _T_9148 = and(_T_9145, _T_9147) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9149 = or(_T_9148, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9150 = bits(_T_9149, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9151 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9152 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9153 = eq(_T_9152, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43035,7 +43035,7 @@ circuit el2_ifu :
     node _T_9157 = and(_T_9154, _T_9156) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9158 = or(_T_9157, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9159 = bits(_T_9158, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9160 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9161 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9162 = eq(_T_9161, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43045,7 +43045,7 @@ circuit el2_ifu :
     node _T_9166 = and(_T_9163, _T_9165) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9167 = or(_T_9166, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9168 = bits(_T_9167, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9169 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9170 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9171 = eq(_T_9170, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43055,7 +43055,7 @@ circuit el2_ifu :
     node _T_9175 = and(_T_9172, _T_9174) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9176 = or(_T_9175, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9177 = bits(_T_9176, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9178 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9179 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9180 = eq(_T_9179, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43065,7 +43065,7 @@ circuit el2_ifu :
     node _T_9184 = and(_T_9181, _T_9183) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9185 = or(_T_9184, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9186 = bits(_T_9185, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9187 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9188 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9189 = eq(_T_9188, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43075,7 +43075,7 @@ circuit el2_ifu :
     node _T_9193 = and(_T_9190, _T_9192) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9194 = or(_T_9193, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9195 = bits(_T_9194, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9196 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9197 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9198 = eq(_T_9197, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43085,7 +43085,7 @@ circuit el2_ifu :
     node _T_9202 = and(_T_9199, _T_9201) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9203 = or(_T_9202, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9204 = bits(_T_9203, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9205 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9206 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9207 = eq(_T_9206, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43095,7 +43095,7 @@ circuit el2_ifu :
     node _T_9211 = and(_T_9208, _T_9210) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9212 = or(_T_9211, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9213 = bits(_T_9212, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9214 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9215 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9216 = eq(_T_9215, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43105,7 +43105,7 @@ circuit el2_ifu :
     node _T_9220 = and(_T_9217, _T_9219) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9221 = or(_T_9220, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9222 = bits(_T_9221, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9223 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9224 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9225 = eq(_T_9224, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43115,7 +43115,7 @@ circuit el2_ifu :
     node _T_9229 = and(_T_9226, _T_9228) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9230 = or(_T_9229, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9231 = bits(_T_9230, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9232 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9233 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9234 = eq(_T_9233, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43125,7 +43125,7 @@ circuit el2_ifu :
     node _T_9238 = and(_T_9235, _T_9237) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9239 = or(_T_9238, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9240 = bits(_T_9239, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9241 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9242 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9243 = eq(_T_9242, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43135,7 +43135,7 @@ circuit el2_ifu :
     node _T_9247 = and(_T_9244, _T_9246) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9248 = or(_T_9247, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9249 = bits(_T_9248, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9250 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9251 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9252 = eq(_T_9251, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43145,7 +43145,7 @@ circuit el2_ifu :
     node _T_9256 = and(_T_9253, _T_9255) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9257 = or(_T_9256, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9258 = bits(_T_9257, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9259 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9260 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9261 = eq(_T_9260, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43155,7 +43155,7 @@ circuit el2_ifu :
     node _T_9265 = and(_T_9262, _T_9264) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9266 = or(_T_9265, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9267 = bits(_T_9266, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9268 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9269 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9270 = eq(_T_9269, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43165,7 +43165,7 @@ circuit el2_ifu :
     node _T_9274 = and(_T_9271, _T_9273) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9275 = or(_T_9274, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9276 = bits(_T_9275, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9277 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9278 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9279 = eq(_T_9278, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43175,7 +43175,7 @@ circuit el2_ifu :
     node _T_9283 = and(_T_9280, _T_9282) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9284 = or(_T_9283, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9285 = bits(_T_9284, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9286 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9287 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9288 = eq(_T_9287, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43185,7 +43185,7 @@ circuit el2_ifu :
     node _T_9292 = and(_T_9289, _T_9291) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9293 = or(_T_9292, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9294 = bits(_T_9293, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9295 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9296 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9297 = eq(_T_9296, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43195,7 +43195,7 @@ circuit el2_ifu :
     node _T_9301 = and(_T_9298, _T_9300) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9302 = or(_T_9301, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9303 = bits(_T_9302, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9304 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9305 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9306 = eq(_T_9305, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43205,7 +43205,7 @@ circuit el2_ifu :
     node _T_9310 = and(_T_9307, _T_9309) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9311 = or(_T_9310, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9312 = bits(_T_9311, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9313 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9314 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9315 = eq(_T_9314, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43215,7 +43215,7 @@ circuit el2_ifu :
     node _T_9319 = and(_T_9316, _T_9318) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9320 = or(_T_9319, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9321 = bits(_T_9320, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9322 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9323 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9324 = eq(_T_9323, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43225,7 +43225,7 @@ circuit el2_ifu :
     node _T_9328 = and(_T_9325, _T_9327) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9329 = or(_T_9328, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9330 = bits(_T_9329, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9331 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9332 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9333 = eq(_T_9332, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43235,7 +43235,7 @@ circuit el2_ifu :
     node _T_9337 = and(_T_9334, _T_9336) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9338 = or(_T_9337, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9339 = bits(_T_9338, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9340 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9341 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9342 = eq(_T_9341, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43245,7 +43245,7 @@ circuit el2_ifu :
     node _T_9346 = and(_T_9343, _T_9345) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9347 = or(_T_9346, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9348 = bits(_T_9347, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9349 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9350 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9351 = eq(_T_9350, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43255,7 +43255,7 @@ circuit el2_ifu :
     node _T_9355 = and(_T_9352, _T_9354) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9356 = or(_T_9355, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9357 = bits(_T_9356, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9358 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9359 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9360 = eq(_T_9359, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43265,7 +43265,7 @@ circuit el2_ifu :
     node _T_9364 = and(_T_9361, _T_9363) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9365 = or(_T_9364, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9366 = bits(_T_9365, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9367 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9368 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9369 = eq(_T_9368, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43275,7 +43275,7 @@ circuit el2_ifu :
     node _T_9373 = and(_T_9370, _T_9372) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9374 = or(_T_9373, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9375 = bits(_T_9374, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9376 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9377 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9378 = eq(_T_9377, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43285,7 +43285,7 @@ circuit el2_ifu :
     node _T_9382 = and(_T_9379, _T_9381) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9383 = or(_T_9382, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9384 = bits(_T_9383, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9385 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9386 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9387 = eq(_T_9386, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43295,7 +43295,7 @@ circuit el2_ifu :
     node _T_9391 = and(_T_9388, _T_9390) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9392 = or(_T_9391, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9393 = bits(_T_9392, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9394 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9395 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9396 = eq(_T_9395, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43305,7 +43305,7 @@ circuit el2_ifu :
     node _T_9400 = and(_T_9397, _T_9399) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9401 = or(_T_9400, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9402 = bits(_T_9401, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9403 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9404 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9405 = eq(_T_9404, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43315,7 +43315,7 @@ circuit el2_ifu :
     node _T_9409 = and(_T_9406, _T_9408) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9410 = or(_T_9409, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9411 = bits(_T_9410, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9412 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9413 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9414 = eq(_T_9413, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43325,7 +43325,7 @@ circuit el2_ifu :
     node _T_9418 = and(_T_9415, _T_9417) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9419 = or(_T_9418, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9420 = bits(_T_9419, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9421 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9422 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9423 = eq(_T_9422, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43335,7 +43335,7 @@ circuit el2_ifu :
     node _T_9427 = and(_T_9424, _T_9426) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9428 = or(_T_9427, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9429 = bits(_T_9428, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9430 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9431 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9432 = eq(_T_9431, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43345,7 +43345,7 @@ circuit el2_ifu :
     node _T_9436 = and(_T_9433, _T_9435) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9437 = or(_T_9436, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9438 = bits(_T_9437, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9439 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9440 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9441 = eq(_T_9440, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43355,7 +43355,7 @@ circuit el2_ifu :
     node _T_9445 = and(_T_9442, _T_9444) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9446 = or(_T_9445, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9447 = bits(_T_9446, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9448 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9449 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9450 = eq(_T_9449, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43365,7 +43365,7 @@ circuit el2_ifu :
     node _T_9454 = and(_T_9451, _T_9453) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9455 = or(_T_9454, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9456 = bits(_T_9455, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9457 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9458 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9459 = eq(_T_9458, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43375,7 +43375,7 @@ circuit el2_ifu :
     node _T_9463 = and(_T_9460, _T_9462) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9464 = or(_T_9463, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9465 = bits(_T_9464, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9466 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9467 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9468 = eq(_T_9467, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43385,7 +43385,7 @@ circuit el2_ifu :
     node _T_9472 = and(_T_9469, _T_9471) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9473 = or(_T_9472, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9474 = bits(_T_9473, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9475 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9476 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9477 = eq(_T_9476, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43395,7 +43395,7 @@ circuit el2_ifu :
     node _T_9481 = and(_T_9478, _T_9480) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9482 = or(_T_9481, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9483 = bits(_T_9482, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9484 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9485 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9486 = eq(_T_9485, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43405,7 +43405,7 @@ circuit el2_ifu :
     node _T_9490 = and(_T_9487, _T_9489) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9491 = or(_T_9490, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9492 = bits(_T_9491, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9493 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9494 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9495 = eq(_T_9494, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43415,7 +43415,7 @@ circuit el2_ifu :
     node _T_9499 = and(_T_9496, _T_9498) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9500 = or(_T_9499, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9501 = bits(_T_9500, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9502 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9503 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9504 = eq(_T_9503, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43425,7 +43425,7 @@ circuit el2_ifu :
     node _T_9508 = and(_T_9505, _T_9507) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9509 = or(_T_9508, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9510 = bits(_T_9509, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9511 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9512 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9513 = eq(_T_9512, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43435,7 +43435,7 @@ circuit el2_ifu :
     node _T_9517 = and(_T_9514, _T_9516) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9518 = or(_T_9517, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9519 = bits(_T_9518, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9520 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9521 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9522 = eq(_T_9521, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43445,7 +43445,7 @@ circuit el2_ifu :
     node _T_9526 = and(_T_9523, _T_9525) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9527 = or(_T_9526, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9528 = bits(_T_9527, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9529 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9530 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9531 = eq(_T_9530, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43455,7 +43455,7 @@ circuit el2_ifu :
     node _T_9535 = and(_T_9532, _T_9534) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9536 = or(_T_9535, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9537 = bits(_T_9536, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9538 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9539 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9540 = eq(_T_9539, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43465,7 +43465,7 @@ circuit el2_ifu :
     node _T_9544 = and(_T_9541, _T_9543) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9545 = or(_T_9544, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9546 = bits(_T_9545, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9547 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9548 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9549 = eq(_T_9548, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43475,7 +43475,7 @@ circuit el2_ifu :
     node _T_9553 = and(_T_9550, _T_9552) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9554 = or(_T_9553, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9555 = bits(_T_9554, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9556 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9557 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9558 = eq(_T_9557, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43485,7 +43485,7 @@ circuit el2_ifu :
     node _T_9562 = and(_T_9559, _T_9561) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9563 = or(_T_9562, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9564 = bits(_T_9563, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9565 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9566 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9567 = eq(_T_9566, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43495,7 +43495,7 @@ circuit el2_ifu :
     node _T_9571 = and(_T_9568, _T_9570) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9572 = or(_T_9571, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9573 = bits(_T_9572, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9574 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9575 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9576 = eq(_T_9575, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43505,7 +43505,7 @@ circuit el2_ifu :
     node _T_9580 = and(_T_9577, _T_9579) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9581 = or(_T_9580, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9582 = bits(_T_9581, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9583 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9584 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9585 = eq(_T_9584, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43515,7 +43515,7 @@ circuit el2_ifu :
     node _T_9589 = and(_T_9586, _T_9588) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9590 = or(_T_9589, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9591 = bits(_T_9590, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9592 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9593 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9594 = eq(_T_9593, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43525,7 +43525,7 @@ circuit el2_ifu :
     node _T_9598 = and(_T_9595, _T_9597) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9599 = or(_T_9598, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9600 = bits(_T_9599, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9601 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9602 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9603 = eq(_T_9602, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43535,7 +43535,7 @@ circuit el2_ifu :
     node _T_9607 = and(_T_9604, _T_9606) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9608 = or(_T_9607, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9609 = bits(_T_9608, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9610 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9611 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9612 = eq(_T_9611, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43545,7 +43545,7 @@ circuit el2_ifu :
     node _T_9616 = and(_T_9613, _T_9615) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9617 = or(_T_9616, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9618 = bits(_T_9617, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9619 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9620 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9621 = eq(_T_9620, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43555,7 +43555,7 @@ circuit el2_ifu :
     node _T_9625 = and(_T_9622, _T_9624) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9626 = or(_T_9625, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9627 = bits(_T_9626, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9628 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9629 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9630 = eq(_T_9629, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43565,7 +43565,7 @@ circuit el2_ifu :
     node _T_9634 = and(_T_9631, _T_9633) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9635 = or(_T_9634, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9636 = bits(_T_9635, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9637 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9638 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9639 = eq(_T_9638, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43575,7 +43575,7 @@ circuit el2_ifu :
     node _T_9643 = and(_T_9640, _T_9642) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9644 = or(_T_9643, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9645 = bits(_T_9644, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9646 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9647 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9648 = eq(_T_9647, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43585,7 +43585,7 @@ circuit el2_ifu :
     node _T_9652 = and(_T_9649, _T_9651) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9653 = or(_T_9652, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9654 = bits(_T_9653, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9655 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9656 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9657 = eq(_T_9656, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43595,7 +43595,7 @@ circuit el2_ifu :
     node _T_9661 = and(_T_9658, _T_9660) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9662 = or(_T_9661, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9663 = bits(_T_9662, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9664 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9665 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9666 = eq(_T_9665, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43605,7 +43605,7 @@ circuit el2_ifu :
     node _T_9670 = and(_T_9667, _T_9669) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9671 = or(_T_9670, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9672 = bits(_T_9671, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9673 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9674 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9675 = eq(_T_9674, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43615,7 +43615,7 @@ circuit el2_ifu :
     node _T_9679 = and(_T_9676, _T_9678) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9680 = or(_T_9679, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9681 = bits(_T_9680, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9682 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9683 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9684 = eq(_T_9683, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43625,7 +43625,7 @@ circuit el2_ifu :
     node _T_9688 = and(_T_9685, _T_9687) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9689 = or(_T_9688, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9690 = bits(_T_9689, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9691 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9692 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9693 = eq(_T_9692, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43635,7 +43635,7 @@ circuit el2_ifu :
     node _T_9697 = and(_T_9694, _T_9696) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9698 = or(_T_9697, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9699 = bits(_T_9698, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9700 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9701 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9702 = eq(_T_9701, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43645,7 +43645,7 @@ circuit el2_ifu :
     node _T_9706 = and(_T_9703, _T_9705) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9707 = or(_T_9706, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9708 = bits(_T_9707, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9709 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9710 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9711 = eq(_T_9710, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43655,7 +43655,7 @@ circuit el2_ifu :
     node _T_9715 = and(_T_9712, _T_9714) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9716 = or(_T_9715, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9717 = bits(_T_9716, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9718 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9719 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9720 = eq(_T_9719, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43665,7 +43665,7 @@ circuit el2_ifu :
     node _T_9724 = and(_T_9721, _T_9723) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9725 = or(_T_9724, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9726 = bits(_T_9725, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9727 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9728 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9729 = eq(_T_9728, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43675,7 +43675,7 @@ circuit el2_ifu :
     node _T_9733 = and(_T_9730, _T_9732) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9734 = or(_T_9733, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9735 = bits(_T_9734, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9736 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9737 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9738 = eq(_T_9737, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43685,7 +43685,7 @@ circuit el2_ifu :
     node _T_9742 = and(_T_9739, _T_9741) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9743 = or(_T_9742, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9744 = bits(_T_9743, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9745 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9746 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9747 = eq(_T_9746, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43695,7 +43695,7 @@ circuit el2_ifu :
     node _T_9751 = and(_T_9748, _T_9750) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9752 = or(_T_9751, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9753 = bits(_T_9752, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9754 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9755 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9756 = eq(_T_9755, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43705,7 +43705,7 @@ circuit el2_ifu :
     node _T_9760 = and(_T_9757, _T_9759) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9761 = or(_T_9760, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9762 = bits(_T_9761, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9763 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9764 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9765 = eq(_T_9764, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43715,7 +43715,7 @@ circuit el2_ifu :
     node _T_9769 = and(_T_9766, _T_9768) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9770 = or(_T_9769, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9771 = bits(_T_9770, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9772 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9773 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9774 = eq(_T_9773, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43725,7 +43725,7 @@ circuit el2_ifu :
     node _T_9778 = and(_T_9775, _T_9777) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9779 = or(_T_9778, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9780 = bits(_T_9779, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9781 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9782 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9783 = eq(_T_9782, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43735,7 +43735,7 @@ circuit el2_ifu :
     node _T_9787 = and(_T_9784, _T_9786) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9788 = or(_T_9787, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9789 = bits(_T_9788, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9790 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9791 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9792 = eq(_T_9791, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43745,7 +43745,7 @@ circuit el2_ifu :
     node _T_9796 = and(_T_9793, _T_9795) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9797 = or(_T_9796, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9798 = bits(_T_9797, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9799 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9800 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9801 = eq(_T_9800, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43755,7 +43755,7 @@ circuit el2_ifu :
     node _T_9805 = and(_T_9802, _T_9804) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9806 = or(_T_9805, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9807 = bits(_T_9806, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9808 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9809 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9810 = eq(_T_9809, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43765,7 +43765,7 @@ circuit el2_ifu :
     node _T_9814 = and(_T_9811, _T_9813) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9815 = or(_T_9814, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9816 = bits(_T_9815, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9817 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9818 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9819 = eq(_T_9818, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43775,7 +43775,7 @@ circuit el2_ifu :
     node _T_9823 = and(_T_9820, _T_9822) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9824 = or(_T_9823, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9825 = bits(_T_9824, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9826 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9827 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9828 = eq(_T_9827, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43785,7 +43785,7 @@ circuit el2_ifu :
     node _T_9832 = and(_T_9829, _T_9831) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9833 = or(_T_9832, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9834 = bits(_T_9833, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9835 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9836 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9837 = eq(_T_9836, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43795,7 +43795,7 @@ circuit el2_ifu :
     node _T_9841 = and(_T_9838, _T_9840) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9842 = or(_T_9841, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9843 = bits(_T_9842, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9844 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9845 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9846 = eq(_T_9845, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43805,7 +43805,7 @@ circuit el2_ifu :
     node _T_9850 = and(_T_9847, _T_9849) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9851 = or(_T_9850, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9852 = bits(_T_9851, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9853 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9854 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9855 = eq(_T_9854, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43815,7 +43815,7 @@ circuit el2_ifu :
     node _T_9859 = and(_T_9856, _T_9858) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9860 = or(_T_9859, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9861 = bits(_T_9860, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9862 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9863 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9864 = eq(_T_9863, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43825,7 +43825,7 @@ circuit el2_ifu :
     node _T_9868 = and(_T_9865, _T_9867) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9869 = or(_T_9868, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9870 = bits(_T_9869, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9871 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9872 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9873 = eq(_T_9872, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43835,7 +43835,7 @@ circuit el2_ifu :
     node _T_9877 = and(_T_9874, _T_9876) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9878 = or(_T_9877, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9879 = bits(_T_9878, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9880 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9881 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9882 = eq(_T_9881, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43845,7 +43845,7 @@ circuit el2_ifu :
     node _T_9886 = and(_T_9883, _T_9885) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9887 = or(_T_9886, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9888 = bits(_T_9887, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9889 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9890 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9891 = eq(_T_9890, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43855,7 +43855,7 @@ circuit el2_ifu :
     node _T_9895 = and(_T_9892, _T_9894) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9896 = or(_T_9895, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9897 = bits(_T_9896, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9898 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9899 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9900 = eq(_T_9899, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43865,7 +43865,7 @@ circuit el2_ifu :
     node _T_9904 = and(_T_9901, _T_9903) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9905 = or(_T_9904, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9906 = bits(_T_9905, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9907 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9908 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9909 = eq(_T_9908, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43875,7 +43875,7 @@ circuit el2_ifu :
     node _T_9913 = and(_T_9910, _T_9912) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9914 = or(_T_9913, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9915 = bits(_T_9914, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9916 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9917 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9918 = eq(_T_9917, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43885,7 +43885,7 @@ circuit el2_ifu :
     node _T_9922 = and(_T_9919, _T_9921) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9923 = or(_T_9922, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9924 = bits(_T_9923, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9925 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9926 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9927 = eq(_T_9926, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43895,7 +43895,7 @@ circuit el2_ifu :
     node _T_9931 = and(_T_9928, _T_9930) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9932 = or(_T_9931, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9933 = bits(_T_9932, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9934 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9935 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9936 = eq(_T_9935, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43905,7 +43905,7 @@ circuit el2_ifu :
     node _T_9940 = and(_T_9937, _T_9939) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9941 = or(_T_9940, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9942 = bits(_T_9941, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9943 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9944 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9945 = eq(_T_9944, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43915,7 +43915,7 @@ circuit el2_ifu :
     node _T_9949 = and(_T_9946, _T_9948) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9950 = or(_T_9949, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9951 = bits(_T_9950, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9952 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9953 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9954 = eq(_T_9953, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43925,7 +43925,7 @@ circuit el2_ifu :
     node _T_9958 = and(_T_9955, _T_9957) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9959 = or(_T_9958, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9960 = bits(_T_9959, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9961 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9962 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9963 = eq(_T_9962, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43935,7 +43935,7 @@ circuit el2_ifu :
     node _T_9967 = and(_T_9964, _T_9966) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9968 = or(_T_9967, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9969 = bits(_T_9968, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9970 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9971 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9972 = eq(_T_9971, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43945,7 +43945,7 @@ circuit el2_ifu :
     node _T_9976 = and(_T_9973, _T_9975) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9977 = or(_T_9976, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9978 = bits(_T_9977, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9979 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9980 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9981 = eq(_T_9980, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43955,7 +43955,7 @@ circuit el2_ifu :
     node _T_9985 = and(_T_9982, _T_9984) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9986 = or(_T_9985, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9987 = bits(_T_9986, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9988 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9989 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9990 = eq(_T_9989, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43965,7 +43965,7 @@ circuit el2_ifu :
     node _T_9994 = and(_T_9991, _T_9993) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9995 = or(_T_9994, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9996 = bits(_T_9995, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9997 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9998 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9999 = eq(_T_9998, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43975,7 +43975,7 @@ circuit el2_ifu :
     node _T_10003 = and(_T_10000, _T_10002) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10004 = or(_T_10003, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10005 = bits(_T_10004, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10006 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10007 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10008 = eq(_T_10007, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43985,7 +43985,7 @@ circuit el2_ifu :
     node _T_10012 = and(_T_10009, _T_10011) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10013 = or(_T_10012, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10014 = bits(_T_10013, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10015 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10016 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10017 = eq(_T_10016, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43995,7 +43995,7 @@ circuit el2_ifu :
     node _T_10021 = and(_T_10018, _T_10020) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10022 = or(_T_10021, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10023 = bits(_T_10022, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10024 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10025 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10026 = eq(_T_10025, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44005,7 +44005,7 @@ circuit el2_ifu :
     node _T_10030 = and(_T_10027, _T_10029) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10031 = or(_T_10030, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10032 = bits(_T_10031, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10033 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10034 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10035 = eq(_T_10034, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44015,7 +44015,7 @@ circuit el2_ifu :
     node _T_10039 = and(_T_10036, _T_10038) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10040 = or(_T_10039, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10041 = bits(_T_10040, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10042 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10043 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10044 = eq(_T_10043, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44025,7 +44025,7 @@ circuit el2_ifu :
     node _T_10048 = and(_T_10045, _T_10047) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10049 = or(_T_10048, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10050 = bits(_T_10049, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10051 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10052 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10053 = eq(_T_10052, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44035,7 +44035,7 @@ circuit el2_ifu :
     node _T_10057 = and(_T_10054, _T_10056) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10058 = or(_T_10057, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10059 = bits(_T_10058, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10060 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10061 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10062 = eq(_T_10061, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44045,7 +44045,7 @@ circuit el2_ifu :
     node _T_10066 = and(_T_10063, _T_10065) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10067 = or(_T_10066, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10068 = bits(_T_10067, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10069 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10070 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10071 = eq(_T_10070, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44055,7 +44055,7 @@ circuit el2_ifu :
     node _T_10075 = and(_T_10072, _T_10074) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10076 = or(_T_10075, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10077 = bits(_T_10076, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10078 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10079 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10080 = eq(_T_10079, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44065,7 +44065,7 @@ circuit el2_ifu :
     node _T_10084 = and(_T_10081, _T_10083) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10085 = or(_T_10084, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10086 = bits(_T_10085, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10087 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10088 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10089 = eq(_T_10088, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44075,7 +44075,7 @@ circuit el2_ifu :
     node _T_10093 = and(_T_10090, _T_10092) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10094 = or(_T_10093, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10095 = bits(_T_10094, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10096 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10097 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10098 = eq(_T_10097, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44085,7 +44085,7 @@ circuit el2_ifu :
     node _T_10102 = and(_T_10099, _T_10101) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10103 = or(_T_10102, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10104 = bits(_T_10103, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10105 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10106 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10107 = eq(_T_10106, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44095,7 +44095,7 @@ circuit el2_ifu :
     node _T_10111 = and(_T_10108, _T_10110) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10112 = or(_T_10111, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10113 = bits(_T_10112, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10114 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10115 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10116 = eq(_T_10115, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44105,7 +44105,7 @@ circuit el2_ifu :
     node _T_10120 = and(_T_10117, _T_10119) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10121 = or(_T_10120, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10122 = bits(_T_10121, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10123 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10124 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10125 = eq(_T_10124, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44115,7 +44115,7 @@ circuit el2_ifu :
     node _T_10129 = and(_T_10126, _T_10128) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10130 = or(_T_10129, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10131 = bits(_T_10130, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10132 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10133 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10134 = eq(_T_10133, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44125,7 +44125,7 @@ circuit el2_ifu :
     node _T_10138 = and(_T_10135, _T_10137) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10139 = or(_T_10138, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10140 = bits(_T_10139, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10141 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10142 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10143 = eq(_T_10142, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44135,7 +44135,7 @@ circuit el2_ifu :
     node _T_10147 = and(_T_10144, _T_10146) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10148 = or(_T_10147, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10149 = bits(_T_10148, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10150 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10151 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10152 = eq(_T_10151, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44145,7 +44145,7 @@ circuit el2_ifu :
     node _T_10156 = and(_T_10153, _T_10155) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10157 = or(_T_10156, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10158 = bits(_T_10157, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10159 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10160 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10161 = eq(_T_10160, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44155,7 +44155,7 @@ circuit el2_ifu :
     node _T_10165 = and(_T_10162, _T_10164) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10166 = or(_T_10165, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10167 = bits(_T_10166, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10168 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10169 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10170 = eq(_T_10169, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44165,7 +44165,7 @@ circuit el2_ifu :
     node _T_10174 = and(_T_10171, _T_10173) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10175 = or(_T_10174, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10176 = bits(_T_10175, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10177 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10178 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10179 = eq(_T_10178, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44175,7 +44175,7 @@ circuit el2_ifu :
     node _T_10183 = and(_T_10180, _T_10182) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10184 = or(_T_10183, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10185 = bits(_T_10184, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10186 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10187 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10188 = eq(_T_10187, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44185,7 +44185,7 @@ circuit el2_ifu :
     node _T_10192 = and(_T_10189, _T_10191) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10193 = or(_T_10192, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10194 = bits(_T_10193, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10195 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10196 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10197 = eq(_T_10196, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44195,7 +44195,7 @@ circuit el2_ifu :
     node _T_10201 = and(_T_10198, _T_10200) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10202 = or(_T_10201, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10203 = bits(_T_10202, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10204 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10205 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10206 = eq(_T_10205, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44205,7 +44205,7 @@ circuit el2_ifu :
     node _T_10210 = and(_T_10207, _T_10209) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10211 = or(_T_10210, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10212 = bits(_T_10211, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10213 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10214 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10215 = eq(_T_10214, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44215,7 +44215,7 @@ circuit el2_ifu :
     node _T_10219 = and(_T_10216, _T_10218) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10220 = or(_T_10219, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10221 = bits(_T_10220, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10222 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10223 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10224 = eq(_T_10223, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44225,7 +44225,7 @@ circuit el2_ifu :
     node _T_10228 = and(_T_10225, _T_10227) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10229 = or(_T_10228, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10230 = bits(_T_10229, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10231 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10232 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10233 = eq(_T_10232, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44235,7 +44235,7 @@ circuit el2_ifu :
     node _T_10237 = and(_T_10234, _T_10236) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10238 = or(_T_10237, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10239 = bits(_T_10238, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10240 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10241 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10242 = eq(_T_10241, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44245,7 +44245,7 @@ circuit el2_ifu :
     node _T_10246 = and(_T_10243, _T_10245) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10247 = or(_T_10246, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10248 = bits(_T_10247, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10249 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10250 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10251 = eq(_T_10250, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44255,7 +44255,7 @@ circuit el2_ifu :
     node _T_10255 = and(_T_10252, _T_10254) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10256 = or(_T_10255, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10257 = bits(_T_10256, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10258 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10259 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10260 = eq(_T_10259, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44265,7 +44265,7 @@ circuit el2_ifu :
     node _T_10264 = and(_T_10261, _T_10263) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10265 = or(_T_10264, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10266 = bits(_T_10265, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10267 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10268 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10269 = eq(_T_10268, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44275,7 +44275,7 @@ circuit el2_ifu :
     node _T_10273 = and(_T_10270, _T_10272) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10274 = or(_T_10273, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10275 = bits(_T_10274, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10276 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10277 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10278 = eq(_T_10277, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44285,7 +44285,7 @@ circuit el2_ifu :
     node _T_10282 = and(_T_10279, _T_10281) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10283 = or(_T_10282, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10284 = bits(_T_10283, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10285 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10286 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10287 = eq(_T_10286, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44295,7 +44295,7 @@ circuit el2_ifu :
     node _T_10291 = and(_T_10288, _T_10290) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10292 = or(_T_10291, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10293 = bits(_T_10292, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10294 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10295 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10296 = eq(_T_10295, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44305,7 +44305,7 @@ circuit el2_ifu :
     node _T_10300 = and(_T_10297, _T_10299) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10301 = or(_T_10300, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10302 = bits(_T_10301, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10303 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10304 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10305 = eq(_T_10304, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44315,7 +44315,7 @@ circuit el2_ifu :
     node _T_10309 = and(_T_10306, _T_10308) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10310 = or(_T_10309, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10311 = bits(_T_10310, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10312 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10313 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10314 = eq(_T_10313, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44325,7 +44325,7 @@ circuit el2_ifu :
     node _T_10318 = and(_T_10315, _T_10317) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10319 = or(_T_10318, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10320 = bits(_T_10319, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10321 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10322 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10323 = eq(_T_10322, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44335,7 +44335,7 @@ circuit el2_ifu :
     node _T_10327 = and(_T_10324, _T_10326) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10328 = or(_T_10327, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10329 = bits(_T_10328, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10330 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10331 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10332 = eq(_T_10331, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44345,7 +44345,7 @@ circuit el2_ifu :
     node _T_10336 = and(_T_10333, _T_10335) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10337 = or(_T_10336, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10338 = bits(_T_10337, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10339 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10340 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10341 = eq(_T_10340, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44355,7 +44355,7 @@ circuit el2_ifu :
     node _T_10345 = and(_T_10342, _T_10344) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10346 = or(_T_10345, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10347 = bits(_T_10346, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10348 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10349 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10350 = eq(_T_10349, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44365,7 +44365,7 @@ circuit el2_ifu :
     node _T_10354 = and(_T_10351, _T_10353) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10355 = or(_T_10354, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10356 = bits(_T_10355, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10357 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10358 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10359 = eq(_T_10358, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44375,7 +44375,7 @@ circuit el2_ifu :
     node _T_10363 = and(_T_10360, _T_10362) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10364 = or(_T_10363, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10365 = bits(_T_10364, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10366 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10367 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10368 = eq(_T_10367, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44385,7 +44385,7 @@ circuit el2_ifu :
     node _T_10372 = and(_T_10369, _T_10371) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10373 = or(_T_10372, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10374 = bits(_T_10373, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10375 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10376 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10377 = eq(_T_10376, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44395,7 +44395,7 @@ circuit el2_ifu :
     node _T_10381 = and(_T_10378, _T_10380) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10382 = or(_T_10381, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10383 = bits(_T_10382, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10384 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10385 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10386 = eq(_T_10385, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44405,7 +44405,7 @@ circuit el2_ifu :
     node _T_10390 = and(_T_10387, _T_10389) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10391 = or(_T_10390, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10392 = bits(_T_10391, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10393 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10394 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10395 = eq(_T_10394, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44415,7 +44415,7 @@ circuit el2_ifu :
     node _T_10399 = and(_T_10396, _T_10398) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10400 = or(_T_10399, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10401 = bits(_T_10400, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10402 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10403 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10404 = eq(_T_10403, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44425,7 +44425,7 @@ circuit el2_ifu :
     node _T_10408 = and(_T_10405, _T_10407) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10409 = or(_T_10408, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10410 = bits(_T_10409, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10411 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10412 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10413 = eq(_T_10412, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44435,7 +44435,7 @@ circuit el2_ifu :
     node _T_10417 = and(_T_10414, _T_10416) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10418 = or(_T_10417, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10419 = bits(_T_10418, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10420 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10421 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10422 = eq(_T_10421, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44445,7 +44445,7 @@ circuit el2_ifu :
     node _T_10426 = and(_T_10423, _T_10425) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10427 = or(_T_10426, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10428 = bits(_T_10427, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10429 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10430 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10431 = eq(_T_10430, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44455,7 +44455,7 @@ circuit el2_ifu :
     node _T_10435 = and(_T_10432, _T_10434) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10436 = or(_T_10435, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10437 = bits(_T_10436, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10438 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10439 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10440 = eq(_T_10439, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44465,7 +44465,7 @@ circuit el2_ifu :
     node _T_10444 = and(_T_10441, _T_10443) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10445 = or(_T_10444, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10446 = bits(_T_10445, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10447 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10448 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10449 = eq(_T_10448, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44475,7 +44475,7 @@ circuit el2_ifu :
     node _T_10453 = and(_T_10450, _T_10452) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10454 = or(_T_10453, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10455 = bits(_T_10454, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10456 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10457 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10458 = eq(_T_10457, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44485,7 +44485,7 @@ circuit el2_ifu :
     node _T_10462 = and(_T_10459, _T_10461) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10463 = or(_T_10462, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10464 = bits(_T_10463, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10465 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10466 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10467 = eq(_T_10466, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44495,7 +44495,7 @@ circuit el2_ifu :
     node _T_10471 = and(_T_10468, _T_10470) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10472 = or(_T_10471, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10473 = bits(_T_10472, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10474 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10475 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10476 = eq(_T_10475, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44505,7 +44505,7 @@ circuit el2_ifu :
     node _T_10480 = and(_T_10477, _T_10479) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10481 = or(_T_10480, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10482 = bits(_T_10481, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10483 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10484 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10485 = eq(_T_10484, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44515,7 +44515,7 @@ circuit el2_ifu :
     node _T_10489 = and(_T_10486, _T_10488) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10490 = or(_T_10489, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10491 = bits(_T_10490, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10492 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10493 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10494 = eq(_T_10493, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44525,7 +44525,7 @@ circuit el2_ifu :
     node _T_10498 = and(_T_10495, _T_10497) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10499 = or(_T_10498, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10500 = bits(_T_10499, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10501 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10502 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10503 = eq(_T_10502, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44535,7 +44535,7 @@ circuit el2_ifu :
     node _T_10507 = and(_T_10504, _T_10506) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10508 = or(_T_10507, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10509 = bits(_T_10508, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10510 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10511 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10512 = eq(_T_10511, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44545,7 +44545,7 @@ circuit el2_ifu :
     node _T_10516 = and(_T_10513, _T_10515) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10517 = or(_T_10516, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10518 = bits(_T_10517, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10519 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10520 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10521 = eq(_T_10520, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44555,7 +44555,7 @@ circuit el2_ifu :
     node _T_10525 = and(_T_10522, _T_10524) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10526 = or(_T_10525, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10527 = bits(_T_10526, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10528 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10529 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10530 = eq(_T_10529, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44565,7 +44565,7 @@ circuit el2_ifu :
     node _T_10534 = and(_T_10531, _T_10533) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10535 = or(_T_10534, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10536 = bits(_T_10535, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10537 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10538 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10539 = eq(_T_10538, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44575,7 +44575,7 @@ circuit el2_ifu :
     node _T_10543 = and(_T_10540, _T_10542) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10544 = or(_T_10543, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10545 = bits(_T_10544, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10546 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10547 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10548 = eq(_T_10547, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44585,7 +44585,7 @@ circuit el2_ifu :
     node _T_10552 = and(_T_10549, _T_10551) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10553 = or(_T_10552, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10554 = bits(_T_10553, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10555 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10556 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10557 = eq(_T_10556, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44595,7 +44595,7 @@ circuit el2_ifu :
     node _T_10561 = and(_T_10558, _T_10560) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10562 = or(_T_10561, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10563 = bits(_T_10562, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10564 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10565 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10566 = eq(_T_10565, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44605,7 +44605,7 @@ circuit el2_ifu :
     node _T_10570 = and(_T_10567, _T_10569) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10571 = or(_T_10570, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10572 = bits(_T_10571, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10573 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10574 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10575 = eq(_T_10574, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44615,7 +44615,7 @@ circuit el2_ifu :
     node _T_10579 = and(_T_10576, _T_10578) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10580 = or(_T_10579, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10581 = bits(_T_10580, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10582 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10583 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10584 = eq(_T_10583, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44625,7 +44625,7 @@ circuit el2_ifu :
     node _T_10588 = and(_T_10585, _T_10587) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10589 = or(_T_10588, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10590 = bits(_T_10589, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10591 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10592 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10593 = eq(_T_10592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44635,7 +44635,7 @@ circuit el2_ifu :
     node _T_10597 = and(_T_10594, _T_10596) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10598 = or(_T_10597, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10599 = bits(_T_10598, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10600 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10601 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10602 = eq(_T_10601, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44645,7 +44645,7 @@ circuit el2_ifu :
     node _T_10606 = and(_T_10603, _T_10605) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10607 = or(_T_10606, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10608 = bits(_T_10607, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10609 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10610 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10611 = eq(_T_10610, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44655,7 +44655,7 @@ circuit el2_ifu :
     node _T_10615 = and(_T_10612, _T_10614) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10616 = or(_T_10615, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10617 = bits(_T_10616, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10618 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10619 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10620 = eq(_T_10619, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44665,7 +44665,7 @@ circuit el2_ifu :
     node _T_10624 = and(_T_10621, _T_10623) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10625 = or(_T_10624, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10626 = bits(_T_10625, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10627 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10628 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10629 = eq(_T_10628, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44675,7 +44675,7 @@ circuit el2_ifu :
     node _T_10633 = and(_T_10630, _T_10632) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10634 = or(_T_10633, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10635 = bits(_T_10634, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10636 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10637 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10638 = eq(_T_10637, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44685,7 +44685,7 @@ circuit el2_ifu :
     node _T_10642 = and(_T_10639, _T_10641) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10643 = or(_T_10642, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10644 = bits(_T_10643, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10645 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10646 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10647 = eq(_T_10646, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44695,7 +44695,7 @@ circuit el2_ifu :
     node _T_10651 = and(_T_10648, _T_10650) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10652 = or(_T_10651, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10653 = bits(_T_10652, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10654 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10655 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10656 = eq(_T_10655, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44705,7 +44705,7 @@ circuit el2_ifu :
     node _T_10660 = and(_T_10657, _T_10659) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10661 = or(_T_10660, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10662 = bits(_T_10661, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10663 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10664 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10665 = eq(_T_10664, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44715,7 +44715,7 @@ circuit el2_ifu :
     node _T_10669 = and(_T_10666, _T_10668) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10670 = or(_T_10669, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10671 = bits(_T_10670, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10672 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10673 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10674 = eq(_T_10673, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44725,7 +44725,7 @@ circuit el2_ifu :
     node _T_10678 = and(_T_10675, _T_10677) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10679 = or(_T_10678, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10680 = bits(_T_10679, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10681 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10682 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10683 = eq(_T_10682, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44735,7 +44735,7 @@ circuit el2_ifu :
     node _T_10687 = and(_T_10684, _T_10686) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10688 = or(_T_10687, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10689 = bits(_T_10688, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10690 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10691 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10692 = eq(_T_10691, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44745,7 +44745,7 @@ circuit el2_ifu :
     node _T_10696 = and(_T_10693, _T_10695) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10697 = or(_T_10696, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10698 = bits(_T_10697, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10699 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10700 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10701 = eq(_T_10700, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44755,7 +44755,7 @@ circuit el2_ifu :
     node _T_10705 = and(_T_10702, _T_10704) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10706 = or(_T_10705, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10707 = bits(_T_10706, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10708 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10709 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10710 = eq(_T_10709, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44765,7 +44765,7 @@ circuit el2_ifu :
     node _T_10714 = and(_T_10711, _T_10713) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10715 = or(_T_10714, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10716 = bits(_T_10715, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10717 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10718 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10719 = eq(_T_10718, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44775,7 +44775,7 @@ circuit el2_ifu :
     node _T_10723 = and(_T_10720, _T_10722) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10724 = or(_T_10723, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10725 = bits(_T_10724, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10726 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10727 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10728 = eq(_T_10727, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44785,7 +44785,7 @@ circuit el2_ifu :
     node _T_10732 = and(_T_10729, _T_10731) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10733 = or(_T_10732, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10734 = bits(_T_10733, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10735 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10736 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10737 = eq(_T_10736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44795,7 +44795,7 @@ circuit el2_ifu :
     node _T_10741 = and(_T_10738, _T_10740) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10742 = or(_T_10741, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10743 = bits(_T_10742, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10744 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10745 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10746 = eq(_T_10745, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44805,7 +44805,7 @@ circuit el2_ifu :
     node _T_10750 = and(_T_10747, _T_10749) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10751 = or(_T_10750, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10752 = bits(_T_10751, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10753 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10754 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10755 = eq(_T_10754, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44815,7 +44815,7 @@ circuit el2_ifu :
     node _T_10759 = and(_T_10756, _T_10758) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10760 = or(_T_10759, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10761 = bits(_T_10760, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10762 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10763 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10764 = eq(_T_10763, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44825,7 +44825,7 @@ circuit el2_ifu :
     node _T_10768 = and(_T_10765, _T_10767) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10769 = or(_T_10768, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10770 = bits(_T_10769, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10771 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10772 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10773 = eq(_T_10772, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44835,7 +44835,7 @@ circuit el2_ifu :
     node _T_10777 = and(_T_10774, _T_10776) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10778 = or(_T_10777, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10779 = bits(_T_10778, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10780 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10781 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10782 = eq(_T_10781, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44845,7 +44845,7 @@ circuit el2_ifu :
     node _T_10786 = and(_T_10783, _T_10785) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10787 = or(_T_10786, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10788 = bits(_T_10787, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10789 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10790 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10791 = eq(_T_10790, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44855,7 +44855,7 @@ circuit el2_ifu :
     node _T_10795 = and(_T_10792, _T_10794) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10796 = or(_T_10795, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10797 = bits(_T_10796, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10798 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10799 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10800 = eq(_T_10799, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44865,7 +44865,7 @@ circuit el2_ifu :
     node _T_10804 = and(_T_10801, _T_10803) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10805 = or(_T_10804, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10806 = bits(_T_10805, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10807 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10808 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10809 = eq(_T_10808, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44875,7 +44875,7 @@ circuit el2_ifu :
     node _T_10813 = and(_T_10810, _T_10812) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10814 = or(_T_10813, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10815 = bits(_T_10814, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10816 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10817 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10818 = eq(_T_10817, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44885,7 +44885,7 @@ circuit el2_ifu :
     node _T_10822 = and(_T_10819, _T_10821) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10823 = or(_T_10822, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10824 = bits(_T_10823, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10825 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10826 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10827 = eq(_T_10826, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44895,7 +44895,7 @@ circuit el2_ifu :
     node _T_10831 = and(_T_10828, _T_10830) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10832 = or(_T_10831, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10833 = bits(_T_10832, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10834 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10835 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10836 = eq(_T_10835, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44905,7 +44905,7 @@ circuit el2_ifu :
     node _T_10840 = and(_T_10837, _T_10839) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10841 = or(_T_10840, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10842 = bits(_T_10841, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10843 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10844 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10845 = eq(_T_10844, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44915,7 +44915,7 @@ circuit el2_ifu :
     node _T_10849 = and(_T_10846, _T_10848) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10850 = or(_T_10849, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10851 = bits(_T_10850, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10852 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10853 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10854 = eq(_T_10853, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44925,7 +44925,7 @@ circuit el2_ifu :
     node _T_10858 = and(_T_10855, _T_10857) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10859 = or(_T_10858, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10860 = bits(_T_10859, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10861 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10862 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10863 = eq(_T_10862, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44935,7 +44935,7 @@ circuit el2_ifu :
     node _T_10867 = and(_T_10864, _T_10866) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10868 = or(_T_10867, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10869 = bits(_T_10868, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10870 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10871 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10872 = eq(_T_10871, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44945,7 +44945,7 @@ circuit el2_ifu :
     node _T_10876 = and(_T_10873, _T_10875) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10877 = or(_T_10876, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10878 = bits(_T_10877, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10879 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10880 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10881 = eq(_T_10880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44955,7 +44955,7 @@ circuit el2_ifu :
     node _T_10885 = and(_T_10882, _T_10884) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10886 = or(_T_10885, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10887 = bits(_T_10886, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10888 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10889 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10890 = eq(_T_10889, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44965,7 +44965,7 @@ circuit el2_ifu :
     node _T_10894 = and(_T_10891, _T_10893) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10895 = or(_T_10894, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10896 = bits(_T_10895, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10897 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10898 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10899 = eq(_T_10898, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44975,7 +44975,7 @@ circuit el2_ifu :
     node _T_10903 = and(_T_10900, _T_10902) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10904 = or(_T_10903, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10905 = bits(_T_10904, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10906 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10907 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10908 = eq(_T_10907, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44985,7 +44985,7 @@ circuit el2_ifu :
     node _T_10912 = and(_T_10909, _T_10911) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10913 = or(_T_10912, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10914 = bits(_T_10913, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10915 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10916 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10917 = eq(_T_10916, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44995,7 +44995,7 @@ circuit el2_ifu :
     node _T_10921 = and(_T_10918, _T_10920) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10922 = or(_T_10921, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10923 = bits(_T_10922, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10924 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10925 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10926 = eq(_T_10925, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45005,7 +45005,7 @@ circuit el2_ifu :
     node _T_10930 = and(_T_10927, _T_10929) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10931 = or(_T_10930, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10932 = bits(_T_10931, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10933 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10934 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10935 = eq(_T_10934, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45015,7 +45015,7 @@ circuit el2_ifu :
     node _T_10939 = and(_T_10936, _T_10938) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10940 = or(_T_10939, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10941 = bits(_T_10940, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10942 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10943 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10944 = eq(_T_10943, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45025,7 +45025,7 @@ circuit el2_ifu :
     node _T_10948 = and(_T_10945, _T_10947) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10949 = or(_T_10948, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10950 = bits(_T_10949, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10951 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10952 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10953 = eq(_T_10952, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45035,7 +45035,7 @@ circuit el2_ifu :
     node _T_10957 = and(_T_10954, _T_10956) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10958 = or(_T_10957, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10959 = bits(_T_10958, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10960 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10961 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10962 = eq(_T_10961, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45045,7 +45045,7 @@ circuit el2_ifu :
     node _T_10966 = and(_T_10963, _T_10965) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10967 = or(_T_10966, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10968 = bits(_T_10967, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10969 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10970 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10971 = eq(_T_10970, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45055,7 +45055,7 @@ circuit el2_ifu :
     node _T_10975 = and(_T_10972, _T_10974) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10976 = or(_T_10975, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10977 = bits(_T_10976, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10978 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10979 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10980 = eq(_T_10979, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45065,7 +45065,7 @@ circuit el2_ifu :
     node _T_10984 = and(_T_10981, _T_10983) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10985 = or(_T_10984, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10986 = bits(_T_10985, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10987 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10988 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10989 = eq(_T_10988, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45075,7 +45075,7 @@ circuit el2_ifu :
     node _T_10993 = and(_T_10990, _T_10992) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10994 = or(_T_10993, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10995 = bits(_T_10994, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10996 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10997 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10998 = eq(_T_10997, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45085,7 +45085,7 @@ circuit el2_ifu :
     node _T_11002 = and(_T_10999, _T_11001) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11003 = or(_T_11002, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11004 = bits(_T_11003, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11005 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11006 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11007 = eq(_T_11006, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45095,7 +45095,7 @@ circuit el2_ifu :
     node _T_11011 = and(_T_11008, _T_11010) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11012 = or(_T_11011, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11013 = bits(_T_11012, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11014 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11015 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11016 = eq(_T_11015, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45105,7 +45105,7 @@ circuit el2_ifu :
     node _T_11020 = and(_T_11017, _T_11019) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11021 = or(_T_11020, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11022 = bits(_T_11021, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11023 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11024 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11025 = eq(_T_11024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45115,7 +45115,7 @@ circuit el2_ifu :
     node _T_11029 = and(_T_11026, _T_11028) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11030 = or(_T_11029, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11031 = bits(_T_11030, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11032 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11033 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11034 = eq(_T_11033, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45125,7 +45125,7 @@ circuit el2_ifu :
     node _T_11038 = and(_T_11035, _T_11037) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11039 = or(_T_11038, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11040 = bits(_T_11039, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11041 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11042 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11043 = eq(_T_11042, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45135,7 +45135,7 @@ circuit el2_ifu :
     node _T_11047 = and(_T_11044, _T_11046) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11048 = or(_T_11047, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11049 = bits(_T_11048, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11050 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11051 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11052 = eq(_T_11051, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45145,7 +45145,7 @@ circuit el2_ifu :
     node _T_11056 = and(_T_11053, _T_11055) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11057 = or(_T_11056, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11058 = bits(_T_11057, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11059 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11060 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11061 = eq(_T_11060, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45155,7 +45155,7 @@ circuit el2_ifu :
     node _T_11065 = and(_T_11062, _T_11064) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11066 = or(_T_11065, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11067 = bits(_T_11066, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11068 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11069 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11070 = eq(_T_11069, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45165,7 +45165,7 @@ circuit el2_ifu :
     node _T_11074 = and(_T_11071, _T_11073) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11075 = or(_T_11074, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11076 = bits(_T_11075, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11077 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11078 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11079 = eq(_T_11078, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45175,7 +45175,7 @@ circuit el2_ifu :
     node _T_11083 = and(_T_11080, _T_11082) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11084 = or(_T_11083, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11085 = bits(_T_11084, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11086 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11087 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11088 = eq(_T_11087, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45185,7 +45185,7 @@ circuit el2_ifu :
     node _T_11092 = and(_T_11089, _T_11091) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11093 = or(_T_11092, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11094 = bits(_T_11093, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11095 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11096 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11097 = eq(_T_11096, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45195,7 +45195,7 @@ circuit el2_ifu :
     node _T_11101 = and(_T_11098, _T_11100) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11102 = or(_T_11101, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11103 = bits(_T_11102, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11104 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11105 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11106 = eq(_T_11105, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45205,7 +45205,7 @@ circuit el2_ifu :
     node _T_11110 = and(_T_11107, _T_11109) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11111 = or(_T_11110, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11112 = bits(_T_11111, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11113 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11114 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11115 = eq(_T_11114, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45215,7 +45215,7 @@ circuit el2_ifu :
     node _T_11119 = and(_T_11116, _T_11118) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11120 = or(_T_11119, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11121 = bits(_T_11120, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11122 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11123 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11124 = eq(_T_11123, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45225,7 +45225,7 @@ circuit el2_ifu :
     node _T_11128 = and(_T_11125, _T_11127) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11129 = or(_T_11128, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11130 = bits(_T_11129, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11131 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11132 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11133 = eq(_T_11132, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45235,7 +45235,7 @@ circuit el2_ifu :
     node _T_11137 = and(_T_11134, _T_11136) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11138 = or(_T_11137, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11139 = bits(_T_11138, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11140 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11141 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11142 = eq(_T_11141, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45245,7 +45245,7 @@ circuit el2_ifu :
     node _T_11146 = and(_T_11143, _T_11145) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11147 = or(_T_11146, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11148 = bits(_T_11147, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11149 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11150 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11151 = eq(_T_11150, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45255,7 +45255,7 @@ circuit el2_ifu :
     node _T_11155 = and(_T_11152, _T_11154) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11156 = or(_T_11155, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11157 = bits(_T_11156, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11158 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11159 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11160 = eq(_T_11159, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45265,7 +45265,7 @@ circuit el2_ifu :
     node _T_11164 = and(_T_11161, _T_11163) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11165 = or(_T_11164, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11166 = bits(_T_11165, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     wire bht_bank_sel : UInt<1>[16][16][2] @[el2_ifu_bp_ctl.scala 449:26]
     node _T_11167 = bits(bht_wr_en0, 0, 0) @[el2_ifu_bp_ctl.scala 455:41]
     node _T_11168 = bits(mp_hashed, 3, 0) @[el2_ifu_bp_ctl.scala 455:60]
@@ -62407,7 +62407,7 @@ circuit el2_ifu :
   module el2_ifu_aln_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}
+    output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}
     
     io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19]
     io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18]
@@ -63516,62 +63516,62 @@ circuit el2_ifu :
     node _T_726 = and(_T_724, _T_725) @[el2_ifu_aln_ctl.scala 378:100]
     node _T_727 = or(_T_722, _T_726) @[el2_ifu_aln_ctl.scala 378:75]
     io.i0_brp.valid <= _T_727 @[el2_ifu_aln_ctl.scala 378:19]
-    node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:39]
-    node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:29]
-    node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:65]
-    node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:55]
-    node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:44]
-    io.i0_brp.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:17]
+    node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:44]
+    node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:34]
+    node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:70]
+    node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:60]
+    node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:49]
+    io.i0_brp.bits.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:22]
     node _T_733 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 382:39]
     node _T_734 = and(first2B, _T_733) @[el2_ifu_aln_ctl.scala 382:29]
     node _T_735 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 382:65]
     node _T_736 = and(first4B, _T_735) @[el2_ifu_aln_ctl.scala 382:55]
     node i0_brp_pc4 = or(_T_734, _T_736) @[el2_ifu_aln_ctl.scala 382:44]
-    node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:45]
-    node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:33]
-    node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:50]
-    node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:66]
-    node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:80]
-    node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:23]
-    io.i0_brp.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:17]
-    node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:46]
-    node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:34]
-    node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:74]
-    node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:62]
-    node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:51]
+    node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:50]
+    node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:38]
+    node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:55]
+    node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:71]
+    node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:85]
+    node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:28]
+    io.i0_brp.bits.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:22]
+    node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:51]
+    node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:39]
+    node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:79]
+    node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:67]
+    node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:56]
     node _T_748 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 387:26]
     node _T_749 = and(first2B, _T_748) @[el2_ifu_aln_ctl.scala 387:14]
     node _T_750 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 387:54]
     node _T_751 = and(first4B, _T_750) @[el2_ifu_aln_ctl.scala 387:42]
     node _T_752 = or(_T_749, _T_751) @[el2_ifu_aln_ctl.scala 387:31]
     node _T_753 = cat(_T_747, _T_752) @[Cat.scala 29:58]
-    io.i0_brp.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:18]
+    io.i0_brp.bits.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:23]
     node i0_ends_f1 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 389:28]
-    node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:39]
-    node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:27]
-    io.i0_brp.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:21]
-    node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:37]
-    node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:25]
-    io.i0_brp.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:19]
-    node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:51]
-    node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:41]
-    node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:67]
-    node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:55]
-    io.i0_brp.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:29]
-    node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:57]
-    node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:45]
-    node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:62]
-    node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:77]
-    node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:90]
-    node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:35]
-    io.i0_brp.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:29]
-    node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:42]
-    node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:56]
-    node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:89]
-    node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:87]
-    node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:101]
-    node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:68]
-    io.i0_brp.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:22]
+    node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:44]
+    node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:32]
+    io.i0_brp.bits.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:26]
+    node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:42]
+    node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:30]
+    io.i0_brp.bits.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:24]
+    node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:56]
+    node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:46]
+    node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:72]
+    node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:60]
+    io.i0_brp.bits.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:34]
+    node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:62]
+    node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:50]
+    node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:67]
+    node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:82]
+    node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:95]
+    node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:40]
+    io.i0_brp.bits.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:34]
+    node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:47]
+    node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:61]
+    node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:94]
+    node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:92]
+    node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:106]
+    node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:73]
+    io.i0_brp.bits.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:27]
     node _T_774 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 400:50]
     node _T_775 = or(first2B, _T_774) @[el2_ifu_aln_ctl.scala 400:38]
     node _T_776 = bits(_T_775, 0, 0) @[el2_ifu_aln_ctl.scala 400:55]
@@ -63910,7 +63910,7 @@ circuit el2_ifu :
   module el2_ifu : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>}
     
     inst mem_ctl_ch of el2_ifu_mem_ctl @[el2_ifu.scala 146:26]
     mem_ctl_ch.clock <= clock
@@ -63965,11 +63965,11 @@ circuit el2_ifu :
     bp_ctl_ch.io.ic_hit_f <= mem_ctl_ch.io.ic_hit_f @[el2_ifu.scala 195:25]
     bp_ctl_ch.io.ifc_fetch_addr_f <= ifc_ctl_ch.io.ifc_fetch_addr_f @[el2_ifu.scala 196:33]
     bp_ctl_ch.io.ifc_fetch_req_f <= ifc_ctl_ch.io.ifc_fetch_req_f @[el2_ifu.scala 197:32]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.middle <= io.dec_tlu_br0_r_pkt.middle @[el2_ifu.scala 198:34]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.way <= io.dec_tlu_br0_r_pkt.way @[el2_ifu.scala 198:34]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_start_error <= io.dec_tlu_br0_r_pkt.br_start_error @[el2_ifu.scala 198:34]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_error <= io.dec_tlu_br0_r_pkt.br_error @[el2_ifu.scala 198:34]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.hist <= io.dec_tlu_br0_r_pkt.hist @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.middle <= io.dec_tlu_br0_r_pkt.bits.middle @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.way <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_start_error <= io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_error <= io.dec_tlu_br0_r_pkt.bits.br_error @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.hist <= io.dec_tlu_br0_r_pkt.bits.hist @[el2_ifu.scala 198:34]
     bp_ctl_ch.io.dec_tlu_br0_r_pkt.valid <= io.dec_tlu_br0_r_pkt.valid @[el2_ifu.scala 198:34]
     bp_ctl_ch.io.exu_i0_br_fghr_r <= io.exu_i0_br_fghr_r @[el2_ifu.scala 199:33]
     bp_ctl_ch.io.exu_i0_br_index_r <= io.exu_i0_br_index_r @[el2_ifu.scala 200:34]
@@ -64111,14 +64111,14 @@ circuit el2_ifu :
     io.ifu_i0_pc <= aln_ctl_ch.io.ifu_i0_pc @[el2_ifu.scala 327:16]
     io.ifu_i0_pc4 <= aln_ctl_ch.io.ifu_i0_pc4 @[el2_ifu.scala 328:17]
     io.ifu_miss_state_idle <= mem_ctl_ch.io.ifu_miss_state_idle @[el2_ifu.scala 329:26]
-    io.i0_brp.ret <= aln_ctl_ch.io.i0_brp.ret @[el2_ifu.scala 331:13]
-    io.i0_brp.way <= aln_ctl_ch.io.i0_brp.way @[el2_ifu.scala 331:13]
-    io.i0_brp.prett <= aln_ctl_ch.io.i0_brp.prett @[el2_ifu.scala 331:13]
-    io.i0_brp.bank <= aln_ctl_ch.io.i0_brp.bank @[el2_ifu.scala 331:13]
-    io.i0_brp.br_start_error <= aln_ctl_ch.io.i0_brp.br_start_error @[el2_ifu.scala 331:13]
-    io.i0_brp.br_error <= aln_ctl_ch.io.i0_brp.br_error @[el2_ifu.scala 331:13]
-    io.i0_brp.hist <= aln_ctl_ch.io.i0_brp.hist @[el2_ifu.scala 331:13]
-    io.i0_brp.toffset <= aln_ctl_ch.io.i0_brp.toffset @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.ret <= aln_ctl_ch.io.i0_brp.bits.ret @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.way <= aln_ctl_ch.io.i0_brp.bits.way @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.prett <= aln_ctl_ch.io.i0_brp.bits.prett @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.bank <= aln_ctl_ch.io.i0_brp.bits.bank @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.br_start_error <= aln_ctl_ch.io.i0_brp.bits.br_start_error @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.br_error <= aln_ctl_ch.io.i0_brp.bits.br_error @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.hist <= aln_ctl_ch.io.i0_brp.bits.hist @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.toffset <= aln_ctl_ch.io.i0_brp.bits.toffset @[el2_ifu.scala 331:13]
     io.i0_brp.valid <= aln_ctl_ch.io.i0_brp.valid @[el2_ifu.scala 331:13]
     io.ifu_i0_bp_index <= aln_ctl_ch.io.ifu_i0_bp_index @[el2_ifu.scala 332:22]
     io.ifu_i0_bp_fghr <= aln_ctl_ch.io.ifu_i0_bp_fghr @[el2_ifu.scala 333:21]
diff --git a/el2_ifu.v b/el2_ifu.v
index d149b538..21edbc0a 100644
--- a/el2_ifu.v
+++ b/el2_ifu.v
@@ -11814,11 +11814,11 @@ module el2_ifu_bp_ctl(
   input  [30:0] io_ifc_fetch_addr_f,
   input         io_ifc_fetch_req_f,
   input         io_dec_tlu_br0_r_pkt_valid,
-  input  [1:0]  io_dec_tlu_br0_r_pkt_hist,
-  input         io_dec_tlu_br0_r_pkt_br_error,
-  input         io_dec_tlu_br0_r_pkt_br_start_error,
-  input         io_dec_tlu_br0_r_pkt_way,
-  input         io_dec_tlu_br0_r_pkt_middle,
+  input  [1:0]  io_dec_tlu_br0_r_pkt_bits_hist,
+  input         io_dec_tlu_br0_r_pkt_bits_br_error,
+  input         io_dec_tlu_br0_r_pkt_bits_br_start_error,
+  input         io_dec_tlu_br0_r_pkt_bits_way,
+  input         io_dec_tlu_br0_r_pkt_bits_middle,
   input  [7:0]  io_exu_i0_br_fghr_r,
   input  [7:0]  io_exu_i0_br_index_r,
   input         io_dec_tlu_flush_lower_wb,
@@ -15115,7 +15115,7 @@ module el2_ifu_bp_ctl(
   wire  leak_one_f = _T_40 | _T_41; // @[el2_ifu_bp_ctl.scala 135:76]
   wire  _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 72:51]
   wire  exu_mp_valid = io_exu_mp_pkt_bits_misp & _T; // @[el2_ifu_bp_ctl.scala 72:49]
-  wire  dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_br_start_error | io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu_bp_ctl.scala 94:50]
+  wire  dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_bits_br_start_error | io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu_bp_ctl.scala 94:50]
   wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 191:47]
   wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 191:85]
   wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_bp_ctl.scala 102:51]
@@ -21046,12 +21046,12 @@ module el2_ifu_bp_ctl(
   wire  exu_mp_valid_write = exu_mp_valid & io_exu_mp_pkt_bits_ataken; // @[el2_ifu_bp_ctl.scala 397:41]
   wire  _T_539 = _T_175 & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 400:39]
   wire  _T_541 = _T_539 & _T_530; // @[el2_ifu_bp_ctl.scala 400:60]
-  wire  _T_542 = ~io_dec_tlu_br0_r_pkt_way; // @[el2_ifu_bp_ctl.scala 400:87]
+  wire  _T_542 = ~io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu_bp_ctl.scala 400:87]
   wire  _T_543 = _T_542 & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 400:104]
   wire  btb_wr_en_way0 = _T_541 | _T_543; // @[el2_ifu_bp_ctl.scala 400:83]
   wire  _T_544 = io_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 401:36]
   wire  _T_546 = _T_544 & _T_530; // @[el2_ifu_bp_ctl.scala 401:57]
-  wire  _T_547 = io_dec_tlu_br0_r_pkt_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98]
+  wire  _T_547 = io_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98]
   wire  btb_wr_en_way1 = _T_546 | _T_547; // @[el2_ifu_bp_ctl.scala 401:80]
   wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_i0_br_index_r : io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 404:24]
   wire  middle_of_bank = io_exu_mp_pkt_bits_pc4 ^ io_exu_mp_pkt_bits_boffset; // @[el2_ifu_bp_ctl.scala 405:35]
@@ -21066,8 +21066,8 @@ module el2_ifu_bp_ctl(
   wire [1:0] _T_558 = {middle_of_bank,_T_557}; // @[Cat.scala 29:58]
   wire [1:0] bht_wr_en0 = _T_556 & _T_558; // @[el2_ifu_bp_ctl.scala 408:84]
   wire [1:0] _T_560 = io_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire  _T_561 = ~io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu_bp_ctl.scala 409:75]
-  wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_middle,_T_561}; // @[Cat.scala 29:58]
+  wire  _T_561 = ~io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu_bp_ctl.scala 409:75]
+  wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_bits_middle,_T_561}; // @[Cat.scala 29:58]
   wire [1:0] bht_wr_en2 = _T_560 & _T_562; // @[el2_ifu_bp_ctl.scala 409:46]
   wire [9:0] _T_563 = {io_exu_mp_index,2'h0}; // @[Cat.scala 29:58]
   wire [7:0] mp_hashed = _T_563[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 196:35]
@@ -35094,7 +35094,7 @@ end // initial
     if (reset) begin
       dec_tlu_way_wb_f <= 1'h0;
     end else begin
-      dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_way;
+      dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_bits_way;
     end
   end
   always @(posedge rvclkhdr_266_io_l1clk or posedge reset) begin
@@ -36901,7 +36901,7 @@ end // initial
       bht_bank_rd_data_out_1_0 <= 2'h0;
     end else if (bht_bank_sel_1_0_0) begin
       if (_T_8869) begin
-        bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_0 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36912,7 +36912,7 @@ end // initial
       bht_bank_rd_data_out_1_1 <= 2'h0;
     end else if (bht_bank_sel_1_0_1) begin
       if (_T_8878) begin
-        bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_1 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36923,7 +36923,7 @@ end // initial
       bht_bank_rd_data_out_1_2 <= 2'h0;
     end else if (bht_bank_sel_1_0_2) begin
       if (_T_8887) begin
-        bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_2 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36934,7 +36934,7 @@ end // initial
       bht_bank_rd_data_out_1_3 <= 2'h0;
     end else if (bht_bank_sel_1_0_3) begin
       if (_T_8896) begin
-        bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_3 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36945,7 +36945,7 @@ end // initial
       bht_bank_rd_data_out_1_4 <= 2'h0;
     end else if (bht_bank_sel_1_0_4) begin
       if (_T_8905) begin
-        bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_4 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36956,7 +36956,7 @@ end // initial
       bht_bank_rd_data_out_1_5 <= 2'h0;
     end else if (bht_bank_sel_1_0_5) begin
       if (_T_8914) begin
-        bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_5 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36967,7 +36967,7 @@ end // initial
       bht_bank_rd_data_out_1_6 <= 2'h0;
     end else if (bht_bank_sel_1_0_6) begin
       if (_T_8923) begin
-        bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_6 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36978,7 +36978,7 @@ end // initial
       bht_bank_rd_data_out_1_7 <= 2'h0;
     end else if (bht_bank_sel_1_0_7) begin
       if (_T_8932) begin
-        bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_7 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36989,7 +36989,7 @@ end // initial
       bht_bank_rd_data_out_1_8 <= 2'h0;
     end else if (bht_bank_sel_1_0_8) begin
       if (_T_8941) begin
-        bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_8 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37000,7 +37000,7 @@ end // initial
       bht_bank_rd_data_out_1_9 <= 2'h0;
     end else if (bht_bank_sel_1_0_9) begin
       if (_T_8950) begin
-        bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_9 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37011,7 +37011,7 @@ end // initial
       bht_bank_rd_data_out_1_10 <= 2'h0;
     end else if (bht_bank_sel_1_0_10) begin
       if (_T_8959) begin
-        bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_10 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37022,7 +37022,7 @@ end // initial
       bht_bank_rd_data_out_1_11 <= 2'h0;
     end else if (bht_bank_sel_1_0_11) begin
       if (_T_8968) begin
-        bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_11 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37033,7 +37033,7 @@ end // initial
       bht_bank_rd_data_out_1_12 <= 2'h0;
     end else if (bht_bank_sel_1_0_12) begin
       if (_T_8977) begin
-        bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_12 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37044,7 +37044,7 @@ end // initial
       bht_bank_rd_data_out_1_13 <= 2'h0;
     end else if (bht_bank_sel_1_0_13) begin
       if (_T_8986) begin
-        bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_13 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37055,7 +37055,7 @@ end // initial
       bht_bank_rd_data_out_1_14 <= 2'h0;
     end else if (bht_bank_sel_1_0_14) begin
       if (_T_8995) begin
-        bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_14 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37066,7 +37066,7 @@ end // initial
       bht_bank_rd_data_out_1_15 <= 2'h0;
     end else if (bht_bank_sel_1_0_15) begin
       if (_T_9004) begin
-        bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_15 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37077,7 +37077,7 @@ end // initial
       bht_bank_rd_data_out_1_16 <= 2'h0;
     end else if (bht_bank_sel_1_1_0) begin
       if (_T_9013) begin
-        bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_16 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37088,7 +37088,7 @@ end // initial
       bht_bank_rd_data_out_1_17 <= 2'h0;
     end else if (bht_bank_sel_1_1_1) begin
       if (_T_9022) begin
-        bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_17 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37099,7 +37099,7 @@ end // initial
       bht_bank_rd_data_out_1_18 <= 2'h0;
     end else if (bht_bank_sel_1_1_2) begin
       if (_T_9031) begin
-        bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_18 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37110,7 +37110,7 @@ end // initial
       bht_bank_rd_data_out_1_19 <= 2'h0;
     end else if (bht_bank_sel_1_1_3) begin
       if (_T_9040) begin
-        bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_19 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37121,7 +37121,7 @@ end // initial
       bht_bank_rd_data_out_1_20 <= 2'h0;
     end else if (bht_bank_sel_1_1_4) begin
       if (_T_9049) begin
-        bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_20 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37132,7 +37132,7 @@ end // initial
       bht_bank_rd_data_out_1_21 <= 2'h0;
     end else if (bht_bank_sel_1_1_5) begin
       if (_T_9058) begin
-        bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_21 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37143,7 +37143,7 @@ end // initial
       bht_bank_rd_data_out_1_22 <= 2'h0;
     end else if (bht_bank_sel_1_1_6) begin
       if (_T_9067) begin
-        bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_22 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37154,7 +37154,7 @@ end // initial
       bht_bank_rd_data_out_1_23 <= 2'h0;
     end else if (bht_bank_sel_1_1_7) begin
       if (_T_9076) begin
-        bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_23 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37165,7 +37165,7 @@ end // initial
       bht_bank_rd_data_out_1_24 <= 2'h0;
     end else if (bht_bank_sel_1_1_8) begin
       if (_T_9085) begin
-        bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_24 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37176,7 +37176,7 @@ end // initial
       bht_bank_rd_data_out_1_25 <= 2'h0;
     end else if (bht_bank_sel_1_1_9) begin
       if (_T_9094) begin
-        bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_25 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37187,7 +37187,7 @@ end // initial
       bht_bank_rd_data_out_1_26 <= 2'h0;
     end else if (bht_bank_sel_1_1_10) begin
       if (_T_9103) begin
-        bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_26 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37198,7 +37198,7 @@ end // initial
       bht_bank_rd_data_out_1_27 <= 2'h0;
     end else if (bht_bank_sel_1_1_11) begin
       if (_T_9112) begin
-        bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_27 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37209,7 +37209,7 @@ end // initial
       bht_bank_rd_data_out_1_28 <= 2'h0;
     end else if (bht_bank_sel_1_1_12) begin
       if (_T_9121) begin
-        bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_28 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37220,7 +37220,7 @@ end // initial
       bht_bank_rd_data_out_1_29 <= 2'h0;
     end else if (bht_bank_sel_1_1_13) begin
       if (_T_9130) begin
-        bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_29 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37231,7 +37231,7 @@ end // initial
       bht_bank_rd_data_out_1_30 <= 2'h0;
     end else if (bht_bank_sel_1_1_14) begin
       if (_T_9139) begin
-        bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_30 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37242,7 +37242,7 @@ end // initial
       bht_bank_rd_data_out_1_31 <= 2'h0;
     end else if (bht_bank_sel_1_1_15) begin
       if (_T_9148) begin
-        bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_31 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37253,7 +37253,7 @@ end // initial
       bht_bank_rd_data_out_1_32 <= 2'h0;
     end else if (bht_bank_sel_1_2_0) begin
       if (_T_9157) begin
-        bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_32 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37264,7 +37264,7 @@ end // initial
       bht_bank_rd_data_out_1_33 <= 2'h0;
     end else if (bht_bank_sel_1_2_1) begin
       if (_T_9166) begin
-        bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_33 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37275,7 +37275,7 @@ end // initial
       bht_bank_rd_data_out_1_34 <= 2'h0;
     end else if (bht_bank_sel_1_2_2) begin
       if (_T_9175) begin
-        bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_34 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37286,7 +37286,7 @@ end // initial
       bht_bank_rd_data_out_1_35 <= 2'h0;
     end else if (bht_bank_sel_1_2_3) begin
       if (_T_9184) begin
-        bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_35 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37297,7 +37297,7 @@ end // initial
       bht_bank_rd_data_out_1_36 <= 2'h0;
     end else if (bht_bank_sel_1_2_4) begin
       if (_T_9193) begin
-        bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_36 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37308,7 +37308,7 @@ end // initial
       bht_bank_rd_data_out_1_37 <= 2'h0;
     end else if (bht_bank_sel_1_2_5) begin
       if (_T_9202) begin
-        bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_37 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37319,7 +37319,7 @@ end // initial
       bht_bank_rd_data_out_1_38 <= 2'h0;
     end else if (bht_bank_sel_1_2_6) begin
       if (_T_9211) begin
-        bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_38 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37330,7 +37330,7 @@ end // initial
       bht_bank_rd_data_out_1_39 <= 2'h0;
     end else if (bht_bank_sel_1_2_7) begin
       if (_T_9220) begin
-        bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_39 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37341,7 +37341,7 @@ end // initial
       bht_bank_rd_data_out_1_40 <= 2'h0;
     end else if (bht_bank_sel_1_2_8) begin
       if (_T_9229) begin
-        bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_40 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37352,7 +37352,7 @@ end // initial
       bht_bank_rd_data_out_1_41 <= 2'h0;
     end else if (bht_bank_sel_1_2_9) begin
       if (_T_9238) begin
-        bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_41 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37363,7 +37363,7 @@ end // initial
       bht_bank_rd_data_out_1_42 <= 2'h0;
     end else if (bht_bank_sel_1_2_10) begin
       if (_T_9247) begin
-        bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_42 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37374,7 +37374,7 @@ end // initial
       bht_bank_rd_data_out_1_43 <= 2'h0;
     end else if (bht_bank_sel_1_2_11) begin
       if (_T_9256) begin
-        bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_43 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37385,7 +37385,7 @@ end // initial
       bht_bank_rd_data_out_1_44 <= 2'h0;
     end else if (bht_bank_sel_1_2_12) begin
       if (_T_9265) begin
-        bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_44 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37396,7 +37396,7 @@ end // initial
       bht_bank_rd_data_out_1_45 <= 2'h0;
     end else if (bht_bank_sel_1_2_13) begin
       if (_T_9274) begin
-        bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_45 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37407,7 +37407,7 @@ end // initial
       bht_bank_rd_data_out_1_46 <= 2'h0;
     end else if (bht_bank_sel_1_2_14) begin
       if (_T_9283) begin
-        bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_46 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37418,7 +37418,7 @@ end // initial
       bht_bank_rd_data_out_1_47 <= 2'h0;
     end else if (bht_bank_sel_1_2_15) begin
       if (_T_9292) begin
-        bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_47 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37429,7 +37429,7 @@ end // initial
       bht_bank_rd_data_out_1_48 <= 2'h0;
     end else if (bht_bank_sel_1_3_0) begin
       if (_T_9301) begin
-        bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_48 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37440,7 +37440,7 @@ end // initial
       bht_bank_rd_data_out_1_49 <= 2'h0;
     end else if (bht_bank_sel_1_3_1) begin
       if (_T_9310) begin
-        bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_49 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37451,7 +37451,7 @@ end // initial
       bht_bank_rd_data_out_1_50 <= 2'h0;
     end else if (bht_bank_sel_1_3_2) begin
       if (_T_9319) begin
-        bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_50 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37462,7 +37462,7 @@ end // initial
       bht_bank_rd_data_out_1_51 <= 2'h0;
     end else if (bht_bank_sel_1_3_3) begin
       if (_T_9328) begin
-        bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_51 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37473,7 +37473,7 @@ end // initial
       bht_bank_rd_data_out_1_52 <= 2'h0;
     end else if (bht_bank_sel_1_3_4) begin
       if (_T_9337) begin
-        bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_52 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37484,7 +37484,7 @@ end // initial
       bht_bank_rd_data_out_1_53 <= 2'h0;
     end else if (bht_bank_sel_1_3_5) begin
       if (_T_9346) begin
-        bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_53 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37495,7 +37495,7 @@ end // initial
       bht_bank_rd_data_out_1_54 <= 2'h0;
     end else if (bht_bank_sel_1_3_6) begin
       if (_T_9355) begin
-        bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_54 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37506,7 +37506,7 @@ end // initial
       bht_bank_rd_data_out_1_55 <= 2'h0;
     end else if (bht_bank_sel_1_3_7) begin
       if (_T_9364) begin
-        bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_55 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37517,7 +37517,7 @@ end // initial
       bht_bank_rd_data_out_1_56 <= 2'h0;
     end else if (bht_bank_sel_1_3_8) begin
       if (_T_9373) begin
-        bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_56 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37528,7 +37528,7 @@ end // initial
       bht_bank_rd_data_out_1_57 <= 2'h0;
     end else if (bht_bank_sel_1_3_9) begin
       if (_T_9382) begin
-        bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_57 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37539,7 +37539,7 @@ end // initial
       bht_bank_rd_data_out_1_58 <= 2'h0;
     end else if (bht_bank_sel_1_3_10) begin
       if (_T_9391) begin
-        bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_58 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37550,7 +37550,7 @@ end // initial
       bht_bank_rd_data_out_1_59 <= 2'h0;
     end else if (bht_bank_sel_1_3_11) begin
       if (_T_9400) begin
-        bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_59 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37561,7 +37561,7 @@ end // initial
       bht_bank_rd_data_out_1_60 <= 2'h0;
     end else if (bht_bank_sel_1_3_12) begin
       if (_T_9409) begin
-        bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_60 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37572,7 +37572,7 @@ end // initial
       bht_bank_rd_data_out_1_61 <= 2'h0;
     end else if (bht_bank_sel_1_3_13) begin
       if (_T_9418) begin
-        bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_61 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37583,7 +37583,7 @@ end // initial
       bht_bank_rd_data_out_1_62 <= 2'h0;
     end else if (bht_bank_sel_1_3_14) begin
       if (_T_9427) begin
-        bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_62 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37594,7 +37594,7 @@ end // initial
       bht_bank_rd_data_out_1_63 <= 2'h0;
     end else if (bht_bank_sel_1_3_15) begin
       if (_T_9436) begin
-        bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_63 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37605,7 +37605,7 @@ end // initial
       bht_bank_rd_data_out_1_64 <= 2'h0;
     end else if (bht_bank_sel_1_4_0) begin
       if (_T_9445) begin
-        bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_64 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37616,7 +37616,7 @@ end // initial
       bht_bank_rd_data_out_1_65 <= 2'h0;
     end else if (bht_bank_sel_1_4_1) begin
       if (_T_9454) begin
-        bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_65 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37627,7 +37627,7 @@ end // initial
       bht_bank_rd_data_out_1_66 <= 2'h0;
     end else if (bht_bank_sel_1_4_2) begin
       if (_T_9463) begin
-        bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_66 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37638,7 +37638,7 @@ end // initial
       bht_bank_rd_data_out_1_67 <= 2'h0;
     end else if (bht_bank_sel_1_4_3) begin
       if (_T_9472) begin
-        bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_67 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37649,7 +37649,7 @@ end // initial
       bht_bank_rd_data_out_1_68 <= 2'h0;
     end else if (bht_bank_sel_1_4_4) begin
       if (_T_9481) begin
-        bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_68 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37660,7 +37660,7 @@ end // initial
       bht_bank_rd_data_out_1_69 <= 2'h0;
     end else if (bht_bank_sel_1_4_5) begin
       if (_T_9490) begin
-        bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_69 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37671,7 +37671,7 @@ end // initial
       bht_bank_rd_data_out_1_70 <= 2'h0;
     end else if (bht_bank_sel_1_4_6) begin
       if (_T_9499) begin
-        bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_70 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37682,7 +37682,7 @@ end // initial
       bht_bank_rd_data_out_1_71 <= 2'h0;
     end else if (bht_bank_sel_1_4_7) begin
       if (_T_9508) begin
-        bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_71 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37693,7 +37693,7 @@ end // initial
       bht_bank_rd_data_out_1_72 <= 2'h0;
     end else if (bht_bank_sel_1_4_8) begin
       if (_T_9517) begin
-        bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_72 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37704,7 +37704,7 @@ end // initial
       bht_bank_rd_data_out_1_73 <= 2'h0;
     end else if (bht_bank_sel_1_4_9) begin
       if (_T_9526) begin
-        bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_73 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37715,7 +37715,7 @@ end // initial
       bht_bank_rd_data_out_1_74 <= 2'h0;
     end else if (bht_bank_sel_1_4_10) begin
       if (_T_9535) begin
-        bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_74 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37726,7 +37726,7 @@ end // initial
       bht_bank_rd_data_out_1_75 <= 2'h0;
     end else if (bht_bank_sel_1_4_11) begin
       if (_T_9544) begin
-        bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_75 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37737,7 +37737,7 @@ end // initial
       bht_bank_rd_data_out_1_76 <= 2'h0;
     end else if (bht_bank_sel_1_4_12) begin
       if (_T_9553) begin
-        bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_76 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37748,7 +37748,7 @@ end // initial
       bht_bank_rd_data_out_1_77 <= 2'h0;
     end else if (bht_bank_sel_1_4_13) begin
       if (_T_9562) begin
-        bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_77 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37759,7 +37759,7 @@ end // initial
       bht_bank_rd_data_out_1_78 <= 2'h0;
     end else if (bht_bank_sel_1_4_14) begin
       if (_T_9571) begin
-        bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_78 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37770,7 +37770,7 @@ end // initial
       bht_bank_rd_data_out_1_79 <= 2'h0;
     end else if (bht_bank_sel_1_4_15) begin
       if (_T_9580) begin
-        bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_79 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37781,7 +37781,7 @@ end // initial
       bht_bank_rd_data_out_1_80 <= 2'h0;
     end else if (bht_bank_sel_1_5_0) begin
       if (_T_9589) begin
-        bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_80 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37792,7 +37792,7 @@ end // initial
       bht_bank_rd_data_out_1_81 <= 2'h0;
     end else if (bht_bank_sel_1_5_1) begin
       if (_T_9598) begin
-        bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_81 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37803,7 +37803,7 @@ end // initial
       bht_bank_rd_data_out_1_82 <= 2'h0;
     end else if (bht_bank_sel_1_5_2) begin
       if (_T_9607) begin
-        bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_82 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37814,7 +37814,7 @@ end // initial
       bht_bank_rd_data_out_1_83 <= 2'h0;
     end else if (bht_bank_sel_1_5_3) begin
       if (_T_9616) begin
-        bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_83 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37825,7 +37825,7 @@ end // initial
       bht_bank_rd_data_out_1_84 <= 2'h0;
     end else if (bht_bank_sel_1_5_4) begin
       if (_T_9625) begin
-        bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_84 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37836,7 +37836,7 @@ end // initial
       bht_bank_rd_data_out_1_85 <= 2'h0;
     end else if (bht_bank_sel_1_5_5) begin
       if (_T_9634) begin
-        bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_85 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37847,7 +37847,7 @@ end // initial
       bht_bank_rd_data_out_1_86 <= 2'h0;
     end else if (bht_bank_sel_1_5_6) begin
       if (_T_9643) begin
-        bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_86 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37858,7 +37858,7 @@ end // initial
       bht_bank_rd_data_out_1_87 <= 2'h0;
     end else if (bht_bank_sel_1_5_7) begin
       if (_T_9652) begin
-        bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_87 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37869,7 +37869,7 @@ end // initial
       bht_bank_rd_data_out_1_88 <= 2'h0;
     end else if (bht_bank_sel_1_5_8) begin
       if (_T_9661) begin
-        bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_88 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37880,7 +37880,7 @@ end // initial
       bht_bank_rd_data_out_1_89 <= 2'h0;
     end else if (bht_bank_sel_1_5_9) begin
       if (_T_9670) begin
-        bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_89 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37891,7 +37891,7 @@ end // initial
       bht_bank_rd_data_out_1_90 <= 2'h0;
     end else if (bht_bank_sel_1_5_10) begin
       if (_T_9679) begin
-        bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_90 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37902,7 +37902,7 @@ end // initial
       bht_bank_rd_data_out_1_91 <= 2'h0;
     end else if (bht_bank_sel_1_5_11) begin
       if (_T_9688) begin
-        bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_91 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37913,7 +37913,7 @@ end // initial
       bht_bank_rd_data_out_1_92 <= 2'h0;
     end else if (bht_bank_sel_1_5_12) begin
       if (_T_9697) begin
-        bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_92 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37924,7 +37924,7 @@ end // initial
       bht_bank_rd_data_out_1_93 <= 2'h0;
     end else if (bht_bank_sel_1_5_13) begin
       if (_T_9706) begin
-        bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_93 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37935,7 +37935,7 @@ end // initial
       bht_bank_rd_data_out_1_94 <= 2'h0;
     end else if (bht_bank_sel_1_5_14) begin
       if (_T_9715) begin
-        bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_94 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37946,7 +37946,7 @@ end // initial
       bht_bank_rd_data_out_1_95 <= 2'h0;
     end else if (bht_bank_sel_1_5_15) begin
       if (_T_9724) begin
-        bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_95 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37957,7 +37957,7 @@ end // initial
       bht_bank_rd_data_out_1_96 <= 2'h0;
     end else if (bht_bank_sel_1_6_0) begin
       if (_T_9733) begin
-        bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_96 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37968,7 +37968,7 @@ end // initial
       bht_bank_rd_data_out_1_97 <= 2'h0;
     end else if (bht_bank_sel_1_6_1) begin
       if (_T_9742) begin
-        bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_97 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37979,7 +37979,7 @@ end // initial
       bht_bank_rd_data_out_1_98 <= 2'h0;
     end else if (bht_bank_sel_1_6_2) begin
       if (_T_9751) begin
-        bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_98 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37990,7 +37990,7 @@ end // initial
       bht_bank_rd_data_out_1_99 <= 2'h0;
     end else if (bht_bank_sel_1_6_3) begin
       if (_T_9760) begin
-        bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_99 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38001,7 +38001,7 @@ end // initial
       bht_bank_rd_data_out_1_100 <= 2'h0;
     end else if (bht_bank_sel_1_6_4) begin
       if (_T_9769) begin
-        bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_100 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38012,7 +38012,7 @@ end // initial
       bht_bank_rd_data_out_1_101 <= 2'h0;
     end else if (bht_bank_sel_1_6_5) begin
       if (_T_9778) begin
-        bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_101 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38023,7 +38023,7 @@ end // initial
       bht_bank_rd_data_out_1_102 <= 2'h0;
     end else if (bht_bank_sel_1_6_6) begin
       if (_T_9787) begin
-        bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_102 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38034,7 +38034,7 @@ end // initial
       bht_bank_rd_data_out_1_103 <= 2'h0;
     end else if (bht_bank_sel_1_6_7) begin
       if (_T_9796) begin
-        bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_103 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38045,7 +38045,7 @@ end // initial
       bht_bank_rd_data_out_1_104 <= 2'h0;
     end else if (bht_bank_sel_1_6_8) begin
       if (_T_9805) begin
-        bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_104 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38056,7 +38056,7 @@ end // initial
       bht_bank_rd_data_out_1_105 <= 2'h0;
     end else if (bht_bank_sel_1_6_9) begin
       if (_T_9814) begin
-        bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_105 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38067,7 +38067,7 @@ end // initial
       bht_bank_rd_data_out_1_106 <= 2'h0;
     end else if (bht_bank_sel_1_6_10) begin
       if (_T_9823) begin
-        bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_106 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38078,7 +38078,7 @@ end // initial
       bht_bank_rd_data_out_1_107 <= 2'h0;
     end else if (bht_bank_sel_1_6_11) begin
       if (_T_9832) begin
-        bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_107 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38089,7 +38089,7 @@ end // initial
       bht_bank_rd_data_out_1_108 <= 2'h0;
     end else if (bht_bank_sel_1_6_12) begin
       if (_T_9841) begin
-        bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_108 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38100,7 +38100,7 @@ end // initial
       bht_bank_rd_data_out_1_109 <= 2'h0;
     end else if (bht_bank_sel_1_6_13) begin
       if (_T_9850) begin
-        bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_109 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38111,7 +38111,7 @@ end // initial
       bht_bank_rd_data_out_1_110 <= 2'h0;
     end else if (bht_bank_sel_1_6_14) begin
       if (_T_9859) begin
-        bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_110 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38122,7 +38122,7 @@ end // initial
       bht_bank_rd_data_out_1_111 <= 2'h0;
     end else if (bht_bank_sel_1_6_15) begin
       if (_T_9868) begin
-        bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_111 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38133,7 +38133,7 @@ end // initial
       bht_bank_rd_data_out_1_112 <= 2'h0;
     end else if (bht_bank_sel_1_7_0) begin
       if (_T_9877) begin
-        bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_112 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38144,7 +38144,7 @@ end // initial
       bht_bank_rd_data_out_1_113 <= 2'h0;
     end else if (bht_bank_sel_1_7_1) begin
       if (_T_9886) begin
-        bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_113 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38155,7 +38155,7 @@ end // initial
       bht_bank_rd_data_out_1_114 <= 2'h0;
     end else if (bht_bank_sel_1_7_2) begin
       if (_T_9895) begin
-        bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_114 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38166,7 +38166,7 @@ end // initial
       bht_bank_rd_data_out_1_115 <= 2'h0;
     end else if (bht_bank_sel_1_7_3) begin
       if (_T_9904) begin
-        bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_115 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38177,7 +38177,7 @@ end // initial
       bht_bank_rd_data_out_1_116 <= 2'h0;
     end else if (bht_bank_sel_1_7_4) begin
       if (_T_9913) begin
-        bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_116 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38188,7 +38188,7 @@ end // initial
       bht_bank_rd_data_out_1_117 <= 2'h0;
     end else if (bht_bank_sel_1_7_5) begin
       if (_T_9922) begin
-        bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_117 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38199,7 +38199,7 @@ end // initial
       bht_bank_rd_data_out_1_118 <= 2'h0;
     end else if (bht_bank_sel_1_7_6) begin
       if (_T_9931) begin
-        bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_118 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38210,7 +38210,7 @@ end // initial
       bht_bank_rd_data_out_1_119 <= 2'h0;
     end else if (bht_bank_sel_1_7_7) begin
       if (_T_9940) begin
-        bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_119 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38221,7 +38221,7 @@ end // initial
       bht_bank_rd_data_out_1_120 <= 2'h0;
     end else if (bht_bank_sel_1_7_8) begin
       if (_T_9949) begin
-        bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_120 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38232,7 +38232,7 @@ end // initial
       bht_bank_rd_data_out_1_121 <= 2'h0;
     end else if (bht_bank_sel_1_7_9) begin
       if (_T_9958) begin
-        bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_121 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38243,7 +38243,7 @@ end // initial
       bht_bank_rd_data_out_1_122 <= 2'h0;
     end else if (bht_bank_sel_1_7_10) begin
       if (_T_9967) begin
-        bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_122 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38254,7 +38254,7 @@ end // initial
       bht_bank_rd_data_out_1_123 <= 2'h0;
     end else if (bht_bank_sel_1_7_11) begin
       if (_T_9976) begin
-        bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_123 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38265,7 +38265,7 @@ end // initial
       bht_bank_rd_data_out_1_124 <= 2'h0;
     end else if (bht_bank_sel_1_7_12) begin
       if (_T_9985) begin
-        bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_124 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38276,7 +38276,7 @@ end // initial
       bht_bank_rd_data_out_1_125 <= 2'h0;
     end else if (bht_bank_sel_1_7_13) begin
       if (_T_9994) begin
-        bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_125 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38287,7 +38287,7 @@ end // initial
       bht_bank_rd_data_out_1_126 <= 2'h0;
     end else if (bht_bank_sel_1_7_14) begin
       if (_T_10003) begin
-        bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_126 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38298,7 +38298,7 @@ end // initial
       bht_bank_rd_data_out_1_127 <= 2'h0;
     end else if (bht_bank_sel_1_7_15) begin
       if (_T_10012) begin
-        bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_127 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38309,7 +38309,7 @@ end // initial
       bht_bank_rd_data_out_1_128 <= 2'h0;
     end else if (bht_bank_sel_1_8_0) begin
       if (_T_10021) begin
-        bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_128 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38320,7 +38320,7 @@ end // initial
       bht_bank_rd_data_out_1_129 <= 2'h0;
     end else if (bht_bank_sel_1_8_1) begin
       if (_T_10030) begin
-        bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_129 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38331,7 +38331,7 @@ end // initial
       bht_bank_rd_data_out_1_130 <= 2'h0;
     end else if (bht_bank_sel_1_8_2) begin
       if (_T_10039) begin
-        bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_130 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38342,7 +38342,7 @@ end // initial
       bht_bank_rd_data_out_1_131 <= 2'h0;
     end else if (bht_bank_sel_1_8_3) begin
       if (_T_10048) begin
-        bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_131 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38353,7 +38353,7 @@ end // initial
       bht_bank_rd_data_out_1_132 <= 2'h0;
     end else if (bht_bank_sel_1_8_4) begin
       if (_T_10057) begin
-        bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_132 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38364,7 +38364,7 @@ end // initial
       bht_bank_rd_data_out_1_133 <= 2'h0;
     end else if (bht_bank_sel_1_8_5) begin
       if (_T_10066) begin
-        bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_133 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38375,7 +38375,7 @@ end // initial
       bht_bank_rd_data_out_1_134 <= 2'h0;
     end else if (bht_bank_sel_1_8_6) begin
       if (_T_10075) begin
-        bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_134 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38386,7 +38386,7 @@ end // initial
       bht_bank_rd_data_out_1_135 <= 2'h0;
     end else if (bht_bank_sel_1_8_7) begin
       if (_T_10084) begin
-        bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_135 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38397,7 +38397,7 @@ end // initial
       bht_bank_rd_data_out_1_136 <= 2'h0;
     end else if (bht_bank_sel_1_8_8) begin
       if (_T_10093) begin
-        bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_136 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38408,7 +38408,7 @@ end // initial
       bht_bank_rd_data_out_1_137 <= 2'h0;
     end else if (bht_bank_sel_1_8_9) begin
       if (_T_10102) begin
-        bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_137 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38419,7 +38419,7 @@ end // initial
       bht_bank_rd_data_out_1_138 <= 2'h0;
     end else if (bht_bank_sel_1_8_10) begin
       if (_T_10111) begin
-        bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_138 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38430,7 +38430,7 @@ end // initial
       bht_bank_rd_data_out_1_139 <= 2'h0;
     end else if (bht_bank_sel_1_8_11) begin
       if (_T_10120) begin
-        bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_139 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38441,7 +38441,7 @@ end // initial
       bht_bank_rd_data_out_1_140 <= 2'h0;
     end else if (bht_bank_sel_1_8_12) begin
       if (_T_10129) begin
-        bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_140 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38452,7 +38452,7 @@ end // initial
       bht_bank_rd_data_out_1_141 <= 2'h0;
     end else if (bht_bank_sel_1_8_13) begin
       if (_T_10138) begin
-        bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_141 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38463,7 +38463,7 @@ end // initial
       bht_bank_rd_data_out_1_142 <= 2'h0;
     end else if (bht_bank_sel_1_8_14) begin
       if (_T_10147) begin
-        bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_142 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38474,7 +38474,7 @@ end // initial
       bht_bank_rd_data_out_1_143 <= 2'h0;
     end else if (bht_bank_sel_1_8_15) begin
       if (_T_10156) begin
-        bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_143 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38485,7 +38485,7 @@ end // initial
       bht_bank_rd_data_out_1_144 <= 2'h0;
     end else if (bht_bank_sel_1_9_0) begin
       if (_T_10165) begin
-        bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_144 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38496,7 +38496,7 @@ end // initial
       bht_bank_rd_data_out_1_145 <= 2'h0;
     end else if (bht_bank_sel_1_9_1) begin
       if (_T_10174) begin
-        bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_145 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38507,7 +38507,7 @@ end // initial
       bht_bank_rd_data_out_1_146 <= 2'h0;
     end else if (bht_bank_sel_1_9_2) begin
       if (_T_10183) begin
-        bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_146 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38518,7 +38518,7 @@ end // initial
       bht_bank_rd_data_out_1_147 <= 2'h0;
     end else if (bht_bank_sel_1_9_3) begin
       if (_T_10192) begin
-        bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_147 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38529,7 +38529,7 @@ end // initial
       bht_bank_rd_data_out_1_148 <= 2'h0;
     end else if (bht_bank_sel_1_9_4) begin
       if (_T_10201) begin
-        bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_148 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38540,7 +38540,7 @@ end // initial
       bht_bank_rd_data_out_1_149 <= 2'h0;
     end else if (bht_bank_sel_1_9_5) begin
       if (_T_10210) begin
-        bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_149 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38551,7 +38551,7 @@ end // initial
       bht_bank_rd_data_out_1_150 <= 2'h0;
     end else if (bht_bank_sel_1_9_6) begin
       if (_T_10219) begin
-        bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_150 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38562,7 +38562,7 @@ end // initial
       bht_bank_rd_data_out_1_151 <= 2'h0;
     end else if (bht_bank_sel_1_9_7) begin
       if (_T_10228) begin
-        bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_151 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38573,7 +38573,7 @@ end // initial
       bht_bank_rd_data_out_1_152 <= 2'h0;
     end else if (bht_bank_sel_1_9_8) begin
       if (_T_10237) begin
-        bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_152 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38584,7 +38584,7 @@ end // initial
       bht_bank_rd_data_out_1_153 <= 2'h0;
     end else if (bht_bank_sel_1_9_9) begin
       if (_T_10246) begin
-        bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_153 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38595,7 +38595,7 @@ end // initial
       bht_bank_rd_data_out_1_154 <= 2'h0;
     end else if (bht_bank_sel_1_9_10) begin
       if (_T_10255) begin
-        bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_154 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38606,7 +38606,7 @@ end // initial
       bht_bank_rd_data_out_1_155 <= 2'h0;
     end else if (bht_bank_sel_1_9_11) begin
       if (_T_10264) begin
-        bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_155 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38617,7 +38617,7 @@ end // initial
       bht_bank_rd_data_out_1_156 <= 2'h0;
     end else if (bht_bank_sel_1_9_12) begin
       if (_T_10273) begin
-        bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_156 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38628,7 +38628,7 @@ end // initial
       bht_bank_rd_data_out_1_157 <= 2'h0;
     end else if (bht_bank_sel_1_9_13) begin
       if (_T_10282) begin
-        bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_157 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38639,7 +38639,7 @@ end // initial
       bht_bank_rd_data_out_1_158 <= 2'h0;
     end else if (bht_bank_sel_1_9_14) begin
       if (_T_10291) begin
-        bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_158 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38650,7 +38650,7 @@ end // initial
       bht_bank_rd_data_out_1_159 <= 2'h0;
     end else if (bht_bank_sel_1_9_15) begin
       if (_T_10300) begin
-        bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_159 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38661,7 +38661,7 @@ end // initial
       bht_bank_rd_data_out_1_160 <= 2'h0;
     end else if (bht_bank_sel_1_10_0) begin
       if (_T_10309) begin
-        bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_160 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38672,7 +38672,7 @@ end // initial
       bht_bank_rd_data_out_1_161 <= 2'h0;
     end else if (bht_bank_sel_1_10_1) begin
       if (_T_10318) begin
-        bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_161 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38683,7 +38683,7 @@ end // initial
       bht_bank_rd_data_out_1_162 <= 2'h0;
     end else if (bht_bank_sel_1_10_2) begin
       if (_T_10327) begin
-        bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_162 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38694,7 +38694,7 @@ end // initial
       bht_bank_rd_data_out_1_163 <= 2'h0;
     end else if (bht_bank_sel_1_10_3) begin
       if (_T_10336) begin
-        bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_163 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38705,7 +38705,7 @@ end // initial
       bht_bank_rd_data_out_1_164 <= 2'h0;
     end else if (bht_bank_sel_1_10_4) begin
       if (_T_10345) begin
-        bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_164 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38716,7 +38716,7 @@ end // initial
       bht_bank_rd_data_out_1_165 <= 2'h0;
     end else if (bht_bank_sel_1_10_5) begin
       if (_T_10354) begin
-        bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_165 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38727,7 +38727,7 @@ end // initial
       bht_bank_rd_data_out_1_166 <= 2'h0;
     end else if (bht_bank_sel_1_10_6) begin
       if (_T_10363) begin
-        bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_166 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38738,7 +38738,7 @@ end // initial
       bht_bank_rd_data_out_1_167 <= 2'h0;
     end else if (bht_bank_sel_1_10_7) begin
       if (_T_10372) begin
-        bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_167 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38749,7 +38749,7 @@ end // initial
       bht_bank_rd_data_out_1_168 <= 2'h0;
     end else if (bht_bank_sel_1_10_8) begin
       if (_T_10381) begin
-        bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_168 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38760,7 +38760,7 @@ end // initial
       bht_bank_rd_data_out_1_169 <= 2'h0;
     end else if (bht_bank_sel_1_10_9) begin
       if (_T_10390) begin
-        bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_169 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38771,7 +38771,7 @@ end // initial
       bht_bank_rd_data_out_1_170 <= 2'h0;
     end else if (bht_bank_sel_1_10_10) begin
       if (_T_10399) begin
-        bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_170 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38782,7 +38782,7 @@ end // initial
       bht_bank_rd_data_out_1_171 <= 2'h0;
     end else if (bht_bank_sel_1_10_11) begin
       if (_T_10408) begin
-        bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_171 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38793,7 +38793,7 @@ end // initial
       bht_bank_rd_data_out_1_172 <= 2'h0;
     end else if (bht_bank_sel_1_10_12) begin
       if (_T_10417) begin
-        bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_172 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38804,7 +38804,7 @@ end // initial
       bht_bank_rd_data_out_1_173 <= 2'h0;
     end else if (bht_bank_sel_1_10_13) begin
       if (_T_10426) begin
-        bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_173 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38815,7 +38815,7 @@ end // initial
       bht_bank_rd_data_out_1_174 <= 2'h0;
     end else if (bht_bank_sel_1_10_14) begin
       if (_T_10435) begin
-        bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_174 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38826,7 +38826,7 @@ end // initial
       bht_bank_rd_data_out_1_175 <= 2'h0;
     end else if (bht_bank_sel_1_10_15) begin
       if (_T_10444) begin
-        bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_175 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38837,7 +38837,7 @@ end // initial
       bht_bank_rd_data_out_1_176 <= 2'h0;
     end else if (bht_bank_sel_1_11_0) begin
       if (_T_10453) begin
-        bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_176 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38848,7 +38848,7 @@ end // initial
       bht_bank_rd_data_out_1_177 <= 2'h0;
     end else if (bht_bank_sel_1_11_1) begin
       if (_T_10462) begin
-        bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_177 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38859,7 +38859,7 @@ end // initial
       bht_bank_rd_data_out_1_178 <= 2'h0;
     end else if (bht_bank_sel_1_11_2) begin
       if (_T_10471) begin
-        bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_178 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38870,7 +38870,7 @@ end // initial
       bht_bank_rd_data_out_1_179 <= 2'h0;
     end else if (bht_bank_sel_1_11_3) begin
       if (_T_10480) begin
-        bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_179 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38881,7 +38881,7 @@ end // initial
       bht_bank_rd_data_out_1_180 <= 2'h0;
     end else if (bht_bank_sel_1_11_4) begin
       if (_T_10489) begin
-        bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_180 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38892,7 +38892,7 @@ end // initial
       bht_bank_rd_data_out_1_181 <= 2'h0;
     end else if (bht_bank_sel_1_11_5) begin
       if (_T_10498) begin
-        bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_181 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38903,7 +38903,7 @@ end // initial
       bht_bank_rd_data_out_1_182 <= 2'h0;
     end else if (bht_bank_sel_1_11_6) begin
       if (_T_10507) begin
-        bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_182 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38914,7 +38914,7 @@ end // initial
       bht_bank_rd_data_out_1_183 <= 2'h0;
     end else if (bht_bank_sel_1_11_7) begin
       if (_T_10516) begin
-        bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_183 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38925,7 +38925,7 @@ end // initial
       bht_bank_rd_data_out_1_184 <= 2'h0;
     end else if (bht_bank_sel_1_11_8) begin
       if (_T_10525) begin
-        bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_184 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38936,7 +38936,7 @@ end // initial
       bht_bank_rd_data_out_1_185 <= 2'h0;
     end else if (bht_bank_sel_1_11_9) begin
       if (_T_10534) begin
-        bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_185 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38947,7 +38947,7 @@ end // initial
       bht_bank_rd_data_out_1_186 <= 2'h0;
     end else if (bht_bank_sel_1_11_10) begin
       if (_T_10543) begin
-        bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_186 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38958,7 +38958,7 @@ end // initial
       bht_bank_rd_data_out_1_187 <= 2'h0;
     end else if (bht_bank_sel_1_11_11) begin
       if (_T_10552) begin
-        bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_187 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38969,7 +38969,7 @@ end // initial
       bht_bank_rd_data_out_1_188 <= 2'h0;
     end else if (bht_bank_sel_1_11_12) begin
       if (_T_10561) begin
-        bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_188 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38980,7 +38980,7 @@ end // initial
       bht_bank_rd_data_out_1_189 <= 2'h0;
     end else if (bht_bank_sel_1_11_13) begin
       if (_T_10570) begin
-        bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_189 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38991,7 +38991,7 @@ end // initial
       bht_bank_rd_data_out_1_190 <= 2'h0;
     end else if (bht_bank_sel_1_11_14) begin
       if (_T_10579) begin
-        bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_190 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39002,7 +39002,7 @@ end // initial
       bht_bank_rd_data_out_1_191 <= 2'h0;
     end else if (bht_bank_sel_1_11_15) begin
       if (_T_10588) begin
-        bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_191 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39013,7 +39013,7 @@ end // initial
       bht_bank_rd_data_out_1_192 <= 2'h0;
     end else if (bht_bank_sel_1_12_0) begin
       if (_T_10597) begin
-        bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_192 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39024,7 +39024,7 @@ end // initial
       bht_bank_rd_data_out_1_193 <= 2'h0;
     end else if (bht_bank_sel_1_12_1) begin
       if (_T_10606) begin
-        bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_193 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39035,7 +39035,7 @@ end // initial
       bht_bank_rd_data_out_1_194 <= 2'h0;
     end else if (bht_bank_sel_1_12_2) begin
       if (_T_10615) begin
-        bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_194 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39046,7 +39046,7 @@ end // initial
       bht_bank_rd_data_out_1_195 <= 2'h0;
     end else if (bht_bank_sel_1_12_3) begin
       if (_T_10624) begin
-        bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_195 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39057,7 +39057,7 @@ end // initial
       bht_bank_rd_data_out_1_196 <= 2'h0;
     end else if (bht_bank_sel_1_12_4) begin
       if (_T_10633) begin
-        bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_196 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39068,7 +39068,7 @@ end // initial
       bht_bank_rd_data_out_1_197 <= 2'h0;
     end else if (bht_bank_sel_1_12_5) begin
       if (_T_10642) begin
-        bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_197 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39079,7 +39079,7 @@ end // initial
       bht_bank_rd_data_out_1_198 <= 2'h0;
     end else if (bht_bank_sel_1_12_6) begin
       if (_T_10651) begin
-        bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_198 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39090,7 +39090,7 @@ end // initial
       bht_bank_rd_data_out_1_199 <= 2'h0;
     end else if (bht_bank_sel_1_12_7) begin
       if (_T_10660) begin
-        bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_199 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39101,7 +39101,7 @@ end // initial
       bht_bank_rd_data_out_1_200 <= 2'h0;
     end else if (bht_bank_sel_1_12_8) begin
       if (_T_10669) begin
-        bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_200 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39112,7 +39112,7 @@ end // initial
       bht_bank_rd_data_out_1_201 <= 2'h0;
     end else if (bht_bank_sel_1_12_9) begin
       if (_T_10678) begin
-        bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_201 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39123,7 +39123,7 @@ end // initial
       bht_bank_rd_data_out_1_202 <= 2'h0;
     end else if (bht_bank_sel_1_12_10) begin
       if (_T_10687) begin
-        bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_202 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39134,7 +39134,7 @@ end // initial
       bht_bank_rd_data_out_1_203 <= 2'h0;
     end else if (bht_bank_sel_1_12_11) begin
       if (_T_10696) begin
-        bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_203 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39145,7 +39145,7 @@ end // initial
       bht_bank_rd_data_out_1_204 <= 2'h0;
     end else if (bht_bank_sel_1_12_12) begin
       if (_T_10705) begin
-        bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_204 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39156,7 +39156,7 @@ end // initial
       bht_bank_rd_data_out_1_205 <= 2'h0;
     end else if (bht_bank_sel_1_12_13) begin
       if (_T_10714) begin
-        bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_205 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39167,7 +39167,7 @@ end // initial
       bht_bank_rd_data_out_1_206 <= 2'h0;
     end else if (bht_bank_sel_1_12_14) begin
       if (_T_10723) begin
-        bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_206 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39178,7 +39178,7 @@ end // initial
       bht_bank_rd_data_out_1_207 <= 2'h0;
     end else if (bht_bank_sel_1_12_15) begin
       if (_T_10732) begin
-        bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_207 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39189,7 +39189,7 @@ end // initial
       bht_bank_rd_data_out_1_208 <= 2'h0;
     end else if (bht_bank_sel_1_13_0) begin
       if (_T_10741) begin
-        bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_208 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39200,7 +39200,7 @@ end // initial
       bht_bank_rd_data_out_1_209 <= 2'h0;
     end else if (bht_bank_sel_1_13_1) begin
       if (_T_10750) begin
-        bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_209 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39211,7 +39211,7 @@ end // initial
       bht_bank_rd_data_out_1_210 <= 2'h0;
     end else if (bht_bank_sel_1_13_2) begin
       if (_T_10759) begin
-        bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_210 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39222,7 +39222,7 @@ end // initial
       bht_bank_rd_data_out_1_211 <= 2'h0;
     end else if (bht_bank_sel_1_13_3) begin
       if (_T_10768) begin
-        bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_211 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39233,7 +39233,7 @@ end // initial
       bht_bank_rd_data_out_1_212 <= 2'h0;
     end else if (bht_bank_sel_1_13_4) begin
       if (_T_10777) begin
-        bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_212 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39244,7 +39244,7 @@ end // initial
       bht_bank_rd_data_out_1_213 <= 2'h0;
     end else if (bht_bank_sel_1_13_5) begin
       if (_T_10786) begin
-        bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_213 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39255,7 +39255,7 @@ end // initial
       bht_bank_rd_data_out_1_214 <= 2'h0;
     end else if (bht_bank_sel_1_13_6) begin
       if (_T_10795) begin
-        bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_214 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39266,7 +39266,7 @@ end // initial
       bht_bank_rd_data_out_1_215 <= 2'h0;
     end else if (bht_bank_sel_1_13_7) begin
       if (_T_10804) begin
-        bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_215 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39277,7 +39277,7 @@ end // initial
       bht_bank_rd_data_out_1_216 <= 2'h0;
     end else if (bht_bank_sel_1_13_8) begin
       if (_T_10813) begin
-        bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_216 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39288,7 +39288,7 @@ end // initial
       bht_bank_rd_data_out_1_217 <= 2'h0;
     end else if (bht_bank_sel_1_13_9) begin
       if (_T_10822) begin
-        bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_217 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39299,7 +39299,7 @@ end // initial
       bht_bank_rd_data_out_1_218 <= 2'h0;
     end else if (bht_bank_sel_1_13_10) begin
       if (_T_10831) begin
-        bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_218 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39310,7 +39310,7 @@ end // initial
       bht_bank_rd_data_out_1_219 <= 2'h0;
     end else if (bht_bank_sel_1_13_11) begin
       if (_T_10840) begin
-        bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_219 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39321,7 +39321,7 @@ end // initial
       bht_bank_rd_data_out_1_220 <= 2'h0;
     end else if (bht_bank_sel_1_13_12) begin
       if (_T_10849) begin
-        bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_220 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39332,7 +39332,7 @@ end // initial
       bht_bank_rd_data_out_1_221 <= 2'h0;
     end else if (bht_bank_sel_1_13_13) begin
       if (_T_10858) begin
-        bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_221 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39343,7 +39343,7 @@ end // initial
       bht_bank_rd_data_out_1_222 <= 2'h0;
     end else if (bht_bank_sel_1_13_14) begin
       if (_T_10867) begin
-        bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_222 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39354,7 +39354,7 @@ end // initial
       bht_bank_rd_data_out_1_223 <= 2'h0;
     end else if (bht_bank_sel_1_13_15) begin
       if (_T_10876) begin
-        bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_223 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39365,7 +39365,7 @@ end // initial
       bht_bank_rd_data_out_1_224 <= 2'h0;
     end else if (bht_bank_sel_1_14_0) begin
       if (_T_10885) begin
-        bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_224 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39376,7 +39376,7 @@ end // initial
       bht_bank_rd_data_out_1_225 <= 2'h0;
     end else if (bht_bank_sel_1_14_1) begin
       if (_T_10894) begin
-        bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_225 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39387,7 +39387,7 @@ end // initial
       bht_bank_rd_data_out_1_226 <= 2'h0;
     end else if (bht_bank_sel_1_14_2) begin
       if (_T_10903) begin
-        bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_226 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39398,7 +39398,7 @@ end // initial
       bht_bank_rd_data_out_1_227 <= 2'h0;
     end else if (bht_bank_sel_1_14_3) begin
       if (_T_10912) begin
-        bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_227 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39409,7 +39409,7 @@ end // initial
       bht_bank_rd_data_out_1_228 <= 2'h0;
     end else if (bht_bank_sel_1_14_4) begin
       if (_T_10921) begin
-        bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_228 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39420,7 +39420,7 @@ end // initial
       bht_bank_rd_data_out_1_229 <= 2'h0;
     end else if (bht_bank_sel_1_14_5) begin
       if (_T_10930) begin
-        bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_229 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39431,7 +39431,7 @@ end // initial
       bht_bank_rd_data_out_1_230 <= 2'h0;
     end else if (bht_bank_sel_1_14_6) begin
       if (_T_10939) begin
-        bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_230 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39442,7 +39442,7 @@ end // initial
       bht_bank_rd_data_out_1_231 <= 2'h0;
     end else if (bht_bank_sel_1_14_7) begin
       if (_T_10948) begin
-        bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_231 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39453,7 +39453,7 @@ end // initial
       bht_bank_rd_data_out_1_232 <= 2'h0;
     end else if (bht_bank_sel_1_14_8) begin
       if (_T_10957) begin
-        bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_232 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39464,7 +39464,7 @@ end // initial
       bht_bank_rd_data_out_1_233 <= 2'h0;
     end else if (bht_bank_sel_1_14_9) begin
       if (_T_10966) begin
-        bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_233 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39475,7 +39475,7 @@ end // initial
       bht_bank_rd_data_out_1_234 <= 2'h0;
     end else if (bht_bank_sel_1_14_10) begin
       if (_T_10975) begin
-        bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_234 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39486,7 +39486,7 @@ end // initial
       bht_bank_rd_data_out_1_235 <= 2'h0;
     end else if (bht_bank_sel_1_14_11) begin
       if (_T_10984) begin
-        bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_235 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39497,7 +39497,7 @@ end // initial
       bht_bank_rd_data_out_1_236 <= 2'h0;
     end else if (bht_bank_sel_1_14_12) begin
       if (_T_10993) begin
-        bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_236 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39508,7 +39508,7 @@ end // initial
       bht_bank_rd_data_out_1_237 <= 2'h0;
     end else if (bht_bank_sel_1_14_13) begin
       if (_T_11002) begin
-        bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_237 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39519,7 +39519,7 @@ end // initial
       bht_bank_rd_data_out_1_238 <= 2'h0;
     end else if (bht_bank_sel_1_14_14) begin
       if (_T_11011) begin
-        bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_238 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39530,7 +39530,7 @@ end // initial
       bht_bank_rd_data_out_1_239 <= 2'h0;
     end else if (bht_bank_sel_1_14_15) begin
       if (_T_11020) begin
-        bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_239 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39541,7 +39541,7 @@ end // initial
       bht_bank_rd_data_out_1_240 <= 2'h0;
     end else if (bht_bank_sel_1_15_0) begin
       if (_T_11029) begin
-        bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_240 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39552,7 +39552,7 @@ end // initial
       bht_bank_rd_data_out_1_241 <= 2'h0;
     end else if (bht_bank_sel_1_15_1) begin
       if (_T_11038) begin
-        bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_241 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39563,7 +39563,7 @@ end // initial
       bht_bank_rd_data_out_1_242 <= 2'h0;
     end else if (bht_bank_sel_1_15_2) begin
       if (_T_11047) begin
-        bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_242 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39574,7 +39574,7 @@ end // initial
       bht_bank_rd_data_out_1_243 <= 2'h0;
     end else if (bht_bank_sel_1_15_3) begin
       if (_T_11056) begin
-        bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_243 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39585,7 +39585,7 @@ end // initial
       bht_bank_rd_data_out_1_244 <= 2'h0;
     end else if (bht_bank_sel_1_15_4) begin
       if (_T_11065) begin
-        bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_244 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39596,7 +39596,7 @@ end // initial
       bht_bank_rd_data_out_1_245 <= 2'h0;
     end else if (bht_bank_sel_1_15_5) begin
       if (_T_11074) begin
-        bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_245 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39607,7 +39607,7 @@ end // initial
       bht_bank_rd_data_out_1_246 <= 2'h0;
     end else if (bht_bank_sel_1_15_6) begin
       if (_T_11083) begin
-        bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_246 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39618,7 +39618,7 @@ end // initial
       bht_bank_rd_data_out_1_247 <= 2'h0;
     end else if (bht_bank_sel_1_15_7) begin
       if (_T_11092) begin
-        bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_247 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39629,7 +39629,7 @@ end // initial
       bht_bank_rd_data_out_1_248 <= 2'h0;
     end else if (bht_bank_sel_1_15_8) begin
       if (_T_11101) begin
-        bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_248 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39640,7 +39640,7 @@ end // initial
       bht_bank_rd_data_out_1_249 <= 2'h0;
     end else if (bht_bank_sel_1_15_9) begin
       if (_T_11110) begin
-        bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_249 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39651,7 +39651,7 @@ end // initial
       bht_bank_rd_data_out_1_250 <= 2'h0;
     end else if (bht_bank_sel_1_15_10) begin
       if (_T_11119) begin
-        bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_250 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39662,7 +39662,7 @@ end // initial
       bht_bank_rd_data_out_1_251 <= 2'h0;
     end else if (bht_bank_sel_1_15_11) begin
       if (_T_11128) begin
-        bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_251 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39673,7 +39673,7 @@ end // initial
       bht_bank_rd_data_out_1_252 <= 2'h0;
     end else if (bht_bank_sel_1_15_12) begin
       if (_T_11137) begin
-        bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_252 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39684,7 +39684,7 @@ end // initial
       bht_bank_rd_data_out_1_253 <= 2'h0;
     end else if (bht_bank_sel_1_15_13) begin
       if (_T_11146) begin
-        bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_253 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39695,7 +39695,7 @@ end // initial
       bht_bank_rd_data_out_1_254 <= 2'h0;
     end else if (bht_bank_sel_1_15_14) begin
       if (_T_11155) begin
-        bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_254 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39706,7 +39706,7 @@ end // initial
       bht_bank_rd_data_out_1_255 <= 2'h0;
     end else if (bht_bank_sel_1_15_15) begin
       if (_T_11164) begin
-        bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_255 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39717,7 +39717,7 @@ end // initial
       bht_bank_rd_data_out_0_0 <= 2'h0;
     end else if (bht_bank_sel_0_0_0) begin
       if (_T_6565) begin
-        bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_0 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39728,7 +39728,7 @@ end // initial
       bht_bank_rd_data_out_0_1 <= 2'h0;
     end else if (bht_bank_sel_0_0_1) begin
       if (_T_6574) begin
-        bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_1 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39739,7 +39739,7 @@ end // initial
       bht_bank_rd_data_out_0_2 <= 2'h0;
     end else if (bht_bank_sel_0_0_2) begin
       if (_T_6583) begin
-        bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_2 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39750,7 +39750,7 @@ end // initial
       bht_bank_rd_data_out_0_3 <= 2'h0;
     end else if (bht_bank_sel_0_0_3) begin
       if (_T_6592) begin
-        bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_3 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39761,7 +39761,7 @@ end // initial
       bht_bank_rd_data_out_0_4 <= 2'h0;
     end else if (bht_bank_sel_0_0_4) begin
       if (_T_6601) begin
-        bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_4 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39772,7 +39772,7 @@ end // initial
       bht_bank_rd_data_out_0_5 <= 2'h0;
     end else if (bht_bank_sel_0_0_5) begin
       if (_T_6610) begin
-        bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_5 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39783,7 +39783,7 @@ end // initial
       bht_bank_rd_data_out_0_6 <= 2'h0;
     end else if (bht_bank_sel_0_0_6) begin
       if (_T_6619) begin
-        bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_6 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39794,7 +39794,7 @@ end // initial
       bht_bank_rd_data_out_0_7 <= 2'h0;
     end else if (bht_bank_sel_0_0_7) begin
       if (_T_6628) begin
-        bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_7 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39805,7 +39805,7 @@ end // initial
       bht_bank_rd_data_out_0_8 <= 2'h0;
     end else if (bht_bank_sel_0_0_8) begin
       if (_T_6637) begin
-        bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_8 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39816,7 +39816,7 @@ end // initial
       bht_bank_rd_data_out_0_9 <= 2'h0;
     end else if (bht_bank_sel_0_0_9) begin
       if (_T_6646) begin
-        bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_9 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39827,7 +39827,7 @@ end // initial
       bht_bank_rd_data_out_0_10 <= 2'h0;
     end else if (bht_bank_sel_0_0_10) begin
       if (_T_6655) begin
-        bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_10 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39838,7 +39838,7 @@ end // initial
       bht_bank_rd_data_out_0_11 <= 2'h0;
     end else if (bht_bank_sel_0_0_11) begin
       if (_T_6664) begin
-        bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_11 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39849,7 +39849,7 @@ end // initial
       bht_bank_rd_data_out_0_12 <= 2'h0;
     end else if (bht_bank_sel_0_0_12) begin
       if (_T_6673) begin
-        bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_12 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39860,7 +39860,7 @@ end // initial
       bht_bank_rd_data_out_0_13 <= 2'h0;
     end else if (bht_bank_sel_0_0_13) begin
       if (_T_6682) begin
-        bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_13 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39871,7 +39871,7 @@ end // initial
       bht_bank_rd_data_out_0_14 <= 2'h0;
     end else if (bht_bank_sel_0_0_14) begin
       if (_T_6691) begin
-        bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_14 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39882,7 +39882,7 @@ end // initial
       bht_bank_rd_data_out_0_15 <= 2'h0;
     end else if (bht_bank_sel_0_0_15) begin
       if (_T_6700) begin
-        bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_15 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39893,7 +39893,7 @@ end // initial
       bht_bank_rd_data_out_0_16 <= 2'h0;
     end else if (bht_bank_sel_0_1_0) begin
       if (_T_6709) begin
-        bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_16 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39904,7 +39904,7 @@ end // initial
       bht_bank_rd_data_out_0_17 <= 2'h0;
     end else if (bht_bank_sel_0_1_1) begin
       if (_T_6718) begin
-        bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_17 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39915,7 +39915,7 @@ end // initial
       bht_bank_rd_data_out_0_18 <= 2'h0;
     end else if (bht_bank_sel_0_1_2) begin
       if (_T_6727) begin
-        bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_18 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39926,7 +39926,7 @@ end // initial
       bht_bank_rd_data_out_0_19 <= 2'h0;
     end else if (bht_bank_sel_0_1_3) begin
       if (_T_6736) begin
-        bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_19 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39937,7 +39937,7 @@ end // initial
       bht_bank_rd_data_out_0_20 <= 2'h0;
     end else if (bht_bank_sel_0_1_4) begin
       if (_T_6745) begin
-        bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_20 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39948,7 +39948,7 @@ end // initial
       bht_bank_rd_data_out_0_21 <= 2'h0;
     end else if (bht_bank_sel_0_1_5) begin
       if (_T_6754) begin
-        bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_21 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39959,7 +39959,7 @@ end // initial
       bht_bank_rd_data_out_0_22 <= 2'h0;
     end else if (bht_bank_sel_0_1_6) begin
       if (_T_6763) begin
-        bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_22 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39970,7 +39970,7 @@ end // initial
       bht_bank_rd_data_out_0_23 <= 2'h0;
     end else if (bht_bank_sel_0_1_7) begin
       if (_T_6772) begin
-        bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_23 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39981,7 +39981,7 @@ end // initial
       bht_bank_rd_data_out_0_24 <= 2'h0;
     end else if (bht_bank_sel_0_1_8) begin
       if (_T_6781) begin
-        bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_24 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39992,7 +39992,7 @@ end // initial
       bht_bank_rd_data_out_0_25 <= 2'h0;
     end else if (bht_bank_sel_0_1_9) begin
       if (_T_6790) begin
-        bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_25 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40003,7 +40003,7 @@ end // initial
       bht_bank_rd_data_out_0_26 <= 2'h0;
     end else if (bht_bank_sel_0_1_10) begin
       if (_T_6799) begin
-        bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_26 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40014,7 +40014,7 @@ end // initial
       bht_bank_rd_data_out_0_27 <= 2'h0;
     end else if (bht_bank_sel_0_1_11) begin
       if (_T_6808) begin
-        bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_27 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40025,7 +40025,7 @@ end // initial
       bht_bank_rd_data_out_0_28 <= 2'h0;
     end else if (bht_bank_sel_0_1_12) begin
       if (_T_6817) begin
-        bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_28 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40036,7 +40036,7 @@ end // initial
       bht_bank_rd_data_out_0_29 <= 2'h0;
     end else if (bht_bank_sel_0_1_13) begin
       if (_T_6826) begin
-        bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_29 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40047,7 +40047,7 @@ end // initial
       bht_bank_rd_data_out_0_30 <= 2'h0;
     end else if (bht_bank_sel_0_1_14) begin
       if (_T_6835) begin
-        bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_30 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40058,7 +40058,7 @@ end // initial
       bht_bank_rd_data_out_0_31 <= 2'h0;
     end else if (bht_bank_sel_0_1_15) begin
       if (_T_6844) begin
-        bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_31 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40069,7 +40069,7 @@ end // initial
       bht_bank_rd_data_out_0_32 <= 2'h0;
     end else if (bht_bank_sel_0_2_0) begin
       if (_T_6853) begin
-        bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_32 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40080,7 +40080,7 @@ end // initial
       bht_bank_rd_data_out_0_33 <= 2'h0;
     end else if (bht_bank_sel_0_2_1) begin
       if (_T_6862) begin
-        bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_33 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40091,7 +40091,7 @@ end // initial
       bht_bank_rd_data_out_0_34 <= 2'h0;
     end else if (bht_bank_sel_0_2_2) begin
       if (_T_6871) begin
-        bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_34 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40102,7 +40102,7 @@ end // initial
       bht_bank_rd_data_out_0_35 <= 2'h0;
     end else if (bht_bank_sel_0_2_3) begin
       if (_T_6880) begin
-        bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_35 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40113,7 +40113,7 @@ end // initial
       bht_bank_rd_data_out_0_36 <= 2'h0;
     end else if (bht_bank_sel_0_2_4) begin
       if (_T_6889) begin
-        bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_36 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40124,7 +40124,7 @@ end // initial
       bht_bank_rd_data_out_0_37 <= 2'h0;
     end else if (bht_bank_sel_0_2_5) begin
       if (_T_6898) begin
-        bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_37 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40135,7 +40135,7 @@ end // initial
       bht_bank_rd_data_out_0_38 <= 2'h0;
     end else if (bht_bank_sel_0_2_6) begin
       if (_T_6907) begin
-        bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_38 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40146,7 +40146,7 @@ end // initial
       bht_bank_rd_data_out_0_39 <= 2'h0;
     end else if (bht_bank_sel_0_2_7) begin
       if (_T_6916) begin
-        bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_39 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40157,7 +40157,7 @@ end // initial
       bht_bank_rd_data_out_0_40 <= 2'h0;
     end else if (bht_bank_sel_0_2_8) begin
       if (_T_6925) begin
-        bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_40 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40168,7 +40168,7 @@ end // initial
       bht_bank_rd_data_out_0_41 <= 2'h0;
     end else if (bht_bank_sel_0_2_9) begin
       if (_T_6934) begin
-        bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_41 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40179,7 +40179,7 @@ end // initial
       bht_bank_rd_data_out_0_42 <= 2'h0;
     end else if (bht_bank_sel_0_2_10) begin
       if (_T_6943) begin
-        bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_42 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40190,7 +40190,7 @@ end // initial
       bht_bank_rd_data_out_0_43 <= 2'h0;
     end else if (bht_bank_sel_0_2_11) begin
       if (_T_6952) begin
-        bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_43 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40201,7 +40201,7 @@ end // initial
       bht_bank_rd_data_out_0_44 <= 2'h0;
     end else if (bht_bank_sel_0_2_12) begin
       if (_T_6961) begin
-        bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_44 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40212,7 +40212,7 @@ end // initial
       bht_bank_rd_data_out_0_45 <= 2'h0;
     end else if (bht_bank_sel_0_2_13) begin
       if (_T_6970) begin
-        bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_45 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40223,7 +40223,7 @@ end // initial
       bht_bank_rd_data_out_0_46 <= 2'h0;
     end else if (bht_bank_sel_0_2_14) begin
       if (_T_6979) begin
-        bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_46 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40234,7 +40234,7 @@ end // initial
       bht_bank_rd_data_out_0_47 <= 2'h0;
     end else if (bht_bank_sel_0_2_15) begin
       if (_T_6988) begin
-        bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_47 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40245,7 +40245,7 @@ end // initial
       bht_bank_rd_data_out_0_48 <= 2'h0;
     end else if (bht_bank_sel_0_3_0) begin
       if (_T_6997) begin
-        bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_48 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40256,7 +40256,7 @@ end // initial
       bht_bank_rd_data_out_0_49 <= 2'h0;
     end else if (bht_bank_sel_0_3_1) begin
       if (_T_7006) begin
-        bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_49 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40267,7 +40267,7 @@ end // initial
       bht_bank_rd_data_out_0_50 <= 2'h0;
     end else if (bht_bank_sel_0_3_2) begin
       if (_T_7015) begin
-        bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_50 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40278,7 +40278,7 @@ end // initial
       bht_bank_rd_data_out_0_51 <= 2'h0;
     end else if (bht_bank_sel_0_3_3) begin
       if (_T_7024) begin
-        bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_51 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40289,7 +40289,7 @@ end // initial
       bht_bank_rd_data_out_0_52 <= 2'h0;
     end else if (bht_bank_sel_0_3_4) begin
       if (_T_7033) begin
-        bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_52 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40300,7 +40300,7 @@ end // initial
       bht_bank_rd_data_out_0_53 <= 2'h0;
     end else if (bht_bank_sel_0_3_5) begin
       if (_T_7042) begin
-        bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_53 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40311,7 +40311,7 @@ end // initial
       bht_bank_rd_data_out_0_54 <= 2'h0;
     end else if (bht_bank_sel_0_3_6) begin
       if (_T_7051) begin
-        bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_54 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40322,7 +40322,7 @@ end // initial
       bht_bank_rd_data_out_0_55 <= 2'h0;
     end else if (bht_bank_sel_0_3_7) begin
       if (_T_7060) begin
-        bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_55 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40333,7 +40333,7 @@ end // initial
       bht_bank_rd_data_out_0_56 <= 2'h0;
     end else if (bht_bank_sel_0_3_8) begin
       if (_T_7069) begin
-        bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_56 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40344,7 +40344,7 @@ end // initial
       bht_bank_rd_data_out_0_57 <= 2'h0;
     end else if (bht_bank_sel_0_3_9) begin
       if (_T_7078) begin
-        bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_57 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40355,7 +40355,7 @@ end // initial
       bht_bank_rd_data_out_0_58 <= 2'h0;
     end else if (bht_bank_sel_0_3_10) begin
       if (_T_7087) begin
-        bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_58 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40366,7 +40366,7 @@ end // initial
       bht_bank_rd_data_out_0_59 <= 2'h0;
     end else if (bht_bank_sel_0_3_11) begin
       if (_T_7096) begin
-        bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_59 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40377,7 +40377,7 @@ end // initial
       bht_bank_rd_data_out_0_60 <= 2'h0;
     end else if (bht_bank_sel_0_3_12) begin
       if (_T_7105) begin
-        bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_60 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40388,7 +40388,7 @@ end // initial
       bht_bank_rd_data_out_0_61 <= 2'h0;
     end else if (bht_bank_sel_0_3_13) begin
       if (_T_7114) begin
-        bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_61 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40399,7 +40399,7 @@ end // initial
       bht_bank_rd_data_out_0_62 <= 2'h0;
     end else if (bht_bank_sel_0_3_14) begin
       if (_T_7123) begin
-        bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_62 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40410,7 +40410,7 @@ end // initial
       bht_bank_rd_data_out_0_63 <= 2'h0;
     end else if (bht_bank_sel_0_3_15) begin
       if (_T_7132) begin
-        bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_63 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40421,7 +40421,7 @@ end // initial
       bht_bank_rd_data_out_0_64 <= 2'h0;
     end else if (bht_bank_sel_0_4_0) begin
       if (_T_7141) begin
-        bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_64 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40432,7 +40432,7 @@ end // initial
       bht_bank_rd_data_out_0_65 <= 2'h0;
     end else if (bht_bank_sel_0_4_1) begin
       if (_T_7150) begin
-        bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_65 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40443,7 +40443,7 @@ end // initial
       bht_bank_rd_data_out_0_66 <= 2'h0;
     end else if (bht_bank_sel_0_4_2) begin
       if (_T_7159) begin
-        bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_66 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40454,7 +40454,7 @@ end // initial
       bht_bank_rd_data_out_0_67 <= 2'h0;
     end else if (bht_bank_sel_0_4_3) begin
       if (_T_7168) begin
-        bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_67 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40465,7 +40465,7 @@ end // initial
       bht_bank_rd_data_out_0_68 <= 2'h0;
     end else if (bht_bank_sel_0_4_4) begin
       if (_T_7177) begin
-        bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_68 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40476,7 +40476,7 @@ end // initial
       bht_bank_rd_data_out_0_69 <= 2'h0;
     end else if (bht_bank_sel_0_4_5) begin
       if (_T_7186) begin
-        bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_69 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40487,7 +40487,7 @@ end // initial
       bht_bank_rd_data_out_0_70 <= 2'h0;
     end else if (bht_bank_sel_0_4_6) begin
       if (_T_7195) begin
-        bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_70 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40498,7 +40498,7 @@ end // initial
       bht_bank_rd_data_out_0_71 <= 2'h0;
     end else if (bht_bank_sel_0_4_7) begin
       if (_T_7204) begin
-        bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_71 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40509,7 +40509,7 @@ end // initial
       bht_bank_rd_data_out_0_72 <= 2'h0;
     end else if (bht_bank_sel_0_4_8) begin
       if (_T_7213) begin
-        bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_72 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40520,7 +40520,7 @@ end // initial
       bht_bank_rd_data_out_0_73 <= 2'h0;
     end else if (bht_bank_sel_0_4_9) begin
       if (_T_7222) begin
-        bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_73 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40531,7 +40531,7 @@ end // initial
       bht_bank_rd_data_out_0_74 <= 2'h0;
     end else if (bht_bank_sel_0_4_10) begin
       if (_T_7231) begin
-        bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_74 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40542,7 +40542,7 @@ end // initial
       bht_bank_rd_data_out_0_75 <= 2'h0;
     end else if (bht_bank_sel_0_4_11) begin
       if (_T_7240) begin
-        bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_75 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40553,7 +40553,7 @@ end // initial
       bht_bank_rd_data_out_0_76 <= 2'h0;
     end else if (bht_bank_sel_0_4_12) begin
       if (_T_7249) begin
-        bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_76 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40564,7 +40564,7 @@ end // initial
       bht_bank_rd_data_out_0_77 <= 2'h0;
     end else if (bht_bank_sel_0_4_13) begin
       if (_T_7258) begin
-        bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_77 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40575,7 +40575,7 @@ end // initial
       bht_bank_rd_data_out_0_78 <= 2'h0;
     end else if (bht_bank_sel_0_4_14) begin
       if (_T_7267) begin
-        bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_78 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40586,7 +40586,7 @@ end // initial
       bht_bank_rd_data_out_0_79 <= 2'h0;
     end else if (bht_bank_sel_0_4_15) begin
       if (_T_7276) begin
-        bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_79 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40597,7 +40597,7 @@ end // initial
       bht_bank_rd_data_out_0_80 <= 2'h0;
     end else if (bht_bank_sel_0_5_0) begin
       if (_T_7285) begin
-        bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_80 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40608,7 +40608,7 @@ end // initial
       bht_bank_rd_data_out_0_81 <= 2'h0;
     end else if (bht_bank_sel_0_5_1) begin
       if (_T_7294) begin
-        bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_81 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40619,7 +40619,7 @@ end // initial
       bht_bank_rd_data_out_0_82 <= 2'h0;
     end else if (bht_bank_sel_0_5_2) begin
       if (_T_7303) begin
-        bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_82 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40630,7 +40630,7 @@ end // initial
       bht_bank_rd_data_out_0_83 <= 2'h0;
     end else if (bht_bank_sel_0_5_3) begin
       if (_T_7312) begin
-        bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_83 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40641,7 +40641,7 @@ end // initial
       bht_bank_rd_data_out_0_84 <= 2'h0;
     end else if (bht_bank_sel_0_5_4) begin
       if (_T_7321) begin
-        bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_84 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40652,7 +40652,7 @@ end // initial
       bht_bank_rd_data_out_0_85 <= 2'h0;
     end else if (bht_bank_sel_0_5_5) begin
       if (_T_7330) begin
-        bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_85 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40663,7 +40663,7 @@ end // initial
       bht_bank_rd_data_out_0_86 <= 2'h0;
     end else if (bht_bank_sel_0_5_6) begin
       if (_T_7339) begin
-        bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_86 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40674,7 +40674,7 @@ end // initial
       bht_bank_rd_data_out_0_87 <= 2'h0;
     end else if (bht_bank_sel_0_5_7) begin
       if (_T_7348) begin
-        bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_87 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40685,7 +40685,7 @@ end // initial
       bht_bank_rd_data_out_0_88 <= 2'h0;
     end else if (bht_bank_sel_0_5_8) begin
       if (_T_7357) begin
-        bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_88 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40696,7 +40696,7 @@ end // initial
       bht_bank_rd_data_out_0_89 <= 2'h0;
     end else if (bht_bank_sel_0_5_9) begin
       if (_T_7366) begin
-        bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_89 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40707,7 +40707,7 @@ end // initial
       bht_bank_rd_data_out_0_90 <= 2'h0;
     end else if (bht_bank_sel_0_5_10) begin
       if (_T_7375) begin
-        bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_90 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40718,7 +40718,7 @@ end // initial
       bht_bank_rd_data_out_0_91 <= 2'h0;
     end else if (bht_bank_sel_0_5_11) begin
       if (_T_7384) begin
-        bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_91 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40729,7 +40729,7 @@ end // initial
       bht_bank_rd_data_out_0_92 <= 2'h0;
     end else if (bht_bank_sel_0_5_12) begin
       if (_T_7393) begin
-        bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_92 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40740,7 +40740,7 @@ end // initial
       bht_bank_rd_data_out_0_93 <= 2'h0;
     end else if (bht_bank_sel_0_5_13) begin
       if (_T_7402) begin
-        bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_93 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40751,7 +40751,7 @@ end // initial
       bht_bank_rd_data_out_0_94 <= 2'h0;
     end else if (bht_bank_sel_0_5_14) begin
       if (_T_7411) begin
-        bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_94 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40762,7 +40762,7 @@ end // initial
       bht_bank_rd_data_out_0_95 <= 2'h0;
     end else if (bht_bank_sel_0_5_15) begin
       if (_T_7420) begin
-        bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_95 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40773,7 +40773,7 @@ end // initial
       bht_bank_rd_data_out_0_96 <= 2'h0;
     end else if (bht_bank_sel_0_6_0) begin
       if (_T_7429) begin
-        bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_96 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40784,7 +40784,7 @@ end // initial
       bht_bank_rd_data_out_0_97 <= 2'h0;
     end else if (bht_bank_sel_0_6_1) begin
       if (_T_7438) begin
-        bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_97 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40795,7 +40795,7 @@ end // initial
       bht_bank_rd_data_out_0_98 <= 2'h0;
     end else if (bht_bank_sel_0_6_2) begin
       if (_T_7447) begin
-        bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_98 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40806,7 +40806,7 @@ end // initial
       bht_bank_rd_data_out_0_99 <= 2'h0;
     end else if (bht_bank_sel_0_6_3) begin
       if (_T_7456) begin
-        bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_99 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40817,7 +40817,7 @@ end // initial
       bht_bank_rd_data_out_0_100 <= 2'h0;
     end else if (bht_bank_sel_0_6_4) begin
       if (_T_7465) begin
-        bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_100 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40828,7 +40828,7 @@ end // initial
       bht_bank_rd_data_out_0_101 <= 2'h0;
     end else if (bht_bank_sel_0_6_5) begin
       if (_T_7474) begin
-        bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_101 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40839,7 +40839,7 @@ end // initial
       bht_bank_rd_data_out_0_102 <= 2'h0;
     end else if (bht_bank_sel_0_6_6) begin
       if (_T_7483) begin
-        bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_102 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40850,7 +40850,7 @@ end // initial
       bht_bank_rd_data_out_0_103 <= 2'h0;
     end else if (bht_bank_sel_0_6_7) begin
       if (_T_7492) begin
-        bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_103 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40861,7 +40861,7 @@ end // initial
       bht_bank_rd_data_out_0_104 <= 2'h0;
     end else if (bht_bank_sel_0_6_8) begin
       if (_T_7501) begin
-        bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_104 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40872,7 +40872,7 @@ end // initial
       bht_bank_rd_data_out_0_105 <= 2'h0;
     end else if (bht_bank_sel_0_6_9) begin
       if (_T_7510) begin
-        bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_105 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40883,7 +40883,7 @@ end // initial
       bht_bank_rd_data_out_0_106 <= 2'h0;
     end else if (bht_bank_sel_0_6_10) begin
       if (_T_7519) begin
-        bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_106 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40894,7 +40894,7 @@ end // initial
       bht_bank_rd_data_out_0_107 <= 2'h0;
     end else if (bht_bank_sel_0_6_11) begin
       if (_T_7528) begin
-        bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_107 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40905,7 +40905,7 @@ end // initial
       bht_bank_rd_data_out_0_108 <= 2'h0;
     end else if (bht_bank_sel_0_6_12) begin
       if (_T_7537) begin
-        bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_108 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40916,7 +40916,7 @@ end // initial
       bht_bank_rd_data_out_0_109 <= 2'h0;
     end else if (bht_bank_sel_0_6_13) begin
       if (_T_7546) begin
-        bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_109 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40927,7 +40927,7 @@ end // initial
       bht_bank_rd_data_out_0_110 <= 2'h0;
     end else if (bht_bank_sel_0_6_14) begin
       if (_T_7555) begin
-        bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_110 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40938,7 +40938,7 @@ end // initial
       bht_bank_rd_data_out_0_111 <= 2'h0;
     end else if (bht_bank_sel_0_6_15) begin
       if (_T_7564) begin
-        bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_111 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40949,7 +40949,7 @@ end // initial
       bht_bank_rd_data_out_0_112 <= 2'h0;
     end else if (bht_bank_sel_0_7_0) begin
       if (_T_7573) begin
-        bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_112 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40960,7 +40960,7 @@ end // initial
       bht_bank_rd_data_out_0_113 <= 2'h0;
     end else if (bht_bank_sel_0_7_1) begin
       if (_T_7582) begin
-        bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_113 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40971,7 +40971,7 @@ end // initial
       bht_bank_rd_data_out_0_114 <= 2'h0;
     end else if (bht_bank_sel_0_7_2) begin
       if (_T_7591) begin
-        bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_114 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40982,7 +40982,7 @@ end // initial
       bht_bank_rd_data_out_0_115 <= 2'h0;
     end else if (bht_bank_sel_0_7_3) begin
       if (_T_7600) begin
-        bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_115 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40993,7 +40993,7 @@ end // initial
       bht_bank_rd_data_out_0_116 <= 2'h0;
     end else if (bht_bank_sel_0_7_4) begin
       if (_T_7609) begin
-        bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_116 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41004,7 +41004,7 @@ end // initial
       bht_bank_rd_data_out_0_117 <= 2'h0;
     end else if (bht_bank_sel_0_7_5) begin
       if (_T_7618) begin
-        bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_117 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41015,7 +41015,7 @@ end // initial
       bht_bank_rd_data_out_0_118 <= 2'h0;
     end else if (bht_bank_sel_0_7_6) begin
       if (_T_7627) begin
-        bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_118 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41026,7 +41026,7 @@ end // initial
       bht_bank_rd_data_out_0_119 <= 2'h0;
     end else if (bht_bank_sel_0_7_7) begin
       if (_T_7636) begin
-        bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_119 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41037,7 +41037,7 @@ end // initial
       bht_bank_rd_data_out_0_120 <= 2'h0;
     end else if (bht_bank_sel_0_7_8) begin
       if (_T_7645) begin
-        bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_120 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41048,7 +41048,7 @@ end // initial
       bht_bank_rd_data_out_0_121 <= 2'h0;
     end else if (bht_bank_sel_0_7_9) begin
       if (_T_7654) begin
-        bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_121 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41059,7 +41059,7 @@ end // initial
       bht_bank_rd_data_out_0_122 <= 2'h0;
     end else if (bht_bank_sel_0_7_10) begin
       if (_T_7663) begin
-        bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_122 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41070,7 +41070,7 @@ end // initial
       bht_bank_rd_data_out_0_123 <= 2'h0;
     end else if (bht_bank_sel_0_7_11) begin
       if (_T_7672) begin
-        bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_123 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41081,7 +41081,7 @@ end // initial
       bht_bank_rd_data_out_0_124 <= 2'h0;
     end else if (bht_bank_sel_0_7_12) begin
       if (_T_7681) begin
-        bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_124 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41092,7 +41092,7 @@ end // initial
       bht_bank_rd_data_out_0_125 <= 2'h0;
     end else if (bht_bank_sel_0_7_13) begin
       if (_T_7690) begin
-        bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_125 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41103,7 +41103,7 @@ end // initial
       bht_bank_rd_data_out_0_126 <= 2'h0;
     end else if (bht_bank_sel_0_7_14) begin
       if (_T_7699) begin
-        bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_126 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41114,7 +41114,7 @@ end // initial
       bht_bank_rd_data_out_0_127 <= 2'h0;
     end else if (bht_bank_sel_0_7_15) begin
       if (_T_7708) begin
-        bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_127 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41125,7 +41125,7 @@ end // initial
       bht_bank_rd_data_out_0_128 <= 2'h0;
     end else if (bht_bank_sel_0_8_0) begin
       if (_T_7717) begin
-        bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_128 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41136,7 +41136,7 @@ end // initial
       bht_bank_rd_data_out_0_129 <= 2'h0;
     end else if (bht_bank_sel_0_8_1) begin
       if (_T_7726) begin
-        bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_129 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41147,7 +41147,7 @@ end // initial
       bht_bank_rd_data_out_0_130 <= 2'h0;
     end else if (bht_bank_sel_0_8_2) begin
       if (_T_7735) begin
-        bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_130 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41158,7 +41158,7 @@ end // initial
       bht_bank_rd_data_out_0_131 <= 2'h0;
     end else if (bht_bank_sel_0_8_3) begin
       if (_T_7744) begin
-        bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_131 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41169,7 +41169,7 @@ end // initial
       bht_bank_rd_data_out_0_132 <= 2'h0;
     end else if (bht_bank_sel_0_8_4) begin
       if (_T_7753) begin
-        bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_132 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41180,7 +41180,7 @@ end // initial
       bht_bank_rd_data_out_0_133 <= 2'h0;
     end else if (bht_bank_sel_0_8_5) begin
       if (_T_7762) begin
-        bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_133 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41191,7 +41191,7 @@ end // initial
       bht_bank_rd_data_out_0_134 <= 2'h0;
     end else if (bht_bank_sel_0_8_6) begin
       if (_T_7771) begin
-        bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_134 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41202,7 +41202,7 @@ end // initial
       bht_bank_rd_data_out_0_135 <= 2'h0;
     end else if (bht_bank_sel_0_8_7) begin
       if (_T_7780) begin
-        bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_135 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41213,7 +41213,7 @@ end // initial
       bht_bank_rd_data_out_0_136 <= 2'h0;
     end else if (bht_bank_sel_0_8_8) begin
       if (_T_7789) begin
-        bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_136 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41224,7 +41224,7 @@ end // initial
       bht_bank_rd_data_out_0_137 <= 2'h0;
     end else if (bht_bank_sel_0_8_9) begin
       if (_T_7798) begin
-        bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_137 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41235,7 +41235,7 @@ end // initial
       bht_bank_rd_data_out_0_138 <= 2'h0;
     end else if (bht_bank_sel_0_8_10) begin
       if (_T_7807) begin
-        bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_138 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41246,7 +41246,7 @@ end // initial
       bht_bank_rd_data_out_0_139 <= 2'h0;
     end else if (bht_bank_sel_0_8_11) begin
       if (_T_7816) begin
-        bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_139 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41257,7 +41257,7 @@ end // initial
       bht_bank_rd_data_out_0_140 <= 2'h0;
     end else if (bht_bank_sel_0_8_12) begin
       if (_T_7825) begin
-        bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_140 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41268,7 +41268,7 @@ end // initial
       bht_bank_rd_data_out_0_141 <= 2'h0;
     end else if (bht_bank_sel_0_8_13) begin
       if (_T_7834) begin
-        bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_141 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41279,7 +41279,7 @@ end // initial
       bht_bank_rd_data_out_0_142 <= 2'h0;
     end else if (bht_bank_sel_0_8_14) begin
       if (_T_7843) begin
-        bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_142 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41290,7 +41290,7 @@ end // initial
       bht_bank_rd_data_out_0_143 <= 2'h0;
     end else if (bht_bank_sel_0_8_15) begin
       if (_T_7852) begin
-        bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_143 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41301,7 +41301,7 @@ end // initial
       bht_bank_rd_data_out_0_144 <= 2'h0;
     end else if (bht_bank_sel_0_9_0) begin
       if (_T_7861) begin
-        bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_144 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41312,7 +41312,7 @@ end // initial
       bht_bank_rd_data_out_0_145 <= 2'h0;
     end else if (bht_bank_sel_0_9_1) begin
       if (_T_7870) begin
-        bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_145 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41323,7 +41323,7 @@ end // initial
       bht_bank_rd_data_out_0_146 <= 2'h0;
     end else if (bht_bank_sel_0_9_2) begin
       if (_T_7879) begin
-        bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_146 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41334,7 +41334,7 @@ end // initial
       bht_bank_rd_data_out_0_147 <= 2'h0;
     end else if (bht_bank_sel_0_9_3) begin
       if (_T_7888) begin
-        bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_147 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41345,7 +41345,7 @@ end // initial
       bht_bank_rd_data_out_0_148 <= 2'h0;
     end else if (bht_bank_sel_0_9_4) begin
       if (_T_7897) begin
-        bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_148 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41356,7 +41356,7 @@ end // initial
       bht_bank_rd_data_out_0_149 <= 2'h0;
     end else if (bht_bank_sel_0_9_5) begin
       if (_T_7906) begin
-        bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_149 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41367,7 +41367,7 @@ end // initial
       bht_bank_rd_data_out_0_150 <= 2'h0;
     end else if (bht_bank_sel_0_9_6) begin
       if (_T_7915) begin
-        bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_150 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41378,7 +41378,7 @@ end // initial
       bht_bank_rd_data_out_0_151 <= 2'h0;
     end else if (bht_bank_sel_0_9_7) begin
       if (_T_7924) begin
-        bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_151 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41389,7 +41389,7 @@ end // initial
       bht_bank_rd_data_out_0_152 <= 2'h0;
     end else if (bht_bank_sel_0_9_8) begin
       if (_T_7933) begin
-        bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_152 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41400,7 +41400,7 @@ end // initial
       bht_bank_rd_data_out_0_153 <= 2'h0;
     end else if (bht_bank_sel_0_9_9) begin
       if (_T_7942) begin
-        bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_153 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41411,7 +41411,7 @@ end // initial
       bht_bank_rd_data_out_0_154 <= 2'h0;
     end else if (bht_bank_sel_0_9_10) begin
       if (_T_7951) begin
-        bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_154 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41422,7 +41422,7 @@ end // initial
       bht_bank_rd_data_out_0_155 <= 2'h0;
     end else if (bht_bank_sel_0_9_11) begin
       if (_T_7960) begin
-        bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_155 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41433,7 +41433,7 @@ end // initial
       bht_bank_rd_data_out_0_156 <= 2'h0;
     end else if (bht_bank_sel_0_9_12) begin
       if (_T_7969) begin
-        bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_156 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41444,7 +41444,7 @@ end // initial
       bht_bank_rd_data_out_0_157 <= 2'h0;
     end else if (bht_bank_sel_0_9_13) begin
       if (_T_7978) begin
-        bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_157 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41455,7 +41455,7 @@ end // initial
       bht_bank_rd_data_out_0_158 <= 2'h0;
     end else if (bht_bank_sel_0_9_14) begin
       if (_T_7987) begin
-        bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_158 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41466,7 +41466,7 @@ end // initial
       bht_bank_rd_data_out_0_159 <= 2'h0;
     end else if (bht_bank_sel_0_9_15) begin
       if (_T_7996) begin
-        bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_159 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41477,7 +41477,7 @@ end // initial
       bht_bank_rd_data_out_0_160 <= 2'h0;
     end else if (bht_bank_sel_0_10_0) begin
       if (_T_8005) begin
-        bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_160 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41488,7 +41488,7 @@ end // initial
       bht_bank_rd_data_out_0_161 <= 2'h0;
     end else if (bht_bank_sel_0_10_1) begin
       if (_T_8014) begin
-        bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_161 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41499,7 +41499,7 @@ end // initial
       bht_bank_rd_data_out_0_162 <= 2'h0;
     end else if (bht_bank_sel_0_10_2) begin
       if (_T_8023) begin
-        bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_162 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41510,7 +41510,7 @@ end // initial
       bht_bank_rd_data_out_0_163 <= 2'h0;
     end else if (bht_bank_sel_0_10_3) begin
       if (_T_8032) begin
-        bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_163 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41521,7 +41521,7 @@ end // initial
       bht_bank_rd_data_out_0_164 <= 2'h0;
     end else if (bht_bank_sel_0_10_4) begin
       if (_T_8041) begin
-        bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_164 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41532,7 +41532,7 @@ end // initial
       bht_bank_rd_data_out_0_165 <= 2'h0;
     end else if (bht_bank_sel_0_10_5) begin
       if (_T_8050) begin
-        bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_165 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41543,7 +41543,7 @@ end // initial
       bht_bank_rd_data_out_0_166 <= 2'h0;
     end else if (bht_bank_sel_0_10_6) begin
       if (_T_8059) begin
-        bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_166 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41554,7 +41554,7 @@ end // initial
       bht_bank_rd_data_out_0_167 <= 2'h0;
     end else if (bht_bank_sel_0_10_7) begin
       if (_T_8068) begin
-        bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_167 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41565,7 +41565,7 @@ end // initial
       bht_bank_rd_data_out_0_168 <= 2'h0;
     end else if (bht_bank_sel_0_10_8) begin
       if (_T_8077) begin
-        bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_168 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41576,7 +41576,7 @@ end // initial
       bht_bank_rd_data_out_0_169 <= 2'h0;
     end else if (bht_bank_sel_0_10_9) begin
       if (_T_8086) begin
-        bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_169 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41587,7 +41587,7 @@ end // initial
       bht_bank_rd_data_out_0_170 <= 2'h0;
     end else if (bht_bank_sel_0_10_10) begin
       if (_T_8095) begin
-        bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_170 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41598,7 +41598,7 @@ end // initial
       bht_bank_rd_data_out_0_171 <= 2'h0;
     end else if (bht_bank_sel_0_10_11) begin
       if (_T_8104) begin
-        bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_171 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41609,7 +41609,7 @@ end // initial
       bht_bank_rd_data_out_0_172 <= 2'h0;
     end else if (bht_bank_sel_0_10_12) begin
       if (_T_8113) begin
-        bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_172 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41620,7 +41620,7 @@ end // initial
       bht_bank_rd_data_out_0_173 <= 2'h0;
     end else if (bht_bank_sel_0_10_13) begin
       if (_T_8122) begin
-        bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_173 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41631,7 +41631,7 @@ end // initial
       bht_bank_rd_data_out_0_174 <= 2'h0;
     end else if (bht_bank_sel_0_10_14) begin
       if (_T_8131) begin
-        bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_174 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41642,7 +41642,7 @@ end // initial
       bht_bank_rd_data_out_0_175 <= 2'h0;
     end else if (bht_bank_sel_0_10_15) begin
       if (_T_8140) begin
-        bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_175 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41653,7 +41653,7 @@ end // initial
       bht_bank_rd_data_out_0_176 <= 2'h0;
     end else if (bht_bank_sel_0_11_0) begin
       if (_T_8149) begin
-        bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_176 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41664,7 +41664,7 @@ end // initial
       bht_bank_rd_data_out_0_177 <= 2'h0;
     end else if (bht_bank_sel_0_11_1) begin
       if (_T_8158) begin
-        bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_177 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41675,7 +41675,7 @@ end // initial
       bht_bank_rd_data_out_0_178 <= 2'h0;
     end else if (bht_bank_sel_0_11_2) begin
       if (_T_8167) begin
-        bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_178 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41686,7 +41686,7 @@ end // initial
       bht_bank_rd_data_out_0_179 <= 2'h0;
     end else if (bht_bank_sel_0_11_3) begin
       if (_T_8176) begin
-        bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_179 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41697,7 +41697,7 @@ end // initial
       bht_bank_rd_data_out_0_180 <= 2'h0;
     end else if (bht_bank_sel_0_11_4) begin
       if (_T_8185) begin
-        bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_180 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41708,7 +41708,7 @@ end // initial
       bht_bank_rd_data_out_0_181 <= 2'h0;
     end else if (bht_bank_sel_0_11_5) begin
       if (_T_8194) begin
-        bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_181 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41719,7 +41719,7 @@ end // initial
       bht_bank_rd_data_out_0_182 <= 2'h0;
     end else if (bht_bank_sel_0_11_6) begin
       if (_T_8203) begin
-        bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_182 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41730,7 +41730,7 @@ end // initial
       bht_bank_rd_data_out_0_183 <= 2'h0;
     end else if (bht_bank_sel_0_11_7) begin
       if (_T_8212) begin
-        bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_183 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41741,7 +41741,7 @@ end // initial
       bht_bank_rd_data_out_0_184 <= 2'h0;
     end else if (bht_bank_sel_0_11_8) begin
       if (_T_8221) begin
-        bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_184 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41752,7 +41752,7 @@ end // initial
       bht_bank_rd_data_out_0_185 <= 2'h0;
     end else if (bht_bank_sel_0_11_9) begin
       if (_T_8230) begin
-        bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_185 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41763,7 +41763,7 @@ end // initial
       bht_bank_rd_data_out_0_186 <= 2'h0;
     end else if (bht_bank_sel_0_11_10) begin
       if (_T_8239) begin
-        bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_186 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41774,7 +41774,7 @@ end // initial
       bht_bank_rd_data_out_0_187 <= 2'h0;
     end else if (bht_bank_sel_0_11_11) begin
       if (_T_8248) begin
-        bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_187 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41785,7 +41785,7 @@ end // initial
       bht_bank_rd_data_out_0_188 <= 2'h0;
     end else if (bht_bank_sel_0_11_12) begin
       if (_T_8257) begin
-        bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_188 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41796,7 +41796,7 @@ end // initial
       bht_bank_rd_data_out_0_189 <= 2'h0;
     end else if (bht_bank_sel_0_11_13) begin
       if (_T_8266) begin
-        bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_189 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41807,7 +41807,7 @@ end // initial
       bht_bank_rd_data_out_0_190 <= 2'h0;
     end else if (bht_bank_sel_0_11_14) begin
       if (_T_8275) begin
-        bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_190 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41818,7 +41818,7 @@ end // initial
       bht_bank_rd_data_out_0_191 <= 2'h0;
     end else if (bht_bank_sel_0_11_15) begin
       if (_T_8284) begin
-        bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_191 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41829,7 +41829,7 @@ end // initial
       bht_bank_rd_data_out_0_192 <= 2'h0;
     end else if (bht_bank_sel_0_12_0) begin
       if (_T_8293) begin
-        bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_192 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41840,7 +41840,7 @@ end // initial
       bht_bank_rd_data_out_0_193 <= 2'h0;
     end else if (bht_bank_sel_0_12_1) begin
       if (_T_8302) begin
-        bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_193 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41851,7 +41851,7 @@ end // initial
       bht_bank_rd_data_out_0_194 <= 2'h0;
     end else if (bht_bank_sel_0_12_2) begin
       if (_T_8311) begin
-        bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_194 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41862,7 +41862,7 @@ end // initial
       bht_bank_rd_data_out_0_195 <= 2'h0;
     end else if (bht_bank_sel_0_12_3) begin
       if (_T_8320) begin
-        bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_195 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41873,7 +41873,7 @@ end // initial
       bht_bank_rd_data_out_0_196 <= 2'h0;
     end else if (bht_bank_sel_0_12_4) begin
       if (_T_8329) begin
-        bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_196 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41884,7 +41884,7 @@ end // initial
       bht_bank_rd_data_out_0_197 <= 2'h0;
     end else if (bht_bank_sel_0_12_5) begin
       if (_T_8338) begin
-        bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_197 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41895,7 +41895,7 @@ end // initial
       bht_bank_rd_data_out_0_198 <= 2'h0;
     end else if (bht_bank_sel_0_12_6) begin
       if (_T_8347) begin
-        bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_198 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41906,7 +41906,7 @@ end // initial
       bht_bank_rd_data_out_0_199 <= 2'h0;
     end else if (bht_bank_sel_0_12_7) begin
       if (_T_8356) begin
-        bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_199 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41917,7 +41917,7 @@ end // initial
       bht_bank_rd_data_out_0_200 <= 2'h0;
     end else if (bht_bank_sel_0_12_8) begin
       if (_T_8365) begin
-        bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_200 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41928,7 +41928,7 @@ end // initial
       bht_bank_rd_data_out_0_201 <= 2'h0;
     end else if (bht_bank_sel_0_12_9) begin
       if (_T_8374) begin
-        bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_201 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41939,7 +41939,7 @@ end // initial
       bht_bank_rd_data_out_0_202 <= 2'h0;
     end else if (bht_bank_sel_0_12_10) begin
       if (_T_8383) begin
-        bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_202 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41950,7 +41950,7 @@ end // initial
       bht_bank_rd_data_out_0_203 <= 2'h0;
     end else if (bht_bank_sel_0_12_11) begin
       if (_T_8392) begin
-        bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_203 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41961,7 +41961,7 @@ end // initial
       bht_bank_rd_data_out_0_204 <= 2'h0;
     end else if (bht_bank_sel_0_12_12) begin
       if (_T_8401) begin
-        bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_204 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41972,7 +41972,7 @@ end // initial
       bht_bank_rd_data_out_0_205 <= 2'h0;
     end else if (bht_bank_sel_0_12_13) begin
       if (_T_8410) begin
-        bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_205 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41983,7 +41983,7 @@ end // initial
       bht_bank_rd_data_out_0_206 <= 2'h0;
     end else if (bht_bank_sel_0_12_14) begin
       if (_T_8419) begin
-        bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_206 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41994,7 +41994,7 @@ end // initial
       bht_bank_rd_data_out_0_207 <= 2'h0;
     end else if (bht_bank_sel_0_12_15) begin
       if (_T_8428) begin
-        bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_207 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42005,7 +42005,7 @@ end // initial
       bht_bank_rd_data_out_0_208 <= 2'h0;
     end else if (bht_bank_sel_0_13_0) begin
       if (_T_8437) begin
-        bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_208 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42016,7 +42016,7 @@ end // initial
       bht_bank_rd_data_out_0_209 <= 2'h0;
     end else if (bht_bank_sel_0_13_1) begin
       if (_T_8446) begin
-        bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_209 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42027,7 +42027,7 @@ end // initial
       bht_bank_rd_data_out_0_210 <= 2'h0;
     end else if (bht_bank_sel_0_13_2) begin
       if (_T_8455) begin
-        bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_210 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42038,7 +42038,7 @@ end // initial
       bht_bank_rd_data_out_0_211 <= 2'h0;
     end else if (bht_bank_sel_0_13_3) begin
       if (_T_8464) begin
-        bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_211 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42049,7 +42049,7 @@ end // initial
       bht_bank_rd_data_out_0_212 <= 2'h0;
     end else if (bht_bank_sel_0_13_4) begin
       if (_T_8473) begin
-        bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_212 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42060,7 +42060,7 @@ end // initial
       bht_bank_rd_data_out_0_213 <= 2'h0;
     end else if (bht_bank_sel_0_13_5) begin
       if (_T_8482) begin
-        bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_213 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42071,7 +42071,7 @@ end // initial
       bht_bank_rd_data_out_0_214 <= 2'h0;
     end else if (bht_bank_sel_0_13_6) begin
       if (_T_8491) begin
-        bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_214 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42082,7 +42082,7 @@ end // initial
       bht_bank_rd_data_out_0_215 <= 2'h0;
     end else if (bht_bank_sel_0_13_7) begin
       if (_T_8500) begin
-        bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_215 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42093,7 +42093,7 @@ end // initial
       bht_bank_rd_data_out_0_216 <= 2'h0;
     end else if (bht_bank_sel_0_13_8) begin
       if (_T_8509) begin
-        bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_216 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42104,7 +42104,7 @@ end // initial
       bht_bank_rd_data_out_0_217 <= 2'h0;
     end else if (bht_bank_sel_0_13_9) begin
       if (_T_8518) begin
-        bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_217 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42115,7 +42115,7 @@ end // initial
       bht_bank_rd_data_out_0_218 <= 2'h0;
     end else if (bht_bank_sel_0_13_10) begin
       if (_T_8527) begin
-        bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_218 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42126,7 +42126,7 @@ end // initial
       bht_bank_rd_data_out_0_219 <= 2'h0;
     end else if (bht_bank_sel_0_13_11) begin
       if (_T_8536) begin
-        bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_219 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42137,7 +42137,7 @@ end // initial
       bht_bank_rd_data_out_0_220 <= 2'h0;
     end else if (bht_bank_sel_0_13_12) begin
       if (_T_8545) begin
-        bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_220 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42148,7 +42148,7 @@ end // initial
       bht_bank_rd_data_out_0_221 <= 2'h0;
     end else if (bht_bank_sel_0_13_13) begin
       if (_T_8554) begin
-        bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_221 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42159,7 +42159,7 @@ end // initial
       bht_bank_rd_data_out_0_222 <= 2'h0;
     end else if (bht_bank_sel_0_13_14) begin
       if (_T_8563) begin
-        bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_222 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42170,7 +42170,7 @@ end // initial
       bht_bank_rd_data_out_0_223 <= 2'h0;
     end else if (bht_bank_sel_0_13_15) begin
       if (_T_8572) begin
-        bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_223 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42181,7 +42181,7 @@ end // initial
       bht_bank_rd_data_out_0_224 <= 2'h0;
     end else if (bht_bank_sel_0_14_0) begin
       if (_T_8581) begin
-        bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_224 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42192,7 +42192,7 @@ end // initial
       bht_bank_rd_data_out_0_225 <= 2'h0;
     end else if (bht_bank_sel_0_14_1) begin
       if (_T_8590) begin
-        bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_225 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42203,7 +42203,7 @@ end // initial
       bht_bank_rd_data_out_0_226 <= 2'h0;
     end else if (bht_bank_sel_0_14_2) begin
       if (_T_8599) begin
-        bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_226 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42214,7 +42214,7 @@ end // initial
       bht_bank_rd_data_out_0_227 <= 2'h0;
     end else if (bht_bank_sel_0_14_3) begin
       if (_T_8608) begin
-        bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_227 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42225,7 +42225,7 @@ end // initial
       bht_bank_rd_data_out_0_228 <= 2'h0;
     end else if (bht_bank_sel_0_14_4) begin
       if (_T_8617) begin
-        bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_228 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42236,7 +42236,7 @@ end // initial
       bht_bank_rd_data_out_0_229 <= 2'h0;
     end else if (bht_bank_sel_0_14_5) begin
       if (_T_8626) begin
-        bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_229 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42247,7 +42247,7 @@ end // initial
       bht_bank_rd_data_out_0_230 <= 2'h0;
     end else if (bht_bank_sel_0_14_6) begin
       if (_T_8635) begin
-        bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_230 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42258,7 +42258,7 @@ end // initial
       bht_bank_rd_data_out_0_231 <= 2'h0;
     end else if (bht_bank_sel_0_14_7) begin
       if (_T_8644) begin
-        bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_231 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42269,7 +42269,7 @@ end // initial
       bht_bank_rd_data_out_0_232 <= 2'h0;
     end else if (bht_bank_sel_0_14_8) begin
       if (_T_8653) begin
-        bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_232 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42280,7 +42280,7 @@ end // initial
       bht_bank_rd_data_out_0_233 <= 2'h0;
     end else if (bht_bank_sel_0_14_9) begin
       if (_T_8662) begin
-        bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_233 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42291,7 +42291,7 @@ end // initial
       bht_bank_rd_data_out_0_234 <= 2'h0;
     end else if (bht_bank_sel_0_14_10) begin
       if (_T_8671) begin
-        bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_234 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42302,7 +42302,7 @@ end // initial
       bht_bank_rd_data_out_0_235 <= 2'h0;
     end else if (bht_bank_sel_0_14_11) begin
       if (_T_8680) begin
-        bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_235 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42313,7 +42313,7 @@ end // initial
       bht_bank_rd_data_out_0_236 <= 2'h0;
     end else if (bht_bank_sel_0_14_12) begin
       if (_T_8689) begin
-        bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_236 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42324,7 +42324,7 @@ end // initial
       bht_bank_rd_data_out_0_237 <= 2'h0;
     end else if (bht_bank_sel_0_14_13) begin
       if (_T_8698) begin
-        bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_237 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42335,7 +42335,7 @@ end // initial
       bht_bank_rd_data_out_0_238 <= 2'h0;
     end else if (bht_bank_sel_0_14_14) begin
       if (_T_8707) begin
-        bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_238 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42346,7 +42346,7 @@ end // initial
       bht_bank_rd_data_out_0_239 <= 2'h0;
     end else if (bht_bank_sel_0_14_15) begin
       if (_T_8716) begin
-        bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_239 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42357,7 +42357,7 @@ end // initial
       bht_bank_rd_data_out_0_240 <= 2'h0;
     end else if (bht_bank_sel_0_15_0) begin
       if (_T_8725) begin
-        bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_240 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42368,7 +42368,7 @@ end // initial
       bht_bank_rd_data_out_0_241 <= 2'h0;
     end else if (bht_bank_sel_0_15_1) begin
       if (_T_8734) begin
-        bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_241 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42379,7 +42379,7 @@ end // initial
       bht_bank_rd_data_out_0_242 <= 2'h0;
     end else if (bht_bank_sel_0_15_2) begin
       if (_T_8743) begin
-        bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_242 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42390,7 +42390,7 @@ end // initial
       bht_bank_rd_data_out_0_243 <= 2'h0;
     end else if (bht_bank_sel_0_15_3) begin
       if (_T_8752) begin
-        bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_243 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42401,7 +42401,7 @@ end // initial
       bht_bank_rd_data_out_0_244 <= 2'h0;
     end else if (bht_bank_sel_0_15_4) begin
       if (_T_8761) begin
-        bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_244 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42412,7 +42412,7 @@ end // initial
       bht_bank_rd_data_out_0_245 <= 2'h0;
     end else if (bht_bank_sel_0_15_5) begin
       if (_T_8770) begin
-        bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_245 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42423,7 +42423,7 @@ end // initial
       bht_bank_rd_data_out_0_246 <= 2'h0;
     end else if (bht_bank_sel_0_15_6) begin
       if (_T_8779) begin
-        bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_246 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42434,7 +42434,7 @@ end // initial
       bht_bank_rd_data_out_0_247 <= 2'h0;
     end else if (bht_bank_sel_0_15_7) begin
       if (_T_8788) begin
-        bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_247 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42445,7 +42445,7 @@ end // initial
       bht_bank_rd_data_out_0_248 <= 2'h0;
     end else if (bht_bank_sel_0_15_8) begin
       if (_T_8797) begin
-        bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_248 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42456,7 +42456,7 @@ end // initial
       bht_bank_rd_data_out_0_249 <= 2'h0;
     end else if (bht_bank_sel_0_15_9) begin
       if (_T_8806) begin
-        bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_249 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42467,7 +42467,7 @@ end // initial
       bht_bank_rd_data_out_0_250 <= 2'h0;
     end else if (bht_bank_sel_0_15_10) begin
       if (_T_8815) begin
-        bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_250 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42478,7 +42478,7 @@ end // initial
       bht_bank_rd_data_out_0_251 <= 2'h0;
     end else if (bht_bank_sel_0_15_11) begin
       if (_T_8824) begin
-        bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_251 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42489,7 +42489,7 @@ end // initial
       bht_bank_rd_data_out_0_252 <= 2'h0;
     end else if (bht_bank_sel_0_15_12) begin
       if (_T_8833) begin
-        bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_252 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42500,7 +42500,7 @@ end // initial
       bht_bank_rd_data_out_0_253 <= 2'h0;
     end else if (bht_bank_sel_0_15_13) begin
       if (_T_8842) begin
-        bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_253 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42511,7 +42511,7 @@ end // initial
       bht_bank_rd_data_out_0_254 <= 2'h0;
     end else if (bht_bank_sel_0_15_14) begin
       if (_T_8851) begin
-        bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_254 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42522,7 +42522,7 @@ end // initial
       bht_bank_rd_data_out_0_255 <= 2'h0;
     end else if (bht_bank_sel_0_15_15) begin
       if (_T_8860) begin
-        bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_255 <= io_exu_mp_pkt_bits_hist;
       end
@@ -43161,14 +43161,14 @@ module el2_ifu_aln_ctl(
   output        io_ifu_pmu_instr_aligned,
   output [15:0] io_ifu_i0_cinst,
   output        io_i0_brp_valid,
-  output [11:0] io_i0_brp_toffset,
-  output [1:0]  io_i0_brp_hist,
-  output        io_i0_brp_br_error,
-  output        io_i0_brp_br_start_error,
-  output        io_i0_brp_bank,
-  output [30:0] io_i0_brp_prett,
-  output        io_i0_brp_way,
-  output        io_i0_brp_ret
+  output [11:0] io_i0_brp_bits_toffset,
+  output [1:0]  io_i0_brp_bits_hist,
+  output        io_i0_brp_bits_br_error,
+  output        io_i0_brp_bits_br_start_error,
+  output        io_i0_brp_bits_bank,
+  output [30:0] io_i0_brp_bits_prett,
+  output        io_i0_brp_bits_way,
+  output        io_i0_brp_bits_ret
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
@@ -43607,24 +43607,24 @@ module el2_ifu_aln_ctl(
   wire  _T_721 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 378:58]
   wire  _T_722 = _T_719 | _T_721; // @[el2_ifu_aln_ctl.scala 378:47]
   wire  _T_726 = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:100]
-  wire  _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:29]
-  wire  _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:55]
+  wire  _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:34]
+  wire  _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:60]
   wire  _T_734 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 382:29]
   wire  _T_736 = first4B & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 382:55]
   wire  i0_brp_pc4 = _T_734 | _T_736; // @[el2_ifu_aln_ctl.scala 382:44]
-  wire  _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:33]
-  wire  _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:34]
-  wire  _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:62]
-  wire  _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:51]
+  wire  _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:38]
+  wire  _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:39]
+  wire  _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:67]
+  wire  _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:56]
   wire  _T_749 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 387:14]
   wire  _T_751 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42]
   wire  _T_752 = _T_749 | _T_751; // @[el2_ifu_aln_ctl.scala 387:31]
   wire  i0_ends_f1 = first4B & _T_515; // @[el2_ifu_aln_ctl.scala 389:28]
-  wire  _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42]
-  wire  _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:56]
-  wire  _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89]
-  wire  _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:87]
-  wire  _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:101]
+  wire  _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:47]
+  wire  _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:61]
+  wire  _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:94]
+  wire  _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:92]
+  wire  _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:106]
   rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -43717,14 +43717,14 @@ module el2_ifu_aln_ctl(
   assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_785; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28]
   assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 61:19 el2_ifu_aln_ctl.scala 346:19]
   assign io_i0_brp_valid = _T_722 | _T_726; // @[el2_ifu_aln_ctl.scala 378:19]
-  assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:21]
-  assign io_i0_brp_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:18]
-  assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22]
-  assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29]
-  assign io_i0_brp_bank = _T_738 ? f0pc[0] : secondpc[0]; // @[el2_ifu_aln_ctl.scala 396:29]
-  assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19]
-  assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17]
-  assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17]
+  assign io_i0_brp_bits_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:26]
+  assign io_i0_brp_bits_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:23]
+  assign io_i0_brp_bits_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:27]
+  assign io_i0_brp_bits_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:34]
+  assign io_i0_brp_bits_bank = _T_738 ? f0pc[0] : secondpc[0]; // @[el2_ifu_aln_ctl.scala 396:34]
+  assign io_i0_brp_bits_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:24]
+  assign io_i0_brp_bits_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:22]
+  assign io_i0_brp_bits_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:22]
   assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
   assign rvclkhdr_io_en = _T_354 | _T_358; // @[el2_lib.scala 511:17]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
@@ -44475,14 +44475,14 @@ module el2_ifu(
   output        io_ifu_i0_pc4,
   output        io_ifu_miss_state_idle,
   output        io_i0_brp_valid,
-  output [11:0] io_i0_brp_toffset,
-  output [1:0]  io_i0_brp_hist,
-  output        io_i0_brp_br_error,
-  output        io_i0_brp_br_start_error,
-  output        io_i0_brp_bank,
-  output [30:0] io_i0_brp_prett,
-  output        io_i0_brp_way,
-  output        io_i0_brp_ret,
+  output [11:0] io_i0_brp_bits_toffset,
+  output [1:0]  io_i0_brp_bits_hist,
+  output        io_i0_brp_bits_br_error,
+  output        io_i0_brp_bits_br_start_error,
+  output        io_i0_brp_bits_bank,
+  output [30:0] io_i0_brp_bits_prett,
+  output        io_i0_brp_bits_way,
+  output        io_i0_brp_bits_ret,
   output [7:0]  io_ifu_i0_bp_index,
   output [7:0]  io_ifu_i0_bp_fghr,
   output [4:0]  io_ifu_i0_bp_btag,
@@ -44505,11 +44505,11 @@ module el2_ifu(
   input  [7:0]  io_exu_mp_index,
   input  [4:0]  io_exu_mp_btag,
   input         io_dec_tlu_br0_r_pkt_valid,
-  input  [1:0]  io_dec_tlu_br0_r_pkt_hist,
-  input         io_dec_tlu_br0_r_pkt_br_error,
-  input         io_dec_tlu_br0_r_pkt_br_start_error,
-  input         io_dec_tlu_br0_r_pkt_way,
-  input         io_dec_tlu_br0_r_pkt_middle,
+  input  [1:0]  io_dec_tlu_br0_r_pkt_bits_hist,
+  input         io_dec_tlu_br0_r_pkt_bits_br_error,
+  input         io_dec_tlu_br0_r_pkt_bits_br_start_error,
+  input         io_dec_tlu_br0_r_pkt_bits_way,
+  input         io_dec_tlu_br0_r_pkt_bits_middle,
   input  [7:0]  io_exu_i0_br_fghr_r,
   input  [7:0]  io_exu_i0_br_index_r,
   input         io_dec_tlu_flush_lower_wb,
@@ -44628,11 +44628,11 @@ module el2_ifu(
   wire [30:0] bp_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 147:25]
   wire  bp_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 147:25]
   wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 147:25]
-  wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 147:25]
-  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 147:25]
-  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 147:25]
-  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 147:25]
-  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 147:25]
+  wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 147:25]
+  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 147:25]
+  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 147:25]
+  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 147:25]
+  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 147:25]
   wire [7:0] bp_ctl_ch_io_exu_i0_br_fghr_r; // @[el2_ifu.scala 147:25]
   wire [7:0] bp_ctl_ch_io_exu_i0_br_index_r; // @[el2_ifu.scala 147:25]
   wire  bp_ctl_ch_io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 147:25]
@@ -44703,14 +44703,14 @@ module el2_ifu(
   wire  aln_ctl_ch_io_ifu_pmu_instr_aligned; // @[el2_ifu.scala 148:26]
   wire [15:0] aln_ctl_ch_io_ifu_i0_cinst; // @[el2_ifu.scala 148:26]
   wire  aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 148:26]
-  wire [11:0] aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 148:26]
-  wire [1:0] aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 148:26]
-  wire  aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 148:26]
-  wire  aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 148:26]
-  wire  aln_ctl_ch_io_i0_brp_bank; // @[el2_ifu.scala 148:26]
-  wire [30:0] aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 148:26]
-  wire  aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 148:26]
-  wire  aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 148:26]
+  wire [11:0] aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 148:26]
+  wire [1:0] aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 148:26]
+  wire  aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 148:26]
+  wire  aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 148:26]
+  wire  aln_ctl_ch_io_i0_brp_bits_bank; // @[el2_ifu.scala 148:26]
+  wire [30:0] aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 148:26]
+  wire  aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 148:26]
+  wire  aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 148:26]
   wire  ifc_ctl_ch_clock; // @[el2_ifu.scala 149:26]
   wire  ifc_ctl_ch_reset; // @[el2_ifu.scala 149:26]
   wire  ifc_ctl_ch_io_free_clk; // @[el2_ifu.scala 149:26]
@@ -44847,11 +44847,11 @@ module el2_ifu(
     .io_ifc_fetch_addr_f(bp_ctl_ch_io_ifc_fetch_addr_f),
     .io_ifc_fetch_req_f(bp_ctl_ch_io_ifc_fetch_req_f),
     .io_dec_tlu_br0_r_pkt_valid(bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid),
-    .io_dec_tlu_br0_r_pkt_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist),
-    .io_dec_tlu_br0_r_pkt_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error),
-    .io_dec_tlu_br0_r_pkt_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error),
-    .io_dec_tlu_br0_r_pkt_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_way),
-    .io_dec_tlu_br0_r_pkt_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle),
+    .io_dec_tlu_br0_r_pkt_bits_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist),
+    .io_dec_tlu_br0_r_pkt_bits_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error),
+    .io_dec_tlu_br0_r_pkt_bits_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error),
+    .io_dec_tlu_br0_r_pkt_bits_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way),
+    .io_dec_tlu_br0_r_pkt_bits_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle),
     .io_exu_i0_br_fghr_r(bp_ctl_ch_io_exu_i0_br_fghr_r),
     .io_exu_i0_br_index_r(bp_ctl_ch_io_exu_i0_br_index_r),
     .io_dec_tlu_flush_lower_wb(bp_ctl_ch_io_dec_tlu_flush_lower_wb),
@@ -44924,14 +44924,14 @@ module el2_ifu(
     .io_ifu_pmu_instr_aligned(aln_ctl_ch_io_ifu_pmu_instr_aligned),
     .io_ifu_i0_cinst(aln_ctl_ch_io_ifu_i0_cinst),
     .io_i0_brp_valid(aln_ctl_ch_io_i0_brp_valid),
-    .io_i0_brp_toffset(aln_ctl_ch_io_i0_brp_toffset),
-    .io_i0_brp_hist(aln_ctl_ch_io_i0_brp_hist),
-    .io_i0_brp_br_error(aln_ctl_ch_io_i0_brp_br_error),
-    .io_i0_brp_br_start_error(aln_ctl_ch_io_i0_brp_br_start_error),
-    .io_i0_brp_bank(aln_ctl_ch_io_i0_brp_bank),
-    .io_i0_brp_prett(aln_ctl_ch_io_i0_brp_prett),
-    .io_i0_brp_way(aln_ctl_ch_io_i0_brp_way),
-    .io_i0_brp_ret(aln_ctl_ch_io_i0_brp_ret)
+    .io_i0_brp_bits_toffset(aln_ctl_ch_io_i0_brp_bits_toffset),
+    .io_i0_brp_bits_hist(aln_ctl_ch_io_i0_brp_bits_hist),
+    .io_i0_brp_bits_br_error(aln_ctl_ch_io_i0_brp_bits_br_error),
+    .io_i0_brp_bits_br_start_error(aln_ctl_ch_io_i0_brp_bits_br_start_error),
+    .io_i0_brp_bits_bank(aln_ctl_ch_io_i0_brp_bits_bank),
+    .io_i0_brp_bits_prett(aln_ctl_ch_io_i0_brp_bits_prett),
+    .io_i0_brp_bits_way(aln_ctl_ch_io_i0_brp_bits_way),
+    .io_i0_brp_bits_ret(aln_ctl_ch_io_i0_brp_bits_ret)
   );
   el2_ifu_ifc_ctl ifc_ctl_ch ( // @[el2_ifu.scala 149:26]
     .clock(ifc_ctl_ch_clock),
@@ -45036,14 +45036,14 @@ module el2_ifu(
   assign io_ifu_i0_pc4 = aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 328:17]
   assign io_ifu_miss_state_idle = mem_ctl_ch_io_ifu_miss_state_idle; // @[el2_ifu.scala 329:26]
   assign io_i0_brp_valid = aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_toffset = aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_hist = aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_br_error = aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_br_start_error = aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_bank = aln_ctl_ch_io_i0_brp_bank; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_prett = aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_way = aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_ret = aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_toffset = aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_hist = aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_br_error = aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_br_start_error = aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_bank = aln_ctl_ch_io_i0_brp_bits_bank; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_prett = aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_way = aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_ret = aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 331:13]
   assign io_ifu_i0_bp_index = aln_ctl_ch_io_ifu_i0_bp_index; // @[el2_ifu.scala 332:22]
   assign io_ifu_i0_bp_fghr = aln_ctl_ch_io_ifu_i0_bp_fghr; // @[el2_ifu.scala 333:21]
   assign io_ifu_i0_bp_btag = aln_ctl_ch_io_ifu_i0_bp_btag; // @[el2_ifu.scala 334:21]
@@ -45104,11 +45104,11 @@ module el2_ifu(
   assign bp_ctl_ch_io_ifc_fetch_addr_f = ifc_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 196:33]
   assign bp_ctl_ch_io_ifc_fetch_req_f = ifc_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 197:32]
   assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid = io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist = io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error = io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error = io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_way = io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle = io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist = io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error = io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error = io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way = io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle = io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 198:34]
   assign bp_ctl_ch_io_exu_i0_br_fghr_r = io_exu_i0_br_fghr_r; // @[el2_ifu.scala 199:33]
   assign bp_ctl_ch_io_exu_i0_br_index_r = io_exu_i0_br_index_r; // @[el2_ifu.scala 200:34]
   assign bp_ctl_ch_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 201:39]
diff --git a/el2_ifu_aln_ctl.fir b/el2_ifu_aln_ctl.fir
index cedffb10..04f9b018 100644
--- a/el2_ifu_aln_ctl.fir
+++ b/el2_ifu_aln_ctl.fir
@@ -2284,7 +2284,7 @@ circuit el2_ifu_aln_ctl :
   module el2_ifu_aln_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}
+    output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}
     
     io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19]
     io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18]
diff --git a/el2_swerv_wrapper.fir b/el2_swerv_wrapper.fir
index 2fe6a999..d10124de 100644
--- a/el2_swerv_wrapper.fir
+++ b/el2_swerv_wrapper.fir
@@ -29076,7 +29076,7 @@ circuit el2_swerv_wrapper :
   module el2_ifu_bp_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt}
+    output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>, test : UInt}
     
     wire leak_one_f : UInt<1>
     leak_one_f <= UInt<1>("h00")
@@ -29103,10 +29103,10 @@ circuit el2_swerv_wrapper :
     dec_tlu_way_wb <= UInt<1>("h00")
     node _T = eq(leak_one_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 72:51]
     node exu_mp_valid = and(io.exu_mp_pkt.bits.misp, _T) @[el2_ifu_bp_ctl.scala 72:49]
-    node _T_1 = or(io.dec_tlu_br0_r_pkt.br_start_error, io.dec_tlu_br0_r_pkt.br_error) @[el2_ifu_bp_ctl.scala 94:50]
+    node _T_1 = or(io.dec_tlu_br0_r_pkt.bits.br_start_error, io.dec_tlu_br0_r_pkt.bits.br_error) @[el2_ifu_bp_ctl.scala 94:50]
     dec_tlu_error_wb <= _T_1 @[el2_ifu_bp_ctl.scala 94:20]
     btb_error_addr_wb <= io.exu_i0_br_index_r @[el2_ifu_bp_ctl.scala 95:21]
-    dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.way @[el2_ifu_bp_ctl.scala 96:18]
+    dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu_bp_ctl.scala 96:18]
     node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 191:13]
     node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 191:51]
     node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 191:47]
@@ -29913,8 +29913,8 @@ circuit el2_swerv_wrapper :
     node bht_wr_en0 = and(_T_556, _T_558) @[el2_ifu_bp_ctl.scala 408:84]
     node _T_559 = bits(io.dec_tlu_br0_r_pkt.valid, 0, 0) @[Bitwise.scala 72:15]
     node _T_560 = mux(_T_559, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_561 = not(io.dec_tlu_br0_r_pkt.middle) @[el2_ifu_bp_ctl.scala 409:75]
-    node _T_562 = cat(io.dec_tlu_br0_r_pkt.middle, _T_561) @[Cat.scala 29:58]
+    node _T_561 = not(io.dec_tlu_br0_r_pkt.bits.middle) @[el2_ifu_bp_ctl.scala 409:75]
+    node _T_562 = cat(io.dec_tlu_br0_r_pkt.bits.middle, _T_561) @[Cat.scala 29:58]
     node bht_wr_en2 = and(_T_560, _T_562) @[el2_ifu_bp_ctl.scala 409:46]
     node _T_563 = cat(io.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58]
     node _T_564 = bits(_T_563, 9, 2) @[el2_lib.scala 196:16]
@@ -40254,7 +40254,7 @@ circuit el2_swerv_wrapper :
     node _T_6565 = and(_T_6562, _T_6564) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6566 = or(_T_6565, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6567 = bits(_T_6566, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_0 = mux(_T_6567, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6568 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6569 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6570 = eq(_T_6569, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40264,7 +40264,7 @@ circuit el2_swerv_wrapper :
     node _T_6574 = and(_T_6571, _T_6573) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6575 = or(_T_6574, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6576 = bits(_T_6575, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_1 = mux(_T_6576, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6577 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6578 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6579 = eq(_T_6578, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40274,7 +40274,7 @@ circuit el2_swerv_wrapper :
     node _T_6583 = and(_T_6580, _T_6582) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6584 = or(_T_6583, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6585 = bits(_T_6584, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_2 = mux(_T_6585, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6586 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6587 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6588 = eq(_T_6587, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40284,7 +40284,7 @@ circuit el2_swerv_wrapper :
     node _T_6592 = and(_T_6589, _T_6591) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6593 = or(_T_6592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6594 = bits(_T_6593, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_3 = mux(_T_6594, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6595 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6596 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6597 = eq(_T_6596, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40294,7 +40294,7 @@ circuit el2_swerv_wrapper :
     node _T_6601 = and(_T_6598, _T_6600) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6602 = or(_T_6601, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6603 = bits(_T_6602, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_4 = mux(_T_6603, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6604 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6605 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6606 = eq(_T_6605, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40304,7 +40304,7 @@ circuit el2_swerv_wrapper :
     node _T_6610 = and(_T_6607, _T_6609) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6611 = or(_T_6610, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6612 = bits(_T_6611, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_5 = mux(_T_6612, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6613 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6614 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6615 = eq(_T_6614, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40314,7 +40314,7 @@ circuit el2_swerv_wrapper :
     node _T_6619 = and(_T_6616, _T_6618) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6620 = or(_T_6619, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6621 = bits(_T_6620, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_6 = mux(_T_6621, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6622 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6623 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6624 = eq(_T_6623, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40324,7 +40324,7 @@ circuit el2_swerv_wrapper :
     node _T_6628 = and(_T_6625, _T_6627) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6629 = or(_T_6628, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6630 = bits(_T_6629, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_7 = mux(_T_6630, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6631 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6632 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6633 = eq(_T_6632, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40334,7 +40334,7 @@ circuit el2_swerv_wrapper :
     node _T_6637 = and(_T_6634, _T_6636) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6638 = or(_T_6637, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6639 = bits(_T_6638, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_8 = mux(_T_6639, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6640 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6641 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6642 = eq(_T_6641, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40344,7 +40344,7 @@ circuit el2_swerv_wrapper :
     node _T_6646 = and(_T_6643, _T_6645) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6647 = or(_T_6646, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6648 = bits(_T_6647, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_9 = mux(_T_6648, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6649 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6650 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6651 = eq(_T_6650, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40354,7 +40354,7 @@ circuit el2_swerv_wrapper :
     node _T_6655 = and(_T_6652, _T_6654) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6656 = or(_T_6655, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6657 = bits(_T_6656, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_10 = mux(_T_6657, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6658 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6659 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6660 = eq(_T_6659, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40364,7 +40364,7 @@ circuit el2_swerv_wrapper :
     node _T_6664 = and(_T_6661, _T_6663) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6665 = or(_T_6664, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6666 = bits(_T_6665, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_11 = mux(_T_6666, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6667 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6668 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6669 = eq(_T_6668, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40374,7 +40374,7 @@ circuit el2_swerv_wrapper :
     node _T_6673 = and(_T_6670, _T_6672) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6674 = or(_T_6673, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6675 = bits(_T_6674, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_12 = mux(_T_6675, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6676 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6677 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6678 = eq(_T_6677, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40384,7 +40384,7 @@ circuit el2_swerv_wrapper :
     node _T_6682 = and(_T_6679, _T_6681) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6683 = or(_T_6682, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6684 = bits(_T_6683, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_13 = mux(_T_6684, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6685 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6686 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6687 = eq(_T_6686, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40394,7 +40394,7 @@ circuit el2_swerv_wrapper :
     node _T_6691 = and(_T_6688, _T_6690) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6692 = or(_T_6691, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6693 = bits(_T_6692, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_14 = mux(_T_6693, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6694 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6695 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6696 = eq(_T_6695, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40404,7 +40404,7 @@ circuit el2_swerv_wrapper :
     node _T_6700 = and(_T_6697, _T_6699) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6701 = or(_T_6700, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6702 = bits(_T_6701, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_0_15 = mux(_T_6702, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6703 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6704 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6705 = eq(_T_6704, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40414,7 +40414,7 @@ circuit el2_swerv_wrapper :
     node _T_6709 = and(_T_6706, _T_6708) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6710 = or(_T_6709, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6711 = bits(_T_6710, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_0 = mux(_T_6711, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6712 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6713 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6714 = eq(_T_6713, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40424,7 +40424,7 @@ circuit el2_swerv_wrapper :
     node _T_6718 = and(_T_6715, _T_6717) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6719 = or(_T_6718, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6720 = bits(_T_6719, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_1 = mux(_T_6720, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6721 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6722 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6723 = eq(_T_6722, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40434,7 +40434,7 @@ circuit el2_swerv_wrapper :
     node _T_6727 = and(_T_6724, _T_6726) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6728 = or(_T_6727, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6729 = bits(_T_6728, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_2 = mux(_T_6729, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6730 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6731 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6732 = eq(_T_6731, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40444,7 +40444,7 @@ circuit el2_swerv_wrapper :
     node _T_6736 = and(_T_6733, _T_6735) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6737 = or(_T_6736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6738 = bits(_T_6737, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_3 = mux(_T_6738, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6739 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6740 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6741 = eq(_T_6740, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40454,7 +40454,7 @@ circuit el2_swerv_wrapper :
     node _T_6745 = and(_T_6742, _T_6744) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6746 = or(_T_6745, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6747 = bits(_T_6746, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_4 = mux(_T_6747, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6748 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6749 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6750 = eq(_T_6749, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40464,7 +40464,7 @@ circuit el2_swerv_wrapper :
     node _T_6754 = and(_T_6751, _T_6753) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6755 = or(_T_6754, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6756 = bits(_T_6755, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_5 = mux(_T_6756, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6757 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6758 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6759 = eq(_T_6758, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40474,7 +40474,7 @@ circuit el2_swerv_wrapper :
     node _T_6763 = and(_T_6760, _T_6762) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6764 = or(_T_6763, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6765 = bits(_T_6764, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_6 = mux(_T_6765, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6766 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6767 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6768 = eq(_T_6767, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40484,7 +40484,7 @@ circuit el2_swerv_wrapper :
     node _T_6772 = and(_T_6769, _T_6771) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6773 = or(_T_6772, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6774 = bits(_T_6773, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_7 = mux(_T_6774, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6775 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6776 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6777 = eq(_T_6776, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40494,7 +40494,7 @@ circuit el2_swerv_wrapper :
     node _T_6781 = and(_T_6778, _T_6780) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6782 = or(_T_6781, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6783 = bits(_T_6782, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_8 = mux(_T_6783, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6784 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6785 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6786 = eq(_T_6785, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40504,7 +40504,7 @@ circuit el2_swerv_wrapper :
     node _T_6790 = and(_T_6787, _T_6789) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6791 = or(_T_6790, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6792 = bits(_T_6791, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_9 = mux(_T_6792, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6793 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6794 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6795 = eq(_T_6794, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40514,7 +40514,7 @@ circuit el2_swerv_wrapper :
     node _T_6799 = and(_T_6796, _T_6798) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6800 = or(_T_6799, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6801 = bits(_T_6800, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_10 = mux(_T_6801, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6802 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6803 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6804 = eq(_T_6803, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40524,7 +40524,7 @@ circuit el2_swerv_wrapper :
     node _T_6808 = and(_T_6805, _T_6807) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6809 = or(_T_6808, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6810 = bits(_T_6809, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_11 = mux(_T_6810, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6811 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6812 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6813 = eq(_T_6812, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40534,7 +40534,7 @@ circuit el2_swerv_wrapper :
     node _T_6817 = and(_T_6814, _T_6816) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6818 = or(_T_6817, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6819 = bits(_T_6818, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_12 = mux(_T_6819, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6820 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6821 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6822 = eq(_T_6821, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40544,7 +40544,7 @@ circuit el2_swerv_wrapper :
     node _T_6826 = and(_T_6823, _T_6825) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6827 = or(_T_6826, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6828 = bits(_T_6827, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_13 = mux(_T_6828, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6829 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6830 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6831 = eq(_T_6830, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40554,7 +40554,7 @@ circuit el2_swerv_wrapper :
     node _T_6835 = and(_T_6832, _T_6834) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6836 = or(_T_6835, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6837 = bits(_T_6836, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_14 = mux(_T_6837, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6838 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6839 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6840 = eq(_T_6839, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40564,7 +40564,7 @@ circuit el2_swerv_wrapper :
     node _T_6844 = and(_T_6841, _T_6843) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6845 = or(_T_6844, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6846 = bits(_T_6845, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_1_15 = mux(_T_6846, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6847 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6848 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6849 = eq(_T_6848, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40574,7 +40574,7 @@ circuit el2_swerv_wrapper :
     node _T_6853 = and(_T_6850, _T_6852) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6854 = or(_T_6853, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6855 = bits(_T_6854, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_0 = mux(_T_6855, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6856 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6857 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6858 = eq(_T_6857, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40584,7 +40584,7 @@ circuit el2_swerv_wrapper :
     node _T_6862 = and(_T_6859, _T_6861) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6863 = or(_T_6862, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6864 = bits(_T_6863, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_1 = mux(_T_6864, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6865 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6866 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6867 = eq(_T_6866, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40594,7 +40594,7 @@ circuit el2_swerv_wrapper :
     node _T_6871 = and(_T_6868, _T_6870) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6872 = or(_T_6871, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6873 = bits(_T_6872, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_2 = mux(_T_6873, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6874 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6875 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6876 = eq(_T_6875, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40604,7 +40604,7 @@ circuit el2_swerv_wrapper :
     node _T_6880 = and(_T_6877, _T_6879) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6881 = or(_T_6880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6882 = bits(_T_6881, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_3 = mux(_T_6882, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6883 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6884 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6885 = eq(_T_6884, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40614,7 +40614,7 @@ circuit el2_swerv_wrapper :
     node _T_6889 = and(_T_6886, _T_6888) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6890 = or(_T_6889, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6891 = bits(_T_6890, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_4 = mux(_T_6891, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6892 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6893 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6894 = eq(_T_6893, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40624,7 +40624,7 @@ circuit el2_swerv_wrapper :
     node _T_6898 = and(_T_6895, _T_6897) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6899 = or(_T_6898, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6900 = bits(_T_6899, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_5 = mux(_T_6900, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6901 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6902 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6903 = eq(_T_6902, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40634,7 +40634,7 @@ circuit el2_swerv_wrapper :
     node _T_6907 = and(_T_6904, _T_6906) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6908 = or(_T_6907, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6909 = bits(_T_6908, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_6 = mux(_T_6909, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6910 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6911 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6912 = eq(_T_6911, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40644,7 +40644,7 @@ circuit el2_swerv_wrapper :
     node _T_6916 = and(_T_6913, _T_6915) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6917 = or(_T_6916, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6918 = bits(_T_6917, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_7 = mux(_T_6918, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6919 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6920 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6921 = eq(_T_6920, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40654,7 +40654,7 @@ circuit el2_swerv_wrapper :
     node _T_6925 = and(_T_6922, _T_6924) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6926 = or(_T_6925, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6927 = bits(_T_6926, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_8 = mux(_T_6927, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6928 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6929 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6930 = eq(_T_6929, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40664,7 +40664,7 @@ circuit el2_swerv_wrapper :
     node _T_6934 = and(_T_6931, _T_6933) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6935 = or(_T_6934, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6936 = bits(_T_6935, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_9 = mux(_T_6936, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6937 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6938 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6939 = eq(_T_6938, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40674,7 +40674,7 @@ circuit el2_swerv_wrapper :
     node _T_6943 = and(_T_6940, _T_6942) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6944 = or(_T_6943, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6945 = bits(_T_6944, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_10 = mux(_T_6945, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6946 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6947 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6948 = eq(_T_6947, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40684,7 +40684,7 @@ circuit el2_swerv_wrapper :
     node _T_6952 = and(_T_6949, _T_6951) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6953 = or(_T_6952, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6954 = bits(_T_6953, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_11 = mux(_T_6954, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6955 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6956 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6957 = eq(_T_6956, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40694,7 +40694,7 @@ circuit el2_swerv_wrapper :
     node _T_6961 = and(_T_6958, _T_6960) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6962 = or(_T_6961, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6963 = bits(_T_6962, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_12 = mux(_T_6963, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6964 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6965 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6966 = eq(_T_6965, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40704,7 +40704,7 @@ circuit el2_swerv_wrapper :
     node _T_6970 = and(_T_6967, _T_6969) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6971 = or(_T_6970, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6972 = bits(_T_6971, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_13 = mux(_T_6972, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6973 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6974 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6975 = eq(_T_6974, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40714,7 +40714,7 @@ circuit el2_swerv_wrapper :
     node _T_6979 = and(_T_6976, _T_6978) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6980 = or(_T_6979, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6981 = bits(_T_6980, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_14 = mux(_T_6981, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6982 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6983 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6984 = eq(_T_6983, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40724,7 +40724,7 @@ circuit el2_swerv_wrapper :
     node _T_6988 = and(_T_6985, _T_6987) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6989 = or(_T_6988, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6990 = bits(_T_6989, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_2_15 = mux(_T_6990, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_6991 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_6992 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_6993 = eq(_T_6992, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40734,7 +40734,7 @@ circuit el2_swerv_wrapper :
     node _T_6997 = and(_T_6994, _T_6996) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_6998 = or(_T_6997, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_6999 = bits(_T_6998, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_0 = mux(_T_6999, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7000 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7001 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7002 = eq(_T_7001, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40744,7 +40744,7 @@ circuit el2_swerv_wrapper :
     node _T_7006 = and(_T_7003, _T_7005) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7007 = or(_T_7006, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7008 = bits(_T_7007, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_1 = mux(_T_7008, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7009 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7010 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7011 = eq(_T_7010, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40754,7 +40754,7 @@ circuit el2_swerv_wrapper :
     node _T_7015 = and(_T_7012, _T_7014) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7016 = or(_T_7015, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7017 = bits(_T_7016, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_2 = mux(_T_7017, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7018 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7019 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7020 = eq(_T_7019, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40764,7 +40764,7 @@ circuit el2_swerv_wrapper :
     node _T_7024 = and(_T_7021, _T_7023) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7025 = or(_T_7024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7026 = bits(_T_7025, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_3 = mux(_T_7026, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7027 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7028 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7029 = eq(_T_7028, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40774,7 +40774,7 @@ circuit el2_swerv_wrapper :
     node _T_7033 = and(_T_7030, _T_7032) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7034 = or(_T_7033, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7035 = bits(_T_7034, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_4 = mux(_T_7035, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7036 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7037 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7038 = eq(_T_7037, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40784,7 +40784,7 @@ circuit el2_swerv_wrapper :
     node _T_7042 = and(_T_7039, _T_7041) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7043 = or(_T_7042, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7044 = bits(_T_7043, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_5 = mux(_T_7044, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7045 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7046 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7047 = eq(_T_7046, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40794,7 +40794,7 @@ circuit el2_swerv_wrapper :
     node _T_7051 = and(_T_7048, _T_7050) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7052 = or(_T_7051, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7053 = bits(_T_7052, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_6 = mux(_T_7053, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7054 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7055 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7056 = eq(_T_7055, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40804,7 +40804,7 @@ circuit el2_swerv_wrapper :
     node _T_7060 = and(_T_7057, _T_7059) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7061 = or(_T_7060, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7062 = bits(_T_7061, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_7 = mux(_T_7062, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7063 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7064 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7065 = eq(_T_7064, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40814,7 +40814,7 @@ circuit el2_swerv_wrapper :
     node _T_7069 = and(_T_7066, _T_7068) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7070 = or(_T_7069, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7071 = bits(_T_7070, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_8 = mux(_T_7071, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7072 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7073 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7074 = eq(_T_7073, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40824,7 +40824,7 @@ circuit el2_swerv_wrapper :
     node _T_7078 = and(_T_7075, _T_7077) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7079 = or(_T_7078, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7080 = bits(_T_7079, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_9 = mux(_T_7080, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7081 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7082 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7083 = eq(_T_7082, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40834,7 +40834,7 @@ circuit el2_swerv_wrapper :
     node _T_7087 = and(_T_7084, _T_7086) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7088 = or(_T_7087, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7089 = bits(_T_7088, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_10 = mux(_T_7089, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7090 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7091 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7092 = eq(_T_7091, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40844,7 +40844,7 @@ circuit el2_swerv_wrapper :
     node _T_7096 = and(_T_7093, _T_7095) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7097 = or(_T_7096, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7098 = bits(_T_7097, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_11 = mux(_T_7098, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7099 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7100 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7101 = eq(_T_7100, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40854,7 +40854,7 @@ circuit el2_swerv_wrapper :
     node _T_7105 = and(_T_7102, _T_7104) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7106 = or(_T_7105, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7107 = bits(_T_7106, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_12 = mux(_T_7107, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7108 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7109 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7110 = eq(_T_7109, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40864,7 +40864,7 @@ circuit el2_swerv_wrapper :
     node _T_7114 = and(_T_7111, _T_7113) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7115 = or(_T_7114, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7116 = bits(_T_7115, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_13 = mux(_T_7116, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7117 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7118 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7119 = eq(_T_7118, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40874,7 +40874,7 @@ circuit el2_swerv_wrapper :
     node _T_7123 = and(_T_7120, _T_7122) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7124 = or(_T_7123, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7125 = bits(_T_7124, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_14 = mux(_T_7125, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7126 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7127 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7128 = eq(_T_7127, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40884,7 +40884,7 @@ circuit el2_swerv_wrapper :
     node _T_7132 = and(_T_7129, _T_7131) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7133 = or(_T_7132, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7134 = bits(_T_7133, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_3_15 = mux(_T_7134, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7135 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7136 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7137 = eq(_T_7136, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40894,7 +40894,7 @@ circuit el2_swerv_wrapper :
     node _T_7141 = and(_T_7138, _T_7140) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7142 = or(_T_7141, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7143 = bits(_T_7142, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_0 = mux(_T_7143, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7144 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7145 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7146 = eq(_T_7145, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40904,7 +40904,7 @@ circuit el2_swerv_wrapper :
     node _T_7150 = and(_T_7147, _T_7149) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7151 = or(_T_7150, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7152 = bits(_T_7151, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_1 = mux(_T_7152, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7153 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7154 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7155 = eq(_T_7154, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40914,7 +40914,7 @@ circuit el2_swerv_wrapper :
     node _T_7159 = and(_T_7156, _T_7158) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7160 = or(_T_7159, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7161 = bits(_T_7160, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_2 = mux(_T_7161, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7162 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7163 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7164 = eq(_T_7163, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40924,7 +40924,7 @@ circuit el2_swerv_wrapper :
     node _T_7168 = and(_T_7165, _T_7167) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7169 = or(_T_7168, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7170 = bits(_T_7169, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_3 = mux(_T_7170, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7171 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7172 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7173 = eq(_T_7172, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40934,7 +40934,7 @@ circuit el2_swerv_wrapper :
     node _T_7177 = and(_T_7174, _T_7176) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7178 = or(_T_7177, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7179 = bits(_T_7178, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_4 = mux(_T_7179, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7180 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7181 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7182 = eq(_T_7181, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40944,7 +40944,7 @@ circuit el2_swerv_wrapper :
     node _T_7186 = and(_T_7183, _T_7185) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7187 = or(_T_7186, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7188 = bits(_T_7187, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_5 = mux(_T_7188, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7189 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7190 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7191 = eq(_T_7190, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40954,7 +40954,7 @@ circuit el2_swerv_wrapper :
     node _T_7195 = and(_T_7192, _T_7194) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7196 = or(_T_7195, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7197 = bits(_T_7196, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_6 = mux(_T_7197, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7198 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7199 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7200 = eq(_T_7199, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40964,7 +40964,7 @@ circuit el2_swerv_wrapper :
     node _T_7204 = and(_T_7201, _T_7203) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7205 = or(_T_7204, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7206 = bits(_T_7205, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_7 = mux(_T_7206, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7207 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7208 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7209 = eq(_T_7208, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40974,7 +40974,7 @@ circuit el2_swerv_wrapper :
     node _T_7213 = and(_T_7210, _T_7212) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7214 = or(_T_7213, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7215 = bits(_T_7214, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_8 = mux(_T_7215, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7216 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7217 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7218 = eq(_T_7217, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40984,7 +40984,7 @@ circuit el2_swerv_wrapper :
     node _T_7222 = and(_T_7219, _T_7221) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7223 = or(_T_7222, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7224 = bits(_T_7223, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_9 = mux(_T_7224, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7225 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7226 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7227 = eq(_T_7226, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -40994,7 +40994,7 @@ circuit el2_swerv_wrapper :
     node _T_7231 = and(_T_7228, _T_7230) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7232 = or(_T_7231, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7233 = bits(_T_7232, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_10 = mux(_T_7233, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7234 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7235 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7236 = eq(_T_7235, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41004,7 +41004,7 @@ circuit el2_swerv_wrapper :
     node _T_7240 = and(_T_7237, _T_7239) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7241 = or(_T_7240, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7242 = bits(_T_7241, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_11 = mux(_T_7242, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7243 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7244 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7245 = eq(_T_7244, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41014,7 +41014,7 @@ circuit el2_swerv_wrapper :
     node _T_7249 = and(_T_7246, _T_7248) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7250 = or(_T_7249, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7251 = bits(_T_7250, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_12 = mux(_T_7251, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7252 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7253 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7254 = eq(_T_7253, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41024,7 +41024,7 @@ circuit el2_swerv_wrapper :
     node _T_7258 = and(_T_7255, _T_7257) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7259 = or(_T_7258, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7260 = bits(_T_7259, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_13 = mux(_T_7260, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7261 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7262 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7263 = eq(_T_7262, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41034,7 +41034,7 @@ circuit el2_swerv_wrapper :
     node _T_7267 = and(_T_7264, _T_7266) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7268 = or(_T_7267, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7269 = bits(_T_7268, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_14 = mux(_T_7269, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7270 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7271 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7272 = eq(_T_7271, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41044,7 +41044,7 @@ circuit el2_swerv_wrapper :
     node _T_7276 = and(_T_7273, _T_7275) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7277 = or(_T_7276, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7278 = bits(_T_7277, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_4_15 = mux(_T_7278, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7279 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7280 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7281 = eq(_T_7280, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41054,7 +41054,7 @@ circuit el2_swerv_wrapper :
     node _T_7285 = and(_T_7282, _T_7284) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7286 = or(_T_7285, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7287 = bits(_T_7286, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_0 = mux(_T_7287, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7288 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7289 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7290 = eq(_T_7289, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41064,7 +41064,7 @@ circuit el2_swerv_wrapper :
     node _T_7294 = and(_T_7291, _T_7293) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7295 = or(_T_7294, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7296 = bits(_T_7295, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_1 = mux(_T_7296, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7297 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7298 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7299 = eq(_T_7298, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41074,7 +41074,7 @@ circuit el2_swerv_wrapper :
     node _T_7303 = and(_T_7300, _T_7302) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7304 = or(_T_7303, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7305 = bits(_T_7304, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_2 = mux(_T_7305, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7306 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7307 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7308 = eq(_T_7307, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41084,7 +41084,7 @@ circuit el2_swerv_wrapper :
     node _T_7312 = and(_T_7309, _T_7311) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7313 = or(_T_7312, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7314 = bits(_T_7313, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_3 = mux(_T_7314, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7315 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7316 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7317 = eq(_T_7316, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41094,7 +41094,7 @@ circuit el2_swerv_wrapper :
     node _T_7321 = and(_T_7318, _T_7320) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7322 = or(_T_7321, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7323 = bits(_T_7322, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_4 = mux(_T_7323, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7324 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7325 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7326 = eq(_T_7325, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41104,7 +41104,7 @@ circuit el2_swerv_wrapper :
     node _T_7330 = and(_T_7327, _T_7329) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7331 = or(_T_7330, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7332 = bits(_T_7331, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_5 = mux(_T_7332, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7333 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7334 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7335 = eq(_T_7334, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41114,7 +41114,7 @@ circuit el2_swerv_wrapper :
     node _T_7339 = and(_T_7336, _T_7338) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7340 = or(_T_7339, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7341 = bits(_T_7340, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_6 = mux(_T_7341, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7342 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7343 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7344 = eq(_T_7343, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41124,7 +41124,7 @@ circuit el2_swerv_wrapper :
     node _T_7348 = and(_T_7345, _T_7347) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7349 = or(_T_7348, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7350 = bits(_T_7349, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_7 = mux(_T_7350, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7351 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7352 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7353 = eq(_T_7352, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41134,7 +41134,7 @@ circuit el2_swerv_wrapper :
     node _T_7357 = and(_T_7354, _T_7356) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7358 = or(_T_7357, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7359 = bits(_T_7358, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_8 = mux(_T_7359, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7360 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7361 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7362 = eq(_T_7361, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41144,7 +41144,7 @@ circuit el2_swerv_wrapper :
     node _T_7366 = and(_T_7363, _T_7365) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7367 = or(_T_7366, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7368 = bits(_T_7367, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_9 = mux(_T_7368, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7369 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7370 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7371 = eq(_T_7370, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41154,7 +41154,7 @@ circuit el2_swerv_wrapper :
     node _T_7375 = and(_T_7372, _T_7374) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7376 = or(_T_7375, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7377 = bits(_T_7376, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_10 = mux(_T_7377, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7378 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7379 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7380 = eq(_T_7379, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41164,7 +41164,7 @@ circuit el2_swerv_wrapper :
     node _T_7384 = and(_T_7381, _T_7383) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7385 = or(_T_7384, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7386 = bits(_T_7385, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_11 = mux(_T_7386, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7387 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7388 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7389 = eq(_T_7388, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41174,7 +41174,7 @@ circuit el2_swerv_wrapper :
     node _T_7393 = and(_T_7390, _T_7392) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7394 = or(_T_7393, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7395 = bits(_T_7394, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_12 = mux(_T_7395, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7396 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7397 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7398 = eq(_T_7397, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41184,7 +41184,7 @@ circuit el2_swerv_wrapper :
     node _T_7402 = and(_T_7399, _T_7401) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7403 = or(_T_7402, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7404 = bits(_T_7403, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_13 = mux(_T_7404, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7405 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7406 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7407 = eq(_T_7406, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41194,7 +41194,7 @@ circuit el2_swerv_wrapper :
     node _T_7411 = and(_T_7408, _T_7410) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7412 = or(_T_7411, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7413 = bits(_T_7412, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_14 = mux(_T_7413, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7414 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7415 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7416 = eq(_T_7415, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41204,7 +41204,7 @@ circuit el2_swerv_wrapper :
     node _T_7420 = and(_T_7417, _T_7419) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7421 = or(_T_7420, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7422 = bits(_T_7421, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_5_15 = mux(_T_7422, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7423 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7424 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7425 = eq(_T_7424, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41214,7 +41214,7 @@ circuit el2_swerv_wrapper :
     node _T_7429 = and(_T_7426, _T_7428) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7430 = or(_T_7429, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7431 = bits(_T_7430, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_0 = mux(_T_7431, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7432 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7433 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7434 = eq(_T_7433, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41224,7 +41224,7 @@ circuit el2_swerv_wrapper :
     node _T_7438 = and(_T_7435, _T_7437) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7439 = or(_T_7438, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7440 = bits(_T_7439, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_1 = mux(_T_7440, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7441 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7442 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7443 = eq(_T_7442, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41234,7 +41234,7 @@ circuit el2_swerv_wrapper :
     node _T_7447 = and(_T_7444, _T_7446) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7448 = or(_T_7447, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7449 = bits(_T_7448, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_2 = mux(_T_7449, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7450 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7451 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7452 = eq(_T_7451, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41244,7 +41244,7 @@ circuit el2_swerv_wrapper :
     node _T_7456 = and(_T_7453, _T_7455) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7457 = or(_T_7456, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7458 = bits(_T_7457, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_3 = mux(_T_7458, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7459 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7460 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7461 = eq(_T_7460, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41254,7 +41254,7 @@ circuit el2_swerv_wrapper :
     node _T_7465 = and(_T_7462, _T_7464) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7466 = or(_T_7465, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7467 = bits(_T_7466, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_4 = mux(_T_7467, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7468 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7469 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7470 = eq(_T_7469, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41264,7 +41264,7 @@ circuit el2_swerv_wrapper :
     node _T_7474 = and(_T_7471, _T_7473) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7475 = or(_T_7474, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7476 = bits(_T_7475, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_5 = mux(_T_7476, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7477 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7478 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7479 = eq(_T_7478, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41274,7 +41274,7 @@ circuit el2_swerv_wrapper :
     node _T_7483 = and(_T_7480, _T_7482) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7484 = or(_T_7483, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7485 = bits(_T_7484, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_6 = mux(_T_7485, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7486 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7487 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7488 = eq(_T_7487, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41284,7 +41284,7 @@ circuit el2_swerv_wrapper :
     node _T_7492 = and(_T_7489, _T_7491) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7493 = or(_T_7492, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7494 = bits(_T_7493, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_7 = mux(_T_7494, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7495 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7496 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7497 = eq(_T_7496, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41294,7 +41294,7 @@ circuit el2_swerv_wrapper :
     node _T_7501 = and(_T_7498, _T_7500) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7502 = or(_T_7501, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7503 = bits(_T_7502, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_8 = mux(_T_7503, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7504 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7505 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7506 = eq(_T_7505, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41304,7 +41304,7 @@ circuit el2_swerv_wrapper :
     node _T_7510 = and(_T_7507, _T_7509) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7511 = or(_T_7510, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7512 = bits(_T_7511, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_9 = mux(_T_7512, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7513 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7514 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7515 = eq(_T_7514, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41314,7 +41314,7 @@ circuit el2_swerv_wrapper :
     node _T_7519 = and(_T_7516, _T_7518) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7520 = or(_T_7519, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7521 = bits(_T_7520, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_10 = mux(_T_7521, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7522 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7523 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7524 = eq(_T_7523, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41324,7 +41324,7 @@ circuit el2_swerv_wrapper :
     node _T_7528 = and(_T_7525, _T_7527) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7529 = or(_T_7528, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7530 = bits(_T_7529, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_11 = mux(_T_7530, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7531 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7532 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7533 = eq(_T_7532, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41334,7 +41334,7 @@ circuit el2_swerv_wrapper :
     node _T_7537 = and(_T_7534, _T_7536) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7538 = or(_T_7537, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7539 = bits(_T_7538, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_12 = mux(_T_7539, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7540 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7541 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7542 = eq(_T_7541, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41344,7 +41344,7 @@ circuit el2_swerv_wrapper :
     node _T_7546 = and(_T_7543, _T_7545) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7547 = or(_T_7546, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7548 = bits(_T_7547, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_13 = mux(_T_7548, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7549 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7550 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7551 = eq(_T_7550, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41354,7 +41354,7 @@ circuit el2_swerv_wrapper :
     node _T_7555 = and(_T_7552, _T_7554) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7556 = or(_T_7555, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7557 = bits(_T_7556, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_14 = mux(_T_7557, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7558 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7559 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7560 = eq(_T_7559, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41364,7 +41364,7 @@ circuit el2_swerv_wrapper :
     node _T_7564 = and(_T_7561, _T_7563) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7565 = or(_T_7564, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7566 = bits(_T_7565, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_6_15 = mux(_T_7566, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7567 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7568 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7569 = eq(_T_7568, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41374,7 +41374,7 @@ circuit el2_swerv_wrapper :
     node _T_7573 = and(_T_7570, _T_7572) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7574 = or(_T_7573, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7575 = bits(_T_7574, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_0 = mux(_T_7575, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7576 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7577 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7578 = eq(_T_7577, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41384,7 +41384,7 @@ circuit el2_swerv_wrapper :
     node _T_7582 = and(_T_7579, _T_7581) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7583 = or(_T_7582, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7584 = bits(_T_7583, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_1 = mux(_T_7584, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7585 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7586 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7587 = eq(_T_7586, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41394,7 +41394,7 @@ circuit el2_swerv_wrapper :
     node _T_7591 = and(_T_7588, _T_7590) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7592 = or(_T_7591, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7593 = bits(_T_7592, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_2 = mux(_T_7593, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7594 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7595 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7596 = eq(_T_7595, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41404,7 +41404,7 @@ circuit el2_swerv_wrapper :
     node _T_7600 = and(_T_7597, _T_7599) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7601 = or(_T_7600, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7602 = bits(_T_7601, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_3 = mux(_T_7602, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7603 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7604 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7605 = eq(_T_7604, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41414,7 +41414,7 @@ circuit el2_swerv_wrapper :
     node _T_7609 = and(_T_7606, _T_7608) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7610 = or(_T_7609, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7611 = bits(_T_7610, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_4 = mux(_T_7611, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7612 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7613 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7614 = eq(_T_7613, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41424,7 +41424,7 @@ circuit el2_swerv_wrapper :
     node _T_7618 = and(_T_7615, _T_7617) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7619 = or(_T_7618, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7620 = bits(_T_7619, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_5 = mux(_T_7620, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7621 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7622 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7623 = eq(_T_7622, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41434,7 +41434,7 @@ circuit el2_swerv_wrapper :
     node _T_7627 = and(_T_7624, _T_7626) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7628 = or(_T_7627, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7629 = bits(_T_7628, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_6 = mux(_T_7629, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7630 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7631 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7632 = eq(_T_7631, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41444,7 +41444,7 @@ circuit el2_swerv_wrapper :
     node _T_7636 = and(_T_7633, _T_7635) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7637 = or(_T_7636, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7638 = bits(_T_7637, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_7 = mux(_T_7638, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7639 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7640 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7641 = eq(_T_7640, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41454,7 +41454,7 @@ circuit el2_swerv_wrapper :
     node _T_7645 = and(_T_7642, _T_7644) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7646 = or(_T_7645, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7647 = bits(_T_7646, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_8 = mux(_T_7647, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7648 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7649 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7650 = eq(_T_7649, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41464,7 +41464,7 @@ circuit el2_swerv_wrapper :
     node _T_7654 = and(_T_7651, _T_7653) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7655 = or(_T_7654, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7656 = bits(_T_7655, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_9 = mux(_T_7656, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7657 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7658 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7659 = eq(_T_7658, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41474,7 +41474,7 @@ circuit el2_swerv_wrapper :
     node _T_7663 = and(_T_7660, _T_7662) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7664 = or(_T_7663, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7665 = bits(_T_7664, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_10 = mux(_T_7665, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7666 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7667 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7668 = eq(_T_7667, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41484,7 +41484,7 @@ circuit el2_swerv_wrapper :
     node _T_7672 = and(_T_7669, _T_7671) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7673 = or(_T_7672, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7674 = bits(_T_7673, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_11 = mux(_T_7674, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7675 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7676 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7677 = eq(_T_7676, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41494,7 +41494,7 @@ circuit el2_swerv_wrapper :
     node _T_7681 = and(_T_7678, _T_7680) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7682 = or(_T_7681, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7683 = bits(_T_7682, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_12 = mux(_T_7683, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7684 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7685 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7686 = eq(_T_7685, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41504,7 +41504,7 @@ circuit el2_swerv_wrapper :
     node _T_7690 = and(_T_7687, _T_7689) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7691 = or(_T_7690, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7692 = bits(_T_7691, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_13 = mux(_T_7692, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7693 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7694 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7695 = eq(_T_7694, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41514,7 +41514,7 @@ circuit el2_swerv_wrapper :
     node _T_7699 = and(_T_7696, _T_7698) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7700 = or(_T_7699, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7701 = bits(_T_7700, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_14 = mux(_T_7701, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7702 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7703 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7704 = eq(_T_7703, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41524,7 +41524,7 @@ circuit el2_swerv_wrapper :
     node _T_7708 = and(_T_7705, _T_7707) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7709 = or(_T_7708, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7710 = bits(_T_7709, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_7_15 = mux(_T_7710, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7711 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7712 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7713 = eq(_T_7712, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41534,7 +41534,7 @@ circuit el2_swerv_wrapper :
     node _T_7717 = and(_T_7714, _T_7716) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7718 = or(_T_7717, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7719 = bits(_T_7718, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_0 = mux(_T_7719, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7720 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7721 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7722 = eq(_T_7721, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41544,7 +41544,7 @@ circuit el2_swerv_wrapper :
     node _T_7726 = and(_T_7723, _T_7725) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7727 = or(_T_7726, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7728 = bits(_T_7727, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_1 = mux(_T_7728, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7729 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7730 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7731 = eq(_T_7730, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41554,7 +41554,7 @@ circuit el2_swerv_wrapper :
     node _T_7735 = and(_T_7732, _T_7734) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7736 = or(_T_7735, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7737 = bits(_T_7736, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_2 = mux(_T_7737, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7738 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7739 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7740 = eq(_T_7739, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41564,7 +41564,7 @@ circuit el2_swerv_wrapper :
     node _T_7744 = and(_T_7741, _T_7743) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7745 = or(_T_7744, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7746 = bits(_T_7745, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_3 = mux(_T_7746, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7747 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7748 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7749 = eq(_T_7748, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41574,7 +41574,7 @@ circuit el2_swerv_wrapper :
     node _T_7753 = and(_T_7750, _T_7752) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7754 = or(_T_7753, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7755 = bits(_T_7754, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_4 = mux(_T_7755, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7756 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7757 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7758 = eq(_T_7757, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41584,7 +41584,7 @@ circuit el2_swerv_wrapper :
     node _T_7762 = and(_T_7759, _T_7761) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7763 = or(_T_7762, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7764 = bits(_T_7763, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_5 = mux(_T_7764, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7765 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7766 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7767 = eq(_T_7766, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41594,7 +41594,7 @@ circuit el2_swerv_wrapper :
     node _T_7771 = and(_T_7768, _T_7770) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7772 = or(_T_7771, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7773 = bits(_T_7772, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_6 = mux(_T_7773, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7774 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7775 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7776 = eq(_T_7775, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41604,7 +41604,7 @@ circuit el2_swerv_wrapper :
     node _T_7780 = and(_T_7777, _T_7779) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7781 = or(_T_7780, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7782 = bits(_T_7781, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_7 = mux(_T_7782, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7783 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7784 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7785 = eq(_T_7784, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41614,7 +41614,7 @@ circuit el2_swerv_wrapper :
     node _T_7789 = and(_T_7786, _T_7788) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7790 = or(_T_7789, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7791 = bits(_T_7790, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_8 = mux(_T_7791, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7792 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7793 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7794 = eq(_T_7793, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41624,7 +41624,7 @@ circuit el2_swerv_wrapper :
     node _T_7798 = and(_T_7795, _T_7797) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7799 = or(_T_7798, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7800 = bits(_T_7799, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_9 = mux(_T_7800, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7801 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7802 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7803 = eq(_T_7802, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41634,7 +41634,7 @@ circuit el2_swerv_wrapper :
     node _T_7807 = and(_T_7804, _T_7806) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7808 = or(_T_7807, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7809 = bits(_T_7808, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_10 = mux(_T_7809, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7810 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7811 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7812 = eq(_T_7811, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41644,7 +41644,7 @@ circuit el2_swerv_wrapper :
     node _T_7816 = and(_T_7813, _T_7815) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7817 = or(_T_7816, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7818 = bits(_T_7817, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_11 = mux(_T_7818, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7819 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7820 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7821 = eq(_T_7820, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41654,7 +41654,7 @@ circuit el2_swerv_wrapper :
     node _T_7825 = and(_T_7822, _T_7824) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7826 = or(_T_7825, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7827 = bits(_T_7826, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_12 = mux(_T_7827, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7828 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7829 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7830 = eq(_T_7829, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41664,7 +41664,7 @@ circuit el2_swerv_wrapper :
     node _T_7834 = and(_T_7831, _T_7833) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7835 = or(_T_7834, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7836 = bits(_T_7835, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_13 = mux(_T_7836, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7837 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7838 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7839 = eq(_T_7838, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41674,7 +41674,7 @@ circuit el2_swerv_wrapper :
     node _T_7843 = and(_T_7840, _T_7842) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7844 = or(_T_7843, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7845 = bits(_T_7844, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_14 = mux(_T_7845, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7846 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7847 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7848 = eq(_T_7847, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41684,7 +41684,7 @@ circuit el2_swerv_wrapper :
     node _T_7852 = and(_T_7849, _T_7851) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7853 = or(_T_7852, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7854 = bits(_T_7853, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_8_15 = mux(_T_7854, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7855 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7856 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7857 = eq(_T_7856, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41694,7 +41694,7 @@ circuit el2_swerv_wrapper :
     node _T_7861 = and(_T_7858, _T_7860) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7862 = or(_T_7861, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7863 = bits(_T_7862, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_0 = mux(_T_7863, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7864 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7865 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7866 = eq(_T_7865, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41704,7 +41704,7 @@ circuit el2_swerv_wrapper :
     node _T_7870 = and(_T_7867, _T_7869) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7871 = or(_T_7870, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7872 = bits(_T_7871, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_1 = mux(_T_7872, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7873 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7874 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7875 = eq(_T_7874, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41714,7 +41714,7 @@ circuit el2_swerv_wrapper :
     node _T_7879 = and(_T_7876, _T_7878) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7880 = or(_T_7879, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7881 = bits(_T_7880, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_2 = mux(_T_7881, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7882 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7883 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7884 = eq(_T_7883, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41724,7 +41724,7 @@ circuit el2_swerv_wrapper :
     node _T_7888 = and(_T_7885, _T_7887) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7889 = or(_T_7888, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7890 = bits(_T_7889, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_3 = mux(_T_7890, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7891 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7892 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7893 = eq(_T_7892, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41734,7 +41734,7 @@ circuit el2_swerv_wrapper :
     node _T_7897 = and(_T_7894, _T_7896) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7898 = or(_T_7897, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7899 = bits(_T_7898, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_4 = mux(_T_7899, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7900 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7901 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7902 = eq(_T_7901, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41744,7 +41744,7 @@ circuit el2_swerv_wrapper :
     node _T_7906 = and(_T_7903, _T_7905) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7907 = or(_T_7906, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7908 = bits(_T_7907, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_5 = mux(_T_7908, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7909 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7910 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7911 = eq(_T_7910, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41754,7 +41754,7 @@ circuit el2_swerv_wrapper :
     node _T_7915 = and(_T_7912, _T_7914) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7916 = or(_T_7915, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7917 = bits(_T_7916, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_6 = mux(_T_7917, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7918 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7919 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7920 = eq(_T_7919, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41764,7 +41764,7 @@ circuit el2_swerv_wrapper :
     node _T_7924 = and(_T_7921, _T_7923) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7925 = or(_T_7924, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7926 = bits(_T_7925, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_7 = mux(_T_7926, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7927 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7928 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7929 = eq(_T_7928, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41774,7 +41774,7 @@ circuit el2_swerv_wrapper :
     node _T_7933 = and(_T_7930, _T_7932) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7934 = or(_T_7933, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7935 = bits(_T_7934, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_8 = mux(_T_7935, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7936 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7937 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7938 = eq(_T_7937, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41784,7 +41784,7 @@ circuit el2_swerv_wrapper :
     node _T_7942 = and(_T_7939, _T_7941) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7943 = or(_T_7942, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7944 = bits(_T_7943, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_9 = mux(_T_7944, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7945 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7946 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7947 = eq(_T_7946, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41794,7 +41794,7 @@ circuit el2_swerv_wrapper :
     node _T_7951 = and(_T_7948, _T_7950) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7952 = or(_T_7951, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7953 = bits(_T_7952, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_10 = mux(_T_7953, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7954 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7955 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7956 = eq(_T_7955, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41804,7 +41804,7 @@ circuit el2_swerv_wrapper :
     node _T_7960 = and(_T_7957, _T_7959) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7961 = or(_T_7960, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7962 = bits(_T_7961, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_11 = mux(_T_7962, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7963 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7964 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7965 = eq(_T_7964, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41814,7 +41814,7 @@ circuit el2_swerv_wrapper :
     node _T_7969 = and(_T_7966, _T_7968) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7970 = or(_T_7969, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7971 = bits(_T_7970, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_12 = mux(_T_7971, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7972 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7973 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7974 = eq(_T_7973, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41824,7 +41824,7 @@ circuit el2_swerv_wrapper :
     node _T_7978 = and(_T_7975, _T_7977) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7979 = or(_T_7978, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7980 = bits(_T_7979, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_13 = mux(_T_7980, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7981 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7982 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7983 = eq(_T_7982, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41834,7 +41834,7 @@ circuit el2_swerv_wrapper :
     node _T_7987 = and(_T_7984, _T_7986) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7988 = or(_T_7987, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7989 = bits(_T_7988, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_14 = mux(_T_7989, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7990 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_7991 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_7992 = eq(_T_7991, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41844,7 +41844,7 @@ circuit el2_swerv_wrapper :
     node _T_7996 = and(_T_7993, _T_7995) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_7997 = or(_T_7996, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_7998 = bits(_T_7997, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_9_15 = mux(_T_7998, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_7999 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8000 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8001 = eq(_T_8000, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41854,7 +41854,7 @@ circuit el2_swerv_wrapper :
     node _T_8005 = and(_T_8002, _T_8004) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8006 = or(_T_8005, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8007 = bits(_T_8006, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_0 = mux(_T_8007, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8008 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8009 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8010 = eq(_T_8009, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41864,7 +41864,7 @@ circuit el2_swerv_wrapper :
     node _T_8014 = and(_T_8011, _T_8013) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8015 = or(_T_8014, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8016 = bits(_T_8015, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_1 = mux(_T_8016, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8017 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8018 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8019 = eq(_T_8018, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41874,7 +41874,7 @@ circuit el2_swerv_wrapper :
     node _T_8023 = and(_T_8020, _T_8022) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8024 = or(_T_8023, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8025 = bits(_T_8024, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_2 = mux(_T_8025, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8026 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8027 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8028 = eq(_T_8027, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41884,7 +41884,7 @@ circuit el2_swerv_wrapper :
     node _T_8032 = and(_T_8029, _T_8031) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8033 = or(_T_8032, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8034 = bits(_T_8033, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_3 = mux(_T_8034, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8035 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8036 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8037 = eq(_T_8036, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41894,7 +41894,7 @@ circuit el2_swerv_wrapper :
     node _T_8041 = and(_T_8038, _T_8040) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8042 = or(_T_8041, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8043 = bits(_T_8042, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_4 = mux(_T_8043, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8044 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8045 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8046 = eq(_T_8045, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41904,7 +41904,7 @@ circuit el2_swerv_wrapper :
     node _T_8050 = and(_T_8047, _T_8049) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8051 = or(_T_8050, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8052 = bits(_T_8051, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_5 = mux(_T_8052, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8053 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8054 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8055 = eq(_T_8054, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41914,7 +41914,7 @@ circuit el2_swerv_wrapper :
     node _T_8059 = and(_T_8056, _T_8058) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8060 = or(_T_8059, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8061 = bits(_T_8060, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_6 = mux(_T_8061, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8062 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8063 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8064 = eq(_T_8063, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41924,7 +41924,7 @@ circuit el2_swerv_wrapper :
     node _T_8068 = and(_T_8065, _T_8067) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8069 = or(_T_8068, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8070 = bits(_T_8069, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_7 = mux(_T_8070, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8071 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8072 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8073 = eq(_T_8072, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41934,7 +41934,7 @@ circuit el2_swerv_wrapper :
     node _T_8077 = and(_T_8074, _T_8076) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8078 = or(_T_8077, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8079 = bits(_T_8078, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_8 = mux(_T_8079, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8080 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8081 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8082 = eq(_T_8081, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41944,7 +41944,7 @@ circuit el2_swerv_wrapper :
     node _T_8086 = and(_T_8083, _T_8085) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8087 = or(_T_8086, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8088 = bits(_T_8087, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_9 = mux(_T_8088, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8089 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8090 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8091 = eq(_T_8090, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41954,7 +41954,7 @@ circuit el2_swerv_wrapper :
     node _T_8095 = and(_T_8092, _T_8094) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8096 = or(_T_8095, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8097 = bits(_T_8096, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_10 = mux(_T_8097, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8098 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8099 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8100 = eq(_T_8099, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41964,7 +41964,7 @@ circuit el2_swerv_wrapper :
     node _T_8104 = and(_T_8101, _T_8103) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8105 = or(_T_8104, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8106 = bits(_T_8105, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_11 = mux(_T_8106, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8107 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8108 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8109 = eq(_T_8108, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41974,7 +41974,7 @@ circuit el2_swerv_wrapper :
     node _T_8113 = and(_T_8110, _T_8112) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8114 = or(_T_8113, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8115 = bits(_T_8114, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_12 = mux(_T_8115, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8116 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8117 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8118 = eq(_T_8117, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41984,7 +41984,7 @@ circuit el2_swerv_wrapper :
     node _T_8122 = and(_T_8119, _T_8121) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8123 = or(_T_8122, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8124 = bits(_T_8123, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_13 = mux(_T_8124, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8125 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8126 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8127 = eq(_T_8126, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -41994,7 +41994,7 @@ circuit el2_swerv_wrapper :
     node _T_8131 = and(_T_8128, _T_8130) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8132 = or(_T_8131, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8133 = bits(_T_8132, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_14 = mux(_T_8133, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8134 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8135 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8136 = eq(_T_8135, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42004,7 +42004,7 @@ circuit el2_swerv_wrapper :
     node _T_8140 = and(_T_8137, _T_8139) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8141 = or(_T_8140, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8142 = bits(_T_8141, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_10_15 = mux(_T_8142, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8143 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8144 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8145 = eq(_T_8144, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42014,7 +42014,7 @@ circuit el2_swerv_wrapper :
     node _T_8149 = and(_T_8146, _T_8148) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8150 = or(_T_8149, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8151 = bits(_T_8150, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_0 = mux(_T_8151, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8152 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8153 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8154 = eq(_T_8153, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42024,7 +42024,7 @@ circuit el2_swerv_wrapper :
     node _T_8158 = and(_T_8155, _T_8157) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8159 = or(_T_8158, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8160 = bits(_T_8159, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_1 = mux(_T_8160, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8161 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8162 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8163 = eq(_T_8162, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42034,7 +42034,7 @@ circuit el2_swerv_wrapper :
     node _T_8167 = and(_T_8164, _T_8166) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8168 = or(_T_8167, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8169 = bits(_T_8168, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_2 = mux(_T_8169, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8170 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8171 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8172 = eq(_T_8171, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42044,7 +42044,7 @@ circuit el2_swerv_wrapper :
     node _T_8176 = and(_T_8173, _T_8175) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8177 = or(_T_8176, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8178 = bits(_T_8177, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_3 = mux(_T_8178, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8179 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8180 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8181 = eq(_T_8180, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42054,7 +42054,7 @@ circuit el2_swerv_wrapper :
     node _T_8185 = and(_T_8182, _T_8184) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8186 = or(_T_8185, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8187 = bits(_T_8186, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_4 = mux(_T_8187, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8188 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8189 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8190 = eq(_T_8189, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42064,7 +42064,7 @@ circuit el2_swerv_wrapper :
     node _T_8194 = and(_T_8191, _T_8193) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8195 = or(_T_8194, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8196 = bits(_T_8195, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_5 = mux(_T_8196, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8197 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8198 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8199 = eq(_T_8198, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42074,7 +42074,7 @@ circuit el2_swerv_wrapper :
     node _T_8203 = and(_T_8200, _T_8202) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8204 = or(_T_8203, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8205 = bits(_T_8204, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_6 = mux(_T_8205, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8206 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8207 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8208 = eq(_T_8207, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42084,7 +42084,7 @@ circuit el2_swerv_wrapper :
     node _T_8212 = and(_T_8209, _T_8211) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8213 = or(_T_8212, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8214 = bits(_T_8213, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_7 = mux(_T_8214, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8215 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8216 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8217 = eq(_T_8216, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42094,7 +42094,7 @@ circuit el2_swerv_wrapper :
     node _T_8221 = and(_T_8218, _T_8220) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8222 = or(_T_8221, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8223 = bits(_T_8222, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_8 = mux(_T_8223, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8224 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8225 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8226 = eq(_T_8225, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42104,7 +42104,7 @@ circuit el2_swerv_wrapper :
     node _T_8230 = and(_T_8227, _T_8229) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8231 = or(_T_8230, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8232 = bits(_T_8231, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_9 = mux(_T_8232, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8233 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8234 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8235 = eq(_T_8234, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42114,7 +42114,7 @@ circuit el2_swerv_wrapper :
     node _T_8239 = and(_T_8236, _T_8238) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8240 = or(_T_8239, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8241 = bits(_T_8240, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_10 = mux(_T_8241, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8242 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8243 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8244 = eq(_T_8243, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42124,7 +42124,7 @@ circuit el2_swerv_wrapper :
     node _T_8248 = and(_T_8245, _T_8247) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8249 = or(_T_8248, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8250 = bits(_T_8249, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_11 = mux(_T_8250, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8251 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8252 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8253 = eq(_T_8252, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42134,7 +42134,7 @@ circuit el2_swerv_wrapper :
     node _T_8257 = and(_T_8254, _T_8256) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8258 = or(_T_8257, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8259 = bits(_T_8258, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_12 = mux(_T_8259, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8260 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8261 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8262 = eq(_T_8261, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42144,7 +42144,7 @@ circuit el2_swerv_wrapper :
     node _T_8266 = and(_T_8263, _T_8265) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8267 = or(_T_8266, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8268 = bits(_T_8267, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_13 = mux(_T_8268, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8269 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8270 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8271 = eq(_T_8270, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42154,7 +42154,7 @@ circuit el2_swerv_wrapper :
     node _T_8275 = and(_T_8272, _T_8274) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8276 = or(_T_8275, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8277 = bits(_T_8276, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_14 = mux(_T_8277, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8278 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8279 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8280 = eq(_T_8279, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42164,7 +42164,7 @@ circuit el2_swerv_wrapper :
     node _T_8284 = and(_T_8281, _T_8283) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8285 = or(_T_8284, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8286 = bits(_T_8285, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_11_15 = mux(_T_8286, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8287 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8288 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8289 = eq(_T_8288, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42174,7 +42174,7 @@ circuit el2_swerv_wrapper :
     node _T_8293 = and(_T_8290, _T_8292) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8294 = or(_T_8293, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8295 = bits(_T_8294, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_0 = mux(_T_8295, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8296 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8297 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8298 = eq(_T_8297, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42184,7 +42184,7 @@ circuit el2_swerv_wrapper :
     node _T_8302 = and(_T_8299, _T_8301) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8303 = or(_T_8302, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8304 = bits(_T_8303, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_1 = mux(_T_8304, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8305 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8306 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8307 = eq(_T_8306, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42194,7 +42194,7 @@ circuit el2_swerv_wrapper :
     node _T_8311 = and(_T_8308, _T_8310) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8312 = or(_T_8311, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8313 = bits(_T_8312, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_2 = mux(_T_8313, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8314 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8315 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8316 = eq(_T_8315, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42204,7 +42204,7 @@ circuit el2_swerv_wrapper :
     node _T_8320 = and(_T_8317, _T_8319) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8321 = or(_T_8320, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8322 = bits(_T_8321, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_3 = mux(_T_8322, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8323 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8324 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8325 = eq(_T_8324, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42214,7 +42214,7 @@ circuit el2_swerv_wrapper :
     node _T_8329 = and(_T_8326, _T_8328) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8330 = or(_T_8329, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8331 = bits(_T_8330, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_4 = mux(_T_8331, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8332 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8333 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8334 = eq(_T_8333, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42224,7 +42224,7 @@ circuit el2_swerv_wrapper :
     node _T_8338 = and(_T_8335, _T_8337) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8339 = or(_T_8338, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8340 = bits(_T_8339, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_5 = mux(_T_8340, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8341 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8342 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8343 = eq(_T_8342, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42234,7 +42234,7 @@ circuit el2_swerv_wrapper :
     node _T_8347 = and(_T_8344, _T_8346) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8348 = or(_T_8347, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8349 = bits(_T_8348, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_6 = mux(_T_8349, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8350 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8351 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8352 = eq(_T_8351, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42244,7 +42244,7 @@ circuit el2_swerv_wrapper :
     node _T_8356 = and(_T_8353, _T_8355) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8357 = or(_T_8356, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8358 = bits(_T_8357, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_7 = mux(_T_8358, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8359 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8360 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8361 = eq(_T_8360, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42254,7 +42254,7 @@ circuit el2_swerv_wrapper :
     node _T_8365 = and(_T_8362, _T_8364) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8366 = or(_T_8365, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8367 = bits(_T_8366, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_8 = mux(_T_8367, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8368 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8369 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8370 = eq(_T_8369, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42264,7 +42264,7 @@ circuit el2_swerv_wrapper :
     node _T_8374 = and(_T_8371, _T_8373) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8375 = or(_T_8374, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8376 = bits(_T_8375, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_9 = mux(_T_8376, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8377 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8378 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8379 = eq(_T_8378, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42274,7 +42274,7 @@ circuit el2_swerv_wrapper :
     node _T_8383 = and(_T_8380, _T_8382) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8384 = or(_T_8383, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8385 = bits(_T_8384, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_10 = mux(_T_8385, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8386 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8387 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8388 = eq(_T_8387, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42284,7 +42284,7 @@ circuit el2_swerv_wrapper :
     node _T_8392 = and(_T_8389, _T_8391) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8393 = or(_T_8392, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8394 = bits(_T_8393, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_11 = mux(_T_8394, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8395 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8396 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8397 = eq(_T_8396, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42294,7 +42294,7 @@ circuit el2_swerv_wrapper :
     node _T_8401 = and(_T_8398, _T_8400) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8402 = or(_T_8401, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8403 = bits(_T_8402, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_12 = mux(_T_8403, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8404 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8405 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8406 = eq(_T_8405, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42304,7 +42304,7 @@ circuit el2_swerv_wrapper :
     node _T_8410 = and(_T_8407, _T_8409) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8411 = or(_T_8410, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8412 = bits(_T_8411, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_13 = mux(_T_8412, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8413 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8414 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8415 = eq(_T_8414, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42314,7 +42314,7 @@ circuit el2_swerv_wrapper :
     node _T_8419 = and(_T_8416, _T_8418) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8420 = or(_T_8419, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8421 = bits(_T_8420, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_14 = mux(_T_8421, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8422 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8423 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8424 = eq(_T_8423, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42324,7 +42324,7 @@ circuit el2_swerv_wrapper :
     node _T_8428 = and(_T_8425, _T_8427) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8429 = or(_T_8428, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8430 = bits(_T_8429, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_12_15 = mux(_T_8430, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8431 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8432 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8433 = eq(_T_8432, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42334,7 +42334,7 @@ circuit el2_swerv_wrapper :
     node _T_8437 = and(_T_8434, _T_8436) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8438 = or(_T_8437, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8439 = bits(_T_8438, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_0 = mux(_T_8439, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8440 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8441 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8442 = eq(_T_8441, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42344,7 +42344,7 @@ circuit el2_swerv_wrapper :
     node _T_8446 = and(_T_8443, _T_8445) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8447 = or(_T_8446, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8448 = bits(_T_8447, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_1 = mux(_T_8448, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8449 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8450 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8451 = eq(_T_8450, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42354,7 +42354,7 @@ circuit el2_swerv_wrapper :
     node _T_8455 = and(_T_8452, _T_8454) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8456 = or(_T_8455, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8457 = bits(_T_8456, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_2 = mux(_T_8457, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8458 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8459 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8460 = eq(_T_8459, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42364,7 +42364,7 @@ circuit el2_swerv_wrapper :
     node _T_8464 = and(_T_8461, _T_8463) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8465 = or(_T_8464, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8466 = bits(_T_8465, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_3 = mux(_T_8466, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8467 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8468 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8469 = eq(_T_8468, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42374,7 +42374,7 @@ circuit el2_swerv_wrapper :
     node _T_8473 = and(_T_8470, _T_8472) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8474 = or(_T_8473, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8475 = bits(_T_8474, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_4 = mux(_T_8475, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8476 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8477 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8478 = eq(_T_8477, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42384,7 +42384,7 @@ circuit el2_swerv_wrapper :
     node _T_8482 = and(_T_8479, _T_8481) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8483 = or(_T_8482, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8484 = bits(_T_8483, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_5 = mux(_T_8484, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8485 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8486 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8487 = eq(_T_8486, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42394,7 +42394,7 @@ circuit el2_swerv_wrapper :
     node _T_8491 = and(_T_8488, _T_8490) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8492 = or(_T_8491, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8493 = bits(_T_8492, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_6 = mux(_T_8493, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8494 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8495 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8496 = eq(_T_8495, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42404,7 +42404,7 @@ circuit el2_swerv_wrapper :
     node _T_8500 = and(_T_8497, _T_8499) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8501 = or(_T_8500, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8502 = bits(_T_8501, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_7 = mux(_T_8502, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8503 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8504 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8505 = eq(_T_8504, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42414,7 +42414,7 @@ circuit el2_swerv_wrapper :
     node _T_8509 = and(_T_8506, _T_8508) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8510 = or(_T_8509, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8511 = bits(_T_8510, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_8 = mux(_T_8511, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8512 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8513 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8514 = eq(_T_8513, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42424,7 +42424,7 @@ circuit el2_swerv_wrapper :
     node _T_8518 = and(_T_8515, _T_8517) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8519 = or(_T_8518, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8520 = bits(_T_8519, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_9 = mux(_T_8520, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8521 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8522 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8523 = eq(_T_8522, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42434,7 +42434,7 @@ circuit el2_swerv_wrapper :
     node _T_8527 = and(_T_8524, _T_8526) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8528 = or(_T_8527, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8529 = bits(_T_8528, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_10 = mux(_T_8529, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8530 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8531 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8532 = eq(_T_8531, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42444,7 +42444,7 @@ circuit el2_swerv_wrapper :
     node _T_8536 = and(_T_8533, _T_8535) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8537 = or(_T_8536, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8538 = bits(_T_8537, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_11 = mux(_T_8538, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8539 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8540 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8541 = eq(_T_8540, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42454,7 +42454,7 @@ circuit el2_swerv_wrapper :
     node _T_8545 = and(_T_8542, _T_8544) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8546 = or(_T_8545, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8547 = bits(_T_8546, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_12 = mux(_T_8547, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8548 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8549 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8550 = eq(_T_8549, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42464,7 +42464,7 @@ circuit el2_swerv_wrapper :
     node _T_8554 = and(_T_8551, _T_8553) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8555 = or(_T_8554, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8556 = bits(_T_8555, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_13 = mux(_T_8556, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8557 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8558 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8559 = eq(_T_8558, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42474,7 +42474,7 @@ circuit el2_swerv_wrapper :
     node _T_8563 = and(_T_8560, _T_8562) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8564 = or(_T_8563, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8565 = bits(_T_8564, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_14 = mux(_T_8565, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8566 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8567 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8568 = eq(_T_8567, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42484,7 +42484,7 @@ circuit el2_swerv_wrapper :
     node _T_8572 = and(_T_8569, _T_8571) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8573 = or(_T_8572, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8574 = bits(_T_8573, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_13_15 = mux(_T_8574, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8575 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8576 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8577 = eq(_T_8576, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42494,7 +42494,7 @@ circuit el2_swerv_wrapper :
     node _T_8581 = and(_T_8578, _T_8580) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8582 = or(_T_8581, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8583 = bits(_T_8582, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_0 = mux(_T_8583, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8584 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8585 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8586 = eq(_T_8585, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42504,7 +42504,7 @@ circuit el2_swerv_wrapper :
     node _T_8590 = and(_T_8587, _T_8589) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8591 = or(_T_8590, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8592 = bits(_T_8591, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_1 = mux(_T_8592, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8593 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8594 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8595 = eq(_T_8594, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42514,7 +42514,7 @@ circuit el2_swerv_wrapper :
     node _T_8599 = and(_T_8596, _T_8598) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8600 = or(_T_8599, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8601 = bits(_T_8600, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_2 = mux(_T_8601, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8602 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8603 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8604 = eq(_T_8603, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42524,7 +42524,7 @@ circuit el2_swerv_wrapper :
     node _T_8608 = and(_T_8605, _T_8607) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8609 = or(_T_8608, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8610 = bits(_T_8609, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_3 = mux(_T_8610, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8611 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8612 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8613 = eq(_T_8612, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42534,7 +42534,7 @@ circuit el2_swerv_wrapper :
     node _T_8617 = and(_T_8614, _T_8616) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8618 = or(_T_8617, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8619 = bits(_T_8618, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_4 = mux(_T_8619, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8620 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8621 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8622 = eq(_T_8621, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42544,7 +42544,7 @@ circuit el2_swerv_wrapper :
     node _T_8626 = and(_T_8623, _T_8625) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8627 = or(_T_8626, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8628 = bits(_T_8627, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_5 = mux(_T_8628, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8629 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8630 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8631 = eq(_T_8630, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42554,7 +42554,7 @@ circuit el2_swerv_wrapper :
     node _T_8635 = and(_T_8632, _T_8634) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8636 = or(_T_8635, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8637 = bits(_T_8636, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_6 = mux(_T_8637, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8638 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8639 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8640 = eq(_T_8639, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42564,7 +42564,7 @@ circuit el2_swerv_wrapper :
     node _T_8644 = and(_T_8641, _T_8643) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8645 = or(_T_8644, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8646 = bits(_T_8645, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_7 = mux(_T_8646, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8647 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8648 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8649 = eq(_T_8648, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42574,7 +42574,7 @@ circuit el2_swerv_wrapper :
     node _T_8653 = and(_T_8650, _T_8652) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8654 = or(_T_8653, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8655 = bits(_T_8654, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_8 = mux(_T_8655, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8656 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8657 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8658 = eq(_T_8657, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42584,7 +42584,7 @@ circuit el2_swerv_wrapper :
     node _T_8662 = and(_T_8659, _T_8661) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8663 = or(_T_8662, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8664 = bits(_T_8663, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_9 = mux(_T_8664, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8665 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8666 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8667 = eq(_T_8666, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42594,7 +42594,7 @@ circuit el2_swerv_wrapper :
     node _T_8671 = and(_T_8668, _T_8670) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8672 = or(_T_8671, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8673 = bits(_T_8672, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_10 = mux(_T_8673, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8674 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8675 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8676 = eq(_T_8675, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42604,7 +42604,7 @@ circuit el2_swerv_wrapper :
     node _T_8680 = and(_T_8677, _T_8679) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8681 = or(_T_8680, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8682 = bits(_T_8681, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_11 = mux(_T_8682, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8683 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8684 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8685 = eq(_T_8684, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42614,7 +42614,7 @@ circuit el2_swerv_wrapper :
     node _T_8689 = and(_T_8686, _T_8688) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8690 = or(_T_8689, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8691 = bits(_T_8690, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_12 = mux(_T_8691, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8692 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8693 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8694 = eq(_T_8693, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42624,7 +42624,7 @@ circuit el2_swerv_wrapper :
     node _T_8698 = and(_T_8695, _T_8697) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8699 = or(_T_8698, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8700 = bits(_T_8699, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_13 = mux(_T_8700, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8701 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8702 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8703 = eq(_T_8702, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42634,7 +42634,7 @@ circuit el2_swerv_wrapper :
     node _T_8707 = and(_T_8704, _T_8706) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8708 = or(_T_8707, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8709 = bits(_T_8708, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_14 = mux(_T_8709, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8710 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8711 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8712 = eq(_T_8711, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42644,7 +42644,7 @@ circuit el2_swerv_wrapper :
     node _T_8716 = and(_T_8713, _T_8715) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8717 = or(_T_8716, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8718 = bits(_T_8717, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_14_15 = mux(_T_8718, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8719 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8720 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8721 = eq(_T_8720, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42654,7 +42654,7 @@ circuit el2_swerv_wrapper :
     node _T_8725 = and(_T_8722, _T_8724) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8726 = or(_T_8725, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8727 = bits(_T_8726, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_0 = mux(_T_8727, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8728 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8729 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8730 = eq(_T_8729, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42664,7 +42664,7 @@ circuit el2_swerv_wrapper :
     node _T_8734 = and(_T_8731, _T_8733) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8735 = or(_T_8734, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8736 = bits(_T_8735, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_1 = mux(_T_8736, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8737 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8738 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8739 = eq(_T_8738, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42674,7 +42674,7 @@ circuit el2_swerv_wrapper :
     node _T_8743 = and(_T_8740, _T_8742) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8744 = or(_T_8743, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8745 = bits(_T_8744, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_2 = mux(_T_8745, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8746 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8747 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8748 = eq(_T_8747, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42684,7 +42684,7 @@ circuit el2_swerv_wrapper :
     node _T_8752 = and(_T_8749, _T_8751) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8753 = or(_T_8752, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8754 = bits(_T_8753, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_3 = mux(_T_8754, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8755 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8756 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8757 = eq(_T_8756, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42694,7 +42694,7 @@ circuit el2_swerv_wrapper :
     node _T_8761 = and(_T_8758, _T_8760) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8762 = or(_T_8761, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8763 = bits(_T_8762, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_4 = mux(_T_8763, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8764 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8765 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8766 = eq(_T_8765, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42704,7 +42704,7 @@ circuit el2_swerv_wrapper :
     node _T_8770 = and(_T_8767, _T_8769) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8771 = or(_T_8770, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8772 = bits(_T_8771, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_5 = mux(_T_8772, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8773 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8774 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8775 = eq(_T_8774, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42714,7 +42714,7 @@ circuit el2_swerv_wrapper :
     node _T_8779 = and(_T_8776, _T_8778) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8780 = or(_T_8779, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8781 = bits(_T_8780, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_6 = mux(_T_8781, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8782 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8783 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8784 = eq(_T_8783, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42724,7 +42724,7 @@ circuit el2_swerv_wrapper :
     node _T_8788 = and(_T_8785, _T_8787) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8789 = or(_T_8788, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8790 = bits(_T_8789, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_7 = mux(_T_8790, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8791 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8792 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8793 = eq(_T_8792, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42734,7 +42734,7 @@ circuit el2_swerv_wrapper :
     node _T_8797 = and(_T_8794, _T_8796) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8798 = or(_T_8797, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8799 = bits(_T_8798, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_8 = mux(_T_8799, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8800 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8801 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8802 = eq(_T_8801, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42744,7 +42744,7 @@ circuit el2_swerv_wrapper :
     node _T_8806 = and(_T_8803, _T_8805) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8807 = or(_T_8806, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8808 = bits(_T_8807, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_9 = mux(_T_8808, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8809 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8810 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8811 = eq(_T_8810, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42754,7 +42754,7 @@ circuit el2_swerv_wrapper :
     node _T_8815 = and(_T_8812, _T_8814) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8816 = or(_T_8815, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8817 = bits(_T_8816, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_10 = mux(_T_8817, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8818 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8819 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8820 = eq(_T_8819, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42764,7 +42764,7 @@ circuit el2_swerv_wrapper :
     node _T_8824 = and(_T_8821, _T_8823) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8825 = or(_T_8824, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8826 = bits(_T_8825, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_11 = mux(_T_8826, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8827 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8828 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8829 = eq(_T_8828, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42774,7 +42774,7 @@ circuit el2_swerv_wrapper :
     node _T_8833 = and(_T_8830, _T_8832) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8834 = or(_T_8833, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8835 = bits(_T_8834, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_12 = mux(_T_8835, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8836 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8837 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8838 = eq(_T_8837, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42784,7 +42784,7 @@ circuit el2_swerv_wrapper :
     node _T_8842 = and(_T_8839, _T_8841) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8843 = or(_T_8842, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8844 = bits(_T_8843, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_13 = mux(_T_8844, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8845 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8846 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8847 = eq(_T_8846, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42794,7 +42794,7 @@ circuit el2_swerv_wrapper :
     node _T_8851 = and(_T_8848, _T_8850) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8852 = or(_T_8851, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8853 = bits(_T_8852, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_14 = mux(_T_8853, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8854 = bits(bht_wr_en2, 0, 0) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8855 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8856 = eq(_T_8855, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42804,7 +42804,7 @@ circuit el2_swerv_wrapper :
     node _T_8860 = and(_T_8857, _T_8859) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8861 = or(_T_8860, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8862 = bits(_T_8861, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_0_15_15 = mux(_T_8862, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8863 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8864 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8865 = eq(_T_8864, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42814,7 +42814,7 @@ circuit el2_swerv_wrapper :
     node _T_8869 = and(_T_8866, _T_8868) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8870 = or(_T_8869, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8871 = bits(_T_8870, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_0 = mux(_T_8871, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8872 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8873 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8874 = eq(_T_8873, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42824,7 +42824,7 @@ circuit el2_swerv_wrapper :
     node _T_8878 = and(_T_8875, _T_8877) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8879 = or(_T_8878, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8880 = bits(_T_8879, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_1 = mux(_T_8880, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8881 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8882 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8883 = eq(_T_8882, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42834,7 +42834,7 @@ circuit el2_swerv_wrapper :
     node _T_8887 = and(_T_8884, _T_8886) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8888 = or(_T_8887, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8889 = bits(_T_8888, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_2 = mux(_T_8889, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8890 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8891 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8892 = eq(_T_8891, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42844,7 +42844,7 @@ circuit el2_swerv_wrapper :
     node _T_8896 = and(_T_8893, _T_8895) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8897 = or(_T_8896, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8898 = bits(_T_8897, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_3 = mux(_T_8898, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8899 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8900 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8901 = eq(_T_8900, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42854,7 +42854,7 @@ circuit el2_swerv_wrapper :
     node _T_8905 = and(_T_8902, _T_8904) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8906 = or(_T_8905, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8907 = bits(_T_8906, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_4 = mux(_T_8907, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8908 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8909 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8910 = eq(_T_8909, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42864,7 +42864,7 @@ circuit el2_swerv_wrapper :
     node _T_8914 = and(_T_8911, _T_8913) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8915 = or(_T_8914, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8916 = bits(_T_8915, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_5 = mux(_T_8916, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8917 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8918 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8919 = eq(_T_8918, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42874,7 +42874,7 @@ circuit el2_swerv_wrapper :
     node _T_8923 = and(_T_8920, _T_8922) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8924 = or(_T_8923, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8925 = bits(_T_8924, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_6 = mux(_T_8925, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8926 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8927 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8928 = eq(_T_8927, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42884,7 +42884,7 @@ circuit el2_swerv_wrapper :
     node _T_8932 = and(_T_8929, _T_8931) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8933 = or(_T_8932, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8934 = bits(_T_8933, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_7 = mux(_T_8934, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8935 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8936 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8937 = eq(_T_8936, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42894,7 +42894,7 @@ circuit el2_swerv_wrapper :
     node _T_8941 = and(_T_8938, _T_8940) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8942 = or(_T_8941, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8943 = bits(_T_8942, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_8 = mux(_T_8943, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8944 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8945 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8946 = eq(_T_8945, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42904,7 +42904,7 @@ circuit el2_swerv_wrapper :
     node _T_8950 = and(_T_8947, _T_8949) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8951 = or(_T_8950, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8952 = bits(_T_8951, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_9 = mux(_T_8952, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8953 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8954 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8955 = eq(_T_8954, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42914,7 +42914,7 @@ circuit el2_swerv_wrapper :
     node _T_8959 = and(_T_8956, _T_8958) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8960 = or(_T_8959, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8961 = bits(_T_8960, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_10 = mux(_T_8961, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8962 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8963 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8964 = eq(_T_8963, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42924,7 +42924,7 @@ circuit el2_swerv_wrapper :
     node _T_8968 = and(_T_8965, _T_8967) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8969 = or(_T_8968, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8970 = bits(_T_8969, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_11 = mux(_T_8970, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8971 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8972 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8973 = eq(_T_8972, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42934,7 +42934,7 @@ circuit el2_swerv_wrapper :
     node _T_8977 = and(_T_8974, _T_8976) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8978 = or(_T_8977, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8979 = bits(_T_8978, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_12 = mux(_T_8979, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8980 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8981 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8982 = eq(_T_8981, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42944,7 +42944,7 @@ circuit el2_swerv_wrapper :
     node _T_8986 = and(_T_8983, _T_8985) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8987 = or(_T_8986, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8988 = bits(_T_8987, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_13 = mux(_T_8988, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8989 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8990 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_8991 = eq(_T_8990, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42954,7 +42954,7 @@ circuit el2_swerv_wrapper :
     node _T_8995 = and(_T_8992, _T_8994) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_8996 = or(_T_8995, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_8997 = bits(_T_8996, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_14 = mux(_T_8997, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_8998 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_8999 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9000 = eq(_T_8999, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42964,7 +42964,7 @@ circuit el2_swerv_wrapper :
     node _T_9004 = and(_T_9001, _T_9003) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9005 = or(_T_9004, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9006 = bits(_T_9005, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_0_15 = mux(_T_9006, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9007 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9008 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9009 = eq(_T_9008, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42974,7 +42974,7 @@ circuit el2_swerv_wrapper :
     node _T_9013 = and(_T_9010, _T_9012) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9014 = or(_T_9013, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9015 = bits(_T_9014, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_0 = mux(_T_9015, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9016 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9017 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9018 = eq(_T_9017, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42984,7 +42984,7 @@ circuit el2_swerv_wrapper :
     node _T_9022 = and(_T_9019, _T_9021) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9023 = or(_T_9022, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9024 = bits(_T_9023, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_1 = mux(_T_9024, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9025 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9026 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9027 = eq(_T_9026, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -42994,7 +42994,7 @@ circuit el2_swerv_wrapper :
     node _T_9031 = and(_T_9028, _T_9030) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9032 = or(_T_9031, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9033 = bits(_T_9032, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_2 = mux(_T_9033, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9034 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9035 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9036 = eq(_T_9035, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43004,7 +43004,7 @@ circuit el2_swerv_wrapper :
     node _T_9040 = and(_T_9037, _T_9039) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9041 = or(_T_9040, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9042 = bits(_T_9041, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_3 = mux(_T_9042, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9043 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9044 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9045 = eq(_T_9044, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43014,7 +43014,7 @@ circuit el2_swerv_wrapper :
     node _T_9049 = and(_T_9046, _T_9048) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9050 = or(_T_9049, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9051 = bits(_T_9050, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_4 = mux(_T_9051, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9052 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9053 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9054 = eq(_T_9053, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43024,7 +43024,7 @@ circuit el2_swerv_wrapper :
     node _T_9058 = and(_T_9055, _T_9057) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9059 = or(_T_9058, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9060 = bits(_T_9059, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_5 = mux(_T_9060, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9061 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9062 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9063 = eq(_T_9062, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43034,7 +43034,7 @@ circuit el2_swerv_wrapper :
     node _T_9067 = and(_T_9064, _T_9066) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9068 = or(_T_9067, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9069 = bits(_T_9068, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_6 = mux(_T_9069, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9070 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9071 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9072 = eq(_T_9071, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43044,7 +43044,7 @@ circuit el2_swerv_wrapper :
     node _T_9076 = and(_T_9073, _T_9075) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9077 = or(_T_9076, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9078 = bits(_T_9077, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_7 = mux(_T_9078, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9079 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9080 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9081 = eq(_T_9080, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43054,7 +43054,7 @@ circuit el2_swerv_wrapper :
     node _T_9085 = and(_T_9082, _T_9084) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9086 = or(_T_9085, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9087 = bits(_T_9086, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_8 = mux(_T_9087, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9088 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9089 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9090 = eq(_T_9089, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43064,7 +43064,7 @@ circuit el2_swerv_wrapper :
     node _T_9094 = and(_T_9091, _T_9093) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9095 = or(_T_9094, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9096 = bits(_T_9095, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_9 = mux(_T_9096, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9097 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9098 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9099 = eq(_T_9098, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43074,7 +43074,7 @@ circuit el2_swerv_wrapper :
     node _T_9103 = and(_T_9100, _T_9102) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9104 = or(_T_9103, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9105 = bits(_T_9104, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_10 = mux(_T_9105, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9106 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9107 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9108 = eq(_T_9107, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43084,7 +43084,7 @@ circuit el2_swerv_wrapper :
     node _T_9112 = and(_T_9109, _T_9111) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9113 = or(_T_9112, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9114 = bits(_T_9113, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_11 = mux(_T_9114, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9115 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9116 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9117 = eq(_T_9116, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43094,7 +43094,7 @@ circuit el2_swerv_wrapper :
     node _T_9121 = and(_T_9118, _T_9120) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9122 = or(_T_9121, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9123 = bits(_T_9122, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_12 = mux(_T_9123, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9124 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9125 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9126 = eq(_T_9125, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43104,7 +43104,7 @@ circuit el2_swerv_wrapper :
     node _T_9130 = and(_T_9127, _T_9129) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9131 = or(_T_9130, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9132 = bits(_T_9131, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_13 = mux(_T_9132, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9133 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9134 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9135 = eq(_T_9134, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43114,7 +43114,7 @@ circuit el2_swerv_wrapper :
     node _T_9139 = and(_T_9136, _T_9138) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9140 = or(_T_9139, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9141 = bits(_T_9140, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_14 = mux(_T_9141, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9142 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9143 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9144 = eq(_T_9143, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43124,7 +43124,7 @@ circuit el2_swerv_wrapper :
     node _T_9148 = and(_T_9145, _T_9147) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9149 = or(_T_9148, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9150 = bits(_T_9149, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_1_15 = mux(_T_9150, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9151 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9152 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9153 = eq(_T_9152, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43134,7 +43134,7 @@ circuit el2_swerv_wrapper :
     node _T_9157 = and(_T_9154, _T_9156) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9158 = or(_T_9157, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9159 = bits(_T_9158, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_0 = mux(_T_9159, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9160 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9161 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9162 = eq(_T_9161, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43144,7 +43144,7 @@ circuit el2_swerv_wrapper :
     node _T_9166 = and(_T_9163, _T_9165) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9167 = or(_T_9166, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9168 = bits(_T_9167, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_1 = mux(_T_9168, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9169 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9170 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9171 = eq(_T_9170, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43154,7 +43154,7 @@ circuit el2_swerv_wrapper :
     node _T_9175 = and(_T_9172, _T_9174) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9176 = or(_T_9175, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9177 = bits(_T_9176, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_2 = mux(_T_9177, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9178 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9179 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9180 = eq(_T_9179, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43164,7 +43164,7 @@ circuit el2_swerv_wrapper :
     node _T_9184 = and(_T_9181, _T_9183) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9185 = or(_T_9184, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9186 = bits(_T_9185, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_3 = mux(_T_9186, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9187 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9188 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9189 = eq(_T_9188, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43174,7 +43174,7 @@ circuit el2_swerv_wrapper :
     node _T_9193 = and(_T_9190, _T_9192) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9194 = or(_T_9193, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9195 = bits(_T_9194, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_4 = mux(_T_9195, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9196 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9197 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9198 = eq(_T_9197, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43184,7 +43184,7 @@ circuit el2_swerv_wrapper :
     node _T_9202 = and(_T_9199, _T_9201) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9203 = or(_T_9202, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9204 = bits(_T_9203, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_5 = mux(_T_9204, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9205 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9206 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9207 = eq(_T_9206, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43194,7 +43194,7 @@ circuit el2_swerv_wrapper :
     node _T_9211 = and(_T_9208, _T_9210) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9212 = or(_T_9211, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9213 = bits(_T_9212, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_6 = mux(_T_9213, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9214 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9215 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9216 = eq(_T_9215, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43204,7 +43204,7 @@ circuit el2_swerv_wrapper :
     node _T_9220 = and(_T_9217, _T_9219) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9221 = or(_T_9220, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9222 = bits(_T_9221, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_7 = mux(_T_9222, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9223 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9224 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9225 = eq(_T_9224, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43214,7 +43214,7 @@ circuit el2_swerv_wrapper :
     node _T_9229 = and(_T_9226, _T_9228) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9230 = or(_T_9229, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9231 = bits(_T_9230, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_8 = mux(_T_9231, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9232 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9233 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9234 = eq(_T_9233, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43224,7 +43224,7 @@ circuit el2_swerv_wrapper :
     node _T_9238 = and(_T_9235, _T_9237) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9239 = or(_T_9238, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9240 = bits(_T_9239, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_9 = mux(_T_9240, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9241 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9242 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9243 = eq(_T_9242, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43234,7 +43234,7 @@ circuit el2_swerv_wrapper :
     node _T_9247 = and(_T_9244, _T_9246) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9248 = or(_T_9247, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9249 = bits(_T_9248, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_10 = mux(_T_9249, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9250 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9251 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9252 = eq(_T_9251, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43244,7 +43244,7 @@ circuit el2_swerv_wrapper :
     node _T_9256 = and(_T_9253, _T_9255) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9257 = or(_T_9256, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9258 = bits(_T_9257, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_11 = mux(_T_9258, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9259 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9260 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9261 = eq(_T_9260, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43254,7 +43254,7 @@ circuit el2_swerv_wrapper :
     node _T_9265 = and(_T_9262, _T_9264) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9266 = or(_T_9265, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9267 = bits(_T_9266, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_12 = mux(_T_9267, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9268 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9269 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9270 = eq(_T_9269, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43264,7 +43264,7 @@ circuit el2_swerv_wrapper :
     node _T_9274 = and(_T_9271, _T_9273) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9275 = or(_T_9274, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9276 = bits(_T_9275, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_13 = mux(_T_9276, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9277 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9278 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9279 = eq(_T_9278, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43274,7 +43274,7 @@ circuit el2_swerv_wrapper :
     node _T_9283 = and(_T_9280, _T_9282) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9284 = or(_T_9283, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9285 = bits(_T_9284, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_14 = mux(_T_9285, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9286 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9287 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9288 = eq(_T_9287, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43284,7 +43284,7 @@ circuit el2_swerv_wrapper :
     node _T_9292 = and(_T_9289, _T_9291) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9293 = or(_T_9292, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9294 = bits(_T_9293, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_2_15 = mux(_T_9294, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9295 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9296 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9297 = eq(_T_9296, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43294,7 +43294,7 @@ circuit el2_swerv_wrapper :
     node _T_9301 = and(_T_9298, _T_9300) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9302 = or(_T_9301, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9303 = bits(_T_9302, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_0 = mux(_T_9303, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9304 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9305 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9306 = eq(_T_9305, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43304,7 +43304,7 @@ circuit el2_swerv_wrapper :
     node _T_9310 = and(_T_9307, _T_9309) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9311 = or(_T_9310, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9312 = bits(_T_9311, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_1 = mux(_T_9312, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9313 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9314 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9315 = eq(_T_9314, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43314,7 +43314,7 @@ circuit el2_swerv_wrapper :
     node _T_9319 = and(_T_9316, _T_9318) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9320 = or(_T_9319, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9321 = bits(_T_9320, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_2 = mux(_T_9321, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9322 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9323 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9324 = eq(_T_9323, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43324,7 +43324,7 @@ circuit el2_swerv_wrapper :
     node _T_9328 = and(_T_9325, _T_9327) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9329 = or(_T_9328, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9330 = bits(_T_9329, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_3 = mux(_T_9330, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9331 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9332 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9333 = eq(_T_9332, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43334,7 +43334,7 @@ circuit el2_swerv_wrapper :
     node _T_9337 = and(_T_9334, _T_9336) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9338 = or(_T_9337, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9339 = bits(_T_9338, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_4 = mux(_T_9339, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9340 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9341 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9342 = eq(_T_9341, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43344,7 +43344,7 @@ circuit el2_swerv_wrapper :
     node _T_9346 = and(_T_9343, _T_9345) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9347 = or(_T_9346, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9348 = bits(_T_9347, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_5 = mux(_T_9348, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9349 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9350 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9351 = eq(_T_9350, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43354,7 +43354,7 @@ circuit el2_swerv_wrapper :
     node _T_9355 = and(_T_9352, _T_9354) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9356 = or(_T_9355, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9357 = bits(_T_9356, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_6 = mux(_T_9357, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9358 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9359 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9360 = eq(_T_9359, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43364,7 +43364,7 @@ circuit el2_swerv_wrapper :
     node _T_9364 = and(_T_9361, _T_9363) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9365 = or(_T_9364, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9366 = bits(_T_9365, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_7 = mux(_T_9366, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9367 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9368 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9369 = eq(_T_9368, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43374,7 +43374,7 @@ circuit el2_swerv_wrapper :
     node _T_9373 = and(_T_9370, _T_9372) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9374 = or(_T_9373, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9375 = bits(_T_9374, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_8 = mux(_T_9375, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9376 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9377 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9378 = eq(_T_9377, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43384,7 +43384,7 @@ circuit el2_swerv_wrapper :
     node _T_9382 = and(_T_9379, _T_9381) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9383 = or(_T_9382, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9384 = bits(_T_9383, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_9 = mux(_T_9384, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9385 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9386 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9387 = eq(_T_9386, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43394,7 +43394,7 @@ circuit el2_swerv_wrapper :
     node _T_9391 = and(_T_9388, _T_9390) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9392 = or(_T_9391, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9393 = bits(_T_9392, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_10 = mux(_T_9393, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9394 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9395 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9396 = eq(_T_9395, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43404,7 +43404,7 @@ circuit el2_swerv_wrapper :
     node _T_9400 = and(_T_9397, _T_9399) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9401 = or(_T_9400, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9402 = bits(_T_9401, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_11 = mux(_T_9402, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9403 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9404 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9405 = eq(_T_9404, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43414,7 +43414,7 @@ circuit el2_swerv_wrapper :
     node _T_9409 = and(_T_9406, _T_9408) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9410 = or(_T_9409, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9411 = bits(_T_9410, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_12 = mux(_T_9411, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9412 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9413 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9414 = eq(_T_9413, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43424,7 +43424,7 @@ circuit el2_swerv_wrapper :
     node _T_9418 = and(_T_9415, _T_9417) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9419 = or(_T_9418, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9420 = bits(_T_9419, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_13 = mux(_T_9420, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9421 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9422 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9423 = eq(_T_9422, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43434,7 +43434,7 @@ circuit el2_swerv_wrapper :
     node _T_9427 = and(_T_9424, _T_9426) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9428 = or(_T_9427, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9429 = bits(_T_9428, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_14 = mux(_T_9429, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9430 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9431 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9432 = eq(_T_9431, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43444,7 +43444,7 @@ circuit el2_swerv_wrapper :
     node _T_9436 = and(_T_9433, _T_9435) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9437 = or(_T_9436, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9438 = bits(_T_9437, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_3_15 = mux(_T_9438, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9439 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9440 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9441 = eq(_T_9440, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43454,7 +43454,7 @@ circuit el2_swerv_wrapper :
     node _T_9445 = and(_T_9442, _T_9444) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9446 = or(_T_9445, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9447 = bits(_T_9446, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_0 = mux(_T_9447, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9448 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9449 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9450 = eq(_T_9449, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43464,7 +43464,7 @@ circuit el2_swerv_wrapper :
     node _T_9454 = and(_T_9451, _T_9453) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9455 = or(_T_9454, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9456 = bits(_T_9455, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_1 = mux(_T_9456, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9457 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9458 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9459 = eq(_T_9458, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43474,7 +43474,7 @@ circuit el2_swerv_wrapper :
     node _T_9463 = and(_T_9460, _T_9462) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9464 = or(_T_9463, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9465 = bits(_T_9464, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_2 = mux(_T_9465, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9466 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9467 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9468 = eq(_T_9467, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43484,7 +43484,7 @@ circuit el2_swerv_wrapper :
     node _T_9472 = and(_T_9469, _T_9471) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9473 = or(_T_9472, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9474 = bits(_T_9473, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_3 = mux(_T_9474, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9475 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9476 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9477 = eq(_T_9476, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43494,7 +43494,7 @@ circuit el2_swerv_wrapper :
     node _T_9481 = and(_T_9478, _T_9480) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9482 = or(_T_9481, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9483 = bits(_T_9482, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_4 = mux(_T_9483, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9484 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9485 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9486 = eq(_T_9485, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43504,7 +43504,7 @@ circuit el2_swerv_wrapper :
     node _T_9490 = and(_T_9487, _T_9489) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9491 = or(_T_9490, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9492 = bits(_T_9491, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_5 = mux(_T_9492, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9493 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9494 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9495 = eq(_T_9494, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43514,7 +43514,7 @@ circuit el2_swerv_wrapper :
     node _T_9499 = and(_T_9496, _T_9498) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9500 = or(_T_9499, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9501 = bits(_T_9500, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_6 = mux(_T_9501, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9502 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9503 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9504 = eq(_T_9503, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43524,7 +43524,7 @@ circuit el2_swerv_wrapper :
     node _T_9508 = and(_T_9505, _T_9507) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9509 = or(_T_9508, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9510 = bits(_T_9509, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_7 = mux(_T_9510, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9511 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9512 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9513 = eq(_T_9512, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43534,7 +43534,7 @@ circuit el2_swerv_wrapper :
     node _T_9517 = and(_T_9514, _T_9516) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9518 = or(_T_9517, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9519 = bits(_T_9518, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_8 = mux(_T_9519, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9520 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9521 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9522 = eq(_T_9521, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43544,7 +43544,7 @@ circuit el2_swerv_wrapper :
     node _T_9526 = and(_T_9523, _T_9525) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9527 = or(_T_9526, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9528 = bits(_T_9527, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_9 = mux(_T_9528, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9529 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9530 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9531 = eq(_T_9530, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43554,7 +43554,7 @@ circuit el2_swerv_wrapper :
     node _T_9535 = and(_T_9532, _T_9534) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9536 = or(_T_9535, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9537 = bits(_T_9536, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_10 = mux(_T_9537, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9538 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9539 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9540 = eq(_T_9539, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43564,7 +43564,7 @@ circuit el2_swerv_wrapper :
     node _T_9544 = and(_T_9541, _T_9543) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9545 = or(_T_9544, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9546 = bits(_T_9545, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_11 = mux(_T_9546, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9547 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9548 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9549 = eq(_T_9548, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43574,7 +43574,7 @@ circuit el2_swerv_wrapper :
     node _T_9553 = and(_T_9550, _T_9552) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9554 = or(_T_9553, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9555 = bits(_T_9554, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_12 = mux(_T_9555, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9556 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9557 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9558 = eq(_T_9557, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43584,7 +43584,7 @@ circuit el2_swerv_wrapper :
     node _T_9562 = and(_T_9559, _T_9561) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9563 = or(_T_9562, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9564 = bits(_T_9563, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_13 = mux(_T_9564, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9565 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9566 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9567 = eq(_T_9566, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43594,7 +43594,7 @@ circuit el2_swerv_wrapper :
     node _T_9571 = and(_T_9568, _T_9570) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9572 = or(_T_9571, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9573 = bits(_T_9572, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_14 = mux(_T_9573, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9574 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9575 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9576 = eq(_T_9575, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43604,7 +43604,7 @@ circuit el2_swerv_wrapper :
     node _T_9580 = and(_T_9577, _T_9579) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9581 = or(_T_9580, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9582 = bits(_T_9581, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_4_15 = mux(_T_9582, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9583 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9584 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9585 = eq(_T_9584, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43614,7 +43614,7 @@ circuit el2_swerv_wrapper :
     node _T_9589 = and(_T_9586, _T_9588) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9590 = or(_T_9589, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9591 = bits(_T_9590, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_0 = mux(_T_9591, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9592 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9593 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9594 = eq(_T_9593, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43624,7 +43624,7 @@ circuit el2_swerv_wrapper :
     node _T_9598 = and(_T_9595, _T_9597) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9599 = or(_T_9598, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9600 = bits(_T_9599, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_1 = mux(_T_9600, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9601 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9602 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9603 = eq(_T_9602, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43634,7 +43634,7 @@ circuit el2_swerv_wrapper :
     node _T_9607 = and(_T_9604, _T_9606) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9608 = or(_T_9607, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9609 = bits(_T_9608, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_2 = mux(_T_9609, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9610 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9611 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9612 = eq(_T_9611, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43644,7 +43644,7 @@ circuit el2_swerv_wrapper :
     node _T_9616 = and(_T_9613, _T_9615) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9617 = or(_T_9616, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9618 = bits(_T_9617, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_3 = mux(_T_9618, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9619 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9620 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9621 = eq(_T_9620, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43654,7 +43654,7 @@ circuit el2_swerv_wrapper :
     node _T_9625 = and(_T_9622, _T_9624) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9626 = or(_T_9625, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9627 = bits(_T_9626, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_4 = mux(_T_9627, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9628 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9629 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9630 = eq(_T_9629, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43664,7 +43664,7 @@ circuit el2_swerv_wrapper :
     node _T_9634 = and(_T_9631, _T_9633) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9635 = or(_T_9634, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9636 = bits(_T_9635, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_5 = mux(_T_9636, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9637 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9638 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9639 = eq(_T_9638, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43674,7 +43674,7 @@ circuit el2_swerv_wrapper :
     node _T_9643 = and(_T_9640, _T_9642) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9644 = or(_T_9643, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9645 = bits(_T_9644, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_6 = mux(_T_9645, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9646 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9647 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9648 = eq(_T_9647, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43684,7 +43684,7 @@ circuit el2_swerv_wrapper :
     node _T_9652 = and(_T_9649, _T_9651) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9653 = or(_T_9652, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9654 = bits(_T_9653, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_7 = mux(_T_9654, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9655 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9656 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9657 = eq(_T_9656, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43694,7 +43694,7 @@ circuit el2_swerv_wrapper :
     node _T_9661 = and(_T_9658, _T_9660) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9662 = or(_T_9661, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9663 = bits(_T_9662, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_8 = mux(_T_9663, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9664 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9665 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9666 = eq(_T_9665, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43704,7 +43704,7 @@ circuit el2_swerv_wrapper :
     node _T_9670 = and(_T_9667, _T_9669) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9671 = or(_T_9670, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9672 = bits(_T_9671, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_9 = mux(_T_9672, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9673 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9674 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9675 = eq(_T_9674, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43714,7 +43714,7 @@ circuit el2_swerv_wrapper :
     node _T_9679 = and(_T_9676, _T_9678) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9680 = or(_T_9679, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9681 = bits(_T_9680, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_10 = mux(_T_9681, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9682 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9683 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9684 = eq(_T_9683, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43724,7 +43724,7 @@ circuit el2_swerv_wrapper :
     node _T_9688 = and(_T_9685, _T_9687) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9689 = or(_T_9688, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9690 = bits(_T_9689, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_11 = mux(_T_9690, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9691 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9692 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9693 = eq(_T_9692, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43734,7 +43734,7 @@ circuit el2_swerv_wrapper :
     node _T_9697 = and(_T_9694, _T_9696) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9698 = or(_T_9697, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9699 = bits(_T_9698, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_12 = mux(_T_9699, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9700 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9701 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9702 = eq(_T_9701, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43744,7 +43744,7 @@ circuit el2_swerv_wrapper :
     node _T_9706 = and(_T_9703, _T_9705) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9707 = or(_T_9706, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9708 = bits(_T_9707, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_13 = mux(_T_9708, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9709 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9710 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9711 = eq(_T_9710, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43754,7 +43754,7 @@ circuit el2_swerv_wrapper :
     node _T_9715 = and(_T_9712, _T_9714) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9716 = or(_T_9715, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9717 = bits(_T_9716, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_14 = mux(_T_9717, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9718 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9719 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9720 = eq(_T_9719, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43764,7 +43764,7 @@ circuit el2_swerv_wrapper :
     node _T_9724 = and(_T_9721, _T_9723) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9725 = or(_T_9724, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9726 = bits(_T_9725, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_5_15 = mux(_T_9726, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9727 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9728 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9729 = eq(_T_9728, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43774,7 +43774,7 @@ circuit el2_swerv_wrapper :
     node _T_9733 = and(_T_9730, _T_9732) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9734 = or(_T_9733, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9735 = bits(_T_9734, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_0 = mux(_T_9735, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9736 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9737 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9738 = eq(_T_9737, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43784,7 +43784,7 @@ circuit el2_swerv_wrapper :
     node _T_9742 = and(_T_9739, _T_9741) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9743 = or(_T_9742, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9744 = bits(_T_9743, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_1 = mux(_T_9744, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9745 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9746 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9747 = eq(_T_9746, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43794,7 +43794,7 @@ circuit el2_swerv_wrapper :
     node _T_9751 = and(_T_9748, _T_9750) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9752 = or(_T_9751, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9753 = bits(_T_9752, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_2 = mux(_T_9753, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9754 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9755 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9756 = eq(_T_9755, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43804,7 +43804,7 @@ circuit el2_swerv_wrapper :
     node _T_9760 = and(_T_9757, _T_9759) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9761 = or(_T_9760, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9762 = bits(_T_9761, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_3 = mux(_T_9762, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9763 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9764 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9765 = eq(_T_9764, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43814,7 +43814,7 @@ circuit el2_swerv_wrapper :
     node _T_9769 = and(_T_9766, _T_9768) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9770 = or(_T_9769, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9771 = bits(_T_9770, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_4 = mux(_T_9771, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9772 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9773 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9774 = eq(_T_9773, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43824,7 +43824,7 @@ circuit el2_swerv_wrapper :
     node _T_9778 = and(_T_9775, _T_9777) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9779 = or(_T_9778, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9780 = bits(_T_9779, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_5 = mux(_T_9780, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9781 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9782 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9783 = eq(_T_9782, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43834,7 +43834,7 @@ circuit el2_swerv_wrapper :
     node _T_9787 = and(_T_9784, _T_9786) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9788 = or(_T_9787, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9789 = bits(_T_9788, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_6 = mux(_T_9789, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9790 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9791 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9792 = eq(_T_9791, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43844,7 +43844,7 @@ circuit el2_swerv_wrapper :
     node _T_9796 = and(_T_9793, _T_9795) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9797 = or(_T_9796, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9798 = bits(_T_9797, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_7 = mux(_T_9798, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9799 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9800 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9801 = eq(_T_9800, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43854,7 +43854,7 @@ circuit el2_swerv_wrapper :
     node _T_9805 = and(_T_9802, _T_9804) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9806 = or(_T_9805, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9807 = bits(_T_9806, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_8 = mux(_T_9807, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9808 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9809 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9810 = eq(_T_9809, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43864,7 +43864,7 @@ circuit el2_swerv_wrapper :
     node _T_9814 = and(_T_9811, _T_9813) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9815 = or(_T_9814, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9816 = bits(_T_9815, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_9 = mux(_T_9816, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9817 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9818 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9819 = eq(_T_9818, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43874,7 +43874,7 @@ circuit el2_swerv_wrapper :
     node _T_9823 = and(_T_9820, _T_9822) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9824 = or(_T_9823, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9825 = bits(_T_9824, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_10 = mux(_T_9825, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9826 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9827 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9828 = eq(_T_9827, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43884,7 +43884,7 @@ circuit el2_swerv_wrapper :
     node _T_9832 = and(_T_9829, _T_9831) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9833 = or(_T_9832, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9834 = bits(_T_9833, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_11 = mux(_T_9834, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9835 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9836 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9837 = eq(_T_9836, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43894,7 +43894,7 @@ circuit el2_swerv_wrapper :
     node _T_9841 = and(_T_9838, _T_9840) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9842 = or(_T_9841, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9843 = bits(_T_9842, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_12 = mux(_T_9843, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9844 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9845 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9846 = eq(_T_9845, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43904,7 +43904,7 @@ circuit el2_swerv_wrapper :
     node _T_9850 = and(_T_9847, _T_9849) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9851 = or(_T_9850, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9852 = bits(_T_9851, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_13 = mux(_T_9852, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9853 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9854 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9855 = eq(_T_9854, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43914,7 +43914,7 @@ circuit el2_swerv_wrapper :
     node _T_9859 = and(_T_9856, _T_9858) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9860 = or(_T_9859, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9861 = bits(_T_9860, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_14 = mux(_T_9861, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9862 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9863 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9864 = eq(_T_9863, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43924,7 +43924,7 @@ circuit el2_swerv_wrapper :
     node _T_9868 = and(_T_9865, _T_9867) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9869 = or(_T_9868, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9870 = bits(_T_9869, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_6_15 = mux(_T_9870, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9871 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9872 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9873 = eq(_T_9872, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43934,7 +43934,7 @@ circuit el2_swerv_wrapper :
     node _T_9877 = and(_T_9874, _T_9876) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9878 = or(_T_9877, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9879 = bits(_T_9878, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_0 = mux(_T_9879, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9880 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9881 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9882 = eq(_T_9881, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43944,7 +43944,7 @@ circuit el2_swerv_wrapper :
     node _T_9886 = and(_T_9883, _T_9885) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9887 = or(_T_9886, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9888 = bits(_T_9887, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_1 = mux(_T_9888, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9889 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9890 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9891 = eq(_T_9890, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43954,7 +43954,7 @@ circuit el2_swerv_wrapper :
     node _T_9895 = and(_T_9892, _T_9894) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9896 = or(_T_9895, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9897 = bits(_T_9896, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_2 = mux(_T_9897, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9898 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9899 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9900 = eq(_T_9899, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43964,7 +43964,7 @@ circuit el2_swerv_wrapper :
     node _T_9904 = and(_T_9901, _T_9903) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9905 = or(_T_9904, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9906 = bits(_T_9905, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_3 = mux(_T_9906, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9907 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9908 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9909 = eq(_T_9908, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43974,7 +43974,7 @@ circuit el2_swerv_wrapper :
     node _T_9913 = and(_T_9910, _T_9912) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9914 = or(_T_9913, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9915 = bits(_T_9914, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_4 = mux(_T_9915, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9916 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9917 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9918 = eq(_T_9917, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43984,7 +43984,7 @@ circuit el2_swerv_wrapper :
     node _T_9922 = and(_T_9919, _T_9921) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9923 = or(_T_9922, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9924 = bits(_T_9923, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_5 = mux(_T_9924, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9925 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9926 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9927 = eq(_T_9926, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -43994,7 +43994,7 @@ circuit el2_swerv_wrapper :
     node _T_9931 = and(_T_9928, _T_9930) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9932 = or(_T_9931, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9933 = bits(_T_9932, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_6 = mux(_T_9933, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9934 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9935 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9936 = eq(_T_9935, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44004,7 +44004,7 @@ circuit el2_swerv_wrapper :
     node _T_9940 = and(_T_9937, _T_9939) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9941 = or(_T_9940, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9942 = bits(_T_9941, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_7 = mux(_T_9942, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9943 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9944 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9945 = eq(_T_9944, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44014,7 +44014,7 @@ circuit el2_swerv_wrapper :
     node _T_9949 = and(_T_9946, _T_9948) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9950 = or(_T_9949, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9951 = bits(_T_9950, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_8 = mux(_T_9951, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9952 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9953 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9954 = eq(_T_9953, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44024,7 +44024,7 @@ circuit el2_swerv_wrapper :
     node _T_9958 = and(_T_9955, _T_9957) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9959 = or(_T_9958, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9960 = bits(_T_9959, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_9 = mux(_T_9960, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9961 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9962 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9963 = eq(_T_9962, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44034,7 +44034,7 @@ circuit el2_swerv_wrapper :
     node _T_9967 = and(_T_9964, _T_9966) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9968 = or(_T_9967, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9969 = bits(_T_9968, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_10 = mux(_T_9969, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9970 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9971 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9972 = eq(_T_9971, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44044,7 +44044,7 @@ circuit el2_swerv_wrapper :
     node _T_9976 = and(_T_9973, _T_9975) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9977 = or(_T_9976, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9978 = bits(_T_9977, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_11 = mux(_T_9978, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9979 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9980 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9981 = eq(_T_9980, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44054,7 +44054,7 @@ circuit el2_swerv_wrapper :
     node _T_9985 = and(_T_9982, _T_9984) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9986 = or(_T_9985, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9987 = bits(_T_9986, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_12 = mux(_T_9987, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9988 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9989 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9990 = eq(_T_9989, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44064,7 +44064,7 @@ circuit el2_swerv_wrapper :
     node _T_9994 = and(_T_9991, _T_9993) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_9995 = or(_T_9994, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_9996 = bits(_T_9995, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_13 = mux(_T_9996, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_9997 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_9998 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_9999 = eq(_T_9998, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44074,7 +44074,7 @@ circuit el2_swerv_wrapper :
     node _T_10003 = and(_T_10000, _T_10002) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10004 = or(_T_10003, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10005 = bits(_T_10004, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_14 = mux(_T_10005, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10006 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10007 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10008 = eq(_T_10007, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44084,7 +44084,7 @@ circuit el2_swerv_wrapper :
     node _T_10012 = and(_T_10009, _T_10011) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10013 = or(_T_10012, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10014 = bits(_T_10013, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_7_15 = mux(_T_10014, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10015 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10016 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10017 = eq(_T_10016, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44094,7 +44094,7 @@ circuit el2_swerv_wrapper :
     node _T_10021 = and(_T_10018, _T_10020) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10022 = or(_T_10021, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10023 = bits(_T_10022, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_0 = mux(_T_10023, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10024 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10025 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10026 = eq(_T_10025, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44104,7 +44104,7 @@ circuit el2_swerv_wrapper :
     node _T_10030 = and(_T_10027, _T_10029) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10031 = or(_T_10030, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10032 = bits(_T_10031, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_1 = mux(_T_10032, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10033 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10034 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10035 = eq(_T_10034, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44114,7 +44114,7 @@ circuit el2_swerv_wrapper :
     node _T_10039 = and(_T_10036, _T_10038) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10040 = or(_T_10039, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10041 = bits(_T_10040, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_2 = mux(_T_10041, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10042 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10043 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10044 = eq(_T_10043, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44124,7 +44124,7 @@ circuit el2_swerv_wrapper :
     node _T_10048 = and(_T_10045, _T_10047) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10049 = or(_T_10048, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10050 = bits(_T_10049, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_3 = mux(_T_10050, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10051 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10052 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10053 = eq(_T_10052, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44134,7 +44134,7 @@ circuit el2_swerv_wrapper :
     node _T_10057 = and(_T_10054, _T_10056) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10058 = or(_T_10057, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10059 = bits(_T_10058, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_4 = mux(_T_10059, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10060 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10061 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10062 = eq(_T_10061, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44144,7 +44144,7 @@ circuit el2_swerv_wrapper :
     node _T_10066 = and(_T_10063, _T_10065) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10067 = or(_T_10066, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10068 = bits(_T_10067, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_5 = mux(_T_10068, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10069 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10070 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10071 = eq(_T_10070, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44154,7 +44154,7 @@ circuit el2_swerv_wrapper :
     node _T_10075 = and(_T_10072, _T_10074) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10076 = or(_T_10075, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10077 = bits(_T_10076, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_6 = mux(_T_10077, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10078 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10079 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10080 = eq(_T_10079, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44164,7 +44164,7 @@ circuit el2_swerv_wrapper :
     node _T_10084 = and(_T_10081, _T_10083) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10085 = or(_T_10084, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10086 = bits(_T_10085, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_7 = mux(_T_10086, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10087 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10088 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10089 = eq(_T_10088, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44174,7 +44174,7 @@ circuit el2_swerv_wrapper :
     node _T_10093 = and(_T_10090, _T_10092) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10094 = or(_T_10093, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10095 = bits(_T_10094, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_8 = mux(_T_10095, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10096 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10097 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10098 = eq(_T_10097, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44184,7 +44184,7 @@ circuit el2_swerv_wrapper :
     node _T_10102 = and(_T_10099, _T_10101) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10103 = or(_T_10102, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10104 = bits(_T_10103, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_9 = mux(_T_10104, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10105 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10106 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10107 = eq(_T_10106, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44194,7 +44194,7 @@ circuit el2_swerv_wrapper :
     node _T_10111 = and(_T_10108, _T_10110) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10112 = or(_T_10111, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10113 = bits(_T_10112, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_10 = mux(_T_10113, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10114 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10115 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10116 = eq(_T_10115, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44204,7 +44204,7 @@ circuit el2_swerv_wrapper :
     node _T_10120 = and(_T_10117, _T_10119) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10121 = or(_T_10120, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10122 = bits(_T_10121, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_11 = mux(_T_10122, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10123 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10124 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10125 = eq(_T_10124, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44214,7 +44214,7 @@ circuit el2_swerv_wrapper :
     node _T_10129 = and(_T_10126, _T_10128) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10130 = or(_T_10129, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10131 = bits(_T_10130, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_12 = mux(_T_10131, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10132 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10133 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10134 = eq(_T_10133, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44224,7 +44224,7 @@ circuit el2_swerv_wrapper :
     node _T_10138 = and(_T_10135, _T_10137) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10139 = or(_T_10138, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10140 = bits(_T_10139, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_13 = mux(_T_10140, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10141 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10142 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10143 = eq(_T_10142, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44234,7 +44234,7 @@ circuit el2_swerv_wrapper :
     node _T_10147 = and(_T_10144, _T_10146) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10148 = or(_T_10147, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10149 = bits(_T_10148, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_14 = mux(_T_10149, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10150 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10151 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10152 = eq(_T_10151, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44244,7 +44244,7 @@ circuit el2_swerv_wrapper :
     node _T_10156 = and(_T_10153, _T_10155) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10157 = or(_T_10156, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10158 = bits(_T_10157, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_8_15 = mux(_T_10158, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10159 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10160 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10161 = eq(_T_10160, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44254,7 +44254,7 @@ circuit el2_swerv_wrapper :
     node _T_10165 = and(_T_10162, _T_10164) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10166 = or(_T_10165, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10167 = bits(_T_10166, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_0 = mux(_T_10167, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10168 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10169 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10170 = eq(_T_10169, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44264,7 +44264,7 @@ circuit el2_swerv_wrapper :
     node _T_10174 = and(_T_10171, _T_10173) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10175 = or(_T_10174, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10176 = bits(_T_10175, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_1 = mux(_T_10176, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10177 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10178 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10179 = eq(_T_10178, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44274,7 +44274,7 @@ circuit el2_swerv_wrapper :
     node _T_10183 = and(_T_10180, _T_10182) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10184 = or(_T_10183, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10185 = bits(_T_10184, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_2 = mux(_T_10185, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10186 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10187 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10188 = eq(_T_10187, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44284,7 +44284,7 @@ circuit el2_swerv_wrapper :
     node _T_10192 = and(_T_10189, _T_10191) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10193 = or(_T_10192, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10194 = bits(_T_10193, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_3 = mux(_T_10194, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10195 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10196 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10197 = eq(_T_10196, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44294,7 +44294,7 @@ circuit el2_swerv_wrapper :
     node _T_10201 = and(_T_10198, _T_10200) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10202 = or(_T_10201, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10203 = bits(_T_10202, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_4 = mux(_T_10203, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10204 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10205 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10206 = eq(_T_10205, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44304,7 +44304,7 @@ circuit el2_swerv_wrapper :
     node _T_10210 = and(_T_10207, _T_10209) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10211 = or(_T_10210, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10212 = bits(_T_10211, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_5 = mux(_T_10212, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10213 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10214 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10215 = eq(_T_10214, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44314,7 +44314,7 @@ circuit el2_swerv_wrapper :
     node _T_10219 = and(_T_10216, _T_10218) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10220 = or(_T_10219, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10221 = bits(_T_10220, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_6 = mux(_T_10221, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10222 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10223 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10224 = eq(_T_10223, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44324,7 +44324,7 @@ circuit el2_swerv_wrapper :
     node _T_10228 = and(_T_10225, _T_10227) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10229 = or(_T_10228, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10230 = bits(_T_10229, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_7 = mux(_T_10230, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10231 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10232 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10233 = eq(_T_10232, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44334,7 +44334,7 @@ circuit el2_swerv_wrapper :
     node _T_10237 = and(_T_10234, _T_10236) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10238 = or(_T_10237, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10239 = bits(_T_10238, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_8 = mux(_T_10239, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10240 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10241 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10242 = eq(_T_10241, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44344,7 +44344,7 @@ circuit el2_swerv_wrapper :
     node _T_10246 = and(_T_10243, _T_10245) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10247 = or(_T_10246, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10248 = bits(_T_10247, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_9 = mux(_T_10248, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10249 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10250 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10251 = eq(_T_10250, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44354,7 +44354,7 @@ circuit el2_swerv_wrapper :
     node _T_10255 = and(_T_10252, _T_10254) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10256 = or(_T_10255, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10257 = bits(_T_10256, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_10 = mux(_T_10257, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10258 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10259 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10260 = eq(_T_10259, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44364,7 +44364,7 @@ circuit el2_swerv_wrapper :
     node _T_10264 = and(_T_10261, _T_10263) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10265 = or(_T_10264, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10266 = bits(_T_10265, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_11 = mux(_T_10266, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10267 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10268 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10269 = eq(_T_10268, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44374,7 +44374,7 @@ circuit el2_swerv_wrapper :
     node _T_10273 = and(_T_10270, _T_10272) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10274 = or(_T_10273, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10275 = bits(_T_10274, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_12 = mux(_T_10275, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10276 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10277 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10278 = eq(_T_10277, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44384,7 +44384,7 @@ circuit el2_swerv_wrapper :
     node _T_10282 = and(_T_10279, _T_10281) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10283 = or(_T_10282, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10284 = bits(_T_10283, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_13 = mux(_T_10284, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10285 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10286 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10287 = eq(_T_10286, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44394,7 +44394,7 @@ circuit el2_swerv_wrapper :
     node _T_10291 = and(_T_10288, _T_10290) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10292 = or(_T_10291, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10293 = bits(_T_10292, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_14 = mux(_T_10293, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10294 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10295 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10296 = eq(_T_10295, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44404,7 +44404,7 @@ circuit el2_swerv_wrapper :
     node _T_10300 = and(_T_10297, _T_10299) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10301 = or(_T_10300, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10302 = bits(_T_10301, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_9_15 = mux(_T_10302, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10303 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10304 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10305 = eq(_T_10304, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44414,7 +44414,7 @@ circuit el2_swerv_wrapper :
     node _T_10309 = and(_T_10306, _T_10308) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10310 = or(_T_10309, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10311 = bits(_T_10310, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_0 = mux(_T_10311, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10312 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10313 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10314 = eq(_T_10313, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44424,7 +44424,7 @@ circuit el2_swerv_wrapper :
     node _T_10318 = and(_T_10315, _T_10317) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10319 = or(_T_10318, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10320 = bits(_T_10319, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_1 = mux(_T_10320, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10321 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10322 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10323 = eq(_T_10322, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44434,7 +44434,7 @@ circuit el2_swerv_wrapper :
     node _T_10327 = and(_T_10324, _T_10326) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10328 = or(_T_10327, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10329 = bits(_T_10328, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_2 = mux(_T_10329, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10330 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10331 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10332 = eq(_T_10331, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44444,7 +44444,7 @@ circuit el2_swerv_wrapper :
     node _T_10336 = and(_T_10333, _T_10335) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10337 = or(_T_10336, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10338 = bits(_T_10337, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_3 = mux(_T_10338, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10339 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10340 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10341 = eq(_T_10340, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44454,7 +44454,7 @@ circuit el2_swerv_wrapper :
     node _T_10345 = and(_T_10342, _T_10344) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10346 = or(_T_10345, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10347 = bits(_T_10346, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_4 = mux(_T_10347, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10348 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10349 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10350 = eq(_T_10349, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44464,7 +44464,7 @@ circuit el2_swerv_wrapper :
     node _T_10354 = and(_T_10351, _T_10353) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10355 = or(_T_10354, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10356 = bits(_T_10355, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_5 = mux(_T_10356, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10357 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10358 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10359 = eq(_T_10358, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44474,7 +44474,7 @@ circuit el2_swerv_wrapper :
     node _T_10363 = and(_T_10360, _T_10362) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10364 = or(_T_10363, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10365 = bits(_T_10364, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_6 = mux(_T_10365, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10366 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10367 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10368 = eq(_T_10367, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44484,7 +44484,7 @@ circuit el2_swerv_wrapper :
     node _T_10372 = and(_T_10369, _T_10371) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10373 = or(_T_10372, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10374 = bits(_T_10373, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_7 = mux(_T_10374, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10375 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10376 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10377 = eq(_T_10376, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44494,7 +44494,7 @@ circuit el2_swerv_wrapper :
     node _T_10381 = and(_T_10378, _T_10380) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10382 = or(_T_10381, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10383 = bits(_T_10382, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_8 = mux(_T_10383, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10384 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10385 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10386 = eq(_T_10385, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44504,7 +44504,7 @@ circuit el2_swerv_wrapper :
     node _T_10390 = and(_T_10387, _T_10389) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10391 = or(_T_10390, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10392 = bits(_T_10391, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_9 = mux(_T_10392, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10393 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10394 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10395 = eq(_T_10394, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44514,7 +44514,7 @@ circuit el2_swerv_wrapper :
     node _T_10399 = and(_T_10396, _T_10398) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10400 = or(_T_10399, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10401 = bits(_T_10400, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_10 = mux(_T_10401, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10402 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10403 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10404 = eq(_T_10403, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44524,7 +44524,7 @@ circuit el2_swerv_wrapper :
     node _T_10408 = and(_T_10405, _T_10407) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10409 = or(_T_10408, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10410 = bits(_T_10409, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_11 = mux(_T_10410, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10411 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10412 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10413 = eq(_T_10412, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44534,7 +44534,7 @@ circuit el2_swerv_wrapper :
     node _T_10417 = and(_T_10414, _T_10416) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10418 = or(_T_10417, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10419 = bits(_T_10418, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_12 = mux(_T_10419, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10420 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10421 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10422 = eq(_T_10421, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44544,7 +44544,7 @@ circuit el2_swerv_wrapper :
     node _T_10426 = and(_T_10423, _T_10425) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10427 = or(_T_10426, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10428 = bits(_T_10427, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_13 = mux(_T_10428, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10429 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10430 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10431 = eq(_T_10430, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44554,7 +44554,7 @@ circuit el2_swerv_wrapper :
     node _T_10435 = and(_T_10432, _T_10434) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10436 = or(_T_10435, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10437 = bits(_T_10436, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_14 = mux(_T_10437, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10438 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10439 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10440 = eq(_T_10439, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44564,7 +44564,7 @@ circuit el2_swerv_wrapper :
     node _T_10444 = and(_T_10441, _T_10443) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10445 = or(_T_10444, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10446 = bits(_T_10445, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_10_15 = mux(_T_10446, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10447 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10448 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10449 = eq(_T_10448, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44574,7 +44574,7 @@ circuit el2_swerv_wrapper :
     node _T_10453 = and(_T_10450, _T_10452) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10454 = or(_T_10453, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10455 = bits(_T_10454, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_0 = mux(_T_10455, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10456 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10457 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10458 = eq(_T_10457, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44584,7 +44584,7 @@ circuit el2_swerv_wrapper :
     node _T_10462 = and(_T_10459, _T_10461) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10463 = or(_T_10462, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10464 = bits(_T_10463, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_1 = mux(_T_10464, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10465 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10466 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10467 = eq(_T_10466, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44594,7 +44594,7 @@ circuit el2_swerv_wrapper :
     node _T_10471 = and(_T_10468, _T_10470) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10472 = or(_T_10471, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10473 = bits(_T_10472, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_2 = mux(_T_10473, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10474 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10475 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10476 = eq(_T_10475, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44604,7 +44604,7 @@ circuit el2_swerv_wrapper :
     node _T_10480 = and(_T_10477, _T_10479) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10481 = or(_T_10480, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10482 = bits(_T_10481, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_3 = mux(_T_10482, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10483 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10484 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10485 = eq(_T_10484, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44614,7 +44614,7 @@ circuit el2_swerv_wrapper :
     node _T_10489 = and(_T_10486, _T_10488) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10490 = or(_T_10489, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10491 = bits(_T_10490, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_4 = mux(_T_10491, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10492 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10493 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10494 = eq(_T_10493, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44624,7 +44624,7 @@ circuit el2_swerv_wrapper :
     node _T_10498 = and(_T_10495, _T_10497) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10499 = or(_T_10498, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10500 = bits(_T_10499, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_5 = mux(_T_10500, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10501 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10502 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10503 = eq(_T_10502, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44634,7 +44634,7 @@ circuit el2_swerv_wrapper :
     node _T_10507 = and(_T_10504, _T_10506) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10508 = or(_T_10507, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10509 = bits(_T_10508, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_6 = mux(_T_10509, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10510 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10511 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10512 = eq(_T_10511, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44644,7 +44644,7 @@ circuit el2_swerv_wrapper :
     node _T_10516 = and(_T_10513, _T_10515) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10517 = or(_T_10516, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10518 = bits(_T_10517, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_7 = mux(_T_10518, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10519 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10520 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10521 = eq(_T_10520, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44654,7 +44654,7 @@ circuit el2_swerv_wrapper :
     node _T_10525 = and(_T_10522, _T_10524) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10526 = or(_T_10525, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10527 = bits(_T_10526, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_8 = mux(_T_10527, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10528 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10529 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10530 = eq(_T_10529, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44664,7 +44664,7 @@ circuit el2_swerv_wrapper :
     node _T_10534 = and(_T_10531, _T_10533) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10535 = or(_T_10534, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10536 = bits(_T_10535, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_9 = mux(_T_10536, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10537 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10538 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10539 = eq(_T_10538, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44674,7 +44674,7 @@ circuit el2_swerv_wrapper :
     node _T_10543 = and(_T_10540, _T_10542) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10544 = or(_T_10543, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10545 = bits(_T_10544, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_10 = mux(_T_10545, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10546 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10547 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10548 = eq(_T_10547, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44684,7 +44684,7 @@ circuit el2_swerv_wrapper :
     node _T_10552 = and(_T_10549, _T_10551) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10553 = or(_T_10552, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10554 = bits(_T_10553, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_11 = mux(_T_10554, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10555 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10556 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10557 = eq(_T_10556, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44694,7 +44694,7 @@ circuit el2_swerv_wrapper :
     node _T_10561 = and(_T_10558, _T_10560) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10562 = or(_T_10561, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10563 = bits(_T_10562, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_12 = mux(_T_10563, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10564 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10565 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10566 = eq(_T_10565, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44704,7 +44704,7 @@ circuit el2_swerv_wrapper :
     node _T_10570 = and(_T_10567, _T_10569) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10571 = or(_T_10570, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10572 = bits(_T_10571, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_13 = mux(_T_10572, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10573 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10574 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10575 = eq(_T_10574, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44714,7 +44714,7 @@ circuit el2_swerv_wrapper :
     node _T_10579 = and(_T_10576, _T_10578) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10580 = or(_T_10579, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10581 = bits(_T_10580, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_14 = mux(_T_10581, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10582 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10583 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10584 = eq(_T_10583, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44724,7 +44724,7 @@ circuit el2_swerv_wrapper :
     node _T_10588 = and(_T_10585, _T_10587) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10589 = or(_T_10588, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10590 = bits(_T_10589, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_11_15 = mux(_T_10590, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10591 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10592 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10593 = eq(_T_10592, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44734,7 +44734,7 @@ circuit el2_swerv_wrapper :
     node _T_10597 = and(_T_10594, _T_10596) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10598 = or(_T_10597, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10599 = bits(_T_10598, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_0 = mux(_T_10599, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10600 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10601 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10602 = eq(_T_10601, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44744,7 +44744,7 @@ circuit el2_swerv_wrapper :
     node _T_10606 = and(_T_10603, _T_10605) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10607 = or(_T_10606, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10608 = bits(_T_10607, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_1 = mux(_T_10608, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10609 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10610 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10611 = eq(_T_10610, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44754,7 +44754,7 @@ circuit el2_swerv_wrapper :
     node _T_10615 = and(_T_10612, _T_10614) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10616 = or(_T_10615, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10617 = bits(_T_10616, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_2 = mux(_T_10617, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10618 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10619 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10620 = eq(_T_10619, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44764,7 +44764,7 @@ circuit el2_swerv_wrapper :
     node _T_10624 = and(_T_10621, _T_10623) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10625 = or(_T_10624, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10626 = bits(_T_10625, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_3 = mux(_T_10626, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10627 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10628 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10629 = eq(_T_10628, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44774,7 +44774,7 @@ circuit el2_swerv_wrapper :
     node _T_10633 = and(_T_10630, _T_10632) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10634 = or(_T_10633, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10635 = bits(_T_10634, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_4 = mux(_T_10635, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10636 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10637 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10638 = eq(_T_10637, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44784,7 +44784,7 @@ circuit el2_swerv_wrapper :
     node _T_10642 = and(_T_10639, _T_10641) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10643 = or(_T_10642, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10644 = bits(_T_10643, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_5 = mux(_T_10644, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10645 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10646 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10647 = eq(_T_10646, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44794,7 +44794,7 @@ circuit el2_swerv_wrapper :
     node _T_10651 = and(_T_10648, _T_10650) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10652 = or(_T_10651, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10653 = bits(_T_10652, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_6 = mux(_T_10653, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10654 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10655 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10656 = eq(_T_10655, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44804,7 +44804,7 @@ circuit el2_swerv_wrapper :
     node _T_10660 = and(_T_10657, _T_10659) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10661 = or(_T_10660, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10662 = bits(_T_10661, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_7 = mux(_T_10662, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10663 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10664 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10665 = eq(_T_10664, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44814,7 +44814,7 @@ circuit el2_swerv_wrapper :
     node _T_10669 = and(_T_10666, _T_10668) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10670 = or(_T_10669, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10671 = bits(_T_10670, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_8 = mux(_T_10671, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10672 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10673 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10674 = eq(_T_10673, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44824,7 +44824,7 @@ circuit el2_swerv_wrapper :
     node _T_10678 = and(_T_10675, _T_10677) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10679 = or(_T_10678, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10680 = bits(_T_10679, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_9 = mux(_T_10680, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10681 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10682 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10683 = eq(_T_10682, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44834,7 +44834,7 @@ circuit el2_swerv_wrapper :
     node _T_10687 = and(_T_10684, _T_10686) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10688 = or(_T_10687, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10689 = bits(_T_10688, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_10 = mux(_T_10689, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10690 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10691 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10692 = eq(_T_10691, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44844,7 +44844,7 @@ circuit el2_swerv_wrapper :
     node _T_10696 = and(_T_10693, _T_10695) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10697 = or(_T_10696, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10698 = bits(_T_10697, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_11 = mux(_T_10698, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10699 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10700 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10701 = eq(_T_10700, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44854,7 +44854,7 @@ circuit el2_swerv_wrapper :
     node _T_10705 = and(_T_10702, _T_10704) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10706 = or(_T_10705, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10707 = bits(_T_10706, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_12 = mux(_T_10707, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10708 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10709 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10710 = eq(_T_10709, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44864,7 +44864,7 @@ circuit el2_swerv_wrapper :
     node _T_10714 = and(_T_10711, _T_10713) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10715 = or(_T_10714, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10716 = bits(_T_10715, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_13 = mux(_T_10716, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10717 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10718 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10719 = eq(_T_10718, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44874,7 +44874,7 @@ circuit el2_swerv_wrapper :
     node _T_10723 = and(_T_10720, _T_10722) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10724 = or(_T_10723, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10725 = bits(_T_10724, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_14 = mux(_T_10725, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10726 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10727 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10728 = eq(_T_10727, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44884,7 +44884,7 @@ circuit el2_swerv_wrapper :
     node _T_10732 = and(_T_10729, _T_10731) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10733 = or(_T_10732, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10734 = bits(_T_10733, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_12_15 = mux(_T_10734, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10735 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10736 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10737 = eq(_T_10736, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44894,7 +44894,7 @@ circuit el2_swerv_wrapper :
     node _T_10741 = and(_T_10738, _T_10740) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10742 = or(_T_10741, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10743 = bits(_T_10742, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_0 = mux(_T_10743, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10744 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10745 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10746 = eq(_T_10745, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44904,7 +44904,7 @@ circuit el2_swerv_wrapper :
     node _T_10750 = and(_T_10747, _T_10749) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10751 = or(_T_10750, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10752 = bits(_T_10751, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_1 = mux(_T_10752, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10753 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10754 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10755 = eq(_T_10754, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44914,7 +44914,7 @@ circuit el2_swerv_wrapper :
     node _T_10759 = and(_T_10756, _T_10758) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10760 = or(_T_10759, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10761 = bits(_T_10760, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_2 = mux(_T_10761, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10762 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10763 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10764 = eq(_T_10763, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44924,7 +44924,7 @@ circuit el2_swerv_wrapper :
     node _T_10768 = and(_T_10765, _T_10767) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10769 = or(_T_10768, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10770 = bits(_T_10769, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_3 = mux(_T_10770, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10771 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10772 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10773 = eq(_T_10772, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44934,7 +44934,7 @@ circuit el2_swerv_wrapper :
     node _T_10777 = and(_T_10774, _T_10776) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10778 = or(_T_10777, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10779 = bits(_T_10778, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_4 = mux(_T_10779, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10780 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10781 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10782 = eq(_T_10781, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44944,7 +44944,7 @@ circuit el2_swerv_wrapper :
     node _T_10786 = and(_T_10783, _T_10785) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10787 = or(_T_10786, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10788 = bits(_T_10787, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_5 = mux(_T_10788, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10789 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10790 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10791 = eq(_T_10790, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44954,7 +44954,7 @@ circuit el2_swerv_wrapper :
     node _T_10795 = and(_T_10792, _T_10794) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10796 = or(_T_10795, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10797 = bits(_T_10796, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_6 = mux(_T_10797, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10798 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10799 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10800 = eq(_T_10799, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44964,7 +44964,7 @@ circuit el2_swerv_wrapper :
     node _T_10804 = and(_T_10801, _T_10803) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10805 = or(_T_10804, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10806 = bits(_T_10805, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_7 = mux(_T_10806, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10807 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10808 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10809 = eq(_T_10808, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44974,7 +44974,7 @@ circuit el2_swerv_wrapper :
     node _T_10813 = and(_T_10810, _T_10812) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10814 = or(_T_10813, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10815 = bits(_T_10814, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_8 = mux(_T_10815, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10816 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10817 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10818 = eq(_T_10817, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44984,7 +44984,7 @@ circuit el2_swerv_wrapper :
     node _T_10822 = and(_T_10819, _T_10821) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10823 = or(_T_10822, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10824 = bits(_T_10823, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_9 = mux(_T_10824, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10825 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10826 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10827 = eq(_T_10826, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -44994,7 +44994,7 @@ circuit el2_swerv_wrapper :
     node _T_10831 = and(_T_10828, _T_10830) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10832 = or(_T_10831, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10833 = bits(_T_10832, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_10 = mux(_T_10833, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10834 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10835 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10836 = eq(_T_10835, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45004,7 +45004,7 @@ circuit el2_swerv_wrapper :
     node _T_10840 = and(_T_10837, _T_10839) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10841 = or(_T_10840, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10842 = bits(_T_10841, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_11 = mux(_T_10842, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10843 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10844 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10845 = eq(_T_10844, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45014,7 +45014,7 @@ circuit el2_swerv_wrapper :
     node _T_10849 = and(_T_10846, _T_10848) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10850 = or(_T_10849, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10851 = bits(_T_10850, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_12 = mux(_T_10851, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10852 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10853 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10854 = eq(_T_10853, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45024,7 +45024,7 @@ circuit el2_swerv_wrapper :
     node _T_10858 = and(_T_10855, _T_10857) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10859 = or(_T_10858, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10860 = bits(_T_10859, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_13 = mux(_T_10860, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10861 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10862 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10863 = eq(_T_10862, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45034,7 +45034,7 @@ circuit el2_swerv_wrapper :
     node _T_10867 = and(_T_10864, _T_10866) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10868 = or(_T_10867, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10869 = bits(_T_10868, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_14 = mux(_T_10869, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10870 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10871 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10872 = eq(_T_10871, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45044,7 +45044,7 @@ circuit el2_swerv_wrapper :
     node _T_10876 = and(_T_10873, _T_10875) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10877 = or(_T_10876, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10878 = bits(_T_10877, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_13_15 = mux(_T_10878, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10879 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10880 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10881 = eq(_T_10880, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45054,7 +45054,7 @@ circuit el2_swerv_wrapper :
     node _T_10885 = and(_T_10882, _T_10884) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10886 = or(_T_10885, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10887 = bits(_T_10886, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_0 = mux(_T_10887, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10888 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10889 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10890 = eq(_T_10889, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45064,7 +45064,7 @@ circuit el2_swerv_wrapper :
     node _T_10894 = and(_T_10891, _T_10893) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10895 = or(_T_10894, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10896 = bits(_T_10895, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_1 = mux(_T_10896, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10897 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10898 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10899 = eq(_T_10898, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45074,7 +45074,7 @@ circuit el2_swerv_wrapper :
     node _T_10903 = and(_T_10900, _T_10902) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10904 = or(_T_10903, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10905 = bits(_T_10904, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_2 = mux(_T_10905, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10906 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10907 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10908 = eq(_T_10907, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45084,7 +45084,7 @@ circuit el2_swerv_wrapper :
     node _T_10912 = and(_T_10909, _T_10911) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10913 = or(_T_10912, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10914 = bits(_T_10913, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_3 = mux(_T_10914, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10915 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10916 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10917 = eq(_T_10916, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45094,7 +45094,7 @@ circuit el2_swerv_wrapper :
     node _T_10921 = and(_T_10918, _T_10920) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10922 = or(_T_10921, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10923 = bits(_T_10922, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_4 = mux(_T_10923, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10924 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10925 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10926 = eq(_T_10925, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45104,7 +45104,7 @@ circuit el2_swerv_wrapper :
     node _T_10930 = and(_T_10927, _T_10929) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10931 = or(_T_10930, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10932 = bits(_T_10931, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_5 = mux(_T_10932, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10933 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10934 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10935 = eq(_T_10934, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45114,7 +45114,7 @@ circuit el2_swerv_wrapper :
     node _T_10939 = and(_T_10936, _T_10938) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10940 = or(_T_10939, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10941 = bits(_T_10940, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_6 = mux(_T_10941, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10942 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10943 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10944 = eq(_T_10943, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45124,7 +45124,7 @@ circuit el2_swerv_wrapper :
     node _T_10948 = and(_T_10945, _T_10947) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10949 = or(_T_10948, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10950 = bits(_T_10949, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_7 = mux(_T_10950, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10951 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10952 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10953 = eq(_T_10952, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45134,7 +45134,7 @@ circuit el2_swerv_wrapper :
     node _T_10957 = and(_T_10954, _T_10956) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10958 = or(_T_10957, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10959 = bits(_T_10958, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_8 = mux(_T_10959, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10960 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10961 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10962 = eq(_T_10961, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45144,7 +45144,7 @@ circuit el2_swerv_wrapper :
     node _T_10966 = and(_T_10963, _T_10965) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10967 = or(_T_10966, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10968 = bits(_T_10967, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_9 = mux(_T_10968, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10969 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10970 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10971 = eq(_T_10970, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45154,7 +45154,7 @@ circuit el2_swerv_wrapper :
     node _T_10975 = and(_T_10972, _T_10974) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10976 = or(_T_10975, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10977 = bits(_T_10976, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_10 = mux(_T_10977, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10978 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10979 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10980 = eq(_T_10979, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45164,7 +45164,7 @@ circuit el2_swerv_wrapper :
     node _T_10984 = and(_T_10981, _T_10983) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10985 = or(_T_10984, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10986 = bits(_T_10985, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_11 = mux(_T_10986, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10987 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10988 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10989 = eq(_T_10988, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45174,7 +45174,7 @@ circuit el2_swerv_wrapper :
     node _T_10993 = and(_T_10990, _T_10992) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_10994 = or(_T_10993, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_10995 = bits(_T_10994, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_12 = mux(_T_10995, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_10996 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_10997 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_10998 = eq(_T_10997, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45184,7 +45184,7 @@ circuit el2_swerv_wrapper :
     node _T_11002 = and(_T_10999, _T_11001) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11003 = or(_T_11002, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11004 = bits(_T_11003, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_13 = mux(_T_11004, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11005 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11006 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11007 = eq(_T_11006, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45194,7 +45194,7 @@ circuit el2_swerv_wrapper :
     node _T_11011 = and(_T_11008, _T_11010) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11012 = or(_T_11011, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11013 = bits(_T_11012, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_14 = mux(_T_11013, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11014 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11015 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11016 = eq(_T_11015, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45204,7 +45204,7 @@ circuit el2_swerv_wrapper :
     node _T_11020 = and(_T_11017, _T_11019) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11021 = or(_T_11020, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11022 = bits(_T_11021, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_14_15 = mux(_T_11022, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11023 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11024 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11025 = eq(_T_11024, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45214,7 +45214,7 @@ circuit el2_swerv_wrapper :
     node _T_11029 = and(_T_11026, _T_11028) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11030 = or(_T_11029, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11031 = bits(_T_11030, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_0 = mux(_T_11031, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11032 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11033 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11034 = eq(_T_11033, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45224,7 +45224,7 @@ circuit el2_swerv_wrapper :
     node _T_11038 = and(_T_11035, _T_11037) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11039 = or(_T_11038, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11040 = bits(_T_11039, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_1 = mux(_T_11040, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11041 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11042 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11043 = eq(_T_11042, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45234,7 +45234,7 @@ circuit el2_swerv_wrapper :
     node _T_11047 = and(_T_11044, _T_11046) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11048 = or(_T_11047, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11049 = bits(_T_11048, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_2 = mux(_T_11049, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11050 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11051 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11052 = eq(_T_11051, UInt<2>("h03")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45244,7 +45244,7 @@ circuit el2_swerv_wrapper :
     node _T_11056 = and(_T_11053, _T_11055) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11057 = or(_T_11056, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11058 = bits(_T_11057, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_3 = mux(_T_11058, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11059 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11060 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11061 = eq(_T_11060, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45254,7 +45254,7 @@ circuit el2_swerv_wrapper :
     node _T_11065 = and(_T_11062, _T_11064) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11066 = or(_T_11065, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11067 = bits(_T_11066, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_4 = mux(_T_11067, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11068 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11069 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11070 = eq(_T_11069, UInt<3>("h05")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45264,7 +45264,7 @@ circuit el2_swerv_wrapper :
     node _T_11074 = and(_T_11071, _T_11073) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11075 = or(_T_11074, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11076 = bits(_T_11075, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_5 = mux(_T_11076, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11077 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11078 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11079 = eq(_T_11078, UInt<3>("h06")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45274,7 +45274,7 @@ circuit el2_swerv_wrapper :
     node _T_11083 = and(_T_11080, _T_11082) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11084 = or(_T_11083, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11085 = bits(_T_11084, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_6 = mux(_T_11085, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11086 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11087 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11088 = eq(_T_11087, UInt<3>("h07")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45284,7 +45284,7 @@ circuit el2_swerv_wrapper :
     node _T_11092 = and(_T_11089, _T_11091) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11093 = or(_T_11092, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11094 = bits(_T_11093, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_7 = mux(_T_11094, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11095 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11096 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11097 = eq(_T_11096, UInt<4>("h08")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45294,7 +45294,7 @@ circuit el2_swerv_wrapper :
     node _T_11101 = and(_T_11098, _T_11100) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11102 = or(_T_11101, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11103 = bits(_T_11102, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_8 = mux(_T_11103, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11104 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11105 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11106 = eq(_T_11105, UInt<4>("h09")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45304,7 +45304,7 @@ circuit el2_swerv_wrapper :
     node _T_11110 = and(_T_11107, _T_11109) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11111 = or(_T_11110, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11112 = bits(_T_11111, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_9 = mux(_T_11112, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11113 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11114 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11115 = eq(_T_11114, UInt<4>("h0a")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45314,7 +45314,7 @@ circuit el2_swerv_wrapper :
     node _T_11119 = and(_T_11116, _T_11118) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11120 = or(_T_11119, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11121 = bits(_T_11120, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_10 = mux(_T_11121, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11122 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11123 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11124 = eq(_T_11123, UInt<4>("h0b")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45324,7 +45324,7 @@ circuit el2_swerv_wrapper :
     node _T_11128 = and(_T_11125, _T_11127) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11129 = or(_T_11128, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11130 = bits(_T_11129, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_11 = mux(_T_11130, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11131 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11132 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11133 = eq(_T_11132, UInt<4>("h0c")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45334,7 +45334,7 @@ circuit el2_swerv_wrapper :
     node _T_11137 = and(_T_11134, _T_11136) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11138 = or(_T_11137, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11139 = bits(_T_11138, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_12 = mux(_T_11139, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11140 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11141 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11142 = eq(_T_11141, UInt<4>("h0d")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45344,7 +45344,7 @@ circuit el2_swerv_wrapper :
     node _T_11146 = and(_T_11143, _T_11145) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11147 = or(_T_11146, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11148 = bits(_T_11147, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_13 = mux(_T_11148, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11149 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11150 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11151 = eq(_T_11150, UInt<4>("h0e")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45354,7 +45354,7 @@ circuit el2_swerv_wrapper :
     node _T_11155 = and(_T_11152, _T_11154) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11156 = or(_T_11155, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11157 = bits(_T_11156, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_14 = mux(_T_11157, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     node _T_11158 = bits(bht_wr_en2, 1, 1) @[el2_ifu_bp_ctl.scala 447:20]
     node _T_11159 = bits(br0_hashed_wb, 3, 0) @[el2_ifu_bp_ctl.scala 447:37]
     node _T_11160 = eq(_T_11159, UInt<4>("h0f")) @[el2_ifu_bp_ctl.scala 447:74]
@@ -45364,7 +45364,7 @@ circuit el2_swerv_wrapper :
     node _T_11164 = and(_T_11161, _T_11163) @[el2_ifu_bp_ctl.scala 447:81]
     node _T_11165 = or(_T_11164, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 447:161]
     node _T_11166 = bits(_T_11165, 0, 0) @[el2_ifu_bp_ctl.scala 447:183]
-    node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
+    node bht_bank_wr_data_1_15_15 = mux(_T_11166, io.dec_tlu_br0_r_pkt.bits.hist, io.exu_mp_pkt.bits.hist) @[el2_ifu_bp_ctl.scala 447:8]
     wire bht_bank_sel : UInt<1>[16][16][2] @[el2_ifu_bp_ctl.scala 449:26]
     node _T_11167 = bits(bht_wr_en0, 0, 0) @[el2_ifu_bp_ctl.scala 455:41]
     node _T_11168 = bits(mp_hashed, 3, 0) @[el2_ifu_bp_ctl.scala 455:60]
@@ -62506,7 +62506,7 @@ circuit el2_swerv_wrapper :
   module el2_ifu_aln_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}
+    output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}
     
     io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19]
     io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18]
@@ -63615,62 +63615,62 @@ circuit el2_swerv_wrapper :
     node _T_726 = and(_T_724, _T_725) @[el2_ifu_aln_ctl.scala 378:100]
     node _T_727 = or(_T_722, _T_726) @[el2_ifu_aln_ctl.scala 378:75]
     io.i0_brp.valid <= _T_727 @[el2_ifu_aln_ctl.scala 378:19]
-    node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:39]
-    node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:29]
-    node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:65]
-    node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:55]
-    node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:44]
-    io.i0_brp.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:17]
+    node _T_728 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 380:44]
+    node _T_729 = and(first2B, _T_728) @[el2_ifu_aln_ctl.scala 380:34]
+    node _T_730 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 380:70]
+    node _T_731 = and(first4B, _T_730) @[el2_ifu_aln_ctl.scala 380:60]
+    node _T_732 = or(_T_729, _T_731) @[el2_ifu_aln_ctl.scala 380:49]
+    io.i0_brp.bits.ret <= _T_732 @[el2_ifu_aln_ctl.scala 380:22]
     node _T_733 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 382:39]
     node _T_734 = and(first2B, _T_733) @[el2_ifu_aln_ctl.scala 382:29]
     node _T_735 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 382:65]
     node _T_736 = and(first4B, _T_735) @[el2_ifu_aln_ctl.scala 382:55]
     node i0_brp_pc4 = or(_T_734, _T_736) @[el2_ifu_aln_ctl.scala 382:44]
-    node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:45]
-    node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:33]
-    node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:50]
-    node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:66]
-    node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:80]
-    node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:23]
-    io.i0_brp.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:17]
-    node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:46]
-    node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:34]
-    node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:74]
-    node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:62]
-    node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:51]
+    node _T_737 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:50]
+    node _T_738 = or(first2B, _T_737) @[el2_ifu_aln_ctl.scala 384:38]
+    node _T_739 = bits(_T_738, 0, 0) @[el2_ifu_aln_ctl.scala 384:55]
+    node _T_740 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 384:71]
+    node _T_741 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 384:85]
+    node _T_742 = mux(_T_739, _T_740, _T_741) @[el2_ifu_aln_ctl.scala 384:28]
+    io.i0_brp.bits.way <= _T_742 @[el2_ifu_aln_ctl.scala 384:22]
+    node _T_743 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 386:51]
+    node _T_744 = and(first2B, _T_743) @[el2_ifu_aln_ctl.scala 386:39]
+    node _T_745 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 386:79]
+    node _T_746 = and(first4B, _T_745) @[el2_ifu_aln_ctl.scala 386:67]
+    node _T_747 = or(_T_744, _T_746) @[el2_ifu_aln_ctl.scala 386:56]
     node _T_748 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 387:26]
     node _T_749 = and(first2B, _T_748) @[el2_ifu_aln_ctl.scala 387:14]
     node _T_750 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 387:54]
     node _T_751 = and(first4B, _T_750) @[el2_ifu_aln_ctl.scala 387:42]
     node _T_752 = or(_T_749, _T_751) @[el2_ifu_aln_ctl.scala 387:31]
     node _T_753 = cat(_T_747, _T_752) @[Cat.scala 29:58]
-    io.i0_brp.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:18]
+    io.i0_brp.bits.hist <= _T_753 @[el2_ifu_aln_ctl.scala 386:23]
     node i0_ends_f1 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 389:28]
-    node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:39]
-    node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:27]
-    io.i0_brp.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:21]
-    node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:37]
-    node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:25]
-    io.i0_brp.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:19]
-    node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:51]
-    node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:41]
-    node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:67]
-    node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:55]
-    io.i0_brp.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:29]
-    node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:57]
-    node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:45]
-    node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:62]
-    node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:77]
-    node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:90]
-    node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:35]
-    io.i0_brp.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:29]
-    node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:42]
-    node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:56]
-    node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:89]
-    node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:87]
-    node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:101]
-    node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:68]
-    io.i0_brp.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:22]
+    node _T_754 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 390:44]
+    node _T_755 = mux(_T_754, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 390:32]
+    io.i0_brp.bits.toffset <= _T_755 @[el2_ifu_aln_ctl.scala 390:26]
+    node _T_756 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 392:42]
+    node _T_757 = mux(_T_756, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 392:30]
+    io.i0_brp.bits.prett <= _T_757 @[el2_ifu_aln_ctl.scala 392:24]
+    node _T_758 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 394:56]
+    node _T_759 = and(first4B, _T_758) @[el2_ifu_aln_ctl.scala 394:46]
+    node _T_760 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 394:72]
+    node _T_761 = and(_T_759, _T_760) @[el2_ifu_aln_ctl.scala 394:60]
+    io.i0_brp.bits.br_start_error <= _T_761 @[el2_ifu_aln_ctl.scala 394:34]
+    node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:62]
+    node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:50]
+    node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:67]
+    node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:82]
+    node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:95]
+    node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:40]
+    io.i0_brp.bits.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:34]
+    node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:47]
+    node _T_769 = and(_T_768, first2B) @[el2_ifu_aln_ctl.scala 398:61]
+    node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 398:94]
+    node _T_771 = and(io.i0_brp.valid, _T_770) @[el2_ifu_aln_ctl.scala 398:92]
+    node _T_772 = and(_T_771, first4B) @[el2_ifu_aln_ctl.scala 398:106]
+    node _T_773 = or(_T_769, _T_772) @[el2_ifu_aln_ctl.scala 398:73]
+    io.i0_brp.bits.br_error <= _T_773 @[el2_ifu_aln_ctl.scala 398:27]
     node _T_774 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 400:50]
     node _T_775 = or(first2B, _T_774) @[el2_ifu_aln_ctl.scala 400:38]
     node _T_776 = bits(_T_775, 0, 0) @[el2_ifu_aln_ctl.scala 400:55]
@@ -64009,7 +64009,7 @@ circuit el2_swerv_wrapper :
   module el2_ifu : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {flip free_clk : Clock, flip active_clk : Clock, flip dec_i0_decode_d : UInt<1>, flip exu_flush_final : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_path_final : UInt<31>, flip dec_tlu_mrac_ff : UInt<32>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, flip ifu_axi_arready : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, flip ifu_axi_rvalid : UInt<1>, ifu_axi_rready : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip dma_iccm_stall_any : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ifu_pmu_instr_aligned : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifu_ic_error_start : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_valid : UInt<1>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, iccm_dma_sb_error : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_miss_state_idle : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, flip exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, ifu_i0_cinst : UInt<16>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>}
     
     inst mem_ctl_ch of el2_ifu_mem_ctl @[el2_ifu.scala 146:26]
     mem_ctl_ch.clock <= clock
@@ -64064,11 +64064,11 @@ circuit el2_swerv_wrapper :
     bp_ctl_ch.io.ic_hit_f <= mem_ctl_ch.io.ic_hit_f @[el2_ifu.scala 195:25]
     bp_ctl_ch.io.ifc_fetch_addr_f <= ifc_ctl_ch.io.ifc_fetch_addr_f @[el2_ifu.scala 196:33]
     bp_ctl_ch.io.ifc_fetch_req_f <= ifc_ctl_ch.io.ifc_fetch_req_f @[el2_ifu.scala 197:32]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.middle <= io.dec_tlu_br0_r_pkt.middle @[el2_ifu.scala 198:34]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.way <= io.dec_tlu_br0_r_pkt.way @[el2_ifu.scala 198:34]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_start_error <= io.dec_tlu_br0_r_pkt.br_start_error @[el2_ifu.scala 198:34]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.br_error <= io.dec_tlu_br0_r_pkt.br_error @[el2_ifu.scala 198:34]
-    bp_ctl_ch.io.dec_tlu_br0_r_pkt.hist <= io.dec_tlu_br0_r_pkt.hist @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.middle <= io.dec_tlu_br0_r_pkt.bits.middle @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.way <= io.dec_tlu_br0_r_pkt.bits.way @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_start_error <= io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.br_error <= io.dec_tlu_br0_r_pkt.bits.br_error @[el2_ifu.scala 198:34]
+    bp_ctl_ch.io.dec_tlu_br0_r_pkt.bits.hist <= io.dec_tlu_br0_r_pkt.bits.hist @[el2_ifu.scala 198:34]
     bp_ctl_ch.io.dec_tlu_br0_r_pkt.valid <= io.dec_tlu_br0_r_pkt.valid @[el2_ifu.scala 198:34]
     bp_ctl_ch.io.exu_i0_br_fghr_r <= io.exu_i0_br_fghr_r @[el2_ifu.scala 199:33]
     bp_ctl_ch.io.exu_i0_br_index_r <= io.exu_i0_br_index_r @[el2_ifu.scala 200:34]
@@ -64210,14 +64210,14 @@ circuit el2_swerv_wrapper :
     io.ifu_i0_pc <= aln_ctl_ch.io.ifu_i0_pc @[el2_ifu.scala 327:16]
     io.ifu_i0_pc4 <= aln_ctl_ch.io.ifu_i0_pc4 @[el2_ifu.scala 328:17]
     io.ifu_miss_state_idle <= mem_ctl_ch.io.ifu_miss_state_idle @[el2_ifu.scala 329:26]
-    io.i0_brp.ret <= aln_ctl_ch.io.i0_brp.ret @[el2_ifu.scala 331:13]
-    io.i0_brp.way <= aln_ctl_ch.io.i0_brp.way @[el2_ifu.scala 331:13]
-    io.i0_brp.prett <= aln_ctl_ch.io.i0_brp.prett @[el2_ifu.scala 331:13]
-    io.i0_brp.bank <= aln_ctl_ch.io.i0_brp.bank @[el2_ifu.scala 331:13]
-    io.i0_brp.br_start_error <= aln_ctl_ch.io.i0_brp.br_start_error @[el2_ifu.scala 331:13]
-    io.i0_brp.br_error <= aln_ctl_ch.io.i0_brp.br_error @[el2_ifu.scala 331:13]
-    io.i0_brp.hist <= aln_ctl_ch.io.i0_brp.hist @[el2_ifu.scala 331:13]
-    io.i0_brp.toffset <= aln_ctl_ch.io.i0_brp.toffset @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.ret <= aln_ctl_ch.io.i0_brp.bits.ret @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.way <= aln_ctl_ch.io.i0_brp.bits.way @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.prett <= aln_ctl_ch.io.i0_brp.bits.prett @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.bank <= aln_ctl_ch.io.i0_brp.bits.bank @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.br_start_error <= aln_ctl_ch.io.i0_brp.bits.br_start_error @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.br_error <= aln_ctl_ch.io.i0_brp.bits.br_error @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.hist <= aln_ctl_ch.io.i0_brp.bits.hist @[el2_ifu.scala 331:13]
+    io.i0_brp.bits.toffset <= aln_ctl_ch.io.i0_brp.bits.toffset @[el2_ifu.scala 331:13]
     io.i0_brp.valid <= aln_ctl_ch.io.i0_brp.valid @[el2_ifu.scala 331:13]
     io.ifu_i0_bp_index <= aln_ctl_ch.io.ifu_i0_bp_index @[el2_ifu.scala 332:22]
     io.ifu_i0_bp_fghr <= aln_ctl_ch.io.ifu_i0_bp_fghr @[el2_ifu.scala 333:21]
@@ -64231,7 +64231,7 @@ circuit el2_swerv_wrapper :
   module el2_dec_ib_ctl : 
     input clock : Clock
     input reset : Reset
-    output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>}
+    output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>}
     
     io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 8:31]
     io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 9:31]
@@ -64239,14 +64239,14 @@ circuit el2_swerv_wrapper :
     io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 11:31]
     io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 12:31]
     io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 13:31]
-    io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 14:31]
-    io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec_ib_ctl.scala 14:31]
+    io.dec_i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec_ib_ctl.scala 14:31]
     io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 14:31]
     io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 15:31]
     io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 16:31]
@@ -66804,7 +66804,7 @@ circuit el2_swerv_wrapper :
   module el2_dec_decode_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>}
     
     wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[el2_dec_decode_ctl.scala 126:27]
     _T.bits.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27]
@@ -67013,9 +67013,9 @@ circuit el2_swerv_wrapper :
     io.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 230:43]
     io.dec_i0_predict_p_d.bits.pja <= i0_pja @[el2_dec_decode_ctl.scala 231:43]
     io.dec_i0_predict_p_d.bits.pret <= i0_pret @[el2_dec_decode_ctl.scala 232:43]
-    io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.prett @[el2_dec_decode_ctl.scala 233:43]
+    io.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[el2_dec_decode_ctl.scala 233:43]
     io.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 234:43]
-    io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.hist @[el2_dec_decode_ctl.scala 235:43]
+    io.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[el2_dec_decode_ctl.scala 235:43]
     node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 236:55]
     io.dec_i0_predict_p_d.valid <= _T_19 @[el2_dec_decode_ctl.scala 236:38]
     node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 237:75]
@@ -67023,34 +67023,34 @@ circuit el2_swerv_wrapper :
     node _T_22 = or(_T_21, i0_pret_raw) @[el2_dec_decode_ctl.scala 237:103]
     node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 237:56]
     node i0_notbr_error = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 237:54]
-    node _T_24 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:67]
+    node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 240:72]
     node _T_25 = and(i0_brp_valid, _T_24) @[el2_dec_decode_ctl.scala 240:47]
-    node _T_26 = neq(io.dec_i0_brp.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:96]
-    node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:71]
-    node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:116]
-    node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:114]
-    node _T_29 = and(i0_brp_valid, io.dec_i0_brp.ret) @[el2_dec_decode_ctl.scala 241:47]
-    node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:69]
-    node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:67]
-    node _T_31 = or(io.dec_i0_brp.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:57]
-    node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:74]
-    node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:96]
+    node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 240:106]
+    node _T_27 = and(_T_25, _T_26) @[el2_dec_decode_ctl.scala 240:76]
+    node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 240:126]
+    node i0_br_toffset_error = and(_T_27, _T_28) @[el2_dec_decode_ctl.scala 240:124]
+    node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[el2_dec_decode_ctl.scala 241:47]
+    node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:74]
+    node i0_ret_error = and(_T_29, _T_30) @[el2_dec_decode_ctl.scala 241:72]
+    node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 242:62]
+    node _T_32 = or(_T_31, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 242:79]
+    node i0_br_error = or(_T_32, i0_ret_error) @[el2_dec_decode_ctl.scala 242:101]
     node _T_33 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 243:72]
     node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 243:94]
     node _T_35 = and(_T_33, _T_34) @[el2_dec_decode_ctl.scala 243:92]
     io.dec_i0_predict_p_d.bits.br_error <= _T_35 @[el2_dec_decode_ctl.scala 243:56]
-    node _T_36 = and(io.dec_i0_brp.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:89]
-    node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:111]
-    node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:109]
+    node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 244:94]
+    node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:116]
+    node _T_38 = and(_T_36, _T_37) @[el2_dec_decode_ctl.scala 244:114]
     io.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[el2_dec_decode_ctl.scala 244:56]
     io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 245:32]
     io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 246:32]
-    node _T_39 = or(i0_br_error, io.dec_i0_brp.br_start_error) @[el2_dec_decode_ctl.scala 247:47]
-    node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:81]
-    node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:79]
+    node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[el2_dec_decode_ctl.scala 247:47]
+    node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:86]
+    node i0_br_error_all = and(_T_39, _T_40) @[el2_dec_decode_ctl.scala 247:84]
     io.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 248:49]
     io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 249:32]
-    io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.way @[el2_dec_decode_ctl.scala 250:56]
+    io.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[el2_dec_decode_ctl.scala 250:56]
     node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 256:36]
     i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 259:9]
     i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 259:9]
@@ -67217,13 +67217,13 @@ circuit el2_swerv_wrapper :
     node _T_44 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 274:38]
     node _T_45 = or(_T_44, i0_pja) @[el2_dec_decode_ctl.scala 274:49]
     node i0_predict_br = or(_T_45, i0_pret) @[el2_dec_decode_ctl.scala 274:58]
-    node _T_46 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:46]
-    node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:50]
+    node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 276:51]
+    node _T_47 = and(_T_46, i0_brp_valid) @[el2_dec_decode_ctl.scala 276:55]
     node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 276:26]
-    node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:66]
-    node _T_49 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:46]
-    node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:50]
-    node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:66]
+    node i0_predict_nt = and(_T_48, i0_predict_br) @[el2_dec_decode_ctl.scala 276:71]
+    node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[el2_dec_decode_ctl.scala 277:51]
+    node _T_50 = and(_T_49, i0_brp_valid) @[el2_dec_decode_ctl.scala 277:55]
+    node i0_predict_t = and(_T_50, i0_predict_br) @[el2_dec_decode_ctl.scala 277:71]
     node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 278:20]
     io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 280:26]
     io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 281:26]
@@ -77826,7 +77826,7 @@ circuit el2_swerv_wrapper :
   module el2_dec_tlu_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>}
+    output io : {flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip exu_npc_r : UInt<31>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_flush_extint : UInt<1>, dec_tlu_meihap : UInt<30>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_fence_i_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_tlu_force_halt : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>}
     
     wire mtdata1_t : UInt<10>[4] @[el2_dec_tlu_ctl.scala 236:59]
     wire pause_expired_wb : UInt<1>
@@ -78789,12 +78789,12 @@ circuit el2_swerv_wrapper :
     node _T_461 = not(io.exu_pmu_i0_br_ataken) @[el2_dec_tlu_ctl.scala 727:118]
     node _T_462 = or(_T_460, _T_461) @[el2_dec_tlu_ctl.scala 727:116]
     node dec_tlu_br0_v_r = and(_T_459, _T_462) @[el2_dec_tlu_ctl.scala 727:94]
-    io.dec_tlu_br0_r_pkt.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:49]
-    io.dec_tlu_br0_r_pkt.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49]
-    io.dec_tlu_br0_r_pkt.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:41]
+    io.dec_tlu_br0_r_pkt.bits.hist <= io.exu_i0_br_hist_r @[el2_dec_tlu_ctl.scala 730:57]
+    io.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[el2_dec_tlu_ctl.scala 731:49]
+    io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[el2_dec_tlu_ctl.scala 732:49]
     io.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[el2_dec_tlu_ctl.scala 733:49]
-    io.dec_tlu_br0_r_pkt.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:49]
-    io.dec_tlu_br0_r_pkt.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:49]
+    io.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[el2_dec_tlu_ctl.scala 734:57]
+    io.dec_tlu_br0_r_pkt.bits.middle <= io.exu_i0_br_middle_r @[el2_dec_tlu_ctl.scala 735:57]
     node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[el2_dec_tlu_ctl.scala 738:51]
     node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[el2_dec_tlu_ctl.scala 738:64]
     node _T_465 = not(i0_trigger_hit_r) @[el2_dec_tlu_ctl.scala 738:90]
@@ -81159,7 +81159,7 @@ circuit el2_swerv_wrapper :
   module el2_dec : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_extint_stall : UInt<1>, dec_i0_decode_d : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip exu_pmu_i0_br_misp : UInt<1>, flip exu_pmu_i0_br_ataken : UInt<1>, flip exu_pmu_i0_pc4 : UInt<1>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip lsu_pmu_bus_trxn : UInt<1>, flip lsu_pmu_bus_misaligned : UInt<1>, flip lsu_pmu_bus_error : UInt<1>, flip lsu_pmu_bus_busy : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_pmu_load_external_m : UInt<1>, flip lsu_pmu_store_external_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip ifu_pmu_instr_aligned : UInt<1>, flip ifu_pmu_fetch_stall : UInt<1>, flip ifu_pmu_ic_miss : UInt<1>, flip ifu_pmu_ic_hit : UInt<1>, flip ifu_pmu_bus_error : UInt<1>, flip ifu_pmu_bus_busy : UInt<1>, flip ifu_pmu_bus_trxn : UInt<1>, flip ifu_ic_error_start : UInt<1>, flip ifu_iccm_rd_ecc_single_err : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<2>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip lsu_idle_any : UInt<1>, flip i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip lsu_imprecise_error_load_any : UInt<1>, flip lsu_imprecise_error_store_any : UInt<1>, flip lsu_imprecise_error_addr_any : UInt<32>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_npc_r : UInt<31>, flip exu_i0_result_x : UInt<32>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, flip ifu_i0_pc4 : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip ifu_ic_debug_rd_data : UInt<71>, flip ifu_ic_debug_rd_data_valid : UInt<1>, dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip ifu_miss_state_idle : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_flush_noredir_r : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_leak_one_r : UInt<1>, dec_tlu_flush_err_r : UInt<1>, dec_tlu_meihap : UInt<30>, dec_debug_wdata_rs1_d : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], dec_tlu_force_halt : UInt<1>, flip exu_i0_br_hist_r : UInt<2>, flip exu_i0_br_error_r : UInt<1>, flip exu_i0_br_start_error_r : UInt<1>, flip exu_i0_br_valid_r : UInt<1>, flip exu_i0_br_mp_r : UInt<1>, flip exu_i0_br_middle_r : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, gpr_i0_rs1_d : UInt<32>, gpr_i0_rs2_d : UInt<32>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_alu_decode_d : UInt<1>, dec_i0_select_pc_d : UInt<1>, dec_i0_pc_d : UInt<31>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, dec_div_cancel : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_tlu_flush_lower_r : UInt<1>, dec_tlu_flush_path_r : UInt<31>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_fence_i_r : UInt<1>, pred_correct_npc_x : UInt<31>, dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_tlu_mrac_ff : UInt<32>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, flip ifu_i0_cinst : UInt<16>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_external_ldfwd_disable : UInt<1>, dec_tlu_sideeffect_posted_disable : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, dec_tlu_bpred_disable : UInt<1>, dec_tlu_wb_coalescing_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_i0_commit_cmt : UInt<1>, flip scan_mode : UInt<1>}
     
     wire dec_i0_inst_wb1 : UInt<32>
     dec_i0_inst_wb1 <= UInt<1>("h00")
@@ -81195,14 +81195,14 @@ circuit el2_swerv_wrapper :
     instbuff.io.dbg_cmd_write <= io.dbg_cmd_write @[el2_dec.scala 298:45]
     instbuff.io.dbg_cmd_type <= io.dbg_cmd_type @[el2_dec.scala 299:45]
     instbuff.io.dbg_cmd_addr <= io.dbg_cmd_addr @[el2_dec.scala 300:45]
-    instbuff.io.i0_brp.ret <= io.i0_brp.ret @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.way <= io.i0_brp.way @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.prett <= io.i0_brp.prett @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.bank <= io.i0_brp.bank @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.br_error <= io.i0_brp.br_error @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.hist <= io.i0_brp.hist @[el2_dec.scala 301:55]
-    instbuff.io.i0_brp.toffset <= io.i0_brp.toffset @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.ret <= io.i0_brp.bits.ret @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.way <= io.i0_brp.bits.way @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.prett <= io.i0_brp.bits.prett @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.bank <= io.i0_brp.bits.bank @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.br_start_error <= io.i0_brp.bits.br_start_error @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.br_error <= io.i0_brp.bits.br_error @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.hist <= io.i0_brp.bits.hist @[el2_dec.scala 301:55]
+    instbuff.io.i0_brp.bits.toffset <= io.i0_brp.bits.toffset @[el2_dec.scala 301:55]
     instbuff.io.i0_brp.valid <= io.i0_brp.valid @[el2_dec.scala 301:55]
     instbuff.io.ifu_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec.scala 302:35]
     instbuff.io.ifu_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec.scala 303:35]
@@ -81269,14 +81269,14 @@ circuit el2_swerv_wrapper :
     decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[el2_dec.scala 351:48]
     decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[el2_dec.scala 352:48]
     decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[el2_dec.scala 353:48]
-    decode.io.dec_i0_brp.ret <= instbuff.io.dec_i0_brp.ret @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.way <= instbuff.io.dec_i0_brp.way @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.prett <= instbuff.io.dec_i0_brp.prett @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.bank <= instbuff.io.dec_i0_brp.bank @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.br_start_error <= instbuff.io.dec_i0_brp.br_start_error @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.br_error <= instbuff.io.dec_i0_brp.br_error @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.hist <= instbuff.io.dec_i0_brp.hist @[el2_dec.scala 354:48]
-    decode.io.dec_i0_brp.toffset <= instbuff.io.dec_i0_brp.toffset @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[el2_dec.scala 354:48]
+    decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[el2_dec.scala 354:48]
     decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[el2_dec.scala 354:48]
     decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[el2_dec.scala 355:48]
     decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[el2_dec.scala 356:48]
@@ -81565,11 +81565,11 @@ circuit el2_swerv_wrapper :
     io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[el2_dec.scala 554:29]
     io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[el2_dec.scala 555:29]
     io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[el2_dec.scala 556:29]
-    io.dec_tlu_br0_r_pkt.middle <= tlu.io.dec_tlu_br0_r_pkt.middle @[el2_dec.scala 557:42]
-    io.dec_tlu_br0_r_pkt.way <= tlu.io.dec_tlu_br0_r_pkt.way @[el2_dec.scala 557:42]
-    io.dec_tlu_br0_r_pkt.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.br_start_error @[el2_dec.scala 557:42]
-    io.dec_tlu_br0_r_pkt.br_error <= tlu.io.dec_tlu_br0_r_pkt.br_error @[el2_dec.scala 557:42]
-    io.dec_tlu_br0_r_pkt.hist <= tlu.io.dec_tlu_br0_r_pkt.hist @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.dec_tlu_br0_r_pkt.bits.middle @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.way <= tlu.io.dec_tlu_br0_r_pkt.bits.way @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_dec.scala 557:42]
+    io.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.dec_tlu_br0_r_pkt.bits.hist @[el2_dec.scala 557:42]
     io.dec_tlu_br0_r_pkt.valid <= tlu.io.dec_tlu_br0_r_pkt.valid @[el2_dec.scala 557:42]
     io.dec_tlu_i0_commit_cmt <= tlu.io.dec_tlu_i0_commit_cmt @[el2_dec.scala 558:34]
     io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[el2_dec.scala 559:34]
@@ -109203,11 +109203,11 @@ circuit el2_swerv_wrapper :
     ifu.io.exu_mp_fghr <= exu.io.exu_mp_fghr @[el2_swerv.scala 384:22]
     ifu.io.exu_mp_index <= exu.io.exu_mp_index @[el2_swerv.scala 385:23]
     ifu.io.exu_mp_btag <= exu.io.exu_mp_btag @[el2_swerv.scala 386:22]
-    ifu.io.dec_tlu_br0_r_pkt.middle <= dec.io.dec_tlu_br0_r_pkt.middle @[el2_swerv.scala 387:28]
-    ifu.io.dec_tlu_br0_r_pkt.way <= dec.io.dec_tlu_br0_r_pkt.way @[el2_swerv.scala 387:28]
-    ifu.io.dec_tlu_br0_r_pkt.br_start_error <= dec.io.dec_tlu_br0_r_pkt.br_start_error @[el2_swerv.scala 387:28]
-    ifu.io.dec_tlu_br0_r_pkt.br_error <= dec.io.dec_tlu_br0_r_pkt.br_error @[el2_swerv.scala 387:28]
-    ifu.io.dec_tlu_br0_r_pkt.hist <= dec.io.dec_tlu_br0_r_pkt.hist @[el2_swerv.scala 387:28]
+    ifu.io.dec_tlu_br0_r_pkt.bits.middle <= dec.io.dec_tlu_br0_r_pkt.bits.middle @[el2_swerv.scala 387:28]
+    ifu.io.dec_tlu_br0_r_pkt.bits.way <= dec.io.dec_tlu_br0_r_pkt.bits.way @[el2_swerv.scala 387:28]
+    ifu.io.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.dec_tlu_br0_r_pkt.bits.br_start_error @[el2_swerv.scala 387:28]
+    ifu.io.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.dec_tlu_br0_r_pkt.bits.br_error @[el2_swerv.scala 387:28]
+    ifu.io.dec_tlu_br0_r_pkt.bits.hist <= dec.io.dec_tlu_br0_r_pkt.bits.hist @[el2_swerv.scala 387:28]
     ifu.io.dec_tlu_br0_r_pkt.valid <= dec.io.dec_tlu_br0_r_pkt.valid @[el2_swerv.scala 387:28]
     ifu.io.exu_i0_br_fghr_r <= exu.io.exu_i0_br_fghr_r @[el2_swerv.scala 388:27]
     ifu.io.exu_i0_br_index_r <= exu.io.exu_i0_br_index_r @[el2_swerv.scala 389:28]
@@ -109273,14 +109273,14 @@ circuit el2_swerv_wrapper :
     dec.io.ifu_i0_icaf_f1 <= ifu.io.ifu_i0_icaf_f1 @[el2_swerv.scala 448:25]
     dec.io.ifu_i0_dbecc <= ifu.io.ifu_i0_dbecc @[el2_swerv.scala 449:23]
     dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[el2_swerv.scala 450:23]
-    dec.io.i0_brp.ret <= ifu.io.i0_brp.ret @[el2_swerv.scala 451:17]
-    dec.io.i0_brp.way <= ifu.io.i0_brp.way @[el2_swerv.scala 451:17]
-    dec.io.i0_brp.prett <= ifu.io.i0_brp.prett @[el2_swerv.scala 451:17]
-    dec.io.i0_brp.bank <= ifu.io.i0_brp.bank @[el2_swerv.scala 451:17]
-    dec.io.i0_brp.br_start_error <= ifu.io.i0_brp.br_start_error @[el2_swerv.scala 451:17]
-    dec.io.i0_brp.br_error <= ifu.io.i0_brp.br_error @[el2_swerv.scala 451:17]
-    dec.io.i0_brp.hist <= ifu.io.i0_brp.hist @[el2_swerv.scala 451:17]
-    dec.io.i0_brp.toffset <= ifu.io.i0_brp.toffset @[el2_swerv.scala 451:17]
+    dec.io.i0_brp.bits.ret <= ifu.io.i0_brp.bits.ret @[el2_swerv.scala 451:17]
+    dec.io.i0_brp.bits.way <= ifu.io.i0_brp.bits.way @[el2_swerv.scala 451:17]
+    dec.io.i0_brp.bits.prett <= ifu.io.i0_brp.bits.prett @[el2_swerv.scala 451:17]
+    dec.io.i0_brp.bits.bank <= ifu.io.i0_brp.bits.bank @[el2_swerv.scala 451:17]
+    dec.io.i0_brp.bits.br_start_error <= ifu.io.i0_brp.bits.br_start_error @[el2_swerv.scala 451:17]
+    dec.io.i0_brp.bits.br_error <= ifu.io.i0_brp.bits.br_error @[el2_swerv.scala 451:17]
+    dec.io.i0_brp.bits.hist <= ifu.io.i0_brp.bits.hist @[el2_swerv.scala 451:17]
+    dec.io.i0_brp.bits.toffset <= ifu.io.i0_brp.bits.toffset @[el2_swerv.scala 451:17]
     dec.io.i0_brp.valid <= ifu.io.i0_brp.valid @[el2_swerv.scala 451:17]
     dec.io.ifu_i0_bp_index <= ifu.io.ifu_i0_bp_index @[el2_swerv.scala 452:26]
     dec.io.ifu_i0_bp_fghr <= ifu.io.ifu_i0_bp_fghr @[el2_swerv.scala 453:25]
diff --git a/el2_swerv_wrapper.v b/el2_swerv_wrapper.v
index 30ea564d..db3c102e 100644
--- a/el2_swerv_wrapper.v
+++ b/el2_swerv_wrapper.v
@@ -11814,11 +11814,11 @@ module el2_ifu_bp_ctl(
   input  [30:0] io_ifc_fetch_addr_f,
   input         io_ifc_fetch_req_f,
   input         io_dec_tlu_br0_r_pkt_valid,
-  input  [1:0]  io_dec_tlu_br0_r_pkt_hist,
-  input         io_dec_tlu_br0_r_pkt_br_error,
-  input         io_dec_tlu_br0_r_pkt_br_start_error,
-  input         io_dec_tlu_br0_r_pkt_way,
-  input         io_dec_tlu_br0_r_pkt_middle,
+  input  [1:0]  io_dec_tlu_br0_r_pkt_bits_hist,
+  input         io_dec_tlu_br0_r_pkt_bits_br_error,
+  input         io_dec_tlu_br0_r_pkt_bits_br_start_error,
+  input         io_dec_tlu_br0_r_pkt_bits_way,
+  input         io_dec_tlu_br0_r_pkt_bits_middle,
   input  [7:0]  io_exu_i0_br_fghr_r,
   input  [7:0]  io_exu_i0_br_index_r,
   input         io_dec_tlu_flush_lower_wb,
@@ -15115,7 +15115,7 @@ module el2_ifu_bp_ctl(
   wire  leak_one_f = _T_40 | _T_41; // @[el2_ifu_bp_ctl.scala 135:76]
   wire  _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 72:51]
   wire  exu_mp_valid = io_exu_mp_pkt_bits_misp & _T; // @[el2_ifu_bp_ctl.scala 72:49]
-  wire  dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_br_start_error | io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu_bp_ctl.scala 94:50]
+  wire  dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_bits_br_start_error | io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu_bp_ctl.scala 94:50]
   wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 191:47]
   wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 191:85]
   wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_bp_ctl.scala 102:51]
@@ -21046,12 +21046,12 @@ module el2_ifu_bp_ctl(
   wire  exu_mp_valid_write = exu_mp_valid & io_exu_mp_pkt_bits_ataken; // @[el2_ifu_bp_ctl.scala 397:41]
   wire  _T_539 = _T_175 & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 400:39]
   wire  _T_541 = _T_539 & _T_530; // @[el2_ifu_bp_ctl.scala 400:60]
-  wire  _T_542 = ~io_dec_tlu_br0_r_pkt_way; // @[el2_ifu_bp_ctl.scala 400:87]
+  wire  _T_542 = ~io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu_bp_ctl.scala 400:87]
   wire  _T_543 = _T_542 & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 400:104]
   wire  btb_wr_en_way0 = _T_541 | _T_543; // @[el2_ifu_bp_ctl.scala 400:83]
   wire  _T_544 = io_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[el2_ifu_bp_ctl.scala 401:36]
   wire  _T_546 = _T_544 & _T_530; // @[el2_ifu_bp_ctl.scala 401:57]
-  wire  _T_547 = io_dec_tlu_br0_r_pkt_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98]
+  wire  _T_547 = io_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 401:98]
   wire  btb_wr_en_way1 = _T_546 | _T_547; // @[el2_ifu_bp_ctl.scala 401:80]
   wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_i0_br_index_r : io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 404:24]
   wire  middle_of_bank = io_exu_mp_pkt_bits_pc4 ^ io_exu_mp_pkt_bits_boffset; // @[el2_ifu_bp_ctl.scala 405:35]
@@ -21066,8 +21066,8 @@ module el2_ifu_bp_ctl(
   wire [1:0] _T_558 = {middle_of_bank,_T_557}; // @[Cat.scala 29:58]
   wire [1:0] bht_wr_en0 = _T_556 & _T_558; // @[el2_ifu_bp_ctl.scala 408:84]
   wire [1:0] _T_560 = io_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire  _T_561 = ~io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu_bp_ctl.scala 409:75]
-  wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_middle,_T_561}; // @[Cat.scala 29:58]
+  wire  _T_561 = ~io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu_bp_ctl.scala 409:75]
+  wire [1:0] _T_562 = {io_dec_tlu_br0_r_pkt_bits_middle,_T_561}; // @[Cat.scala 29:58]
   wire [1:0] bht_wr_en2 = _T_560 & _T_562; // @[el2_ifu_bp_ctl.scala 409:46]
   wire [9:0] _T_563 = {io_exu_mp_index,2'h0}; // @[Cat.scala 29:58]
   wire [7:0] mp_hashed = _T_563[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 196:35]
@@ -35094,7 +35094,7 @@ end // initial
     if (reset) begin
       dec_tlu_way_wb_f <= 1'h0;
     end else begin
-      dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_way;
+      dec_tlu_way_wb_f <= io_dec_tlu_br0_r_pkt_bits_way;
     end
   end
   always @(posedge rvclkhdr_266_io_l1clk or posedge reset) begin
@@ -36901,7 +36901,7 @@ end // initial
       bht_bank_rd_data_out_1_0 <= 2'h0;
     end else if (bht_bank_sel_1_0_0) begin
       if (_T_8869) begin
-        bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_0 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_0 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36912,7 +36912,7 @@ end // initial
       bht_bank_rd_data_out_1_1 <= 2'h0;
     end else if (bht_bank_sel_1_0_1) begin
       if (_T_8878) begin
-        bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_1 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_1 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36923,7 +36923,7 @@ end // initial
       bht_bank_rd_data_out_1_2 <= 2'h0;
     end else if (bht_bank_sel_1_0_2) begin
       if (_T_8887) begin
-        bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_2 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_2 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36934,7 +36934,7 @@ end // initial
       bht_bank_rd_data_out_1_3 <= 2'h0;
     end else if (bht_bank_sel_1_0_3) begin
       if (_T_8896) begin
-        bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_3 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_3 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36945,7 +36945,7 @@ end // initial
       bht_bank_rd_data_out_1_4 <= 2'h0;
     end else if (bht_bank_sel_1_0_4) begin
       if (_T_8905) begin
-        bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_4 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_4 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36956,7 +36956,7 @@ end // initial
       bht_bank_rd_data_out_1_5 <= 2'h0;
     end else if (bht_bank_sel_1_0_5) begin
       if (_T_8914) begin
-        bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_5 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_5 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36967,7 +36967,7 @@ end // initial
       bht_bank_rd_data_out_1_6 <= 2'h0;
     end else if (bht_bank_sel_1_0_6) begin
       if (_T_8923) begin
-        bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_6 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_6 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36978,7 +36978,7 @@ end // initial
       bht_bank_rd_data_out_1_7 <= 2'h0;
     end else if (bht_bank_sel_1_0_7) begin
       if (_T_8932) begin
-        bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_7 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_7 <= io_exu_mp_pkt_bits_hist;
       end
@@ -36989,7 +36989,7 @@ end // initial
       bht_bank_rd_data_out_1_8 <= 2'h0;
     end else if (bht_bank_sel_1_0_8) begin
       if (_T_8941) begin
-        bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_8 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_8 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37000,7 +37000,7 @@ end // initial
       bht_bank_rd_data_out_1_9 <= 2'h0;
     end else if (bht_bank_sel_1_0_9) begin
       if (_T_8950) begin
-        bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_9 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_9 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37011,7 +37011,7 @@ end // initial
       bht_bank_rd_data_out_1_10 <= 2'h0;
     end else if (bht_bank_sel_1_0_10) begin
       if (_T_8959) begin
-        bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_10 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_10 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37022,7 +37022,7 @@ end // initial
       bht_bank_rd_data_out_1_11 <= 2'h0;
     end else if (bht_bank_sel_1_0_11) begin
       if (_T_8968) begin
-        bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_11 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_11 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37033,7 +37033,7 @@ end // initial
       bht_bank_rd_data_out_1_12 <= 2'h0;
     end else if (bht_bank_sel_1_0_12) begin
       if (_T_8977) begin
-        bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_12 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_12 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37044,7 +37044,7 @@ end // initial
       bht_bank_rd_data_out_1_13 <= 2'h0;
     end else if (bht_bank_sel_1_0_13) begin
       if (_T_8986) begin
-        bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_13 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_13 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37055,7 +37055,7 @@ end // initial
       bht_bank_rd_data_out_1_14 <= 2'h0;
     end else if (bht_bank_sel_1_0_14) begin
       if (_T_8995) begin
-        bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_14 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_14 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37066,7 +37066,7 @@ end // initial
       bht_bank_rd_data_out_1_15 <= 2'h0;
     end else if (bht_bank_sel_1_0_15) begin
       if (_T_9004) begin
-        bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_15 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_15 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37077,7 +37077,7 @@ end // initial
       bht_bank_rd_data_out_1_16 <= 2'h0;
     end else if (bht_bank_sel_1_1_0) begin
       if (_T_9013) begin
-        bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_16 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_16 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37088,7 +37088,7 @@ end // initial
       bht_bank_rd_data_out_1_17 <= 2'h0;
     end else if (bht_bank_sel_1_1_1) begin
       if (_T_9022) begin
-        bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_17 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_17 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37099,7 +37099,7 @@ end // initial
       bht_bank_rd_data_out_1_18 <= 2'h0;
     end else if (bht_bank_sel_1_1_2) begin
       if (_T_9031) begin
-        bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_18 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_18 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37110,7 +37110,7 @@ end // initial
       bht_bank_rd_data_out_1_19 <= 2'h0;
     end else if (bht_bank_sel_1_1_3) begin
       if (_T_9040) begin
-        bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_19 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_19 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37121,7 +37121,7 @@ end // initial
       bht_bank_rd_data_out_1_20 <= 2'h0;
     end else if (bht_bank_sel_1_1_4) begin
       if (_T_9049) begin
-        bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_20 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_20 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37132,7 +37132,7 @@ end // initial
       bht_bank_rd_data_out_1_21 <= 2'h0;
     end else if (bht_bank_sel_1_1_5) begin
       if (_T_9058) begin
-        bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_21 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_21 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37143,7 +37143,7 @@ end // initial
       bht_bank_rd_data_out_1_22 <= 2'h0;
     end else if (bht_bank_sel_1_1_6) begin
       if (_T_9067) begin
-        bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_22 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_22 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37154,7 +37154,7 @@ end // initial
       bht_bank_rd_data_out_1_23 <= 2'h0;
     end else if (bht_bank_sel_1_1_7) begin
       if (_T_9076) begin
-        bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_23 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_23 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37165,7 +37165,7 @@ end // initial
       bht_bank_rd_data_out_1_24 <= 2'h0;
     end else if (bht_bank_sel_1_1_8) begin
       if (_T_9085) begin
-        bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_24 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_24 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37176,7 +37176,7 @@ end // initial
       bht_bank_rd_data_out_1_25 <= 2'h0;
     end else if (bht_bank_sel_1_1_9) begin
       if (_T_9094) begin
-        bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_25 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_25 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37187,7 +37187,7 @@ end // initial
       bht_bank_rd_data_out_1_26 <= 2'h0;
     end else if (bht_bank_sel_1_1_10) begin
       if (_T_9103) begin
-        bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_26 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_26 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37198,7 +37198,7 @@ end // initial
       bht_bank_rd_data_out_1_27 <= 2'h0;
     end else if (bht_bank_sel_1_1_11) begin
       if (_T_9112) begin
-        bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_27 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_27 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37209,7 +37209,7 @@ end // initial
       bht_bank_rd_data_out_1_28 <= 2'h0;
     end else if (bht_bank_sel_1_1_12) begin
       if (_T_9121) begin
-        bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_28 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_28 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37220,7 +37220,7 @@ end // initial
       bht_bank_rd_data_out_1_29 <= 2'h0;
     end else if (bht_bank_sel_1_1_13) begin
       if (_T_9130) begin
-        bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_29 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_29 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37231,7 +37231,7 @@ end // initial
       bht_bank_rd_data_out_1_30 <= 2'h0;
     end else if (bht_bank_sel_1_1_14) begin
       if (_T_9139) begin
-        bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_30 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_30 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37242,7 +37242,7 @@ end // initial
       bht_bank_rd_data_out_1_31 <= 2'h0;
     end else if (bht_bank_sel_1_1_15) begin
       if (_T_9148) begin
-        bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_31 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_31 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37253,7 +37253,7 @@ end // initial
       bht_bank_rd_data_out_1_32 <= 2'h0;
     end else if (bht_bank_sel_1_2_0) begin
       if (_T_9157) begin
-        bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_32 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_32 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37264,7 +37264,7 @@ end // initial
       bht_bank_rd_data_out_1_33 <= 2'h0;
     end else if (bht_bank_sel_1_2_1) begin
       if (_T_9166) begin
-        bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_33 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_33 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37275,7 +37275,7 @@ end // initial
       bht_bank_rd_data_out_1_34 <= 2'h0;
     end else if (bht_bank_sel_1_2_2) begin
       if (_T_9175) begin
-        bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_34 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_34 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37286,7 +37286,7 @@ end // initial
       bht_bank_rd_data_out_1_35 <= 2'h0;
     end else if (bht_bank_sel_1_2_3) begin
       if (_T_9184) begin
-        bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_35 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_35 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37297,7 +37297,7 @@ end // initial
       bht_bank_rd_data_out_1_36 <= 2'h0;
     end else if (bht_bank_sel_1_2_4) begin
       if (_T_9193) begin
-        bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_36 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_36 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37308,7 +37308,7 @@ end // initial
       bht_bank_rd_data_out_1_37 <= 2'h0;
     end else if (bht_bank_sel_1_2_5) begin
       if (_T_9202) begin
-        bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_37 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_37 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37319,7 +37319,7 @@ end // initial
       bht_bank_rd_data_out_1_38 <= 2'h0;
     end else if (bht_bank_sel_1_2_6) begin
       if (_T_9211) begin
-        bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_38 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_38 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37330,7 +37330,7 @@ end // initial
       bht_bank_rd_data_out_1_39 <= 2'h0;
     end else if (bht_bank_sel_1_2_7) begin
       if (_T_9220) begin
-        bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_39 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_39 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37341,7 +37341,7 @@ end // initial
       bht_bank_rd_data_out_1_40 <= 2'h0;
     end else if (bht_bank_sel_1_2_8) begin
       if (_T_9229) begin
-        bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_40 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_40 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37352,7 +37352,7 @@ end // initial
       bht_bank_rd_data_out_1_41 <= 2'h0;
     end else if (bht_bank_sel_1_2_9) begin
       if (_T_9238) begin
-        bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_41 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_41 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37363,7 +37363,7 @@ end // initial
       bht_bank_rd_data_out_1_42 <= 2'h0;
     end else if (bht_bank_sel_1_2_10) begin
       if (_T_9247) begin
-        bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_42 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_42 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37374,7 +37374,7 @@ end // initial
       bht_bank_rd_data_out_1_43 <= 2'h0;
     end else if (bht_bank_sel_1_2_11) begin
       if (_T_9256) begin
-        bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_43 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_43 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37385,7 +37385,7 @@ end // initial
       bht_bank_rd_data_out_1_44 <= 2'h0;
     end else if (bht_bank_sel_1_2_12) begin
       if (_T_9265) begin
-        bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_44 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_44 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37396,7 +37396,7 @@ end // initial
       bht_bank_rd_data_out_1_45 <= 2'h0;
     end else if (bht_bank_sel_1_2_13) begin
       if (_T_9274) begin
-        bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_45 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_45 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37407,7 +37407,7 @@ end // initial
       bht_bank_rd_data_out_1_46 <= 2'h0;
     end else if (bht_bank_sel_1_2_14) begin
       if (_T_9283) begin
-        bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_46 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_46 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37418,7 +37418,7 @@ end // initial
       bht_bank_rd_data_out_1_47 <= 2'h0;
     end else if (bht_bank_sel_1_2_15) begin
       if (_T_9292) begin
-        bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_47 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_47 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37429,7 +37429,7 @@ end // initial
       bht_bank_rd_data_out_1_48 <= 2'h0;
     end else if (bht_bank_sel_1_3_0) begin
       if (_T_9301) begin
-        bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_48 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_48 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37440,7 +37440,7 @@ end // initial
       bht_bank_rd_data_out_1_49 <= 2'h0;
     end else if (bht_bank_sel_1_3_1) begin
       if (_T_9310) begin
-        bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_49 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_49 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37451,7 +37451,7 @@ end // initial
       bht_bank_rd_data_out_1_50 <= 2'h0;
     end else if (bht_bank_sel_1_3_2) begin
       if (_T_9319) begin
-        bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_50 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_50 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37462,7 +37462,7 @@ end // initial
       bht_bank_rd_data_out_1_51 <= 2'h0;
     end else if (bht_bank_sel_1_3_3) begin
       if (_T_9328) begin
-        bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_51 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_51 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37473,7 +37473,7 @@ end // initial
       bht_bank_rd_data_out_1_52 <= 2'h0;
     end else if (bht_bank_sel_1_3_4) begin
       if (_T_9337) begin
-        bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_52 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_52 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37484,7 +37484,7 @@ end // initial
       bht_bank_rd_data_out_1_53 <= 2'h0;
     end else if (bht_bank_sel_1_3_5) begin
       if (_T_9346) begin
-        bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_53 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_53 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37495,7 +37495,7 @@ end // initial
       bht_bank_rd_data_out_1_54 <= 2'h0;
     end else if (bht_bank_sel_1_3_6) begin
       if (_T_9355) begin
-        bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_54 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_54 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37506,7 +37506,7 @@ end // initial
       bht_bank_rd_data_out_1_55 <= 2'h0;
     end else if (bht_bank_sel_1_3_7) begin
       if (_T_9364) begin
-        bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_55 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_55 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37517,7 +37517,7 @@ end // initial
       bht_bank_rd_data_out_1_56 <= 2'h0;
     end else if (bht_bank_sel_1_3_8) begin
       if (_T_9373) begin
-        bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_56 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_56 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37528,7 +37528,7 @@ end // initial
       bht_bank_rd_data_out_1_57 <= 2'h0;
     end else if (bht_bank_sel_1_3_9) begin
       if (_T_9382) begin
-        bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_57 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_57 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37539,7 +37539,7 @@ end // initial
       bht_bank_rd_data_out_1_58 <= 2'h0;
     end else if (bht_bank_sel_1_3_10) begin
       if (_T_9391) begin
-        bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_58 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_58 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37550,7 +37550,7 @@ end // initial
       bht_bank_rd_data_out_1_59 <= 2'h0;
     end else if (bht_bank_sel_1_3_11) begin
       if (_T_9400) begin
-        bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_59 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_59 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37561,7 +37561,7 @@ end // initial
       bht_bank_rd_data_out_1_60 <= 2'h0;
     end else if (bht_bank_sel_1_3_12) begin
       if (_T_9409) begin
-        bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_60 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_60 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37572,7 +37572,7 @@ end // initial
       bht_bank_rd_data_out_1_61 <= 2'h0;
     end else if (bht_bank_sel_1_3_13) begin
       if (_T_9418) begin
-        bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_61 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_61 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37583,7 +37583,7 @@ end // initial
       bht_bank_rd_data_out_1_62 <= 2'h0;
     end else if (bht_bank_sel_1_3_14) begin
       if (_T_9427) begin
-        bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_62 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_62 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37594,7 +37594,7 @@ end // initial
       bht_bank_rd_data_out_1_63 <= 2'h0;
     end else if (bht_bank_sel_1_3_15) begin
       if (_T_9436) begin
-        bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_63 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_63 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37605,7 +37605,7 @@ end // initial
       bht_bank_rd_data_out_1_64 <= 2'h0;
     end else if (bht_bank_sel_1_4_0) begin
       if (_T_9445) begin
-        bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_64 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_64 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37616,7 +37616,7 @@ end // initial
       bht_bank_rd_data_out_1_65 <= 2'h0;
     end else if (bht_bank_sel_1_4_1) begin
       if (_T_9454) begin
-        bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_65 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_65 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37627,7 +37627,7 @@ end // initial
       bht_bank_rd_data_out_1_66 <= 2'h0;
     end else if (bht_bank_sel_1_4_2) begin
       if (_T_9463) begin
-        bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_66 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_66 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37638,7 +37638,7 @@ end // initial
       bht_bank_rd_data_out_1_67 <= 2'h0;
     end else if (bht_bank_sel_1_4_3) begin
       if (_T_9472) begin
-        bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_67 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_67 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37649,7 +37649,7 @@ end // initial
       bht_bank_rd_data_out_1_68 <= 2'h0;
     end else if (bht_bank_sel_1_4_4) begin
       if (_T_9481) begin
-        bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_68 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_68 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37660,7 +37660,7 @@ end // initial
       bht_bank_rd_data_out_1_69 <= 2'h0;
     end else if (bht_bank_sel_1_4_5) begin
       if (_T_9490) begin
-        bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_69 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_69 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37671,7 +37671,7 @@ end // initial
       bht_bank_rd_data_out_1_70 <= 2'h0;
     end else if (bht_bank_sel_1_4_6) begin
       if (_T_9499) begin
-        bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_70 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_70 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37682,7 +37682,7 @@ end // initial
       bht_bank_rd_data_out_1_71 <= 2'h0;
     end else if (bht_bank_sel_1_4_7) begin
       if (_T_9508) begin
-        bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_71 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_71 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37693,7 +37693,7 @@ end // initial
       bht_bank_rd_data_out_1_72 <= 2'h0;
     end else if (bht_bank_sel_1_4_8) begin
       if (_T_9517) begin
-        bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_72 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_72 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37704,7 +37704,7 @@ end // initial
       bht_bank_rd_data_out_1_73 <= 2'h0;
     end else if (bht_bank_sel_1_4_9) begin
       if (_T_9526) begin
-        bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_73 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_73 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37715,7 +37715,7 @@ end // initial
       bht_bank_rd_data_out_1_74 <= 2'h0;
     end else if (bht_bank_sel_1_4_10) begin
       if (_T_9535) begin
-        bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_74 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_74 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37726,7 +37726,7 @@ end // initial
       bht_bank_rd_data_out_1_75 <= 2'h0;
     end else if (bht_bank_sel_1_4_11) begin
       if (_T_9544) begin
-        bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_75 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_75 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37737,7 +37737,7 @@ end // initial
       bht_bank_rd_data_out_1_76 <= 2'h0;
     end else if (bht_bank_sel_1_4_12) begin
       if (_T_9553) begin
-        bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_76 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_76 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37748,7 +37748,7 @@ end // initial
       bht_bank_rd_data_out_1_77 <= 2'h0;
     end else if (bht_bank_sel_1_4_13) begin
       if (_T_9562) begin
-        bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_77 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_77 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37759,7 +37759,7 @@ end // initial
       bht_bank_rd_data_out_1_78 <= 2'h0;
     end else if (bht_bank_sel_1_4_14) begin
       if (_T_9571) begin
-        bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_78 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_78 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37770,7 +37770,7 @@ end // initial
       bht_bank_rd_data_out_1_79 <= 2'h0;
     end else if (bht_bank_sel_1_4_15) begin
       if (_T_9580) begin
-        bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_79 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_79 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37781,7 +37781,7 @@ end // initial
       bht_bank_rd_data_out_1_80 <= 2'h0;
     end else if (bht_bank_sel_1_5_0) begin
       if (_T_9589) begin
-        bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_80 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_80 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37792,7 +37792,7 @@ end // initial
       bht_bank_rd_data_out_1_81 <= 2'h0;
     end else if (bht_bank_sel_1_5_1) begin
       if (_T_9598) begin
-        bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_81 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_81 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37803,7 +37803,7 @@ end // initial
       bht_bank_rd_data_out_1_82 <= 2'h0;
     end else if (bht_bank_sel_1_5_2) begin
       if (_T_9607) begin
-        bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_82 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_82 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37814,7 +37814,7 @@ end // initial
       bht_bank_rd_data_out_1_83 <= 2'h0;
     end else if (bht_bank_sel_1_5_3) begin
       if (_T_9616) begin
-        bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_83 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_83 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37825,7 +37825,7 @@ end // initial
       bht_bank_rd_data_out_1_84 <= 2'h0;
     end else if (bht_bank_sel_1_5_4) begin
       if (_T_9625) begin
-        bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_84 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_84 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37836,7 +37836,7 @@ end // initial
       bht_bank_rd_data_out_1_85 <= 2'h0;
     end else if (bht_bank_sel_1_5_5) begin
       if (_T_9634) begin
-        bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_85 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_85 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37847,7 +37847,7 @@ end // initial
       bht_bank_rd_data_out_1_86 <= 2'h0;
     end else if (bht_bank_sel_1_5_6) begin
       if (_T_9643) begin
-        bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_86 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_86 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37858,7 +37858,7 @@ end // initial
       bht_bank_rd_data_out_1_87 <= 2'h0;
     end else if (bht_bank_sel_1_5_7) begin
       if (_T_9652) begin
-        bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_87 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_87 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37869,7 +37869,7 @@ end // initial
       bht_bank_rd_data_out_1_88 <= 2'h0;
     end else if (bht_bank_sel_1_5_8) begin
       if (_T_9661) begin
-        bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_88 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_88 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37880,7 +37880,7 @@ end // initial
       bht_bank_rd_data_out_1_89 <= 2'h0;
     end else if (bht_bank_sel_1_5_9) begin
       if (_T_9670) begin
-        bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_89 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_89 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37891,7 +37891,7 @@ end // initial
       bht_bank_rd_data_out_1_90 <= 2'h0;
     end else if (bht_bank_sel_1_5_10) begin
       if (_T_9679) begin
-        bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_90 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_90 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37902,7 +37902,7 @@ end // initial
       bht_bank_rd_data_out_1_91 <= 2'h0;
     end else if (bht_bank_sel_1_5_11) begin
       if (_T_9688) begin
-        bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_91 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_91 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37913,7 +37913,7 @@ end // initial
       bht_bank_rd_data_out_1_92 <= 2'h0;
     end else if (bht_bank_sel_1_5_12) begin
       if (_T_9697) begin
-        bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_92 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_92 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37924,7 +37924,7 @@ end // initial
       bht_bank_rd_data_out_1_93 <= 2'h0;
     end else if (bht_bank_sel_1_5_13) begin
       if (_T_9706) begin
-        bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_93 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_93 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37935,7 +37935,7 @@ end // initial
       bht_bank_rd_data_out_1_94 <= 2'h0;
     end else if (bht_bank_sel_1_5_14) begin
       if (_T_9715) begin
-        bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_94 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_94 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37946,7 +37946,7 @@ end // initial
       bht_bank_rd_data_out_1_95 <= 2'h0;
     end else if (bht_bank_sel_1_5_15) begin
       if (_T_9724) begin
-        bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_95 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_95 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37957,7 +37957,7 @@ end // initial
       bht_bank_rd_data_out_1_96 <= 2'h0;
     end else if (bht_bank_sel_1_6_0) begin
       if (_T_9733) begin
-        bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_96 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_96 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37968,7 +37968,7 @@ end // initial
       bht_bank_rd_data_out_1_97 <= 2'h0;
     end else if (bht_bank_sel_1_6_1) begin
       if (_T_9742) begin
-        bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_97 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_97 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37979,7 +37979,7 @@ end // initial
       bht_bank_rd_data_out_1_98 <= 2'h0;
     end else if (bht_bank_sel_1_6_2) begin
       if (_T_9751) begin
-        bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_98 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_98 <= io_exu_mp_pkt_bits_hist;
       end
@@ -37990,7 +37990,7 @@ end // initial
       bht_bank_rd_data_out_1_99 <= 2'h0;
     end else if (bht_bank_sel_1_6_3) begin
       if (_T_9760) begin
-        bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_99 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_99 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38001,7 +38001,7 @@ end // initial
       bht_bank_rd_data_out_1_100 <= 2'h0;
     end else if (bht_bank_sel_1_6_4) begin
       if (_T_9769) begin
-        bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_100 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_100 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38012,7 +38012,7 @@ end // initial
       bht_bank_rd_data_out_1_101 <= 2'h0;
     end else if (bht_bank_sel_1_6_5) begin
       if (_T_9778) begin
-        bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_101 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_101 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38023,7 +38023,7 @@ end // initial
       bht_bank_rd_data_out_1_102 <= 2'h0;
     end else if (bht_bank_sel_1_6_6) begin
       if (_T_9787) begin
-        bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_102 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_102 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38034,7 +38034,7 @@ end // initial
       bht_bank_rd_data_out_1_103 <= 2'h0;
     end else if (bht_bank_sel_1_6_7) begin
       if (_T_9796) begin
-        bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_103 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_103 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38045,7 +38045,7 @@ end // initial
       bht_bank_rd_data_out_1_104 <= 2'h0;
     end else if (bht_bank_sel_1_6_8) begin
       if (_T_9805) begin
-        bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_104 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_104 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38056,7 +38056,7 @@ end // initial
       bht_bank_rd_data_out_1_105 <= 2'h0;
     end else if (bht_bank_sel_1_6_9) begin
       if (_T_9814) begin
-        bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_105 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_105 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38067,7 +38067,7 @@ end // initial
       bht_bank_rd_data_out_1_106 <= 2'h0;
     end else if (bht_bank_sel_1_6_10) begin
       if (_T_9823) begin
-        bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_106 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_106 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38078,7 +38078,7 @@ end // initial
       bht_bank_rd_data_out_1_107 <= 2'h0;
     end else if (bht_bank_sel_1_6_11) begin
       if (_T_9832) begin
-        bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_107 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_107 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38089,7 +38089,7 @@ end // initial
       bht_bank_rd_data_out_1_108 <= 2'h0;
     end else if (bht_bank_sel_1_6_12) begin
       if (_T_9841) begin
-        bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_108 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_108 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38100,7 +38100,7 @@ end // initial
       bht_bank_rd_data_out_1_109 <= 2'h0;
     end else if (bht_bank_sel_1_6_13) begin
       if (_T_9850) begin
-        bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_109 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_109 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38111,7 +38111,7 @@ end // initial
       bht_bank_rd_data_out_1_110 <= 2'h0;
     end else if (bht_bank_sel_1_6_14) begin
       if (_T_9859) begin
-        bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_110 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_110 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38122,7 +38122,7 @@ end // initial
       bht_bank_rd_data_out_1_111 <= 2'h0;
     end else if (bht_bank_sel_1_6_15) begin
       if (_T_9868) begin
-        bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_111 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_111 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38133,7 +38133,7 @@ end // initial
       bht_bank_rd_data_out_1_112 <= 2'h0;
     end else if (bht_bank_sel_1_7_0) begin
       if (_T_9877) begin
-        bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_112 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_112 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38144,7 +38144,7 @@ end // initial
       bht_bank_rd_data_out_1_113 <= 2'h0;
     end else if (bht_bank_sel_1_7_1) begin
       if (_T_9886) begin
-        bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_113 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_113 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38155,7 +38155,7 @@ end // initial
       bht_bank_rd_data_out_1_114 <= 2'h0;
     end else if (bht_bank_sel_1_7_2) begin
       if (_T_9895) begin
-        bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_114 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_114 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38166,7 +38166,7 @@ end // initial
       bht_bank_rd_data_out_1_115 <= 2'h0;
     end else if (bht_bank_sel_1_7_3) begin
       if (_T_9904) begin
-        bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_115 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_115 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38177,7 +38177,7 @@ end // initial
       bht_bank_rd_data_out_1_116 <= 2'h0;
     end else if (bht_bank_sel_1_7_4) begin
       if (_T_9913) begin
-        bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_116 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_116 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38188,7 +38188,7 @@ end // initial
       bht_bank_rd_data_out_1_117 <= 2'h0;
     end else if (bht_bank_sel_1_7_5) begin
       if (_T_9922) begin
-        bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_117 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_117 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38199,7 +38199,7 @@ end // initial
       bht_bank_rd_data_out_1_118 <= 2'h0;
     end else if (bht_bank_sel_1_7_6) begin
       if (_T_9931) begin
-        bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_118 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_118 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38210,7 +38210,7 @@ end // initial
       bht_bank_rd_data_out_1_119 <= 2'h0;
     end else if (bht_bank_sel_1_7_7) begin
       if (_T_9940) begin
-        bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_119 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_119 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38221,7 +38221,7 @@ end // initial
       bht_bank_rd_data_out_1_120 <= 2'h0;
     end else if (bht_bank_sel_1_7_8) begin
       if (_T_9949) begin
-        bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_120 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_120 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38232,7 +38232,7 @@ end // initial
       bht_bank_rd_data_out_1_121 <= 2'h0;
     end else if (bht_bank_sel_1_7_9) begin
       if (_T_9958) begin
-        bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_121 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_121 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38243,7 +38243,7 @@ end // initial
       bht_bank_rd_data_out_1_122 <= 2'h0;
     end else if (bht_bank_sel_1_7_10) begin
       if (_T_9967) begin
-        bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_122 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_122 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38254,7 +38254,7 @@ end // initial
       bht_bank_rd_data_out_1_123 <= 2'h0;
     end else if (bht_bank_sel_1_7_11) begin
       if (_T_9976) begin
-        bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_123 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_123 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38265,7 +38265,7 @@ end // initial
       bht_bank_rd_data_out_1_124 <= 2'h0;
     end else if (bht_bank_sel_1_7_12) begin
       if (_T_9985) begin
-        bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_124 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_124 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38276,7 +38276,7 @@ end // initial
       bht_bank_rd_data_out_1_125 <= 2'h0;
     end else if (bht_bank_sel_1_7_13) begin
       if (_T_9994) begin
-        bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_125 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_125 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38287,7 +38287,7 @@ end // initial
       bht_bank_rd_data_out_1_126 <= 2'h0;
     end else if (bht_bank_sel_1_7_14) begin
       if (_T_10003) begin
-        bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_126 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_126 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38298,7 +38298,7 @@ end // initial
       bht_bank_rd_data_out_1_127 <= 2'h0;
     end else if (bht_bank_sel_1_7_15) begin
       if (_T_10012) begin
-        bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_127 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_127 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38309,7 +38309,7 @@ end // initial
       bht_bank_rd_data_out_1_128 <= 2'h0;
     end else if (bht_bank_sel_1_8_0) begin
       if (_T_10021) begin
-        bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_128 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_128 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38320,7 +38320,7 @@ end // initial
       bht_bank_rd_data_out_1_129 <= 2'h0;
     end else if (bht_bank_sel_1_8_1) begin
       if (_T_10030) begin
-        bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_129 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_129 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38331,7 +38331,7 @@ end // initial
       bht_bank_rd_data_out_1_130 <= 2'h0;
     end else if (bht_bank_sel_1_8_2) begin
       if (_T_10039) begin
-        bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_130 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_130 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38342,7 +38342,7 @@ end // initial
       bht_bank_rd_data_out_1_131 <= 2'h0;
     end else if (bht_bank_sel_1_8_3) begin
       if (_T_10048) begin
-        bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_131 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_131 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38353,7 +38353,7 @@ end // initial
       bht_bank_rd_data_out_1_132 <= 2'h0;
     end else if (bht_bank_sel_1_8_4) begin
       if (_T_10057) begin
-        bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_132 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_132 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38364,7 +38364,7 @@ end // initial
       bht_bank_rd_data_out_1_133 <= 2'h0;
     end else if (bht_bank_sel_1_8_5) begin
       if (_T_10066) begin
-        bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_133 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_133 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38375,7 +38375,7 @@ end // initial
       bht_bank_rd_data_out_1_134 <= 2'h0;
     end else if (bht_bank_sel_1_8_6) begin
       if (_T_10075) begin
-        bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_134 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_134 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38386,7 +38386,7 @@ end // initial
       bht_bank_rd_data_out_1_135 <= 2'h0;
     end else if (bht_bank_sel_1_8_7) begin
       if (_T_10084) begin
-        bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_135 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_135 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38397,7 +38397,7 @@ end // initial
       bht_bank_rd_data_out_1_136 <= 2'h0;
     end else if (bht_bank_sel_1_8_8) begin
       if (_T_10093) begin
-        bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_136 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_136 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38408,7 +38408,7 @@ end // initial
       bht_bank_rd_data_out_1_137 <= 2'h0;
     end else if (bht_bank_sel_1_8_9) begin
       if (_T_10102) begin
-        bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_137 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_137 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38419,7 +38419,7 @@ end // initial
       bht_bank_rd_data_out_1_138 <= 2'h0;
     end else if (bht_bank_sel_1_8_10) begin
       if (_T_10111) begin
-        bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_138 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_138 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38430,7 +38430,7 @@ end // initial
       bht_bank_rd_data_out_1_139 <= 2'h0;
     end else if (bht_bank_sel_1_8_11) begin
       if (_T_10120) begin
-        bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_139 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_139 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38441,7 +38441,7 @@ end // initial
       bht_bank_rd_data_out_1_140 <= 2'h0;
     end else if (bht_bank_sel_1_8_12) begin
       if (_T_10129) begin
-        bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_140 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_140 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38452,7 +38452,7 @@ end // initial
       bht_bank_rd_data_out_1_141 <= 2'h0;
     end else if (bht_bank_sel_1_8_13) begin
       if (_T_10138) begin
-        bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_141 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_141 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38463,7 +38463,7 @@ end // initial
       bht_bank_rd_data_out_1_142 <= 2'h0;
     end else if (bht_bank_sel_1_8_14) begin
       if (_T_10147) begin
-        bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_142 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_142 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38474,7 +38474,7 @@ end // initial
       bht_bank_rd_data_out_1_143 <= 2'h0;
     end else if (bht_bank_sel_1_8_15) begin
       if (_T_10156) begin
-        bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_143 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_143 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38485,7 +38485,7 @@ end // initial
       bht_bank_rd_data_out_1_144 <= 2'h0;
     end else if (bht_bank_sel_1_9_0) begin
       if (_T_10165) begin
-        bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_144 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_144 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38496,7 +38496,7 @@ end // initial
       bht_bank_rd_data_out_1_145 <= 2'h0;
     end else if (bht_bank_sel_1_9_1) begin
       if (_T_10174) begin
-        bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_145 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_145 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38507,7 +38507,7 @@ end // initial
       bht_bank_rd_data_out_1_146 <= 2'h0;
     end else if (bht_bank_sel_1_9_2) begin
       if (_T_10183) begin
-        bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_146 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_146 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38518,7 +38518,7 @@ end // initial
       bht_bank_rd_data_out_1_147 <= 2'h0;
     end else if (bht_bank_sel_1_9_3) begin
       if (_T_10192) begin
-        bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_147 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_147 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38529,7 +38529,7 @@ end // initial
       bht_bank_rd_data_out_1_148 <= 2'h0;
     end else if (bht_bank_sel_1_9_4) begin
       if (_T_10201) begin
-        bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_148 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_148 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38540,7 +38540,7 @@ end // initial
       bht_bank_rd_data_out_1_149 <= 2'h0;
     end else if (bht_bank_sel_1_9_5) begin
       if (_T_10210) begin
-        bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_149 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_149 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38551,7 +38551,7 @@ end // initial
       bht_bank_rd_data_out_1_150 <= 2'h0;
     end else if (bht_bank_sel_1_9_6) begin
       if (_T_10219) begin
-        bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_150 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_150 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38562,7 +38562,7 @@ end // initial
       bht_bank_rd_data_out_1_151 <= 2'h0;
     end else if (bht_bank_sel_1_9_7) begin
       if (_T_10228) begin
-        bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_151 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_151 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38573,7 +38573,7 @@ end // initial
       bht_bank_rd_data_out_1_152 <= 2'h0;
     end else if (bht_bank_sel_1_9_8) begin
       if (_T_10237) begin
-        bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_152 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_152 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38584,7 +38584,7 @@ end // initial
       bht_bank_rd_data_out_1_153 <= 2'h0;
     end else if (bht_bank_sel_1_9_9) begin
       if (_T_10246) begin
-        bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_153 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_153 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38595,7 +38595,7 @@ end // initial
       bht_bank_rd_data_out_1_154 <= 2'h0;
     end else if (bht_bank_sel_1_9_10) begin
       if (_T_10255) begin
-        bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_154 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_154 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38606,7 +38606,7 @@ end // initial
       bht_bank_rd_data_out_1_155 <= 2'h0;
     end else if (bht_bank_sel_1_9_11) begin
       if (_T_10264) begin
-        bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_155 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_155 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38617,7 +38617,7 @@ end // initial
       bht_bank_rd_data_out_1_156 <= 2'h0;
     end else if (bht_bank_sel_1_9_12) begin
       if (_T_10273) begin
-        bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_156 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_156 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38628,7 +38628,7 @@ end // initial
       bht_bank_rd_data_out_1_157 <= 2'h0;
     end else if (bht_bank_sel_1_9_13) begin
       if (_T_10282) begin
-        bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_157 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_157 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38639,7 +38639,7 @@ end // initial
       bht_bank_rd_data_out_1_158 <= 2'h0;
     end else if (bht_bank_sel_1_9_14) begin
       if (_T_10291) begin
-        bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_158 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_158 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38650,7 +38650,7 @@ end // initial
       bht_bank_rd_data_out_1_159 <= 2'h0;
     end else if (bht_bank_sel_1_9_15) begin
       if (_T_10300) begin
-        bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_159 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_159 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38661,7 +38661,7 @@ end // initial
       bht_bank_rd_data_out_1_160 <= 2'h0;
     end else if (bht_bank_sel_1_10_0) begin
       if (_T_10309) begin
-        bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_160 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_160 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38672,7 +38672,7 @@ end // initial
       bht_bank_rd_data_out_1_161 <= 2'h0;
     end else if (bht_bank_sel_1_10_1) begin
       if (_T_10318) begin
-        bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_161 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_161 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38683,7 +38683,7 @@ end // initial
       bht_bank_rd_data_out_1_162 <= 2'h0;
     end else if (bht_bank_sel_1_10_2) begin
       if (_T_10327) begin
-        bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_162 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_162 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38694,7 +38694,7 @@ end // initial
       bht_bank_rd_data_out_1_163 <= 2'h0;
     end else if (bht_bank_sel_1_10_3) begin
       if (_T_10336) begin
-        bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_163 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_163 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38705,7 +38705,7 @@ end // initial
       bht_bank_rd_data_out_1_164 <= 2'h0;
     end else if (bht_bank_sel_1_10_4) begin
       if (_T_10345) begin
-        bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_164 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_164 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38716,7 +38716,7 @@ end // initial
       bht_bank_rd_data_out_1_165 <= 2'h0;
     end else if (bht_bank_sel_1_10_5) begin
       if (_T_10354) begin
-        bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_165 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_165 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38727,7 +38727,7 @@ end // initial
       bht_bank_rd_data_out_1_166 <= 2'h0;
     end else if (bht_bank_sel_1_10_6) begin
       if (_T_10363) begin
-        bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_166 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_166 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38738,7 +38738,7 @@ end // initial
       bht_bank_rd_data_out_1_167 <= 2'h0;
     end else if (bht_bank_sel_1_10_7) begin
       if (_T_10372) begin
-        bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_167 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_167 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38749,7 +38749,7 @@ end // initial
       bht_bank_rd_data_out_1_168 <= 2'h0;
     end else if (bht_bank_sel_1_10_8) begin
       if (_T_10381) begin
-        bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_168 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_168 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38760,7 +38760,7 @@ end // initial
       bht_bank_rd_data_out_1_169 <= 2'h0;
     end else if (bht_bank_sel_1_10_9) begin
       if (_T_10390) begin
-        bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_169 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_169 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38771,7 +38771,7 @@ end // initial
       bht_bank_rd_data_out_1_170 <= 2'h0;
     end else if (bht_bank_sel_1_10_10) begin
       if (_T_10399) begin
-        bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_170 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_170 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38782,7 +38782,7 @@ end // initial
       bht_bank_rd_data_out_1_171 <= 2'h0;
     end else if (bht_bank_sel_1_10_11) begin
       if (_T_10408) begin
-        bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_171 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_171 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38793,7 +38793,7 @@ end // initial
       bht_bank_rd_data_out_1_172 <= 2'h0;
     end else if (bht_bank_sel_1_10_12) begin
       if (_T_10417) begin
-        bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_172 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_172 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38804,7 +38804,7 @@ end // initial
       bht_bank_rd_data_out_1_173 <= 2'h0;
     end else if (bht_bank_sel_1_10_13) begin
       if (_T_10426) begin
-        bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_173 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_173 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38815,7 +38815,7 @@ end // initial
       bht_bank_rd_data_out_1_174 <= 2'h0;
     end else if (bht_bank_sel_1_10_14) begin
       if (_T_10435) begin
-        bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_174 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_174 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38826,7 +38826,7 @@ end // initial
       bht_bank_rd_data_out_1_175 <= 2'h0;
     end else if (bht_bank_sel_1_10_15) begin
       if (_T_10444) begin
-        bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_175 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_175 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38837,7 +38837,7 @@ end // initial
       bht_bank_rd_data_out_1_176 <= 2'h0;
     end else if (bht_bank_sel_1_11_0) begin
       if (_T_10453) begin
-        bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_176 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_176 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38848,7 +38848,7 @@ end // initial
       bht_bank_rd_data_out_1_177 <= 2'h0;
     end else if (bht_bank_sel_1_11_1) begin
       if (_T_10462) begin
-        bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_177 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_177 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38859,7 +38859,7 @@ end // initial
       bht_bank_rd_data_out_1_178 <= 2'h0;
     end else if (bht_bank_sel_1_11_2) begin
       if (_T_10471) begin
-        bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_178 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_178 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38870,7 +38870,7 @@ end // initial
       bht_bank_rd_data_out_1_179 <= 2'h0;
     end else if (bht_bank_sel_1_11_3) begin
       if (_T_10480) begin
-        bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_179 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_179 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38881,7 +38881,7 @@ end // initial
       bht_bank_rd_data_out_1_180 <= 2'h0;
     end else if (bht_bank_sel_1_11_4) begin
       if (_T_10489) begin
-        bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_180 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_180 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38892,7 +38892,7 @@ end // initial
       bht_bank_rd_data_out_1_181 <= 2'h0;
     end else if (bht_bank_sel_1_11_5) begin
       if (_T_10498) begin
-        bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_181 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_181 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38903,7 +38903,7 @@ end // initial
       bht_bank_rd_data_out_1_182 <= 2'h0;
     end else if (bht_bank_sel_1_11_6) begin
       if (_T_10507) begin
-        bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_182 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_182 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38914,7 +38914,7 @@ end // initial
       bht_bank_rd_data_out_1_183 <= 2'h0;
     end else if (bht_bank_sel_1_11_7) begin
       if (_T_10516) begin
-        bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_183 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_183 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38925,7 +38925,7 @@ end // initial
       bht_bank_rd_data_out_1_184 <= 2'h0;
     end else if (bht_bank_sel_1_11_8) begin
       if (_T_10525) begin
-        bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_184 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_184 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38936,7 +38936,7 @@ end // initial
       bht_bank_rd_data_out_1_185 <= 2'h0;
     end else if (bht_bank_sel_1_11_9) begin
       if (_T_10534) begin
-        bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_185 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_185 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38947,7 +38947,7 @@ end // initial
       bht_bank_rd_data_out_1_186 <= 2'h0;
     end else if (bht_bank_sel_1_11_10) begin
       if (_T_10543) begin
-        bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_186 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_186 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38958,7 +38958,7 @@ end // initial
       bht_bank_rd_data_out_1_187 <= 2'h0;
     end else if (bht_bank_sel_1_11_11) begin
       if (_T_10552) begin
-        bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_187 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_187 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38969,7 +38969,7 @@ end // initial
       bht_bank_rd_data_out_1_188 <= 2'h0;
     end else if (bht_bank_sel_1_11_12) begin
       if (_T_10561) begin
-        bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_188 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_188 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38980,7 +38980,7 @@ end // initial
       bht_bank_rd_data_out_1_189 <= 2'h0;
     end else if (bht_bank_sel_1_11_13) begin
       if (_T_10570) begin
-        bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_189 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_189 <= io_exu_mp_pkt_bits_hist;
       end
@@ -38991,7 +38991,7 @@ end // initial
       bht_bank_rd_data_out_1_190 <= 2'h0;
     end else if (bht_bank_sel_1_11_14) begin
       if (_T_10579) begin
-        bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_190 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_190 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39002,7 +39002,7 @@ end // initial
       bht_bank_rd_data_out_1_191 <= 2'h0;
     end else if (bht_bank_sel_1_11_15) begin
       if (_T_10588) begin
-        bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_191 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_191 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39013,7 +39013,7 @@ end // initial
       bht_bank_rd_data_out_1_192 <= 2'h0;
     end else if (bht_bank_sel_1_12_0) begin
       if (_T_10597) begin
-        bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_192 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_192 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39024,7 +39024,7 @@ end // initial
       bht_bank_rd_data_out_1_193 <= 2'h0;
     end else if (bht_bank_sel_1_12_1) begin
       if (_T_10606) begin
-        bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_193 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_193 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39035,7 +39035,7 @@ end // initial
       bht_bank_rd_data_out_1_194 <= 2'h0;
     end else if (bht_bank_sel_1_12_2) begin
       if (_T_10615) begin
-        bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_194 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_194 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39046,7 +39046,7 @@ end // initial
       bht_bank_rd_data_out_1_195 <= 2'h0;
     end else if (bht_bank_sel_1_12_3) begin
       if (_T_10624) begin
-        bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_195 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_195 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39057,7 +39057,7 @@ end // initial
       bht_bank_rd_data_out_1_196 <= 2'h0;
     end else if (bht_bank_sel_1_12_4) begin
       if (_T_10633) begin
-        bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_196 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_196 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39068,7 +39068,7 @@ end // initial
       bht_bank_rd_data_out_1_197 <= 2'h0;
     end else if (bht_bank_sel_1_12_5) begin
       if (_T_10642) begin
-        bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_197 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_197 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39079,7 +39079,7 @@ end // initial
       bht_bank_rd_data_out_1_198 <= 2'h0;
     end else if (bht_bank_sel_1_12_6) begin
       if (_T_10651) begin
-        bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_198 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_198 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39090,7 +39090,7 @@ end // initial
       bht_bank_rd_data_out_1_199 <= 2'h0;
     end else if (bht_bank_sel_1_12_7) begin
       if (_T_10660) begin
-        bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_199 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_199 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39101,7 +39101,7 @@ end // initial
       bht_bank_rd_data_out_1_200 <= 2'h0;
     end else if (bht_bank_sel_1_12_8) begin
       if (_T_10669) begin
-        bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_200 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_200 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39112,7 +39112,7 @@ end // initial
       bht_bank_rd_data_out_1_201 <= 2'h0;
     end else if (bht_bank_sel_1_12_9) begin
       if (_T_10678) begin
-        bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_201 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_201 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39123,7 +39123,7 @@ end // initial
       bht_bank_rd_data_out_1_202 <= 2'h0;
     end else if (bht_bank_sel_1_12_10) begin
       if (_T_10687) begin
-        bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_202 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_202 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39134,7 +39134,7 @@ end // initial
       bht_bank_rd_data_out_1_203 <= 2'h0;
     end else if (bht_bank_sel_1_12_11) begin
       if (_T_10696) begin
-        bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_203 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_203 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39145,7 +39145,7 @@ end // initial
       bht_bank_rd_data_out_1_204 <= 2'h0;
     end else if (bht_bank_sel_1_12_12) begin
       if (_T_10705) begin
-        bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_204 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_204 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39156,7 +39156,7 @@ end // initial
       bht_bank_rd_data_out_1_205 <= 2'h0;
     end else if (bht_bank_sel_1_12_13) begin
       if (_T_10714) begin
-        bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_205 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_205 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39167,7 +39167,7 @@ end // initial
       bht_bank_rd_data_out_1_206 <= 2'h0;
     end else if (bht_bank_sel_1_12_14) begin
       if (_T_10723) begin
-        bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_206 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_206 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39178,7 +39178,7 @@ end // initial
       bht_bank_rd_data_out_1_207 <= 2'h0;
     end else if (bht_bank_sel_1_12_15) begin
       if (_T_10732) begin
-        bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_207 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_207 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39189,7 +39189,7 @@ end // initial
       bht_bank_rd_data_out_1_208 <= 2'h0;
     end else if (bht_bank_sel_1_13_0) begin
       if (_T_10741) begin
-        bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_208 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_208 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39200,7 +39200,7 @@ end // initial
       bht_bank_rd_data_out_1_209 <= 2'h0;
     end else if (bht_bank_sel_1_13_1) begin
       if (_T_10750) begin
-        bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_209 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_209 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39211,7 +39211,7 @@ end // initial
       bht_bank_rd_data_out_1_210 <= 2'h0;
     end else if (bht_bank_sel_1_13_2) begin
       if (_T_10759) begin
-        bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_210 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_210 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39222,7 +39222,7 @@ end // initial
       bht_bank_rd_data_out_1_211 <= 2'h0;
     end else if (bht_bank_sel_1_13_3) begin
       if (_T_10768) begin
-        bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_211 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_211 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39233,7 +39233,7 @@ end // initial
       bht_bank_rd_data_out_1_212 <= 2'h0;
     end else if (bht_bank_sel_1_13_4) begin
       if (_T_10777) begin
-        bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_212 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_212 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39244,7 +39244,7 @@ end // initial
       bht_bank_rd_data_out_1_213 <= 2'h0;
     end else if (bht_bank_sel_1_13_5) begin
       if (_T_10786) begin
-        bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_213 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_213 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39255,7 +39255,7 @@ end // initial
       bht_bank_rd_data_out_1_214 <= 2'h0;
     end else if (bht_bank_sel_1_13_6) begin
       if (_T_10795) begin
-        bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_214 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_214 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39266,7 +39266,7 @@ end // initial
       bht_bank_rd_data_out_1_215 <= 2'h0;
     end else if (bht_bank_sel_1_13_7) begin
       if (_T_10804) begin
-        bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_215 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_215 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39277,7 +39277,7 @@ end // initial
       bht_bank_rd_data_out_1_216 <= 2'h0;
     end else if (bht_bank_sel_1_13_8) begin
       if (_T_10813) begin
-        bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_216 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_216 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39288,7 +39288,7 @@ end // initial
       bht_bank_rd_data_out_1_217 <= 2'h0;
     end else if (bht_bank_sel_1_13_9) begin
       if (_T_10822) begin
-        bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_217 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_217 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39299,7 +39299,7 @@ end // initial
       bht_bank_rd_data_out_1_218 <= 2'h0;
     end else if (bht_bank_sel_1_13_10) begin
       if (_T_10831) begin
-        bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_218 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_218 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39310,7 +39310,7 @@ end // initial
       bht_bank_rd_data_out_1_219 <= 2'h0;
     end else if (bht_bank_sel_1_13_11) begin
       if (_T_10840) begin
-        bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_219 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_219 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39321,7 +39321,7 @@ end // initial
       bht_bank_rd_data_out_1_220 <= 2'h0;
     end else if (bht_bank_sel_1_13_12) begin
       if (_T_10849) begin
-        bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_220 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_220 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39332,7 +39332,7 @@ end // initial
       bht_bank_rd_data_out_1_221 <= 2'h0;
     end else if (bht_bank_sel_1_13_13) begin
       if (_T_10858) begin
-        bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_221 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_221 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39343,7 +39343,7 @@ end // initial
       bht_bank_rd_data_out_1_222 <= 2'h0;
     end else if (bht_bank_sel_1_13_14) begin
       if (_T_10867) begin
-        bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_222 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_222 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39354,7 +39354,7 @@ end // initial
       bht_bank_rd_data_out_1_223 <= 2'h0;
     end else if (bht_bank_sel_1_13_15) begin
       if (_T_10876) begin
-        bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_223 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_223 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39365,7 +39365,7 @@ end // initial
       bht_bank_rd_data_out_1_224 <= 2'h0;
     end else if (bht_bank_sel_1_14_0) begin
       if (_T_10885) begin
-        bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_224 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_224 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39376,7 +39376,7 @@ end // initial
       bht_bank_rd_data_out_1_225 <= 2'h0;
     end else if (bht_bank_sel_1_14_1) begin
       if (_T_10894) begin
-        bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_225 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_225 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39387,7 +39387,7 @@ end // initial
       bht_bank_rd_data_out_1_226 <= 2'h0;
     end else if (bht_bank_sel_1_14_2) begin
       if (_T_10903) begin
-        bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_226 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_226 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39398,7 +39398,7 @@ end // initial
       bht_bank_rd_data_out_1_227 <= 2'h0;
     end else if (bht_bank_sel_1_14_3) begin
       if (_T_10912) begin
-        bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_227 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_227 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39409,7 +39409,7 @@ end // initial
       bht_bank_rd_data_out_1_228 <= 2'h0;
     end else if (bht_bank_sel_1_14_4) begin
       if (_T_10921) begin
-        bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_228 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_228 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39420,7 +39420,7 @@ end // initial
       bht_bank_rd_data_out_1_229 <= 2'h0;
     end else if (bht_bank_sel_1_14_5) begin
       if (_T_10930) begin
-        bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_229 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_229 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39431,7 +39431,7 @@ end // initial
       bht_bank_rd_data_out_1_230 <= 2'h0;
     end else if (bht_bank_sel_1_14_6) begin
       if (_T_10939) begin
-        bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_230 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_230 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39442,7 +39442,7 @@ end // initial
       bht_bank_rd_data_out_1_231 <= 2'h0;
     end else if (bht_bank_sel_1_14_7) begin
       if (_T_10948) begin
-        bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_231 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_231 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39453,7 +39453,7 @@ end // initial
       bht_bank_rd_data_out_1_232 <= 2'h0;
     end else if (bht_bank_sel_1_14_8) begin
       if (_T_10957) begin
-        bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_232 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_232 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39464,7 +39464,7 @@ end // initial
       bht_bank_rd_data_out_1_233 <= 2'h0;
     end else if (bht_bank_sel_1_14_9) begin
       if (_T_10966) begin
-        bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_233 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_233 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39475,7 +39475,7 @@ end // initial
       bht_bank_rd_data_out_1_234 <= 2'h0;
     end else if (bht_bank_sel_1_14_10) begin
       if (_T_10975) begin
-        bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_234 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_234 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39486,7 +39486,7 @@ end // initial
       bht_bank_rd_data_out_1_235 <= 2'h0;
     end else if (bht_bank_sel_1_14_11) begin
       if (_T_10984) begin
-        bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_235 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_235 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39497,7 +39497,7 @@ end // initial
       bht_bank_rd_data_out_1_236 <= 2'h0;
     end else if (bht_bank_sel_1_14_12) begin
       if (_T_10993) begin
-        bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_236 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_236 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39508,7 +39508,7 @@ end // initial
       bht_bank_rd_data_out_1_237 <= 2'h0;
     end else if (bht_bank_sel_1_14_13) begin
       if (_T_11002) begin
-        bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_237 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_237 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39519,7 +39519,7 @@ end // initial
       bht_bank_rd_data_out_1_238 <= 2'h0;
     end else if (bht_bank_sel_1_14_14) begin
       if (_T_11011) begin
-        bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_238 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_238 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39530,7 +39530,7 @@ end // initial
       bht_bank_rd_data_out_1_239 <= 2'h0;
     end else if (bht_bank_sel_1_14_15) begin
       if (_T_11020) begin
-        bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_239 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_239 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39541,7 +39541,7 @@ end // initial
       bht_bank_rd_data_out_1_240 <= 2'h0;
     end else if (bht_bank_sel_1_15_0) begin
       if (_T_11029) begin
-        bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_240 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_240 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39552,7 +39552,7 @@ end // initial
       bht_bank_rd_data_out_1_241 <= 2'h0;
     end else if (bht_bank_sel_1_15_1) begin
       if (_T_11038) begin
-        bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_241 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_241 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39563,7 +39563,7 @@ end // initial
       bht_bank_rd_data_out_1_242 <= 2'h0;
     end else if (bht_bank_sel_1_15_2) begin
       if (_T_11047) begin
-        bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_242 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_242 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39574,7 +39574,7 @@ end // initial
       bht_bank_rd_data_out_1_243 <= 2'h0;
     end else if (bht_bank_sel_1_15_3) begin
       if (_T_11056) begin
-        bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_243 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_243 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39585,7 +39585,7 @@ end // initial
       bht_bank_rd_data_out_1_244 <= 2'h0;
     end else if (bht_bank_sel_1_15_4) begin
       if (_T_11065) begin
-        bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_244 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_244 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39596,7 +39596,7 @@ end // initial
       bht_bank_rd_data_out_1_245 <= 2'h0;
     end else if (bht_bank_sel_1_15_5) begin
       if (_T_11074) begin
-        bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_245 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_245 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39607,7 +39607,7 @@ end // initial
       bht_bank_rd_data_out_1_246 <= 2'h0;
     end else if (bht_bank_sel_1_15_6) begin
       if (_T_11083) begin
-        bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_246 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_246 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39618,7 +39618,7 @@ end // initial
       bht_bank_rd_data_out_1_247 <= 2'h0;
     end else if (bht_bank_sel_1_15_7) begin
       if (_T_11092) begin
-        bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_247 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_247 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39629,7 +39629,7 @@ end // initial
       bht_bank_rd_data_out_1_248 <= 2'h0;
     end else if (bht_bank_sel_1_15_8) begin
       if (_T_11101) begin
-        bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_248 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_248 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39640,7 +39640,7 @@ end // initial
       bht_bank_rd_data_out_1_249 <= 2'h0;
     end else if (bht_bank_sel_1_15_9) begin
       if (_T_11110) begin
-        bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_249 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_249 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39651,7 +39651,7 @@ end // initial
       bht_bank_rd_data_out_1_250 <= 2'h0;
     end else if (bht_bank_sel_1_15_10) begin
       if (_T_11119) begin
-        bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_250 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_250 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39662,7 +39662,7 @@ end // initial
       bht_bank_rd_data_out_1_251 <= 2'h0;
     end else if (bht_bank_sel_1_15_11) begin
       if (_T_11128) begin
-        bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_251 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_251 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39673,7 +39673,7 @@ end // initial
       bht_bank_rd_data_out_1_252 <= 2'h0;
     end else if (bht_bank_sel_1_15_12) begin
       if (_T_11137) begin
-        bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_252 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_252 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39684,7 +39684,7 @@ end // initial
       bht_bank_rd_data_out_1_253 <= 2'h0;
     end else if (bht_bank_sel_1_15_13) begin
       if (_T_11146) begin
-        bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_253 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_253 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39695,7 +39695,7 @@ end // initial
       bht_bank_rd_data_out_1_254 <= 2'h0;
     end else if (bht_bank_sel_1_15_14) begin
       if (_T_11155) begin
-        bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_254 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_254 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39706,7 +39706,7 @@ end // initial
       bht_bank_rd_data_out_1_255 <= 2'h0;
     end else if (bht_bank_sel_1_15_15) begin
       if (_T_11164) begin
-        bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_1_255 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_1_255 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39717,7 +39717,7 @@ end // initial
       bht_bank_rd_data_out_0_0 <= 2'h0;
     end else if (bht_bank_sel_0_0_0) begin
       if (_T_6565) begin
-        bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_0 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_0 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39728,7 +39728,7 @@ end // initial
       bht_bank_rd_data_out_0_1 <= 2'h0;
     end else if (bht_bank_sel_0_0_1) begin
       if (_T_6574) begin
-        bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_1 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_1 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39739,7 +39739,7 @@ end // initial
       bht_bank_rd_data_out_0_2 <= 2'h0;
     end else if (bht_bank_sel_0_0_2) begin
       if (_T_6583) begin
-        bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_2 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_2 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39750,7 +39750,7 @@ end // initial
       bht_bank_rd_data_out_0_3 <= 2'h0;
     end else if (bht_bank_sel_0_0_3) begin
       if (_T_6592) begin
-        bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_3 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_3 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39761,7 +39761,7 @@ end // initial
       bht_bank_rd_data_out_0_4 <= 2'h0;
     end else if (bht_bank_sel_0_0_4) begin
       if (_T_6601) begin
-        bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_4 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_4 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39772,7 +39772,7 @@ end // initial
       bht_bank_rd_data_out_0_5 <= 2'h0;
     end else if (bht_bank_sel_0_0_5) begin
       if (_T_6610) begin
-        bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_5 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_5 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39783,7 +39783,7 @@ end // initial
       bht_bank_rd_data_out_0_6 <= 2'h0;
     end else if (bht_bank_sel_0_0_6) begin
       if (_T_6619) begin
-        bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_6 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_6 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39794,7 +39794,7 @@ end // initial
       bht_bank_rd_data_out_0_7 <= 2'h0;
     end else if (bht_bank_sel_0_0_7) begin
       if (_T_6628) begin
-        bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_7 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_7 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39805,7 +39805,7 @@ end // initial
       bht_bank_rd_data_out_0_8 <= 2'h0;
     end else if (bht_bank_sel_0_0_8) begin
       if (_T_6637) begin
-        bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_8 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_8 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39816,7 +39816,7 @@ end // initial
       bht_bank_rd_data_out_0_9 <= 2'h0;
     end else if (bht_bank_sel_0_0_9) begin
       if (_T_6646) begin
-        bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_9 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_9 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39827,7 +39827,7 @@ end // initial
       bht_bank_rd_data_out_0_10 <= 2'h0;
     end else if (bht_bank_sel_0_0_10) begin
       if (_T_6655) begin
-        bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_10 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_10 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39838,7 +39838,7 @@ end // initial
       bht_bank_rd_data_out_0_11 <= 2'h0;
     end else if (bht_bank_sel_0_0_11) begin
       if (_T_6664) begin
-        bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_11 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_11 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39849,7 +39849,7 @@ end // initial
       bht_bank_rd_data_out_0_12 <= 2'h0;
     end else if (bht_bank_sel_0_0_12) begin
       if (_T_6673) begin
-        bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_12 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_12 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39860,7 +39860,7 @@ end // initial
       bht_bank_rd_data_out_0_13 <= 2'h0;
     end else if (bht_bank_sel_0_0_13) begin
       if (_T_6682) begin
-        bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_13 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_13 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39871,7 +39871,7 @@ end // initial
       bht_bank_rd_data_out_0_14 <= 2'h0;
     end else if (bht_bank_sel_0_0_14) begin
       if (_T_6691) begin
-        bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_14 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_14 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39882,7 +39882,7 @@ end // initial
       bht_bank_rd_data_out_0_15 <= 2'h0;
     end else if (bht_bank_sel_0_0_15) begin
       if (_T_6700) begin
-        bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_15 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_15 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39893,7 +39893,7 @@ end // initial
       bht_bank_rd_data_out_0_16 <= 2'h0;
     end else if (bht_bank_sel_0_1_0) begin
       if (_T_6709) begin
-        bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_16 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_16 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39904,7 +39904,7 @@ end // initial
       bht_bank_rd_data_out_0_17 <= 2'h0;
     end else if (bht_bank_sel_0_1_1) begin
       if (_T_6718) begin
-        bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_17 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_17 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39915,7 +39915,7 @@ end // initial
       bht_bank_rd_data_out_0_18 <= 2'h0;
     end else if (bht_bank_sel_0_1_2) begin
       if (_T_6727) begin
-        bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_18 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_18 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39926,7 +39926,7 @@ end // initial
       bht_bank_rd_data_out_0_19 <= 2'h0;
     end else if (bht_bank_sel_0_1_3) begin
       if (_T_6736) begin
-        bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_19 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_19 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39937,7 +39937,7 @@ end // initial
       bht_bank_rd_data_out_0_20 <= 2'h0;
     end else if (bht_bank_sel_0_1_4) begin
       if (_T_6745) begin
-        bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_20 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_20 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39948,7 +39948,7 @@ end // initial
       bht_bank_rd_data_out_0_21 <= 2'h0;
     end else if (bht_bank_sel_0_1_5) begin
       if (_T_6754) begin
-        bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_21 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_21 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39959,7 +39959,7 @@ end // initial
       bht_bank_rd_data_out_0_22 <= 2'h0;
     end else if (bht_bank_sel_0_1_6) begin
       if (_T_6763) begin
-        bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_22 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_22 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39970,7 +39970,7 @@ end // initial
       bht_bank_rd_data_out_0_23 <= 2'h0;
     end else if (bht_bank_sel_0_1_7) begin
       if (_T_6772) begin
-        bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_23 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_23 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39981,7 +39981,7 @@ end // initial
       bht_bank_rd_data_out_0_24 <= 2'h0;
     end else if (bht_bank_sel_0_1_8) begin
       if (_T_6781) begin
-        bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_24 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_24 <= io_exu_mp_pkt_bits_hist;
       end
@@ -39992,7 +39992,7 @@ end // initial
       bht_bank_rd_data_out_0_25 <= 2'h0;
     end else if (bht_bank_sel_0_1_9) begin
       if (_T_6790) begin
-        bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_25 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_25 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40003,7 +40003,7 @@ end // initial
       bht_bank_rd_data_out_0_26 <= 2'h0;
     end else if (bht_bank_sel_0_1_10) begin
       if (_T_6799) begin
-        bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_26 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_26 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40014,7 +40014,7 @@ end // initial
       bht_bank_rd_data_out_0_27 <= 2'h0;
     end else if (bht_bank_sel_0_1_11) begin
       if (_T_6808) begin
-        bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_27 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_27 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40025,7 +40025,7 @@ end // initial
       bht_bank_rd_data_out_0_28 <= 2'h0;
     end else if (bht_bank_sel_0_1_12) begin
       if (_T_6817) begin
-        bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_28 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_28 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40036,7 +40036,7 @@ end // initial
       bht_bank_rd_data_out_0_29 <= 2'h0;
     end else if (bht_bank_sel_0_1_13) begin
       if (_T_6826) begin
-        bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_29 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_29 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40047,7 +40047,7 @@ end // initial
       bht_bank_rd_data_out_0_30 <= 2'h0;
     end else if (bht_bank_sel_0_1_14) begin
       if (_T_6835) begin
-        bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_30 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_30 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40058,7 +40058,7 @@ end // initial
       bht_bank_rd_data_out_0_31 <= 2'h0;
     end else if (bht_bank_sel_0_1_15) begin
       if (_T_6844) begin
-        bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_31 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_31 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40069,7 +40069,7 @@ end // initial
       bht_bank_rd_data_out_0_32 <= 2'h0;
     end else if (bht_bank_sel_0_2_0) begin
       if (_T_6853) begin
-        bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_32 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_32 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40080,7 +40080,7 @@ end // initial
       bht_bank_rd_data_out_0_33 <= 2'h0;
     end else if (bht_bank_sel_0_2_1) begin
       if (_T_6862) begin
-        bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_33 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_33 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40091,7 +40091,7 @@ end // initial
       bht_bank_rd_data_out_0_34 <= 2'h0;
     end else if (bht_bank_sel_0_2_2) begin
       if (_T_6871) begin
-        bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_34 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_34 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40102,7 +40102,7 @@ end // initial
       bht_bank_rd_data_out_0_35 <= 2'h0;
     end else if (bht_bank_sel_0_2_3) begin
       if (_T_6880) begin
-        bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_35 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_35 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40113,7 +40113,7 @@ end // initial
       bht_bank_rd_data_out_0_36 <= 2'h0;
     end else if (bht_bank_sel_0_2_4) begin
       if (_T_6889) begin
-        bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_36 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_36 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40124,7 +40124,7 @@ end // initial
       bht_bank_rd_data_out_0_37 <= 2'h0;
     end else if (bht_bank_sel_0_2_5) begin
       if (_T_6898) begin
-        bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_37 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_37 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40135,7 +40135,7 @@ end // initial
       bht_bank_rd_data_out_0_38 <= 2'h0;
     end else if (bht_bank_sel_0_2_6) begin
       if (_T_6907) begin
-        bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_38 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_38 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40146,7 +40146,7 @@ end // initial
       bht_bank_rd_data_out_0_39 <= 2'h0;
     end else if (bht_bank_sel_0_2_7) begin
       if (_T_6916) begin
-        bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_39 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_39 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40157,7 +40157,7 @@ end // initial
       bht_bank_rd_data_out_0_40 <= 2'h0;
     end else if (bht_bank_sel_0_2_8) begin
       if (_T_6925) begin
-        bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_40 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_40 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40168,7 +40168,7 @@ end // initial
       bht_bank_rd_data_out_0_41 <= 2'h0;
     end else if (bht_bank_sel_0_2_9) begin
       if (_T_6934) begin
-        bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_41 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_41 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40179,7 +40179,7 @@ end // initial
       bht_bank_rd_data_out_0_42 <= 2'h0;
     end else if (bht_bank_sel_0_2_10) begin
       if (_T_6943) begin
-        bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_42 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_42 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40190,7 +40190,7 @@ end // initial
       bht_bank_rd_data_out_0_43 <= 2'h0;
     end else if (bht_bank_sel_0_2_11) begin
       if (_T_6952) begin
-        bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_43 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_43 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40201,7 +40201,7 @@ end // initial
       bht_bank_rd_data_out_0_44 <= 2'h0;
     end else if (bht_bank_sel_0_2_12) begin
       if (_T_6961) begin
-        bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_44 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_44 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40212,7 +40212,7 @@ end // initial
       bht_bank_rd_data_out_0_45 <= 2'h0;
     end else if (bht_bank_sel_0_2_13) begin
       if (_T_6970) begin
-        bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_45 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_45 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40223,7 +40223,7 @@ end // initial
       bht_bank_rd_data_out_0_46 <= 2'h0;
     end else if (bht_bank_sel_0_2_14) begin
       if (_T_6979) begin
-        bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_46 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_46 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40234,7 +40234,7 @@ end // initial
       bht_bank_rd_data_out_0_47 <= 2'h0;
     end else if (bht_bank_sel_0_2_15) begin
       if (_T_6988) begin
-        bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_47 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_47 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40245,7 +40245,7 @@ end // initial
       bht_bank_rd_data_out_0_48 <= 2'h0;
     end else if (bht_bank_sel_0_3_0) begin
       if (_T_6997) begin
-        bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_48 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_48 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40256,7 +40256,7 @@ end // initial
       bht_bank_rd_data_out_0_49 <= 2'h0;
     end else if (bht_bank_sel_0_3_1) begin
       if (_T_7006) begin
-        bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_49 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_49 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40267,7 +40267,7 @@ end // initial
       bht_bank_rd_data_out_0_50 <= 2'h0;
     end else if (bht_bank_sel_0_3_2) begin
       if (_T_7015) begin
-        bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_50 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_50 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40278,7 +40278,7 @@ end // initial
       bht_bank_rd_data_out_0_51 <= 2'h0;
     end else if (bht_bank_sel_0_3_3) begin
       if (_T_7024) begin
-        bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_51 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_51 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40289,7 +40289,7 @@ end // initial
       bht_bank_rd_data_out_0_52 <= 2'h0;
     end else if (bht_bank_sel_0_3_4) begin
       if (_T_7033) begin
-        bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_52 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_52 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40300,7 +40300,7 @@ end // initial
       bht_bank_rd_data_out_0_53 <= 2'h0;
     end else if (bht_bank_sel_0_3_5) begin
       if (_T_7042) begin
-        bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_53 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_53 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40311,7 +40311,7 @@ end // initial
       bht_bank_rd_data_out_0_54 <= 2'h0;
     end else if (bht_bank_sel_0_3_6) begin
       if (_T_7051) begin
-        bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_54 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_54 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40322,7 +40322,7 @@ end // initial
       bht_bank_rd_data_out_0_55 <= 2'h0;
     end else if (bht_bank_sel_0_3_7) begin
       if (_T_7060) begin
-        bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_55 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_55 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40333,7 +40333,7 @@ end // initial
       bht_bank_rd_data_out_0_56 <= 2'h0;
     end else if (bht_bank_sel_0_3_8) begin
       if (_T_7069) begin
-        bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_56 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_56 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40344,7 +40344,7 @@ end // initial
       bht_bank_rd_data_out_0_57 <= 2'h0;
     end else if (bht_bank_sel_0_3_9) begin
       if (_T_7078) begin
-        bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_57 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_57 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40355,7 +40355,7 @@ end // initial
       bht_bank_rd_data_out_0_58 <= 2'h0;
     end else if (bht_bank_sel_0_3_10) begin
       if (_T_7087) begin
-        bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_58 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_58 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40366,7 +40366,7 @@ end // initial
       bht_bank_rd_data_out_0_59 <= 2'h0;
     end else if (bht_bank_sel_0_3_11) begin
       if (_T_7096) begin
-        bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_59 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_59 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40377,7 +40377,7 @@ end // initial
       bht_bank_rd_data_out_0_60 <= 2'h0;
     end else if (bht_bank_sel_0_3_12) begin
       if (_T_7105) begin
-        bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_60 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_60 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40388,7 +40388,7 @@ end // initial
       bht_bank_rd_data_out_0_61 <= 2'h0;
     end else if (bht_bank_sel_0_3_13) begin
       if (_T_7114) begin
-        bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_61 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_61 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40399,7 +40399,7 @@ end // initial
       bht_bank_rd_data_out_0_62 <= 2'h0;
     end else if (bht_bank_sel_0_3_14) begin
       if (_T_7123) begin
-        bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_62 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_62 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40410,7 +40410,7 @@ end // initial
       bht_bank_rd_data_out_0_63 <= 2'h0;
     end else if (bht_bank_sel_0_3_15) begin
       if (_T_7132) begin
-        bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_63 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_63 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40421,7 +40421,7 @@ end // initial
       bht_bank_rd_data_out_0_64 <= 2'h0;
     end else if (bht_bank_sel_0_4_0) begin
       if (_T_7141) begin
-        bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_64 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_64 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40432,7 +40432,7 @@ end // initial
       bht_bank_rd_data_out_0_65 <= 2'h0;
     end else if (bht_bank_sel_0_4_1) begin
       if (_T_7150) begin
-        bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_65 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_65 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40443,7 +40443,7 @@ end // initial
       bht_bank_rd_data_out_0_66 <= 2'h0;
     end else if (bht_bank_sel_0_4_2) begin
       if (_T_7159) begin
-        bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_66 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_66 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40454,7 +40454,7 @@ end // initial
       bht_bank_rd_data_out_0_67 <= 2'h0;
     end else if (bht_bank_sel_0_4_3) begin
       if (_T_7168) begin
-        bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_67 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_67 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40465,7 +40465,7 @@ end // initial
       bht_bank_rd_data_out_0_68 <= 2'h0;
     end else if (bht_bank_sel_0_4_4) begin
       if (_T_7177) begin
-        bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_68 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_68 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40476,7 +40476,7 @@ end // initial
       bht_bank_rd_data_out_0_69 <= 2'h0;
     end else if (bht_bank_sel_0_4_5) begin
       if (_T_7186) begin
-        bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_69 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_69 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40487,7 +40487,7 @@ end // initial
       bht_bank_rd_data_out_0_70 <= 2'h0;
     end else if (bht_bank_sel_0_4_6) begin
       if (_T_7195) begin
-        bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_70 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_70 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40498,7 +40498,7 @@ end // initial
       bht_bank_rd_data_out_0_71 <= 2'h0;
     end else if (bht_bank_sel_0_4_7) begin
       if (_T_7204) begin
-        bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_71 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_71 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40509,7 +40509,7 @@ end // initial
       bht_bank_rd_data_out_0_72 <= 2'h0;
     end else if (bht_bank_sel_0_4_8) begin
       if (_T_7213) begin
-        bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_72 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_72 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40520,7 +40520,7 @@ end // initial
       bht_bank_rd_data_out_0_73 <= 2'h0;
     end else if (bht_bank_sel_0_4_9) begin
       if (_T_7222) begin
-        bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_73 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_73 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40531,7 +40531,7 @@ end // initial
       bht_bank_rd_data_out_0_74 <= 2'h0;
     end else if (bht_bank_sel_0_4_10) begin
       if (_T_7231) begin
-        bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_74 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_74 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40542,7 +40542,7 @@ end // initial
       bht_bank_rd_data_out_0_75 <= 2'h0;
     end else if (bht_bank_sel_0_4_11) begin
       if (_T_7240) begin
-        bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_75 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_75 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40553,7 +40553,7 @@ end // initial
       bht_bank_rd_data_out_0_76 <= 2'h0;
     end else if (bht_bank_sel_0_4_12) begin
       if (_T_7249) begin
-        bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_76 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_76 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40564,7 +40564,7 @@ end // initial
       bht_bank_rd_data_out_0_77 <= 2'h0;
     end else if (bht_bank_sel_0_4_13) begin
       if (_T_7258) begin
-        bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_77 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_77 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40575,7 +40575,7 @@ end // initial
       bht_bank_rd_data_out_0_78 <= 2'h0;
     end else if (bht_bank_sel_0_4_14) begin
       if (_T_7267) begin
-        bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_78 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_78 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40586,7 +40586,7 @@ end // initial
       bht_bank_rd_data_out_0_79 <= 2'h0;
     end else if (bht_bank_sel_0_4_15) begin
       if (_T_7276) begin
-        bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_79 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_79 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40597,7 +40597,7 @@ end // initial
       bht_bank_rd_data_out_0_80 <= 2'h0;
     end else if (bht_bank_sel_0_5_0) begin
       if (_T_7285) begin
-        bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_80 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_80 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40608,7 +40608,7 @@ end // initial
       bht_bank_rd_data_out_0_81 <= 2'h0;
     end else if (bht_bank_sel_0_5_1) begin
       if (_T_7294) begin
-        bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_81 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_81 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40619,7 +40619,7 @@ end // initial
       bht_bank_rd_data_out_0_82 <= 2'h0;
     end else if (bht_bank_sel_0_5_2) begin
       if (_T_7303) begin
-        bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_82 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_82 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40630,7 +40630,7 @@ end // initial
       bht_bank_rd_data_out_0_83 <= 2'h0;
     end else if (bht_bank_sel_0_5_3) begin
       if (_T_7312) begin
-        bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_83 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_83 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40641,7 +40641,7 @@ end // initial
       bht_bank_rd_data_out_0_84 <= 2'h0;
     end else if (bht_bank_sel_0_5_4) begin
       if (_T_7321) begin
-        bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_84 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_84 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40652,7 +40652,7 @@ end // initial
       bht_bank_rd_data_out_0_85 <= 2'h0;
     end else if (bht_bank_sel_0_5_5) begin
       if (_T_7330) begin
-        bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_85 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_85 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40663,7 +40663,7 @@ end // initial
       bht_bank_rd_data_out_0_86 <= 2'h0;
     end else if (bht_bank_sel_0_5_6) begin
       if (_T_7339) begin
-        bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_86 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_86 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40674,7 +40674,7 @@ end // initial
       bht_bank_rd_data_out_0_87 <= 2'h0;
     end else if (bht_bank_sel_0_5_7) begin
       if (_T_7348) begin
-        bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_87 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_87 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40685,7 +40685,7 @@ end // initial
       bht_bank_rd_data_out_0_88 <= 2'h0;
     end else if (bht_bank_sel_0_5_8) begin
       if (_T_7357) begin
-        bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_88 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_88 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40696,7 +40696,7 @@ end // initial
       bht_bank_rd_data_out_0_89 <= 2'h0;
     end else if (bht_bank_sel_0_5_9) begin
       if (_T_7366) begin
-        bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_89 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_89 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40707,7 +40707,7 @@ end // initial
       bht_bank_rd_data_out_0_90 <= 2'h0;
     end else if (bht_bank_sel_0_5_10) begin
       if (_T_7375) begin
-        bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_90 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_90 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40718,7 +40718,7 @@ end // initial
       bht_bank_rd_data_out_0_91 <= 2'h0;
     end else if (bht_bank_sel_0_5_11) begin
       if (_T_7384) begin
-        bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_91 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_91 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40729,7 +40729,7 @@ end // initial
       bht_bank_rd_data_out_0_92 <= 2'h0;
     end else if (bht_bank_sel_0_5_12) begin
       if (_T_7393) begin
-        bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_92 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_92 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40740,7 +40740,7 @@ end // initial
       bht_bank_rd_data_out_0_93 <= 2'h0;
     end else if (bht_bank_sel_0_5_13) begin
       if (_T_7402) begin
-        bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_93 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_93 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40751,7 +40751,7 @@ end // initial
       bht_bank_rd_data_out_0_94 <= 2'h0;
     end else if (bht_bank_sel_0_5_14) begin
       if (_T_7411) begin
-        bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_94 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_94 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40762,7 +40762,7 @@ end // initial
       bht_bank_rd_data_out_0_95 <= 2'h0;
     end else if (bht_bank_sel_0_5_15) begin
       if (_T_7420) begin
-        bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_95 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_95 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40773,7 +40773,7 @@ end // initial
       bht_bank_rd_data_out_0_96 <= 2'h0;
     end else if (bht_bank_sel_0_6_0) begin
       if (_T_7429) begin
-        bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_96 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_96 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40784,7 +40784,7 @@ end // initial
       bht_bank_rd_data_out_0_97 <= 2'h0;
     end else if (bht_bank_sel_0_6_1) begin
       if (_T_7438) begin
-        bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_97 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_97 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40795,7 +40795,7 @@ end // initial
       bht_bank_rd_data_out_0_98 <= 2'h0;
     end else if (bht_bank_sel_0_6_2) begin
       if (_T_7447) begin
-        bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_98 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_98 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40806,7 +40806,7 @@ end // initial
       bht_bank_rd_data_out_0_99 <= 2'h0;
     end else if (bht_bank_sel_0_6_3) begin
       if (_T_7456) begin
-        bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_99 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_99 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40817,7 +40817,7 @@ end // initial
       bht_bank_rd_data_out_0_100 <= 2'h0;
     end else if (bht_bank_sel_0_6_4) begin
       if (_T_7465) begin
-        bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_100 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_100 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40828,7 +40828,7 @@ end // initial
       bht_bank_rd_data_out_0_101 <= 2'h0;
     end else if (bht_bank_sel_0_6_5) begin
       if (_T_7474) begin
-        bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_101 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_101 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40839,7 +40839,7 @@ end // initial
       bht_bank_rd_data_out_0_102 <= 2'h0;
     end else if (bht_bank_sel_0_6_6) begin
       if (_T_7483) begin
-        bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_102 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_102 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40850,7 +40850,7 @@ end // initial
       bht_bank_rd_data_out_0_103 <= 2'h0;
     end else if (bht_bank_sel_0_6_7) begin
       if (_T_7492) begin
-        bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_103 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_103 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40861,7 +40861,7 @@ end // initial
       bht_bank_rd_data_out_0_104 <= 2'h0;
     end else if (bht_bank_sel_0_6_8) begin
       if (_T_7501) begin
-        bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_104 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_104 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40872,7 +40872,7 @@ end // initial
       bht_bank_rd_data_out_0_105 <= 2'h0;
     end else if (bht_bank_sel_0_6_9) begin
       if (_T_7510) begin
-        bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_105 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_105 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40883,7 +40883,7 @@ end // initial
       bht_bank_rd_data_out_0_106 <= 2'h0;
     end else if (bht_bank_sel_0_6_10) begin
       if (_T_7519) begin
-        bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_106 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_106 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40894,7 +40894,7 @@ end // initial
       bht_bank_rd_data_out_0_107 <= 2'h0;
     end else if (bht_bank_sel_0_6_11) begin
       if (_T_7528) begin
-        bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_107 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_107 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40905,7 +40905,7 @@ end // initial
       bht_bank_rd_data_out_0_108 <= 2'h0;
     end else if (bht_bank_sel_0_6_12) begin
       if (_T_7537) begin
-        bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_108 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_108 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40916,7 +40916,7 @@ end // initial
       bht_bank_rd_data_out_0_109 <= 2'h0;
     end else if (bht_bank_sel_0_6_13) begin
       if (_T_7546) begin
-        bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_109 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_109 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40927,7 +40927,7 @@ end // initial
       bht_bank_rd_data_out_0_110 <= 2'h0;
     end else if (bht_bank_sel_0_6_14) begin
       if (_T_7555) begin
-        bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_110 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_110 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40938,7 +40938,7 @@ end // initial
       bht_bank_rd_data_out_0_111 <= 2'h0;
     end else if (bht_bank_sel_0_6_15) begin
       if (_T_7564) begin
-        bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_111 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_111 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40949,7 +40949,7 @@ end // initial
       bht_bank_rd_data_out_0_112 <= 2'h0;
     end else if (bht_bank_sel_0_7_0) begin
       if (_T_7573) begin
-        bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_112 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_112 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40960,7 +40960,7 @@ end // initial
       bht_bank_rd_data_out_0_113 <= 2'h0;
     end else if (bht_bank_sel_0_7_1) begin
       if (_T_7582) begin
-        bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_113 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_113 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40971,7 +40971,7 @@ end // initial
       bht_bank_rd_data_out_0_114 <= 2'h0;
     end else if (bht_bank_sel_0_7_2) begin
       if (_T_7591) begin
-        bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_114 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_114 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40982,7 +40982,7 @@ end // initial
       bht_bank_rd_data_out_0_115 <= 2'h0;
     end else if (bht_bank_sel_0_7_3) begin
       if (_T_7600) begin
-        bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_115 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_115 <= io_exu_mp_pkt_bits_hist;
       end
@@ -40993,7 +40993,7 @@ end // initial
       bht_bank_rd_data_out_0_116 <= 2'h0;
     end else if (bht_bank_sel_0_7_4) begin
       if (_T_7609) begin
-        bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_116 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_116 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41004,7 +41004,7 @@ end // initial
       bht_bank_rd_data_out_0_117 <= 2'h0;
     end else if (bht_bank_sel_0_7_5) begin
       if (_T_7618) begin
-        bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_117 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_117 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41015,7 +41015,7 @@ end // initial
       bht_bank_rd_data_out_0_118 <= 2'h0;
     end else if (bht_bank_sel_0_7_6) begin
       if (_T_7627) begin
-        bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_118 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_118 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41026,7 +41026,7 @@ end // initial
       bht_bank_rd_data_out_0_119 <= 2'h0;
     end else if (bht_bank_sel_0_7_7) begin
       if (_T_7636) begin
-        bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_119 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_119 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41037,7 +41037,7 @@ end // initial
       bht_bank_rd_data_out_0_120 <= 2'h0;
     end else if (bht_bank_sel_0_7_8) begin
       if (_T_7645) begin
-        bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_120 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_120 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41048,7 +41048,7 @@ end // initial
       bht_bank_rd_data_out_0_121 <= 2'h0;
     end else if (bht_bank_sel_0_7_9) begin
       if (_T_7654) begin
-        bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_121 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_121 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41059,7 +41059,7 @@ end // initial
       bht_bank_rd_data_out_0_122 <= 2'h0;
     end else if (bht_bank_sel_0_7_10) begin
       if (_T_7663) begin
-        bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_122 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_122 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41070,7 +41070,7 @@ end // initial
       bht_bank_rd_data_out_0_123 <= 2'h0;
     end else if (bht_bank_sel_0_7_11) begin
       if (_T_7672) begin
-        bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_123 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_123 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41081,7 +41081,7 @@ end // initial
       bht_bank_rd_data_out_0_124 <= 2'h0;
     end else if (bht_bank_sel_0_7_12) begin
       if (_T_7681) begin
-        bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_124 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_124 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41092,7 +41092,7 @@ end // initial
       bht_bank_rd_data_out_0_125 <= 2'h0;
     end else if (bht_bank_sel_0_7_13) begin
       if (_T_7690) begin
-        bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_125 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_125 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41103,7 +41103,7 @@ end // initial
       bht_bank_rd_data_out_0_126 <= 2'h0;
     end else if (bht_bank_sel_0_7_14) begin
       if (_T_7699) begin
-        bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_126 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_126 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41114,7 +41114,7 @@ end // initial
       bht_bank_rd_data_out_0_127 <= 2'h0;
     end else if (bht_bank_sel_0_7_15) begin
       if (_T_7708) begin
-        bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_127 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_127 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41125,7 +41125,7 @@ end // initial
       bht_bank_rd_data_out_0_128 <= 2'h0;
     end else if (bht_bank_sel_0_8_0) begin
       if (_T_7717) begin
-        bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_128 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_128 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41136,7 +41136,7 @@ end // initial
       bht_bank_rd_data_out_0_129 <= 2'h0;
     end else if (bht_bank_sel_0_8_1) begin
       if (_T_7726) begin
-        bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_129 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_129 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41147,7 +41147,7 @@ end // initial
       bht_bank_rd_data_out_0_130 <= 2'h0;
     end else if (bht_bank_sel_0_8_2) begin
       if (_T_7735) begin
-        bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_130 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_130 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41158,7 +41158,7 @@ end // initial
       bht_bank_rd_data_out_0_131 <= 2'h0;
     end else if (bht_bank_sel_0_8_3) begin
       if (_T_7744) begin
-        bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_131 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_131 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41169,7 +41169,7 @@ end // initial
       bht_bank_rd_data_out_0_132 <= 2'h0;
     end else if (bht_bank_sel_0_8_4) begin
       if (_T_7753) begin
-        bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_132 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_132 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41180,7 +41180,7 @@ end // initial
       bht_bank_rd_data_out_0_133 <= 2'h0;
     end else if (bht_bank_sel_0_8_5) begin
       if (_T_7762) begin
-        bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_133 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_133 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41191,7 +41191,7 @@ end // initial
       bht_bank_rd_data_out_0_134 <= 2'h0;
     end else if (bht_bank_sel_0_8_6) begin
       if (_T_7771) begin
-        bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_134 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_134 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41202,7 +41202,7 @@ end // initial
       bht_bank_rd_data_out_0_135 <= 2'h0;
     end else if (bht_bank_sel_0_8_7) begin
       if (_T_7780) begin
-        bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_135 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_135 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41213,7 +41213,7 @@ end // initial
       bht_bank_rd_data_out_0_136 <= 2'h0;
     end else if (bht_bank_sel_0_8_8) begin
       if (_T_7789) begin
-        bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_136 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_136 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41224,7 +41224,7 @@ end // initial
       bht_bank_rd_data_out_0_137 <= 2'h0;
     end else if (bht_bank_sel_0_8_9) begin
       if (_T_7798) begin
-        bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_137 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_137 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41235,7 +41235,7 @@ end // initial
       bht_bank_rd_data_out_0_138 <= 2'h0;
     end else if (bht_bank_sel_0_8_10) begin
       if (_T_7807) begin
-        bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_138 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_138 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41246,7 +41246,7 @@ end // initial
       bht_bank_rd_data_out_0_139 <= 2'h0;
     end else if (bht_bank_sel_0_8_11) begin
       if (_T_7816) begin
-        bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_139 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_139 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41257,7 +41257,7 @@ end // initial
       bht_bank_rd_data_out_0_140 <= 2'h0;
     end else if (bht_bank_sel_0_8_12) begin
       if (_T_7825) begin
-        bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_140 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_140 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41268,7 +41268,7 @@ end // initial
       bht_bank_rd_data_out_0_141 <= 2'h0;
     end else if (bht_bank_sel_0_8_13) begin
       if (_T_7834) begin
-        bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_141 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_141 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41279,7 +41279,7 @@ end // initial
       bht_bank_rd_data_out_0_142 <= 2'h0;
     end else if (bht_bank_sel_0_8_14) begin
       if (_T_7843) begin
-        bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_142 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_142 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41290,7 +41290,7 @@ end // initial
       bht_bank_rd_data_out_0_143 <= 2'h0;
     end else if (bht_bank_sel_0_8_15) begin
       if (_T_7852) begin
-        bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_143 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_143 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41301,7 +41301,7 @@ end // initial
       bht_bank_rd_data_out_0_144 <= 2'h0;
     end else if (bht_bank_sel_0_9_0) begin
       if (_T_7861) begin
-        bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_144 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_144 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41312,7 +41312,7 @@ end // initial
       bht_bank_rd_data_out_0_145 <= 2'h0;
     end else if (bht_bank_sel_0_9_1) begin
       if (_T_7870) begin
-        bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_145 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_145 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41323,7 +41323,7 @@ end // initial
       bht_bank_rd_data_out_0_146 <= 2'h0;
     end else if (bht_bank_sel_0_9_2) begin
       if (_T_7879) begin
-        bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_146 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_146 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41334,7 +41334,7 @@ end // initial
       bht_bank_rd_data_out_0_147 <= 2'h0;
     end else if (bht_bank_sel_0_9_3) begin
       if (_T_7888) begin
-        bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_147 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_147 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41345,7 +41345,7 @@ end // initial
       bht_bank_rd_data_out_0_148 <= 2'h0;
     end else if (bht_bank_sel_0_9_4) begin
       if (_T_7897) begin
-        bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_148 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_148 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41356,7 +41356,7 @@ end // initial
       bht_bank_rd_data_out_0_149 <= 2'h0;
     end else if (bht_bank_sel_0_9_5) begin
       if (_T_7906) begin
-        bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_149 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_149 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41367,7 +41367,7 @@ end // initial
       bht_bank_rd_data_out_0_150 <= 2'h0;
     end else if (bht_bank_sel_0_9_6) begin
       if (_T_7915) begin
-        bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_150 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_150 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41378,7 +41378,7 @@ end // initial
       bht_bank_rd_data_out_0_151 <= 2'h0;
     end else if (bht_bank_sel_0_9_7) begin
       if (_T_7924) begin
-        bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_151 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_151 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41389,7 +41389,7 @@ end // initial
       bht_bank_rd_data_out_0_152 <= 2'h0;
     end else if (bht_bank_sel_0_9_8) begin
       if (_T_7933) begin
-        bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_152 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_152 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41400,7 +41400,7 @@ end // initial
       bht_bank_rd_data_out_0_153 <= 2'h0;
     end else if (bht_bank_sel_0_9_9) begin
       if (_T_7942) begin
-        bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_153 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_153 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41411,7 +41411,7 @@ end // initial
       bht_bank_rd_data_out_0_154 <= 2'h0;
     end else if (bht_bank_sel_0_9_10) begin
       if (_T_7951) begin
-        bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_154 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_154 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41422,7 +41422,7 @@ end // initial
       bht_bank_rd_data_out_0_155 <= 2'h0;
     end else if (bht_bank_sel_0_9_11) begin
       if (_T_7960) begin
-        bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_155 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_155 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41433,7 +41433,7 @@ end // initial
       bht_bank_rd_data_out_0_156 <= 2'h0;
     end else if (bht_bank_sel_0_9_12) begin
       if (_T_7969) begin
-        bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_156 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_156 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41444,7 +41444,7 @@ end // initial
       bht_bank_rd_data_out_0_157 <= 2'h0;
     end else if (bht_bank_sel_0_9_13) begin
       if (_T_7978) begin
-        bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_157 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_157 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41455,7 +41455,7 @@ end // initial
       bht_bank_rd_data_out_0_158 <= 2'h0;
     end else if (bht_bank_sel_0_9_14) begin
       if (_T_7987) begin
-        bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_158 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_158 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41466,7 +41466,7 @@ end // initial
       bht_bank_rd_data_out_0_159 <= 2'h0;
     end else if (bht_bank_sel_0_9_15) begin
       if (_T_7996) begin
-        bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_159 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_159 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41477,7 +41477,7 @@ end // initial
       bht_bank_rd_data_out_0_160 <= 2'h0;
     end else if (bht_bank_sel_0_10_0) begin
       if (_T_8005) begin
-        bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_160 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_160 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41488,7 +41488,7 @@ end // initial
       bht_bank_rd_data_out_0_161 <= 2'h0;
     end else if (bht_bank_sel_0_10_1) begin
       if (_T_8014) begin
-        bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_161 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_161 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41499,7 +41499,7 @@ end // initial
       bht_bank_rd_data_out_0_162 <= 2'h0;
     end else if (bht_bank_sel_0_10_2) begin
       if (_T_8023) begin
-        bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_162 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_162 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41510,7 +41510,7 @@ end // initial
       bht_bank_rd_data_out_0_163 <= 2'h0;
     end else if (bht_bank_sel_0_10_3) begin
       if (_T_8032) begin
-        bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_163 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_163 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41521,7 +41521,7 @@ end // initial
       bht_bank_rd_data_out_0_164 <= 2'h0;
     end else if (bht_bank_sel_0_10_4) begin
       if (_T_8041) begin
-        bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_164 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_164 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41532,7 +41532,7 @@ end // initial
       bht_bank_rd_data_out_0_165 <= 2'h0;
     end else if (bht_bank_sel_0_10_5) begin
       if (_T_8050) begin
-        bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_165 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_165 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41543,7 +41543,7 @@ end // initial
       bht_bank_rd_data_out_0_166 <= 2'h0;
     end else if (bht_bank_sel_0_10_6) begin
       if (_T_8059) begin
-        bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_166 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_166 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41554,7 +41554,7 @@ end // initial
       bht_bank_rd_data_out_0_167 <= 2'h0;
     end else if (bht_bank_sel_0_10_7) begin
       if (_T_8068) begin
-        bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_167 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_167 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41565,7 +41565,7 @@ end // initial
       bht_bank_rd_data_out_0_168 <= 2'h0;
     end else if (bht_bank_sel_0_10_8) begin
       if (_T_8077) begin
-        bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_168 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_168 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41576,7 +41576,7 @@ end // initial
       bht_bank_rd_data_out_0_169 <= 2'h0;
     end else if (bht_bank_sel_0_10_9) begin
       if (_T_8086) begin
-        bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_169 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_169 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41587,7 +41587,7 @@ end // initial
       bht_bank_rd_data_out_0_170 <= 2'h0;
     end else if (bht_bank_sel_0_10_10) begin
       if (_T_8095) begin
-        bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_170 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_170 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41598,7 +41598,7 @@ end // initial
       bht_bank_rd_data_out_0_171 <= 2'h0;
     end else if (bht_bank_sel_0_10_11) begin
       if (_T_8104) begin
-        bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_171 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_171 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41609,7 +41609,7 @@ end // initial
       bht_bank_rd_data_out_0_172 <= 2'h0;
     end else if (bht_bank_sel_0_10_12) begin
       if (_T_8113) begin
-        bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_172 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_172 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41620,7 +41620,7 @@ end // initial
       bht_bank_rd_data_out_0_173 <= 2'h0;
     end else if (bht_bank_sel_0_10_13) begin
       if (_T_8122) begin
-        bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_173 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_173 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41631,7 +41631,7 @@ end // initial
       bht_bank_rd_data_out_0_174 <= 2'h0;
     end else if (bht_bank_sel_0_10_14) begin
       if (_T_8131) begin
-        bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_174 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_174 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41642,7 +41642,7 @@ end // initial
       bht_bank_rd_data_out_0_175 <= 2'h0;
     end else if (bht_bank_sel_0_10_15) begin
       if (_T_8140) begin
-        bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_175 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_175 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41653,7 +41653,7 @@ end // initial
       bht_bank_rd_data_out_0_176 <= 2'h0;
     end else if (bht_bank_sel_0_11_0) begin
       if (_T_8149) begin
-        bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_176 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_176 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41664,7 +41664,7 @@ end // initial
       bht_bank_rd_data_out_0_177 <= 2'h0;
     end else if (bht_bank_sel_0_11_1) begin
       if (_T_8158) begin
-        bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_177 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_177 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41675,7 +41675,7 @@ end // initial
       bht_bank_rd_data_out_0_178 <= 2'h0;
     end else if (bht_bank_sel_0_11_2) begin
       if (_T_8167) begin
-        bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_178 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_178 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41686,7 +41686,7 @@ end // initial
       bht_bank_rd_data_out_0_179 <= 2'h0;
     end else if (bht_bank_sel_0_11_3) begin
       if (_T_8176) begin
-        bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_179 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_179 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41697,7 +41697,7 @@ end // initial
       bht_bank_rd_data_out_0_180 <= 2'h0;
     end else if (bht_bank_sel_0_11_4) begin
       if (_T_8185) begin
-        bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_180 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_180 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41708,7 +41708,7 @@ end // initial
       bht_bank_rd_data_out_0_181 <= 2'h0;
     end else if (bht_bank_sel_0_11_5) begin
       if (_T_8194) begin
-        bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_181 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_181 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41719,7 +41719,7 @@ end // initial
       bht_bank_rd_data_out_0_182 <= 2'h0;
     end else if (bht_bank_sel_0_11_6) begin
       if (_T_8203) begin
-        bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_182 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_182 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41730,7 +41730,7 @@ end // initial
       bht_bank_rd_data_out_0_183 <= 2'h0;
     end else if (bht_bank_sel_0_11_7) begin
       if (_T_8212) begin
-        bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_183 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_183 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41741,7 +41741,7 @@ end // initial
       bht_bank_rd_data_out_0_184 <= 2'h0;
     end else if (bht_bank_sel_0_11_8) begin
       if (_T_8221) begin
-        bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_184 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_184 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41752,7 +41752,7 @@ end // initial
       bht_bank_rd_data_out_0_185 <= 2'h0;
     end else if (bht_bank_sel_0_11_9) begin
       if (_T_8230) begin
-        bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_185 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_185 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41763,7 +41763,7 @@ end // initial
       bht_bank_rd_data_out_0_186 <= 2'h0;
     end else if (bht_bank_sel_0_11_10) begin
       if (_T_8239) begin
-        bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_186 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_186 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41774,7 +41774,7 @@ end // initial
       bht_bank_rd_data_out_0_187 <= 2'h0;
     end else if (bht_bank_sel_0_11_11) begin
       if (_T_8248) begin
-        bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_187 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_187 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41785,7 +41785,7 @@ end // initial
       bht_bank_rd_data_out_0_188 <= 2'h0;
     end else if (bht_bank_sel_0_11_12) begin
       if (_T_8257) begin
-        bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_188 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_188 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41796,7 +41796,7 @@ end // initial
       bht_bank_rd_data_out_0_189 <= 2'h0;
     end else if (bht_bank_sel_0_11_13) begin
       if (_T_8266) begin
-        bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_189 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_189 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41807,7 +41807,7 @@ end // initial
       bht_bank_rd_data_out_0_190 <= 2'h0;
     end else if (bht_bank_sel_0_11_14) begin
       if (_T_8275) begin
-        bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_190 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_190 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41818,7 +41818,7 @@ end // initial
       bht_bank_rd_data_out_0_191 <= 2'h0;
     end else if (bht_bank_sel_0_11_15) begin
       if (_T_8284) begin
-        bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_191 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_191 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41829,7 +41829,7 @@ end // initial
       bht_bank_rd_data_out_0_192 <= 2'h0;
     end else if (bht_bank_sel_0_12_0) begin
       if (_T_8293) begin
-        bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_192 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_192 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41840,7 +41840,7 @@ end // initial
       bht_bank_rd_data_out_0_193 <= 2'h0;
     end else if (bht_bank_sel_0_12_1) begin
       if (_T_8302) begin
-        bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_193 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_193 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41851,7 +41851,7 @@ end // initial
       bht_bank_rd_data_out_0_194 <= 2'h0;
     end else if (bht_bank_sel_0_12_2) begin
       if (_T_8311) begin
-        bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_194 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_194 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41862,7 +41862,7 @@ end // initial
       bht_bank_rd_data_out_0_195 <= 2'h0;
     end else if (bht_bank_sel_0_12_3) begin
       if (_T_8320) begin
-        bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_195 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_195 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41873,7 +41873,7 @@ end // initial
       bht_bank_rd_data_out_0_196 <= 2'h0;
     end else if (bht_bank_sel_0_12_4) begin
       if (_T_8329) begin
-        bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_196 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_196 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41884,7 +41884,7 @@ end // initial
       bht_bank_rd_data_out_0_197 <= 2'h0;
     end else if (bht_bank_sel_0_12_5) begin
       if (_T_8338) begin
-        bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_197 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_197 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41895,7 +41895,7 @@ end // initial
       bht_bank_rd_data_out_0_198 <= 2'h0;
     end else if (bht_bank_sel_0_12_6) begin
       if (_T_8347) begin
-        bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_198 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_198 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41906,7 +41906,7 @@ end // initial
       bht_bank_rd_data_out_0_199 <= 2'h0;
     end else if (bht_bank_sel_0_12_7) begin
       if (_T_8356) begin
-        bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_199 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_199 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41917,7 +41917,7 @@ end // initial
       bht_bank_rd_data_out_0_200 <= 2'h0;
     end else if (bht_bank_sel_0_12_8) begin
       if (_T_8365) begin
-        bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_200 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_200 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41928,7 +41928,7 @@ end // initial
       bht_bank_rd_data_out_0_201 <= 2'h0;
     end else if (bht_bank_sel_0_12_9) begin
       if (_T_8374) begin
-        bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_201 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_201 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41939,7 +41939,7 @@ end // initial
       bht_bank_rd_data_out_0_202 <= 2'h0;
     end else if (bht_bank_sel_0_12_10) begin
       if (_T_8383) begin
-        bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_202 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_202 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41950,7 +41950,7 @@ end // initial
       bht_bank_rd_data_out_0_203 <= 2'h0;
     end else if (bht_bank_sel_0_12_11) begin
       if (_T_8392) begin
-        bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_203 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_203 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41961,7 +41961,7 @@ end // initial
       bht_bank_rd_data_out_0_204 <= 2'h0;
     end else if (bht_bank_sel_0_12_12) begin
       if (_T_8401) begin
-        bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_204 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_204 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41972,7 +41972,7 @@ end // initial
       bht_bank_rd_data_out_0_205 <= 2'h0;
     end else if (bht_bank_sel_0_12_13) begin
       if (_T_8410) begin
-        bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_205 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_205 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41983,7 +41983,7 @@ end // initial
       bht_bank_rd_data_out_0_206 <= 2'h0;
     end else if (bht_bank_sel_0_12_14) begin
       if (_T_8419) begin
-        bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_206 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_206 <= io_exu_mp_pkt_bits_hist;
       end
@@ -41994,7 +41994,7 @@ end // initial
       bht_bank_rd_data_out_0_207 <= 2'h0;
     end else if (bht_bank_sel_0_12_15) begin
       if (_T_8428) begin
-        bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_207 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_207 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42005,7 +42005,7 @@ end // initial
       bht_bank_rd_data_out_0_208 <= 2'h0;
     end else if (bht_bank_sel_0_13_0) begin
       if (_T_8437) begin
-        bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_208 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_208 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42016,7 +42016,7 @@ end // initial
       bht_bank_rd_data_out_0_209 <= 2'h0;
     end else if (bht_bank_sel_0_13_1) begin
       if (_T_8446) begin
-        bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_209 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_209 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42027,7 +42027,7 @@ end // initial
       bht_bank_rd_data_out_0_210 <= 2'h0;
     end else if (bht_bank_sel_0_13_2) begin
       if (_T_8455) begin
-        bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_210 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_210 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42038,7 +42038,7 @@ end // initial
       bht_bank_rd_data_out_0_211 <= 2'h0;
     end else if (bht_bank_sel_0_13_3) begin
       if (_T_8464) begin
-        bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_211 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_211 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42049,7 +42049,7 @@ end // initial
       bht_bank_rd_data_out_0_212 <= 2'h0;
     end else if (bht_bank_sel_0_13_4) begin
       if (_T_8473) begin
-        bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_212 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_212 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42060,7 +42060,7 @@ end // initial
       bht_bank_rd_data_out_0_213 <= 2'h0;
     end else if (bht_bank_sel_0_13_5) begin
       if (_T_8482) begin
-        bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_213 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_213 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42071,7 +42071,7 @@ end // initial
       bht_bank_rd_data_out_0_214 <= 2'h0;
     end else if (bht_bank_sel_0_13_6) begin
       if (_T_8491) begin
-        bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_214 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_214 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42082,7 +42082,7 @@ end // initial
       bht_bank_rd_data_out_0_215 <= 2'h0;
     end else if (bht_bank_sel_0_13_7) begin
       if (_T_8500) begin
-        bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_215 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_215 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42093,7 +42093,7 @@ end // initial
       bht_bank_rd_data_out_0_216 <= 2'h0;
     end else if (bht_bank_sel_0_13_8) begin
       if (_T_8509) begin
-        bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_216 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_216 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42104,7 +42104,7 @@ end // initial
       bht_bank_rd_data_out_0_217 <= 2'h0;
     end else if (bht_bank_sel_0_13_9) begin
       if (_T_8518) begin
-        bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_217 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_217 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42115,7 +42115,7 @@ end // initial
       bht_bank_rd_data_out_0_218 <= 2'h0;
     end else if (bht_bank_sel_0_13_10) begin
       if (_T_8527) begin
-        bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_218 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_218 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42126,7 +42126,7 @@ end // initial
       bht_bank_rd_data_out_0_219 <= 2'h0;
     end else if (bht_bank_sel_0_13_11) begin
       if (_T_8536) begin
-        bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_219 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_219 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42137,7 +42137,7 @@ end // initial
       bht_bank_rd_data_out_0_220 <= 2'h0;
     end else if (bht_bank_sel_0_13_12) begin
       if (_T_8545) begin
-        bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_220 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_220 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42148,7 +42148,7 @@ end // initial
       bht_bank_rd_data_out_0_221 <= 2'h0;
     end else if (bht_bank_sel_0_13_13) begin
       if (_T_8554) begin
-        bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_221 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_221 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42159,7 +42159,7 @@ end // initial
       bht_bank_rd_data_out_0_222 <= 2'h0;
     end else if (bht_bank_sel_0_13_14) begin
       if (_T_8563) begin
-        bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_222 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_222 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42170,7 +42170,7 @@ end // initial
       bht_bank_rd_data_out_0_223 <= 2'h0;
     end else if (bht_bank_sel_0_13_15) begin
       if (_T_8572) begin
-        bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_223 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_223 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42181,7 +42181,7 @@ end // initial
       bht_bank_rd_data_out_0_224 <= 2'h0;
     end else if (bht_bank_sel_0_14_0) begin
       if (_T_8581) begin
-        bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_224 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_224 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42192,7 +42192,7 @@ end // initial
       bht_bank_rd_data_out_0_225 <= 2'h0;
     end else if (bht_bank_sel_0_14_1) begin
       if (_T_8590) begin
-        bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_225 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_225 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42203,7 +42203,7 @@ end // initial
       bht_bank_rd_data_out_0_226 <= 2'h0;
     end else if (bht_bank_sel_0_14_2) begin
       if (_T_8599) begin
-        bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_226 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_226 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42214,7 +42214,7 @@ end // initial
       bht_bank_rd_data_out_0_227 <= 2'h0;
     end else if (bht_bank_sel_0_14_3) begin
       if (_T_8608) begin
-        bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_227 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_227 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42225,7 +42225,7 @@ end // initial
       bht_bank_rd_data_out_0_228 <= 2'h0;
     end else if (bht_bank_sel_0_14_4) begin
       if (_T_8617) begin
-        bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_228 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_228 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42236,7 +42236,7 @@ end // initial
       bht_bank_rd_data_out_0_229 <= 2'h0;
     end else if (bht_bank_sel_0_14_5) begin
       if (_T_8626) begin
-        bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_229 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_229 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42247,7 +42247,7 @@ end // initial
       bht_bank_rd_data_out_0_230 <= 2'h0;
     end else if (bht_bank_sel_0_14_6) begin
       if (_T_8635) begin
-        bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_230 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_230 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42258,7 +42258,7 @@ end // initial
       bht_bank_rd_data_out_0_231 <= 2'h0;
     end else if (bht_bank_sel_0_14_7) begin
       if (_T_8644) begin
-        bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_231 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_231 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42269,7 +42269,7 @@ end // initial
       bht_bank_rd_data_out_0_232 <= 2'h0;
     end else if (bht_bank_sel_0_14_8) begin
       if (_T_8653) begin
-        bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_232 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_232 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42280,7 +42280,7 @@ end // initial
       bht_bank_rd_data_out_0_233 <= 2'h0;
     end else if (bht_bank_sel_0_14_9) begin
       if (_T_8662) begin
-        bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_233 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_233 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42291,7 +42291,7 @@ end // initial
       bht_bank_rd_data_out_0_234 <= 2'h0;
     end else if (bht_bank_sel_0_14_10) begin
       if (_T_8671) begin
-        bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_234 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_234 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42302,7 +42302,7 @@ end // initial
       bht_bank_rd_data_out_0_235 <= 2'h0;
     end else if (bht_bank_sel_0_14_11) begin
       if (_T_8680) begin
-        bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_235 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_235 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42313,7 +42313,7 @@ end // initial
       bht_bank_rd_data_out_0_236 <= 2'h0;
     end else if (bht_bank_sel_0_14_12) begin
       if (_T_8689) begin
-        bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_236 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_236 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42324,7 +42324,7 @@ end // initial
       bht_bank_rd_data_out_0_237 <= 2'h0;
     end else if (bht_bank_sel_0_14_13) begin
       if (_T_8698) begin
-        bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_237 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_237 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42335,7 +42335,7 @@ end // initial
       bht_bank_rd_data_out_0_238 <= 2'h0;
     end else if (bht_bank_sel_0_14_14) begin
       if (_T_8707) begin
-        bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_238 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_238 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42346,7 +42346,7 @@ end // initial
       bht_bank_rd_data_out_0_239 <= 2'h0;
     end else if (bht_bank_sel_0_14_15) begin
       if (_T_8716) begin
-        bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_239 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_239 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42357,7 +42357,7 @@ end // initial
       bht_bank_rd_data_out_0_240 <= 2'h0;
     end else if (bht_bank_sel_0_15_0) begin
       if (_T_8725) begin
-        bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_240 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_240 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42368,7 +42368,7 @@ end // initial
       bht_bank_rd_data_out_0_241 <= 2'h0;
     end else if (bht_bank_sel_0_15_1) begin
       if (_T_8734) begin
-        bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_241 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_241 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42379,7 +42379,7 @@ end // initial
       bht_bank_rd_data_out_0_242 <= 2'h0;
     end else if (bht_bank_sel_0_15_2) begin
       if (_T_8743) begin
-        bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_242 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_242 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42390,7 +42390,7 @@ end // initial
       bht_bank_rd_data_out_0_243 <= 2'h0;
     end else if (bht_bank_sel_0_15_3) begin
       if (_T_8752) begin
-        bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_243 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_243 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42401,7 +42401,7 @@ end // initial
       bht_bank_rd_data_out_0_244 <= 2'h0;
     end else if (bht_bank_sel_0_15_4) begin
       if (_T_8761) begin
-        bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_244 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_244 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42412,7 +42412,7 @@ end // initial
       bht_bank_rd_data_out_0_245 <= 2'h0;
     end else if (bht_bank_sel_0_15_5) begin
       if (_T_8770) begin
-        bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_245 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_245 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42423,7 +42423,7 @@ end // initial
       bht_bank_rd_data_out_0_246 <= 2'h0;
     end else if (bht_bank_sel_0_15_6) begin
       if (_T_8779) begin
-        bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_246 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_246 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42434,7 +42434,7 @@ end // initial
       bht_bank_rd_data_out_0_247 <= 2'h0;
     end else if (bht_bank_sel_0_15_7) begin
       if (_T_8788) begin
-        bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_247 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_247 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42445,7 +42445,7 @@ end // initial
       bht_bank_rd_data_out_0_248 <= 2'h0;
     end else if (bht_bank_sel_0_15_8) begin
       if (_T_8797) begin
-        bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_248 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_248 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42456,7 +42456,7 @@ end // initial
       bht_bank_rd_data_out_0_249 <= 2'h0;
     end else if (bht_bank_sel_0_15_9) begin
       if (_T_8806) begin
-        bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_249 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_249 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42467,7 +42467,7 @@ end // initial
       bht_bank_rd_data_out_0_250 <= 2'h0;
     end else if (bht_bank_sel_0_15_10) begin
       if (_T_8815) begin
-        bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_250 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_250 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42478,7 +42478,7 @@ end // initial
       bht_bank_rd_data_out_0_251 <= 2'h0;
     end else if (bht_bank_sel_0_15_11) begin
       if (_T_8824) begin
-        bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_251 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_251 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42489,7 +42489,7 @@ end // initial
       bht_bank_rd_data_out_0_252 <= 2'h0;
     end else if (bht_bank_sel_0_15_12) begin
       if (_T_8833) begin
-        bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_252 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_252 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42500,7 +42500,7 @@ end // initial
       bht_bank_rd_data_out_0_253 <= 2'h0;
     end else if (bht_bank_sel_0_15_13) begin
       if (_T_8842) begin
-        bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_253 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_253 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42511,7 +42511,7 @@ end // initial
       bht_bank_rd_data_out_0_254 <= 2'h0;
     end else if (bht_bank_sel_0_15_14) begin
       if (_T_8851) begin
-        bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_254 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_254 <= io_exu_mp_pkt_bits_hist;
       end
@@ -42522,7 +42522,7 @@ end // initial
       bht_bank_rd_data_out_0_255 <= 2'h0;
     end else if (bht_bank_sel_0_15_15) begin
       if (_T_8860) begin
-        bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_hist;
+        bht_bank_rd_data_out_0_255 <= io_dec_tlu_br0_r_pkt_bits_hist;
       end else begin
         bht_bank_rd_data_out_0_255 <= io_exu_mp_pkt_bits_hist;
       end
@@ -43161,13 +43161,13 @@ module el2_ifu_aln_ctl(
   output        io_ifu_pmu_instr_aligned,
   output [15:0] io_ifu_i0_cinst,
   output        io_i0_brp_valid,
-  output [11:0] io_i0_brp_toffset,
-  output [1:0]  io_i0_brp_hist,
-  output        io_i0_brp_br_error,
-  output        io_i0_brp_br_start_error,
-  output [30:0] io_i0_brp_prett,
-  output        io_i0_brp_way,
-  output        io_i0_brp_ret
+  output [11:0] io_i0_brp_bits_toffset,
+  output [1:0]  io_i0_brp_bits_hist,
+  output        io_i0_brp_bits_br_error,
+  output        io_i0_brp_bits_br_start_error,
+  output [30:0] io_i0_brp_bits_prett,
+  output        io_i0_brp_bits_way,
+  output        io_i0_brp_bits_ret
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
@@ -43606,24 +43606,24 @@ module el2_ifu_aln_ctl(
   wire  _T_721 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 378:58]
   wire  _T_722 = _T_719 | _T_721; // @[el2_ifu_aln_ctl.scala 378:47]
   wire  _T_726 = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:100]
-  wire  _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:29]
-  wire  _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:55]
+  wire  _T_729 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 380:34]
+  wire  _T_731 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 380:60]
   wire  _T_734 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 382:29]
   wire  _T_736 = first4B & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 382:55]
   wire  i0_brp_pc4 = _T_734 | _T_736; // @[el2_ifu_aln_ctl.scala 382:44]
-  wire  _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:33]
-  wire  _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:34]
-  wire  _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:62]
-  wire  _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:51]
+  wire  _T_738 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 384:38]
+  wire  _T_744 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 386:39]
+  wire  _T_746 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 386:67]
+  wire  _T_747 = _T_744 | _T_746; // @[el2_ifu_aln_ctl.scala 386:56]
   wire  _T_749 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 387:14]
   wire  _T_751 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 387:42]
   wire  _T_752 = _T_749 | _T_751; // @[el2_ifu_aln_ctl.scala 387:31]
   wire  i0_ends_f1 = first4B & _T_515; // @[el2_ifu_aln_ctl.scala 389:28]
-  wire  _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:42]
-  wire  _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:56]
-  wire  _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:89]
-  wire  _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:87]
-  wire  _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:101]
+  wire  _T_768 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:47]
+  wire  _T_769 = _T_768 & first2B; // @[el2_ifu_aln_ctl.scala 398:61]
+  wire  _T_770 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 398:94]
+  wire  _T_771 = io_i0_brp_valid & _T_770; // @[el2_ifu_aln_ctl.scala 398:92]
+  wire  _T_772 = _T_771 & first4B; // @[el2_ifu_aln_ctl.scala 398:106]
   rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -43716,13 +43716,13 @@ module el2_ifu_aln_ctl(
   assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_785; // @[el2_ifu_aln_ctl.scala 60:28 el2_ifu_aln_ctl.scala 410:28]
   assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 61:19 el2_ifu_aln_ctl.scala 346:19]
   assign io_i0_brp_valid = _T_722 | _T_726; // @[el2_ifu_aln_ctl.scala 378:19]
-  assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:21]
-  assign io_i0_brp_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:18]
-  assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22]
-  assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29]
-  assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19]
-  assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17]
-  assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17]
+  assign io_i0_brp_bits_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 390:26]
+  assign io_i0_brp_bits_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:23]
+  assign io_i0_brp_bits_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:27]
+  assign io_i0_brp_bits_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:34]
+  assign io_i0_brp_bits_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:24]
+  assign io_i0_brp_bits_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:22]
+  assign io_i0_brp_bits_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:22]
   assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
   assign rvclkhdr_io_en = _T_354 | _T_358; // @[el2_lib.scala 511:17]
   assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
@@ -44448,13 +44448,13 @@ module el2_ifu(
   output        io_ifu_i0_pc4,
   output        io_ifu_miss_state_idle,
   output        io_i0_brp_valid,
-  output [11:0] io_i0_brp_toffset,
-  output [1:0]  io_i0_brp_hist,
-  output        io_i0_brp_br_error,
-  output        io_i0_brp_br_start_error,
-  output [30:0] io_i0_brp_prett,
-  output        io_i0_brp_way,
-  output        io_i0_brp_ret,
+  output [11:0] io_i0_brp_bits_toffset,
+  output [1:0]  io_i0_brp_bits_hist,
+  output        io_i0_brp_bits_br_error,
+  output        io_i0_brp_bits_br_start_error,
+  output [30:0] io_i0_brp_bits_prett,
+  output        io_i0_brp_bits_way,
+  output        io_i0_brp_bits_ret,
   output [7:0]  io_ifu_i0_bp_index,
   output [7:0]  io_ifu_i0_bp_fghr,
   output [4:0]  io_ifu_i0_bp_btag,
@@ -44473,11 +44473,11 @@ module el2_ifu(
   input  [7:0]  io_exu_mp_index,
   input  [4:0]  io_exu_mp_btag,
   input         io_dec_tlu_br0_r_pkt_valid,
-  input  [1:0]  io_dec_tlu_br0_r_pkt_hist,
-  input         io_dec_tlu_br0_r_pkt_br_error,
-  input         io_dec_tlu_br0_r_pkt_br_start_error,
-  input         io_dec_tlu_br0_r_pkt_way,
-  input         io_dec_tlu_br0_r_pkt_middle,
+  input  [1:0]  io_dec_tlu_br0_r_pkt_bits_hist,
+  input         io_dec_tlu_br0_r_pkt_bits_br_error,
+  input         io_dec_tlu_br0_r_pkt_bits_br_start_error,
+  input         io_dec_tlu_br0_r_pkt_bits_way,
+  input         io_dec_tlu_br0_r_pkt_bits_middle,
   input  [7:0]  io_exu_i0_br_fghr_r,
   input  [7:0]  io_exu_i0_br_index_r,
   input         io_dec_tlu_flush_lower_wb,
@@ -44596,11 +44596,11 @@ module el2_ifu(
   wire [30:0] bp_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 147:25]
   wire  bp_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 147:25]
   wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 147:25]
-  wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 147:25]
-  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 147:25]
-  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 147:25]
-  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 147:25]
-  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 147:25]
+  wire [1:0] bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 147:25]
+  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 147:25]
+  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 147:25]
+  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 147:25]
+  wire  bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 147:25]
   wire [7:0] bp_ctl_ch_io_exu_i0_br_fghr_r; // @[el2_ifu.scala 147:25]
   wire [7:0] bp_ctl_ch_io_exu_i0_br_index_r; // @[el2_ifu.scala 147:25]
   wire  bp_ctl_ch_io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 147:25]
@@ -44671,13 +44671,13 @@ module el2_ifu(
   wire  aln_ctl_ch_io_ifu_pmu_instr_aligned; // @[el2_ifu.scala 148:26]
   wire [15:0] aln_ctl_ch_io_ifu_i0_cinst; // @[el2_ifu.scala 148:26]
   wire  aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 148:26]
-  wire [11:0] aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 148:26]
-  wire [1:0] aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 148:26]
-  wire  aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 148:26]
-  wire  aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 148:26]
-  wire [30:0] aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 148:26]
-  wire  aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 148:26]
-  wire  aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 148:26]
+  wire [11:0] aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 148:26]
+  wire [1:0] aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 148:26]
+  wire  aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 148:26]
+  wire  aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 148:26]
+  wire [30:0] aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 148:26]
+  wire  aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 148:26]
+  wire  aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 148:26]
   wire  ifc_ctl_ch_clock; // @[el2_ifu.scala 149:26]
   wire  ifc_ctl_ch_reset; // @[el2_ifu.scala 149:26]
   wire  ifc_ctl_ch_io_free_clk; // @[el2_ifu.scala 149:26]
@@ -44814,11 +44814,11 @@ module el2_ifu(
     .io_ifc_fetch_addr_f(bp_ctl_ch_io_ifc_fetch_addr_f),
     .io_ifc_fetch_req_f(bp_ctl_ch_io_ifc_fetch_req_f),
     .io_dec_tlu_br0_r_pkt_valid(bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid),
-    .io_dec_tlu_br0_r_pkt_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist),
-    .io_dec_tlu_br0_r_pkt_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error),
-    .io_dec_tlu_br0_r_pkt_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error),
-    .io_dec_tlu_br0_r_pkt_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_way),
-    .io_dec_tlu_br0_r_pkt_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle),
+    .io_dec_tlu_br0_r_pkt_bits_hist(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist),
+    .io_dec_tlu_br0_r_pkt_bits_br_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error),
+    .io_dec_tlu_br0_r_pkt_bits_br_start_error(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error),
+    .io_dec_tlu_br0_r_pkt_bits_way(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way),
+    .io_dec_tlu_br0_r_pkt_bits_middle(bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle),
     .io_exu_i0_br_fghr_r(bp_ctl_ch_io_exu_i0_br_fghr_r),
     .io_exu_i0_br_index_r(bp_ctl_ch_io_exu_i0_br_index_r),
     .io_dec_tlu_flush_lower_wb(bp_ctl_ch_io_dec_tlu_flush_lower_wb),
@@ -44891,13 +44891,13 @@ module el2_ifu(
     .io_ifu_pmu_instr_aligned(aln_ctl_ch_io_ifu_pmu_instr_aligned),
     .io_ifu_i0_cinst(aln_ctl_ch_io_ifu_i0_cinst),
     .io_i0_brp_valid(aln_ctl_ch_io_i0_brp_valid),
-    .io_i0_brp_toffset(aln_ctl_ch_io_i0_brp_toffset),
-    .io_i0_brp_hist(aln_ctl_ch_io_i0_brp_hist),
-    .io_i0_brp_br_error(aln_ctl_ch_io_i0_brp_br_error),
-    .io_i0_brp_br_start_error(aln_ctl_ch_io_i0_brp_br_start_error),
-    .io_i0_brp_prett(aln_ctl_ch_io_i0_brp_prett),
-    .io_i0_brp_way(aln_ctl_ch_io_i0_brp_way),
-    .io_i0_brp_ret(aln_ctl_ch_io_i0_brp_ret)
+    .io_i0_brp_bits_toffset(aln_ctl_ch_io_i0_brp_bits_toffset),
+    .io_i0_brp_bits_hist(aln_ctl_ch_io_i0_brp_bits_hist),
+    .io_i0_brp_bits_br_error(aln_ctl_ch_io_i0_brp_bits_br_error),
+    .io_i0_brp_bits_br_start_error(aln_ctl_ch_io_i0_brp_bits_br_start_error),
+    .io_i0_brp_bits_prett(aln_ctl_ch_io_i0_brp_bits_prett),
+    .io_i0_brp_bits_way(aln_ctl_ch_io_i0_brp_bits_way),
+    .io_i0_brp_bits_ret(aln_ctl_ch_io_i0_brp_bits_ret)
   );
   el2_ifu_ifc_ctl ifc_ctl_ch ( // @[el2_ifu.scala 149:26]
     .clock(ifc_ctl_ch_clock),
@@ -44978,13 +44978,13 @@ module el2_ifu(
   assign io_ifu_i0_pc4 = aln_ctl_ch_io_ifu_i0_pc4; // @[el2_ifu.scala 328:17]
   assign io_ifu_miss_state_idle = mem_ctl_ch_io_ifu_miss_state_idle; // @[el2_ifu.scala 329:26]
   assign io_i0_brp_valid = aln_ctl_ch_io_i0_brp_valid; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_toffset = aln_ctl_ch_io_i0_brp_toffset; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_hist = aln_ctl_ch_io_i0_brp_hist; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_br_error = aln_ctl_ch_io_i0_brp_br_error; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_br_start_error = aln_ctl_ch_io_i0_brp_br_start_error; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_prett = aln_ctl_ch_io_i0_brp_prett; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_way = aln_ctl_ch_io_i0_brp_way; // @[el2_ifu.scala 331:13]
-  assign io_i0_brp_ret = aln_ctl_ch_io_i0_brp_ret; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_toffset = aln_ctl_ch_io_i0_brp_bits_toffset; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_hist = aln_ctl_ch_io_i0_brp_bits_hist; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_br_error = aln_ctl_ch_io_i0_brp_bits_br_error; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_br_start_error = aln_ctl_ch_io_i0_brp_bits_br_start_error; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_prett = aln_ctl_ch_io_i0_brp_bits_prett; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_way = aln_ctl_ch_io_i0_brp_bits_way; // @[el2_ifu.scala 331:13]
+  assign io_i0_brp_bits_ret = aln_ctl_ch_io_i0_brp_bits_ret; // @[el2_ifu.scala 331:13]
   assign io_ifu_i0_bp_index = aln_ctl_ch_io_ifu_i0_bp_index; // @[el2_ifu.scala 332:22]
   assign io_ifu_i0_bp_fghr = aln_ctl_ch_io_ifu_i0_bp_fghr; // @[el2_ifu.scala 333:21]
   assign io_ifu_i0_bp_btag = aln_ctl_ch_io_ifu_i0_bp_btag; // @[el2_ifu.scala 334:21]
@@ -45045,11 +45045,11 @@ module el2_ifu(
   assign bp_ctl_ch_io_ifc_fetch_addr_f = ifc_ctl_ch_io_ifc_fetch_addr_f; // @[el2_ifu.scala 196:33]
   assign bp_ctl_ch_io_ifc_fetch_req_f = ifc_ctl_ch_io_ifc_fetch_req_f; // @[el2_ifu.scala 197:32]
   assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_valid = io_dec_tlu_br0_r_pkt_valid; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_hist = io_dec_tlu_br0_r_pkt_hist; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_error = io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_br_start_error = io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_way = io_dec_tlu_br0_r_pkt_way; // @[el2_ifu.scala 198:34]
-  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_middle = io_dec_tlu_br0_r_pkt_middle; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_hist = io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_error = io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_br_start_error = io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_way = io_dec_tlu_br0_r_pkt_bits_way; // @[el2_ifu.scala 198:34]
+  assign bp_ctl_ch_io_dec_tlu_br0_r_pkt_bits_middle = io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_ifu.scala 198:34]
   assign bp_ctl_ch_io_exu_i0_br_fghr_r = io_exu_i0_br_fghr_r; // @[el2_ifu.scala 199:33]
   assign bp_ctl_ch_io_exu_i0_br_index_r = io_exu_i0_br_index_r; // @[el2_ifu.scala 200:34]
   assign bp_ctl_ch_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[el2_ifu.scala 201:39]
@@ -45118,13 +45118,13 @@ module el2_dec_ib_ctl(
   input  [1:0]  io_dbg_cmd_type,
   input  [31:0] io_dbg_cmd_addr,
   input         io_i0_brp_valid,
-  input  [11:0] io_i0_brp_toffset,
-  input  [1:0]  io_i0_brp_hist,
-  input         io_i0_brp_br_error,
-  input         io_i0_brp_br_start_error,
-  input  [30:0] io_i0_brp_prett,
-  input         io_i0_brp_way,
-  input         io_i0_brp_ret,
+  input  [11:0] io_i0_brp_bits_toffset,
+  input  [1:0]  io_i0_brp_bits_hist,
+  input         io_i0_brp_bits_br_error,
+  input         io_i0_brp_bits_br_start_error,
+  input  [30:0] io_i0_brp_bits_prett,
+  input         io_i0_brp_bits_way,
+  input         io_i0_brp_bits_ret,
   input  [7:0]  io_ifu_i0_bp_index,
   input  [7:0]  io_ifu_i0_bp_fghr,
   input  [4:0]  io_ifu_i0_bp_btag,
@@ -45142,13 +45142,13 @@ module el2_dec_ib_ctl(
   output [30:0] io_dec_i0_pc_d,
   output        io_dec_i0_pc4_d,
   output        io_dec_i0_brp_valid,
-  output [11:0] io_dec_i0_brp_toffset,
-  output [1:0]  io_dec_i0_brp_hist,
-  output        io_dec_i0_brp_br_error,
-  output        io_dec_i0_brp_br_start_error,
-  output [30:0] io_dec_i0_brp_prett,
-  output        io_dec_i0_brp_way,
-  output        io_dec_i0_brp_ret,
+  output [11:0] io_dec_i0_brp_bits_toffset,
+  output [1:0]  io_dec_i0_brp_bits_hist,
+  output        io_dec_i0_brp_bits_br_error,
+  output        io_dec_i0_brp_bits_br_start_error,
+  output [30:0] io_dec_i0_brp_bits_prett,
+  output        io_dec_i0_brp_bits_way,
+  output        io_dec_i0_brp_bits_ret,
   output [7:0]  io_dec_i0_bp_index,
   output [7:0]  io_dec_i0_bp_fghr,
   output [4:0]  io_dec_i0_bp_btag,
@@ -45192,13 +45192,13 @@ module el2_dec_ib_ctl(
   assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31]
   assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31]
   assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 14:31]
-  assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec_ib_ctl.scala 14:31]
+  assign io_dec_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec_ib_ctl.scala 14:31]
   assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31]
   assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31]
   assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31]
@@ -45948,13 +45948,13 @@ module el2_dec_decode_ctl(
   input  [1:0]  io_dec_i0_icaf_type_d,
   input         io_dec_i0_dbecc_d,
   input         io_dec_i0_brp_valid,
-  input  [11:0] io_dec_i0_brp_toffset,
-  input  [1:0]  io_dec_i0_brp_hist,
-  input         io_dec_i0_brp_br_error,
-  input         io_dec_i0_brp_br_start_error,
-  input  [30:0] io_dec_i0_brp_prett,
-  input         io_dec_i0_brp_way,
-  input         io_dec_i0_brp_ret,
+  input  [11:0] io_dec_i0_brp_bits_toffset,
+  input  [1:0]  io_dec_i0_brp_bits_hist,
+  input         io_dec_i0_brp_bits_br_error,
+  input         io_dec_i0_brp_bits_br_start_error,
+  input  [30:0] io_dec_i0_brp_bits_prett,
+  input         io_dec_i0_brp_bits_way,
+  input         io_dec_i0_brp_bits_ret,
   input  [7:0]  io_dec_i0_bp_index,
   input  [7:0]  io_dec_i0_bp_fghr,
   input  [4:0]  io_dec_i0_bp_btag,
@@ -46378,21 +46378,21 @@ module el2_dec_decode_ctl(
   wire  _T_22 = _T_21 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 237:103]
   wire  _T_23 = ~_T_22; // @[el2_dec_decode_ctl.scala 237:56]
   wire  i0_notbr_error = i0_brp_valid & _T_23; // @[el2_dec_decode_ctl.scala 237:54]
-  wire  _T_31 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:57]
-  wire  _T_25 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 240:47]
+  wire  _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:62]
+  wire  _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[el2_dec_decode_ctl.scala 240:47]
   wire  _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 415:41]
   wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58]
   wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 415:26]
-  wire  _T_26 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:96]
-  wire  _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:71]
-  wire  _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:116]
-  wire  i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:114]
-  wire  _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:74]
-  wire  _T_29 = i0_brp_valid & io_dec_i0_brp_ret; // @[el2_dec_decode_ctl.scala 241:47]
-  wire  i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:67]
-  wire  i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:96]
-  wire  _T_39 = i0_br_error | io_dec_i0_brp_br_start_error; // @[el2_dec_decode_ctl.scala 247:47]
-  wire  i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:79]
+  wire  _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:106]
+  wire  _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:76]
+  wire  _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:126]
+  wire  i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:124]
+  wire  _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:79]
+  wire  _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[el2_dec_decode_ctl.scala 241:47]
+  wire  i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:72]
+  wire  i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:101]
+  wire  _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[el2_dec_decode_ctl.scala 247:47]
+  wire  i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:84]
   wire  i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 256:36]
   wire  _T_41 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 260:25]
   wire  i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
@@ -46437,7 +46437,7 @@ module el2_dec_decode_ctl(
   wire  _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32]
   wire  i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 644:46]
   wire  _T_33 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 243:72]
-  wire  _T_36 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:89]
+  wire  _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:94]
   wire  i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
   wire  i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 260:50]
   wire  i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
@@ -46514,7 +46514,7 @@ module el2_dec_decode_ctl(
   wire  _T_45 = _T_44 | i0_pja; // @[el2_dec_decode_ctl.scala 274:49]
   wire  i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 419:32]
   wire  i0_predict_br = _T_45 | i0_pret; // @[el2_dec_decode_ctl.scala 274:58]
-  wire  _T_47 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:50]
+  wire  _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:55]
   wire  _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26]
   wire  i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20]
   wire  cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63]
@@ -47301,15 +47301,15 @@ module el2_dec_decode_ctl(
   assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 764:25]
   assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 236:38]
   assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 234:43]
-  assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_hist; // @[el2_dec_decode_ctl.scala 235:43]
+  assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[el2_dec_decode_ctl.scala 235:43]
   assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 248:49]
   assign io_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[el2_dec_decode_ctl.scala 243:56]
   assign io_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[el2_dec_decode_ctl.scala 244:56]
-  assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_prett; // @[el2_dec_decode_ctl.scala 233:43]
+  assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[el2_dec_decode_ctl.scala 233:43]
   assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 230:43]
   assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 232:43]
   assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 231:43]
-  assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_way; // @[el2_dec_decode_ctl.scala 250:56]
+  assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[el2_dec_decode_ctl.scala 250:56]
   assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 249:32]
   assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 245:32]
   assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 246:32]
@@ -54340,11 +54340,11 @@ module el2_dec_tlu_ctl(
   output [31:0] io_dec_csr_rddata_d,
   output        io_dec_csr_legal_d,
   output        io_dec_tlu_br0_r_pkt_valid,
-  output [1:0]  io_dec_tlu_br0_r_pkt_hist,
-  output        io_dec_tlu_br0_r_pkt_br_error,
-  output        io_dec_tlu_br0_r_pkt_br_start_error,
-  output        io_dec_tlu_br0_r_pkt_way,
-  output        io_dec_tlu_br0_r_pkt_middle,
+  output [1:0]  io_dec_tlu_br0_r_pkt_bits_hist,
+  output        io_dec_tlu_br0_r_pkt_bits_br_error,
+  output        io_dec_tlu_br0_r_pkt_bits_br_start_error,
+  output        io_dec_tlu_br0_r_pkt_bits_way,
+  output        io_dec_tlu_br0_r_pkt_bits_middle,
   output        io_dec_tlu_i0_kill_writeb_wb,
   output        io_dec_tlu_flush_lower_wb,
   output        io_dec_tlu_i0_commit_cmt,
@@ -55979,11 +55979,11 @@ module el2_dec_tlu_ctl(
   assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40]
   assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22]
   assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49]
-  assign io_dec_tlu_br0_r_pkt_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:49]
-  assign io_dec_tlu_br0_r_pkt_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49]
-  assign io_dec_tlu_br0_r_pkt_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:41]
-  assign io_dec_tlu_br0_r_pkt_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:49]
-  assign io_dec_tlu_br0_r_pkt_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:49]
+  assign io_dec_tlu_br0_r_pkt_bits_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:57]
+  assign io_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49]
+  assign io_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:49]
+  assign io_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:57]
+  assign io_dec_tlu_br0_r_pkt_bits_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:57]
   assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33]
   assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33]
   assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28]
@@ -57857,13 +57857,13 @@ module el2_dec(
   input         io_ifu_i0_dbecc,
   input         io_lsu_idle_any,
   input         io_i0_brp_valid,
-  input  [11:0] io_i0_brp_toffset,
-  input  [1:0]  io_i0_brp_hist,
-  input         io_i0_brp_br_error,
-  input         io_i0_brp_br_start_error,
-  input  [30:0] io_i0_brp_prett,
-  input         io_i0_brp_way,
-  input         io_i0_brp_ret,
+  input  [11:0] io_i0_brp_bits_toffset,
+  input  [1:0]  io_i0_brp_bits_hist,
+  input         io_i0_brp_bits_br_error,
+  input         io_i0_brp_bits_br_start_error,
+  input  [30:0] io_i0_brp_bits_prett,
+  input         io_i0_brp_bits_way,
+  input         io_i0_brp_bits_ret,
   input  [7:0]  io_ifu_i0_bp_index,
   input  [7:0]  io_ifu_i0_bp_fghr,
   input  [4:0]  io_ifu_i0_bp_btag,
@@ -58010,11 +58010,11 @@ module el2_dec(
   output        io_dec_tlu_fence_i_r,
   output [30:0] io_pred_correct_npc_x,
   output        io_dec_tlu_br0_r_pkt_valid,
-  output [1:0]  io_dec_tlu_br0_r_pkt_hist,
-  output        io_dec_tlu_br0_r_pkt_br_error,
-  output        io_dec_tlu_br0_r_pkt_br_start_error,
-  output        io_dec_tlu_br0_r_pkt_way,
-  output        io_dec_tlu_br0_r_pkt_middle,
+  output [1:0]  io_dec_tlu_br0_r_pkt_bits_hist,
+  output        io_dec_tlu_br0_r_pkt_bits_br_error,
+  output        io_dec_tlu_br0_r_pkt_bits_br_start_error,
+  output        io_dec_tlu_br0_r_pkt_bits_way,
+  output        io_dec_tlu_br0_r_pkt_bits_middle,
   output        io_dec_tlu_perfcnt0,
   output        io_dec_tlu_perfcnt1,
   output        io_dec_tlu_perfcnt2,
@@ -58064,13 +58064,13 @@ module el2_dec(
   wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 285:24]
   wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 285:24]
   wire  instbuff_io_i0_brp_valid; // @[el2_dec.scala 285:24]
-  wire [11:0] instbuff_io_i0_brp_toffset; // @[el2_dec.scala 285:24]
-  wire [1:0] instbuff_io_i0_brp_hist; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_i0_brp_br_error; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_i0_brp_br_start_error; // @[el2_dec.scala 285:24]
-  wire [30:0] instbuff_io_i0_brp_prett; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_i0_brp_way; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_i0_brp_ret; // @[el2_dec.scala 285:24]
+  wire [11:0] instbuff_io_i0_brp_bits_toffset; // @[el2_dec.scala 285:24]
+  wire [1:0] instbuff_io_i0_brp_bits_hist; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_i0_brp_bits_br_error; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24]
+  wire [30:0] instbuff_io_i0_brp_bits_prett; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_i0_brp_bits_way; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_i0_brp_bits_ret; // @[el2_dec.scala 285:24]
   wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 285:24]
   wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 285:24]
   wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 285:24]
@@ -58088,13 +58088,13 @@ module el2_dec(
   wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 285:24]
   wire  instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 285:24]
   wire  instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 285:24]
-  wire [11:0] instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 285:24]
-  wire [1:0] instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 285:24]
-  wire [30:0] instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 285:24]
-  wire  instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 285:24]
+  wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 285:24]
+  wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24]
+  wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 285:24]
+  wire  instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 285:24]
   wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 285:24]
   wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 285:24]
   wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 285:24]
@@ -58133,13 +58133,13 @@ module el2_dec(
   wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 286:22]
   wire  decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 286:22]
   wire  decode_io_dec_i0_brp_valid; // @[el2_dec.scala 286:22]
-  wire [11:0] decode_io_dec_i0_brp_toffset; // @[el2_dec.scala 286:22]
-  wire [1:0] decode_io_dec_i0_brp_hist; // @[el2_dec.scala 286:22]
-  wire  decode_io_dec_i0_brp_br_error; // @[el2_dec.scala 286:22]
-  wire  decode_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 286:22]
-  wire [30:0] decode_io_dec_i0_brp_prett; // @[el2_dec.scala 286:22]
-  wire  decode_io_dec_i0_brp_way; // @[el2_dec.scala 286:22]
-  wire  decode_io_dec_i0_brp_ret; // @[el2_dec.scala 286:22]
+  wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 286:22]
+  wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 286:22]
+  wire  decode_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 286:22]
+  wire  decode_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 286:22]
+  wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 286:22]
+  wire  decode_io_dec_i0_brp_bits_way; // @[el2_dec.scala 286:22]
+  wire  decode_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 286:22]
   wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 286:22]
   wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 286:22]
   wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 286:22]
@@ -58445,11 +58445,11 @@ module el2_dec(
   wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_csr_legal_d; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 288:19]
-  wire [1:0] tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 288:19]
-  wire  tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 288:19]
-  wire  tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 288:19]
-  wire  tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 288:19]
-  wire  tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 288:19]
+  wire [1:0] tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 288:19]
+  wire  tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 288:19]
+  wire  tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 288:19]
+  wire  tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 288:19]
+  wire  tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 288:19]
   wire  tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 288:19]
@@ -58514,13 +58514,13 @@ module el2_dec(
     .io_dbg_cmd_type(instbuff_io_dbg_cmd_type),
     .io_dbg_cmd_addr(instbuff_io_dbg_cmd_addr),
     .io_i0_brp_valid(instbuff_io_i0_brp_valid),
-    .io_i0_brp_toffset(instbuff_io_i0_brp_toffset),
-    .io_i0_brp_hist(instbuff_io_i0_brp_hist),
-    .io_i0_brp_br_error(instbuff_io_i0_brp_br_error),
-    .io_i0_brp_br_start_error(instbuff_io_i0_brp_br_start_error),
-    .io_i0_brp_prett(instbuff_io_i0_brp_prett),
-    .io_i0_brp_way(instbuff_io_i0_brp_way),
-    .io_i0_brp_ret(instbuff_io_i0_brp_ret),
+    .io_i0_brp_bits_toffset(instbuff_io_i0_brp_bits_toffset),
+    .io_i0_brp_bits_hist(instbuff_io_i0_brp_bits_hist),
+    .io_i0_brp_bits_br_error(instbuff_io_i0_brp_bits_br_error),
+    .io_i0_brp_bits_br_start_error(instbuff_io_i0_brp_bits_br_start_error),
+    .io_i0_brp_bits_prett(instbuff_io_i0_brp_bits_prett),
+    .io_i0_brp_bits_way(instbuff_io_i0_brp_bits_way),
+    .io_i0_brp_bits_ret(instbuff_io_i0_brp_bits_ret),
     .io_ifu_i0_bp_index(instbuff_io_ifu_i0_bp_index),
     .io_ifu_i0_bp_fghr(instbuff_io_ifu_i0_bp_fghr),
     .io_ifu_i0_bp_btag(instbuff_io_ifu_i0_bp_btag),
@@ -58538,13 +58538,13 @@ module el2_dec(
     .io_dec_i0_pc_d(instbuff_io_dec_i0_pc_d),
     .io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d),
     .io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid),
-    .io_dec_i0_brp_toffset(instbuff_io_dec_i0_brp_toffset),
-    .io_dec_i0_brp_hist(instbuff_io_dec_i0_brp_hist),
-    .io_dec_i0_brp_br_error(instbuff_io_dec_i0_brp_br_error),
-    .io_dec_i0_brp_br_start_error(instbuff_io_dec_i0_brp_br_start_error),
-    .io_dec_i0_brp_prett(instbuff_io_dec_i0_brp_prett),
-    .io_dec_i0_brp_way(instbuff_io_dec_i0_brp_way),
-    .io_dec_i0_brp_ret(instbuff_io_dec_i0_brp_ret),
+    .io_dec_i0_brp_bits_toffset(instbuff_io_dec_i0_brp_bits_toffset),
+    .io_dec_i0_brp_bits_hist(instbuff_io_dec_i0_brp_bits_hist),
+    .io_dec_i0_brp_bits_br_error(instbuff_io_dec_i0_brp_bits_br_error),
+    .io_dec_i0_brp_bits_br_start_error(instbuff_io_dec_i0_brp_bits_br_start_error),
+    .io_dec_i0_brp_bits_prett(instbuff_io_dec_i0_brp_bits_prett),
+    .io_dec_i0_brp_bits_way(instbuff_io_dec_i0_brp_bits_way),
+    .io_dec_i0_brp_bits_ret(instbuff_io_dec_i0_brp_bits_ret),
     .io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index),
     .io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr),
     .io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag),
@@ -58585,13 +58585,13 @@ module el2_dec(
     .io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d),
     .io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d),
     .io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid),
-    .io_dec_i0_brp_toffset(decode_io_dec_i0_brp_toffset),
-    .io_dec_i0_brp_hist(decode_io_dec_i0_brp_hist),
-    .io_dec_i0_brp_br_error(decode_io_dec_i0_brp_br_error),
-    .io_dec_i0_brp_br_start_error(decode_io_dec_i0_brp_br_start_error),
-    .io_dec_i0_brp_prett(decode_io_dec_i0_brp_prett),
-    .io_dec_i0_brp_way(decode_io_dec_i0_brp_way),
-    .io_dec_i0_brp_ret(decode_io_dec_i0_brp_ret),
+    .io_dec_i0_brp_bits_toffset(decode_io_dec_i0_brp_bits_toffset),
+    .io_dec_i0_brp_bits_hist(decode_io_dec_i0_brp_bits_hist),
+    .io_dec_i0_brp_bits_br_error(decode_io_dec_i0_brp_bits_br_error),
+    .io_dec_i0_brp_bits_br_start_error(decode_io_dec_i0_brp_bits_br_start_error),
+    .io_dec_i0_brp_bits_prett(decode_io_dec_i0_brp_bits_prett),
+    .io_dec_i0_brp_bits_way(decode_io_dec_i0_brp_bits_way),
+    .io_dec_i0_brp_bits_ret(decode_io_dec_i0_brp_bits_ret),
     .io_dec_i0_bp_index(decode_io_dec_i0_bp_index),
     .io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr),
     .io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag),
@@ -58901,11 +58901,11 @@ module el2_dec(
     .io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d),
     .io_dec_csr_legal_d(tlu_io_dec_csr_legal_d),
     .io_dec_tlu_br0_r_pkt_valid(tlu_io_dec_tlu_br0_r_pkt_valid),
-    .io_dec_tlu_br0_r_pkt_hist(tlu_io_dec_tlu_br0_r_pkt_hist),
-    .io_dec_tlu_br0_r_pkt_br_error(tlu_io_dec_tlu_br0_r_pkt_br_error),
-    .io_dec_tlu_br0_r_pkt_br_start_error(tlu_io_dec_tlu_br0_r_pkt_br_start_error),
-    .io_dec_tlu_br0_r_pkt_way(tlu_io_dec_tlu_br0_r_pkt_way),
-    .io_dec_tlu_br0_r_pkt_middle(tlu_io_dec_tlu_br0_r_pkt_middle),
+    .io_dec_tlu_br0_r_pkt_bits_hist(tlu_io_dec_tlu_br0_r_pkt_bits_hist),
+    .io_dec_tlu_br0_r_pkt_bits_br_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_error),
+    .io_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error),
+    .io_dec_tlu_br0_r_pkt_bits_way(tlu_io_dec_tlu_br0_r_pkt_bits_way),
+    .io_dec_tlu_br0_r_pkt_bits_middle(tlu_io_dec_tlu_br0_r_pkt_bits_middle),
     .io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb),
     .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb),
     .io_dec_tlu_i0_commit_cmt(tlu_io_dec_tlu_i0_commit_cmt),
@@ -59073,11 +59073,11 @@ module el2_dec(
   assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 562:34]
   assign io_pred_correct_npc_x = decode_io_pred_correct_npc_x; // @[el2_dec.scala 411:40]
   assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_hist = tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_br_error = tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_br_start_error = tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_way = tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 557:42]
-  assign io_dec_tlu_br0_r_pkt_middle = tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_hist = tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_way = tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 557:42]
+  assign io_dec_tlu_br0_r_pkt_bits_middle = tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 557:42]
   assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 565:29]
   assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 566:29]
   assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 567:29]
@@ -59124,13 +59124,13 @@ module el2_dec(
   assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 299:45]
   assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 300:45]
   assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_hist = io_i0_brp_hist; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_prett = io_i0_brp_prett; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_way = io_i0_brp_way; // @[el2_dec.scala 301:55]
-  assign instbuff_io_i0_brp_ret = io_i0_brp_ret; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec.scala 301:55]
+  assign instbuff_io_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec.scala 301:55]
   assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec.scala 302:35]
   assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 303:35]
   assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 304:35]
@@ -59169,13 +59169,13 @@ module el2_dec(
   assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 352:48]
   assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:48]
   assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_toffset = instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_hist = instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_br_error = instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_br_start_error = instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_prett = instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_way = instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 354:48]
-  assign decode_io_dec_i0_brp_ret = instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 354:48]
+  assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 354:48]
   assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 355:48]
   assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 356:48]
   assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 357:48]
@@ -80409,13 +80409,13 @@ module el2_swerv(
   wire  ifu_io_ifu_i0_pc4; // @[el2_swerv.scala 321:19]
   wire  ifu_io_ifu_miss_state_idle; // @[el2_swerv.scala 321:19]
   wire  ifu_io_i0_brp_valid; // @[el2_swerv.scala 321:19]
-  wire [11:0] ifu_io_i0_brp_toffset; // @[el2_swerv.scala 321:19]
-  wire [1:0] ifu_io_i0_brp_hist; // @[el2_swerv.scala 321:19]
-  wire  ifu_io_i0_brp_br_error; // @[el2_swerv.scala 321:19]
-  wire  ifu_io_i0_brp_br_start_error; // @[el2_swerv.scala 321:19]
-  wire [30:0] ifu_io_i0_brp_prett; // @[el2_swerv.scala 321:19]
-  wire  ifu_io_i0_brp_way; // @[el2_swerv.scala 321:19]
-  wire  ifu_io_i0_brp_ret; // @[el2_swerv.scala 321:19]
+  wire [11:0] ifu_io_i0_brp_bits_toffset; // @[el2_swerv.scala 321:19]
+  wire [1:0] ifu_io_i0_brp_bits_hist; // @[el2_swerv.scala 321:19]
+  wire  ifu_io_i0_brp_bits_br_error; // @[el2_swerv.scala 321:19]
+  wire  ifu_io_i0_brp_bits_br_start_error; // @[el2_swerv.scala 321:19]
+  wire [30:0] ifu_io_i0_brp_bits_prett; // @[el2_swerv.scala 321:19]
+  wire  ifu_io_i0_brp_bits_way; // @[el2_swerv.scala 321:19]
+  wire  ifu_io_i0_brp_bits_ret; // @[el2_swerv.scala 321:19]
   wire [7:0] ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 321:19]
   wire [7:0] ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 321:19]
   wire [4:0] ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 321:19]
@@ -80434,11 +80434,11 @@ module el2_swerv(
   wire [7:0] ifu_io_exu_mp_index; // @[el2_swerv.scala 321:19]
   wire [4:0] ifu_io_exu_mp_btag; // @[el2_swerv.scala 321:19]
   wire  ifu_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 321:19]
-  wire [1:0] ifu_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 321:19]
-  wire  ifu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 321:19]
-  wire  ifu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 321:19]
-  wire  ifu_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 321:19]
-  wire  ifu_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 321:19]
+  wire [1:0] ifu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 321:19]
+  wire  ifu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 321:19]
+  wire  ifu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_swerv.scala 321:19]
+  wire  ifu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_swerv.scala 321:19]
+  wire  ifu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_swerv.scala 321:19]
   wire [7:0] ifu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 321:19]
   wire [7:0] ifu_io_exu_i0_br_index_r; // @[el2_swerv.scala 321:19]
   wire  ifu_io_dec_tlu_flush_lower_wb; // @[el2_swerv.scala 321:19]
@@ -80519,13 +80519,13 @@ module el2_swerv(
   wire  dec_io_ifu_i0_dbecc; // @[el2_swerv.scala 322:19]
   wire  dec_io_lsu_idle_any; // @[el2_swerv.scala 322:19]
   wire  dec_io_i0_brp_valid; // @[el2_swerv.scala 322:19]
-  wire [11:0] dec_io_i0_brp_toffset; // @[el2_swerv.scala 322:19]
-  wire [1:0] dec_io_i0_brp_hist; // @[el2_swerv.scala 322:19]
-  wire  dec_io_i0_brp_br_error; // @[el2_swerv.scala 322:19]
-  wire  dec_io_i0_brp_br_start_error; // @[el2_swerv.scala 322:19]
-  wire [30:0] dec_io_i0_brp_prett; // @[el2_swerv.scala 322:19]
-  wire  dec_io_i0_brp_way; // @[el2_swerv.scala 322:19]
-  wire  dec_io_i0_brp_ret; // @[el2_swerv.scala 322:19]
+  wire [11:0] dec_io_i0_brp_bits_toffset; // @[el2_swerv.scala 322:19]
+  wire [1:0] dec_io_i0_brp_bits_hist; // @[el2_swerv.scala 322:19]
+  wire  dec_io_i0_brp_bits_br_error; // @[el2_swerv.scala 322:19]
+  wire  dec_io_i0_brp_bits_br_start_error; // @[el2_swerv.scala 322:19]
+  wire [30:0] dec_io_i0_brp_bits_prett; // @[el2_swerv.scala 322:19]
+  wire  dec_io_i0_brp_bits_way; // @[el2_swerv.scala 322:19]
+  wire  dec_io_i0_brp_bits_ret; // @[el2_swerv.scala 322:19]
   wire [7:0] dec_io_ifu_i0_bp_index; // @[el2_swerv.scala 322:19]
   wire [7:0] dec_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 322:19]
   wire [4:0] dec_io_ifu_i0_bp_btag; // @[el2_swerv.scala 322:19]
@@ -80672,11 +80672,11 @@ module el2_swerv(
   wire  dec_io_dec_tlu_fence_i_r; // @[el2_swerv.scala 322:19]
   wire [30:0] dec_io_pred_correct_npc_x; // @[el2_swerv.scala 322:19]
   wire  dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 322:19]
-  wire [1:0] dec_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 322:19]
-  wire  dec_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 322:19]
-  wire  dec_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 322:19]
-  wire  dec_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 322:19]
-  wire  dec_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 322:19]
+  wire [1:0] dec_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 322:19]
+  wire  dec_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 322:19]
+  wire  dec_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_swerv.scala 322:19]
+  wire  dec_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_swerv.scala 322:19]
+  wire  dec_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_swerv.scala 322:19]
   wire  dec_io_dec_tlu_perfcnt0; // @[el2_swerv.scala 322:19]
   wire  dec_io_dec_tlu_perfcnt1; // @[el2_swerv.scala 322:19]
   wire  dec_io_dec_tlu_perfcnt2; // @[el2_swerv.scala 322:19]
@@ -81188,13 +81188,13 @@ module el2_swerv(
     .io_ifu_i0_pc4(ifu_io_ifu_i0_pc4),
     .io_ifu_miss_state_idle(ifu_io_ifu_miss_state_idle),
     .io_i0_brp_valid(ifu_io_i0_brp_valid),
-    .io_i0_brp_toffset(ifu_io_i0_brp_toffset),
-    .io_i0_brp_hist(ifu_io_i0_brp_hist),
-    .io_i0_brp_br_error(ifu_io_i0_brp_br_error),
-    .io_i0_brp_br_start_error(ifu_io_i0_brp_br_start_error),
-    .io_i0_brp_prett(ifu_io_i0_brp_prett),
-    .io_i0_brp_way(ifu_io_i0_brp_way),
-    .io_i0_brp_ret(ifu_io_i0_brp_ret),
+    .io_i0_brp_bits_toffset(ifu_io_i0_brp_bits_toffset),
+    .io_i0_brp_bits_hist(ifu_io_i0_brp_bits_hist),
+    .io_i0_brp_bits_br_error(ifu_io_i0_brp_bits_br_error),
+    .io_i0_brp_bits_br_start_error(ifu_io_i0_brp_bits_br_start_error),
+    .io_i0_brp_bits_prett(ifu_io_i0_brp_bits_prett),
+    .io_i0_brp_bits_way(ifu_io_i0_brp_bits_way),
+    .io_i0_brp_bits_ret(ifu_io_i0_brp_bits_ret),
     .io_ifu_i0_bp_index(ifu_io_ifu_i0_bp_index),
     .io_ifu_i0_bp_fghr(ifu_io_ifu_i0_bp_fghr),
     .io_ifu_i0_bp_btag(ifu_io_ifu_i0_bp_btag),
@@ -81213,11 +81213,11 @@ module el2_swerv(
     .io_exu_mp_index(ifu_io_exu_mp_index),
     .io_exu_mp_btag(ifu_io_exu_mp_btag),
     .io_dec_tlu_br0_r_pkt_valid(ifu_io_dec_tlu_br0_r_pkt_valid),
-    .io_dec_tlu_br0_r_pkt_hist(ifu_io_dec_tlu_br0_r_pkt_hist),
-    .io_dec_tlu_br0_r_pkt_br_error(ifu_io_dec_tlu_br0_r_pkt_br_error),
-    .io_dec_tlu_br0_r_pkt_br_start_error(ifu_io_dec_tlu_br0_r_pkt_br_start_error),
-    .io_dec_tlu_br0_r_pkt_way(ifu_io_dec_tlu_br0_r_pkt_way),
-    .io_dec_tlu_br0_r_pkt_middle(ifu_io_dec_tlu_br0_r_pkt_middle),
+    .io_dec_tlu_br0_r_pkt_bits_hist(ifu_io_dec_tlu_br0_r_pkt_bits_hist),
+    .io_dec_tlu_br0_r_pkt_bits_br_error(ifu_io_dec_tlu_br0_r_pkt_bits_br_error),
+    .io_dec_tlu_br0_r_pkt_bits_br_start_error(ifu_io_dec_tlu_br0_r_pkt_bits_br_start_error),
+    .io_dec_tlu_br0_r_pkt_bits_way(ifu_io_dec_tlu_br0_r_pkt_bits_way),
+    .io_dec_tlu_br0_r_pkt_bits_middle(ifu_io_dec_tlu_br0_r_pkt_bits_middle),
     .io_exu_i0_br_fghr_r(ifu_io_exu_i0_br_fghr_r),
     .io_exu_i0_br_index_r(ifu_io_exu_i0_br_index_r),
     .io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb),
@@ -81300,13 +81300,13 @@ module el2_swerv(
     .io_ifu_i0_dbecc(dec_io_ifu_i0_dbecc),
     .io_lsu_idle_any(dec_io_lsu_idle_any),
     .io_i0_brp_valid(dec_io_i0_brp_valid),
-    .io_i0_brp_toffset(dec_io_i0_brp_toffset),
-    .io_i0_brp_hist(dec_io_i0_brp_hist),
-    .io_i0_brp_br_error(dec_io_i0_brp_br_error),
-    .io_i0_brp_br_start_error(dec_io_i0_brp_br_start_error),
-    .io_i0_brp_prett(dec_io_i0_brp_prett),
-    .io_i0_brp_way(dec_io_i0_brp_way),
-    .io_i0_brp_ret(dec_io_i0_brp_ret),
+    .io_i0_brp_bits_toffset(dec_io_i0_brp_bits_toffset),
+    .io_i0_brp_bits_hist(dec_io_i0_brp_bits_hist),
+    .io_i0_brp_bits_br_error(dec_io_i0_brp_bits_br_error),
+    .io_i0_brp_bits_br_start_error(dec_io_i0_brp_bits_br_start_error),
+    .io_i0_brp_bits_prett(dec_io_i0_brp_bits_prett),
+    .io_i0_brp_bits_way(dec_io_i0_brp_bits_way),
+    .io_i0_brp_bits_ret(dec_io_i0_brp_bits_ret),
     .io_ifu_i0_bp_index(dec_io_ifu_i0_bp_index),
     .io_ifu_i0_bp_fghr(dec_io_ifu_i0_bp_fghr),
     .io_ifu_i0_bp_btag(dec_io_ifu_i0_bp_btag),
@@ -81453,11 +81453,11 @@ module el2_swerv(
     .io_dec_tlu_fence_i_r(dec_io_dec_tlu_fence_i_r),
     .io_pred_correct_npc_x(dec_io_pred_correct_npc_x),
     .io_dec_tlu_br0_r_pkt_valid(dec_io_dec_tlu_br0_r_pkt_valid),
-    .io_dec_tlu_br0_r_pkt_hist(dec_io_dec_tlu_br0_r_pkt_hist),
-    .io_dec_tlu_br0_r_pkt_br_error(dec_io_dec_tlu_br0_r_pkt_br_error),
-    .io_dec_tlu_br0_r_pkt_br_start_error(dec_io_dec_tlu_br0_r_pkt_br_start_error),
-    .io_dec_tlu_br0_r_pkt_way(dec_io_dec_tlu_br0_r_pkt_way),
-    .io_dec_tlu_br0_r_pkt_middle(dec_io_dec_tlu_br0_r_pkt_middle),
+    .io_dec_tlu_br0_r_pkt_bits_hist(dec_io_dec_tlu_br0_r_pkt_bits_hist),
+    .io_dec_tlu_br0_r_pkt_bits_br_error(dec_io_dec_tlu_br0_r_pkt_bits_br_error),
+    .io_dec_tlu_br0_r_pkt_bits_br_start_error(dec_io_dec_tlu_br0_r_pkt_bits_br_start_error),
+    .io_dec_tlu_br0_r_pkt_bits_way(dec_io_dec_tlu_br0_r_pkt_bits_way),
+    .io_dec_tlu_br0_r_pkt_bits_middle(dec_io_dec_tlu_br0_r_pkt_bits_middle),
     .io_dec_tlu_perfcnt0(dec_io_dec_tlu_perfcnt0),
     .io_dec_tlu_perfcnt1(dec_io_dec_tlu_perfcnt1),
     .io_dec_tlu_perfcnt2(dec_io_dec_tlu_perfcnt2),
@@ -82036,11 +82036,11 @@ module el2_swerv(
   assign ifu_io_exu_mp_index = exu_io_exu_mp_index; // @[el2_swerv.scala 385:23]
   assign ifu_io_exu_mp_btag = exu_io_exu_mp_btag; // @[el2_swerv.scala 386:22]
   assign ifu_io_dec_tlu_br0_r_pkt_valid = dec_io_dec_tlu_br0_r_pkt_valid; // @[el2_swerv.scala 387:28]
-  assign ifu_io_dec_tlu_br0_r_pkt_hist = dec_io_dec_tlu_br0_r_pkt_hist; // @[el2_swerv.scala 387:28]
-  assign ifu_io_dec_tlu_br0_r_pkt_br_error = dec_io_dec_tlu_br0_r_pkt_br_error; // @[el2_swerv.scala 387:28]
-  assign ifu_io_dec_tlu_br0_r_pkt_br_start_error = dec_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_swerv.scala 387:28]
-  assign ifu_io_dec_tlu_br0_r_pkt_way = dec_io_dec_tlu_br0_r_pkt_way; // @[el2_swerv.scala 387:28]
-  assign ifu_io_dec_tlu_br0_r_pkt_middle = dec_io_dec_tlu_br0_r_pkt_middle; // @[el2_swerv.scala 387:28]
+  assign ifu_io_dec_tlu_br0_r_pkt_bits_hist = dec_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_swerv.scala 387:28]
+  assign ifu_io_dec_tlu_br0_r_pkt_bits_br_error = dec_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_swerv.scala 387:28]
+  assign ifu_io_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_swerv.scala 387:28]
+  assign ifu_io_dec_tlu_br0_r_pkt_bits_way = dec_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_swerv.scala 387:28]
+  assign ifu_io_dec_tlu_br0_r_pkt_bits_middle = dec_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_swerv.scala 387:28]
   assign ifu_io_exu_i0_br_fghr_r = exu_io_exu_i0_br_fghr_r; // @[el2_swerv.scala 388:27]
   assign ifu_io_exu_i0_br_index_r = exu_io_exu_i0_br_index_r; // @[el2_swerv.scala 389:28]
   assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_tlu_flush_lower_r; // @[el2_swerv.scala 390:33]
@@ -82107,13 +82107,13 @@ module el2_swerv(
   assign dec_io_ifu_i0_dbecc = ifu_io_ifu_i0_dbecc; // @[el2_swerv.scala 449:23]
   assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[el2_swerv.scala 450:23]
   assign dec_io_i0_brp_valid = ifu_io_i0_brp_valid; // @[el2_swerv.scala 451:17]
-  assign dec_io_i0_brp_toffset = ifu_io_i0_brp_toffset; // @[el2_swerv.scala 451:17]
-  assign dec_io_i0_brp_hist = ifu_io_i0_brp_hist; // @[el2_swerv.scala 451:17]
-  assign dec_io_i0_brp_br_error = ifu_io_i0_brp_br_error; // @[el2_swerv.scala 451:17]
-  assign dec_io_i0_brp_br_start_error = ifu_io_i0_brp_br_start_error; // @[el2_swerv.scala 451:17]
-  assign dec_io_i0_brp_prett = ifu_io_i0_brp_prett; // @[el2_swerv.scala 451:17]
-  assign dec_io_i0_brp_way = ifu_io_i0_brp_way; // @[el2_swerv.scala 451:17]
-  assign dec_io_i0_brp_ret = ifu_io_i0_brp_ret; // @[el2_swerv.scala 451:17]
+  assign dec_io_i0_brp_bits_toffset = ifu_io_i0_brp_bits_toffset; // @[el2_swerv.scala 451:17]
+  assign dec_io_i0_brp_bits_hist = ifu_io_i0_brp_bits_hist; // @[el2_swerv.scala 451:17]
+  assign dec_io_i0_brp_bits_br_error = ifu_io_i0_brp_bits_br_error; // @[el2_swerv.scala 451:17]
+  assign dec_io_i0_brp_bits_br_start_error = ifu_io_i0_brp_bits_br_start_error; // @[el2_swerv.scala 451:17]
+  assign dec_io_i0_brp_bits_prett = ifu_io_i0_brp_bits_prett; // @[el2_swerv.scala 451:17]
+  assign dec_io_i0_brp_bits_way = ifu_io_i0_brp_bits_way; // @[el2_swerv.scala 451:17]
+  assign dec_io_i0_brp_bits_ret = ifu_io_i0_brp_bits_ret; // @[el2_swerv.scala 451:17]
   assign dec_io_ifu_i0_bp_index = ifu_io_ifu_i0_bp_index; // @[el2_swerv.scala 452:26]
   assign dec_io_ifu_i0_bp_fghr = ifu_io_ifu_i0_bp_fghr; // @[el2_swerv.scala 453:25]
   assign dec_io_ifu_i0_bp_btag = ifu_io_ifu_i0_bp_btag; // @[el2_swerv.scala 454:25]
diff --git a/src/main/scala/dec/el2_dec.scala b/src/main/scala/dec/el2_dec.scala
index 5bafa63e..527b3ba3 100644
--- a/src/main/scala/dec/el2_dec.scala
+++ b/src/main/scala/dec/el2_dec.scala
@@ -96,7 +96,7 @@ class el2_dec_IO extends Bundle with el2_lib {
 
   val lsu_idle_any            = Input(Bool())     // lsu idle for halting
 
-  val i0_brp                  = Input(new el2_br_pkt_t)         // branch packet
+  val i0_brp                  = Flipped(Valid(new el2_br_pkt_t))         // branch packet
   val ifu_i0_bp_index         = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))      // BP index
   val ifu_i0_bp_fghr          = Input(UInt(BHT_GHR_SIZE.W))     // BP FGHR
   val ifu_i0_bp_btag          = Input(UInt(BTB_BTAG_SIZE.W))    // BP tag
@@ -223,7 +223,7 @@ class el2_dec_IO extends Bundle with el2_lib {
 
   val pred_correct_npc_x  = Output(UInt(31.W))       // npc if prediction is correct at e2 stage
 
-  val dec_tlu_br0_r_pkt  = Output(new el2_br_tlu_pkt_t)    // slot 0 branch predictor update packet
+  val dec_tlu_br0_r_pkt  = Valid(new el2_br_tlu_pkt_t)    // slot 0 branch predictor update packet
 
   val dec_tlu_perfcnt0   = Output(Bool())      // toggles when slot0 perf counter 0 has an event inc
   val dec_tlu_perfcnt1   = Output(Bool())      // toggles when slot0 perf counter 1 has an event inc
diff --git a/src/main/scala/dec/el2_dec_decode_ctl.scala b/src/main/scala/dec/el2_dec_decode_ctl.scala
index 4b9c91c4..d51481b7 100644
--- a/src/main/scala/dec/el2_dec_decode_ctl.scala
+++ b/src/main/scala/dec/el2_dec_decode_ctl.scala
@@ -35,7 +35,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
     val dec_i0_icaf_f1_d           =   Input(Bool())            // i0 instruction access fault at decode for f1 fetch group
     val dec_i0_icaf_type_d         =   Input(UInt(2.W))      // i0 instruction access fault type
     val dec_i0_dbecc_d             =   Input(Bool())            // icache/iccm double-bit error
-    val dec_i0_brp                 =   Input(new el2_br_pkt_t)          // branch packet
+    val dec_i0_brp                 =   Flipped(Valid(new el2_br_pkt_t))          // branch packet
     val dec_i0_bp_index            =   Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W))    // i0 branch index
     val dec_i0_bp_fghr             =   Input(UInt(BHT_GHR_SIZE.W))   // BP FGHR
     val dec_i0_bp_btag             =   Input(UInt(BTB_BTAG_SIZE.W))   // BP tag
@@ -230,24 +230,24 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
   io.dec_i0_predict_p_d.bits.pcall        :=  i0_pcall  // don't mark as pcall if branch error
   io.dec_i0_predict_p_d.bits.pja          :=  i0_pja
   io.dec_i0_predict_p_d.bits.pret         :=  i0_pret
-  io.dec_i0_predict_p_d.bits.prett        :=  io.dec_i0_brp.prett
+  io.dec_i0_predict_p_d.bits.prett        :=  io.dec_i0_brp.bits.prett
   io.dec_i0_predict_p_d.bits.pc4          :=  io.dec_i0_pc4_d
-  io.dec_i0_predict_p_d.bits.hist         :=  io.dec_i0_brp.hist
+  io.dec_i0_predict_p_d.bits.hist         :=  io.dec_i0_brp.bits.hist
   io.dec_i0_predict_p_d.valid        :=  i0_brp_valid & i0_legal_decode_d
   val i0_notbr_error                 =  i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
 
   // no toffset error for a pret
-  val i0_br_toffset_error     =  i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw
-  val i0_ret_error            =  i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw;
-  val i0_br_error             =  io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
+  val i0_br_toffset_error     =  i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw
+  val i0_ret_error            =  i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw;
+  val i0_br_error             =  io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
   io.dec_i0_predict_p_d.bits.br_error                  :=  i0_br_error & i0_legal_decode_d & !leak1_mode
-  io.dec_i0_predict_p_d.bits.br_start_error            :=  io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode
+  io.dec_i0_predict_p_d.bits.br_start_error            :=  io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode
   io.i0_predict_index_d        :=  io.dec_i0_bp_index
   io.i0_predict_btag_d         :=  io.dec_i0_bp_btag
-  val i0_br_error_all          = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode
+  val i0_br_error_all          = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode
   io.dec_i0_predict_p_d.bits.toffset            :=  i0_br_offset
   io.i0_predict_fghr_d         :=  io.dec_i0_bp_fghr
-  io.dec_i0_predict_p_d.bits.way                       :=  io.dec_i0_brp.way
+  io.dec_i0_predict_p_d.bits.way                       :=  io.dec_i0_brp.bits.way
   //   end
 
   // on br error turn anything into a nop
@@ -273,8 +273,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
   // branches that can be predicted
   val i0_predict_br  =  i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
 
-  val i0_predict_nt    = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
-  val i0_predict_t     =  (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
+  val i0_predict_nt    = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
+  val i0_predict_t     =  (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
   val i0_ap_pc2  = !io.dec_i0_pc4_d
   val i0_ap_pc4  =  io.dec_i0_pc4_d
   io.i0_ap.predict_nt    := i0_predict_nt
diff --git a/src/main/scala/dec/el2_dec_ib_ctl.scala b/src/main/scala/dec/el2_dec_ib_ctl.scala
index 89d73c8a..180e4493 100644
--- a/src/main/scala/dec/el2_dec_ib_ctl.scala
+++ b/src/main/scala/dec/el2_dec_ib_ctl.scala
@@ -63,7 +63,7 @@ class el2_dec_ib_ctl_IO extends Bundle with param{
   val dbg_cmd_write		    =Input(UInt(1.W))  // dbg cmd is write
   val dbg_cmd_type		    =Input(UInt(2.W))  // dbg type
   val dbg_cmd_addr		    =Input(UInt(32.W)) // expand to 31:0
-  val i0_brp				=Input(new el2_br_pkt_t) // i0 branch packet from aligner
+  val i0_brp				=Flipped(Valid(new el2_br_pkt_t)) // i0 branch packet from aligner
   val ifu_i0_bp_index       =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size)
   val ifu_i0_bp_fghr        =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR
   val ifu_i0_bp_btag        =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag
@@ -81,7 +81,7 @@ class el2_dec_ib_ctl_IO extends Bundle with param{
   val dec_i0_instr_d        =Output(UInt(32.W)) // i0 inst at decode
   val dec_i0_pc_d           =Output(UInt(31.W)) // i0 pc at decode
   val dec_i0_pc4_d          =Output(UInt(1.W))  // i0 is 4B inst else 2B
-  val dec_i0_brp            =Output(new el2_br_pkt_t) // i0 branch packet at decode
+  val dec_i0_brp            =Valid(new el2_br_pkt_t) // i0 branch packet at decode
   val dec_i0_bp_index       =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W))   // i0 branch index
   val dec_i0_bp_fghr        =Output(UInt(BHT_GHR_SIZE.W))   // BP FGHR
   val dec_i0_bp_btag        =Output(UInt(BTB_BTAG_SIZE.W))  // BP tag
diff --git a/src/main/scala/dec/el2_dec_tlu_ctl.scala b/src/main/scala/dec/el2_dec_tlu_ctl.scala
index ba15f177..57c94fd3 100644
--- a/src/main/scala/dec/el2_dec_tlu_ctl.scala
+++ b/src/main/scala/dec/el2_dec_tlu_ctl.scala
@@ -188,7 +188,7 @@ class el2_dec_tlu_ctl_IO extends Bundle with el2_lib {
   val  dec_tlu_meipt              = Output(UInt(4.W)) // to PIC
   val  dec_csr_rddata_d           = Output(UInt(32.W))      // csr read data at wb
   val dec_csr_legal_d             = Output(UInt(1.W))              // csr indicates legal operation
-  val dec_tlu_br0_r_pkt           = Output(new el2_br_tlu_pkt_t) // branch pkt to bp
+  val dec_tlu_br0_r_pkt           = Valid(new el2_br_tlu_pkt_t) // branch pkt to bp
   val dec_tlu_i0_kill_writeb_wb   = Output(UInt(1.W))    // I0 is flushed, don't writeback any results to arch state
   val dec_tlu_flush_lower_wb      = Output(UInt(1.W))       // commit has a flush (exception, int, mispredict at e4)
   val dec_tlu_i0_commit_cmt       = Output(UInt(1.W))        // committed an instruction
@@ -727,12 +727,12 @@ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CS
   val dec_tlu_br0_v_r = io.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.exu_i0_br_mp_r | ~io.exu_pmu_i0_br_ataken)
 
 
-  io.dec_tlu_br0_r_pkt.hist 			:= io.exu_i0_br_hist_r
-  io.dec_tlu_br0_r_pkt.br_error 		:= dec_tlu_br0_error_r
-  io.dec_tlu_br0_r_pkt.br_start_error 	:= dec_tlu_br0_start_error_r
+  io.dec_tlu_br0_r_pkt.bits.hist 			:= io.exu_i0_br_hist_r
+  io.dec_tlu_br0_r_pkt.bits.br_error 		:= dec_tlu_br0_error_r
+  io.dec_tlu_br0_r_pkt.bits.br_start_error 	:= dec_tlu_br0_start_error_r
   io.dec_tlu_br0_r_pkt.valid 			:= dec_tlu_br0_v_r
-  io.dec_tlu_br0_r_pkt.way 			:= io.exu_i0_br_way_r
-  io.dec_tlu_br0_r_pkt.middle 			:= io.exu_i0_br_middle_r
+  io.dec_tlu_br0_r_pkt.bits.way 			:= io.exu_i0_br_way_r
+  io.dec_tlu_br0_r_pkt.bits.middle 			:= io.exu_i0_br_middle_r
 
 
   ebreak_r  :=  (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK)  & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r
diff --git a/src/main/scala/el2_swerv.scala b/src/main/scala/el2_swerv.scala
index 45f381da..40df1be9 100644
--- a/src/main/scala/el2_swerv.scala
+++ b/src/main/scala/el2_swerv.scala
@@ -384,7 +384,7 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
   ifu.io.exu_mp_fghr := exu.io.exu_mp_fghr
   ifu.io.exu_mp_index := exu.io.exu_mp_index
   ifu.io.exu_mp_btag := exu.io.exu_mp_btag
-  ifu.io.dec_tlu_br0_r_pkt := dec.io.dec_tlu_br0_r_pkt
+  ifu.io.dec_tlu_br0_r_pkt <> dec.io.dec_tlu_br0_r_pkt
   ifu.io.exu_i0_br_fghr_r := exu.io.exu_i0_br_fghr_r
   ifu.io.exu_i0_br_index_r := exu.io.exu_i0_br_index_r
   ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_tlu_flush_lower_r
diff --git a/src/main/scala/ifu/el2_ifu.scala b/src/main/scala/ifu/el2_ifu.scala
index 50b79db4..89311c3d 100644
--- a/src/main/scala/ifu/el2_ifu.scala
+++ b/src/main/scala/ifu/el2_ifu.scala
@@ -122,7 +122,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
     val ifu_i0_pc4 = Output(Bool())
     val ifu_miss_state_idle = Output(Bool())
     // Aligner branch data
-    val i0_brp = Output(new el2_br_pkt_t)
+    val i0_brp = Valid(new el2_br_pkt_t)
     val ifu_i0_bp_index         = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
     val ifu_i0_bp_fghr          = Output(UInt(BHT_GHR_SIZE.W))
     val ifu_i0_bp_btag          = Output(UInt(BTB_BTAG_SIZE.W))
@@ -132,7 +132,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
     val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
     val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
     val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W))
-    val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
+    val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t))
     val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
     val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
     val dec_tlu_flush_lower_wb = Input(Bool())
@@ -328,7 +328,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
   io.ifu_i0_pc4 := aln_ctl_ch.io.ifu_i0_pc4
   io.ifu_miss_state_idle := mem_ctl_ch.io.ifu_miss_state_idle
   // Aligner branch data
-  io.i0_brp <> aln_ctl_ch.io.i0_brp
+  io.i0_brp := aln_ctl_ch.io.i0_brp
   io.ifu_i0_bp_index := aln_ctl_ch.io.ifu_i0_bp_index
   io.ifu_i0_bp_fghr := aln_ctl_ch.io.ifu_i0_bp_fghr
   io.ifu_i0_bp_btag := aln_ctl_ch.io.ifu_i0_bp_btag
diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
index c3b64aeb..ac2ea554 100644
--- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala
@@ -42,7 +42,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
     val ifu_i0_bp_btag          = Output(UInt(BTB_BTAG_SIZE.W))
     val ifu_pmu_instr_aligned   = Output(Bool())
     val ifu_i0_cinst            = Output(UInt(16.W))
-    val i0_brp                  = Output(new el2_br_pkt_t)
+    val i0_brp                  = Valid(new el2_br_pkt_t)
   })
   io.ifu_i0_valid := 0.U
   io.ifu_i0_icaf := 0.U
@@ -377,25 +377,25 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
 
   io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
 
-  io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1))
+  io.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
 
   val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
 
-  io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0),  alignway(1))
+  io.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0),  alignway(1))
 
-  io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
+  io.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
     (first2B & alignhist0(0)) | (first4B & alignhist0(1)))
 
   val i0_ends_f1 = first4B & alignfromf1
-  io.i0_brp.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
+  io.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
 
-  io.i0_brp.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
+  io.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
 
-  io.i0_brp.br_start_error  := (first4B & alignval(1) & alignbrend(0))
+  io.i0_brp.bits.br_start_error  := (first4B & alignval(1) & alignbrend(0))
 
-  io.i0_brp.bank            := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
+  io.i0_brp.bits.bank            := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
 
-  io.i0_brp.br_error := (io.i0_brp.valid &  i0_brp_pc4 &  first2B) | (io.i0_brp.valid & !i0_brp_pc4 &  first4B)
+  io.i0_brp.bits.br_error := (io.i0_brp.valid &  i0_brp_pc4 &  first2B) | (io.i0_brp.valid & !i0_brp_pc4 &  first4B)
 
   io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
 
diff --git a/src/main/scala/ifu/el2_ifu_bp_ctl.scala b/src/main/scala/ifu/el2_ifu_bp_ctl.scala
index 53a0e3fc..f9329764 100644
--- a/src/main/scala/ifu/el2_ifu_bp_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_bp_ctl.scala
@@ -13,7 +13,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
     val ifc_fetch_addr_f = Input(UInt(31.W))
     val ifc_fetch_req_f = Input(Bool())           // Fetch request generated by the IFC
     // Decode packet containing information if its a brnach or not
-    val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
+    val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t))
     val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
     val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit
     val dec_tlu_flush_lower_wb = Input(Bool())
@@ -83,12 +83,12 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
 
   // Its a commit or update packet
   val dec_tlu_br0_v_wb            = io.dec_tlu_br0_r_pkt.valid
-  val dec_tlu_br0_hist_wb         = io.dec_tlu_br0_r_pkt.hist
+  val dec_tlu_br0_hist_wb         = io.dec_tlu_br0_r_pkt.bits.hist
   val dec_tlu_br0_addr_wb         = io.exu_i0_br_index_r
-  val dec_tlu_br0_error_wb        = io.dec_tlu_br0_r_pkt.br_error
-  val dec_tlu_br0_middle_wb       = io.dec_tlu_br0_r_pkt.middle
-  val dec_tlu_br0_way_wb          = io.dec_tlu_br0_r_pkt.way
-  val dec_tlu_br0_start_error_wb  = io.dec_tlu_br0_r_pkt.br_start_error
+  val dec_tlu_br0_error_wb        = io.dec_tlu_br0_r_pkt.bits.br_error
+  val dec_tlu_br0_middle_wb       = io.dec_tlu_br0_r_pkt.bits.middle
+  val dec_tlu_br0_way_wb          = io.dec_tlu_br0_r_pkt.bits.way
+  val dec_tlu_br0_start_error_wb  = io.dec_tlu_br0_r_pkt.bits.br_start_error
   val exu_i0_br_fghr_wb           = io.exu_i0_br_fghr_r
 
   dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb
diff --git a/src/main/scala/include/el2_bundle.scala b/src/main/scala/include/el2_bundle.scala
index be9c652c..8145e097 100644
--- a/src/main/scala/include/el2_bundle.scala
+++ b/src/main/scala/include/el2_bundle.scala
@@ -49,7 +49,7 @@ class el2_rets_pkt_t extends Bundle {
 }
 
 class el2_br_pkt_t extends Bundle {
-  val valid          = UInt(1.W)
+ // val valid          = UInt(1.W)
   val toffset        = UInt(12.W)
   val hist           = UInt(2.W)
   val br_error       = UInt(1.W)
@@ -62,7 +62,7 @@ class el2_br_pkt_t extends Bundle {
 
 
 class el2_br_tlu_pkt_t extends Bundle {
-  val valid           = UInt(1.W)
+ // val valid           = UInt(1.W)
   val hist            = UInt(2.W)
   val br_error        = UInt(1.W)
   val br_start_error  = UInt(1.W)
diff --git a/target/scala-2.12/classes/dec/el2_dec.class b/target/scala-2.12/classes/dec/el2_dec.class
index 7fc422ff..090cc101 100644
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diff --git a/target/scala-2.12/classes/dec/el2_dec_IO.class b/target/scala-2.12/classes/dec/el2_dec_IO.class
index 2202dcec..9d3c06fe 100644
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diff --git a/target/scala-2.12/classes/dec/el2_dec_decode_ctl$$anon$1.class b/target/scala-2.12/classes/dec/el2_dec_decode_ctl$$anon$1.class
index 04da0330..e6335dd8 100644
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diff --git a/target/scala-2.12/classes/dec/el2_dec_decode_ctl.class b/target/scala-2.12/classes/dec/el2_dec_decode_ctl.class
index d15e3bb6..cbb391f1 100644
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diff --git a/target/scala-2.12/classes/dec/el2_dec_ib_ctl.class b/target/scala-2.12/classes/dec/el2_dec_ib_ctl.class
index 020338dc..09404dd9 100644
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diff --git a/target/scala-2.12/classes/dec/el2_dec_ib_ctl_IO.class b/target/scala-2.12/classes/dec/el2_dec_ib_ctl_IO.class
index c8481d03..a860587f 100644
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diff --git a/target/scala-2.12/classes/dec/el2_dec_tlu_ctl.class b/target/scala-2.12/classes/dec/el2_dec_tlu_ctl.class
index a14cd85b..e51eff16 100644
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diff --git a/target/scala-2.12/classes/dec/el2_dec_tlu_ctl_IO.class b/target/scala-2.12/classes/dec/el2_dec_tlu_ctl_IO.class
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diff --git a/target/scala-2.12/classes/el2_swerv.class b/target/scala-2.12/classes/el2_swerv.class
index 963e302e..d8d4d66b 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu$$anon$1.class
index 2a6c6869..51940f08 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu.class b/target/scala-2.12/classes/ifu/el2_ifu.class
index 96a766de..e121784b 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class
index 18f942c6..2e23d08a 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
index f9fc2117..d3b6a78e 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl$$anon$1.class
index 4d1cacf4..d3785206 100644
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diff --git a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
index 3ba1df9f..cd0b1c4f 100644
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diff --git a/target/scala-2.12/classes/include/el2_br_pkt_t.class b/target/scala-2.12/classes/include/el2_br_pkt_t.class
index 8e9514a3..6b08fb30 100644
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diff --git a/target/scala-2.12/classes/include/el2_br_tlu_pkt_t.class b/target/scala-2.12/classes/include/el2_br_tlu_pkt_t.class
index a13aacb9..320cb8db 100644
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