From 23995c11dac9af13b852b55ef2bd3554027ba4dc Mon Sep 17 00:00:00 2001 From: Laraib Khan <68371562+laraibkhan119@users.noreply.github.com> Date: Tue, 8 Sep 2020 18:06:30 +0500 Subject: [PATCH] Add files via upload --- src/main/scala/lsu/el2_lsu_ecc.scala | 104 +++++++++++++++++++ src/main/scala/lsu/el2_lsu_stbuf.scala | 126 +++++++++++++++++++++++ src/main/scala/lsu/el2_lsu_trigger.scala | 15 +++ 3 files changed, 245 insertions(+) create mode 100644 src/main/scala/lsu/el2_lsu_ecc.scala create mode 100644 src/main/scala/lsu/el2_lsu_stbuf.scala create mode 100644 src/main/scala/lsu/el2_lsu_trigger.scala diff --git a/src/main/scala/lsu/el2_lsu_ecc.scala b/src/main/scala/lsu/el2_lsu_ecc.scala new file mode 100644 index 00000000..3b3c5eb3 --- /dev/null +++ b/src/main/scala/lsu/el2_lsu_ecc.scala @@ -0,0 +1,104 @@ +class el2_lsu_ecc extends Module { +val io = IO(new Bundle{ + + val lsu_c2_r_clk = Input(Clock()) + val lsu_pkt_m = Input(new el2_lsu_pkt_t) + val lsu_pkt_r = Input(new el2_lsu_pkt_t) + val stbuf_data_any = Input(UInt(32.W)) + val dec_tlu_core_ecc_disable = Input(UInt(1.W)) + val lsu_dccm_rden_r = Input(UInt(1.W)) + val addr_in_dccm_r = Input(UInt(1.W)) + + val lsu_addr_r = Input(UInt(16.W)) + val end_addr_r = Input(UInt(16.W)) + val lsu_addr_m = Input(UInt(16.W)) + val end_addr_m = Input(UInt(16.W)) + + val dccm_rdata_hi_r = Input(UInt(32.W)) + val dccm_rdata_lo_r = Input(UInt(32.W)) + val dccm_rdata_hi_m = Input(UInt(32.W)) + val dccm_rdata_lo_m = Input(UInt(32.W)) + + val dccm_data_ecc_hi_r = Input(UInt(7.W)) + val dccm_data_ecc_lo_r = Input(UInt(7.W)) + val dccm_data_ecc_hi_m = Input(UInt(7.W)) + val dccm_data_ecc_lo_m = Input(UInt(7.W)) + + val ld_single_ecc_error_r = Input(UInt(1.W)) + val ld_single_ecc_error_r_ff = Input(UInt(1.W)) + val lsu_dccm_rden_m = Input(UInt(1.W)) + val addr_in_dccm_m = Input(UInt(1.W)) + + val dma_dccm_wen = Input(UInt(1.W)) + val dma_dccm_wdata_lo = Input(UInt(32.W)) + val dma_dccm_wdata_hi = Input(UInt(32.W)) + + val scan_mode = Input(UInt(1.W)) + + //Outputs + val sec_data_hi_r = Output(UInt(32.W)) + val sec_data_lo_r = Output(UInt(32.W)) + val sec_data_hi_m = Output(UInt(32.W)) + val sec_data_lo_m = Output(UInt(32.W)) + val sec_data_hi_r_ff = Output(UInt(32.W)) + val sec_data_lo_r_ff = Output(UInt(32.W)) + + val dma_dccm_wdata_ecc_hi = Output(UInt(7.W)) + val dma_dccm_wdata_ecc_lo = Output(UInt(7.W)) + val stbuf_ecc_any = Output(UInt(7.W)) + val sec_data_ecc_hi_r_ff = Output(UInt(7.W)) + val sec_data_ecc_lo_r_ff = Output(UInt(7.W)) + + val single_ecc_error_hi_r = Output(UInt(1.W)) + val single_ecc_error_lo_r = Output(UInt(1.W)) + val lsu_single_ecc_error_r = Output(UInt(1.W)) + val lsu_double_ecc_error_r = Output(UInt(1.W)) + val lsu_single_ecc_error_m = Output(UInt(1.W)) + val lsu_double_ecc_error_m = Output(UInt(1.W)) +}) + val is_ldst_r = WireInit(0.U(1.W)) + val is_ldst_hi_any = WireInit(0.U(1.W)) + val is_ldst_lo_any = WireInit(0.U(1.W)) + val dccm_wdata_hi_any = WireInit(0.U(32.W)) + val dccm_wdata_lo_any = WireInit(0.U(32.W)) + val dccm_rdata_hi_any = WireInit(0.U(32.W)) + val dccm_rdata_lo_any = WireInit(0.U(32.W)) + val sec_data_hi_any = WireInit(0.U(32.W)) + val sec_data_lo_any = WireInit(0.U(32.W)) + val dccm_wdata_ecc_hi_any = WireInit(0.U(7.W)) + val dccm_wdata_ecc_lo_any = WireInit(0.U(7.W)) + val dccm_data_ecc_hi_any = WireInit(0.U(7.W)) + val dccm_data_ecc_lo_any = WireInit(0.U(7.W)) + + val single_ecc_error_hi_any = WireInit(0.U(1.W)) + val single_ecc_error_lo_any = WireInit(0.U(1.W)) + val double_ecc_error_hi_any = WireInit(0.U(1.W)) + val double_ecc_error_lo_any = WireInit(0.U(1.W)) + val double_ecc_error_hi_m = WireInit(0.U(1.W)) + val double_ecc_error_lo_m = WireInit(0.U(1.W)) + val double_ecc_error_hi_r = WireInit(0.U(1.W)) + val double_ecc_error_lo_r = WireInit(0.U(1.W)) + val ecc_out_hi_nc = WireInit(0.U(7.W)) + val ecc_out_lo_nc = WireInit(0.U(7.W)) + + io.sec_data_hi_r :=0.U + io.sec_data_lo_r :=0.U + io.sec_data_hi_m :=0.U + io.sec_data_lo_m :=0.U + io.sec_data_hi_r_ff :=0.U + io.sec_data_lo_r_ff :=0.U + + io.dma_dccm_wdata_ecc_hi :=0.U + io.dma_dccm_wdata_ecc_lo :=0.U + io.stbuf_ecc_any :=0.U + io.sec_data_ecc_hi_r_ff :=0.U + io.sec_data_ecc_lo_r_ff :=0.U + + io.single_ecc_error_hi_r :=0.U + io.single_ecc_error_lo_r :=0.U + io.lsu_single_ecc_error_r :=0.U + io.lsu_double_ecc_error_r :=0.U + io.lsu_single_ecc_error_m :=0.U + io.lsu_double_ecc_error_m :=0.U +} + diff --git a/src/main/scala/lsu/el2_lsu_stbuf.scala b/src/main/scala/lsu/el2_lsu_stbuf.scala new file mode 100644 index 00000000..422d1154 --- /dev/null +++ b/src/main/scala/lsu/el2_lsu_stbuf.scala @@ -0,0 +1,126 @@ +class el2_lsu_stbuf extends Module { +val io = IO (new Bundle { + val lsu_c1_m_clk = Input(Clock()) + val lsu_c1_r_clk = Input(Clock()) + val lsu_stbuf_c1_clk = Input(Clock()) + val lsu_free_c2_clk = Input(Clock()) + val lsu_pkt_m = Input(new el2_lsu_pkt_t) + val lsu_pkt_r = Input(new el2_lsu_pkt_t) + val store_stbuf_reqvld_r = Input(UInt(1.W)) + val lsu_commit_r = Input(UInt(1.W)) + val dec_lsu_valid_raw_d = Input(UInt(1.W)) + val store_data_hi_r = Input(UInt(32.W)) + val store_data_lo_r = Input(UInt(32.W)) + val store_datafn_hi_r = Input(UInt(32.W)) + val store_datafn_lo_r = Input(UInt(32.W)) + val lsu_stbuf_commit_any = Input(UInt(1.W)) + val lsu_addr_d = Input(UInt(16.W)) + val lsu_addr_m = Input(UInt(32.W)) + val lsu_addr_r = Input(UInt(32.W)) + val end_addr_d = Input(UInt(16.W)) + val end_addr_m = Input(UInt(32.W)) + val end_addr_r = Input(UInt(32.W)) + + val addr_in_dccm_m = Input(UInt(1.W)) + val addr_in_dccm_r = Input(UInt(1.W)) + val lsu_cmpen_m = Input(UInt(1.W)) + val scan_mode = Input(UInt(1.W)) + + //Outputs + val stbuf_reqvld_any = Output(UInt(1.W)) + val stbuf_reqvld_flushed_any = Output(UInt(1.W)) + val stbuf_addr_any = Output(UInt(16.W)) + val stbuf_data_any = Output(UInt(32.W)) + val lsu_stbuf_full_any = Output(UInt(1.W)) + val lsu_stbuf_empty_any = Output(UInt(1.W)) + val ldst_stbuf_reqvld_r = Output(UInt(1.W)) + val stbuf_fwddata_hi_m = Output(UInt(32.W)) + val stbuf_fwddata_lo_m = Output(UInt(32.W)) + val stbuf_fwdbyteen_hi_m = Output(UInt(4.W)) + val stbuf_fwdbyteen_lo_m = Output(UInt(32.W)) +}) + val stbuf_wr_en = WireInit(0.U(1.W)) + val stbuf_vld = WireInit(0.U(1.W)) + val stbuf_dma_kill_en = WireInit(0.U(1.W)) + val stbuf_dma_kill = WireInit(0.U(1.W)) + val sel_lo = WireInit(0.U(4.W)) + val stbuf_reset = WireInit(0.U(4.W)) + val store_byteen_ext_r = WireInit(0.U(8.W)) + val store_byteen_hi_r = WireInit(0.U(4.W)) + val store_byteen_lo_r = WireInit(0.U(4.W)) + val stbuf_addr = Vec(4,UInt(16.W)) + val stbuf_byteen = Vec(4,UInt(4.W)) + val stbuf_data = Vec(4,UInt(32.W)) + val stbuf_addrin = Vec(4,UInt(16.W)) + val stbuf_datain = Vec(4,UInt(32.W)) + val stbuf_byteenin = Vec(4,UInt(4.W)) + val store_matchvec_lo_r = WireInit(0.U(4.W)) + val store_matchvec_hi_r = WireInit(0.U(4.W)) + val store_coalesce_lo_r = WireInit(0.U(1.W)) + val store_coalesce_hi_r = WireInit(0.U(1.W)) + + val WrPtrEn = WireInit(0.U(1.W)) + val RdPtrEn = WireInit(0.U(1.W)) + val WrPtr = WireInit(0.U(4.W)) + val RdPtr = WireInit(0.U(4.W)) + val NxtWrPtr = WireInit(0.U(4.W)) + val NxtRdPtr = WireInit(0.U(4.W)) + val WrPtrPlus1 = WireInit(0.U(4.W)) + val WrPtrPlus2 = WireInit(0.U(4.W)) + val RdPtrPlus1 = WireInit(0.U(4.W)) + val ldst_dual_d = WireInit(0.U(1.W)) + val ldst_dual_m = WireInit(0.U(1.W)) + val ldst_dual_r = WireInit(0.U(1.W)) + val dual_stbuf_write_r = WireInit(0.U(1.W)) + val isdccmst_m = WireInit(0.U(1.W)) + val isdccmst_r = WireInit(0.U(1.W)) + val stbuf_numvld_any = WireInit(0.U(4.W)) + val stbuf_specvld_any = WireInit(0.U(4.W)) + val stbuf_specvld_m = WireInit(0.U(2.W)) + val stbuf_specvld_r = WireInit(0.U(2.W)) + val cmpen_hi_m = WireInit(0.U(1.W)) + val cmpen_lo_m = WireInit(0.U(1.W)) + val cmpaddr_hi_m = WireInit(0.U(12.W)) + val cmpaddr_lo_m = WireInit(0.U(12.W)) + val stbuf_match_hi = WireInit(0.U(4.W)) + val stbuf_match_lo = WireInit(0.U(4.W)) + val stbuf_fwdbyteenvec_hi = Vec(4,UInt(4.W)) + val stbuf_fwdbyteenvec_lo = Vec(4,UInt(4.W)) + val stbuf_fwdata_hi_pre_m = WireInit(0.U(32.W)) + val stbuf_fwdata_lo_pre_m = WireInit(0.U(32.W)) + val stbuf_fwdbyteen_hi_pre_m = WireInit(0.U(4.W)) + val stbuf_fwdbyteen_lo_pre_m = WireInit(0.U(4.W)) + val ld_byte_rhit_lo_lo = WireInit(0.U(4.W)) + val ld_byte_rhit_hi_lo = WireInit(0.U(4.W)) + val ld_byte_rhit_lo_hi = WireInit(0.U(4.W)) + val ld_byte_rhit_hi_hi = WireInit(0.U(4.W)) + val ld_addr_rhit_lo_lo = WireInit(0.U(1.W)) + val ld_addr_rhit_hi_lo = WireInit(0.U(1.W)) + val ld_addr_rhit_lo_hi = WireInit(0.U(1.W)) + val ld_addr_rhit_hi_hi = WireInit(0.U(1.W)) + val ld_byte_hit_lo = WireInit(0.U(4.W)) + val ld_byte_rhit_lo = WireInit(0.U(4.W)) + val ld_byte_hit_hi = WireInit(0.U(4.W)) + val ld_byte_rhit_hi = WireInit(0.U(4.W)) + val ldst_byteen_hi_r = WireInit(0.U(4.W)) + val ldst_byteen_lo_r = WireInit(0.U(4.W)) + val ldst_byteen_r = WireInit(0.U(8.W)) + val ldst_byteen_ext_r = WireInit(0.U(8.W)) + val ld_fwddata_rpipe_lo = WireInit(0.U(32.W)) + val ld_fwddata_rpipe_hi = WireInit(0.U(32.W)) + + + io.stbuf_reqvld_any := 0.U + io.stbuf_reqvld_flushed_any := 0.U + io.stbuf_addr_any := 0.U + io.stbuf_data_any := 0.U + io.lsu_stbuf_full_any := 0.U + io.lsu_stbuf_empty_any := 0.U + io.ldst_stbuf_reqvld_r := 0.U + io.stbuf_fwddata_hi_m := 0.U + io.stbuf_fwddata_lo_m := 0.U + io.stbuf_fwdbyteen_hi_m := 0.U + io.stbuf_fwdbyteen_lo_m := 0.U + + } +println(chisel3.Driver.emitVerilog(new el2_lsu_stbuf)) diff --git a/src/main/scala/lsu/el2_lsu_trigger.scala b/src/main/scala/lsu/el2_lsu_trigger.scala new file mode 100644 index 00000000..c46a2185 --- /dev/null +++ b/src/main/scala/lsu/el2_lsu_trigger.scala @@ -0,0 +1,15 @@ +class el2_lsu_trigger extends Module{ + val io = IO(new Bundle{ + val trigger_pkt_any = Input(Vec (4,(new el2_trigger_pkt_t))) + val lsu_pkt_m = Input(new el2_lsu_pkt_t) + val lsu_addr_m = Input(UInt(32.W)) + val store_data_m = Input(UInt(32.W)) + val lsu_trigger_m_match = Output(UInt(4.W)) + }) + val lsu_match_data = Vec(4,UInt(32.W)) + val lsu_trigger_data_match = WireInit(0.U(4.W)) + val store_data_trigger_m = WireInit(0.U(32.W)) + + io.lsu_trigger_m_match:=0.U + +}